1 //
2 // Copyright (c) 1998, 2013, Oracle and/or its affiliates. All rights reserved.
3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 //
5 // This code is free software; you can redistribute it and/or modify it
6 // under the terms of the GNU General Public License version 2 only, as
7 // published by the Free Software Foundation.
8 //
9 // This code is distributed in the hope that it will be useful, but WITHOUT
10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 // version 2 for more details (a copy is included in the LICENSE file that
13 // accompanied this code).
14 //
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20 // or visit www.oracle.com if you need additional information or have any
21 // questions.
22 //
23 //
24
25 // SPARC Architecture Description File
26
27 //----------REGISTER DEFINITION BLOCK------------------------------------------
28 // This information is used by the matcher and the register allocator to
29 // describe individual registers and classes of registers within the target
30 // archtecture.
31 register %{
32 //----------Architecture Description Register Definitions----------------------
33 // General Registers
34 // "reg_def" name ( register save type, C convention save type,
35 // ideal register type, encoding, vm name );
36 // Register Save Types:
37 //
38 // NS = No-Save: The register allocator assumes that these registers
39 // can be used without saving upon entry to the method, &
40 // that they do not need to be saved at call sites.
41 //
42 // SOC = Save-On-Call: The register allocator assumes that these registers
43 // can be used without saving upon entry to the method,
44 // but that they must be saved at call sites.
45 //
46 // SOE = Save-On-Entry: The register allocator assumes that these registers
47 // must be saved before using them upon entry to the
48 // method, but they do not need to be saved at call
49 // sites.
50 //
51 // AS = Always-Save: The register allocator assumes that these registers
52 // must be saved before using them upon entry to the
53 // method, & that they must be saved at call sites.
54 //
55 // Ideal Register Type is used to determine how to save & restore a
56 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
57 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
58 //
59 // The encoding number is the actual bit-pattern placed into the opcodes.
60
61
62 // ----------------------------
63 // Integer/Long Registers
64 // ----------------------------
65
66 // Need to expose the hi/lo aspect of 64-bit registers
67 // This register set is used for both the 64-bit build and
68 // the 32-bit build with 1-register longs.
69
70 // Global Registers 0-7
71 reg_def R_G0H( NS, NS, Op_RegI,128, G0->as_VMReg()->next());
72 reg_def R_G0 ( NS, NS, Op_RegI, 0, G0->as_VMReg());
73 reg_def R_G1H(SOC, SOC, Op_RegI,129, G1->as_VMReg()->next());
74 reg_def R_G1 (SOC, SOC, Op_RegI, 1, G1->as_VMReg());
75 reg_def R_G2H( NS, NS, Op_RegI,130, G2->as_VMReg()->next());
76 reg_def R_G2 ( NS, NS, Op_RegI, 2, G2->as_VMReg());
77 reg_def R_G3H(SOC, SOC, Op_RegI,131, G3->as_VMReg()->next());
78 reg_def R_G3 (SOC, SOC, Op_RegI, 3, G3->as_VMReg());
79 reg_def R_G4H(SOC, SOC, Op_RegI,132, G4->as_VMReg()->next());
80 reg_def R_G4 (SOC, SOC, Op_RegI, 4, G4->as_VMReg());
81 reg_def R_G5H(SOC, SOC, Op_RegI,133, G5->as_VMReg()->next());
82 reg_def R_G5 (SOC, SOC, Op_RegI, 5, G5->as_VMReg());
83 reg_def R_G6H( NS, NS, Op_RegI,134, G6->as_VMReg()->next());
84 reg_def R_G6 ( NS, NS, Op_RegI, 6, G6->as_VMReg());
85 reg_def R_G7H( NS, NS, Op_RegI,135, G7->as_VMReg()->next());
86 reg_def R_G7 ( NS, NS, Op_RegI, 7, G7->as_VMReg());
87
88 // Output Registers 0-7
89 reg_def R_O0H(SOC, SOC, Op_RegI,136, O0->as_VMReg()->next());
90 reg_def R_O0 (SOC, SOC, Op_RegI, 8, O0->as_VMReg());
91 reg_def R_O1H(SOC, SOC, Op_RegI,137, O1->as_VMReg()->next());
92 reg_def R_O1 (SOC, SOC, Op_RegI, 9, O1->as_VMReg());
93 reg_def R_O2H(SOC, SOC, Op_RegI,138, O2->as_VMReg()->next());
94 reg_def R_O2 (SOC, SOC, Op_RegI, 10, O2->as_VMReg());
95 reg_def R_O3H(SOC, SOC, Op_RegI,139, O3->as_VMReg()->next());
96 reg_def R_O3 (SOC, SOC, Op_RegI, 11, O3->as_VMReg());
97 reg_def R_O4H(SOC, SOC, Op_RegI,140, O4->as_VMReg()->next());
98 reg_def R_O4 (SOC, SOC, Op_RegI, 12, O4->as_VMReg());
99 reg_def R_O5H(SOC, SOC, Op_RegI,141, O5->as_VMReg()->next());
100 reg_def R_O5 (SOC, SOC, Op_RegI, 13, O5->as_VMReg());
101 reg_def R_SPH( NS, NS, Op_RegI,142, SP->as_VMReg()->next());
102 reg_def R_SP ( NS, NS, Op_RegI, 14, SP->as_VMReg());
103 reg_def R_O7H(SOC, SOC, Op_RegI,143, O7->as_VMReg()->next());
104 reg_def R_O7 (SOC, SOC, Op_RegI, 15, O7->as_VMReg());
105
106 // Local Registers 0-7
107 reg_def R_L0H( NS, NS, Op_RegI,144, L0->as_VMReg()->next());
108 reg_def R_L0 ( NS, NS, Op_RegI, 16, L0->as_VMReg());
109 reg_def R_L1H( NS, NS, Op_RegI,145, L1->as_VMReg()->next());
110 reg_def R_L1 ( NS, NS, Op_RegI, 17, L1->as_VMReg());
111 reg_def R_L2H( NS, NS, Op_RegI,146, L2->as_VMReg()->next());
112 reg_def R_L2 ( NS, NS, Op_RegI, 18, L2->as_VMReg());
113 reg_def R_L3H( NS, NS, Op_RegI,147, L3->as_VMReg()->next());
114 reg_def R_L3 ( NS, NS, Op_RegI, 19, L3->as_VMReg());
115 reg_def R_L4H( NS, NS, Op_RegI,148, L4->as_VMReg()->next());
116 reg_def R_L4 ( NS, NS, Op_RegI, 20, L4->as_VMReg());
117 reg_def R_L5H( NS, NS, Op_RegI,149, L5->as_VMReg()->next());
118 reg_def R_L5 ( NS, NS, Op_RegI, 21, L5->as_VMReg());
119 reg_def R_L6H( NS, NS, Op_RegI,150, L6->as_VMReg()->next());
120 reg_def R_L6 ( NS, NS, Op_RegI, 22, L6->as_VMReg());
121 reg_def R_L7H( NS, NS, Op_RegI,151, L7->as_VMReg()->next());
122 reg_def R_L7 ( NS, NS, Op_RegI, 23, L7->as_VMReg());
123
124 // Input Registers 0-7
125 reg_def R_I0H( NS, NS, Op_RegI,152, I0->as_VMReg()->next());
126 reg_def R_I0 ( NS, NS, Op_RegI, 24, I0->as_VMReg());
127 reg_def R_I1H( NS, NS, Op_RegI,153, I1->as_VMReg()->next());
128 reg_def R_I1 ( NS, NS, Op_RegI, 25, I1->as_VMReg());
129 reg_def R_I2H( NS, NS, Op_RegI,154, I2->as_VMReg()->next());
130 reg_def R_I2 ( NS, NS, Op_RegI, 26, I2->as_VMReg());
131 reg_def R_I3H( NS, NS, Op_RegI,155, I3->as_VMReg()->next());
132 reg_def R_I3 ( NS, NS, Op_RegI, 27, I3->as_VMReg());
133 reg_def R_I4H( NS, NS, Op_RegI,156, I4->as_VMReg()->next());
134 reg_def R_I4 ( NS, NS, Op_RegI, 28, I4->as_VMReg());
135 reg_def R_I5H( NS, NS, Op_RegI,157, I5->as_VMReg()->next());
136 reg_def R_I5 ( NS, NS, Op_RegI, 29, I5->as_VMReg());
137 reg_def R_FPH( NS, NS, Op_RegI,158, FP->as_VMReg()->next());
138 reg_def R_FP ( NS, NS, Op_RegI, 30, FP->as_VMReg());
139 reg_def R_I7H( NS, NS, Op_RegI,159, I7->as_VMReg()->next());
140 reg_def R_I7 ( NS, NS, Op_RegI, 31, I7->as_VMReg());
141
142 // ----------------------------
143 // Float/Double Registers
144 // ----------------------------
145
146 // Float Registers
147 reg_def R_F0 ( SOC, SOC, Op_RegF, 0, F0->as_VMReg());
148 reg_def R_F1 ( SOC, SOC, Op_RegF, 1, F1->as_VMReg());
149 reg_def R_F2 ( SOC, SOC, Op_RegF, 2, F2->as_VMReg());
150 reg_def R_F3 ( SOC, SOC, Op_RegF, 3, F3->as_VMReg());
151 reg_def R_F4 ( SOC, SOC, Op_RegF, 4, F4->as_VMReg());
152 reg_def R_F5 ( SOC, SOC, Op_RegF, 5, F5->as_VMReg());
153 reg_def R_F6 ( SOC, SOC, Op_RegF, 6, F6->as_VMReg());
154 reg_def R_F7 ( SOC, SOC, Op_RegF, 7, F7->as_VMReg());
155 reg_def R_F8 ( SOC, SOC, Op_RegF, 8, F8->as_VMReg());
156 reg_def R_F9 ( SOC, SOC, Op_RegF, 9, F9->as_VMReg());
157 reg_def R_F10( SOC, SOC, Op_RegF, 10, F10->as_VMReg());
158 reg_def R_F11( SOC, SOC, Op_RegF, 11, F11->as_VMReg());
159 reg_def R_F12( SOC, SOC, Op_RegF, 12, F12->as_VMReg());
160 reg_def R_F13( SOC, SOC, Op_RegF, 13, F13->as_VMReg());
161 reg_def R_F14( SOC, SOC, Op_RegF, 14, F14->as_VMReg());
162 reg_def R_F15( SOC, SOC, Op_RegF, 15, F15->as_VMReg());
163 reg_def R_F16( SOC, SOC, Op_RegF, 16, F16->as_VMReg());
164 reg_def R_F17( SOC, SOC, Op_RegF, 17, F17->as_VMReg());
165 reg_def R_F18( SOC, SOC, Op_RegF, 18, F18->as_VMReg());
166 reg_def R_F19( SOC, SOC, Op_RegF, 19, F19->as_VMReg());
167 reg_def R_F20( SOC, SOC, Op_RegF, 20, F20->as_VMReg());
168 reg_def R_F21( SOC, SOC, Op_RegF, 21, F21->as_VMReg());
169 reg_def R_F22( SOC, SOC, Op_RegF, 22, F22->as_VMReg());
170 reg_def R_F23( SOC, SOC, Op_RegF, 23, F23->as_VMReg());
171 reg_def R_F24( SOC, SOC, Op_RegF, 24, F24->as_VMReg());
172 reg_def R_F25( SOC, SOC, Op_RegF, 25, F25->as_VMReg());
173 reg_def R_F26( SOC, SOC, Op_RegF, 26, F26->as_VMReg());
174 reg_def R_F27( SOC, SOC, Op_RegF, 27, F27->as_VMReg());
175 reg_def R_F28( SOC, SOC, Op_RegF, 28, F28->as_VMReg());
176 reg_def R_F29( SOC, SOC, Op_RegF, 29, F29->as_VMReg());
177 reg_def R_F30( SOC, SOC, Op_RegF, 30, F30->as_VMReg());
178 reg_def R_F31( SOC, SOC, Op_RegF, 31, F31->as_VMReg());
179
180 // Double Registers
181 // The rules of ADL require that double registers be defined in pairs.
182 // Each pair must be two 32-bit values, but not necessarily a pair of
183 // single float registers. In each pair, ADLC-assigned register numbers
184 // must be adjacent, with the lower number even. Finally, when the
185 // CPU stores such a register pair to memory, the word associated with
186 // the lower ADLC-assigned number must be stored to the lower address.
187
188 // These definitions specify the actual bit encodings of the sparc
189 // double fp register numbers. FloatRegisterImpl in register_sparc.hpp
190 // wants 0-63, so we have to convert every time we want to use fp regs
191 // with the macroassembler, using reg_to_DoubleFloatRegister_object().
192 // 255 is a flag meaning "don't go here".
193 // I believe we can't handle callee-save doubles D32 and up until
194 // the place in the sparc stack crawler that asserts on the 255 is
195 // fixed up.
196 reg_def R_D32 (SOC, SOC, Op_RegD, 1, F32->as_VMReg());
197 reg_def R_D32x(SOC, SOC, Op_RegD,255, F32->as_VMReg()->next());
198 reg_def R_D34 (SOC, SOC, Op_RegD, 3, F34->as_VMReg());
199 reg_def R_D34x(SOC, SOC, Op_RegD,255, F34->as_VMReg()->next());
200 reg_def R_D36 (SOC, SOC, Op_RegD, 5, F36->as_VMReg());
201 reg_def R_D36x(SOC, SOC, Op_RegD,255, F36->as_VMReg()->next());
202 reg_def R_D38 (SOC, SOC, Op_RegD, 7, F38->as_VMReg());
203 reg_def R_D38x(SOC, SOC, Op_RegD,255, F38->as_VMReg()->next());
204 reg_def R_D40 (SOC, SOC, Op_RegD, 9, F40->as_VMReg());
205 reg_def R_D40x(SOC, SOC, Op_RegD,255, F40->as_VMReg()->next());
206 reg_def R_D42 (SOC, SOC, Op_RegD, 11, F42->as_VMReg());
207 reg_def R_D42x(SOC, SOC, Op_RegD,255, F42->as_VMReg()->next());
208 reg_def R_D44 (SOC, SOC, Op_RegD, 13, F44->as_VMReg());
209 reg_def R_D44x(SOC, SOC, Op_RegD,255, F44->as_VMReg()->next());
210 reg_def R_D46 (SOC, SOC, Op_RegD, 15, F46->as_VMReg());
211 reg_def R_D46x(SOC, SOC, Op_RegD,255, F46->as_VMReg()->next());
212 reg_def R_D48 (SOC, SOC, Op_RegD, 17, F48->as_VMReg());
213 reg_def R_D48x(SOC, SOC, Op_RegD,255, F48->as_VMReg()->next());
214 reg_def R_D50 (SOC, SOC, Op_RegD, 19, F50->as_VMReg());
215 reg_def R_D50x(SOC, SOC, Op_RegD,255, F50->as_VMReg()->next());
216 reg_def R_D52 (SOC, SOC, Op_RegD, 21, F52->as_VMReg());
217 reg_def R_D52x(SOC, SOC, Op_RegD,255, F52->as_VMReg()->next());
218 reg_def R_D54 (SOC, SOC, Op_RegD, 23, F54->as_VMReg());
219 reg_def R_D54x(SOC, SOC, Op_RegD,255, F54->as_VMReg()->next());
220 reg_def R_D56 (SOC, SOC, Op_RegD, 25, F56->as_VMReg());
221 reg_def R_D56x(SOC, SOC, Op_RegD,255, F56->as_VMReg()->next());
222 reg_def R_D58 (SOC, SOC, Op_RegD, 27, F58->as_VMReg());
223 reg_def R_D58x(SOC, SOC, Op_RegD,255, F58->as_VMReg()->next());
224 reg_def R_D60 (SOC, SOC, Op_RegD, 29, F60->as_VMReg());
225 reg_def R_D60x(SOC, SOC, Op_RegD,255, F60->as_VMReg()->next());
226 reg_def R_D62 (SOC, SOC, Op_RegD, 31, F62->as_VMReg());
227 reg_def R_D62x(SOC, SOC, Op_RegD,255, F62->as_VMReg()->next());
228
229
230 // ----------------------------
231 // Special Registers
232 // Condition Codes Flag Registers
233 // I tried to break out ICC and XCC but it's not very pretty.
234 // Every Sparc instruction which defs/kills one also kills the other.
235 // Hence every compare instruction which defs one kind of flags ends
236 // up needing a kill of the other.
237 reg_def CCR (SOC, SOC, Op_RegFlags, 0, VMRegImpl::Bad());
238
239 reg_def FCC0(SOC, SOC, Op_RegFlags, 0, VMRegImpl::Bad());
240 reg_def FCC1(SOC, SOC, Op_RegFlags, 1, VMRegImpl::Bad());
241 reg_def FCC2(SOC, SOC, Op_RegFlags, 2, VMRegImpl::Bad());
242 reg_def FCC3(SOC, SOC, Op_RegFlags, 3, VMRegImpl::Bad());
243
244 // ----------------------------
245 // Specify the enum values for the registers. These enums are only used by the
246 // OptoReg "class". We can convert these enum values at will to VMReg when needed
247 // for visibility to the rest of the vm. The order of this enum influences the
248 // register allocator so having the freedom to set this order and not be stuck
249 // with the order that is natural for the rest of the vm is worth it.
250 alloc_class chunk0(
251 R_L0,R_L0H, R_L1,R_L1H, R_L2,R_L2H, R_L3,R_L3H, R_L4,R_L4H, R_L5,R_L5H, R_L6,R_L6H, R_L7,R_L7H,
252 R_G0,R_G0H, R_G1,R_G1H, R_G2,R_G2H, R_G3,R_G3H, R_G4,R_G4H, R_G5,R_G5H, R_G6,R_G6H, R_G7,R_G7H,
253 R_O7,R_O7H, R_SP,R_SPH, R_O0,R_O0H, R_O1,R_O1H, R_O2,R_O2H, R_O3,R_O3H, R_O4,R_O4H, R_O5,R_O5H,
254 R_I0,R_I0H, R_I1,R_I1H, R_I2,R_I2H, R_I3,R_I3H, R_I4,R_I4H, R_I5,R_I5H, R_FP,R_FPH, R_I7,R_I7H);
255
256 // Note that a register is not allocatable unless it is also mentioned
257 // in a widely-used reg_class below. Thus, R_G7 and R_G0 are outside i_reg.
258
259 alloc_class chunk1(
260 // The first registers listed here are those most likely to be used
261 // as temporaries. We move F0..F7 away from the front of the list,
262 // to reduce the likelihood of interferences with parameters and
263 // return values. Likewise, we avoid using F0/F1 for parameters,
264 // since they are used for return values.
265 // This FPU fine-tuning is worth about 1% on the SPEC geomean.
266 R_F8 ,R_F9 ,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,
267 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,
268 R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,R_F30,R_F31,
269 R_F0 ,R_F1 ,R_F2 ,R_F3 ,R_F4 ,R_F5 ,R_F6 ,R_F7 , // used for arguments and return values
270 R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x,
271 R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x,
272 R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x,
273 R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x);
274
275 alloc_class chunk2(CCR, FCC0, FCC1, FCC2, FCC3);
276
277 //----------Architecture Description Register Classes--------------------------
278 // Several register classes are automatically defined based upon information in
279 // this architecture description.
280 // 1) reg_class inline_cache_reg ( as defined in frame section )
281 // 2) reg_class interpreter_method_oop_reg ( as defined in frame section )
282 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
283 //
284
285 // G0 is not included in integer class since it has special meaning.
286 reg_class g0_reg(R_G0);
287
288 // ----------------------------
289 // Integer Register Classes
290 // ----------------------------
291 // Exclusions from i_reg:
292 // R_G0: hardwired zero
293 // R_G2: reserved by HotSpot to the TLS register (invariant within Java)
294 // R_G6: reserved by Solaris ABI to tools
295 // R_G7: reserved by Solaris ABI to libthread
296 // R_O7: Used as a temp in many encodings
297 reg_class int_reg(R_G1,R_G3,R_G4,R_G5,R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
298
299 // Class for all integer registers, except the G registers. This is used for
300 // encodings which use G registers as temps. The regular inputs to such
301 // instructions use a "notemp_" prefix, as a hack to ensure that the allocator
302 // will not put an input into a temp register.
303 reg_class notemp_int_reg(R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
304
305 reg_class g1_regI(R_G1);
306 reg_class g3_regI(R_G3);
307 reg_class g4_regI(R_G4);
308 reg_class o0_regI(R_O0);
309 reg_class o7_regI(R_O7);
310
311 // ----------------------------
312 // Pointer Register Classes
313 // ----------------------------
314 #ifdef _LP64
315 // 64-bit build means 64-bit pointers means hi/lo pairs
316 reg_class ptr_reg( R_G1H,R_G1, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5,
317 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5,
318 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7,
319 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 );
320 // Lock encodings use G3 and G4 internally
321 reg_class lock_ptr_reg( R_G1H,R_G1, R_G5H,R_G5,
322 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5,
323 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7,
324 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 );
325 // Special class for storeP instructions, which can store SP or RPC to TLS.
326 // It is also used for memory addressing, allowing direct TLS addressing.
327 reg_class sp_ptr_reg( R_G1H,R_G1, R_G2H,R_G2, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5,
328 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5, R_SPH,R_SP,
329 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7,
330 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5, R_FPH,R_FP );
331 // R_L7 is the lowest-priority callee-save (i.e., NS) register
332 // We use it to save R_G2 across calls out of Java.
333 reg_class l7_regP(R_L7H,R_L7);
334
335 // Other special pointer regs
336 reg_class g1_regP(R_G1H,R_G1);
337 reg_class g2_regP(R_G2H,R_G2);
338 reg_class g3_regP(R_G3H,R_G3);
339 reg_class g4_regP(R_G4H,R_G4);
340 reg_class g5_regP(R_G5H,R_G5);
341 reg_class i0_regP(R_I0H,R_I0);
342 reg_class o0_regP(R_O0H,R_O0);
343 reg_class o1_regP(R_O1H,R_O1);
344 reg_class o2_regP(R_O2H,R_O2);
345 reg_class o7_regP(R_O7H,R_O7);
346
347 #else // _LP64
348 // 32-bit build means 32-bit pointers means 1 register.
349 reg_class ptr_reg( R_G1, R_G3,R_G4,R_G5,
350 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,
351 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,
352 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
353 // Lock encodings use G3 and G4 internally
354 reg_class lock_ptr_reg(R_G1, R_G5,
355 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,
356 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,
357 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
358 // Special class for storeP instructions, which can store SP or RPC to TLS.
359 // It is also used for memory addressing, allowing direct TLS addressing.
360 reg_class sp_ptr_reg( R_G1,R_G2,R_G3,R_G4,R_G5,
361 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_SP,
362 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,
363 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5,R_FP);
364 // R_L7 is the lowest-priority callee-save (i.e., NS) register
365 // We use it to save R_G2 across calls out of Java.
366 reg_class l7_regP(R_L7);
367
368 // Other special pointer regs
369 reg_class g1_regP(R_G1);
370 reg_class g2_regP(R_G2);
371 reg_class g3_regP(R_G3);
372 reg_class g4_regP(R_G4);
373 reg_class g5_regP(R_G5);
374 reg_class i0_regP(R_I0);
375 reg_class o0_regP(R_O0);
376 reg_class o1_regP(R_O1);
377 reg_class o2_regP(R_O2);
378 reg_class o7_regP(R_O7);
379 #endif // _LP64
380
381
382 // ----------------------------
383 // Long Register Classes
384 // ----------------------------
385 // Longs in 1 register. Aligned adjacent hi/lo pairs.
386 // Note: O7 is never in this class; it is sometimes used as an encoding temp.
387 reg_class long_reg( R_G1H,R_G1, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5
388 ,R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5
389 #ifdef _LP64
390 // 64-bit, longs in 1 register: use all 64-bit integer registers
391 // 32-bit, longs in 1 register: cannot use I's and L's. Restrict to O's and G's.
392 ,R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7
393 ,R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5
394 #endif // _LP64
395 );
396
397 reg_class g1_regL(R_G1H,R_G1);
398 reg_class g3_regL(R_G3H,R_G3);
399 reg_class o2_regL(R_O2H,R_O2);
400 reg_class o7_regL(R_O7H,R_O7);
401
402 // ----------------------------
403 // Special Class for Condition Code Flags Register
404 reg_class int_flags(CCR);
405 reg_class float_flags(FCC0,FCC1,FCC2,FCC3);
406 reg_class float_flag0(FCC0);
407
408
409 // ----------------------------
410 // Float Point Register Classes
411 // ----------------------------
412 // Skip F30/F31, they are reserved for mem-mem copies
413 reg_class sflt_reg(R_F0,R_F1,R_F2,R_F3,R_F4,R_F5,R_F6,R_F7,R_F8,R_F9,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29);
414
415 // Paired floating point registers--they show up in the same order as the floats,
416 // but they are used with the "Op_RegD" type, and always occur in even/odd pairs.
417 reg_class dflt_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,
418 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,
419 /* Use extra V9 double registers; this AD file does not support V8 */
420 R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x,R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x,
421 R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x,R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x
422 );
423
424 // Paired floating point registers--they show up in the same order as the floats,
425 // but they are used with the "Op_RegD" type, and always occur in even/odd pairs.
426 // This class is usable for mis-aligned loads as happen in I2C adapters.
427 reg_class dflt_low_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,
428 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29);
429 %}
430
431 //----------DEFINITION BLOCK---------------------------------------------------
432 // Define name --> value mappings to inform the ADLC of an integer valued name
433 // Current support includes integer values in the range [0, 0x7FFFFFFF]
434 // Format:
435 // int_def <name> ( <int_value>, <expression>);
436 // Generated Code in ad_<arch>.hpp
437 // #define <name> (<expression>)
438 // // value == <int_value>
439 // Generated code in ad_<arch>.cpp adlc_verification()
440 // assert( <name> == <int_value>, "Expect (<expression>) to equal <int_value>");
441 //
442 definitions %{
443 // The default cost (of an ALU instruction).
444 int_def DEFAULT_COST ( 100, 100);
445 int_def HUGE_COST (1000000, 1000000);
446
447 // Memory refs are twice as expensive as run-of-the-mill.
448 int_def MEMORY_REF_COST ( 200, DEFAULT_COST * 2);
449
450 // Branches are even more expensive.
451 int_def BRANCH_COST ( 300, DEFAULT_COST * 3);
452 int_def CALL_COST ( 300, DEFAULT_COST * 3);
453 %}
454
455
456 //----------SOURCE BLOCK-------------------------------------------------------
457 // This is a block of C++ code which provides values, functions, and
458 // definitions necessary in the rest of the architecture description
459 source_hpp %{
460 // Must be visible to the DFA in dfa_sparc.cpp
461 extern bool can_branch_register( Node *bol, Node *cmp );
462
463 extern bool use_block_zeroing(Node* count);
464
465 // Macros to extract hi & lo halves from a long pair.
466 // G0 is not part of any long pair, so assert on that.
467 // Prevents accidentally using G1 instead of G0.
468 #define LONG_HI_REG(x) (x)
469 #define LONG_LO_REG(x) (x)
470
471 %}
472
473 source %{
474 #define __ _masm.
475
476 // tertiary op of a LoadP or StoreP encoding
477 #define REGP_OP true
478
479 static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding);
480 static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding);
481 static Register reg_to_register_object(int register_encoding);
482
483 // Used by the DFA in dfa_sparc.cpp.
484 // Check for being able to use a V9 branch-on-register. Requires a
485 // compare-vs-zero, equal/not-equal, of a value which was zero- or sign-
486 // extended. Doesn't work following an integer ADD, for example, because of
487 // overflow (-1 incremented yields 0 plus a carry in the high-order word). On
488 // 32-bit V9 systems, interrupts currently blow away the high-order 32 bits and
489 // replace them with zero, which could become sign-extension in a different OS
490 // release. There's no obvious reason why an interrupt will ever fill these
491 // bits with non-zero junk (the registers are reloaded with standard LD
492 // instructions which either zero-fill or sign-fill).
493 bool can_branch_register( Node *bol, Node *cmp ) {
494 if( !BranchOnRegister ) return false;
495 #ifdef _LP64
496 if( cmp->Opcode() == Op_CmpP )
497 return true; // No problems with pointer compares
498 #endif
499 if( cmp->Opcode() == Op_CmpL )
500 return true; // No problems with long compares
501
502 if( !SparcV9RegsHiBitsZero ) return false;
503 if( bol->as_Bool()->_test._test != BoolTest::ne &&
504 bol->as_Bool()->_test._test != BoolTest::eq )
505 return false;
506
507 // Check for comparing against a 'safe' value. Any operation which
508 // clears out the high word is safe. Thus, loads and certain shifts
509 // are safe, as are non-negative constants. Any operation which
510 // preserves zero bits in the high word is safe as long as each of its
511 // inputs are safe. Thus, phis and bitwise booleans are safe if their
512 // inputs are safe. At present, the only important case to recognize
513 // seems to be loads. Constants should fold away, and shifts &
514 // logicals can use the 'cc' forms.
515 Node *x = cmp->in(1);
516 if( x->is_Load() ) return true;
517 if( x->is_Phi() ) {
518 for( uint i = 1; i < x->req(); i++ )
519 if( !x->in(i)->is_Load() )
520 return false;
521 return true;
522 }
523 return false;
524 }
525
526 bool use_block_zeroing(Node* count) {
527 // Use BIS for zeroing if count is not constant
528 // or it is >= BlockZeroingLowLimit.
529 return UseBlockZeroing && (count->find_intptr_t_con(BlockZeroingLowLimit) >= BlockZeroingLowLimit);
530 }
531
532 // ****************************************************************************
533
534 // REQUIRED FUNCTIONALITY
535
536 // !!!!! Special hack to get all type of calls to specify the byte offset
537 // from the start of the call to the point where the return address
538 // will point.
539 // The "return address" is the address of the call instruction, plus 8.
540
541 int MachCallStaticJavaNode::ret_addr_offset() {
542 int offset = NativeCall::instruction_size; // call; delay slot
543 if (_method_handle_invoke)
544 offset += 4; // restore SP
545 return offset;
546 }
547
548 int MachCallDynamicJavaNode::ret_addr_offset() {
549 int vtable_index = this->_vtable_index;
550 if (vtable_index < 0) {
551 // must be invalid_vtable_index, not nonvirtual_vtable_index
552 assert(vtable_index == Method::invalid_vtable_index, "correct sentinel value");
553 return (NativeMovConstReg::instruction_size +
554 NativeCall::instruction_size); // sethi; setlo; call; delay slot
555 } else {
556 assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
557 int entry_offset = InstanceKlass::vtable_start_offset() + vtable_index*vtableEntry::size();
558 int v_off = entry_offset*wordSize + vtableEntry::method_offset_in_bytes();
559 int klass_load_size;
560 if (UseCompressedKlassPointers) {
561 assert(Universe::heap() != NULL, "java heap should be initialized");
562 if (Universe::narrow_klass_base() == NULL)
563 klass_load_size = 2*BytesPerInstWord; // see MacroAssembler::load_klass()
564 else
565 klass_load_size = 3*BytesPerInstWord;
566 } else {
567 klass_load_size = 1*BytesPerInstWord;
568 }
569 if (Assembler::is_simm13(v_off)) {
570 return klass_load_size +
571 (2*BytesPerInstWord + // ld_ptr, ld_ptr
572 NativeCall::instruction_size); // call; delay slot
573 } else {
574 return klass_load_size +
575 (4*BytesPerInstWord + // set_hi, set, ld_ptr, ld_ptr
576 NativeCall::instruction_size); // call; delay slot
577 }
578 }
579 }
580
581 int MachCallRuntimeNode::ret_addr_offset() {
582 #ifdef _LP64
583 if (MacroAssembler::is_far_target(entry_point())) {
584 return NativeFarCall::instruction_size;
585 } else {
586 return NativeCall::instruction_size;
587 }
588 #else
589 return NativeCall::instruction_size; // call; delay slot
590 #endif
591 }
592
593 // Indicate if the safepoint node needs the polling page as an input.
594 // Since Sparc does not have absolute addressing, it does.
595 bool SafePointNode::needs_polling_address_input() {
596 return true;
597 }
598
599 // emit an interrupt that is caught by the debugger (for debugging compiler)
600 void emit_break(CodeBuffer &cbuf) {
601 MacroAssembler _masm(&cbuf);
602 __ breakpoint_trap();
603 }
604
605 #ifndef PRODUCT
606 void MachBreakpointNode::format( PhaseRegAlloc *, outputStream *st ) const {
607 st->print("TA");
608 }
609 #endif
610
611 void MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
612 emit_break(cbuf);
613 }
614
615 uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const {
616 return MachNode::size(ra_);
617 }
618
619 // Traceable jump
620 void emit_jmpl(CodeBuffer &cbuf, int jump_target) {
621 MacroAssembler _masm(&cbuf);
622 Register rdest = reg_to_register_object(jump_target);
623 __ JMP(rdest, 0);
624 __ delayed()->nop();
625 }
626
627 // Traceable jump and set exception pc
628 void emit_jmpl_set_exception_pc(CodeBuffer &cbuf, int jump_target) {
629 MacroAssembler _masm(&cbuf);
630 Register rdest = reg_to_register_object(jump_target);
631 __ JMP(rdest, 0);
632 __ delayed()->add(O7, frame::pc_return_offset, Oissuing_pc );
633 }
634
635 void emit_nop(CodeBuffer &cbuf) {
636 MacroAssembler _masm(&cbuf);
637 __ nop();
638 }
639
640 void emit_illtrap(CodeBuffer &cbuf) {
641 MacroAssembler _masm(&cbuf);
642 __ illtrap(0);
643 }
644
645
646 intptr_t get_offset_from_base(const MachNode* n, const TypePtr* atype, int disp32) {
647 assert(n->rule() != loadUB_rule, "");
648
649 intptr_t offset = 0;
650 const TypePtr *adr_type = TYPE_PTR_SENTINAL; // Check for base==RegI, disp==immP
651 const Node* addr = n->get_base_and_disp(offset, adr_type);
652 assert(adr_type == (const TypePtr*)-1, "VerifyOops: no support for sparc operands with base==RegI, disp==immP");
653 assert(addr != NULL && addr != (Node*)-1, "invalid addr");
654 assert(addr->bottom_type()->isa_oopptr() == atype, "");
655 atype = atype->add_offset(offset);
656 assert(disp32 == offset, "wrong disp32");
657 return atype->_offset;
658 }
659
660
661 intptr_t get_offset_from_base_2(const MachNode* n, const TypePtr* atype, int disp32) {
662 assert(n->rule() != loadUB_rule, "");
663
664 intptr_t offset = 0;
665 Node* addr = n->in(2);
666 assert(addr->bottom_type()->isa_oopptr() == atype, "");
667 if (addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP) {
668 Node* a = addr->in(2/*AddPNode::Address*/);
669 Node* o = addr->in(3/*AddPNode::Offset*/);
670 offset = o->is_Con() ? o->bottom_type()->is_intptr_t()->get_con() : Type::OffsetBot;
671 atype = a->bottom_type()->is_ptr()->add_offset(offset);
672 assert(atype->isa_oop_ptr(), "still an oop");
673 }
674 offset = atype->is_ptr()->_offset;
675 if (offset != Type::OffsetBot) offset += disp32;
676 return offset;
677 }
678
679 static inline jdouble replicate_immI(int con, int count, int width) {
680 // Load a constant replicated "count" times with width "width"
681 assert(count*width == 8 && width <= 4, "sanity");
682 int bit_width = width * 8;
683 jlong val = con;
684 val &= (((jlong) 1) << bit_width) - 1; // mask off sign bits
685 for (int i = 0; i < count - 1; i++) {
686 val |= (val << bit_width);
687 }
688 jdouble dval = *((jdouble*) &val); // coerce to double type
689 return dval;
690 }
691
692 static inline jdouble replicate_immF(float con) {
693 // Replicate float con 2 times and pack into vector.
694 int val = *((int*)&con);
695 jlong lval = val;
696 lval = (lval << 32) | (lval & 0xFFFFFFFFl);
697 jdouble dval = *((jdouble*) &lval); // coerce to double type
698 return dval;
699 }
700
701 // Standard Sparc opcode form2 field breakdown
702 static inline void emit2_19(CodeBuffer &cbuf, int f30, int f29, int f25, int f22, int f20, int f19, int f0 ) {
703 f0 &= (1<<19)-1; // Mask displacement to 19 bits
704 int op = (f30 << 30) |
705 (f29 << 29) |
706 (f25 << 25) |
707 (f22 << 22) |
708 (f20 << 20) |
709 (f19 << 19) |
710 (f0 << 0);
711 cbuf.insts()->emit_int32(op);
712 }
713
714 // Standard Sparc opcode form2 field breakdown
715 static inline void emit2_22(CodeBuffer &cbuf, int f30, int f25, int f22, int f0 ) {
716 f0 >>= 10; // Drop 10 bits
717 f0 &= (1<<22)-1; // Mask displacement to 22 bits
718 int op = (f30 << 30) |
719 (f25 << 25) |
720 (f22 << 22) |
721 (f0 << 0);
722 cbuf.insts()->emit_int32(op);
723 }
724
725 // Standard Sparc opcode form3 field breakdown
726 static inline void emit3(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int f5, int f0 ) {
727 int op = (f30 << 30) |
728 (f25 << 25) |
729 (f19 << 19) |
730 (f14 << 14) |
731 (f5 << 5) |
732 (f0 << 0);
733 cbuf.insts()->emit_int32(op);
734 }
735
736 // Standard Sparc opcode form3 field breakdown
737 static inline void emit3_simm13(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm13 ) {
738 simm13 &= (1<<13)-1; // Mask to 13 bits
739 int op = (f30 << 30) |
740 (f25 << 25) |
741 (f19 << 19) |
742 (f14 << 14) |
743 (1 << 13) | // bit to indicate immediate-mode
744 (simm13<<0);
745 cbuf.insts()->emit_int32(op);
746 }
747
748 static inline void emit3_simm10(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm10 ) {
749 simm10 &= (1<<10)-1; // Mask to 10 bits
750 emit3_simm13(cbuf,f30,f25,f19,f14,simm10);
751 }
752
753 #ifdef ASSERT
754 // Helper function for VerifyOops in emit_form3_mem_reg
755 void verify_oops_warning(const MachNode *n, int ideal_op, int mem_op) {
756 warning("VerifyOops encountered unexpected instruction:");
757 n->dump(2);
758 warning("Instruction has ideal_Opcode==Op_%s and op_ld==Op_%s \n", NodeClassNames[ideal_op], NodeClassNames[mem_op]);
759 }
760 #endif
761
762
763 void emit_form3_mem_reg(CodeBuffer &cbuf, const MachNode* n, int primary, int tertiary,
764 int src1_enc, int disp32, int src2_enc, int dst_enc) {
765
766 #ifdef ASSERT
767 // The following code implements the +VerifyOops feature.
768 // It verifies oop values which are loaded into or stored out of
769 // the current method activation. +VerifyOops complements techniques
770 // like ScavengeALot, because it eagerly inspects oops in transit,
771 // as they enter or leave the stack, as opposed to ScavengeALot,
772 // which inspects oops "at rest", in the stack or heap, at safepoints.
773 // For this reason, +VerifyOops can sometimes detect bugs very close
774 // to their point of creation. It can also serve as a cross-check
775 // on the validity of oop maps, when used toegether with ScavengeALot.
776
777 // It would be good to verify oops at other points, especially
778 // when an oop is used as a base pointer for a load or store.
779 // This is presently difficult, because it is hard to know when
780 // a base address is biased or not. (If we had such information,
781 // it would be easy and useful to make a two-argument version of
782 // verify_oop which unbiases the base, and performs verification.)
783
784 assert((uint)tertiary == 0xFFFFFFFF || tertiary == REGP_OP, "valid tertiary");
785 bool is_verified_oop_base = false;
786 bool is_verified_oop_load = false;
787 bool is_verified_oop_store = false;
788 int tmp_enc = -1;
789 if (VerifyOops && src1_enc != R_SP_enc) {
790 // classify the op, mainly for an assert check
791 int st_op = 0, ld_op = 0;
792 switch (primary) {
793 case Assembler::stb_op3: st_op = Op_StoreB; break;
794 case Assembler::sth_op3: st_op = Op_StoreC; break;
795 case Assembler::stx_op3: // may become StoreP or stay StoreI or StoreD0
796 case Assembler::stw_op3: st_op = Op_StoreI; break;
797 case Assembler::std_op3: st_op = Op_StoreL; break;
798 case Assembler::stf_op3: st_op = Op_StoreF; break;
799 case Assembler::stdf_op3: st_op = Op_StoreD; break;
800
801 case Assembler::ldsb_op3: ld_op = Op_LoadB; break;
802 case Assembler::ldub_op3: ld_op = Op_LoadUB; break;
803 case Assembler::lduh_op3: ld_op = Op_LoadUS; break;
804 case Assembler::ldsh_op3: ld_op = Op_LoadS; break;
805 case Assembler::ldx_op3: // may become LoadP or stay LoadI
806 case Assembler::ldsw_op3: // may become LoadP or stay LoadI
807 case Assembler::lduw_op3: ld_op = Op_LoadI; break;
808 case Assembler::ldd_op3: ld_op = Op_LoadL; break;
809 case Assembler::ldf_op3: ld_op = Op_LoadF; break;
810 case Assembler::lddf_op3: ld_op = Op_LoadD; break;
811 case Assembler::prefetch_op3: ld_op = Op_LoadI; break;
812
813 default: ShouldNotReachHere();
814 }
815 if (tertiary == REGP_OP) {
816 if (st_op == Op_StoreI) st_op = Op_StoreP;
817 else if (ld_op == Op_LoadI) ld_op = Op_LoadP;
818 else ShouldNotReachHere();
819 if (st_op) {
820 // a store
821 // inputs are (0:control, 1:memory, 2:address, 3:value)
822 Node* n2 = n->in(3);
823 if (n2 != NULL) {
824 const Type* t = n2->bottom_type();
825 is_verified_oop_store = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false;
826 }
827 } else {
828 // a load
829 const Type* t = n->bottom_type();
830 is_verified_oop_load = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false;
831 }
832 }
833
834 if (ld_op) {
835 // a Load
836 // inputs are (0:control, 1:memory, 2:address)
837 if (!(n->ideal_Opcode()==ld_op) && // Following are special cases
838 !(n->ideal_Opcode()==Op_LoadPLocked && ld_op==Op_LoadP) &&
839 !(n->ideal_Opcode()==Op_LoadI && ld_op==Op_LoadF) &&
840 !(n->ideal_Opcode()==Op_LoadF && ld_op==Op_LoadI) &&
841 !(n->ideal_Opcode()==Op_LoadRange && ld_op==Op_LoadI) &&
842 !(n->ideal_Opcode()==Op_LoadKlass && ld_op==Op_LoadP) &&
843 !(n->ideal_Opcode()==Op_LoadL && ld_op==Op_LoadI) &&
844 !(n->ideal_Opcode()==Op_LoadL_unaligned && ld_op==Op_LoadI) &&
845 !(n->ideal_Opcode()==Op_LoadD_unaligned && ld_op==Op_LoadF) &&
846 !(n->ideal_Opcode()==Op_ConvI2F && ld_op==Op_LoadF) &&
847 !(n->ideal_Opcode()==Op_ConvI2D && ld_op==Op_LoadF) &&
848 !(n->ideal_Opcode()==Op_PrefetchRead && ld_op==Op_LoadI) &&
849 !(n->ideal_Opcode()==Op_PrefetchWrite && ld_op==Op_LoadI) &&
850 !(n->ideal_Opcode()==Op_PrefetchAllocation && ld_op==Op_LoadI) &&
851 !(n->ideal_Opcode()==Op_LoadVector && ld_op==Op_LoadD) &&
852 !(n->rule() == loadUB_rule)) {
853 verify_oops_warning(n, n->ideal_Opcode(), ld_op);
854 }
855 } else if (st_op) {
856 // a Store
857 // inputs are (0:control, 1:memory, 2:address, 3:value)
858 if (!(n->ideal_Opcode()==st_op) && // Following are special cases
859 !(n->ideal_Opcode()==Op_StoreCM && st_op==Op_StoreB) &&
860 !(n->ideal_Opcode()==Op_StoreI && st_op==Op_StoreF) &&
861 !(n->ideal_Opcode()==Op_StoreF && st_op==Op_StoreI) &&
862 !(n->ideal_Opcode()==Op_StoreL && st_op==Op_StoreI) &&
863 !(n->ideal_Opcode()==Op_StoreVector && st_op==Op_StoreD) &&
864 !(n->ideal_Opcode()==Op_StoreD && st_op==Op_StoreI && n->rule() == storeD0_rule)) {
865 verify_oops_warning(n, n->ideal_Opcode(), st_op);
866 }
867 }
868
869 if (src2_enc == R_G0_enc && n->rule() != loadUB_rule && n->ideal_Opcode() != Op_StoreCM ) {
870 Node* addr = n->in(2);
871 if (!(addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP)) {
872 const TypeOopPtr* atype = addr->bottom_type()->isa_instptr(); // %%% oopptr?
873 if (atype != NULL) {
874 intptr_t offset = get_offset_from_base(n, atype, disp32);
875 intptr_t offset_2 = get_offset_from_base_2(n, atype, disp32);
876 if (offset != offset_2) {
877 get_offset_from_base(n, atype, disp32);
878 get_offset_from_base_2(n, atype, disp32);
879 }
880 assert(offset == offset_2, "different offsets");
881 if (offset == disp32) {
882 // we now know that src1 is a true oop pointer
883 is_verified_oop_base = true;
884 if (ld_op && src1_enc == dst_enc && ld_op != Op_LoadF && ld_op != Op_LoadD) {
885 if( primary == Assembler::ldd_op3 ) {
886 is_verified_oop_base = false; // Cannot 'ldd' into O7
887 } else {
888 tmp_enc = dst_enc;
889 dst_enc = R_O7_enc; // Load into O7; preserve source oop
890 assert(src1_enc != dst_enc, "");
891 }
892 }
893 }
894 if (st_op && (( offset == oopDesc::klass_offset_in_bytes())
895 || offset == oopDesc::mark_offset_in_bytes())) {
896 // loading the mark should not be allowed either, but
897 // we don't check this since it conflicts with InlineObjectHash
898 // usage of LoadINode to get the mark. We could keep the
899 // check if we create a new LoadMarkNode
900 // but do not verify the object before its header is initialized
901 ShouldNotReachHere();
902 }
903 }
904 }
905 }
906 }
907 #endif
908
909 uint instr;
910 instr = (Assembler::ldst_op << 30)
911 | (dst_enc << 25)
912 | (primary << 19)
913 | (src1_enc << 14);
914
915 uint index = src2_enc;
916 int disp = disp32;
917
918 if (src1_enc == R_SP_enc || src1_enc == R_FP_enc)
919 disp += STACK_BIAS;
920
921 // We should have a compiler bailout here rather than a guarantee.
922 // Better yet would be some mechanism to handle variable-size matches correctly.
923 guarantee(Assembler::is_simm13(disp), "Do not match large constant offsets" );
924
925 if( disp == 0 ) {
926 // use reg-reg form
927 // bit 13 is already zero
928 instr |= index;
929 } else {
930 // use reg-imm form
931 instr |= 0x00002000; // set bit 13 to one
932 instr |= disp & 0x1FFF;
933 }
934
935 cbuf.insts()->emit_int32(instr);
936
937 #ifdef ASSERT
938 {
939 MacroAssembler _masm(&cbuf);
940 if (is_verified_oop_base) {
941 __ verify_oop(reg_to_register_object(src1_enc));
942 }
943 if (is_verified_oop_store) {
944 __ verify_oop(reg_to_register_object(dst_enc));
945 }
946 if (tmp_enc != -1) {
947 __ mov(O7, reg_to_register_object(tmp_enc));
948 }
949 if (is_verified_oop_load) {
950 __ verify_oop(reg_to_register_object(dst_enc));
951 }
952 }
953 #endif
954 }
955
956 void emit_call_reloc(CodeBuffer &cbuf, intptr_t entry_point, relocInfo::relocType rtype, bool preserve_g2 = false) {
957 // The method which records debug information at every safepoint
958 // expects the call to be the first instruction in the snippet as
959 // it creates a PcDesc structure which tracks the offset of a call
960 // from the start of the codeBlob. This offset is computed as
961 // code_end() - code_begin() of the code which has been emitted
962 // so far.
963 // In this particular case we have skirted around the problem by
964 // putting the "mov" instruction in the delay slot but the problem
965 // may bite us again at some other point and a cleaner/generic
966 // solution using relocations would be needed.
967 MacroAssembler _masm(&cbuf);
968 __ set_inst_mark();
969
970 // We flush the current window just so that there is a valid stack copy
971 // the fact that the current window becomes active again instantly is
972 // not a problem there is nothing live in it.
973
974 #ifdef ASSERT
975 int startpos = __ offset();
976 #endif /* ASSERT */
977
978 __ call((address)entry_point, rtype);
979
980 if (preserve_g2) __ delayed()->mov(G2, L7);
981 else __ delayed()->nop();
982
983 if (preserve_g2) __ mov(L7, G2);
984
985 #ifdef ASSERT
986 if (preserve_g2 && (VerifyCompiledCode || VerifyOops)) {
987 #ifdef _LP64
988 // Trash argument dump slots.
989 __ set(0xb0b8ac0db0b8ac0d, G1);
990 __ mov(G1, G5);
991 __ stx(G1, SP, STACK_BIAS + 0x80);
992 __ stx(G1, SP, STACK_BIAS + 0x88);
993 __ stx(G1, SP, STACK_BIAS + 0x90);
994 __ stx(G1, SP, STACK_BIAS + 0x98);
995 __ stx(G1, SP, STACK_BIAS + 0xA0);
996 __ stx(G1, SP, STACK_BIAS + 0xA8);
997 #else // _LP64
998 // this is also a native call, so smash the first 7 stack locations,
999 // and the various registers
1000
1001 // Note: [SP+0x40] is sp[callee_aggregate_return_pointer_sp_offset],
1002 // while [SP+0x44..0x58] are the argument dump slots.
1003 __ set((intptr_t)0xbaadf00d, G1);
1004 __ mov(G1, G5);
1005 __ sllx(G1, 32, G1);
1006 __ or3(G1, G5, G1);
1007 __ mov(G1, G5);
1008 __ stx(G1, SP, 0x40);
1009 __ stx(G1, SP, 0x48);
1010 __ stx(G1, SP, 0x50);
1011 __ stw(G1, SP, 0x58); // Do not trash [SP+0x5C] which is a usable spill slot
1012 #endif // _LP64
1013 }
1014 #endif /*ASSERT*/
1015 }
1016
1017 //=============================================================================
1018 // REQUIRED FUNCTIONALITY for encoding
1019 void emit_lo(CodeBuffer &cbuf, int val) { }
1020 void emit_hi(CodeBuffer &cbuf, int val) { }
1021
1022
1023 //=============================================================================
1024 const RegMask& MachConstantBaseNode::_out_RegMask = PTR_REG_mask();
1025
1026 int Compile::ConstantTable::calculate_table_base_offset() const {
1027 if (UseRDPCForConstantTableBase) {
1028 // The table base offset might be less but then it fits into
1029 // simm13 anyway and we are good (cf. MachConstantBaseNode::emit).
1030 return Assembler::min_simm13();
1031 } else {
1032 int offset = -(size() / 2);
1033 if (!Assembler::is_simm13(offset)) {
1034 offset = Assembler::min_simm13();
1035 }
1036 return offset;
1037 }
1038 }
1039
1040 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
1041 Compile* C = ra_->C;
1042 Compile::ConstantTable& constant_table = C->constant_table();
1043 MacroAssembler _masm(&cbuf);
1044
1045 Register r = as_Register(ra_->get_encode(this));
1046 CodeSection* consts_section = __ code()->consts();
1047 int consts_size = consts_section->align_at_start(consts_section->size());
1048 assert(constant_table.size() == consts_size, err_msg("must be: %d == %d", constant_table.size(), consts_size));
1049
1050 if (UseRDPCForConstantTableBase) {
1051 // For the following RDPC logic to work correctly the consts
1052 // section must be allocated right before the insts section. This
1053 // assert checks for that. The layout and the SECT_* constants
1054 // are defined in src/share/vm/asm/codeBuffer.hpp.
1055 assert(CodeBuffer::SECT_CONSTS + 1 == CodeBuffer::SECT_INSTS, "must be");
1056 int insts_offset = __ offset();
1057
1058 // Layout:
1059 //
1060 // |----------- consts section ------------|----------- insts section -----------...
1061 // |------ constant table -----|- padding -|------------------x----
1062 // \ current PC (RDPC instruction)
1063 // |<------------- consts_size ----------->|<- insts_offset ->|
1064 // \ table base
1065 // The table base offset is later added to the load displacement
1066 // so it has to be negative.
1067 int table_base_offset = -(consts_size + insts_offset);
1068 int disp;
1069
1070 // If the displacement from the current PC to the constant table
1071 // base fits into simm13 we set the constant table base to the
1072 // current PC.
1073 if (Assembler::is_simm13(table_base_offset)) {
1074 constant_table.set_table_base_offset(table_base_offset);
1075 disp = 0;
1076 } else {
1077 // Otherwise we set the constant table base offset to the
1078 // maximum negative displacement of load instructions to keep
1079 // the disp as small as possible:
1080 //
1081 // |<------------- consts_size ----------->|<- insts_offset ->|
1082 // |<--------- min_simm13 --------->|<-------- disp --------->|
1083 // \ table base
1084 table_base_offset = Assembler::min_simm13();
1085 constant_table.set_table_base_offset(table_base_offset);
1086 disp = (consts_size + insts_offset) + table_base_offset;
1087 }
1088
1089 __ rdpc(r);
1090
1091 if (disp != 0) {
1092 assert(r != O7, "need temporary");
1093 __ sub(r, __ ensure_simm13_or_reg(disp, O7), r);
1094 }
1095 }
1096 else {
1097 // Materialize the constant table base.
1098 address baseaddr = consts_section->start() + -(constant_table.table_base_offset());
1099 RelocationHolder rspec = internal_word_Relocation::spec(baseaddr);
1100 AddressLiteral base(baseaddr, rspec);
1101 __ set(base, r);
1102 }
1103 }
1104
1105 uint MachConstantBaseNode::size(PhaseRegAlloc*) const {
1106 if (UseRDPCForConstantTableBase) {
1107 // This is really the worst case but generally it's only 1 instruction.
1108 return (1 /*rdpc*/ + 1 /*sub*/ + MacroAssembler::worst_case_insts_for_set()) * BytesPerInstWord;
1109 } else {
1110 return MacroAssembler::worst_case_insts_for_set() * BytesPerInstWord;
1111 }
1112 }
1113
1114 #ifndef PRODUCT
1115 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
1116 char reg[128];
1117 ra_->dump_register(this, reg);
1118 if (UseRDPCForConstantTableBase) {
1119 st->print("RDPC %s\t! constant table base", reg);
1120 } else {
1121 st->print("SET &constanttable,%s\t! constant table base", reg);
1122 }
1123 }
1124 #endif
1125
1126
1127 //=============================================================================
1128
1129 #ifndef PRODUCT
1130 void MachPrologNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1131 Compile* C = ra_->C;
1132
1133 for (int i = 0; i < OptoPrologueNops; i++) {
1134 st->print_cr("NOP"); st->print("\t");
1135 }
1136
1137 if( VerifyThread ) {
1138 st->print_cr("Verify_Thread"); st->print("\t");
1139 }
1140
1141 size_t framesize = C->frame_slots() << LogBytesPerInt;
1142
1143 // Calls to C2R adapters often do not accept exceptional returns.
1144 // We require that their callers must bang for them. But be careful, because
1145 // some VM calls (such as call site linkage) can use several kilobytes of
1146 // stack. But the stack safety zone should account for that.
1147 // See bugs 4446381, 4468289, 4497237.
1148 if (C->need_stack_bang(framesize)) {
1149 st->print_cr("! stack bang"); st->print("\t");
1150 }
1151
1152 if (Assembler::is_simm13(-framesize)) {
1153 st->print ("SAVE R_SP,-%d,R_SP",framesize);
1154 } else {
1155 st->print_cr("SETHI R_SP,hi%%(-%d),R_G3",framesize); st->print("\t");
1156 st->print_cr("ADD R_G3,lo%%(-%d),R_G3",framesize); st->print("\t");
1157 st->print ("SAVE R_SP,R_G3,R_SP");
1158 }
1159
1160 }
1161 #endif
1162
1163 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1164 Compile* C = ra_->C;
1165 MacroAssembler _masm(&cbuf);
1166
1167 for (int i = 0; i < OptoPrologueNops; i++) {
1168 __ nop();
1169 }
1170
1171 __ verify_thread();
1172
1173 size_t framesize = C->frame_slots() << LogBytesPerInt;
1174 assert(framesize >= 16*wordSize, "must have room for reg. save area");
1175 assert(framesize%(2*wordSize) == 0, "must preserve 2*wordSize alignment");
1176
1177 // Calls to C2R adapters often do not accept exceptional returns.
1178 // We require that their callers must bang for them. But be careful, because
1179 // some VM calls (such as call site linkage) can use several kilobytes of
1180 // stack. But the stack safety zone should account for that.
1181 // See bugs 4446381, 4468289, 4497237.
1182 if (C->need_stack_bang(framesize)) {
1183 __ generate_stack_overflow_check(framesize);
1184 }
1185
1186 if (Assembler::is_simm13(-framesize)) {
1187 __ save(SP, -framesize, SP);
1188 } else {
1189 __ sethi(-framesize & ~0x3ff, G3);
1190 __ add(G3, -framesize & 0x3ff, G3);
1191 __ save(SP, G3, SP);
1192 }
1193 C->set_frame_complete( __ offset() );
1194
1195 if (!UseRDPCForConstantTableBase && C->has_mach_constant_base_node()) {
1196 // NOTE: We set the table base offset here because users might be
1197 // emitted before MachConstantBaseNode.
1198 Compile::ConstantTable& constant_table = C->constant_table();
1199 constant_table.set_table_base_offset(constant_table.calculate_table_base_offset());
1200 }
1201 }
1202
1203 uint MachPrologNode::size(PhaseRegAlloc *ra_) const {
1204 return MachNode::size(ra_);
1205 }
1206
1207 int MachPrologNode::reloc() const {
1208 return 10; // a large enough number
1209 }
1210
1211 //=============================================================================
1212 #ifndef PRODUCT
1213 void MachEpilogNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1214 Compile* C = ra_->C;
1215
1216 if( do_polling() && ra_->C->is_method_compilation() ) {
1217 st->print("SETHI #PollAddr,L0\t! Load Polling address\n\t");
1218 #ifdef _LP64
1219 st->print("LDX [L0],G0\t!Poll for Safepointing\n\t");
1220 #else
1221 st->print("LDUW [L0],G0\t!Poll for Safepointing\n\t");
1222 #endif
1223 }
1224
1225 if( do_polling() )
1226 st->print("RET\n\t");
1227
1228 st->print("RESTORE");
1229 }
1230 #endif
1231
1232 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1233 MacroAssembler _masm(&cbuf);
1234 Compile* C = ra_->C;
1235
1236 __ verify_thread();
1237
1238 // If this does safepoint polling, then do it here
1239 if( do_polling() && ra_->C->is_method_compilation() ) {
1240 AddressLiteral polling_page(os::get_polling_page());
1241 __ sethi(polling_page, L0);
1242 __ relocate(relocInfo::poll_return_type);
1243 __ ld_ptr( L0, 0, G0 );
1244 }
1245
1246 // If this is a return, then stuff the restore in the delay slot
1247 if( do_polling() ) {
1248 __ ret();
1249 __ delayed()->restore();
1250 } else {
1251 __ restore();
1252 }
1253 }
1254
1255 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const {
1256 return MachNode::size(ra_);
1257 }
1258
1259 int MachEpilogNode::reloc() const {
1260 return 16; // a large enough number
1261 }
1262
1263 const Pipeline * MachEpilogNode::pipeline() const {
1264 return MachNode::pipeline_class();
1265 }
1266
1267 int MachEpilogNode::safepoint_offset() const {
1268 assert( do_polling(), "no return for this epilog node");
1269 return MacroAssembler::insts_for_sethi(os::get_polling_page()) * BytesPerInstWord;
1270 }
1271
1272 //=============================================================================
1273
1274 // Figure out which register class each belongs in: rc_int, rc_float, rc_stack
1275 enum RC { rc_bad, rc_int, rc_float, rc_stack };
1276 static enum RC rc_class( OptoReg::Name reg ) {
1277 if( !OptoReg::is_valid(reg) ) return rc_bad;
1278 if (OptoReg::is_stack(reg)) return rc_stack;
1279 VMReg r = OptoReg::as_VMReg(reg);
1280 if (r->is_Register()) return rc_int;
1281 assert(r->is_FloatRegister(), "must be");
1282 return rc_float;
1283 }
1284
1285 static int impl_helper( const MachNode *mach, CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, bool is_load, int offset, int reg, int opcode, const char *op_str, int size, outputStream* st ) {
1286 if( cbuf ) {
1287 // Better yet would be some mechanism to handle variable-size matches correctly
1288 if (!Assembler::is_simm13(offset + STACK_BIAS)) {
1289 ra_->C->record_method_not_compilable("unable to handle large constant offsets");
1290 } else {
1291 emit_form3_mem_reg(*cbuf, mach, opcode, -1, R_SP_enc, offset, 0, Matcher::_regEncode[reg]);
1292 }
1293 }
1294 #ifndef PRODUCT
1295 else if( !do_size ) {
1296 if( size != 0 ) st->print("\n\t");
1297 if( is_load ) st->print("%s [R_SP + #%d],R_%s\t! spill",op_str,offset,OptoReg::regname(reg));
1298 else st->print("%s R_%s,[R_SP + #%d]\t! spill",op_str,OptoReg::regname(reg),offset);
1299 }
1300 #endif
1301 return size+4;
1302 }
1303
1304 static int impl_mov_helper( CodeBuffer *cbuf, bool do_size, int src, int dst, int op1, int op2, const char *op_str, int size, outputStream* st ) {
1305 if( cbuf ) emit3( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst], op1, 0, op2, Matcher::_regEncode[src] );
1306 #ifndef PRODUCT
1307 else if( !do_size ) {
1308 if( size != 0 ) st->print("\n\t");
1309 st->print("%s R_%s,R_%s\t! spill",op_str,OptoReg::regname(src),OptoReg::regname(dst));
1310 }
1311 #endif
1312 return size+4;
1313 }
1314
1315 uint MachSpillCopyNode::implementation( CodeBuffer *cbuf,
1316 PhaseRegAlloc *ra_,
1317 bool do_size,
1318 outputStream* st ) const {
1319 // Get registers to move
1320 OptoReg::Name src_second = ra_->get_reg_second(in(1));
1321 OptoReg::Name src_first = ra_->get_reg_first(in(1));
1322 OptoReg::Name dst_second = ra_->get_reg_second(this );
1323 OptoReg::Name dst_first = ra_->get_reg_first(this );
1324
1325 enum RC src_second_rc = rc_class(src_second);
1326 enum RC src_first_rc = rc_class(src_first);
1327 enum RC dst_second_rc = rc_class(dst_second);
1328 enum RC dst_first_rc = rc_class(dst_first);
1329
1330 assert( OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), "must move at least 1 register" );
1331
1332 // Generate spill code!
1333 int size = 0;
1334
1335 if( src_first == dst_first && src_second == dst_second )
1336 return size; // Self copy, no move
1337
1338 // --------------------------------------
1339 // Check for mem-mem move. Load into unused float registers and fall into
1340 // the float-store case.
1341 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) {
1342 int offset = ra_->reg2offset(src_first);
1343 // Further check for aligned-adjacent pair, so we can use a double load
1344 if( (src_first&1)==0 && src_first+1 == src_second ) {
1345 src_second = OptoReg::Name(R_F31_num);
1346 src_second_rc = rc_float;
1347 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F30_num,Assembler::lddf_op3,"LDDF",size, st);
1348 } else {
1349 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F30_num,Assembler::ldf_op3 ,"LDF ",size, st);
1350 }
1351 src_first = OptoReg::Name(R_F30_num);
1352 src_first_rc = rc_float;
1353 }
1354
1355 if( src_second_rc == rc_stack && dst_second_rc == rc_stack ) {
1356 int offset = ra_->reg2offset(src_second);
1357 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F31_num,Assembler::ldf_op3,"LDF ",size, st);
1358 src_second = OptoReg::Name(R_F31_num);
1359 src_second_rc = rc_float;
1360 }
1361
1362 // --------------------------------------
1363 // Check for float->int copy; requires a trip through memory
1364 if (src_first_rc == rc_float && dst_first_rc == rc_int && UseVIS < 3) {
1365 int offset = frame::register_save_words*wordSize;
1366 if (cbuf) {
1367 emit3_simm13( *cbuf, Assembler::arith_op, R_SP_enc, Assembler::sub_op3, R_SP_enc, 16 );
1368 impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st);
1369 impl_helper(this,cbuf,ra_,do_size,true ,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st);
1370 emit3_simm13( *cbuf, Assembler::arith_op, R_SP_enc, Assembler::add_op3, R_SP_enc, 16 );
1371 }
1372 #ifndef PRODUCT
1373 else if (!do_size) {
1374 if (size != 0) st->print("\n\t");
1375 st->print( "SUB R_SP,16,R_SP\n");
1376 impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st);
1377 impl_helper(this,cbuf,ra_,do_size,true ,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st);
1378 st->print("\tADD R_SP,16,R_SP\n");
1379 }
1380 #endif
1381 size += 16;
1382 }
1383
1384 // Check for float->int copy on T4
1385 if (src_first_rc == rc_float && dst_first_rc == rc_int && UseVIS >= 3) {
1386 // Further check for aligned-adjacent pair, so we can use a double move
1387 if ((src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second)
1388 return impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mdtox_opf,"MOVDTOX",size, st);
1389 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mstouw_opf,"MOVSTOUW",size, st);
1390 }
1391 // Check for int->float copy on T4
1392 if (src_first_rc == rc_int && dst_first_rc == rc_float && UseVIS >= 3) {
1393 // Further check for aligned-adjacent pair, so we can use a double move
1394 if ((src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second)
1395 return impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mxtod_opf,"MOVXTOD",size, st);
1396 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mwtos_opf,"MOVWTOS",size, st);
1397 }
1398
1399 // --------------------------------------
1400 // In the 32-bit 1-reg-longs build ONLY, I see mis-aligned long destinations.
1401 // In such cases, I have to do the big-endian swap. For aligned targets, the
1402 // hardware does the flop for me. Doubles are always aligned, so no problem
1403 // there. Misaligned sources only come from native-long-returns (handled
1404 // special below).
1405 #ifndef _LP64
1406 if( src_first_rc == rc_int && // source is already big-endian
1407 src_second_rc != rc_bad && // 64-bit move
1408 ((dst_first&1)!=0 || dst_second != dst_first+1) ) { // misaligned dst
1409 assert( (src_first&1)==0 && src_second == src_first+1, "source must be aligned" );
1410 // Do the big-endian flop.
1411 OptoReg::Name tmp = dst_first ; dst_first = dst_second ; dst_second = tmp ;
1412 enum RC tmp_rc = dst_first_rc; dst_first_rc = dst_second_rc; dst_second_rc = tmp_rc;
1413 }
1414 #endif
1415
1416 // --------------------------------------
1417 // Check for integer reg-reg copy
1418 if( src_first_rc == rc_int && dst_first_rc == rc_int ) {
1419 #ifndef _LP64
1420 if( src_first == R_O0_num && src_second == R_O1_num ) { // Check for the evil O0/O1 native long-return case
1421 // Note: The _first and _second suffixes refer to the addresses of the the 2 halves of the 64-bit value
1422 // as stored in memory. On a big-endian machine like SPARC, this means that the _second
1423 // operand contains the least significant word of the 64-bit value and vice versa.
1424 OptoReg::Name tmp = OptoReg::Name(R_O7_num);
1425 assert( (dst_first&1)==0 && dst_second == dst_first+1, "return a native O0/O1 long to an aligned-adjacent 64-bit reg" );
1426 // Shift O0 left in-place, zero-extend O1, then OR them into the dst
1427 if( cbuf ) {
1428 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[tmp], Assembler::sllx_op3, Matcher::_regEncode[src_first], 0x1020 );
1429 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[src_second], Assembler::srl_op3, Matcher::_regEncode[src_second], 0x0000 );
1430 emit3 ( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_first], Assembler:: or_op3, Matcher::_regEncode[tmp], 0, Matcher::_regEncode[src_second] );
1431 #ifndef PRODUCT
1432 } else if( !do_size ) {
1433 if( size != 0 ) st->print("\n\t");
1434 st->print("SLLX R_%s,32,R_%s\t! Move O0-first to O7-high\n\t", OptoReg::regname(src_first), OptoReg::regname(tmp));
1435 st->print("SRL R_%s, 0,R_%s\t! Zero-extend O1\n\t", OptoReg::regname(src_second), OptoReg::regname(src_second));
1436 st->print("OR R_%s,R_%s,R_%s\t! spill",OptoReg::regname(tmp), OptoReg::regname(src_second), OptoReg::regname(dst_first));
1437 #endif
1438 }
1439 return size+12;
1440 }
1441 else if( dst_first == R_I0_num && dst_second == R_I1_num ) {
1442 // returning a long value in I0/I1
1443 // a SpillCopy must be able to target a return instruction's reg_class
1444 // Note: The _first and _second suffixes refer to the addresses of the the 2 halves of the 64-bit value
1445 // as stored in memory. On a big-endian machine like SPARC, this means that the _second
1446 // operand contains the least significant word of the 64-bit value and vice versa.
1447 OptoReg::Name tdest = dst_first;
1448
1449 if (src_first == dst_first) {
1450 tdest = OptoReg::Name(R_O7_num);
1451 size += 4;
1452 }
1453
1454 if( cbuf ) {
1455 assert( (src_first&1) == 0 && (src_first+1) == src_second, "return value was in an aligned-adjacent 64-bit reg");
1456 // Shift value in upper 32-bits of src to lower 32-bits of I0; move lower 32-bits to I1
1457 // ShrL_reg_imm6
1458 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[tdest], Assembler::srlx_op3, Matcher::_regEncode[src_second], 32 | 0x1000 );
1459 // ShrR_reg_imm6 src, 0, dst
1460 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_second], Assembler::srl_op3, Matcher::_regEncode[src_first], 0x0000 );
1461 if (tdest != dst_first) {
1462 emit3 ( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_first], Assembler::or_op3, 0/*G0*/, 0/*op2*/, Matcher::_regEncode[tdest] );
1463 }
1464 }
1465 #ifndef PRODUCT
1466 else if( !do_size ) {
1467 if( size != 0 ) st->print("\n\t"); // %%%%% !!!!!
1468 st->print("SRLX R_%s,32,R_%s\t! Extract MSW\n\t",OptoReg::regname(src_second),OptoReg::regname(tdest));
1469 st->print("SRL R_%s, 0,R_%s\t! Extract LSW\n\t",OptoReg::regname(src_first),OptoReg::regname(dst_second));
1470 if (tdest != dst_first) {
1471 st->print("MOV R_%s,R_%s\t! spill\n\t", OptoReg::regname(tdest), OptoReg::regname(dst_first));
1472 }
1473 }
1474 #endif // PRODUCT
1475 return size+8;
1476 }
1477 #endif // !_LP64
1478 // Else normal reg-reg copy
1479 assert( src_second != dst_first, "smashed second before evacuating it" );
1480 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::or_op3,0,"MOV ",size, st);
1481 assert( (src_first&1) == 0 && (dst_first&1) == 0, "never move second-halves of int registers" );
1482 // This moves an aligned adjacent pair.
1483 // See if we are done.
1484 if( src_first+1 == src_second && dst_first+1 == dst_second )
1485 return size;
1486 }
1487
1488 // Check for integer store
1489 if( src_first_rc == rc_int && dst_first_rc == rc_stack ) {
1490 int offset = ra_->reg2offset(dst_first);
1491 // Further check for aligned-adjacent pair, so we can use a double store
1492 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1493 return impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stx_op3,"STX ",size, st);
1494 size = impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stw_op3,"STW ",size, st);
1495 }
1496
1497 // Check for integer load
1498 if( dst_first_rc == rc_int && src_first_rc == rc_stack ) {
1499 int offset = ra_->reg2offset(src_first);
1500 // Further check for aligned-adjacent pair, so we can use a double load
1501 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1502 return impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::ldx_op3 ,"LDX ",size, st);
1503 size = impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st);
1504 }
1505
1506 // Check for float reg-reg copy
1507 if( src_first_rc == rc_float && dst_first_rc == rc_float ) {
1508 // Further check for aligned-adjacent pair, so we can use a double move
1509 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1510 return impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::fpop1_op3,Assembler::fmovd_opf,"FMOVD",size, st);
1511 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::fpop1_op3,Assembler::fmovs_opf,"FMOVS",size, st);
1512 }
1513
1514 // Check for float store
1515 if( src_first_rc == rc_float && dst_first_rc == rc_stack ) {
1516 int offset = ra_->reg2offset(dst_first);
1517 // Further check for aligned-adjacent pair, so we can use a double store
1518 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1519 return impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stdf_op3,"STDF",size, st);
1520 size = impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st);
1521 }
1522
1523 // Check for float load
1524 if( dst_first_rc == rc_float && src_first_rc == rc_stack ) {
1525 int offset = ra_->reg2offset(src_first);
1526 // Further check for aligned-adjacent pair, so we can use a double load
1527 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1528 return impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::lddf_op3,"LDDF",size, st);
1529 size = impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::ldf_op3 ,"LDF ",size, st);
1530 }
1531
1532 // --------------------------------------------------------------------
1533 // Check for hi bits still needing moving. Only happens for misaligned
1534 // arguments to native calls.
1535 if( src_second == dst_second )
1536 return size; // Self copy; no move
1537 assert( src_second_rc != rc_bad && dst_second_rc != rc_bad, "src_second & dst_second cannot be Bad" );
1538
1539 #ifndef _LP64
1540 // In the LP64 build, all registers can be moved as aligned/adjacent
1541 // pairs, so there's never any need to move the high bits separately.
1542 // The 32-bit builds have to deal with the 32-bit ABI which can force
1543 // all sorts of silly alignment problems.
1544
1545 // Check for integer reg-reg copy. Hi bits are stuck up in the top
1546 // 32-bits of a 64-bit register, but are needed in low bits of another
1547 // register (else it's a hi-bits-to-hi-bits copy which should have
1548 // happened already as part of a 64-bit move)
1549 if( src_second_rc == rc_int && dst_second_rc == rc_int ) {
1550 assert( (src_second&1)==1, "its the evil O0/O1 native return case" );
1551 assert( (dst_second&1)==0, "should have moved with 1 64-bit move" );
1552 // Shift src_second down to dst_second's low bits.
1553 if( cbuf ) {
1554 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_second], Assembler::srlx_op3, Matcher::_regEncode[src_second-1], 0x1020 );
1555 #ifndef PRODUCT
1556 } else if( !do_size ) {
1557 if( size != 0 ) st->print("\n\t");
1558 st->print("SRLX R_%s,32,R_%s\t! spill: Move high bits down low",OptoReg::regname(src_second-1),OptoReg::regname(dst_second));
1559 #endif
1560 }
1561 return size+4;
1562 }
1563
1564 // Check for high word integer store. Must down-shift the hi bits
1565 // into a temp register, then fall into the case of storing int bits.
1566 if( src_second_rc == rc_int && dst_second_rc == rc_stack && (src_second&1)==1 ) {
1567 // Shift src_second down to dst_second's low bits.
1568 if( cbuf ) {
1569 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[R_O7_num], Assembler::srlx_op3, Matcher::_regEncode[src_second-1], 0x1020 );
1570 #ifndef PRODUCT
1571 } else if( !do_size ) {
1572 if( size != 0 ) st->print("\n\t");
1573 st->print("SRLX R_%s,32,R_%s\t! spill: Move high bits down low",OptoReg::regname(src_second-1),OptoReg::regname(R_O7_num));
1574 #endif
1575 }
1576 size+=4;
1577 src_second = OptoReg::Name(R_O7_num); // Not R_O7H_num!
1578 }
1579
1580 // Check for high word integer load
1581 if( dst_second_rc == rc_int && src_second_rc == rc_stack )
1582 return impl_helper(this,cbuf,ra_,do_size,true ,ra_->reg2offset(src_second),dst_second,Assembler::lduw_op3,"LDUW",size, st);
1583
1584 // Check for high word integer store
1585 if( src_second_rc == rc_int && dst_second_rc == rc_stack )
1586 return impl_helper(this,cbuf,ra_,do_size,false,ra_->reg2offset(dst_second),src_second,Assembler::stw_op3 ,"STW ",size, st);
1587
1588 // Check for high word float store
1589 if( src_second_rc == rc_float && dst_second_rc == rc_stack )
1590 return impl_helper(this,cbuf,ra_,do_size,false,ra_->reg2offset(dst_second),src_second,Assembler::stf_op3 ,"STF ",size, st);
1591
1592 #endif // !_LP64
1593
1594 Unimplemented();
1595 }
1596
1597 #ifndef PRODUCT
1598 void MachSpillCopyNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1599 implementation( NULL, ra_, false, st );
1600 }
1601 #endif
1602
1603 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1604 implementation( &cbuf, ra_, false, NULL );
1605 }
1606
1607 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1608 return implementation( NULL, ra_, true, NULL );
1609 }
1610
1611 //=============================================================================
1612 #ifndef PRODUCT
1613 void MachNopNode::format( PhaseRegAlloc *, outputStream *st ) const {
1614 st->print("NOP \t# %d bytes pad for loops and calls", 4 * _count);
1615 }
1616 #endif
1617
1618 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc * ) const {
1619 MacroAssembler _masm(&cbuf);
1620 for(int i = 0; i < _count; i += 1) {
1621 __ nop();
1622 }
1623 }
1624
1625 uint MachNopNode::size(PhaseRegAlloc *ra_) const {
1626 return 4 * _count;
1627 }
1628
1629
1630 //=============================================================================
1631 #ifndef PRODUCT
1632 void BoxLockNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1633 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1634 int reg = ra_->get_reg_first(this);
1635 st->print("LEA [R_SP+#%d+BIAS],%s",offset,Matcher::regName[reg]);
1636 }
1637 #endif
1638
1639 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1640 MacroAssembler _masm(&cbuf);
1641 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()) + STACK_BIAS;
1642 int reg = ra_->get_encode(this);
1643
1644 if (Assembler::is_simm13(offset)) {
1645 __ add(SP, offset, reg_to_register_object(reg));
1646 } else {
1647 __ set(offset, O7);
1648 __ add(SP, O7, reg_to_register_object(reg));
1649 }
1650 }
1651
1652 uint BoxLockNode::size(PhaseRegAlloc *ra_) const {
1653 // BoxLockNode is not a MachNode, so we can't just call MachNode::size(ra_)
1654 assert(ra_ == ra_->C->regalloc(), "sanity");
1655 return ra_->C->scratch_emit_size(this);
1656 }
1657
1658 //=============================================================================
1659 #ifndef PRODUCT
1660 void MachUEPNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1661 st->print_cr("\nUEP:");
1662 #ifdef _LP64
1663 if (UseCompressedKlassPointers) {
1664 assert(Universe::heap() != NULL, "java heap should be initialized");
1665 st->print_cr("\tLDUW [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check - compressed klass");
1666 st->print_cr("\tSLL R_G5,3,R_G5");
1667 if (Universe::narrow_klass_base() != NULL)
1668 st->print_cr("\tADD R_G5,R_G6_heap_base,R_G5");
1669 } else {
1670 st->print_cr("\tLDX [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check");
1671 }
1672 st->print_cr("\tCMP R_G5,R_G3" );
1673 st->print ("\tTne xcc,R_G0+ST_RESERVED_FOR_USER_0+2");
1674 #else // _LP64
1675 st->print_cr("\tLDUW [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check");
1676 st->print_cr("\tCMP R_G5,R_G3" );
1677 st->print ("\tTne icc,R_G0+ST_RESERVED_FOR_USER_0+2");
1678 #endif // _LP64
1679 }
1680 #endif
1681
1682 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1683 MacroAssembler _masm(&cbuf);
1684 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode());
1685 Register temp_reg = G3;
1686 assert( G5_ic_reg != temp_reg, "conflicting registers" );
1687
1688 // Load klass from receiver
1689 __ load_klass(O0, temp_reg);
1690 // Compare against expected klass
1691 __ cmp(temp_reg, G5_ic_reg);
1692 // Branch to miss code, checks xcc or icc depending
1693 __ trap(Assembler::notEqual, Assembler::ptr_cc, G0, ST_RESERVED_FOR_USER_0+2);
1694 }
1695
1696 uint MachUEPNode::size(PhaseRegAlloc *ra_) const {
1697 return MachNode::size(ra_);
1698 }
1699
1700
1701 //=============================================================================
1702
1703 uint size_exception_handler() {
1704 if (TraceJumps) {
1705 return (400); // just a guess
1706 }
1707 return ( NativeJump::instruction_size ); // sethi;jmp;nop
1708 }
1709
1710 uint size_deopt_handler() {
1711 if (TraceJumps) {
1712 return (400); // just a guess
1713 }
1714 return ( 4+ NativeJump::instruction_size ); // save;sethi;jmp;restore
1715 }
1716
1717 // Emit exception handler code.
1718 int emit_exception_handler(CodeBuffer& cbuf) {
1719 Register temp_reg = G3;
1720 AddressLiteral exception_blob(OptoRuntime::exception_blob()->entry_point());
1721 MacroAssembler _masm(&cbuf);
1722
1723 address base =
1724 __ start_a_stub(size_exception_handler());
1725 if (base == NULL) return 0; // CodeBuffer::expand failed
1726
1727 int offset = __ offset();
1728
1729 __ JUMP(exception_blob, temp_reg, 0); // sethi;jmp
1730 __ delayed()->nop();
1731
1732 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow");
1733
1734 __ end_a_stub();
1735
1736 return offset;
1737 }
1738
1739 int emit_deopt_handler(CodeBuffer& cbuf) {
1740 // Can't use any of the current frame's registers as we may have deopted
1741 // at a poll and everything (including G3) can be live.
1742 Register temp_reg = L0;
1743 AddressLiteral deopt_blob(SharedRuntime::deopt_blob()->unpack());
1744 MacroAssembler _masm(&cbuf);
1745
1746 address base =
1747 __ start_a_stub(size_deopt_handler());
1748 if (base == NULL) return 0; // CodeBuffer::expand failed
1749
1750 int offset = __ offset();
1751 __ save_frame(0);
1752 __ JUMP(deopt_blob, temp_reg, 0); // sethi;jmp
1753 __ delayed()->restore();
1754
1755 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow");
1756
1757 __ end_a_stub();
1758 return offset;
1759
1760 }
1761
1762 // Given a register encoding, produce a Integer Register object
1763 static Register reg_to_register_object(int register_encoding) {
1764 assert(L5->encoding() == R_L5_enc && G1->encoding() == R_G1_enc, "right coding");
1765 return as_Register(register_encoding);
1766 }
1767
1768 // Given a register encoding, produce a single-precision Float Register object
1769 static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding) {
1770 assert(F5->encoding(FloatRegisterImpl::S) == R_F5_enc && F12->encoding(FloatRegisterImpl::S) == R_F12_enc, "right coding");
1771 return as_SingleFloatRegister(register_encoding);
1772 }
1773
1774 // Given a register encoding, produce a double-precision Float Register object
1775 static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding) {
1776 assert(F4->encoding(FloatRegisterImpl::D) == R_F4_enc, "right coding");
1777 assert(F32->encoding(FloatRegisterImpl::D) == R_D32_enc, "right coding");
1778 return as_DoubleFloatRegister(register_encoding);
1779 }
1780
1781 const bool Matcher::match_rule_supported(int opcode) {
1782 if (!has_match_rule(opcode))
1783 return false;
1784
1785 switch (opcode) {
1786 case Op_CountLeadingZerosI:
1787 case Op_CountLeadingZerosL:
1788 case Op_CountTrailingZerosI:
1789 case Op_CountTrailingZerosL:
1790 case Op_PopCountI:
1791 case Op_PopCountL:
1792 if (!UsePopCountInstruction)
1793 return false;
1794 case Op_CompareAndSwapL:
1795 #ifdef _LP64
1796 case Op_CompareAndSwapP:
1797 #endif
1798 if (!VM_Version::supports_cx8())
1799 return false;
1800 break;
1801 }
1802
1803 return true; // Per default match rules are supported.
1804 }
1805
1806 int Matcher::regnum_to_fpu_offset(int regnum) {
1807 return regnum - 32; // The FP registers are in the second chunk
1808 }
1809
1810 #ifdef ASSERT
1811 address last_rethrow = NULL; // debugging aid for Rethrow encoding
1812 #endif
1813
1814 // Vector width in bytes
1815 const int Matcher::vector_width_in_bytes(BasicType bt) {
1816 assert(MaxVectorSize == 8, "");
1817 return 8;
1818 }
1819
1820 // Vector ideal reg
1821 const int Matcher::vector_ideal_reg(int size) {
1822 assert(MaxVectorSize == 8, "");
1823 return Op_RegD;
1824 }
1825
1826 const int Matcher::vector_shift_count_ideal_reg(int size) {
1827 fatal("vector shift is not supported");
1828 return Node::NotAMachineReg;
1829 }
1830
1831 // Limits on vector size (number of elements) loaded into vector.
1832 const int Matcher::max_vector_size(const BasicType bt) {
1833 assert(is_java_primitive(bt), "only primitive type vectors");
1834 return vector_width_in_bytes(bt)/type2aelembytes(bt);
1835 }
1836
1837 const int Matcher::min_vector_size(const BasicType bt) {
1838 return max_vector_size(bt); // Same as max.
1839 }
1840
1841 // SPARC doesn't support misaligned vectors store/load.
1842 const bool Matcher::misaligned_vectors_ok() {
1843 return false;
1844 }
1845
1846 // USII supports fxtof through the whole range of number, USIII doesn't
1847 const bool Matcher::convL2FSupported(void) {
1848 return VM_Version::has_fast_fxtof();
1849 }
1850
1851 // Is this branch offset short enough that a short branch can be used?
1852 //
1853 // NOTE: If the platform does not provide any short branch variants, then
1854 // this method should return false for offset 0.
1855 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
1856 // The passed offset is relative to address of the branch.
1857 // Don't need to adjust the offset.
1858 return UseCBCond && Assembler::is_simm12(offset);
1859 }
1860
1861 const bool Matcher::isSimpleConstant64(jlong value) {
1862 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?.
1863 // Depends on optimizations in MacroAssembler::setx.
1864 int hi = (int)(value >> 32);
1865 int lo = (int)(value & ~0);
1866 return (hi == 0) || (hi == -1) || (lo == 0);
1867 }
1868
1869 // No scaling for the parameter the ClearArray node.
1870 const bool Matcher::init_array_count_is_in_bytes = true;
1871
1872 // Threshold size for cleararray.
1873 const int Matcher::init_array_short_size = 8 * BytesPerLong;
1874
1875 // No additional cost for CMOVL.
1876 const int Matcher::long_cmove_cost() { return 0; }
1877
1878 // CMOVF/CMOVD are expensive on T4 and on SPARC64.
1879 const int Matcher::float_cmove_cost() {
1880 return (VM_Version::is_T4() || VM_Version::is_sparc64()) ? ConditionalMoveLimit : 0;
1881 }
1882
1883 // Should the Matcher clone shifts on addressing modes, expecting them to
1884 // be subsumed into complex addressing expressions or compute them into
1885 // registers? True for Intel but false for most RISCs
1886 const bool Matcher::clone_shift_expressions = false;
1887
1888 // Do we need to mask the count passed to shift instructions or does
1889 // the cpu only look at the lower 5/6 bits anyway?
1890 const bool Matcher::need_masked_shift_count = false;
1891
1892 bool Matcher::narrow_oop_use_complex_address() {
1893 NOT_LP64(ShouldNotCallThis());
1894 assert(UseCompressedOops, "only for compressed oops code");
1895 return false;
1896 }
1897
1898 bool Matcher::narrow_klass_use_complex_address() {
1899 NOT_LP64(ShouldNotCallThis());
1900 assert(UseCompressedKlassPointers, "only for compressed klass code");
1901 return false;
1902 }
1903
1904 // Is it better to copy float constants, or load them directly from memory?
1905 // Intel can load a float constant from a direct address, requiring no
1906 // extra registers. Most RISCs will have to materialize an address into a
1907 // register first, so they would do better to copy the constant from stack.
1908 const bool Matcher::rematerialize_float_constants = false;
1909
1910 // If CPU can load and store mis-aligned doubles directly then no fixup is
1911 // needed. Else we split the double into 2 integer pieces and move it
1912 // piece-by-piece. Only happens when passing doubles into C code as the
1913 // Java calling convention forces doubles to be aligned.
1914 #ifdef _LP64
1915 const bool Matcher::misaligned_doubles_ok = true;
1916 #else
1917 const bool Matcher::misaligned_doubles_ok = false;
1918 #endif
1919
1920 // No-op on SPARC.
1921 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {
1922 }
1923
1924 // Advertise here if the CPU requires explicit rounding operations
1925 // to implement the UseStrictFP mode.
1926 const bool Matcher::strict_fp_requires_explicit_rounding = false;
1927
1928 // Are floats conerted to double when stored to stack during deoptimization?
1929 // Sparc does not handle callee-save floats.
1930 bool Matcher::float_in_double() { return false; }
1931
1932 // Do ints take an entire long register or just half?
1933 // Note that we if-def off of _LP64.
1934 // The relevant question is how the int is callee-saved. In _LP64
1935 // the whole long is written but de-opt'ing will have to extract
1936 // the relevant 32 bits, in not-_LP64 only the low 32 bits is written.
1937 #ifdef _LP64
1938 const bool Matcher::int_in_long = true;
1939 #else
1940 const bool Matcher::int_in_long = false;
1941 #endif
1942
1943 // Return whether or not this register is ever used as an argument. This
1944 // function is used on startup to build the trampoline stubs in generateOptoStub.
1945 // Registers not mentioned will be killed by the VM call in the trampoline, and
1946 // arguments in those registers not be available to the callee.
1947 bool Matcher::can_be_java_arg( int reg ) {
1948 // Standard sparc 6 args in registers
1949 if( reg == R_I0_num ||
1950 reg == R_I1_num ||
1951 reg == R_I2_num ||
1952 reg == R_I3_num ||
1953 reg == R_I4_num ||
1954 reg == R_I5_num ) return true;
1955 #ifdef _LP64
1956 // 64-bit builds can pass 64-bit pointers and longs in
1957 // the high I registers
1958 if( reg == R_I0H_num ||
1959 reg == R_I1H_num ||
1960 reg == R_I2H_num ||
1961 reg == R_I3H_num ||
1962 reg == R_I4H_num ||
1963 reg == R_I5H_num ) return true;
1964
1965 if ((UseCompressedOops) && (reg == R_G6_num || reg == R_G6H_num)) {
1966 return true;
1967 }
1968
1969 #else
1970 // 32-bit builds with longs-in-one-entry pass longs in G1 & G4.
1971 // Longs cannot be passed in O regs, because O regs become I regs
1972 // after a 'save' and I regs get their high bits chopped off on
1973 // interrupt.
1974 if( reg == R_G1H_num || reg == R_G1_num ) return true;
1975 if( reg == R_G4H_num || reg == R_G4_num ) return true;
1976 #endif
1977 // A few float args in registers
1978 if( reg >= R_F0_num && reg <= R_F7_num ) return true;
1979
1980 return false;
1981 }
1982
1983 bool Matcher::is_spillable_arg( int reg ) {
1984 return can_be_java_arg(reg);
1985 }
1986
1987 bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) {
1988 // Use hardware SDIVX instruction when it is
1989 // faster than a code which use multiply.
1990 return VM_Version::has_fast_idiv();
1991 }
1992
1993 // Register for DIVI projection of divmodI
1994 RegMask Matcher::divI_proj_mask() {
1995 ShouldNotReachHere();
1996 return RegMask();
1997 }
1998
1999 // Register for MODI projection of divmodI
2000 RegMask Matcher::modI_proj_mask() {
2001 ShouldNotReachHere();
2002 return RegMask();
2003 }
2004
2005 // Register for DIVL projection of divmodL
2006 RegMask Matcher::divL_proj_mask() {
2007 ShouldNotReachHere();
2008 return RegMask();
2009 }
2010
2011 // Register for MODL projection of divmodL
2012 RegMask Matcher::modL_proj_mask() {
2013 ShouldNotReachHere();
2014 return RegMask();
2015 }
2016
2017 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
2018 return L7_REGP_mask();
2019 }
2020
2021 %}
2022
2023
2024 // The intptr_t operand types, defined by textual substitution.
2025 // (Cf. opto/type.hpp. This lets us avoid many, many other ifdefs.)
2026 #ifdef _LP64
2027 #define immX immL
2028 #define immX13 immL13
2029 #define immX13m7 immL13m7
2030 #define iRegX iRegL
2031 #define g1RegX g1RegL
2032 #else
2033 #define immX immI
2034 #define immX13 immI13
2035 #define immX13m7 immI13m7
2036 #define iRegX iRegI
2037 #define g1RegX g1RegI
2038 #endif
2039
2040 //----------ENCODING BLOCK-----------------------------------------------------
2041 // This block specifies the encoding classes used by the compiler to output
2042 // byte streams. Encoding classes are parameterized macros used by
2043 // Machine Instruction Nodes in order to generate the bit encoding of the
2044 // instruction. Operands specify their base encoding interface with the
2045 // interface keyword. There are currently supported four interfaces,
2046 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an
2047 // operand to generate a function which returns its register number when
2048 // queried. CONST_INTER causes an operand to generate a function which
2049 // returns the value of the constant when queried. MEMORY_INTER causes an
2050 // operand to generate four functions which return the Base Register, the
2051 // Index Register, the Scale Value, and the Offset Value of the operand when
2052 // queried. COND_INTER causes an operand to generate six functions which
2053 // return the encoding code (ie - encoding bits for the instruction)
2054 // associated with each basic boolean condition for a conditional instruction.
2055 //
2056 // Instructions specify two basic values for encoding. Again, a function
2057 // is available to check if the constant displacement is an oop. They use the
2058 // ins_encode keyword to specify their encoding classes (which must be
2059 // a sequence of enc_class names, and their parameters, specified in
2060 // the encoding block), and they use the
2061 // opcode keyword to specify, in order, their primary, secondary, and
2062 // tertiary opcode. Only the opcode sections which a particular instruction
2063 // needs for encoding need to be specified.
2064 encode %{
2065 enc_class enc_untested %{
2066 #ifdef ASSERT
2067 MacroAssembler _masm(&cbuf);
2068 __ untested("encoding");
2069 #endif
2070 %}
2071
2072 enc_class form3_mem_reg( memory mem, iRegI dst ) %{
2073 emit_form3_mem_reg(cbuf, this, $primary, $tertiary,
2074 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg);
2075 %}
2076
2077 enc_class simple_form3_mem_reg( memory mem, iRegI dst ) %{
2078 emit_form3_mem_reg(cbuf, this, $primary, -1,
2079 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg);
2080 %}
2081
2082 enc_class form3_mem_prefetch_read( memory mem ) %{
2083 emit_form3_mem_reg(cbuf, this, $primary, -1,
2084 $mem$$base, $mem$$disp, $mem$$index, 0/*prefetch function many-reads*/);
2085 %}
2086
2087 enc_class form3_mem_prefetch_write( memory mem ) %{
2088 emit_form3_mem_reg(cbuf, this, $primary, -1,
2089 $mem$$base, $mem$$disp, $mem$$index, 2/*prefetch function many-writes*/);
2090 %}
2091
2092 enc_class form3_mem_reg_long_unaligned_marshal( memory mem, iRegL reg ) %{
2093 assert(Assembler::is_simm13($mem$$disp ), "need disp and disp+4");
2094 assert(Assembler::is_simm13($mem$$disp+4), "need disp and disp+4");
2095 guarantee($mem$$index == R_G0_enc, "double index?");
2096 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, R_O7_enc );
2097 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg );
2098 emit3_simm13( cbuf, Assembler::arith_op, $reg$$reg, Assembler::sllx_op3, $reg$$reg, 0x1020 );
2099 emit3( cbuf, Assembler::arith_op, $reg$$reg, Assembler::or_op3, $reg$$reg, 0, R_O7_enc );
2100 %}
2101
2102 enc_class form3_mem_reg_double_unaligned( memory mem, RegD_low reg ) %{
2103 assert(Assembler::is_simm13($mem$$disp ), "need disp and disp+4");
2104 assert(Assembler::is_simm13($mem$$disp+4), "need disp and disp+4");
2105 guarantee($mem$$index == R_G0_enc, "double index?");
2106 // Load long with 2 instructions
2107 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg+0 );
2108 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, $reg$$reg+1 );
2109 %}
2110
2111 //%%% form3_mem_plus_4_reg is a hack--get rid of it
2112 enc_class form3_mem_plus_4_reg( memory mem, iRegI dst ) %{
2113 guarantee($mem$$disp, "cannot offset a reg-reg operand by 4");
2114 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp + 4, $mem$$index, $dst$$reg);
2115 %}
2116
2117 enc_class form3_g0_rs2_rd_move( iRegI rs2, iRegI rd ) %{
2118 // Encode a reg-reg copy. If it is useless, then empty encoding.
2119 if( $rs2$$reg != $rd$$reg )
2120 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, $rs2$$reg );
2121 %}
2122
2123 // Target lo half of long
2124 enc_class form3_g0_rs2_rd_move_lo( iRegI rs2, iRegL rd ) %{
2125 // Encode a reg-reg copy. If it is useless, then empty encoding.
2126 if( $rs2$$reg != LONG_LO_REG($rd$$reg) )
2127 emit3( cbuf, Assembler::arith_op, LONG_LO_REG($rd$$reg), Assembler::or_op3, 0, 0, $rs2$$reg );
2128 %}
2129
2130 // Source lo half of long
2131 enc_class form3_g0_rs2_rd_move_lo2( iRegL rs2, iRegI rd ) %{
2132 // Encode a reg-reg copy. If it is useless, then empty encoding.
2133 if( LONG_LO_REG($rs2$$reg) != $rd$$reg )
2134 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_LO_REG($rs2$$reg) );
2135 %}
2136
2137 // Target hi half of long
2138 enc_class form3_rs1_rd_copysign_hi( iRegI rs1, iRegL rd ) %{
2139 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 31 );
2140 %}
2141
2142 // Source lo half of long, and leave it sign extended.
2143 enc_class form3_rs1_rd_signextend_lo1( iRegL rs1, iRegI rd ) %{
2144 // Sign extend low half
2145 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 0, 0 );
2146 %}
2147
2148 // Source hi half of long, and leave it sign extended.
2149 enc_class form3_rs1_rd_copy_hi1( iRegL rs1, iRegI rd ) %{
2150 // Shift high half to low half
2151 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::srlx_op3, $rs1$$reg, 32 );
2152 %}
2153
2154 // Source hi half of long
2155 enc_class form3_g0_rs2_rd_move_hi2( iRegL rs2, iRegI rd ) %{
2156 // Encode a reg-reg copy. If it is useless, then empty encoding.
2157 if( LONG_HI_REG($rs2$$reg) != $rd$$reg )
2158 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_HI_REG($rs2$$reg) );
2159 %}
2160
2161 enc_class form3_rs1_rs2_rd( iRegI rs1, iRegI rs2, iRegI rd ) %{
2162 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0, $rs2$$reg );
2163 %}
2164
2165 enc_class enc_to_bool( iRegI src, iRegI dst ) %{
2166 emit3 ( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, 0, 0, $src$$reg );
2167 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::addc_op3 , 0, 0 );
2168 %}
2169
2170 enc_class enc_ltmask( iRegI p, iRegI q, iRegI dst ) %{
2171 emit3 ( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, $p$$reg, 0, $q$$reg );
2172 // clear if nothing else is happening
2173 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, 0 );
2174 // blt,a,pn done
2175 emit2_19 ( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less, Assembler::bp_op2, Assembler::icc, 0/*predict not taken*/, 2 );
2176 // mov dst,-1 in delay slot
2177 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 );
2178 %}
2179
2180 enc_class form3_rs1_imm5_rd( iRegI rs1, immU5 imm5, iRegI rd ) %{
2181 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $imm5$$constant & 0x1F );
2182 %}
2183
2184 enc_class form3_sd_rs1_imm6_rd( iRegL rs1, immU6 imm6, iRegL rd ) %{
2185 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, ($imm6$$constant & 0x3F) | 0x1000 );
2186 %}
2187
2188 enc_class form3_sd_rs1_rs2_rd( iRegL rs1, iRegI rs2, iRegL rd ) %{
2189 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0x80, $rs2$$reg );
2190 %}
2191
2192 enc_class form3_rs1_simm13_rd( iRegI rs1, immI13 simm13, iRegI rd ) %{
2193 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $simm13$$constant );
2194 %}
2195
2196 enc_class move_return_pc_to_o1() %{
2197 emit3_simm13( cbuf, Assembler::arith_op, R_O1_enc, Assembler::add_op3, R_O7_enc, frame::pc_return_offset );
2198 %}
2199
2200 #ifdef _LP64
2201 /* %%% merge with enc_to_bool */
2202 enc_class enc_convP2B( iRegI dst, iRegP src ) %{
2203 MacroAssembler _masm(&cbuf);
2204
2205 Register src_reg = reg_to_register_object($src$$reg);
2206 Register dst_reg = reg_to_register_object($dst$$reg);
2207 __ movr(Assembler::rc_nz, src_reg, 1, dst_reg);
2208 %}
2209 #endif
2210
2211 enc_class enc_cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp ) %{
2212 // (Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)))
2213 MacroAssembler _masm(&cbuf);
2214
2215 Register p_reg = reg_to_register_object($p$$reg);
2216 Register q_reg = reg_to_register_object($q$$reg);
2217 Register y_reg = reg_to_register_object($y$$reg);
2218 Register tmp_reg = reg_to_register_object($tmp$$reg);
2219
2220 __ subcc( p_reg, q_reg, p_reg );
2221 __ add ( p_reg, y_reg, tmp_reg );
2222 __ movcc( Assembler::less, false, Assembler::icc, tmp_reg, p_reg );
2223 %}
2224
2225 enc_class form_d2i_helper(regD src, regF dst) %{
2226 // fcmp %fcc0,$src,$src
2227 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg );
2228 // branch %fcc0 not-nan, predict taken
2229 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2230 // fdtoi $src,$dst
2231 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fdtoi_opf, $src$$reg );
2232 // fitos $dst,$dst (if nan)
2233 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fitos_opf, $dst$$reg );
2234 // clear $dst (if nan)
2235 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg );
2236 // carry on here...
2237 %}
2238
2239 enc_class form_d2l_helper(regD src, regD dst) %{
2240 // fcmp %fcc0,$src,$src check for NAN
2241 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg );
2242 // branch %fcc0 not-nan, predict taken
2243 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2244 // fdtox $src,$dst convert in delay slot
2245 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fdtox_opf, $src$$reg );
2246 // fxtod $dst,$dst (if nan)
2247 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fxtod_opf, $dst$$reg );
2248 // clear $dst (if nan)
2249 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg );
2250 // carry on here...
2251 %}
2252
2253 enc_class form_f2i_helper(regF src, regF dst) %{
2254 // fcmps %fcc0,$src,$src
2255 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg );
2256 // branch %fcc0 not-nan, predict taken
2257 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2258 // fstoi $src,$dst
2259 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fstoi_opf, $src$$reg );
2260 // fitos $dst,$dst (if nan)
2261 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fitos_opf, $dst$$reg );
2262 // clear $dst (if nan)
2263 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg );
2264 // carry on here...
2265 %}
2266
2267 enc_class form_f2l_helper(regF src, regD dst) %{
2268 // fcmps %fcc0,$src,$src
2269 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg );
2270 // branch %fcc0 not-nan, predict taken
2271 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2272 // fstox $src,$dst
2273 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fstox_opf, $src$$reg );
2274 // fxtod $dst,$dst (if nan)
2275 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fxtod_opf, $dst$$reg );
2276 // clear $dst (if nan)
2277 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg );
2278 // carry on here...
2279 %}
2280
2281 enc_class form3_opf_rs2F_rdF(regF rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2282 enc_class form3_opf_rs2F_rdD(regF rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2283 enc_class form3_opf_rs2D_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2284 enc_class form3_opf_rs2D_rdD(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2285
2286 enc_class form3_opf_rs2D_lo_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg+1); %}
2287
2288 enc_class form3_opf_rs2D_hi_rdD_hi(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2289 enc_class form3_opf_rs2D_lo_rdD_lo(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg+1,$primary,0,$tertiary,$rs2$$reg+1); %}
2290
2291 enc_class form3_opf_rs1F_rs2F_rdF( regF rs1, regF rs2, regF rd ) %{
2292 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2293 %}
2294
2295 enc_class form3_opf_rs1D_rs2D_rdD( regD rs1, regD rs2, regD rd ) %{
2296 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2297 %}
2298
2299 enc_class form3_opf_rs1F_rs2F_fcc( regF rs1, regF rs2, flagsRegF fcc ) %{
2300 emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2301 %}
2302
2303 enc_class form3_opf_rs1D_rs2D_fcc( regD rs1, regD rs2, flagsRegF fcc ) %{
2304 emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2305 %}
2306
2307 enc_class form3_convI2F(regF rs2, regF rd) %{
2308 emit3(cbuf,Assembler::arith_op,$rd$$reg,Assembler::fpop1_op3,0,$secondary,$rs2$$reg);
2309 %}
2310
2311 // Encloding class for traceable jumps
2312 enc_class form_jmpl(g3RegP dest) %{
2313 emit_jmpl(cbuf, $dest$$reg);
2314 %}
2315
2316 enc_class form_jmpl_set_exception_pc(g1RegP dest) %{
2317 emit_jmpl_set_exception_pc(cbuf, $dest$$reg);
2318 %}
2319
2320 enc_class form2_nop() %{
2321 emit_nop(cbuf);
2322 %}
2323
2324 enc_class form2_illtrap() %{
2325 emit_illtrap(cbuf);
2326 %}
2327
2328
2329 // Compare longs and convert into -1, 0, 1.
2330 enc_class cmpl_flag( iRegL src1, iRegL src2, iRegI dst ) %{
2331 // CMP $src1,$src2
2332 emit3( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, $src1$$reg, 0, $src2$$reg );
2333 // blt,a,pn done
2334 emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less , Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 5 );
2335 // mov dst,-1 in delay slot
2336 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 );
2337 // bgt,a,pn done
2338 emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::greater, Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 3 );
2339 // mov dst,1 in delay slot
2340 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, 1 );
2341 // CLR $dst
2342 emit3( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3 , 0, 0, 0 );
2343 %}
2344
2345 enc_class enc_PartialSubtypeCheck() %{
2346 MacroAssembler _masm(&cbuf);
2347 __ call(StubRoutines::Sparc::partial_subtype_check(), relocInfo::runtime_call_type);
2348 __ delayed()->nop();
2349 %}
2350
2351 enc_class enc_bp( label labl, cmpOp cmp, flagsReg cc ) %{
2352 MacroAssembler _masm(&cbuf);
2353 Label* L = $labl$$label;
2354 Assembler::Predict predict_taken =
2355 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
2356
2357 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
2358 __ delayed()->nop();
2359 %}
2360
2361 enc_class enc_bpr( label labl, cmpOp_reg cmp, iRegI op1 ) %{
2362 MacroAssembler _masm(&cbuf);
2363 Label* L = $labl$$label;
2364 Assembler::Predict predict_taken =
2365 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
2366
2367 __ bpr( (Assembler::RCondition)($cmp$$cmpcode), false, predict_taken, as_Register($op1$$reg), *L);
2368 __ delayed()->nop();
2369 %}
2370
2371 enc_class enc_cmov_reg( cmpOp cmp, iRegI dst, iRegI src, immI pcc) %{
2372 int op = (Assembler::arith_op << 30) |
2373 ($dst$$reg << 25) |
2374 (Assembler::movcc_op3 << 19) |
2375 (1 << 18) | // cc2 bit for 'icc'
2376 ($cmp$$cmpcode << 14) |
2377 (0 << 13) | // select register move
2378 ($pcc$$constant << 11) | // cc1, cc0 bits for 'icc' or 'xcc'
2379 ($src$$reg << 0);
2380 cbuf.insts()->emit_int32(op);
2381 %}
2382
2383 enc_class enc_cmov_imm( cmpOp cmp, iRegI dst, immI11 src, immI pcc ) %{
2384 int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits
2385 int op = (Assembler::arith_op << 30) |
2386 ($dst$$reg << 25) |
2387 (Assembler::movcc_op3 << 19) |
2388 (1 << 18) | // cc2 bit for 'icc'
2389 ($cmp$$cmpcode << 14) |
2390 (1 << 13) | // select immediate move
2391 ($pcc$$constant << 11) | // cc1, cc0 bits for 'icc'
2392 (simm11 << 0);
2393 cbuf.insts()->emit_int32(op);
2394 %}
2395
2396 enc_class enc_cmov_reg_f( cmpOpF cmp, iRegI dst, iRegI src, flagsRegF fcc ) %{
2397 int op = (Assembler::arith_op << 30) |
2398 ($dst$$reg << 25) |
2399 (Assembler::movcc_op3 << 19) |
2400 (0 << 18) | // cc2 bit for 'fccX'
2401 ($cmp$$cmpcode << 14) |
2402 (0 << 13) | // select register move
2403 ($fcc$$reg << 11) | // cc1, cc0 bits for fcc0-fcc3
2404 ($src$$reg << 0);
2405 cbuf.insts()->emit_int32(op);
2406 %}
2407
2408 enc_class enc_cmov_imm_f( cmpOp cmp, iRegI dst, immI11 src, flagsRegF fcc ) %{
2409 int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits
2410 int op = (Assembler::arith_op << 30) |
2411 ($dst$$reg << 25) |
2412 (Assembler::movcc_op3 << 19) |
2413 (0 << 18) | // cc2 bit for 'fccX'
2414 ($cmp$$cmpcode << 14) |
2415 (1 << 13) | // select immediate move
2416 ($fcc$$reg << 11) | // cc1, cc0 bits for fcc0-fcc3
2417 (simm11 << 0);
2418 cbuf.insts()->emit_int32(op);
2419 %}
2420
2421 enc_class enc_cmovf_reg( cmpOp cmp, regD dst, regD src, immI pcc ) %{
2422 int op = (Assembler::arith_op << 30) |
2423 ($dst$$reg << 25) |
2424 (Assembler::fpop2_op3 << 19) |
2425 (0 << 18) |
2426 ($cmp$$cmpcode << 14) |
2427 (1 << 13) | // select register move
2428 ($pcc$$constant << 11) | // cc1-cc0 bits for 'icc' or 'xcc'
2429 ($primary << 5) | // select single, double or quad
2430 ($src$$reg << 0);
2431 cbuf.insts()->emit_int32(op);
2432 %}
2433
2434 enc_class enc_cmovff_reg( cmpOpF cmp, flagsRegF fcc, regD dst, regD src ) %{
2435 int op = (Assembler::arith_op << 30) |
2436 ($dst$$reg << 25) |
2437 (Assembler::fpop2_op3 << 19) |
2438 (0 << 18) |
2439 ($cmp$$cmpcode << 14) |
2440 ($fcc$$reg << 11) | // cc2-cc0 bits for 'fccX'
2441 ($primary << 5) | // select single, double or quad
2442 ($src$$reg << 0);
2443 cbuf.insts()->emit_int32(op);
2444 %}
2445
2446 // Used by the MIN/MAX encodings. Same as a CMOV, but
2447 // the condition comes from opcode-field instead of an argument.
2448 enc_class enc_cmov_reg_minmax( iRegI dst, iRegI src ) %{
2449 int op = (Assembler::arith_op << 30) |
2450 ($dst$$reg << 25) |
2451 (Assembler::movcc_op3 << 19) |
2452 (1 << 18) | // cc2 bit for 'icc'
2453 ($primary << 14) |
2454 (0 << 13) | // select register move
2455 (0 << 11) | // cc1, cc0 bits for 'icc'
2456 ($src$$reg << 0);
2457 cbuf.insts()->emit_int32(op);
2458 %}
2459
2460 enc_class enc_cmov_reg_minmax_long( iRegL dst, iRegL src ) %{
2461 int op = (Assembler::arith_op << 30) |
2462 ($dst$$reg << 25) |
2463 (Assembler::movcc_op3 << 19) |
2464 (6 << 16) | // cc2 bit for 'xcc'
2465 ($primary << 14) |
2466 (0 << 13) | // select register move
2467 (0 << 11) | // cc1, cc0 bits for 'icc'
2468 ($src$$reg << 0);
2469 cbuf.insts()->emit_int32(op);
2470 %}
2471
2472 enc_class Set13( immI13 src, iRegI rd ) %{
2473 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, $src$$constant );
2474 %}
2475
2476 enc_class SetHi22( immI src, iRegI rd ) %{
2477 emit2_22( cbuf, Assembler::branch_op, $rd$$reg, Assembler::sethi_op2, $src$$constant );
2478 %}
2479
2480 enc_class Set32( immI src, iRegI rd ) %{
2481 MacroAssembler _masm(&cbuf);
2482 __ set($src$$constant, reg_to_register_object($rd$$reg));
2483 %}
2484
2485 enc_class call_epilog %{
2486 if( VerifyStackAtCalls ) {
2487 MacroAssembler _masm(&cbuf);
2488 int framesize = ra_->C->frame_slots() << LogBytesPerInt;
2489 Register temp_reg = G3;
2490 __ add(SP, framesize, temp_reg);
2491 __ cmp(temp_reg, FP);
2492 __ breakpoint_trap(Assembler::notEqual, Assembler::ptr_cc);
2493 }
2494 %}
2495
2496 // Long values come back from native calls in O0:O1 in the 32-bit VM, copy the value
2497 // to G1 so the register allocator will not have to deal with the misaligned register
2498 // pair.
2499 enc_class adjust_long_from_native_call %{
2500 #ifndef _LP64
2501 if (returns_long()) {
2502 // sllx O0,32,O0
2503 emit3_simm13( cbuf, Assembler::arith_op, R_O0_enc, Assembler::sllx_op3, R_O0_enc, 0x1020 );
2504 // srl O1,0,O1
2505 emit3_simm13( cbuf, Assembler::arith_op, R_O1_enc, Assembler::srl_op3, R_O1_enc, 0x0000 );
2506 // or O0,O1,G1
2507 emit3 ( cbuf, Assembler::arith_op, R_G1_enc, Assembler:: or_op3, R_O0_enc, 0, R_O1_enc );
2508 }
2509 #endif
2510 %}
2511
2512 enc_class Java_To_Runtime (method meth) %{ // CALL Java_To_Runtime
2513 // CALL directly to the runtime
2514 // The user of this is responsible for ensuring that R_L7 is empty (killed).
2515 emit_call_reloc(cbuf, $meth$$method, relocInfo::runtime_call_type,
2516 /*preserve_g2=*/true);
2517 %}
2518
2519 enc_class preserve_SP %{
2520 MacroAssembler _masm(&cbuf);
2521 __ mov(SP, L7_mh_SP_save);
2522 %}
2523
2524 enc_class restore_SP %{
2525 MacroAssembler _masm(&cbuf);
2526 __ mov(L7_mh_SP_save, SP);
2527 %}
2528
2529 enc_class Java_Static_Call (method meth) %{ // JAVA STATIC CALL
2530 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine
2531 // who we intended to call.
2532 if (!_method) {
2533 emit_call_reloc(cbuf, $meth$$method, relocInfo::runtime_call_type);
2534 } else if (_optimized_virtual) {
2535 emit_call_reloc(cbuf, $meth$$method, relocInfo::opt_virtual_call_type);
2536 } else {
2537 emit_call_reloc(cbuf, $meth$$method, relocInfo::static_call_type);
2538 }
2539 if (_method) { // Emit stub for static call.
2540 CompiledStaticCall::emit_to_interp_stub(cbuf);
2541 }
2542 %}
2543
2544 enc_class Java_Dynamic_Call (method meth) %{ // JAVA DYNAMIC CALL
2545 MacroAssembler _masm(&cbuf);
2546 __ set_inst_mark();
2547 int vtable_index = this->_vtable_index;
2548 // MachCallDynamicJavaNode::ret_addr_offset uses this same test
2549 if (vtable_index < 0) {
2550 // must be invalid_vtable_index, not nonvirtual_vtable_index
2551 assert(vtable_index == Method::invalid_vtable_index, "correct sentinel value");
2552 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode());
2553 assert(G5_ic_reg == G5_inline_cache_reg, "G5_inline_cache_reg used in assemble_ic_buffer_code()");
2554 assert(G5_ic_reg == G5_megamorphic_method, "G5_megamorphic_method used in megamorphic call stub");
2555 __ ic_call((address)$meth$$method);
2556 } else {
2557 assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
2558 // Just go thru the vtable
2559 // get receiver klass (receiver already checked for non-null)
2560 // If we end up going thru a c2i adapter interpreter expects method in G5
2561 int off = __ offset();
2562 __ load_klass(O0, G3_scratch);
2563 int klass_load_size;
2564 if (UseCompressedKlassPointers) {
2565 assert(Universe::heap() != NULL, "java heap should be initialized");
2566 if (Universe::narrow_klass_base() == NULL)
2567 klass_load_size = 2*BytesPerInstWord;
2568 else
2569 klass_load_size = 3*BytesPerInstWord;
2570 } else {
2571 klass_load_size = 1*BytesPerInstWord;
2572 }
2573 int entry_offset = InstanceKlass::vtable_start_offset() + vtable_index*vtableEntry::size();
2574 int v_off = entry_offset*wordSize + vtableEntry::method_offset_in_bytes();
2575 if (Assembler::is_simm13(v_off)) {
2576 __ ld_ptr(G3, v_off, G5_method);
2577 } else {
2578 // Generate 2 instructions
2579 __ Assembler::sethi(v_off & ~0x3ff, G5_method);
2580 __ or3(G5_method, v_off & 0x3ff, G5_method);
2581 // ld_ptr, set_hi, set
2582 assert(__ offset() - off == klass_load_size + 2*BytesPerInstWord,
2583 "Unexpected instruction size(s)");
2584 __ ld_ptr(G3, G5_method, G5_method);
2585 }
2586 // NOTE: for vtable dispatches, the vtable entry will never be null.
2587 // However it may very well end up in handle_wrong_method if the
2588 // method is abstract for the particular class.
2589 __ ld_ptr(G5_method, in_bytes(Method::from_compiled_offset()), G3_scratch);
2590 // jump to target (either compiled code or c2iadapter)
2591 __ jmpl(G3_scratch, G0, O7);
2592 __ delayed()->nop();
2593 }
2594 %}
2595
2596 enc_class Java_Compiled_Call (method meth) %{ // JAVA COMPILED CALL
2597 MacroAssembler _masm(&cbuf);
2598
2599 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode());
2600 Register temp_reg = G3; // caller must kill G3! We cannot reuse G5_ic_reg here because
2601 // we might be calling a C2I adapter which needs it.
2602
2603 assert(temp_reg != G5_ic_reg, "conflicting registers");
2604 // Load nmethod
2605 __ ld_ptr(G5_ic_reg, in_bytes(Method::from_compiled_offset()), temp_reg);
2606
2607 // CALL to compiled java, indirect the contents of G3
2608 __ set_inst_mark();
2609 __ callr(temp_reg, G0);
2610 __ delayed()->nop();
2611 %}
2612
2613 enc_class idiv_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst) %{
2614 MacroAssembler _masm(&cbuf);
2615 Register Rdividend = reg_to_register_object($src1$$reg);
2616 Register Rdivisor = reg_to_register_object($src2$$reg);
2617 Register Rresult = reg_to_register_object($dst$$reg);
2618
2619 __ sra(Rdivisor, 0, Rdivisor);
2620 __ sra(Rdividend, 0, Rdividend);
2621 __ sdivx(Rdividend, Rdivisor, Rresult);
2622 %}
2623
2624 enc_class idiv_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst) %{
2625 MacroAssembler _masm(&cbuf);
2626
2627 Register Rdividend = reg_to_register_object($src1$$reg);
2628 int divisor = $imm$$constant;
2629 Register Rresult = reg_to_register_object($dst$$reg);
2630
2631 __ sra(Rdividend, 0, Rdividend);
2632 __ sdivx(Rdividend, divisor, Rresult);
2633 %}
2634
2635 enc_class enc_mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2) %{
2636 MacroAssembler _masm(&cbuf);
2637 Register Rsrc1 = reg_to_register_object($src1$$reg);
2638 Register Rsrc2 = reg_to_register_object($src2$$reg);
2639 Register Rdst = reg_to_register_object($dst$$reg);
2640
2641 __ sra( Rsrc1, 0, Rsrc1 );
2642 __ sra( Rsrc2, 0, Rsrc2 );
2643 __ mulx( Rsrc1, Rsrc2, Rdst );
2644 __ srlx( Rdst, 32, Rdst );
2645 %}
2646
2647 enc_class irem_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst, o7RegL scratch) %{
2648 MacroAssembler _masm(&cbuf);
2649 Register Rdividend = reg_to_register_object($src1$$reg);
2650 Register Rdivisor = reg_to_register_object($src2$$reg);
2651 Register Rresult = reg_to_register_object($dst$$reg);
2652 Register Rscratch = reg_to_register_object($scratch$$reg);
2653
2654 assert(Rdividend != Rscratch, "");
2655 assert(Rdivisor != Rscratch, "");
2656
2657 __ sra(Rdividend, 0, Rdividend);
2658 __ sra(Rdivisor, 0, Rdivisor);
2659 __ sdivx(Rdividend, Rdivisor, Rscratch);
2660 __ mulx(Rscratch, Rdivisor, Rscratch);
2661 __ sub(Rdividend, Rscratch, Rresult);
2662 %}
2663
2664 enc_class irem_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst, o7RegL scratch) %{
2665 MacroAssembler _masm(&cbuf);
2666
2667 Register Rdividend = reg_to_register_object($src1$$reg);
2668 int divisor = $imm$$constant;
2669 Register Rresult = reg_to_register_object($dst$$reg);
2670 Register Rscratch = reg_to_register_object($scratch$$reg);
2671
2672 assert(Rdividend != Rscratch, "");
2673
2674 __ sra(Rdividend, 0, Rdividend);
2675 __ sdivx(Rdividend, divisor, Rscratch);
2676 __ mulx(Rscratch, divisor, Rscratch);
2677 __ sub(Rdividend, Rscratch, Rresult);
2678 %}
2679
2680 enc_class fabss (sflt_reg dst, sflt_reg src) %{
2681 MacroAssembler _masm(&cbuf);
2682
2683 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg);
2684 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg);
2685
2686 __ fabs(FloatRegisterImpl::S, Fsrc, Fdst);
2687 %}
2688
2689 enc_class fabsd (dflt_reg dst, dflt_reg src) %{
2690 MacroAssembler _masm(&cbuf);
2691
2692 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2693 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2694
2695 __ fabs(FloatRegisterImpl::D, Fsrc, Fdst);
2696 %}
2697
2698 enc_class fnegd (dflt_reg dst, dflt_reg src) %{
2699 MacroAssembler _masm(&cbuf);
2700
2701 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2702 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2703
2704 __ fneg(FloatRegisterImpl::D, Fsrc, Fdst);
2705 %}
2706
2707 enc_class fsqrts (sflt_reg dst, sflt_reg src) %{
2708 MacroAssembler _masm(&cbuf);
2709
2710 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg);
2711 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg);
2712
2713 __ fsqrt(FloatRegisterImpl::S, Fsrc, Fdst);
2714 %}
2715
2716 enc_class fsqrtd (dflt_reg dst, dflt_reg src) %{
2717 MacroAssembler _masm(&cbuf);
2718
2719 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2720 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2721
2722 __ fsqrt(FloatRegisterImpl::D, Fsrc, Fdst);
2723 %}
2724
2725 enc_class fmovs (dflt_reg dst, dflt_reg src) %{
2726 MacroAssembler _masm(&cbuf);
2727
2728 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg);
2729 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg);
2730
2731 __ fmov(FloatRegisterImpl::S, Fsrc, Fdst);
2732 %}
2733
2734 enc_class fmovd (dflt_reg dst, dflt_reg src) %{
2735 MacroAssembler _masm(&cbuf);
2736
2737 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2738 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2739
2740 __ fmov(FloatRegisterImpl::D, Fsrc, Fdst);
2741 %}
2742
2743 enc_class Fast_Lock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{
2744 MacroAssembler _masm(&cbuf);
2745
2746 Register Roop = reg_to_register_object($oop$$reg);
2747 Register Rbox = reg_to_register_object($box$$reg);
2748 Register Rscratch = reg_to_register_object($scratch$$reg);
2749 Register Rmark = reg_to_register_object($scratch2$$reg);
2750
2751 assert(Roop != Rscratch, "");
2752 assert(Roop != Rmark, "");
2753 assert(Rbox != Rscratch, "");
2754 assert(Rbox != Rmark, "");
2755
2756 __ compiler_lock_object(Roop, Rmark, Rbox, Rscratch, _counters, UseBiasedLocking && !UseOptoBiasInlining);
2757 %}
2758
2759 enc_class Fast_Unlock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{
2760 MacroAssembler _masm(&cbuf);
2761
2762 Register Roop = reg_to_register_object($oop$$reg);
2763 Register Rbox = reg_to_register_object($box$$reg);
2764 Register Rscratch = reg_to_register_object($scratch$$reg);
2765 Register Rmark = reg_to_register_object($scratch2$$reg);
2766
2767 assert(Roop != Rscratch, "");
2768 assert(Roop != Rmark, "");
2769 assert(Rbox != Rscratch, "");
2770 assert(Rbox != Rmark, "");
2771
2772 __ compiler_unlock_object(Roop, Rmark, Rbox, Rscratch, UseBiasedLocking && !UseOptoBiasInlining);
2773 %}
2774
2775 enc_class enc_cas( iRegP mem, iRegP old, iRegP new ) %{
2776 MacroAssembler _masm(&cbuf);
2777 Register Rmem = reg_to_register_object($mem$$reg);
2778 Register Rold = reg_to_register_object($old$$reg);
2779 Register Rnew = reg_to_register_object($new$$reg);
2780
2781 __ cas_ptr(Rmem, Rold, Rnew); // Swap(*Rmem,Rnew) if *Rmem == Rold
2782 __ cmp( Rold, Rnew );
2783 %}
2784
2785 enc_class enc_casx( iRegP mem, iRegL old, iRegL new) %{
2786 Register Rmem = reg_to_register_object($mem$$reg);
2787 Register Rold = reg_to_register_object($old$$reg);
2788 Register Rnew = reg_to_register_object($new$$reg);
2789
2790 MacroAssembler _masm(&cbuf);
2791 __ mov(Rnew, O7);
2792 __ casx(Rmem, Rold, O7);
2793 __ cmp( Rold, O7 );
2794 %}
2795
2796 // raw int cas, used for compareAndSwap
2797 enc_class enc_casi( iRegP mem, iRegL old, iRegL new) %{
2798 Register Rmem = reg_to_register_object($mem$$reg);
2799 Register Rold = reg_to_register_object($old$$reg);
2800 Register Rnew = reg_to_register_object($new$$reg);
2801
2802 MacroAssembler _masm(&cbuf);
2803 __ mov(Rnew, O7);
2804 __ cas(Rmem, Rold, O7);
2805 __ cmp( Rold, O7 );
2806 %}
2807
2808 enc_class enc_lflags_ne_to_boolean( iRegI res ) %{
2809 Register Rres = reg_to_register_object($res$$reg);
2810
2811 MacroAssembler _masm(&cbuf);
2812 __ mov(1, Rres);
2813 __ movcc( Assembler::notEqual, false, Assembler::xcc, G0, Rres );
2814 %}
2815
2816 enc_class enc_iflags_ne_to_boolean( iRegI res ) %{
2817 Register Rres = reg_to_register_object($res$$reg);
2818
2819 MacroAssembler _masm(&cbuf);
2820 __ mov(1, Rres);
2821 __ movcc( Assembler::notEqual, false, Assembler::icc, G0, Rres );
2822 %}
2823
2824 enc_class floating_cmp ( iRegP dst, regF src1, regF src2 ) %{
2825 MacroAssembler _masm(&cbuf);
2826 Register Rdst = reg_to_register_object($dst$$reg);
2827 FloatRegister Fsrc1 = $primary ? reg_to_SingleFloatRegister_object($src1$$reg)
2828 : reg_to_DoubleFloatRegister_object($src1$$reg);
2829 FloatRegister Fsrc2 = $primary ? reg_to_SingleFloatRegister_object($src2$$reg)
2830 : reg_to_DoubleFloatRegister_object($src2$$reg);
2831
2832 // Convert condition code fcc0 into -1,0,1; unordered reports less-than (-1)
2833 __ float_cmp( $primary, -1, Fsrc1, Fsrc2, Rdst);
2834 %}
2835
2836
2837 enc_class enc_String_Compare(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result) %{
2838 Label Ldone, Lloop;
2839 MacroAssembler _masm(&cbuf);
2840
2841 Register str1_reg = reg_to_register_object($str1$$reg);
2842 Register str2_reg = reg_to_register_object($str2$$reg);
2843 Register cnt1_reg = reg_to_register_object($cnt1$$reg);
2844 Register cnt2_reg = reg_to_register_object($cnt2$$reg);
2845 Register result_reg = reg_to_register_object($result$$reg);
2846
2847 assert(result_reg != str1_reg &&
2848 result_reg != str2_reg &&
2849 result_reg != cnt1_reg &&
2850 result_reg != cnt2_reg ,
2851 "need different registers");
2852
2853 // Compute the minimum of the string lengths(str1_reg) and the
2854 // difference of the string lengths (stack)
2855
2856 // See if the lengths are different, and calculate min in str1_reg.
2857 // Stash diff in O7 in case we need it for a tie-breaker.
2858 Label Lskip;
2859 __ subcc(cnt1_reg, cnt2_reg, O7);
2860 __ sll(cnt1_reg, exact_log2(sizeof(jchar)), cnt1_reg); // scale the limit
2861 __ br(Assembler::greater, true, Assembler::pt, Lskip);
2862 // cnt2 is shorter, so use its count:
2863 __ delayed()->sll(cnt2_reg, exact_log2(sizeof(jchar)), cnt1_reg); // scale the limit
2864 __ bind(Lskip);
2865
2866 // reallocate cnt1_reg, cnt2_reg, result_reg
2867 // Note: limit_reg holds the string length pre-scaled by 2
2868 Register limit_reg = cnt1_reg;
2869 Register chr2_reg = cnt2_reg;
2870 Register chr1_reg = result_reg;
2871 // str{12} are the base pointers
2872
2873 // Is the minimum length zero?
2874 __ cmp(limit_reg, (int)(0 * sizeof(jchar))); // use cast to resolve overloading ambiguity
2875 __ br(Assembler::equal, true, Assembler::pn, Ldone);
2876 __ delayed()->mov(O7, result_reg); // result is difference in lengths
2877
2878 // Load first characters
2879 __ lduh(str1_reg, 0, chr1_reg);
2880 __ lduh(str2_reg, 0, chr2_reg);
2881
2882 // Compare first characters
2883 __ subcc(chr1_reg, chr2_reg, chr1_reg);
2884 __ br(Assembler::notZero, false, Assembler::pt, Ldone);
2885 assert(chr1_reg == result_reg, "result must be pre-placed");
2886 __ delayed()->nop();
2887
2888 {
2889 // Check after comparing first character to see if strings are equivalent
2890 Label LSkip2;
2891 // Check if the strings start at same location
2892 __ cmp(str1_reg, str2_reg);
2893 __ brx(Assembler::notEqual, true, Assembler::pt, LSkip2);
2894 __ delayed()->nop();
2895
2896 // Check if the length difference is zero (in O7)
2897 __ cmp(G0, O7);
2898 __ br(Assembler::equal, true, Assembler::pn, Ldone);
2899 __ delayed()->mov(G0, result_reg); // result is zero
2900
2901 // Strings might not be equal
2902 __ bind(LSkip2);
2903 }
2904
2905 __ subcc(limit_reg, 1 * sizeof(jchar), chr1_reg);
2906 __ br(Assembler::equal, true, Assembler::pn, Ldone);
2907 __ delayed()->mov(O7, result_reg); // result is difference in lengths
2908
2909 // Shift str1_reg and str2_reg to the end of the arrays, negate limit
2910 __ add(str1_reg, limit_reg, str1_reg);
2911 __ add(str2_reg, limit_reg, str2_reg);
2912 __ neg(chr1_reg, limit_reg); // limit = -(limit-2)
2913
2914 // Compare the rest of the characters
2915 __ lduh(str1_reg, limit_reg, chr1_reg);
2916 __ bind(Lloop);
2917 // __ lduh(str1_reg, limit_reg, chr1_reg); // hoisted
2918 __ lduh(str2_reg, limit_reg, chr2_reg);
2919 __ subcc(chr1_reg, chr2_reg, chr1_reg);
2920 __ br(Assembler::notZero, false, Assembler::pt, Ldone);
2921 assert(chr1_reg == result_reg, "result must be pre-placed");
2922 __ delayed()->inccc(limit_reg, sizeof(jchar));
2923 // annul LDUH if branch is not taken to prevent access past end of string
2924 __ br(Assembler::notZero, true, Assembler::pt, Lloop);
2925 __ delayed()->lduh(str1_reg, limit_reg, chr1_reg); // hoisted
2926
2927 // If strings are equal up to min length, return the length difference.
2928 __ mov(O7, result_reg);
2929
2930 // Otherwise, return the difference between the first mismatched chars.
2931 __ bind(Ldone);
2932 %}
2933
2934 enc_class enc_String_Equals(o0RegP str1, o1RegP str2, g3RegI cnt, notemp_iRegI result) %{
2935 Label Lword_loop, Lpost_word, Lchar, Lchar_loop, Ldone;
2936 MacroAssembler _masm(&cbuf);
2937
2938 Register str1_reg = reg_to_register_object($str1$$reg);
2939 Register str2_reg = reg_to_register_object($str2$$reg);
2940 Register cnt_reg = reg_to_register_object($cnt$$reg);
2941 Register tmp1_reg = O7;
2942 Register result_reg = reg_to_register_object($result$$reg);
2943
2944 assert(result_reg != str1_reg &&
2945 result_reg != str2_reg &&
2946 result_reg != cnt_reg &&
2947 result_reg != tmp1_reg ,
2948 "need different registers");
2949
2950 __ cmp(str1_reg, str2_reg); //same char[] ?
2951 __ brx(Assembler::equal, true, Assembler::pn, Ldone);
2952 __ delayed()->add(G0, 1, result_reg);
2953
2954 __ cmp_zero_and_br(Assembler::zero, cnt_reg, Ldone, true, Assembler::pn);
2955 __ delayed()->add(G0, 1, result_reg); // count == 0
2956
2957 //rename registers
2958 Register limit_reg = cnt_reg;
2959 Register chr1_reg = result_reg;
2960 Register chr2_reg = tmp1_reg;
2961
2962 //check for alignment and position the pointers to the ends
2963 __ or3(str1_reg, str2_reg, chr1_reg);
2964 __ andcc(chr1_reg, 0x3, chr1_reg);
2965 // notZero means at least one not 4-byte aligned.
2966 // We could optimize the case when both arrays are not aligned
2967 // but it is not frequent case and it requires additional checks.
2968 __ br(Assembler::notZero, false, Assembler::pn, Lchar); // char by char compare
2969 __ delayed()->sll(limit_reg, exact_log2(sizeof(jchar)), limit_reg); // set byte count
2970
2971 // Compare char[] arrays aligned to 4 bytes.
2972 __ char_arrays_equals(str1_reg, str2_reg, limit_reg, result_reg,
2973 chr1_reg, chr2_reg, Ldone);
2974 __ ba(Ldone);
2975 __ delayed()->add(G0, 1, result_reg);
2976
2977 // char by char compare
2978 __ bind(Lchar);
2979 __ add(str1_reg, limit_reg, str1_reg);
2980 __ add(str2_reg, limit_reg, str2_reg);
2981 __ neg(limit_reg); //negate count
2982
2983 __ lduh(str1_reg, limit_reg, chr1_reg);
2984 // Lchar_loop
2985 __ bind(Lchar_loop);
2986 __ lduh(str2_reg, limit_reg, chr2_reg);
2987 __ cmp(chr1_reg, chr2_reg);
2988 __ br(Assembler::notEqual, true, Assembler::pt, Ldone);
2989 __ delayed()->mov(G0, result_reg); //not equal
2990 __ inccc(limit_reg, sizeof(jchar));
2991 // annul LDUH if branch is not taken to prevent access past end of string
2992 __ br(Assembler::notZero, true, Assembler::pt, Lchar_loop);
2993 __ delayed()->lduh(str1_reg, limit_reg, chr1_reg); // hoisted
2994
2995 __ add(G0, 1, result_reg); //equal
2996
2997 __ bind(Ldone);
2998 %}
2999
3000 enc_class enc_Array_Equals(o0RegP ary1, o1RegP ary2, g3RegP tmp1, notemp_iRegI result) %{
3001 Label Lvector, Ldone, Lloop;
3002 MacroAssembler _masm(&cbuf);
3003
3004 Register ary1_reg = reg_to_register_object($ary1$$reg);
3005 Register ary2_reg = reg_to_register_object($ary2$$reg);
3006 Register tmp1_reg = reg_to_register_object($tmp1$$reg);
3007 Register tmp2_reg = O7;
3008 Register result_reg = reg_to_register_object($result$$reg);
3009
3010 int length_offset = arrayOopDesc::length_offset_in_bytes();
3011 int base_offset = arrayOopDesc::base_offset_in_bytes(T_CHAR);
3012
3013 // return true if the same array
3014 __ cmp(ary1_reg, ary2_reg);
3015 __ brx(Assembler::equal, true, Assembler::pn, Ldone);
3016 __ delayed()->add(G0, 1, result_reg); // equal
3017
3018 __ br_null(ary1_reg, true, Assembler::pn, Ldone);
3019 __ delayed()->mov(G0, result_reg); // not equal
3020
3021 __ br_null(ary2_reg, true, Assembler::pn, Ldone);
3022 __ delayed()->mov(G0, result_reg); // not equal
3023
3024 //load the lengths of arrays
3025 __ ld(Address(ary1_reg, length_offset), tmp1_reg);
3026 __ ld(Address(ary2_reg, length_offset), tmp2_reg);
3027
3028 // return false if the two arrays are not equal length
3029 __ cmp(tmp1_reg, tmp2_reg);
3030 __ br(Assembler::notEqual, true, Assembler::pn, Ldone);
3031 __ delayed()->mov(G0, result_reg); // not equal
3032
3033 __ cmp_zero_and_br(Assembler::zero, tmp1_reg, Ldone, true, Assembler::pn);
3034 __ delayed()->add(G0, 1, result_reg); // zero-length arrays are equal
3035
3036 // load array addresses
3037 __ add(ary1_reg, base_offset, ary1_reg);
3038 __ add(ary2_reg, base_offset, ary2_reg);
3039
3040 // renaming registers
3041 Register chr1_reg = result_reg; // for characters in ary1
3042 Register chr2_reg = tmp2_reg; // for characters in ary2
3043 Register limit_reg = tmp1_reg; // length
3044
3045 // set byte count
3046 __ sll(limit_reg, exact_log2(sizeof(jchar)), limit_reg);
3047
3048 // Compare char[] arrays aligned to 4 bytes.
3049 __ char_arrays_equals(ary1_reg, ary2_reg, limit_reg, result_reg,
3050 chr1_reg, chr2_reg, Ldone);
3051 __ add(G0, 1, result_reg); // equals
3052
3053 __ bind(Ldone);
3054 %}
3055
3056 enc_class enc_rethrow() %{
3057 cbuf.set_insts_mark();
3058 Register temp_reg = G3;
3059 AddressLiteral rethrow_stub(OptoRuntime::rethrow_stub());
3060 assert(temp_reg != reg_to_register_object(R_I0_num), "temp must not break oop_reg");
3061 MacroAssembler _masm(&cbuf);
3062 #ifdef ASSERT
3063 __ save_frame(0);
3064 AddressLiteral last_rethrow_addrlit(&last_rethrow);
3065 __ sethi(last_rethrow_addrlit, L1);
3066 Address addr(L1, last_rethrow_addrlit.low10());
3067 __ rdpc(L2);
3068 __ inc(L2, 3 * BytesPerInstWord); // skip this & 2 more insns to point at jump_to
3069 __ st_ptr(L2, addr);
3070 __ restore();
3071 #endif
3072 __ JUMP(rethrow_stub, temp_reg, 0); // sethi;jmp
3073 __ delayed()->nop();
3074 %}
3075
3076 enc_class emit_mem_nop() %{
3077 // Generates the instruction LDUXA [o6,g0],#0x82,g0
3078 cbuf.insts()->emit_int32((unsigned int) 0xc0839040);
3079 %}
3080
3081 enc_class emit_fadd_nop() %{
3082 // Generates the instruction FMOVS f31,f31
3083 cbuf.insts()->emit_int32((unsigned int) 0xbfa0003f);
3084 %}
3085
3086 enc_class emit_br_nop() %{
3087 // Generates the instruction BPN,PN .
3088 cbuf.insts()->emit_int32((unsigned int) 0x00400000);
3089 %}
3090
3091 enc_class enc_membar_acquire %{
3092 MacroAssembler _masm(&cbuf);
3093 __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::LoadLoad) );
3094 %}
3095
3096 enc_class enc_membar_release %{
3097 MacroAssembler _masm(&cbuf);
3098 __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::StoreStore) );
3099 %}
3100
3101 enc_class enc_membar_volatile %{
3102 MacroAssembler _masm(&cbuf);
3103 __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad) );
3104 %}
3105
3106 %}
3107
3108 //----------FRAME--------------------------------------------------------------
3109 // Definition of frame structure and management information.
3110 //
3111 // S T A C K L A Y O U T Allocators stack-slot number
3112 // | (to get allocators register number
3113 // G Owned by | | v add VMRegImpl::stack0)
3114 // r CALLER | |
3115 // o | +--------+ pad to even-align allocators stack-slot
3116 // w V | pad0 | numbers; owned by CALLER
3117 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned
3118 // h ^ | in | 5
3119 // | | args | 4 Holes in incoming args owned by SELF
3120 // | | | | 3
3121 // | | +--------+
3122 // V | | old out| Empty on Intel, window on Sparc
3123 // | old |preserve| Must be even aligned.
3124 // | SP-+--------+----> Matcher::_old_SP, 8 (or 16 in LP64)-byte aligned
3125 // | | in | 3 area for Intel ret address
3126 // Owned by |preserve| Empty on Sparc.
3127 // SELF +--------+
3128 // | | pad2 | 2 pad to align old SP
3129 // | +--------+ 1
3130 // | | locks | 0
3131 // | +--------+----> VMRegImpl::stack0, 8 (or 16 in LP64)-byte aligned
3132 // | | pad1 | 11 pad to align new SP
3133 // | +--------+
3134 // | | | 10
3135 // | | spills | 9 spills
3136 // V | | 8 (pad0 slot for callee)
3137 // -----------+--------+----> Matcher::_out_arg_limit, unaligned
3138 // ^ | out | 7
3139 // | | args | 6 Holes in outgoing args owned by CALLEE
3140 // Owned by +--------+
3141 // CALLEE | new out| 6 Empty on Intel, window on Sparc
3142 // | new |preserve| Must be even-aligned.
3143 // | SP-+--------+----> Matcher::_new_SP, even aligned
3144 // | | |
3145 //
3146 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is
3147 // known from SELF's arguments and the Java calling convention.
3148 // Region 6-7 is determined per call site.
3149 // Note 2: If the calling convention leaves holes in the incoming argument
3150 // area, those holes are owned by SELF. Holes in the outgoing area
3151 // are owned by the CALLEE. Holes should not be nessecary in the
3152 // incoming area, as the Java calling convention is completely under
3153 // the control of the AD file. Doubles can be sorted and packed to
3154 // avoid holes. Holes in the outgoing arguments may be nessecary for
3155 // varargs C calling conventions.
3156 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is
3157 // even aligned with pad0 as needed.
3158 // Region 6 is even aligned. Region 6-7 is NOT even aligned;
3159 // region 6-11 is even aligned; it may be padded out more so that
3160 // the region from SP to FP meets the minimum stack alignment.
3161
3162 frame %{
3163 // What direction does stack grow in (assumed to be same for native & Java)
3164 stack_direction(TOWARDS_LOW);
3165
3166 // These two registers define part of the calling convention
3167 // between compiled code and the interpreter.
3168 inline_cache_reg(R_G5); // Inline Cache Register or Method* for I2C
3169 interpreter_method_oop_reg(R_G5); // Method Oop Register when calling interpreter
3170
3171 // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset]
3172 cisc_spilling_operand_name(indOffset);
3173
3174 // Number of stack slots consumed by a Monitor enter
3175 #ifdef _LP64
3176 sync_stack_slots(2);
3177 #else
3178 sync_stack_slots(1);
3179 #endif
3180
3181 // Compiled code's Frame Pointer
3182 frame_pointer(R_SP);
3183
3184 // Stack alignment requirement
3185 stack_alignment(StackAlignmentInBytes);
3186 // LP64: Alignment size in bytes (128-bit -> 16 bytes)
3187 // !LP64: Alignment size in bytes (64-bit -> 8 bytes)
3188
3189 // Number of stack slots between incoming argument block and the start of
3190 // a new frame. The PROLOG must add this many slots to the stack. The
3191 // EPILOG must remove this many slots.
3192 in_preserve_stack_slots(0);
3193
3194 // Number of outgoing stack slots killed above the out_preserve_stack_slots
3195 // for calls to C. Supports the var-args backing area for register parms.
3196 // ADLC doesn't support parsing expressions, so I folded the math by hand.
3197 #ifdef _LP64
3198 // (callee_register_argument_save_area_words (6) + callee_aggregate_return_pointer_words (0)) * 2-stack-slots-per-word
3199 varargs_C_out_slots_killed(12);
3200 #else
3201 // (callee_register_argument_save_area_words (6) + callee_aggregate_return_pointer_words (1)) * 1-stack-slots-per-word
3202 varargs_C_out_slots_killed( 7);
3203 #endif
3204
3205 // The after-PROLOG location of the return address. Location of
3206 // return address specifies a type (REG or STACK) and a number
3207 // representing the register number (i.e. - use a register name) or
3208 // stack slot.
3209 return_addr(REG R_I7); // Ret Addr is in register I7
3210
3211 // Body of function which returns an OptoRegs array locating
3212 // arguments either in registers or in stack slots for calling
3213 // java
3214 calling_convention %{
3215 (void) SharedRuntime::java_calling_convention(sig_bt, regs, length, is_outgoing);
3216
3217 %}
3218
3219 // Body of function which returns an OptoRegs array locating
3220 // arguments either in registers or in stack slots for callin
3221 // C.
3222 c_calling_convention %{
3223 // This is obviously always outgoing
3224 (void) SharedRuntime::c_calling_convention(sig_bt, regs, length);
3225 %}
3226
3227 // Location of native (C/C++) and interpreter return values. This is specified to
3228 // be the same as Java. In the 32-bit VM, long values are actually returned from
3229 // native calls in O0:O1 and returned to the interpreter in I0:I1. The copying
3230 // to and from the register pairs is done by the appropriate call and epilog
3231 // opcodes. This simplifies the register allocator.
3232 c_return_value %{
3233 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
3234 #ifdef _LP64
3235 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_O0_num };
3236 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num, OptoReg::Bad, R_F1_num, R_O0H_num};
3237 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_I0_num };
3238 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num, OptoReg::Bad, R_F1_num, R_I0H_num};
3239 #else // !_LP64
3240 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_G1_num };
3241 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num };
3242 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_G1_num };
3243 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num };
3244 #endif
3245 return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg],
3246 (is_outgoing?lo_out:lo_in)[ideal_reg] );
3247 %}
3248
3249 // Location of compiled Java return values. Same as C
3250 return_value %{
3251 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
3252 #ifdef _LP64
3253 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_O0_num };
3254 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num, OptoReg::Bad, R_F1_num, R_O0H_num};
3255 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_I0_num };
3256 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num, OptoReg::Bad, R_F1_num, R_I0H_num};
3257 #else // !_LP64
3258 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_G1_num };
3259 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num};
3260 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_G1_num };
3261 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num};
3262 #endif
3263 return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg],
3264 (is_outgoing?lo_out:lo_in)[ideal_reg] );
3265 %}
3266
3267 %}
3268
3269
3270 //----------ATTRIBUTES---------------------------------------------------------
3271 //----------Operand Attributes-------------------------------------------------
3272 op_attrib op_cost(1); // Required cost attribute
3273
3274 //----------Instruction Attributes---------------------------------------------
3275 ins_attrib ins_cost(DEFAULT_COST); // Required cost attribute
3276 ins_attrib ins_size(32); // Required size attribute (in bits)
3277 ins_attrib ins_avoid_back_to_back(0); // instruction should not be generated back to back
3278 ins_attrib ins_short_branch(0); // Required flag: is this instruction a
3279 // non-matching short branch variant of some
3280 // long branch?
3281
3282 //----------OPERANDS-----------------------------------------------------------
3283 // Operand definitions must precede instruction definitions for correct parsing
3284 // in the ADLC because operands constitute user defined types which are used in
3285 // instruction definitions.
3286
3287 //----------Simple Operands----------------------------------------------------
3288 // Immediate Operands
3289 // Integer Immediate: 32-bit
3290 operand immI() %{
3291 match(ConI);
3292
3293 op_cost(0);
3294 // formats are generated automatically for constants and base registers
3295 format %{ %}
3296 interface(CONST_INTER);
3297 %}
3298
3299 // Integer Immediate: 8-bit
3300 operand immI8() %{
3301 predicate(Assembler::is_simm8(n->get_int()));
3302 match(ConI);
3303 op_cost(0);
3304 format %{ %}
3305 interface(CONST_INTER);
3306 %}
3307
3308 // Integer Immediate: 13-bit
3309 operand immI13() %{
3310 predicate(Assembler::is_simm13(n->get_int()));
3311 match(ConI);
3312 op_cost(0);
3313
3314 format %{ %}
3315 interface(CONST_INTER);
3316 %}
3317
3318 // Integer Immediate: 13-bit minus 7
3319 operand immI13m7() %{
3320 predicate((-4096 < n->get_int()) && ((n->get_int() + 7) <= 4095));
3321 match(ConI);
3322 op_cost(0);
3323
3324 format %{ %}
3325 interface(CONST_INTER);
3326 %}
3327
3328 // Integer Immediate: 16-bit
3329 operand immI16() %{
3330 predicate(Assembler::is_simm16(n->get_int()));
3331 match(ConI);
3332 op_cost(0);
3333 format %{ %}
3334 interface(CONST_INTER);
3335 %}
3336
3337 // Unsigned (positive) Integer Immediate: 13-bit
3338 operand immU13() %{
3339 predicate((0 <= n->get_int()) && Assembler::is_simm13(n->get_int()));
3340 match(ConI);
3341 op_cost(0);
3342
3343 format %{ %}
3344 interface(CONST_INTER);
3345 %}
3346
3347 // Integer Immediate: 6-bit
3348 operand immU6() %{
3349 predicate(n->get_int() >= 0 && n->get_int() <= 63);
3350 match(ConI);
3351 op_cost(0);
3352 format %{ %}
3353 interface(CONST_INTER);
3354 %}
3355
3356 // Integer Immediate: 11-bit
3357 operand immI11() %{
3358 predicate(Assembler::is_simm11(n->get_int()));
3359 match(ConI);
3360 op_cost(0);
3361 format %{ %}
3362 interface(CONST_INTER);
3363 %}
3364
3365 // Integer Immediate: 5-bit
3366 operand immI5() %{
3367 predicate(Assembler::is_simm5(n->get_int()));
3368 match(ConI);
3369 op_cost(0);
3370 format %{ %}
3371 interface(CONST_INTER);
3372 %}
3373
3374 // Integer Immediate: 0-bit
3375 operand immI0() %{
3376 predicate(n->get_int() == 0);
3377 match(ConI);
3378 op_cost(0);
3379
3380 format %{ %}
3381 interface(CONST_INTER);
3382 %}
3383
3384 // Integer Immediate: the value 10
3385 operand immI10() %{
3386 predicate(n->get_int() == 10);
3387 match(ConI);
3388 op_cost(0);
3389
3390 format %{ %}
3391 interface(CONST_INTER);
3392 %}
3393
3394 // Integer Immediate: the values 0-31
3395 operand immU5() %{
3396 predicate(n->get_int() >= 0 && n->get_int() <= 31);
3397 match(ConI);
3398 op_cost(0);
3399
3400 format %{ %}
3401 interface(CONST_INTER);
3402 %}
3403
3404 // Integer Immediate: the values 1-31
3405 operand immI_1_31() %{
3406 predicate(n->get_int() >= 1 && n->get_int() <= 31);
3407 match(ConI);
3408 op_cost(0);
3409
3410 format %{ %}
3411 interface(CONST_INTER);
3412 %}
3413
3414 // Integer Immediate: the values 32-63
3415 operand immI_32_63() %{
3416 predicate(n->get_int() >= 32 && n->get_int() <= 63);
3417 match(ConI);
3418 op_cost(0);
3419
3420 format %{ %}
3421 interface(CONST_INTER);
3422 %}
3423
3424 // Immediates for special shifts (sign extend)
3425
3426 // Integer Immediate: the value 16
3427 operand immI_16() %{
3428 predicate(n->get_int() == 16);
3429 match(ConI);
3430 op_cost(0);
3431
3432 format %{ %}
3433 interface(CONST_INTER);
3434 %}
3435
3436 // Integer Immediate: the value 24
3437 operand immI_24() %{
3438 predicate(n->get_int() == 24);
3439 match(ConI);
3440 op_cost(0);
3441
3442 format %{ %}
3443 interface(CONST_INTER);
3444 %}
3445
3446 // Integer Immediate: the value 255
3447 operand immI_255() %{
3448 predicate( n->get_int() == 255 );
3449 match(ConI);
3450 op_cost(0);
3451
3452 format %{ %}
3453 interface(CONST_INTER);
3454 %}
3455
3456 // Integer Immediate: the value 65535
3457 operand immI_65535() %{
3458 predicate(n->get_int() == 65535);
3459 match(ConI);
3460 op_cost(0);
3461
3462 format %{ %}
3463 interface(CONST_INTER);
3464 %}
3465
3466 // Long Immediate: the value FF
3467 operand immL_FF() %{
3468 predicate( n->get_long() == 0xFFL );
3469 match(ConL);
3470 op_cost(0);
3471
3472 format %{ %}
3473 interface(CONST_INTER);
3474 %}
3475
3476 // Long Immediate: the value FFFF
3477 operand immL_FFFF() %{
3478 predicate( n->get_long() == 0xFFFFL );
3479 match(ConL);
3480 op_cost(0);
3481
3482 format %{ %}
3483 interface(CONST_INTER);
3484 %}
3485
3486 // Pointer Immediate: 32 or 64-bit
3487 operand immP() %{
3488 match(ConP);
3489
3490 op_cost(5);
3491 // formats are generated automatically for constants and base registers
3492 format %{ %}
3493 interface(CONST_INTER);
3494 %}
3495
3496 #ifdef _LP64
3497 // Pointer Immediate: 64-bit
3498 operand immP_set() %{
3499 predicate(!VM_Version::is_niagara_plus());
3500 match(ConP);
3501
3502 op_cost(5);
3503 // formats are generated automatically for constants and base registers
3504 format %{ %}
3505 interface(CONST_INTER);
3506 %}
3507
3508 // Pointer Immediate: 64-bit
3509 // From Niagara2 processors on a load should be better than materializing.
3510 operand immP_load() %{
3511 predicate(VM_Version::is_niagara_plus() && (n->bottom_type()->isa_oop_ptr() || (MacroAssembler::insts_for_set(n->get_ptr()) > 3)));
3512 match(ConP);
3513
3514 op_cost(5);
3515 // formats are generated automatically for constants and base registers
3516 format %{ %}
3517 interface(CONST_INTER);
3518 %}
3519
3520 // Pointer Immediate: 64-bit
3521 operand immP_no_oop_cheap() %{
3522 predicate(VM_Version::is_niagara_plus() && !n->bottom_type()->isa_oop_ptr() && (MacroAssembler::insts_for_set(n->get_ptr()) <= 3));
3523 match(ConP);
3524
3525 op_cost(5);
3526 // formats are generated automatically for constants and base registers
3527 format %{ %}
3528 interface(CONST_INTER);
3529 %}
3530 #endif
3531
3532 operand immP13() %{
3533 predicate((-4096 < n->get_ptr()) && (n->get_ptr() <= 4095));
3534 match(ConP);
3535 op_cost(0);
3536
3537 format %{ %}
3538 interface(CONST_INTER);
3539 %}
3540
3541 operand immP0() %{
3542 predicate(n->get_ptr() == 0);
3543 match(ConP);
3544 op_cost(0);
3545
3546 format %{ %}
3547 interface(CONST_INTER);
3548 %}
3549
3550 operand immP_poll() %{
3551 predicate(n->get_ptr() != 0 && n->get_ptr() == (intptr_t)os::get_polling_page());
3552 match(ConP);
3553
3554 // formats are generated automatically for constants and base registers
3555 format %{ %}
3556 interface(CONST_INTER);
3557 %}
3558
3559 // Pointer Immediate
3560 operand immN()
3561 %{
3562 match(ConN);
3563
3564 op_cost(10);
3565 format %{ %}
3566 interface(CONST_INTER);
3567 %}
3568
3569 operand immNKlass()
3570 %{
3571 match(ConNKlass);
3572
3573 op_cost(10);
3574 format %{ %}
3575 interface(CONST_INTER);
3576 %}
3577
3578 // NULL Pointer Immediate
3579 operand immN0()
3580 %{
3581 predicate(n->get_narrowcon() == 0);
3582 match(ConN);
3583
3584 op_cost(0);
3585 format %{ %}
3586 interface(CONST_INTER);
3587 %}
3588
3589 operand immL() %{
3590 match(ConL);
3591 op_cost(40);
3592 // formats are generated automatically for constants and base registers
3593 format %{ %}
3594 interface(CONST_INTER);
3595 %}
3596
3597 operand immL0() %{
3598 predicate(n->get_long() == 0L);
3599 match(ConL);
3600 op_cost(0);
3601 // formats are generated automatically for constants and base registers
3602 format %{ %}
3603 interface(CONST_INTER);
3604 %}
3605
3606 // Integer Immediate: 5-bit
3607 operand immL5() %{
3608 predicate(n->get_long() == (int)n->get_long() && Assembler::is_simm5((int)n->get_long()));
3609 match(ConL);
3610 op_cost(0);
3611 format %{ %}
3612 interface(CONST_INTER);
3613 %}
3614
3615 // Long Immediate: 13-bit
3616 operand immL13() %{
3617 predicate((-4096L < n->get_long()) && (n->get_long() <= 4095L));
3618 match(ConL);
3619 op_cost(0);
3620
3621 format %{ %}
3622 interface(CONST_INTER);
3623 %}
3624
3625 // Long Immediate: 13-bit minus 7
3626 operand immL13m7() %{
3627 predicate((-4096L < n->get_long()) && ((n->get_long() + 7L) <= 4095L));
3628 match(ConL);
3629 op_cost(0);
3630
3631 format %{ %}
3632 interface(CONST_INTER);
3633 %}
3634
3635 // Long Immediate: low 32-bit mask
3636 operand immL_32bits() %{
3637 predicate(n->get_long() == 0xFFFFFFFFL);
3638 match(ConL);
3639 op_cost(0);
3640
3641 format %{ %}
3642 interface(CONST_INTER);
3643 %}
3644
3645 // Long Immediate: cheap (materialize in <= 3 instructions)
3646 operand immL_cheap() %{
3647 predicate(!VM_Version::is_niagara_plus() || MacroAssembler::insts_for_set64(n->get_long()) <= 3);
3648 match(ConL);
3649 op_cost(0);
3650
3651 format %{ %}
3652 interface(CONST_INTER);
3653 %}
3654
3655 // Long Immediate: expensive (materialize in > 3 instructions)
3656 operand immL_expensive() %{
3657 predicate(VM_Version::is_niagara_plus() && MacroAssembler::insts_for_set64(n->get_long()) > 3);
3658 match(ConL);
3659 op_cost(0);
3660
3661 format %{ %}
3662 interface(CONST_INTER);
3663 %}
3664
3665 // Double Immediate
3666 operand immD() %{
3667 match(ConD);
3668
3669 op_cost(40);
3670 format %{ %}
3671 interface(CONST_INTER);
3672 %}
3673
3674 operand immD0() %{
3675 #ifdef _LP64
3676 // on 64-bit architectures this comparision is faster
3677 predicate(jlong_cast(n->getd()) == 0);
3678 #else
3679 predicate((n->getd() == 0) && (fpclass(n->getd()) == FP_PZERO));
3680 #endif
3681 match(ConD);
3682
3683 op_cost(0);
3684 format %{ %}
3685 interface(CONST_INTER);
3686 %}
3687
3688 // Float Immediate
3689 operand immF() %{
3690 match(ConF);
3691
3692 op_cost(20);
3693 format %{ %}
3694 interface(CONST_INTER);
3695 %}
3696
3697 // Float Immediate: 0
3698 operand immF0() %{
3699 predicate((n->getf() == 0) && (fpclass(n->getf()) == FP_PZERO));
3700 match(ConF);
3701
3702 op_cost(0);
3703 format %{ %}
3704 interface(CONST_INTER);
3705 %}
3706
3707 // Integer Register Operands
3708 // Integer Register
3709 operand iRegI() %{
3710 constraint(ALLOC_IN_RC(int_reg));
3711 match(RegI);
3712
3713 match(notemp_iRegI);
3714 match(g1RegI);
3715 match(o0RegI);
3716 match(iRegIsafe);
3717
3718 format %{ %}
3719 interface(REG_INTER);
3720 %}
3721
3722 operand notemp_iRegI() %{
3723 constraint(ALLOC_IN_RC(notemp_int_reg));
3724 match(RegI);
3725
3726 match(o0RegI);
3727
3728 format %{ %}
3729 interface(REG_INTER);
3730 %}
3731
3732 operand o0RegI() %{
3733 constraint(ALLOC_IN_RC(o0_regI));
3734 match(iRegI);
3735
3736 format %{ %}
3737 interface(REG_INTER);
3738 %}
3739
3740 // Pointer Register
3741 operand iRegP() %{
3742 constraint(ALLOC_IN_RC(ptr_reg));
3743 match(RegP);
3744
3745 match(lock_ptr_RegP);
3746 match(g1RegP);
3747 match(g2RegP);
3748 match(g3RegP);
3749 match(g4RegP);
3750 match(i0RegP);
3751 match(o0RegP);
3752 match(o1RegP);
3753 match(l7RegP);
3754
3755 format %{ %}
3756 interface(REG_INTER);
3757 %}
3758
3759 operand sp_ptr_RegP() %{
3760 constraint(ALLOC_IN_RC(sp_ptr_reg));
3761 match(RegP);
3762 match(iRegP);
3763
3764 format %{ %}
3765 interface(REG_INTER);
3766 %}
3767
3768 operand lock_ptr_RegP() %{
3769 constraint(ALLOC_IN_RC(lock_ptr_reg));
3770 match(RegP);
3771 match(i0RegP);
3772 match(o0RegP);
3773 match(o1RegP);
3774 match(l7RegP);
3775
3776 format %{ %}
3777 interface(REG_INTER);
3778 %}
3779
3780 operand g1RegP() %{
3781 constraint(ALLOC_IN_RC(g1_regP));
3782 match(iRegP);
3783
3784 format %{ %}
3785 interface(REG_INTER);
3786 %}
3787
3788 operand g2RegP() %{
3789 constraint(ALLOC_IN_RC(g2_regP));
3790 match(iRegP);
3791
3792 format %{ %}
3793 interface(REG_INTER);
3794 %}
3795
3796 operand g3RegP() %{
3797 constraint(ALLOC_IN_RC(g3_regP));
3798 match(iRegP);
3799
3800 format %{ %}
3801 interface(REG_INTER);
3802 %}
3803
3804 operand g1RegI() %{
3805 constraint(ALLOC_IN_RC(g1_regI));
3806 match(iRegI);
3807
3808 format %{ %}
3809 interface(REG_INTER);
3810 %}
3811
3812 operand g3RegI() %{
3813 constraint(ALLOC_IN_RC(g3_regI));
3814 match(iRegI);
3815
3816 format %{ %}
3817 interface(REG_INTER);
3818 %}
3819
3820 operand g4RegI() %{
3821 constraint(ALLOC_IN_RC(g4_regI));
3822 match(iRegI);
3823
3824 format %{ %}
3825 interface(REG_INTER);
3826 %}
3827
3828 operand g4RegP() %{
3829 constraint(ALLOC_IN_RC(g4_regP));
3830 match(iRegP);
3831
3832 format %{ %}
3833 interface(REG_INTER);
3834 %}
3835
3836 operand i0RegP() %{
3837 constraint(ALLOC_IN_RC(i0_regP));
3838 match(iRegP);
3839
3840 format %{ %}
3841 interface(REG_INTER);
3842 %}
3843
3844 operand o0RegP() %{
3845 constraint(ALLOC_IN_RC(o0_regP));
3846 match(iRegP);
3847
3848 format %{ %}
3849 interface(REG_INTER);
3850 %}
3851
3852 operand o1RegP() %{
3853 constraint(ALLOC_IN_RC(o1_regP));
3854 match(iRegP);
3855
3856 format %{ %}
3857 interface(REG_INTER);
3858 %}
3859
3860 operand o2RegP() %{
3861 constraint(ALLOC_IN_RC(o2_regP));
3862 match(iRegP);
3863
3864 format %{ %}
3865 interface(REG_INTER);
3866 %}
3867
3868 operand o7RegP() %{
3869 constraint(ALLOC_IN_RC(o7_regP));
3870 match(iRegP);
3871
3872 format %{ %}
3873 interface(REG_INTER);
3874 %}
3875
3876 operand l7RegP() %{
3877 constraint(ALLOC_IN_RC(l7_regP));
3878 match(iRegP);
3879
3880 format %{ %}
3881 interface(REG_INTER);
3882 %}
3883
3884 operand o7RegI() %{
3885 constraint(ALLOC_IN_RC(o7_regI));
3886 match(iRegI);
3887
3888 format %{ %}
3889 interface(REG_INTER);
3890 %}
3891
3892 operand iRegN() %{
3893 constraint(ALLOC_IN_RC(int_reg));
3894 match(RegN);
3895
3896 format %{ %}
3897 interface(REG_INTER);
3898 %}
3899
3900 // Long Register
3901 operand iRegL() %{
3902 constraint(ALLOC_IN_RC(long_reg));
3903 match(RegL);
3904
3905 format %{ %}
3906 interface(REG_INTER);
3907 %}
3908
3909 operand o2RegL() %{
3910 constraint(ALLOC_IN_RC(o2_regL));
3911 match(iRegL);
3912
3913 format %{ %}
3914 interface(REG_INTER);
3915 %}
3916
3917 operand o7RegL() %{
3918 constraint(ALLOC_IN_RC(o7_regL));
3919 match(iRegL);
3920
3921 format %{ %}
3922 interface(REG_INTER);
3923 %}
3924
3925 operand g1RegL() %{
3926 constraint(ALLOC_IN_RC(g1_regL));
3927 match(iRegL);
3928
3929 format %{ %}
3930 interface(REG_INTER);
3931 %}
3932
3933 operand g3RegL() %{
3934 constraint(ALLOC_IN_RC(g3_regL));
3935 match(iRegL);
3936
3937 format %{ %}
3938 interface(REG_INTER);
3939 %}
3940
3941 // Int Register safe
3942 // This is 64bit safe
3943 operand iRegIsafe() %{
3944 constraint(ALLOC_IN_RC(long_reg));
3945
3946 match(iRegI);
3947
3948 format %{ %}
3949 interface(REG_INTER);
3950 %}
3951
3952 // Condition Code Flag Register
3953 operand flagsReg() %{
3954 constraint(ALLOC_IN_RC(int_flags));
3955 match(RegFlags);
3956
3957 format %{ "ccr" %} // both ICC and XCC
3958 interface(REG_INTER);
3959 %}
3960
3961 // Condition Code Register, unsigned comparisons.
3962 operand flagsRegU() %{
3963 constraint(ALLOC_IN_RC(int_flags));
3964 match(RegFlags);
3965
3966 format %{ "icc_U" %}
3967 interface(REG_INTER);
3968 %}
3969
3970 // Condition Code Register, pointer comparisons.
3971 operand flagsRegP() %{
3972 constraint(ALLOC_IN_RC(int_flags));
3973 match(RegFlags);
3974
3975 #ifdef _LP64
3976 format %{ "xcc_P" %}
3977 #else
3978 format %{ "icc_P" %}
3979 #endif
3980 interface(REG_INTER);
3981 %}
3982
3983 // Condition Code Register, long comparisons.
3984 operand flagsRegL() %{
3985 constraint(ALLOC_IN_RC(int_flags));
3986 match(RegFlags);
3987
3988 format %{ "xcc_L" %}
3989 interface(REG_INTER);
3990 %}
3991
3992 // Condition Code Register, floating comparisons, unordered same as "less".
3993 operand flagsRegF() %{
3994 constraint(ALLOC_IN_RC(float_flags));
3995 match(RegFlags);
3996 match(flagsRegF0);
3997
3998 format %{ %}
3999 interface(REG_INTER);
4000 %}
4001
4002 operand flagsRegF0() %{
4003 constraint(ALLOC_IN_RC(float_flag0));
4004 match(RegFlags);
4005
4006 format %{ %}
4007 interface(REG_INTER);
4008 %}
4009
4010
4011 // Condition Code Flag Register used by long compare
4012 operand flagsReg_long_LTGE() %{
4013 constraint(ALLOC_IN_RC(int_flags));
4014 match(RegFlags);
4015 format %{ "icc_LTGE" %}
4016 interface(REG_INTER);
4017 %}
4018 operand flagsReg_long_EQNE() %{
4019 constraint(ALLOC_IN_RC(int_flags));
4020 match(RegFlags);
4021 format %{ "icc_EQNE" %}
4022 interface(REG_INTER);
4023 %}
4024 operand flagsReg_long_LEGT() %{
4025 constraint(ALLOC_IN_RC(int_flags));
4026 match(RegFlags);
4027 format %{ "icc_LEGT" %}
4028 interface(REG_INTER);
4029 %}
4030
4031
4032 operand regD() %{
4033 constraint(ALLOC_IN_RC(dflt_reg));
4034 match(RegD);
4035
4036 match(regD_low);
4037
4038 format %{ %}
4039 interface(REG_INTER);
4040 %}
4041
4042 operand regF() %{
4043 constraint(ALLOC_IN_RC(sflt_reg));
4044 match(RegF);
4045
4046 format %{ %}
4047 interface(REG_INTER);
4048 %}
4049
4050 operand regD_low() %{
4051 constraint(ALLOC_IN_RC(dflt_low_reg));
4052 match(regD);
4053
4054 format %{ %}
4055 interface(REG_INTER);
4056 %}
4057
4058 // Special Registers
4059
4060 // Method Register
4061 operand inline_cache_regP(iRegP reg) %{
4062 constraint(ALLOC_IN_RC(g5_regP)); // G5=inline_cache_reg but uses 2 bits instead of 1
4063 match(reg);
4064 format %{ %}
4065 interface(REG_INTER);
4066 %}
4067
4068 operand interpreter_method_oop_regP(iRegP reg) %{
4069 constraint(ALLOC_IN_RC(g5_regP)); // G5=interpreter_method_oop_reg but uses 2 bits instead of 1
4070 match(reg);
4071 format %{ %}
4072 interface(REG_INTER);
4073 %}
4074
4075
4076 //----------Complex Operands---------------------------------------------------
4077 // Indirect Memory Reference
4078 operand indirect(sp_ptr_RegP reg) %{
4079 constraint(ALLOC_IN_RC(sp_ptr_reg));
4080 match(reg);
4081
4082 op_cost(100);
4083 format %{ "[$reg]" %}
4084 interface(MEMORY_INTER) %{
4085 base($reg);
4086 index(0x0);
4087 scale(0x0);
4088 disp(0x0);
4089 %}
4090 %}
4091
4092 // Indirect with simm13 Offset
4093 operand indOffset13(sp_ptr_RegP reg, immX13 offset) %{
4094 constraint(ALLOC_IN_RC(sp_ptr_reg));
4095 match(AddP reg offset);
4096
4097 op_cost(100);
4098 format %{ "[$reg + $offset]" %}
4099 interface(MEMORY_INTER) %{
4100 base($reg);
4101 index(0x0);
4102 scale(0x0);
4103 disp($offset);
4104 %}
4105 %}
4106
4107 // Indirect with simm13 Offset minus 7
4108 operand indOffset13m7(sp_ptr_RegP reg, immX13m7 offset) %{
4109 constraint(ALLOC_IN_RC(sp_ptr_reg));
4110 match(AddP reg offset);
4111
4112 op_cost(100);
4113 format %{ "[$reg + $offset]" %}
4114 interface(MEMORY_INTER) %{
4115 base($reg);
4116 index(0x0);
4117 scale(0x0);
4118 disp($offset);
4119 %}
4120 %}
4121
4122 // Note: Intel has a swapped version also, like this:
4123 //operand indOffsetX(iRegI reg, immP offset) %{
4124 // constraint(ALLOC_IN_RC(int_reg));
4125 // match(AddP offset reg);
4126 //
4127 // op_cost(100);
4128 // format %{ "[$reg + $offset]" %}
4129 // interface(MEMORY_INTER) %{
4130 // base($reg);
4131 // index(0x0);
4132 // scale(0x0);
4133 // disp($offset);
4134 // %}
4135 //%}
4136 //// However, it doesn't make sense for SPARC, since
4137 // we have no particularly good way to embed oops in
4138 // single instructions.
4139
4140 // Indirect with Register Index
4141 operand indIndex(iRegP addr, iRegX index) %{
4142 constraint(ALLOC_IN_RC(ptr_reg));
4143 match(AddP addr index);
4144
4145 op_cost(100);
4146 format %{ "[$addr + $index]" %}
4147 interface(MEMORY_INTER) %{
4148 base($addr);
4149 index($index);
4150 scale(0x0);
4151 disp(0x0);
4152 %}
4153 %}
4154
4155 //----------Special Memory Operands--------------------------------------------
4156 // Stack Slot Operand - This operand is used for loading and storing temporary
4157 // values on the stack where a match requires a value to
4158 // flow through memory.
4159 operand stackSlotI(sRegI reg) %{
4160 constraint(ALLOC_IN_RC(stack_slots));
4161 op_cost(100);
4162 //match(RegI);
4163 format %{ "[$reg]" %}
4164 interface(MEMORY_INTER) %{
4165 base(0xE); // R_SP
4166 index(0x0);
4167 scale(0x0);
4168 disp($reg); // Stack Offset
4169 %}
4170 %}
4171
4172 operand stackSlotP(sRegP reg) %{
4173 constraint(ALLOC_IN_RC(stack_slots));
4174 op_cost(100);
4175 //match(RegP);
4176 format %{ "[$reg]" %}
4177 interface(MEMORY_INTER) %{
4178 base(0xE); // R_SP
4179 index(0x0);
4180 scale(0x0);
4181 disp($reg); // Stack Offset
4182 %}
4183 %}
4184
4185 operand stackSlotF(sRegF reg) %{
4186 constraint(ALLOC_IN_RC(stack_slots));
4187 op_cost(100);
4188 //match(RegF);
4189 format %{ "[$reg]" %}
4190 interface(MEMORY_INTER) %{
4191 base(0xE); // R_SP
4192 index(0x0);
4193 scale(0x0);
4194 disp($reg); // Stack Offset
4195 %}
4196 %}
4197 operand stackSlotD(sRegD reg) %{
4198 constraint(ALLOC_IN_RC(stack_slots));
4199 op_cost(100);
4200 //match(RegD);
4201 format %{ "[$reg]" %}
4202 interface(MEMORY_INTER) %{
4203 base(0xE); // R_SP
4204 index(0x0);
4205 scale(0x0);
4206 disp($reg); // Stack Offset
4207 %}
4208 %}
4209 operand stackSlotL(sRegL reg) %{
4210 constraint(ALLOC_IN_RC(stack_slots));
4211 op_cost(100);
4212 //match(RegL);
4213 format %{ "[$reg]" %}
4214 interface(MEMORY_INTER) %{
4215 base(0xE); // R_SP
4216 index(0x0);
4217 scale(0x0);
4218 disp($reg); // Stack Offset
4219 %}
4220 %}
4221
4222 // Operands for expressing Control Flow
4223 // NOTE: Label is a predefined operand which should not be redefined in
4224 // the AD file. It is generically handled within the ADLC.
4225
4226 //----------Conditional Branch Operands----------------------------------------
4227 // Comparison Op - This is the operation of the comparison, and is limited to
4228 // the following set of codes:
4229 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
4230 //
4231 // Other attributes of the comparison, such as unsignedness, are specified
4232 // by the comparison instruction that sets a condition code flags register.
4233 // That result is represented by a flags operand whose subtype is appropriate
4234 // to the unsignedness (etc.) of the comparison.
4235 //
4236 // Later, the instruction which matches both the Comparison Op (a Bool) and
4237 // the flags (produced by the Cmp) specifies the coding of the comparison op
4238 // by matching a specific subtype of Bool operand below, such as cmpOpU.
4239
4240 operand cmpOp() %{
4241 match(Bool);
4242
4243 format %{ "" %}
4244 interface(COND_INTER) %{
4245 equal(0x1);
4246 not_equal(0x9);
4247 less(0x3);
4248 greater_equal(0xB);
4249 less_equal(0x2);
4250 greater(0xA);
4251 %}
4252 %}
4253
4254 // Comparison Op, unsigned
4255 operand cmpOpU() %{
4256 match(Bool);
4257
4258 format %{ "u" %}
4259 interface(COND_INTER) %{
4260 equal(0x1);
4261 not_equal(0x9);
4262 less(0x5);
4263 greater_equal(0xD);
4264 less_equal(0x4);
4265 greater(0xC);
4266 %}
4267 %}
4268
4269 // Comparison Op, pointer (same as unsigned)
4270 operand cmpOpP() %{
4271 match(Bool);
4272
4273 format %{ "p" %}
4274 interface(COND_INTER) %{
4275 equal(0x1);
4276 not_equal(0x9);
4277 less(0x5);
4278 greater_equal(0xD);
4279 less_equal(0x4);
4280 greater(0xC);
4281 %}
4282 %}
4283
4284 // Comparison Op, branch-register encoding
4285 operand cmpOp_reg() %{
4286 match(Bool);
4287
4288 format %{ "" %}
4289 interface(COND_INTER) %{
4290 equal (0x1);
4291 not_equal (0x5);
4292 less (0x3);
4293 greater_equal(0x7);
4294 less_equal (0x2);
4295 greater (0x6);
4296 %}
4297 %}
4298
4299 // Comparison Code, floating, unordered same as less
4300 operand cmpOpF() %{
4301 match(Bool);
4302
4303 format %{ "fl" %}
4304 interface(COND_INTER) %{
4305 equal(0x9);
4306 not_equal(0x1);
4307 less(0x3);
4308 greater_equal(0xB);
4309 less_equal(0xE);
4310 greater(0x6);
4311 %}
4312 %}
4313
4314 // Used by long compare
4315 operand cmpOp_commute() %{
4316 match(Bool);
4317
4318 format %{ "" %}
4319 interface(COND_INTER) %{
4320 equal(0x1);
4321 not_equal(0x9);
4322 less(0xA);
4323 greater_equal(0x2);
4324 less_equal(0xB);
4325 greater(0x3);
4326 %}
4327 %}
4328
4329 //----------OPERAND CLASSES----------------------------------------------------
4330 // Operand Classes are groups of operands that are used to simplify
4331 // instruction definitions by not requiring the AD writer to specify separate
4332 // instructions for every form of operand when the instruction accepts
4333 // multiple operand types with the same basic encoding and format. The classic
4334 // case of this is memory operands.
4335 opclass memory( indirect, indOffset13, indIndex );
4336 opclass indIndexMemory( indIndex );
4337
4338 //----------PIPELINE-----------------------------------------------------------
4339 pipeline %{
4340
4341 //----------ATTRIBUTES---------------------------------------------------------
4342 attributes %{
4343 fixed_size_instructions; // Fixed size instructions
4344 branch_has_delay_slot; // Branch has delay slot following
4345 max_instructions_per_bundle = 4; // Up to 4 instructions per bundle
4346 instruction_unit_size = 4; // An instruction is 4 bytes long
4347 instruction_fetch_unit_size = 16; // The processor fetches one line
4348 instruction_fetch_units = 1; // of 16 bytes
4349
4350 // List of nop instructions
4351 nops( Nop_A0, Nop_A1, Nop_MS, Nop_FA, Nop_BR );
4352 %}
4353
4354 //----------RESOURCES----------------------------------------------------------
4355 // Resources are the functional units available to the machine
4356 resources(A0, A1, MS, BR, FA, FM, IDIV, FDIV, IALU = A0 | A1);
4357
4358 //----------PIPELINE DESCRIPTION-----------------------------------------------
4359 // Pipeline Description specifies the stages in the machine's pipeline
4360
4361 pipe_desc(A, P, F, B, I, J, S, R, E, C, M, W, X, T, D);
4362
4363 //----------PIPELINE CLASSES---------------------------------------------------
4364 // Pipeline Classes describe the stages in which input and output are
4365 // referenced by the hardware pipeline.
4366
4367 // Integer ALU reg-reg operation
4368 pipe_class ialu_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
4369 single_instruction;
4370 dst : E(write);
4371 src1 : R(read);
4372 src2 : R(read);
4373 IALU : R;
4374 %}
4375
4376 // Integer ALU reg-reg long operation
4377 pipe_class ialu_reg_reg_2(iRegL dst, iRegL src1, iRegL src2) %{
4378 instruction_count(2);
4379 dst : E(write);
4380 src1 : R(read);
4381 src2 : R(read);
4382 IALU : R;
4383 IALU : R;
4384 %}
4385
4386 // Integer ALU reg-reg long dependent operation
4387 pipe_class ialu_reg_reg_2_dep(iRegL dst, iRegL src1, iRegL src2, flagsReg cr) %{
4388 instruction_count(1); multiple_bundles;
4389 dst : E(write);
4390 src1 : R(read);
4391 src2 : R(read);
4392 cr : E(write);
4393 IALU : R(2);
4394 %}
4395
4396 // Integer ALU reg-imm operaion
4397 pipe_class ialu_reg_imm(iRegI dst, iRegI src1, immI13 src2) %{
4398 single_instruction;
4399 dst : E(write);
4400 src1 : R(read);
4401 IALU : R;
4402 %}
4403
4404 // Integer ALU reg-reg operation with condition code
4405 pipe_class ialu_cc_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{
4406 single_instruction;
4407 dst : E(write);
4408 cr : E(write);
4409 src1 : R(read);
4410 src2 : R(read);
4411 IALU : R;
4412 %}
4413
4414 // Integer ALU reg-imm operation with condition code
4415 pipe_class ialu_cc_reg_imm(iRegI dst, iRegI src1, immI13 src2, flagsReg cr) %{
4416 single_instruction;
4417 dst : E(write);
4418 cr : E(write);
4419 src1 : R(read);
4420 IALU : R;
4421 %}
4422
4423 // Integer ALU zero-reg operation
4424 pipe_class ialu_zero_reg(iRegI dst, immI0 zero, iRegI src2) %{
4425 single_instruction;
4426 dst : E(write);
4427 src2 : R(read);
4428 IALU : R;
4429 %}
4430
4431 // Integer ALU zero-reg operation with condition code only
4432 pipe_class ialu_cconly_zero_reg(flagsReg cr, iRegI src) %{
4433 single_instruction;
4434 cr : E(write);
4435 src : R(read);
4436 IALU : R;
4437 %}
4438
4439 // Integer ALU reg-reg operation with condition code only
4440 pipe_class ialu_cconly_reg_reg(flagsReg cr, iRegI src1, iRegI src2) %{
4441 single_instruction;
4442 cr : E(write);
4443 src1 : R(read);
4444 src2 : R(read);
4445 IALU : R;
4446 %}
4447
4448 // Integer ALU reg-imm operation with condition code only
4449 pipe_class ialu_cconly_reg_imm(flagsReg cr, iRegI src1, immI13 src2) %{
4450 single_instruction;
4451 cr : E(write);
4452 src1 : R(read);
4453 IALU : R;
4454 %}
4455
4456 // Integer ALU reg-reg-zero operation with condition code only
4457 pipe_class ialu_cconly_reg_reg_zero(flagsReg cr, iRegI src1, iRegI src2, immI0 zero) %{
4458 single_instruction;
4459 cr : E(write);
4460 src1 : R(read);
4461 src2 : R(read);
4462 IALU : R;
4463 %}
4464
4465 // Integer ALU reg-imm-zero operation with condition code only
4466 pipe_class ialu_cconly_reg_imm_zero(flagsReg cr, iRegI src1, immI13 src2, immI0 zero) %{
4467 single_instruction;
4468 cr : E(write);
4469 src1 : R(read);
4470 IALU : R;
4471 %}
4472
4473 // Integer ALU reg-reg operation with condition code, src1 modified
4474 pipe_class ialu_cc_rwreg_reg(flagsReg cr, iRegI src1, iRegI src2) %{
4475 single_instruction;
4476 cr : E(write);
4477 src1 : E(write);
4478 src1 : R(read);
4479 src2 : R(read);
4480 IALU : R;
4481 %}
4482
4483 // Integer ALU reg-imm operation with condition code, src1 modified
4484 pipe_class ialu_cc_rwreg_imm(flagsReg cr, iRegI src1, immI13 src2) %{
4485 single_instruction;
4486 cr : E(write);
4487 src1 : E(write);
4488 src1 : R(read);
4489 IALU : R;
4490 %}
4491
4492 pipe_class cmpL_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg cr ) %{
4493 multiple_bundles;
4494 dst : E(write)+4;
4495 cr : E(write);
4496 src1 : R(read);
4497 src2 : R(read);
4498 IALU : R(3);
4499 BR : R(2);
4500 %}
4501
4502 // Integer ALU operation
4503 pipe_class ialu_none(iRegI dst) %{
4504 single_instruction;
4505 dst : E(write);
4506 IALU : R;
4507 %}
4508
4509 // Integer ALU reg operation
4510 pipe_class ialu_reg(iRegI dst, iRegI src) %{
4511 single_instruction; may_have_no_code;
4512 dst : E(write);
4513 src : R(read);
4514 IALU : R;
4515 %}
4516
4517 // Integer ALU reg conditional operation
4518 // This instruction has a 1 cycle stall, and cannot execute
4519 // in the same cycle as the instruction setting the condition
4520 // code. We kludge this by pretending to read the condition code
4521 // 1 cycle earlier, and by marking the functional units as busy
4522 // for 2 cycles with the result available 1 cycle later than
4523 // is really the case.
4524 pipe_class ialu_reg_flags( iRegI op2_out, iRegI op2_in, iRegI op1, flagsReg cr ) %{
4525 single_instruction;
4526 op2_out : C(write);
4527 op1 : R(read);
4528 cr : R(read); // This is really E, with a 1 cycle stall
4529 BR : R(2);
4530 MS : R(2);
4531 %}
4532
4533 #ifdef _LP64
4534 pipe_class ialu_clr_and_mover( iRegI dst, iRegP src ) %{
4535 instruction_count(1); multiple_bundles;
4536 dst : C(write)+1;
4537 src : R(read)+1;
4538 IALU : R(1);
4539 BR : E(2);
4540 MS : E(2);
4541 %}
4542 #endif
4543
4544 // Integer ALU reg operation
4545 pipe_class ialu_move_reg_L_to_I(iRegI dst, iRegL src) %{
4546 single_instruction; may_have_no_code;
4547 dst : E(write);
4548 src : R(read);
4549 IALU : R;
4550 %}
4551 pipe_class ialu_move_reg_I_to_L(iRegL dst, iRegI src) %{
4552 single_instruction; may_have_no_code;
4553 dst : E(write);
4554 src : R(read);
4555 IALU : R;
4556 %}
4557
4558 // Two integer ALU reg operations
4559 pipe_class ialu_reg_2(iRegL dst, iRegL src) %{
4560 instruction_count(2);
4561 dst : E(write);
4562 src : R(read);
4563 A0 : R;
4564 A1 : R;
4565 %}
4566
4567 // Two integer ALU reg operations
4568 pipe_class ialu_move_reg_L_to_L(iRegL dst, iRegL src) %{
4569 instruction_count(2); may_have_no_code;
4570 dst : E(write);
4571 src : R(read);
4572 A0 : R;
4573 A1 : R;
4574 %}
4575
4576 // Integer ALU imm operation
4577 pipe_class ialu_imm(iRegI dst, immI13 src) %{
4578 single_instruction;
4579 dst : E(write);
4580 IALU : R;
4581 %}
4582
4583 // Integer ALU reg-reg with carry operation
4584 pipe_class ialu_reg_reg_cy(iRegI dst, iRegI src1, iRegI src2, iRegI cy) %{
4585 single_instruction;
4586 dst : E(write);
4587 src1 : R(read);
4588 src2 : R(read);
4589 IALU : R;
4590 %}
4591
4592 // Integer ALU cc operation
4593 pipe_class ialu_cc(iRegI dst, flagsReg cc) %{
4594 single_instruction;
4595 dst : E(write);
4596 cc : R(read);
4597 IALU : R;
4598 %}
4599
4600 // Integer ALU cc / second IALU operation
4601 pipe_class ialu_reg_ialu( iRegI dst, iRegI src ) %{
4602 instruction_count(1); multiple_bundles;
4603 dst : E(write)+1;
4604 src : R(read);
4605 IALU : R;
4606 %}
4607
4608 // Integer ALU cc / second IALU operation
4609 pipe_class ialu_reg_reg_ialu( iRegI dst, iRegI p, iRegI q ) %{
4610 instruction_count(1); multiple_bundles;
4611 dst : E(write)+1;
4612 p : R(read);
4613 q : R(read);
4614 IALU : R;
4615 %}
4616
4617 // Integer ALU hi-lo-reg operation
4618 pipe_class ialu_hi_lo_reg(iRegI dst, immI src) %{
4619 instruction_count(1); multiple_bundles;
4620 dst : E(write)+1;
4621 IALU : R(2);
4622 %}
4623
4624 // Float ALU hi-lo-reg operation (with temp)
4625 pipe_class ialu_hi_lo_reg_temp(regF dst, immF src, g3RegP tmp) %{
4626 instruction_count(1); multiple_bundles;
4627 dst : E(write)+1;
4628 IALU : R(2);
4629 %}
4630
4631 // Long Constant
4632 pipe_class loadConL( iRegL dst, immL src ) %{
4633 instruction_count(2); multiple_bundles;
4634 dst : E(write)+1;
4635 IALU : R(2);
4636 IALU : R(2);
4637 %}
4638
4639 // Pointer Constant
4640 pipe_class loadConP( iRegP dst, immP src ) %{
4641 instruction_count(0); multiple_bundles;
4642 fixed_latency(6);
4643 %}
4644
4645 // Polling Address
4646 pipe_class loadConP_poll( iRegP dst, immP_poll src ) %{
4647 #ifdef _LP64
4648 instruction_count(0); multiple_bundles;
4649 fixed_latency(6);
4650 #else
4651 dst : E(write);
4652 IALU : R;
4653 #endif
4654 %}
4655
4656 // Long Constant small
4657 pipe_class loadConLlo( iRegL dst, immL src ) %{
4658 instruction_count(2);
4659 dst : E(write);
4660 IALU : R;
4661 IALU : R;
4662 %}
4663
4664 // [PHH] This is wrong for 64-bit. See LdImmF/D.
4665 pipe_class loadConFD(regF dst, immF src, g3RegP tmp) %{
4666 instruction_count(1); multiple_bundles;
4667 src : R(read);
4668 dst : M(write)+1;
4669 IALU : R;
4670 MS : E;
4671 %}
4672
4673 // Integer ALU nop operation
4674 pipe_class ialu_nop() %{
4675 single_instruction;
4676 IALU : R;
4677 %}
4678
4679 // Integer ALU nop operation
4680 pipe_class ialu_nop_A0() %{
4681 single_instruction;
4682 A0 : R;
4683 %}
4684
4685 // Integer ALU nop operation
4686 pipe_class ialu_nop_A1() %{
4687 single_instruction;
4688 A1 : R;
4689 %}
4690
4691 // Integer Multiply reg-reg operation
4692 pipe_class imul_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
4693 single_instruction;
4694 dst : E(write);
4695 src1 : R(read);
4696 src2 : R(read);
4697 MS : R(5);
4698 %}
4699
4700 // Integer Multiply reg-imm operation
4701 pipe_class imul_reg_imm(iRegI dst, iRegI src1, immI13 src2) %{
4702 single_instruction;
4703 dst : E(write);
4704 src1 : R(read);
4705 MS : R(5);
4706 %}
4707
4708 pipe_class mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
4709 single_instruction;
4710 dst : E(write)+4;
4711 src1 : R(read);
4712 src2 : R(read);
4713 MS : R(6);
4714 %}
4715
4716 pipe_class mulL_reg_imm(iRegL dst, iRegL src1, immL13 src2) %{
4717 single_instruction;
4718 dst : E(write)+4;
4719 src1 : R(read);
4720 MS : R(6);
4721 %}
4722
4723 // Integer Divide reg-reg
4724 pipe_class sdiv_reg_reg(iRegI dst, iRegI src1, iRegI src2, iRegI temp, flagsReg cr) %{
4725 instruction_count(1); multiple_bundles;
4726 dst : E(write);
4727 temp : E(write);
4728 src1 : R(read);
4729 src2 : R(read);
4730 temp : R(read);
4731 MS : R(38);
4732 %}
4733
4734 // Integer Divide reg-imm
4735 pipe_class sdiv_reg_imm(iRegI dst, iRegI src1, immI13 src2, iRegI temp, flagsReg cr) %{
4736 instruction_count(1); multiple_bundles;
4737 dst : E(write);
4738 temp : E(write);
4739 src1 : R(read);
4740 temp : R(read);
4741 MS : R(38);
4742 %}
4743
4744 // Long Divide
4745 pipe_class divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
4746 dst : E(write)+71;
4747 src1 : R(read);
4748 src2 : R(read)+1;
4749 MS : R(70);
4750 %}
4751
4752 pipe_class divL_reg_imm(iRegL dst, iRegL src1, immL13 src2) %{
4753 dst : E(write)+71;
4754 src1 : R(read);
4755 MS : R(70);
4756 %}
4757
4758 // Floating Point Add Float
4759 pipe_class faddF_reg_reg(regF dst, regF src1, regF src2) %{
4760 single_instruction;
4761 dst : X(write);
4762 src1 : E(read);
4763 src2 : E(read);
4764 FA : R;
4765 %}
4766
4767 // Floating Point Add Double
4768 pipe_class faddD_reg_reg(regD dst, regD src1, regD src2) %{
4769 single_instruction;
4770 dst : X(write);
4771 src1 : E(read);
4772 src2 : E(read);
4773 FA : R;
4774 %}
4775
4776 // Floating Point Conditional Move based on integer flags
4777 pipe_class int_conditional_float_move (cmpOp cmp, flagsReg cr, regF dst, regF src) %{
4778 single_instruction;
4779 dst : X(write);
4780 src : E(read);
4781 cr : R(read);
4782 FA : R(2);
4783 BR : R(2);
4784 %}
4785
4786 // Floating Point Conditional Move based on integer flags
4787 pipe_class int_conditional_double_move (cmpOp cmp, flagsReg cr, regD dst, regD src) %{
4788 single_instruction;
4789 dst : X(write);
4790 src : E(read);
4791 cr : R(read);
4792 FA : R(2);
4793 BR : R(2);
4794 %}
4795
4796 // Floating Point Multiply Float
4797 pipe_class fmulF_reg_reg(regF dst, regF src1, regF src2) %{
4798 single_instruction;
4799 dst : X(write);
4800 src1 : E(read);
4801 src2 : E(read);
4802 FM : R;
4803 %}
4804
4805 // Floating Point Multiply Double
4806 pipe_class fmulD_reg_reg(regD dst, regD src1, regD src2) %{
4807 single_instruction;
4808 dst : X(write);
4809 src1 : E(read);
4810 src2 : E(read);
4811 FM : R;
4812 %}
4813
4814 // Floating Point Divide Float
4815 pipe_class fdivF_reg_reg(regF dst, regF src1, regF src2) %{
4816 single_instruction;
4817 dst : X(write);
4818 src1 : E(read);
4819 src2 : E(read);
4820 FM : R;
4821 FDIV : C(14);
4822 %}
4823
4824 // Floating Point Divide Double
4825 pipe_class fdivD_reg_reg(regD dst, regD src1, regD src2) %{
4826 single_instruction;
4827 dst : X(write);
4828 src1 : E(read);
4829 src2 : E(read);
4830 FM : R;
4831 FDIV : C(17);
4832 %}
4833
4834 // Floating Point Move/Negate/Abs Float
4835 pipe_class faddF_reg(regF dst, regF src) %{
4836 single_instruction;
4837 dst : W(write);
4838 src : E(read);
4839 FA : R(1);
4840 %}
4841
4842 // Floating Point Move/Negate/Abs Double
4843 pipe_class faddD_reg(regD dst, regD src) %{
4844 single_instruction;
4845 dst : W(write);
4846 src : E(read);
4847 FA : R;
4848 %}
4849
4850 // Floating Point Convert F->D
4851 pipe_class fcvtF2D(regD dst, regF src) %{
4852 single_instruction;
4853 dst : X(write);
4854 src : E(read);
4855 FA : R;
4856 %}
4857
4858 // Floating Point Convert I->D
4859 pipe_class fcvtI2D(regD dst, regF src) %{
4860 single_instruction;
4861 dst : X(write);
4862 src : E(read);
4863 FA : R;
4864 %}
4865
4866 // Floating Point Convert LHi->D
4867 pipe_class fcvtLHi2D(regD dst, regD src) %{
4868 single_instruction;
4869 dst : X(write);
4870 src : E(read);
4871 FA : R;
4872 %}
4873
4874 // Floating Point Convert L->D
4875 pipe_class fcvtL2D(regD dst, regF src) %{
4876 single_instruction;
4877 dst : X(write);
4878 src : E(read);
4879 FA : R;
4880 %}
4881
4882 // Floating Point Convert L->F
4883 pipe_class fcvtL2F(regD dst, regF src) %{
4884 single_instruction;
4885 dst : X(write);
4886 src : E(read);
4887 FA : R;
4888 %}
4889
4890 // Floating Point Convert D->F
4891 pipe_class fcvtD2F(regD dst, regF src) %{
4892 single_instruction;
4893 dst : X(write);
4894 src : E(read);
4895 FA : R;
4896 %}
4897
4898 // Floating Point Convert I->L
4899 pipe_class fcvtI2L(regD dst, regF src) %{
4900 single_instruction;
4901 dst : X(write);
4902 src : E(read);
4903 FA : R;
4904 %}
4905
4906 // Floating Point Convert D->F
4907 pipe_class fcvtD2I(regF dst, regD src, flagsReg cr) %{
4908 instruction_count(1); multiple_bundles;
4909 dst : X(write)+6;
4910 src : E(read);
4911 FA : R;
4912 %}
4913
4914 // Floating Point Convert D->L
4915 pipe_class fcvtD2L(regD dst, regD src, flagsReg cr) %{
4916 instruction_count(1); multiple_bundles;
4917 dst : X(write)+6;
4918 src : E(read);
4919 FA : R;
4920 %}
4921
4922 // Floating Point Convert F->I
4923 pipe_class fcvtF2I(regF dst, regF src, flagsReg cr) %{
4924 instruction_count(1); multiple_bundles;
4925 dst : X(write)+6;
4926 src : E(read);
4927 FA : R;
4928 %}
4929
4930 // Floating Point Convert F->L
4931 pipe_class fcvtF2L(regD dst, regF src, flagsReg cr) %{
4932 instruction_count(1); multiple_bundles;
4933 dst : X(write)+6;
4934 src : E(read);
4935 FA : R;
4936 %}
4937
4938 // Floating Point Convert I->F
4939 pipe_class fcvtI2F(regF dst, regF src) %{
4940 single_instruction;
4941 dst : X(write);
4942 src : E(read);
4943 FA : R;
4944 %}
4945
4946 // Floating Point Compare
4947 pipe_class faddF_fcc_reg_reg_zero(flagsRegF cr, regF src1, regF src2, immI0 zero) %{
4948 single_instruction;
4949 cr : X(write);
4950 src1 : E(read);
4951 src2 : E(read);
4952 FA : R;
4953 %}
4954
4955 // Floating Point Compare
4956 pipe_class faddD_fcc_reg_reg_zero(flagsRegF cr, regD src1, regD src2, immI0 zero) %{
4957 single_instruction;
4958 cr : X(write);
4959 src1 : E(read);
4960 src2 : E(read);
4961 FA : R;
4962 %}
4963
4964 // Floating Add Nop
4965 pipe_class fadd_nop() %{
4966 single_instruction;
4967 FA : R;
4968 %}
4969
4970 // Integer Store to Memory
4971 pipe_class istore_mem_reg(memory mem, iRegI src) %{
4972 single_instruction;
4973 mem : R(read);
4974 src : C(read);
4975 MS : R;
4976 %}
4977
4978 // Integer Store to Memory
4979 pipe_class istore_mem_spORreg(memory mem, sp_ptr_RegP src) %{
4980 single_instruction;
4981 mem : R(read);
4982 src : C(read);
4983 MS : R;
4984 %}
4985
4986 // Integer Store Zero to Memory
4987 pipe_class istore_mem_zero(memory mem, immI0 src) %{
4988 single_instruction;
4989 mem : R(read);
4990 MS : R;
4991 %}
4992
4993 // Special Stack Slot Store
4994 pipe_class istore_stk_reg(stackSlotI stkSlot, iRegI src) %{
4995 single_instruction;
4996 stkSlot : R(read);
4997 src : C(read);
4998 MS : R;
4999 %}
5000
5001 // Special Stack Slot Store
5002 pipe_class lstoreI_stk_reg(stackSlotL stkSlot, iRegI src) %{
5003 instruction_count(2); multiple_bundles;
5004 stkSlot : R(read);
5005 src : C(read);
5006 MS : R(2);
5007 %}
5008
5009 // Float Store
5010 pipe_class fstoreF_mem_reg(memory mem, RegF src) %{
5011 single_instruction;
5012 mem : R(read);
5013 src : C(read);
5014 MS : R;
5015 %}
5016
5017 // Float Store
5018 pipe_class fstoreF_mem_zero(memory mem, immF0 src) %{
5019 single_instruction;
5020 mem : R(read);
5021 MS : R;
5022 %}
5023
5024 // Double Store
5025 pipe_class fstoreD_mem_reg(memory mem, RegD src) %{
5026 instruction_count(1);
5027 mem : R(read);
5028 src : C(read);
5029 MS : R;
5030 %}
5031
5032 // Double Store
5033 pipe_class fstoreD_mem_zero(memory mem, immD0 src) %{
5034 single_instruction;
5035 mem : R(read);
5036 MS : R;
5037 %}
5038
5039 // Special Stack Slot Float Store
5040 pipe_class fstoreF_stk_reg(stackSlotI stkSlot, RegF src) %{
5041 single_instruction;
5042 stkSlot : R(read);
5043 src : C(read);
5044 MS : R;
5045 %}
5046
5047 // Special Stack Slot Double Store
5048 pipe_class fstoreD_stk_reg(stackSlotI stkSlot, RegD src) %{
5049 single_instruction;
5050 stkSlot : R(read);
5051 src : C(read);
5052 MS : R;
5053 %}
5054
5055 // Integer Load (when sign bit propagation not needed)
5056 pipe_class iload_mem(iRegI dst, memory mem) %{
5057 single_instruction;
5058 mem : R(read);
5059 dst : C(write);
5060 MS : R;
5061 %}
5062
5063 // Integer Load from stack operand
5064 pipe_class iload_stkD(iRegI dst, stackSlotD mem ) %{
5065 single_instruction;
5066 mem : R(read);
5067 dst : C(write);
5068 MS : R;
5069 %}
5070
5071 // Integer Load (when sign bit propagation or masking is needed)
5072 pipe_class iload_mask_mem(iRegI dst, memory mem) %{
5073 single_instruction;
5074 mem : R(read);
5075 dst : M(write);
5076 MS : R;
5077 %}
5078
5079 // Float Load
5080 pipe_class floadF_mem(regF dst, memory mem) %{
5081 single_instruction;
5082 mem : R(read);
5083 dst : M(write);
5084 MS : R;
5085 %}
5086
5087 // Float Load
5088 pipe_class floadD_mem(regD dst, memory mem) %{
5089 instruction_count(1); multiple_bundles; // Again, unaligned argument is only multiple case
5090 mem : R(read);
5091 dst : M(write);
5092 MS : R;
5093 %}
5094
5095 // Float Load
5096 pipe_class floadF_stk(regF dst, stackSlotI stkSlot) %{
5097 single_instruction;
5098 stkSlot : R(read);
5099 dst : M(write);
5100 MS : R;
5101 %}
5102
5103 // Float Load
5104 pipe_class floadD_stk(regD dst, stackSlotI stkSlot) %{
5105 single_instruction;
5106 stkSlot : R(read);
5107 dst : M(write);
5108 MS : R;
5109 %}
5110
5111 // Memory Nop
5112 pipe_class mem_nop() %{
5113 single_instruction;
5114 MS : R;
5115 %}
5116
5117 pipe_class sethi(iRegP dst, immI src) %{
5118 single_instruction;
5119 dst : E(write);
5120 IALU : R;
5121 %}
5122
5123 pipe_class loadPollP(iRegP poll) %{
5124 single_instruction;
5125 poll : R(read);
5126 MS : R;
5127 %}
5128
5129 pipe_class br(Universe br, label labl) %{
5130 single_instruction_with_delay_slot;
5131 BR : R;
5132 %}
5133
5134 pipe_class br_cc(Universe br, cmpOp cmp, flagsReg cr, label labl) %{
5135 single_instruction_with_delay_slot;
5136 cr : E(read);
5137 BR : R;
5138 %}
5139
5140 pipe_class br_reg(Universe br, cmpOp cmp, iRegI op1, label labl) %{
5141 single_instruction_with_delay_slot;
5142 op1 : E(read);
5143 BR : R;
5144 MS : R;
5145 %}
5146
5147 // Compare and branch
5148 pipe_class cmp_br_reg_reg(Universe br, cmpOp cmp, iRegI src1, iRegI src2, label labl, flagsReg cr) %{
5149 instruction_count(2); has_delay_slot;
5150 cr : E(write);
5151 src1 : R(read);
5152 src2 : R(read);
5153 IALU : R;
5154 BR : R;
5155 %}
5156
5157 // Compare and branch
5158 pipe_class cmp_br_reg_imm(Universe br, cmpOp cmp, iRegI src1, immI13 src2, label labl, flagsReg cr) %{
5159 instruction_count(2); has_delay_slot;
5160 cr : E(write);
5161 src1 : R(read);
5162 IALU : R;
5163 BR : R;
5164 %}
5165
5166 // Compare and branch using cbcond
5167 pipe_class cbcond_reg_reg(Universe br, cmpOp cmp, iRegI src1, iRegI src2, label labl) %{
5168 single_instruction;
5169 src1 : E(read);
5170 src2 : E(read);
5171 IALU : R;
5172 BR : R;
5173 %}
5174
5175 // Compare and branch using cbcond
5176 pipe_class cbcond_reg_imm(Universe br, cmpOp cmp, iRegI src1, immI5 src2, label labl) %{
5177 single_instruction;
5178 src1 : E(read);
5179 IALU : R;
5180 BR : R;
5181 %}
5182
5183 pipe_class br_fcc(Universe br, cmpOpF cc, flagsReg cr, label labl) %{
5184 single_instruction_with_delay_slot;
5185 cr : E(read);
5186 BR : R;
5187 %}
5188
5189 pipe_class br_nop() %{
5190 single_instruction;
5191 BR : R;
5192 %}
5193
5194 pipe_class simple_call(method meth) %{
5195 instruction_count(2); multiple_bundles; force_serialization;
5196 fixed_latency(100);
5197 BR : R(1);
5198 MS : R(1);
5199 A0 : R(1);
5200 %}
5201
5202 pipe_class compiled_call(method meth) %{
5203 instruction_count(1); multiple_bundles; force_serialization;
5204 fixed_latency(100);
5205 MS : R(1);
5206 %}
5207
5208 pipe_class call(method meth) %{
5209 instruction_count(0); multiple_bundles; force_serialization;
5210 fixed_latency(100);
5211 %}
5212
5213 pipe_class tail_call(Universe ignore, label labl) %{
5214 single_instruction; has_delay_slot;
5215 fixed_latency(100);
5216 BR : R(1);
5217 MS : R(1);
5218 %}
5219
5220 pipe_class ret(Universe ignore) %{
5221 single_instruction; has_delay_slot;
5222 BR : R(1);
5223 MS : R(1);
5224 %}
5225
5226 pipe_class ret_poll(g3RegP poll) %{
5227 instruction_count(3); has_delay_slot;
5228 poll : E(read);
5229 MS : R;
5230 %}
5231
5232 // The real do-nothing guy
5233 pipe_class empty( ) %{
5234 instruction_count(0);
5235 %}
5236
5237 pipe_class long_memory_op() %{
5238 instruction_count(0); multiple_bundles; force_serialization;
5239 fixed_latency(25);
5240 MS : R(1);
5241 %}
5242
5243 // Check-cast
5244 pipe_class partial_subtype_check_pipe(Universe ignore, iRegP array, iRegP match ) %{
5245 array : R(read);
5246 match : R(read);
5247 IALU : R(2);
5248 BR : R(2);
5249 MS : R;
5250 %}
5251
5252 // Convert FPU flags into +1,0,-1
5253 pipe_class floating_cmp( iRegI dst, regF src1, regF src2 ) %{
5254 src1 : E(read);
5255 src2 : E(read);
5256 dst : E(write);
5257 FA : R;
5258 MS : R(2);
5259 BR : R(2);
5260 %}
5261
5262 // Compare for p < q, and conditionally add y
5263 pipe_class cadd_cmpltmask( iRegI p, iRegI q, iRegI y ) %{
5264 p : E(read);
5265 q : E(read);
5266 y : E(read);
5267 IALU : R(3)
5268 %}
5269
5270 // Perform a compare, then move conditionally in a branch delay slot.
5271 pipe_class min_max( iRegI src2, iRegI srcdst ) %{
5272 src2 : E(read);
5273 srcdst : E(read);
5274 IALU : R;
5275 BR : R;
5276 %}
5277
5278 // Define the class for the Nop node
5279 define %{
5280 MachNop = ialu_nop;
5281 %}
5282
5283 %}
5284
5285 //----------INSTRUCTIONS-------------------------------------------------------
5286
5287 //------------Special Stack Slot instructions - no match rules-----------------
5288 instruct stkI_to_regF(regF dst, stackSlotI src) %{
5289 // No match rule to avoid chain rule match.
5290 effect(DEF dst, USE src);
5291 ins_cost(MEMORY_REF_COST);
5292 size(4);
5293 format %{ "LDF $src,$dst\t! stkI to regF" %}
5294 opcode(Assembler::ldf_op3);
5295 ins_encode(simple_form3_mem_reg(src, dst));
5296 ins_pipe(floadF_stk);
5297 %}
5298
5299 instruct stkL_to_regD(regD dst, stackSlotL src) %{
5300 // No match rule to avoid chain rule match.
5301 effect(DEF dst, USE src);
5302 ins_cost(MEMORY_REF_COST);
5303 size(4);
5304 format %{ "LDDF $src,$dst\t! stkL to regD" %}
5305 opcode(Assembler::lddf_op3);
5306 ins_encode(simple_form3_mem_reg(src, dst));
5307 ins_pipe(floadD_stk);
5308 %}
5309
5310 instruct regF_to_stkI(stackSlotI dst, regF src) %{
5311 // No match rule to avoid chain rule match.
5312 effect(DEF dst, USE src);
5313 ins_cost(MEMORY_REF_COST);
5314 size(4);
5315 format %{ "STF $src,$dst\t! regF to stkI" %}
5316 opcode(Assembler::stf_op3);
5317 ins_encode(simple_form3_mem_reg(dst, src));
5318 ins_pipe(fstoreF_stk_reg);
5319 %}
5320
5321 instruct regD_to_stkL(stackSlotL dst, regD src) %{
5322 // No match rule to avoid chain rule match.
5323 effect(DEF dst, USE src);
5324 ins_cost(MEMORY_REF_COST);
5325 size(4);
5326 format %{ "STDF $src,$dst\t! regD to stkL" %}
5327 opcode(Assembler::stdf_op3);
5328 ins_encode(simple_form3_mem_reg(dst, src));
5329 ins_pipe(fstoreD_stk_reg);
5330 %}
5331
5332 instruct regI_to_stkLHi(stackSlotL dst, iRegI src) %{
5333 effect(DEF dst, USE src);
5334 ins_cost(MEMORY_REF_COST*2);
5335 size(8);
5336 format %{ "STW $src,$dst.hi\t! long\n\t"
5337 "STW R_G0,$dst.lo" %}
5338 opcode(Assembler::stw_op3);
5339 ins_encode(simple_form3_mem_reg(dst, src), form3_mem_plus_4_reg(dst, R_G0));
5340 ins_pipe(lstoreI_stk_reg);
5341 %}
5342
5343 instruct regL_to_stkD(stackSlotD dst, iRegL src) %{
5344 // No match rule to avoid chain rule match.
5345 effect(DEF dst, USE src);
5346 ins_cost(MEMORY_REF_COST);
5347 size(4);
5348 format %{ "STX $src,$dst\t! regL to stkD" %}
5349 opcode(Assembler::stx_op3);
5350 ins_encode(simple_form3_mem_reg( dst, src ) );
5351 ins_pipe(istore_stk_reg);
5352 %}
5353
5354 //---------- Chain stack slots between similar types --------
5355
5356 // Load integer from stack slot
5357 instruct stkI_to_regI( iRegI dst, stackSlotI src ) %{
5358 match(Set dst src);
5359 ins_cost(MEMORY_REF_COST);
5360
5361 size(4);
5362 format %{ "LDUW $src,$dst\t!stk" %}
5363 opcode(Assembler::lduw_op3);
5364 ins_encode(simple_form3_mem_reg( src, dst ) );
5365 ins_pipe(iload_mem);
5366 %}
5367
5368 // Store integer to stack slot
5369 instruct regI_to_stkI( stackSlotI dst, iRegI src ) %{
5370 match(Set dst src);
5371 ins_cost(MEMORY_REF_COST);
5372
5373 size(4);
5374 format %{ "STW $src,$dst\t!stk" %}
5375 opcode(Assembler::stw_op3);
5376 ins_encode(simple_form3_mem_reg( dst, src ) );
5377 ins_pipe(istore_mem_reg);
5378 %}
5379
5380 // Load long from stack slot
5381 instruct stkL_to_regL( iRegL dst, stackSlotL src ) %{
5382 match(Set dst src);
5383
5384 ins_cost(MEMORY_REF_COST);
5385 size(4);
5386 format %{ "LDX $src,$dst\t! long" %}
5387 opcode(Assembler::ldx_op3);
5388 ins_encode(simple_form3_mem_reg( src, dst ) );
5389 ins_pipe(iload_mem);
5390 %}
5391
5392 // Store long to stack slot
5393 instruct regL_to_stkL(stackSlotL dst, iRegL src) %{
5394 match(Set dst src);
5395
5396 ins_cost(MEMORY_REF_COST);
5397 size(4);
5398 format %{ "STX $src,$dst\t! long" %}
5399 opcode(Assembler::stx_op3);
5400 ins_encode(simple_form3_mem_reg( dst, src ) );
5401 ins_pipe(istore_mem_reg);
5402 %}
5403
5404 #ifdef _LP64
5405 // Load pointer from stack slot, 64-bit encoding
5406 instruct stkP_to_regP( iRegP dst, stackSlotP src ) %{
5407 match(Set dst src);
5408 ins_cost(MEMORY_REF_COST);
5409 size(4);
5410 format %{ "LDX $src,$dst\t!ptr" %}
5411 opcode(Assembler::ldx_op3);
5412 ins_encode(simple_form3_mem_reg( src, dst ) );
5413 ins_pipe(iload_mem);
5414 %}
5415
5416 // Store pointer to stack slot
5417 instruct regP_to_stkP(stackSlotP dst, iRegP src) %{
5418 match(Set dst src);
5419 ins_cost(MEMORY_REF_COST);
5420 size(4);
5421 format %{ "STX $src,$dst\t!ptr" %}
5422 opcode(Assembler::stx_op3);
5423 ins_encode(simple_form3_mem_reg( dst, src ) );
5424 ins_pipe(istore_mem_reg);
5425 %}
5426 #else // _LP64
5427 // Load pointer from stack slot, 32-bit encoding
5428 instruct stkP_to_regP( iRegP dst, stackSlotP src ) %{
5429 match(Set dst src);
5430 ins_cost(MEMORY_REF_COST);
5431 format %{ "LDUW $src,$dst\t!ptr" %}
5432 opcode(Assembler::lduw_op3, Assembler::ldst_op);
5433 ins_encode(simple_form3_mem_reg( src, dst ) );
5434 ins_pipe(iload_mem);
5435 %}
5436
5437 // Store pointer to stack slot
5438 instruct regP_to_stkP(stackSlotP dst, iRegP src) %{
5439 match(Set dst src);
5440 ins_cost(MEMORY_REF_COST);
5441 format %{ "STW $src,$dst\t!ptr" %}
5442 opcode(Assembler::stw_op3, Assembler::ldst_op);
5443 ins_encode(simple_form3_mem_reg( dst, src ) );
5444 ins_pipe(istore_mem_reg);
5445 %}
5446 #endif // _LP64
5447
5448 //------------Special Nop instructions for bundling - no match rules-----------
5449 // Nop using the A0 functional unit
5450 instruct Nop_A0() %{
5451 ins_cost(0);
5452
5453 format %{ "NOP ! Alu Pipeline" %}
5454 opcode(Assembler::or_op3, Assembler::arith_op);
5455 ins_encode( form2_nop() );
5456 ins_pipe(ialu_nop_A0);
5457 %}
5458
5459 // Nop using the A1 functional unit
5460 instruct Nop_A1( ) %{
5461 ins_cost(0);
5462
5463 format %{ "NOP ! Alu Pipeline" %}
5464 opcode(Assembler::or_op3, Assembler::arith_op);
5465 ins_encode( form2_nop() );
5466 ins_pipe(ialu_nop_A1);
5467 %}
5468
5469 // Nop using the memory functional unit
5470 instruct Nop_MS( ) %{
5471 ins_cost(0);
5472
5473 format %{ "NOP ! Memory Pipeline" %}
5474 ins_encode( emit_mem_nop );
5475 ins_pipe(mem_nop);
5476 %}
5477
5478 // Nop using the floating add functional unit
5479 instruct Nop_FA( ) %{
5480 ins_cost(0);
5481
5482 format %{ "NOP ! Floating Add Pipeline" %}
5483 ins_encode( emit_fadd_nop );
5484 ins_pipe(fadd_nop);
5485 %}
5486
5487 // Nop using the branch functional unit
5488 instruct Nop_BR( ) %{
5489 ins_cost(0);
5490
5491 format %{ "NOP ! Branch Pipeline" %}
5492 ins_encode( emit_br_nop );
5493 ins_pipe(br_nop);
5494 %}
5495
5496 //----------Load/Store/Move Instructions---------------------------------------
5497 //----------Load Instructions--------------------------------------------------
5498 // Load Byte (8bit signed)
5499 instruct loadB(iRegI dst, memory mem) %{
5500 match(Set dst (LoadB mem));
5501 ins_cost(MEMORY_REF_COST);
5502
5503 size(4);
5504 format %{ "LDSB $mem,$dst\t! byte" %}
5505 ins_encode %{
5506 __ ldsb($mem$$Address, $dst$$Register);
5507 %}
5508 ins_pipe(iload_mask_mem);
5509 %}
5510
5511 // Load Byte (8bit signed) into a Long Register
5512 instruct loadB2L(iRegL dst, memory mem) %{
5513 match(Set dst (ConvI2L (LoadB mem)));
5514 ins_cost(MEMORY_REF_COST);
5515
5516 size(4);
5517 format %{ "LDSB $mem,$dst\t! byte -> long" %}
5518 ins_encode %{
5519 __ ldsb($mem$$Address, $dst$$Register);
5520 %}
5521 ins_pipe(iload_mask_mem);
5522 %}
5523
5524 // Load Unsigned Byte (8bit UNsigned) into an int reg
5525 instruct loadUB(iRegI dst, memory mem) %{
5526 match(Set dst (LoadUB mem));
5527 ins_cost(MEMORY_REF_COST);
5528
5529 size(4);
5530 format %{ "LDUB $mem,$dst\t! ubyte" %}
5531 ins_encode %{
5532 __ ldub($mem$$Address, $dst$$Register);
5533 %}
5534 ins_pipe(iload_mem);
5535 %}
5536
5537 // Load Unsigned Byte (8bit UNsigned) into a Long Register
5538 instruct loadUB2L(iRegL dst, memory mem) %{
5539 match(Set dst (ConvI2L (LoadUB mem)));
5540 ins_cost(MEMORY_REF_COST);
5541
5542 size(4);
5543 format %{ "LDUB $mem,$dst\t! ubyte -> long" %}
5544 ins_encode %{
5545 __ ldub($mem$$Address, $dst$$Register);
5546 %}
5547 ins_pipe(iload_mem);
5548 %}
5549
5550 // Load Unsigned Byte (8 bit UNsigned) with 8-bit mask into Long Register
5551 instruct loadUB2L_immI8(iRegL dst, memory mem, immI8 mask) %{
5552 match(Set dst (ConvI2L (AndI (LoadUB mem) mask)));
5553 ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5554
5555 size(2*4);
5556 format %{ "LDUB $mem,$dst\t# ubyte & 8-bit mask -> long\n\t"
5557 "AND $dst,$mask,$dst" %}
5558 ins_encode %{
5559 __ ldub($mem$$Address, $dst$$Register);
5560 __ and3($dst$$Register, $mask$$constant, $dst$$Register);
5561 %}
5562 ins_pipe(iload_mem);
5563 %}
5564
5565 // Load Short (16bit signed)
5566 instruct loadS(iRegI dst, memory mem) %{
5567 match(Set dst (LoadS mem));
5568 ins_cost(MEMORY_REF_COST);
5569
5570 size(4);
5571 format %{ "LDSH $mem,$dst\t! short" %}
5572 ins_encode %{
5573 __ ldsh($mem$$Address, $dst$$Register);
5574 %}
5575 ins_pipe(iload_mask_mem);
5576 %}
5577
5578 // Load Short (16 bit signed) to Byte (8 bit signed)
5579 instruct loadS2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{
5580 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour));
5581 ins_cost(MEMORY_REF_COST);
5582
5583 size(4);
5584
5585 format %{ "LDSB $mem+1,$dst\t! short -> byte" %}
5586 ins_encode %{
5587 __ ldsb($mem$$Address, $dst$$Register, 1);
5588 %}
5589 ins_pipe(iload_mask_mem);
5590 %}
5591
5592 // Load Short (16bit signed) into a Long Register
5593 instruct loadS2L(iRegL dst, memory mem) %{
5594 match(Set dst (ConvI2L (LoadS mem)));
5595 ins_cost(MEMORY_REF_COST);
5596
5597 size(4);
5598 format %{ "LDSH $mem,$dst\t! short -> long" %}
5599 ins_encode %{
5600 __ ldsh($mem$$Address, $dst$$Register);
5601 %}
5602 ins_pipe(iload_mask_mem);
5603 %}
5604
5605 // Load Unsigned Short/Char (16bit UNsigned)
5606 instruct loadUS(iRegI dst, memory mem) %{
5607 match(Set dst (LoadUS mem));
5608 ins_cost(MEMORY_REF_COST);
5609
5610 size(4);
5611 format %{ "LDUH $mem,$dst\t! ushort/char" %}
5612 ins_encode %{
5613 __ lduh($mem$$Address, $dst$$Register);
5614 %}
5615 ins_pipe(iload_mem);
5616 %}
5617
5618 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed)
5619 instruct loadUS2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{
5620 match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour));
5621 ins_cost(MEMORY_REF_COST);
5622
5623 size(4);
5624 format %{ "LDSB $mem+1,$dst\t! ushort -> byte" %}
5625 ins_encode %{
5626 __ ldsb($mem$$Address, $dst$$Register, 1);
5627 %}
5628 ins_pipe(iload_mask_mem);
5629 %}
5630
5631 // Load Unsigned Short/Char (16bit UNsigned) into a Long Register
5632 instruct loadUS2L(iRegL dst, memory mem) %{
5633 match(Set dst (ConvI2L (LoadUS mem)));
5634 ins_cost(MEMORY_REF_COST);
5635
5636 size(4);
5637 format %{ "LDUH $mem,$dst\t! ushort/char -> long" %}
5638 ins_encode %{
5639 __ lduh($mem$$Address, $dst$$Register);
5640 %}
5641 ins_pipe(iload_mem);
5642 %}
5643
5644 // Load Unsigned Short/Char (16bit UNsigned) with mask 0xFF into a Long Register
5645 instruct loadUS2L_immI_255(iRegL dst, indOffset13m7 mem, immI_255 mask) %{
5646 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5647 ins_cost(MEMORY_REF_COST);
5648
5649 size(4);
5650 format %{ "LDUB $mem+1,$dst\t! ushort/char & 0xFF -> long" %}
5651 ins_encode %{
5652 __ ldub($mem$$Address, $dst$$Register, 1); // LSB is index+1 on BE
5653 %}
5654 ins_pipe(iload_mem);
5655 %}
5656
5657 // Load Unsigned Short/Char (16bit UNsigned) with a 13-bit mask into a Long Register
5658 instruct loadUS2L_immI13(iRegL dst, memory mem, immI13 mask) %{
5659 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5660 ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5661
5662 size(2*4);
5663 format %{ "LDUH $mem,$dst\t! ushort/char & 13-bit mask -> long\n\t"
5664 "AND $dst,$mask,$dst" %}
5665 ins_encode %{
5666 Register Rdst = $dst$$Register;
5667 __ lduh($mem$$Address, Rdst);
5668 __ and3(Rdst, $mask$$constant, Rdst);
5669 %}
5670 ins_pipe(iload_mem);
5671 %}
5672
5673 // Load Unsigned Short/Char (16bit UNsigned) with a 16-bit mask into a Long Register
5674 instruct loadUS2L_immI16(iRegL dst, memory mem, immI16 mask, iRegL tmp) %{
5675 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5676 effect(TEMP dst, TEMP tmp);
5677 ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST);
5678
5679 size((3+1)*4); // set may use two instructions.
5680 format %{ "LDUH $mem,$dst\t! ushort/char & 16-bit mask -> long\n\t"
5681 "SET $mask,$tmp\n\t"
5682 "AND $dst,$tmp,$dst" %}
5683 ins_encode %{
5684 Register Rdst = $dst$$Register;
5685 Register Rtmp = $tmp$$Register;
5686 __ lduh($mem$$Address, Rdst);
5687 __ set($mask$$constant, Rtmp);
5688 __ and3(Rdst, Rtmp, Rdst);
5689 %}
5690 ins_pipe(iload_mem);
5691 %}
5692
5693 // Load Integer
5694 instruct loadI(iRegI dst, memory mem) %{
5695 match(Set dst (LoadI mem));
5696 ins_cost(MEMORY_REF_COST);
5697
5698 size(4);
5699 format %{ "LDUW $mem,$dst\t! int" %}
5700 ins_encode %{
5701 __ lduw($mem$$Address, $dst$$Register);
5702 %}
5703 ins_pipe(iload_mem);
5704 %}
5705
5706 // Load Integer to Byte (8 bit signed)
5707 instruct loadI2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{
5708 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour));
5709 ins_cost(MEMORY_REF_COST);
5710
5711 size(4);
5712
5713 format %{ "LDSB $mem+3,$dst\t! int -> byte" %}
5714 ins_encode %{
5715 __ ldsb($mem$$Address, $dst$$Register, 3);
5716 %}
5717 ins_pipe(iload_mask_mem);
5718 %}
5719
5720 // Load Integer to Unsigned Byte (8 bit UNsigned)
5721 instruct loadI2UB(iRegI dst, indOffset13m7 mem, immI_255 mask) %{
5722 match(Set dst (AndI (LoadI mem) mask));
5723 ins_cost(MEMORY_REF_COST);
5724
5725 size(4);
5726
5727 format %{ "LDUB $mem+3,$dst\t! int -> ubyte" %}
5728 ins_encode %{
5729 __ ldub($mem$$Address, $dst$$Register, 3);
5730 %}
5731 ins_pipe(iload_mask_mem);
5732 %}
5733
5734 // Load Integer to Short (16 bit signed)
5735 instruct loadI2S(iRegI dst, indOffset13m7 mem, immI_16 sixteen) %{
5736 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen));
5737 ins_cost(MEMORY_REF_COST);
5738
5739 size(4);
5740
5741 format %{ "LDSH $mem+2,$dst\t! int -> short" %}
5742 ins_encode %{
5743 __ ldsh($mem$$Address, $dst$$Register, 2);
5744 %}
5745 ins_pipe(iload_mask_mem);
5746 %}
5747
5748 // Load Integer to Unsigned Short (16 bit UNsigned)
5749 instruct loadI2US(iRegI dst, indOffset13m7 mem, immI_65535 mask) %{
5750 match(Set dst (AndI (LoadI mem) mask));
5751 ins_cost(MEMORY_REF_COST);
5752
5753 size(4);
5754
5755 format %{ "LDUH $mem+2,$dst\t! int -> ushort/char" %}
5756 ins_encode %{
5757 __ lduh($mem$$Address, $dst$$Register, 2);
5758 %}
5759 ins_pipe(iload_mask_mem);
5760 %}
5761
5762 // Load Integer into a Long Register
5763 instruct loadI2L(iRegL dst, memory mem) %{
5764 match(Set dst (ConvI2L (LoadI mem)));
5765 ins_cost(MEMORY_REF_COST);
5766
5767 size(4);
5768 format %{ "LDSW $mem,$dst\t! int -> long" %}
5769 ins_encode %{
5770 __ ldsw($mem$$Address, $dst$$Register);
5771 %}
5772 ins_pipe(iload_mask_mem);
5773 %}
5774
5775 // Load Integer with mask 0xFF into a Long Register
5776 instruct loadI2L_immI_255(iRegL dst, indOffset13m7 mem, immI_255 mask) %{
5777 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5778 ins_cost(MEMORY_REF_COST);
5779
5780 size(4);
5781 format %{ "LDUB $mem+3,$dst\t! int & 0xFF -> long" %}
5782 ins_encode %{
5783 __ ldub($mem$$Address, $dst$$Register, 3); // LSB is index+3 on BE
5784 %}
5785 ins_pipe(iload_mem);
5786 %}
5787
5788 // Load Integer with mask 0xFFFF into a Long Register
5789 instruct loadI2L_immI_65535(iRegL dst, indOffset13m7 mem, immI_65535 mask) %{
5790 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5791 ins_cost(MEMORY_REF_COST);
5792
5793 size(4);
5794 format %{ "LDUH $mem+2,$dst\t! int & 0xFFFF -> long" %}
5795 ins_encode %{
5796 __ lduh($mem$$Address, $dst$$Register, 2); // LSW is index+2 on BE
5797 %}
5798 ins_pipe(iload_mem);
5799 %}
5800
5801 // Load Integer with a 13-bit mask into a Long Register
5802 instruct loadI2L_immI13(iRegL dst, memory mem, immI13 mask) %{
5803 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5804 ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5805
5806 size(2*4);
5807 format %{ "LDUW $mem,$dst\t! int & 13-bit mask -> long\n\t"
5808 "AND $dst,$mask,$dst" %}
5809 ins_encode %{
5810 Register Rdst = $dst$$Register;
5811 __ lduw($mem$$Address, Rdst);
5812 __ and3(Rdst, $mask$$constant, Rdst);
5813 %}
5814 ins_pipe(iload_mem);
5815 %}
5816
5817 // Load Integer with a 32-bit mask into a Long Register
5818 instruct loadI2L_immI(iRegL dst, memory mem, immI mask, iRegL tmp) %{
5819 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5820 effect(TEMP dst, TEMP tmp);
5821 ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST);
5822
5823 size((3+1)*4); // set may use two instructions.
5824 format %{ "LDUW $mem,$dst\t! int & 32-bit mask -> long\n\t"
5825 "SET $mask,$tmp\n\t"
5826 "AND $dst,$tmp,$dst" %}
5827 ins_encode %{
5828 Register Rdst = $dst$$Register;
5829 Register Rtmp = $tmp$$Register;
5830 __ lduw($mem$$Address, Rdst);
5831 __ set($mask$$constant, Rtmp);
5832 __ and3(Rdst, Rtmp, Rdst);
5833 %}
5834 ins_pipe(iload_mem);
5835 %}
5836
5837 // Load Unsigned Integer into a Long Register
5838 instruct loadUI2L(iRegL dst, memory mem, immL_32bits mask) %{
5839 match(Set dst (AndL (ConvI2L (LoadI mem)) mask));
5840 ins_cost(MEMORY_REF_COST);
5841
5842 size(4);
5843 format %{ "LDUW $mem,$dst\t! uint -> long" %}
5844 ins_encode %{
5845 __ lduw($mem$$Address, $dst$$Register);
5846 %}
5847 ins_pipe(iload_mem);
5848 %}
5849
5850 // Load Long - aligned
5851 instruct loadL(iRegL dst, memory mem ) %{
5852 match(Set dst (LoadL mem));
5853 ins_cost(MEMORY_REF_COST);
5854
5855 size(4);
5856 format %{ "LDX $mem,$dst\t! long" %}
5857 ins_encode %{
5858 __ ldx($mem$$Address, $dst$$Register);
5859 %}
5860 ins_pipe(iload_mem);
5861 %}
5862
5863 // Load Long - UNaligned
5864 instruct loadL_unaligned(iRegL dst, memory mem, o7RegI tmp) %{
5865 match(Set dst (LoadL_unaligned mem));
5866 effect(KILL tmp);
5867 ins_cost(MEMORY_REF_COST*2+DEFAULT_COST);
5868 size(16);
5869 format %{ "LDUW $mem+4,R_O7\t! misaligned long\n"
5870 "\tLDUW $mem ,$dst\n"
5871 "\tSLLX #32, $dst, $dst\n"
5872 "\tOR $dst, R_O7, $dst" %}
5873 opcode(Assembler::lduw_op3);
5874 ins_encode(form3_mem_reg_long_unaligned_marshal( mem, dst ));
5875 ins_pipe(iload_mem);
5876 %}
5877
5878 // Load Range
5879 instruct loadRange(iRegI dst, memory mem) %{
5880 match(Set dst (LoadRange mem));
5881 ins_cost(MEMORY_REF_COST);
5882
5883 size(4);
5884 format %{ "LDUW $mem,$dst\t! range" %}
5885 opcode(Assembler::lduw_op3);
5886 ins_encode(simple_form3_mem_reg( mem, dst ) );
5887 ins_pipe(iload_mem);
5888 %}
5889
5890 // Load Integer into %f register (for fitos/fitod)
5891 instruct loadI_freg(regF dst, memory mem) %{
5892 match(Set dst (LoadI mem));
5893 ins_cost(MEMORY_REF_COST);
5894 size(4);
5895
5896 format %{ "LDF $mem,$dst\t! for fitos/fitod" %}
5897 opcode(Assembler::ldf_op3);
5898 ins_encode(simple_form3_mem_reg( mem, dst ) );
5899 ins_pipe(floadF_mem);
5900 %}
5901
5902 // Load Pointer
5903 instruct loadP(iRegP dst, memory mem) %{
5904 match(Set dst (LoadP mem));
5905 ins_cost(MEMORY_REF_COST);
5906 size(4);
5907
5908 #ifndef _LP64
5909 format %{ "LDUW $mem,$dst\t! ptr" %}
5910 ins_encode %{
5911 __ lduw($mem$$Address, $dst$$Register);
5912 %}
5913 #else
5914 format %{ "LDX $mem,$dst\t! ptr" %}
5915 ins_encode %{
5916 __ ldx($mem$$Address, $dst$$Register);
5917 %}
5918 #endif
5919 ins_pipe(iload_mem);
5920 %}
5921
5922 // Load Compressed Pointer
5923 instruct loadN(iRegN dst, memory mem) %{
5924 match(Set dst (LoadN mem));
5925 ins_cost(MEMORY_REF_COST);
5926 size(4);
5927
5928 format %{ "LDUW $mem,$dst\t! compressed ptr" %}
5929 ins_encode %{
5930 __ lduw($mem$$Address, $dst$$Register);
5931 %}
5932 ins_pipe(iload_mem);
5933 %}
5934
5935 // Load Klass Pointer
5936 instruct loadKlass(iRegP dst, memory mem) %{
5937 match(Set dst (LoadKlass mem));
5938 ins_cost(MEMORY_REF_COST);
5939 size(4);
5940
5941 #ifndef _LP64
5942 format %{ "LDUW $mem,$dst\t! klass ptr" %}
5943 ins_encode %{
5944 __ lduw($mem$$Address, $dst$$Register);
5945 %}
5946 #else
5947 format %{ "LDX $mem,$dst\t! klass ptr" %}
5948 ins_encode %{
5949 __ ldx($mem$$Address, $dst$$Register);
5950 %}
5951 #endif
5952 ins_pipe(iload_mem);
5953 %}
5954
5955 // Load narrow Klass Pointer
5956 instruct loadNKlass(iRegN dst, memory mem) %{
5957 match(Set dst (LoadNKlass mem));
5958 ins_cost(MEMORY_REF_COST);
5959 size(4);
5960
5961 format %{ "LDUW $mem,$dst\t! compressed klass ptr" %}
5962 ins_encode %{
5963 __ lduw($mem$$Address, $dst$$Register);
5964 %}
5965 ins_pipe(iload_mem);
5966 %}
5967
5968 // Load Double
5969 instruct loadD(regD dst, memory mem) %{
5970 match(Set dst (LoadD mem));
5971 ins_cost(MEMORY_REF_COST);
5972
5973 size(4);
5974 format %{ "LDDF $mem,$dst" %}
5975 opcode(Assembler::lddf_op3);
5976 ins_encode(simple_form3_mem_reg( mem, dst ) );
5977 ins_pipe(floadD_mem);
5978 %}
5979
5980 // Load Double - UNaligned
5981 instruct loadD_unaligned(regD_low dst, memory mem ) %{
5982 match(Set dst (LoadD_unaligned mem));
5983 ins_cost(MEMORY_REF_COST*2+DEFAULT_COST);
5984 size(8);
5985 format %{ "LDF $mem ,$dst.hi\t! misaligned double\n"
5986 "\tLDF $mem+4,$dst.lo\t!" %}
5987 opcode(Assembler::ldf_op3);
5988 ins_encode( form3_mem_reg_double_unaligned( mem, dst ));
5989 ins_pipe(iload_mem);
5990 %}
5991
5992 // Load Float
5993 instruct loadF(regF dst, memory mem) %{
5994 match(Set dst (LoadF mem));
5995 ins_cost(MEMORY_REF_COST);
5996
5997 size(4);
5998 format %{ "LDF $mem,$dst" %}
5999 opcode(Assembler::ldf_op3);
6000 ins_encode(simple_form3_mem_reg( mem, dst ) );
6001 ins_pipe(floadF_mem);
6002 %}
6003
6004 // Load Constant
6005 instruct loadConI( iRegI dst, immI src ) %{
6006 match(Set dst src);
6007 ins_cost(DEFAULT_COST * 3/2);
6008 format %{ "SET $src,$dst" %}
6009 ins_encode( Set32(src, dst) );
6010 ins_pipe(ialu_hi_lo_reg);
6011 %}
6012
6013 instruct loadConI13( iRegI dst, immI13 src ) %{
6014 match(Set dst src);
6015
6016 size(4);
6017 format %{ "MOV $src,$dst" %}
6018 ins_encode( Set13( src, dst ) );
6019 ins_pipe(ialu_imm);
6020 %}
6021
6022 #ifndef _LP64
6023 instruct loadConP(iRegP dst, immP con) %{
6024 match(Set dst con);
6025 ins_cost(DEFAULT_COST * 3/2);
6026 format %{ "SET $con,$dst\t!ptr" %}
6027 ins_encode %{
6028 relocInfo::relocType constant_reloc = _opnds[1]->constant_reloc();
6029 intptr_t val = $con$$constant;
6030 if (constant_reloc == relocInfo::oop_type) {
6031 __ set_oop_constant((jobject) val, $dst$$Register);
6032 } else if (constant_reloc == relocInfo::metadata_type) {
6033 __ set_metadata_constant((Metadata*)val, $dst$$Register);
6034 } else { // non-oop pointers, e.g. card mark base, heap top
6035 assert(constant_reloc == relocInfo::none, "unexpected reloc type");
6036 __ set(val, $dst$$Register);
6037 }
6038 %}
6039 ins_pipe(loadConP);
6040 %}
6041 #else
6042 instruct loadConP_set(iRegP dst, immP_set con) %{
6043 match(Set dst con);
6044 ins_cost(DEFAULT_COST * 3/2);
6045 format %{ "SET $con,$dst\t! ptr" %}
6046 ins_encode %{
6047 relocInfo::relocType constant_reloc = _opnds[1]->constant_reloc();
6048 intptr_t val = $con$$constant;
6049 if (constant_reloc == relocInfo::oop_type) {
6050 __ set_oop_constant((jobject) val, $dst$$Register);
6051 } else if (constant_reloc == relocInfo::metadata_type) {
6052 __ set_metadata_constant((Metadata*)val, $dst$$Register);
6053 } else { // non-oop pointers, e.g. card mark base, heap top
6054 assert(constant_reloc == relocInfo::none, "unexpected reloc type");
6055 __ set(val, $dst$$Register);
6056 }
6057 %}
6058 ins_pipe(loadConP);
6059 %}
6060
6061 instruct loadConP_load(iRegP dst, immP_load con) %{
6062 match(Set dst con);
6063 ins_cost(MEMORY_REF_COST);
6064 format %{ "LD [$constanttablebase + $constantoffset],$dst\t! load from constant table: ptr=$con" %}
6065 ins_encode %{
6066 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $dst$$Register);
6067 __ ld_ptr($constanttablebase, con_offset, $dst$$Register);
6068 %}
6069 ins_pipe(loadConP);
6070 %}
6071
6072 instruct loadConP_no_oop_cheap(iRegP dst, immP_no_oop_cheap con) %{
6073 match(Set dst con);
6074 ins_cost(DEFAULT_COST * 3/2);
6075 format %{ "SET $con,$dst\t! non-oop ptr" %}
6076 ins_encode %{
6077 __ set($con$$constant, $dst$$Register);
6078 %}
6079 ins_pipe(loadConP);
6080 %}
6081 #endif // _LP64
6082
6083 instruct loadConP0(iRegP dst, immP0 src) %{
6084 match(Set dst src);
6085
6086 size(4);
6087 format %{ "CLR $dst\t!ptr" %}
6088 ins_encode %{
6089 __ clr($dst$$Register);
6090 %}
6091 ins_pipe(ialu_imm);
6092 %}
6093
6094 instruct loadConP_poll(iRegP dst, immP_poll src) %{
6095 match(Set dst src);
6096 ins_cost(DEFAULT_COST);
6097 format %{ "SET $src,$dst\t!ptr" %}
6098 ins_encode %{
6099 AddressLiteral polling_page(os::get_polling_page());
6100 __ sethi(polling_page, reg_to_register_object($dst$$reg));
6101 %}
6102 ins_pipe(loadConP_poll);
6103 %}
6104
6105 instruct loadConN0(iRegN dst, immN0 src) %{
6106 match(Set dst src);
6107
6108 size(4);
6109 format %{ "CLR $dst\t! compressed NULL ptr" %}
6110 ins_encode %{
6111 __ clr($dst$$Register);
6112 %}
6113 ins_pipe(ialu_imm);
6114 %}
6115
6116 instruct loadConN(iRegN dst, immN src) %{
6117 match(Set dst src);
6118 ins_cost(DEFAULT_COST * 3/2);
6119 format %{ "SET $src,$dst\t! compressed ptr" %}
6120 ins_encode %{
6121 Register dst = $dst$$Register;
6122 __ set_narrow_oop((jobject)$src$$constant, dst);
6123 %}
6124 ins_pipe(ialu_hi_lo_reg);
6125 %}
6126
6127 instruct loadConNKlass(iRegN dst, immNKlass src) %{
6128 match(Set dst src);
6129 ins_cost(DEFAULT_COST * 3/2);
6130 format %{ "SET $src,$dst\t! compressed klass ptr" %}
6131 ins_encode %{
6132 Register dst = $dst$$Register;
6133 __ set_narrow_klass((Klass*)$src$$constant, dst);
6134 %}
6135 ins_pipe(ialu_hi_lo_reg);
6136 %}
6137
6138 // Materialize long value (predicated by immL_cheap).
6139 instruct loadConL_set64(iRegL dst, immL_cheap con, o7RegL tmp) %{
6140 match(Set dst con);
6141 effect(KILL tmp);
6142 ins_cost(DEFAULT_COST * 3);
6143 format %{ "SET64 $con,$dst KILL $tmp\t! cheap long" %}
6144 ins_encode %{
6145 __ set64($con$$constant, $dst$$Register, $tmp$$Register);
6146 %}
6147 ins_pipe(loadConL);
6148 %}
6149
6150 // Load long value from constant table (predicated by immL_expensive).
6151 instruct loadConL_ldx(iRegL dst, immL_expensive con) %{
6152 match(Set dst con);
6153 ins_cost(MEMORY_REF_COST);
6154 format %{ "LDX [$constanttablebase + $constantoffset],$dst\t! load from constant table: long=$con" %}
6155 ins_encode %{
6156 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $dst$$Register);
6157 __ ldx($constanttablebase, con_offset, $dst$$Register);
6158 %}
6159 ins_pipe(loadConL);
6160 %}
6161
6162 instruct loadConL0( iRegL dst, immL0 src ) %{
6163 match(Set dst src);
6164 ins_cost(DEFAULT_COST);
6165 size(4);
6166 format %{ "CLR $dst\t! long" %}
6167 ins_encode( Set13( src, dst ) );
6168 ins_pipe(ialu_imm);
6169 %}
6170
6171 instruct loadConL13( iRegL dst, immL13 src ) %{
6172 match(Set dst src);
6173 ins_cost(DEFAULT_COST * 2);
6174
6175 size(4);
6176 format %{ "MOV $src,$dst\t! long" %}
6177 ins_encode( Set13( src, dst ) );
6178 ins_pipe(ialu_imm);
6179 %}
6180
6181 instruct loadConF(regF dst, immF con, o7RegI tmp) %{
6182 match(Set dst con);
6183 effect(KILL tmp);
6184 format %{ "LDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: float=$con" %}
6185 ins_encode %{
6186 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $tmp$$Register);
6187 __ ldf(FloatRegisterImpl::S, $constanttablebase, con_offset, $dst$$FloatRegister);
6188 %}
6189 ins_pipe(loadConFD);
6190 %}
6191
6192 instruct loadConD(regD dst, immD con, o7RegI tmp) %{
6193 match(Set dst con);
6194 effect(KILL tmp);
6195 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: double=$con" %}
6196 ins_encode %{
6197 // XXX This is a quick fix for 6833573.
6198 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset($con), $dst$$FloatRegister);
6199 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $tmp$$Register);
6200 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
6201 %}
6202 ins_pipe(loadConFD);
6203 %}
6204
6205 // Prefetch instructions.
6206 // Must be safe to execute with invalid address (cannot fault).
6207
6208 instruct prefetchr( memory mem ) %{
6209 match( PrefetchRead mem );
6210 ins_cost(MEMORY_REF_COST);
6211 size(4);
6212
6213 format %{ "PREFETCH $mem,0\t! Prefetch read-many" %}
6214 opcode(Assembler::prefetch_op3);
6215 ins_encode( form3_mem_prefetch_read( mem ) );
6216 ins_pipe(iload_mem);
6217 %}
6218
6219 instruct prefetchw( memory mem ) %{
6220 match( PrefetchWrite mem );
6221 ins_cost(MEMORY_REF_COST);
6222 size(4);
6223
6224 format %{ "PREFETCH $mem,2\t! Prefetch write-many (and read)" %}
6225 opcode(Assembler::prefetch_op3);
6226 ins_encode( form3_mem_prefetch_write( mem ) );
6227 ins_pipe(iload_mem);
6228 %}
6229
6230 // Prefetch instructions for allocation.
6231
6232 instruct prefetchAlloc( memory mem ) %{
6233 predicate(AllocatePrefetchInstr == 0);
6234 match( PrefetchAllocation mem );
6235 ins_cost(MEMORY_REF_COST);
6236 size(4);
6237
6238 format %{ "PREFETCH $mem,2\t! Prefetch allocation" %}
6239 opcode(Assembler::prefetch_op3);
6240 ins_encode( form3_mem_prefetch_write( mem ) );
6241 ins_pipe(iload_mem);
6242 %}
6243
6244 // Use BIS instruction to prefetch for allocation.
6245 // Could fault, need space at the end of TLAB.
6246 instruct prefetchAlloc_bis( iRegP dst ) %{
6247 predicate(AllocatePrefetchInstr == 1);
6248 match( PrefetchAllocation dst );
6249 ins_cost(MEMORY_REF_COST);
6250 size(4);
6251
6252 format %{ "STXA [$dst]\t! // Prefetch allocation using BIS" %}
6253 ins_encode %{
6254 __ stxa(G0, $dst$$Register, G0, Assembler::ASI_ST_BLKINIT_PRIMARY);
6255 %}
6256 ins_pipe(istore_mem_reg);
6257 %}
6258
6259 // Next code is used for finding next cache line address to prefetch.
6260 #ifndef _LP64
6261 instruct cacheLineAdr( iRegP dst, iRegP src, immI13 mask ) %{
6262 match(Set dst (CastX2P (AndI (CastP2X src) mask)));
6263 ins_cost(DEFAULT_COST);
6264 size(4);
6265
6266 format %{ "AND $src,$mask,$dst\t! next cache line address" %}
6267 ins_encode %{
6268 __ and3($src$$Register, $mask$$constant, $dst$$Register);
6269 %}
6270 ins_pipe(ialu_reg_imm);
6271 %}
6272 #else
6273 instruct cacheLineAdr( iRegP dst, iRegP src, immL13 mask ) %{
6274 match(Set dst (CastX2P (AndL (CastP2X src) mask)));
6275 ins_cost(DEFAULT_COST);
6276 size(4);
6277
6278 format %{ "AND $src,$mask,$dst\t! next cache line address" %}
6279 ins_encode %{
6280 __ and3($src$$Register, $mask$$constant, $dst$$Register);
6281 %}
6282 ins_pipe(ialu_reg_imm);
6283 %}
6284 #endif
6285
6286 //----------Store Instructions-------------------------------------------------
6287 // Store Byte
6288 instruct storeB(memory mem, iRegI src) %{
6289 match(Set mem (StoreB mem src));
6290 ins_cost(MEMORY_REF_COST);
6291
6292 size(4);
6293 format %{ "STB $src,$mem\t! byte" %}
6294 opcode(Assembler::stb_op3);
6295 ins_encode(simple_form3_mem_reg( mem, src ) );
6296 ins_pipe(istore_mem_reg);
6297 %}
6298
6299 instruct storeB0(memory mem, immI0 src) %{
6300 match(Set mem (StoreB mem src));
6301 ins_cost(MEMORY_REF_COST);
6302
6303 size(4);
6304 format %{ "STB $src,$mem\t! byte" %}
6305 opcode(Assembler::stb_op3);
6306 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6307 ins_pipe(istore_mem_zero);
6308 %}
6309
6310 instruct storeCM0(memory mem, immI0 src) %{
6311 match(Set mem (StoreCM mem src));
6312 ins_cost(MEMORY_REF_COST);
6313
6314 size(4);
6315 format %{ "STB $src,$mem\t! CMS card-mark byte 0" %}
6316 opcode(Assembler::stb_op3);
6317 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6318 ins_pipe(istore_mem_zero);
6319 %}
6320
6321 // Store Char/Short
6322 instruct storeC(memory mem, iRegI src) %{
6323 match(Set mem (StoreC mem src));
6324 ins_cost(MEMORY_REF_COST);
6325
6326 size(4);
6327 format %{ "STH $src,$mem\t! short" %}
6328 opcode(Assembler::sth_op3);
6329 ins_encode(simple_form3_mem_reg( mem, src ) );
6330 ins_pipe(istore_mem_reg);
6331 %}
6332
6333 instruct storeC0(memory mem, immI0 src) %{
6334 match(Set mem (StoreC mem src));
6335 ins_cost(MEMORY_REF_COST);
6336
6337 size(4);
6338 format %{ "STH $src,$mem\t! short" %}
6339 opcode(Assembler::sth_op3);
6340 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6341 ins_pipe(istore_mem_zero);
6342 %}
6343
6344 // Store Integer
6345 instruct storeI(memory mem, iRegI src) %{
6346 match(Set mem (StoreI mem src));
6347 ins_cost(MEMORY_REF_COST);
6348
6349 size(4);
6350 format %{ "STW $src,$mem" %}
6351 opcode(Assembler::stw_op3);
6352 ins_encode(simple_form3_mem_reg( mem, src ) );
6353 ins_pipe(istore_mem_reg);
6354 %}
6355
6356 // Store Long
6357 instruct storeL(memory mem, iRegL src) %{
6358 match(Set mem (StoreL mem src));
6359 ins_cost(MEMORY_REF_COST);
6360 size(4);
6361 format %{ "STX $src,$mem\t! long" %}
6362 opcode(Assembler::stx_op3);
6363 ins_encode(simple_form3_mem_reg( mem, src ) );
6364 ins_pipe(istore_mem_reg);
6365 %}
6366
6367 instruct storeI0(memory mem, immI0 src) %{
6368 match(Set mem (StoreI mem src));
6369 ins_cost(MEMORY_REF_COST);
6370
6371 size(4);
6372 format %{ "STW $src,$mem" %}
6373 opcode(Assembler::stw_op3);
6374 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6375 ins_pipe(istore_mem_zero);
6376 %}
6377
6378 instruct storeL0(memory mem, immL0 src) %{
6379 match(Set mem (StoreL mem src));
6380 ins_cost(MEMORY_REF_COST);
6381
6382 size(4);
6383 format %{ "STX $src,$mem" %}
6384 opcode(Assembler::stx_op3);
6385 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6386 ins_pipe(istore_mem_zero);
6387 %}
6388
6389 // Store Integer from float register (used after fstoi)
6390 instruct storeI_Freg(memory mem, regF src) %{
6391 match(Set mem (StoreI mem src));
6392 ins_cost(MEMORY_REF_COST);
6393
6394 size(4);
6395 format %{ "STF $src,$mem\t! after fstoi/fdtoi" %}
6396 opcode(Assembler::stf_op3);
6397 ins_encode(simple_form3_mem_reg( mem, src ) );
6398 ins_pipe(fstoreF_mem_reg);
6399 %}
6400
6401 // Store Pointer
6402 instruct storeP(memory dst, sp_ptr_RegP src) %{
6403 match(Set dst (StoreP dst src));
6404 ins_cost(MEMORY_REF_COST);
6405 size(4);
6406
6407 #ifndef _LP64
6408 format %{ "STW $src,$dst\t! ptr" %}
6409 opcode(Assembler::stw_op3, 0, REGP_OP);
6410 #else
6411 format %{ "STX $src,$dst\t! ptr" %}
6412 opcode(Assembler::stx_op3, 0, REGP_OP);
6413 #endif
6414 ins_encode( form3_mem_reg( dst, src ) );
6415 ins_pipe(istore_mem_spORreg);
6416 %}
6417
6418 instruct storeP0(memory dst, immP0 src) %{
6419 match(Set dst (StoreP dst src));
6420 ins_cost(MEMORY_REF_COST);
6421 size(4);
6422
6423 #ifndef _LP64
6424 format %{ "STW $src,$dst\t! ptr" %}
6425 opcode(Assembler::stw_op3, 0, REGP_OP);
6426 #else
6427 format %{ "STX $src,$dst\t! ptr" %}
6428 opcode(Assembler::stx_op3, 0, REGP_OP);
6429 #endif
6430 ins_encode( form3_mem_reg( dst, R_G0 ) );
6431 ins_pipe(istore_mem_zero);
6432 %}
6433
6434 // Store Compressed Pointer
6435 instruct storeN(memory dst, iRegN src) %{
6436 match(Set dst (StoreN dst src));
6437 ins_cost(MEMORY_REF_COST);
6438 size(4);
6439
6440 format %{ "STW $src,$dst\t! compressed ptr" %}
6441 ins_encode %{
6442 Register base = as_Register($dst$$base);
6443 Register index = as_Register($dst$$index);
6444 Register src = $src$$Register;
6445 if (index != G0) {
6446 __ stw(src, base, index);
6447 } else {
6448 __ stw(src, base, $dst$$disp);
6449 }
6450 %}
6451 ins_pipe(istore_mem_spORreg);
6452 %}
6453
6454 instruct storeNKlass(memory dst, iRegN src) %{
6455 match(Set dst (StoreNKlass dst src));
6456 ins_cost(MEMORY_REF_COST);
6457 size(4);
6458
6459 format %{ "STW $src,$dst\t! compressed klass ptr" %}
6460 ins_encode %{
6461 Register base = as_Register($dst$$base);
6462 Register index = as_Register($dst$$index);
6463 Register src = $src$$Register;
6464 if (index != G0) {
6465 __ stw(src, base, index);
6466 } else {
6467 __ stw(src, base, $dst$$disp);
6468 }
6469 %}
6470 ins_pipe(istore_mem_spORreg);
6471 %}
6472
6473 instruct storeN0(memory dst, immN0 src) %{
6474 match(Set dst (StoreN dst src));
6475 ins_cost(MEMORY_REF_COST);
6476 size(4);
6477
6478 format %{ "STW $src,$dst\t! compressed ptr" %}
6479 ins_encode %{
6480 Register base = as_Register($dst$$base);
6481 Register index = as_Register($dst$$index);
6482 if (index != G0) {
6483 __ stw(0, base, index);
6484 } else {
6485 __ stw(0, base, $dst$$disp);
6486 }
6487 %}
6488 ins_pipe(istore_mem_zero);
6489 %}
6490
6491 // Store Double
6492 instruct storeD( memory mem, regD src) %{
6493 match(Set mem (StoreD mem src));
6494 ins_cost(MEMORY_REF_COST);
6495
6496 size(4);
6497 format %{ "STDF $src,$mem" %}
6498 opcode(Assembler::stdf_op3);
6499 ins_encode(simple_form3_mem_reg( mem, src ) );
6500 ins_pipe(fstoreD_mem_reg);
6501 %}
6502
6503 instruct storeD0( memory mem, immD0 src) %{
6504 match(Set mem (StoreD mem src));
6505 ins_cost(MEMORY_REF_COST);
6506
6507 size(4);
6508 format %{ "STX $src,$mem" %}
6509 opcode(Assembler::stx_op3);
6510 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6511 ins_pipe(fstoreD_mem_zero);
6512 %}
6513
6514 // Store Float
6515 instruct storeF( memory mem, regF src) %{
6516 match(Set mem (StoreF mem src));
6517 ins_cost(MEMORY_REF_COST);
6518
6519 size(4);
6520 format %{ "STF $src,$mem" %}
6521 opcode(Assembler::stf_op3);
6522 ins_encode(simple_form3_mem_reg( mem, src ) );
6523 ins_pipe(fstoreF_mem_reg);
6524 %}
6525
6526 instruct storeF0( memory mem, immF0 src) %{
6527 match(Set mem (StoreF mem src));
6528 ins_cost(MEMORY_REF_COST);
6529
6530 size(4);
6531 format %{ "STW $src,$mem\t! storeF0" %}
6532 opcode(Assembler::stw_op3);
6533 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6534 ins_pipe(fstoreF_mem_zero);
6535 %}
6536
6537 // Convert oop pointer into compressed form
6538 instruct encodeHeapOop(iRegN dst, iRegP src) %{
6539 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull);
6540 match(Set dst (EncodeP src));
6541 format %{ "encode_heap_oop $src, $dst" %}
6542 ins_encode %{
6543 __ encode_heap_oop($src$$Register, $dst$$Register);
6544 %}
6545 ins_pipe(ialu_reg);
6546 %}
6547
6548 instruct encodeHeapOop_not_null(iRegN dst, iRegP src) %{
6549 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull);
6550 match(Set dst (EncodeP src));
6551 format %{ "encode_heap_oop_not_null $src, $dst" %}
6552 ins_encode %{
6553 __ encode_heap_oop_not_null($src$$Register, $dst$$Register);
6554 %}
6555 ins_pipe(ialu_reg);
6556 %}
6557
6558 instruct decodeHeapOop(iRegP dst, iRegN src) %{
6559 predicate(n->bottom_type()->is_oopptr()->ptr() != TypePtr::NotNull &&
6560 n->bottom_type()->is_oopptr()->ptr() != TypePtr::Constant);
6561 match(Set dst (DecodeN src));
6562 format %{ "decode_heap_oop $src, $dst" %}
6563 ins_encode %{
6564 __ decode_heap_oop($src$$Register, $dst$$Register);
6565 %}
6566 ins_pipe(ialu_reg);
6567 %}
6568
6569 instruct decodeHeapOop_not_null(iRegP dst, iRegN src) %{
6570 predicate(n->bottom_type()->is_oopptr()->ptr() == TypePtr::NotNull ||
6571 n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant);
6572 match(Set dst (DecodeN src));
6573 format %{ "decode_heap_oop_not_null $src, $dst" %}
6574 ins_encode %{
6575 __ decode_heap_oop_not_null($src$$Register, $dst$$Register);
6576 %}
6577 ins_pipe(ialu_reg);
6578 %}
6579
6580 instruct encodeKlass_not_null(iRegN dst, iRegP src) %{
6581 match(Set dst (EncodePKlass src));
6582 format %{ "encode_klass_not_null $src, $dst" %}
6583 ins_encode %{
6584 __ encode_klass_not_null($src$$Register, $dst$$Register);
6585 %}
6586 ins_pipe(ialu_reg);
6587 %}
6588
6589 instruct decodeKlass_not_null(iRegP dst, iRegN src) %{
6590 match(Set dst (DecodeNKlass src));
6591 format %{ "decode_klass_not_null $src, $dst" %}
6592 ins_encode %{
6593 __ decode_klass_not_null($src$$Register, $dst$$Register);
6594 %}
6595 ins_pipe(ialu_reg);
6596 %}
6597
6598 //----------MemBar Instructions-----------------------------------------------
6599 // Memory barrier flavors
6600
6601 instruct membar_acquire() %{
6602 match(MemBarAcquire);
6603 ins_cost(4*MEMORY_REF_COST);
6604
6605 size(0);
6606 format %{ "MEMBAR-acquire" %}
6607 ins_encode( enc_membar_acquire );
6608 ins_pipe(long_memory_op);
6609 %}
6610
6611 instruct membar_acquire_lock() %{
6612 match(MemBarAcquireLock);
6613 ins_cost(0);
6614
6615 size(0);
6616 format %{ "!MEMBAR-acquire (CAS in prior FastLock so empty encoding)" %}
6617 ins_encode( );
6618 ins_pipe(empty);
6619 %}
6620
6621 instruct membar_release() %{
6622 match(MemBarRelease);
6623 ins_cost(4*MEMORY_REF_COST);
6624
6625 size(0);
6626 format %{ "MEMBAR-release" %}
6627 ins_encode( enc_membar_release );
6628 ins_pipe(long_memory_op);
6629 %}
6630
6631 instruct membar_release_lock() %{
6632 match(MemBarReleaseLock);
6633 ins_cost(0);
6634
6635 size(0);
6636 format %{ "!MEMBAR-release (CAS in succeeding FastUnlock so empty encoding)" %}
6637 ins_encode( );
6638 ins_pipe(empty);
6639 %}
6640
6641 instruct membar_volatile() %{
6642 match(MemBarVolatile);
6643 ins_cost(4*MEMORY_REF_COST);
6644
6645 size(4);
6646 format %{ "MEMBAR-volatile" %}
6647 ins_encode( enc_membar_volatile );
6648 ins_pipe(long_memory_op);
6649 %}
6650
6651 instruct unnecessary_membar_volatile() %{
6652 match(MemBarVolatile);
6653 predicate(Matcher::post_store_load_barrier(n));
6654 ins_cost(0);
6655
6656 size(0);
6657 format %{ "!MEMBAR-volatile (unnecessary so empty encoding)" %}
6658 ins_encode( );
6659 ins_pipe(empty);
6660 %}
6661
6662 instruct membar_storestore() %{
6663 match(MemBarStoreStore);
6664 ins_cost(0);
6665
6666 size(0);
6667 format %{ "!MEMBAR-storestore (empty encoding)" %}
6668 ins_encode( );
6669 ins_pipe(empty);
6670 %}
6671
6672 //----------Register Move Instructions-----------------------------------------
6673 instruct roundDouble_nop(regD dst) %{
6674 match(Set dst (RoundDouble dst));
6675 ins_cost(0);
6676 // SPARC results are already "rounded" (i.e., normal-format IEEE)
6677 ins_encode( );
6678 ins_pipe(empty);
6679 %}
6680
6681
6682 instruct roundFloat_nop(regF dst) %{
6683 match(Set dst (RoundFloat dst));
6684 ins_cost(0);
6685 // SPARC results are already "rounded" (i.e., normal-format IEEE)
6686 ins_encode( );
6687 ins_pipe(empty);
6688 %}
6689
6690
6691 // Cast Index to Pointer for unsafe natives
6692 instruct castX2P(iRegX src, iRegP dst) %{
6693 match(Set dst (CastX2P src));
6694
6695 format %{ "MOV $src,$dst\t! IntX->Ptr" %}
6696 ins_encode( form3_g0_rs2_rd_move( src, dst ) );
6697 ins_pipe(ialu_reg);
6698 %}
6699
6700 // Cast Pointer to Index for unsafe natives
6701 instruct castP2X(iRegP src, iRegX dst) %{
6702 match(Set dst (CastP2X src));
6703
6704 format %{ "MOV $src,$dst\t! Ptr->IntX" %}
6705 ins_encode( form3_g0_rs2_rd_move( src, dst ) );
6706 ins_pipe(ialu_reg);
6707 %}
6708
6709 instruct stfSSD(stackSlotD stkSlot, regD src) %{
6710 // %%%% TO DO: Tell the coalescer that this kind of node is a copy!
6711 match(Set stkSlot src); // chain rule
6712 ins_cost(MEMORY_REF_COST);
6713 format %{ "STDF $src,$stkSlot\t!stk" %}
6714 opcode(Assembler::stdf_op3);
6715 ins_encode(simple_form3_mem_reg(stkSlot, src));
6716 ins_pipe(fstoreD_stk_reg);
6717 %}
6718
6719 instruct ldfSSD(regD dst, stackSlotD stkSlot) %{
6720 // %%%% TO DO: Tell the coalescer that this kind of node is a copy!
6721 match(Set dst stkSlot); // chain rule
6722 ins_cost(MEMORY_REF_COST);
6723 format %{ "LDDF $stkSlot,$dst\t!stk" %}
6724 opcode(Assembler::lddf_op3);
6725 ins_encode(simple_form3_mem_reg(stkSlot, dst));
6726 ins_pipe(floadD_stk);
6727 %}
6728
6729 instruct stfSSF(stackSlotF stkSlot, regF src) %{
6730 // %%%% TO DO: Tell the coalescer that this kind of node is a copy!
6731 match(Set stkSlot src); // chain rule
6732 ins_cost(MEMORY_REF_COST);
6733 format %{ "STF $src,$stkSlot\t!stk" %}
6734 opcode(Assembler::stf_op3);
6735 ins_encode(simple_form3_mem_reg(stkSlot, src));
6736 ins_pipe(fstoreF_stk_reg);
6737 %}
6738
6739 //----------Conditional Move---------------------------------------------------
6740 // Conditional move
6741 instruct cmovIP_reg(cmpOpP cmp, flagsRegP pcc, iRegI dst, iRegI src) %{
6742 match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src)));
6743 ins_cost(150);
6744 format %{ "MOV$cmp $pcc,$src,$dst" %}
6745 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6746 ins_pipe(ialu_reg);
6747 %}
6748
6749 instruct cmovIP_imm(cmpOpP cmp, flagsRegP pcc, iRegI dst, immI11 src) %{
6750 match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src)));
6751 ins_cost(140);
6752 format %{ "MOV$cmp $pcc,$src,$dst" %}
6753 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) );
6754 ins_pipe(ialu_imm);
6755 %}
6756
6757 instruct cmovII_reg(cmpOp cmp, flagsReg icc, iRegI dst, iRegI src) %{
6758 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6759 ins_cost(150);
6760 size(4);
6761 format %{ "MOV$cmp $icc,$src,$dst" %}
6762 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6763 ins_pipe(ialu_reg);
6764 %}
6765
6766 instruct cmovII_imm(cmpOp cmp, flagsReg icc, iRegI dst, immI11 src) %{
6767 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6768 ins_cost(140);
6769 size(4);
6770 format %{ "MOV$cmp $icc,$src,$dst" %}
6771 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6772 ins_pipe(ialu_imm);
6773 %}
6774
6775 instruct cmovIIu_reg(cmpOpU cmp, flagsRegU icc, iRegI dst, iRegI src) %{
6776 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6777 ins_cost(150);
6778 size(4);
6779 format %{ "MOV$cmp $icc,$src,$dst" %}
6780 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6781 ins_pipe(ialu_reg);
6782 %}
6783
6784 instruct cmovIIu_imm(cmpOpU cmp, flagsRegU icc, iRegI dst, immI11 src) %{
6785 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6786 ins_cost(140);
6787 size(4);
6788 format %{ "MOV$cmp $icc,$src,$dst" %}
6789 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6790 ins_pipe(ialu_imm);
6791 %}
6792
6793 instruct cmovIF_reg(cmpOpF cmp, flagsRegF fcc, iRegI dst, iRegI src) %{
6794 match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src)));
6795 ins_cost(150);
6796 size(4);
6797 format %{ "MOV$cmp $fcc,$src,$dst" %}
6798 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6799 ins_pipe(ialu_reg);
6800 %}
6801
6802 instruct cmovIF_imm(cmpOpF cmp, flagsRegF fcc, iRegI dst, immI11 src) %{
6803 match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src)));
6804 ins_cost(140);
6805 size(4);
6806 format %{ "MOV$cmp $fcc,$src,$dst" %}
6807 ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) );
6808 ins_pipe(ialu_imm);
6809 %}
6810
6811 // Conditional move for RegN. Only cmov(reg,reg).
6812 instruct cmovNP_reg(cmpOpP cmp, flagsRegP pcc, iRegN dst, iRegN src) %{
6813 match(Set dst (CMoveN (Binary cmp pcc) (Binary dst src)));
6814 ins_cost(150);
6815 format %{ "MOV$cmp $pcc,$src,$dst" %}
6816 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6817 ins_pipe(ialu_reg);
6818 %}
6819
6820 // This instruction also works with CmpN so we don't need cmovNN_reg.
6821 instruct cmovNI_reg(cmpOp cmp, flagsReg icc, iRegN dst, iRegN src) %{
6822 match(Set dst (CMoveN (Binary cmp icc) (Binary dst src)));
6823 ins_cost(150);
6824 size(4);
6825 format %{ "MOV$cmp $icc,$src,$dst" %}
6826 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6827 ins_pipe(ialu_reg);
6828 %}
6829
6830 // This instruction also works with CmpN so we don't need cmovNN_reg.
6831 instruct cmovNIu_reg(cmpOpU cmp, flagsRegU icc, iRegN dst, iRegN src) %{
6832 match(Set dst (CMoveN (Binary cmp icc) (Binary dst src)));
6833 ins_cost(150);
6834 size(4);
6835 format %{ "MOV$cmp $icc,$src,$dst" %}
6836 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6837 ins_pipe(ialu_reg);
6838 %}
6839
6840 instruct cmovNF_reg(cmpOpF cmp, flagsRegF fcc, iRegN dst, iRegN src) %{
6841 match(Set dst (CMoveN (Binary cmp fcc) (Binary dst src)));
6842 ins_cost(150);
6843 size(4);
6844 format %{ "MOV$cmp $fcc,$src,$dst" %}
6845 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6846 ins_pipe(ialu_reg);
6847 %}
6848
6849 // Conditional move
6850 instruct cmovPP_reg(cmpOpP cmp, flagsRegP pcc, iRegP dst, iRegP src) %{
6851 match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src)));
6852 ins_cost(150);
6853 format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %}
6854 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6855 ins_pipe(ialu_reg);
6856 %}
6857
6858 instruct cmovPP_imm(cmpOpP cmp, flagsRegP pcc, iRegP dst, immP0 src) %{
6859 match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src)));
6860 ins_cost(140);
6861 format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %}
6862 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) );
6863 ins_pipe(ialu_imm);
6864 %}
6865
6866 // This instruction also works with CmpN so we don't need cmovPN_reg.
6867 instruct cmovPI_reg(cmpOp cmp, flagsReg icc, iRegP dst, iRegP src) %{
6868 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6869 ins_cost(150);
6870
6871 size(4);
6872 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %}
6873 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6874 ins_pipe(ialu_reg);
6875 %}
6876
6877 instruct cmovPIu_reg(cmpOpU cmp, flagsRegU icc, iRegP dst, iRegP src) %{
6878 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6879 ins_cost(150);
6880
6881 size(4);
6882 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %}
6883 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6884 ins_pipe(ialu_reg);
6885 %}
6886
6887 instruct cmovPI_imm(cmpOp cmp, flagsReg icc, iRegP dst, immP0 src) %{
6888 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6889 ins_cost(140);
6890
6891 size(4);
6892 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %}
6893 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6894 ins_pipe(ialu_imm);
6895 %}
6896
6897 instruct cmovPIu_imm(cmpOpU cmp, flagsRegU icc, iRegP dst, immP0 src) %{
6898 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6899 ins_cost(140);
6900
6901 size(4);
6902 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %}
6903 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6904 ins_pipe(ialu_imm);
6905 %}
6906
6907 instruct cmovPF_reg(cmpOpF cmp, flagsRegF fcc, iRegP dst, iRegP src) %{
6908 match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src)));
6909 ins_cost(150);
6910 size(4);
6911 format %{ "MOV$cmp $fcc,$src,$dst" %}
6912 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6913 ins_pipe(ialu_imm);
6914 %}
6915
6916 instruct cmovPF_imm(cmpOpF cmp, flagsRegF fcc, iRegP dst, immP0 src) %{
6917 match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src)));
6918 ins_cost(140);
6919 size(4);
6920 format %{ "MOV$cmp $fcc,$src,$dst" %}
6921 ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) );
6922 ins_pipe(ialu_imm);
6923 %}
6924
6925 // Conditional move
6926 instruct cmovFP_reg(cmpOpP cmp, flagsRegP pcc, regF dst, regF src) %{
6927 match(Set dst (CMoveF (Binary cmp pcc) (Binary dst src)));
6928 ins_cost(150);
6929 opcode(0x101);
6930 format %{ "FMOVD$cmp $pcc,$src,$dst" %}
6931 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6932 ins_pipe(int_conditional_float_move);
6933 %}
6934
6935 instruct cmovFI_reg(cmpOp cmp, flagsReg icc, regF dst, regF src) %{
6936 match(Set dst (CMoveF (Binary cmp icc) (Binary dst src)));
6937 ins_cost(150);
6938
6939 size(4);
6940 format %{ "FMOVS$cmp $icc,$src,$dst" %}
6941 opcode(0x101);
6942 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
6943 ins_pipe(int_conditional_float_move);
6944 %}
6945
6946 instruct cmovFIu_reg(cmpOpU cmp, flagsRegU icc, regF dst, regF src) %{
6947 match(Set dst (CMoveF (Binary cmp icc) (Binary dst src)));
6948 ins_cost(150);
6949
6950 size(4);
6951 format %{ "FMOVS$cmp $icc,$src,$dst" %}
6952 opcode(0x101);
6953 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
6954 ins_pipe(int_conditional_float_move);
6955 %}
6956
6957 // Conditional move,
6958 instruct cmovFF_reg(cmpOpF cmp, flagsRegF fcc, regF dst, regF src) %{
6959 match(Set dst (CMoveF (Binary cmp fcc) (Binary dst src)));
6960 ins_cost(150);
6961 size(4);
6962 format %{ "FMOVF$cmp $fcc,$src,$dst" %}
6963 opcode(0x1);
6964 ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) );
6965 ins_pipe(int_conditional_double_move);
6966 %}
6967
6968 // Conditional move
6969 instruct cmovDP_reg(cmpOpP cmp, flagsRegP pcc, regD dst, regD src) %{
6970 match(Set dst (CMoveD (Binary cmp pcc) (Binary dst src)));
6971 ins_cost(150);
6972 size(4);
6973 opcode(0x102);
6974 format %{ "FMOVD$cmp $pcc,$src,$dst" %}
6975 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6976 ins_pipe(int_conditional_double_move);
6977 %}
6978
6979 instruct cmovDI_reg(cmpOp cmp, flagsReg icc, regD dst, regD src) %{
6980 match(Set dst (CMoveD (Binary cmp icc) (Binary dst src)));
6981 ins_cost(150);
6982
6983 size(4);
6984 format %{ "FMOVD$cmp $icc,$src,$dst" %}
6985 opcode(0x102);
6986 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
6987 ins_pipe(int_conditional_double_move);
6988 %}
6989
6990 instruct cmovDIu_reg(cmpOpU cmp, flagsRegU icc, regD dst, regD src) %{
6991 match(Set dst (CMoveD (Binary cmp icc) (Binary dst src)));
6992 ins_cost(150);
6993
6994 size(4);
6995 format %{ "FMOVD$cmp $icc,$src,$dst" %}
6996 opcode(0x102);
6997 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
6998 ins_pipe(int_conditional_double_move);
6999 %}
7000
7001 // Conditional move,
7002 instruct cmovDF_reg(cmpOpF cmp, flagsRegF fcc, regD dst, regD src) %{
7003 match(Set dst (CMoveD (Binary cmp fcc) (Binary dst src)));
7004 ins_cost(150);
7005 size(4);
7006 format %{ "FMOVD$cmp $fcc,$src,$dst" %}
7007 opcode(0x2);
7008 ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) );
7009 ins_pipe(int_conditional_double_move);
7010 %}
7011
7012 // Conditional move
7013 instruct cmovLP_reg(cmpOpP cmp, flagsRegP pcc, iRegL dst, iRegL src) %{
7014 match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src)));
7015 ins_cost(150);
7016 format %{ "MOV$cmp $pcc,$src,$dst\t! long" %}
7017 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
7018 ins_pipe(ialu_reg);
7019 %}
7020
7021 instruct cmovLP_imm(cmpOpP cmp, flagsRegP pcc, iRegL dst, immI11 src) %{
7022 match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src)));
7023 ins_cost(140);
7024 format %{ "MOV$cmp $pcc,$src,$dst\t! long" %}
7025 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) );
7026 ins_pipe(ialu_imm);
7027 %}
7028
7029 instruct cmovLI_reg(cmpOp cmp, flagsReg icc, iRegL dst, iRegL src) %{
7030 match(Set dst (CMoveL (Binary cmp icc) (Binary dst src)));
7031 ins_cost(150);
7032
7033 size(4);
7034 format %{ "MOV$cmp $icc,$src,$dst\t! long" %}
7035 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
7036 ins_pipe(ialu_reg);
7037 %}
7038
7039
7040 instruct cmovLIu_reg(cmpOpU cmp, flagsRegU icc, iRegL dst, iRegL src) %{
7041 match(Set dst (CMoveL (Binary cmp icc) (Binary dst src)));
7042 ins_cost(150);
7043
7044 size(4);
7045 format %{ "MOV$cmp $icc,$src,$dst\t! long" %}
7046 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
7047 ins_pipe(ialu_reg);
7048 %}
7049
7050
7051 instruct cmovLF_reg(cmpOpF cmp, flagsRegF fcc, iRegL dst, iRegL src) %{
7052 match(Set dst (CMoveL (Binary cmp fcc) (Binary dst src)));
7053 ins_cost(150);
7054
7055 size(4);
7056 format %{ "MOV$cmp $fcc,$src,$dst\t! long" %}
7057 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
7058 ins_pipe(ialu_reg);
7059 %}
7060
7061
7062
7063 //----------OS and Locking Instructions----------------------------------------
7064
7065 // This name is KNOWN by the ADLC and cannot be changed.
7066 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type
7067 // for this guy.
7068 instruct tlsLoadP(g2RegP dst) %{
7069 match(Set dst (ThreadLocal));
7070
7071 size(0);
7072 ins_cost(0);
7073 format %{ "# TLS is in G2" %}
7074 ins_encode( /*empty encoding*/ );
7075 ins_pipe(ialu_none);
7076 %}
7077
7078 instruct checkCastPP( iRegP dst ) %{
7079 match(Set dst (CheckCastPP dst));
7080
7081 size(0);
7082 format %{ "# checkcastPP of $dst" %}
7083 ins_encode( /*empty encoding*/ );
7084 ins_pipe(empty);
7085 %}
7086
7087
7088 instruct castPP( iRegP dst ) %{
7089 match(Set dst (CastPP dst));
7090 format %{ "# castPP of $dst" %}
7091 ins_encode( /*empty encoding*/ );
7092 ins_pipe(empty);
7093 %}
7094
7095 instruct castII( iRegI dst ) %{
7096 match(Set dst (CastII dst));
7097 format %{ "# castII of $dst" %}
7098 ins_encode( /*empty encoding*/ );
7099 ins_cost(0);
7100 ins_pipe(empty);
7101 %}
7102
7103 //----------Arithmetic Instructions--------------------------------------------
7104 // Addition Instructions
7105 // Register Addition
7106 instruct addI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7107 match(Set dst (AddI src1 src2));
7108
7109 size(4);
7110 format %{ "ADD $src1,$src2,$dst" %}
7111 ins_encode %{
7112 __ add($src1$$Register, $src2$$Register, $dst$$Register);
7113 %}
7114 ins_pipe(ialu_reg_reg);
7115 %}
7116
7117 // Immediate Addition
7118 instruct addI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7119 match(Set dst (AddI src1 src2));
7120
7121 size(4);
7122 format %{ "ADD $src1,$src2,$dst" %}
7123 opcode(Assembler::add_op3, Assembler::arith_op);
7124 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7125 ins_pipe(ialu_reg_imm);
7126 %}
7127
7128 // Pointer Register Addition
7129 instruct addP_reg_reg(iRegP dst, iRegP src1, iRegX src2) %{
7130 match(Set dst (AddP src1 src2));
7131
7132 size(4);
7133 format %{ "ADD $src1,$src2,$dst" %}
7134 opcode(Assembler::add_op3, Assembler::arith_op);
7135 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7136 ins_pipe(ialu_reg_reg);
7137 %}
7138
7139 // Pointer Immediate Addition
7140 instruct addP_reg_imm13(iRegP dst, iRegP src1, immX13 src2) %{
7141 match(Set dst (AddP src1 src2));
7142
7143 size(4);
7144 format %{ "ADD $src1,$src2,$dst" %}
7145 opcode(Assembler::add_op3, Assembler::arith_op);
7146 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7147 ins_pipe(ialu_reg_imm);
7148 %}
7149
7150 // Long Addition
7151 instruct addL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7152 match(Set dst (AddL src1 src2));
7153
7154 size(4);
7155 format %{ "ADD $src1,$src2,$dst\t! long" %}
7156 opcode(Assembler::add_op3, Assembler::arith_op);
7157 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7158 ins_pipe(ialu_reg_reg);
7159 %}
7160
7161 instruct addL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
7162 match(Set dst (AddL src1 con));
7163
7164 size(4);
7165 format %{ "ADD $src1,$con,$dst" %}
7166 opcode(Assembler::add_op3, Assembler::arith_op);
7167 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
7168 ins_pipe(ialu_reg_imm);
7169 %}
7170
7171 //----------Conditional_store--------------------------------------------------
7172 // Conditional-store of the updated heap-top.
7173 // Used during allocation of the shared heap.
7174 // Sets flags (EQ) on success. Implemented with a CASA on Sparc.
7175
7176 // LoadP-locked. Same as a regular pointer load when used with a compare-swap
7177 instruct loadPLocked(iRegP dst, memory mem) %{
7178 match(Set dst (LoadPLocked mem));
7179 ins_cost(MEMORY_REF_COST);
7180
7181 #ifndef _LP64
7182 size(4);
7183 format %{ "LDUW $mem,$dst\t! ptr" %}
7184 opcode(Assembler::lduw_op3, 0, REGP_OP);
7185 #else
7186 format %{ "LDX $mem,$dst\t! ptr" %}
7187 opcode(Assembler::ldx_op3, 0, REGP_OP);
7188 #endif
7189 ins_encode( form3_mem_reg( mem, dst ) );
7190 ins_pipe(iload_mem);
7191 %}
7192
7193 instruct storePConditional( iRegP heap_top_ptr, iRegP oldval, g3RegP newval, flagsRegP pcc ) %{
7194 match(Set pcc (StorePConditional heap_top_ptr (Binary oldval newval)));
7195 effect( KILL newval );
7196 format %{ "CASA [$heap_top_ptr],$oldval,R_G3\t! If $oldval==[$heap_top_ptr] Then store R_G3 into [$heap_top_ptr], set R_G3=[$heap_top_ptr] in any case\n\t"
7197 "CMP R_G3,$oldval\t\t! See if we made progress" %}
7198 ins_encode( enc_cas(heap_top_ptr,oldval,newval) );
7199 ins_pipe( long_memory_op );
7200 %}
7201
7202 // Conditional-store of an int value.
7203 instruct storeIConditional( iRegP mem_ptr, iRegI oldval, g3RegI newval, flagsReg icc ) %{
7204 match(Set icc (StoreIConditional mem_ptr (Binary oldval newval)));
7205 effect( KILL newval );
7206 format %{ "CASA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr], set $newval=[$mem_ptr] in any case\n\t"
7207 "CMP $oldval,$newval\t\t! See if we made progress" %}
7208 ins_encode( enc_cas(mem_ptr,oldval,newval) );
7209 ins_pipe( long_memory_op );
7210 %}
7211
7212 // Conditional-store of a long value.
7213 instruct storeLConditional( iRegP mem_ptr, iRegL oldval, g3RegL newval, flagsRegL xcc ) %{
7214 match(Set xcc (StoreLConditional mem_ptr (Binary oldval newval)));
7215 effect( KILL newval );
7216 format %{ "CASXA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr], set $newval=[$mem_ptr] in any case\n\t"
7217 "CMP $oldval,$newval\t\t! See if we made progress" %}
7218 ins_encode( enc_cas(mem_ptr,oldval,newval) );
7219 ins_pipe( long_memory_op );
7220 %}
7221
7222 // No flag versions for CompareAndSwap{P,I,L} because matcher can't match them
7223
7224 instruct compareAndSwapL_bool(iRegP mem_ptr, iRegL oldval, iRegL newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
7225 predicate(VM_Version::supports_cx8());
7226 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval)));
7227 effect( USE mem_ptr, KILL ccr, KILL tmp1);
7228 format %{
7229 "MOV $newval,O7\n\t"
7230 "CASXA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
7231 "CMP $oldval,O7\t\t! See if we made progress\n\t"
7232 "MOV 1,$res\n\t"
7233 "MOVne xcc,R_G0,$res"
7234 %}
7235 ins_encode( enc_casx(mem_ptr, oldval, newval),
7236 enc_lflags_ne_to_boolean(res) );
7237 ins_pipe( long_memory_op );
7238 %}
7239
7240
7241 instruct compareAndSwapI_bool(iRegP mem_ptr, iRegI oldval, iRegI newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
7242 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval)));
7243 effect( USE mem_ptr, KILL ccr, KILL tmp1);
7244 format %{
7245 "MOV $newval,O7\n\t"
7246 "CASA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
7247 "CMP $oldval,O7\t\t! See if we made progress\n\t"
7248 "MOV 1,$res\n\t"
7249 "MOVne icc,R_G0,$res"
7250 %}
7251 ins_encode( enc_casi(mem_ptr, oldval, newval),
7252 enc_iflags_ne_to_boolean(res) );
7253 ins_pipe( long_memory_op );
7254 %}
7255
7256 instruct compareAndSwapP_bool(iRegP mem_ptr, iRegP oldval, iRegP newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
7257 #ifdef _LP64
7258 predicate(VM_Version::supports_cx8());
7259 #endif
7260 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval)));
7261 effect( USE mem_ptr, KILL ccr, KILL tmp1);
7262 format %{
7263 "MOV $newval,O7\n\t"
7264 "CASA_PTR [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
7265 "CMP $oldval,O7\t\t! See if we made progress\n\t"
7266 "MOV 1,$res\n\t"
7267 "MOVne xcc,R_G0,$res"
7268 %}
7269 #ifdef _LP64
7270 ins_encode( enc_casx(mem_ptr, oldval, newval),
7271 enc_lflags_ne_to_boolean(res) );
7272 #else
7273 ins_encode( enc_casi(mem_ptr, oldval, newval),
7274 enc_iflags_ne_to_boolean(res) );
7275 #endif
7276 ins_pipe( long_memory_op );
7277 %}
7278
7279 instruct compareAndSwapN_bool(iRegP mem_ptr, iRegN oldval, iRegN newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
7280 match(Set res (CompareAndSwapN mem_ptr (Binary oldval newval)));
7281 effect( USE mem_ptr, KILL ccr, KILL tmp1);
7282 format %{
7283 "MOV $newval,O7\n\t"
7284 "CASA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
7285 "CMP $oldval,O7\t\t! See if we made progress\n\t"
7286 "MOV 1,$res\n\t"
7287 "MOVne icc,R_G0,$res"
7288 %}
7289 ins_encode( enc_casi(mem_ptr, oldval, newval),
7290 enc_iflags_ne_to_boolean(res) );
7291 ins_pipe( long_memory_op );
7292 %}
7293
7294 instruct xchgI( memory mem, iRegI newval) %{
7295 match(Set newval (GetAndSetI mem newval));
7296 format %{ "SWAP [$mem],$newval" %}
7297 size(4);
7298 ins_encode %{
7299 __ swap($mem$$Address, $newval$$Register);
7300 %}
7301 ins_pipe( long_memory_op );
7302 %}
7303
7304 #ifndef _LP64
7305 instruct xchgP( memory mem, iRegP newval) %{
7306 match(Set newval (GetAndSetP mem newval));
7307 format %{ "SWAP [$mem],$newval" %}
7308 size(4);
7309 ins_encode %{
7310 __ swap($mem$$Address, $newval$$Register);
7311 %}
7312 ins_pipe( long_memory_op );
7313 %}
7314 #endif
7315
7316 instruct xchgN( memory mem, iRegN newval) %{
7317 match(Set newval (GetAndSetN mem newval));
7318 format %{ "SWAP [$mem],$newval" %}
7319 size(4);
7320 ins_encode %{
7321 __ swap($mem$$Address, $newval$$Register);
7322 %}
7323 ins_pipe( long_memory_op );
7324 %}
7325
7326 //---------------------
7327 // Subtraction Instructions
7328 // Register Subtraction
7329 instruct subI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7330 match(Set dst (SubI src1 src2));
7331
7332 size(4);
7333 format %{ "SUB $src1,$src2,$dst" %}
7334 opcode(Assembler::sub_op3, Assembler::arith_op);
7335 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7336 ins_pipe(ialu_reg_reg);
7337 %}
7338
7339 // Immediate Subtraction
7340 instruct subI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7341 match(Set dst (SubI src1 src2));
7342
7343 size(4);
7344 format %{ "SUB $src1,$src2,$dst" %}
7345 opcode(Assembler::sub_op3, Assembler::arith_op);
7346 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7347 ins_pipe(ialu_reg_imm);
7348 %}
7349
7350 instruct subI_zero_reg(iRegI dst, immI0 zero, iRegI src2) %{
7351 match(Set dst (SubI zero src2));
7352
7353 size(4);
7354 format %{ "NEG $src2,$dst" %}
7355 opcode(Assembler::sub_op3, Assembler::arith_op);
7356 ins_encode( form3_rs1_rs2_rd( R_G0, src2, dst ) );
7357 ins_pipe(ialu_zero_reg);
7358 %}
7359
7360 // Long subtraction
7361 instruct subL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7362 match(Set dst (SubL src1 src2));
7363
7364 size(4);
7365 format %{ "SUB $src1,$src2,$dst\t! long" %}
7366 opcode(Assembler::sub_op3, Assembler::arith_op);
7367 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7368 ins_pipe(ialu_reg_reg);
7369 %}
7370
7371 // Immediate Subtraction
7372 instruct subL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
7373 match(Set dst (SubL src1 con));
7374
7375 size(4);
7376 format %{ "SUB $src1,$con,$dst\t! long" %}
7377 opcode(Assembler::sub_op3, Assembler::arith_op);
7378 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
7379 ins_pipe(ialu_reg_imm);
7380 %}
7381
7382 // Long negation
7383 instruct negL_reg_reg(iRegL dst, immL0 zero, iRegL src2) %{
7384 match(Set dst (SubL zero src2));
7385
7386 size(4);
7387 format %{ "NEG $src2,$dst\t! long" %}
7388 opcode(Assembler::sub_op3, Assembler::arith_op);
7389 ins_encode( form3_rs1_rs2_rd( R_G0, src2, dst ) );
7390 ins_pipe(ialu_zero_reg);
7391 %}
7392
7393 // Multiplication Instructions
7394 // Integer Multiplication
7395 // Register Multiplication
7396 instruct mulI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7397 match(Set dst (MulI src1 src2));
7398
7399 size(4);
7400 format %{ "MULX $src1,$src2,$dst" %}
7401 opcode(Assembler::mulx_op3, Assembler::arith_op);
7402 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7403 ins_pipe(imul_reg_reg);
7404 %}
7405
7406 // Immediate Multiplication
7407 instruct mulI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7408 match(Set dst (MulI src1 src2));
7409
7410 size(4);
7411 format %{ "MULX $src1,$src2,$dst" %}
7412 opcode(Assembler::mulx_op3, Assembler::arith_op);
7413 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7414 ins_pipe(imul_reg_imm);
7415 %}
7416
7417 instruct mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7418 match(Set dst (MulL src1 src2));
7419 ins_cost(DEFAULT_COST * 5);
7420 size(4);
7421 format %{ "MULX $src1,$src2,$dst\t! long" %}
7422 opcode(Assembler::mulx_op3, Assembler::arith_op);
7423 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7424 ins_pipe(mulL_reg_reg);
7425 %}
7426
7427 // Immediate Multiplication
7428 instruct mulL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{
7429 match(Set dst (MulL src1 src2));
7430 ins_cost(DEFAULT_COST * 5);
7431 size(4);
7432 format %{ "MULX $src1,$src2,$dst" %}
7433 opcode(Assembler::mulx_op3, Assembler::arith_op);
7434 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7435 ins_pipe(mulL_reg_imm);
7436 %}
7437
7438 // Integer Division
7439 // Register Division
7440 instruct divI_reg_reg(iRegI dst, iRegIsafe src1, iRegIsafe src2) %{
7441 match(Set dst (DivI src1 src2));
7442 ins_cost((2+71)*DEFAULT_COST);
7443
7444 format %{ "SRA $src2,0,$src2\n\t"
7445 "SRA $src1,0,$src1\n\t"
7446 "SDIVX $src1,$src2,$dst" %}
7447 ins_encode( idiv_reg( src1, src2, dst ) );
7448 ins_pipe(sdiv_reg_reg);
7449 %}
7450
7451 // Immediate Division
7452 instruct divI_reg_imm13(iRegI dst, iRegIsafe src1, immI13 src2) %{
7453 match(Set dst (DivI src1 src2));
7454 ins_cost((2+71)*DEFAULT_COST);
7455
7456 format %{ "SRA $src1,0,$src1\n\t"
7457 "SDIVX $src1,$src2,$dst" %}
7458 ins_encode( idiv_imm( src1, src2, dst ) );
7459 ins_pipe(sdiv_reg_imm);
7460 %}
7461
7462 //----------Div-By-10-Expansion------------------------------------------------
7463 // Extract hi bits of a 32x32->64 bit multiply.
7464 // Expand rule only, not matched
7465 instruct mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2 ) %{
7466 effect( DEF dst, USE src1, USE src2 );
7467 format %{ "MULX $src1,$src2,$dst\t! Used in div-by-10\n\t"
7468 "SRLX $dst,#32,$dst\t\t! Extract only hi word of result" %}
7469 ins_encode( enc_mul_hi(dst,src1,src2));
7470 ins_pipe(sdiv_reg_reg);
7471 %}
7472
7473 // Magic constant, reciprocal of 10
7474 instruct loadConI_x66666667(iRegIsafe dst) %{
7475 effect( DEF dst );
7476
7477 size(8);
7478 format %{ "SET 0x66666667,$dst\t! Used in div-by-10" %}
7479 ins_encode( Set32(0x66666667, dst) );
7480 ins_pipe(ialu_hi_lo_reg);
7481 %}
7482
7483 // Register Shift Right Arithmetic Long by 32-63
7484 instruct sra_31( iRegI dst, iRegI src ) %{
7485 effect( DEF dst, USE src );
7486 format %{ "SRA $src,31,$dst\t! Used in div-by-10" %}
7487 ins_encode( form3_rs1_rd_copysign_hi(src,dst) );
7488 ins_pipe(ialu_reg_reg);
7489 %}
7490
7491 // Arithmetic Shift Right by 8-bit immediate
7492 instruct sra_reg_2( iRegI dst, iRegI src ) %{
7493 effect( DEF dst, USE src );
7494 format %{ "SRA $src,2,$dst\t! Used in div-by-10" %}
7495 opcode(Assembler::sra_op3, Assembler::arith_op);
7496 ins_encode( form3_rs1_simm13_rd( src, 0x2, dst ) );
7497 ins_pipe(ialu_reg_imm);
7498 %}
7499
7500 // Integer DIV with 10
7501 instruct divI_10( iRegI dst, iRegIsafe src, immI10 div ) %{
7502 match(Set dst (DivI src div));
7503 ins_cost((6+6)*DEFAULT_COST);
7504 expand %{
7505 iRegIsafe tmp1; // Killed temps;
7506 iRegIsafe tmp2; // Killed temps;
7507 iRegI tmp3; // Killed temps;
7508 iRegI tmp4; // Killed temps;
7509 loadConI_x66666667( tmp1 ); // SET 0x66666667 -> tmp1
7510 mul_hi( tmp2, src, tmp1 ); // MUL hibits(src * tmp1) -> tmp2
7511 sra_31( tmp3, src ); // SRA src,31 -> tmp3
7512 sra_reg_2( tmp4, tmp2 ); // SRA tmp2,2 -> tmp4
7513 subI_reg_reg( dst,tmp4,tmp3); // SUB tmp4 - tmp3 -> dst
7514 %}
7515 %}
7516
7517 // Register Long Division
7518 instruct divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7519 match(Set dst (DivL src1 src2));
7520 ins_cost(DEFAULT_COST*71);
7521 size(4);
7522 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
7523 opcode(Assembler::sdivx_op3, Assembler::arith_op);
7524 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7525 ins_pipe(divL_reg_reg);
7526 %}
7527
7528 // Register Long Division
7529 instruct divL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{
7530 match(Set dst (DivL src1 src2));
7531 ins_cost(DEFAULT_COST*71);
7532 size(4);
7533 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
7534 opcode(Assembler::sdivx_op3, Assembler::arith_op);
7535 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7536 ins_pipe(divL_reg_imm);
7537 %}
7538
7539 // Integer Remainder
7540 // Register Remainder
7541 instruct modI_reg_reg(iRegI dst, iRegIsafe src1, iRegIsafe src2, o7RegP temp, flagsReg ccr ) %{
7542 match(Set dst (ModI src1 src2));
7543 effect( KILL ccr, KILL temp);
7544
7545 format %{ "SREM $src1,$src2,$dst" %}
7546 ins_encode( irem_reg(src1, src2, dst, temp) );
7547 ins_pipe(sdiv_reg_reg);
7548 %}
7549
7550 // Immediate Remainder
7551 instruct modI_reg_imm13(iRegI dst, iRegIsafe src1, immI13 src2, o7RegP temp, flagsReg ccr ) %{
7552 match(Set dst (ModI src1 src2));
7553 effect( KILL ccr, KILL temp);
7554
7555 format %{ "SREM $src1,$src2,$dst" %}
7556 ins_encode( irem_imm(src1, src2, dst, temp) );
7557 ins_pipe(sdiv_reg_imm);
7558 %}
7559
7560 // Register Long Remainder
7561 instruct divL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{
7562 effect(DEF dst, USE src1, USE src2);
7563 size(4);
7564 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
7565 opcode(Assembler::sdivx_op3, Assembler::arith_op);
7566 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7567 ins_pipe(divL_reg_reg);
7568 %}
7569
7570 // Register Long Division
7571 instruct divL_reg_imm13_1(iRegL dst, iRegL src1, immL13 src2) %{
7572 effect(DEF dst, USE src1, USE src2);
7573 size(4);
7574 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
7575 opcode(Assembler::sdivx_op3, Assembler::arith_op);
7576 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7577 ins_pipe(divL_reg_imm);
7578 %}
7579
7580 instruct mulL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{
7581 effect(DEF dst, USE src1, USE src2);
7582 size(4);
7583 format %{ "MULX $src1,$src2,$dst\t! long" %}
7584 opcode(Assembler::mulx_op3, Assembler::arith_op);
7585 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7586 ins_pipe(mulL_reg_reg);
7587 %}
7588
7589 // Immediate Multiplication
7590 instruct mulL_reg_imm13_1(iRegL dst, iRegL src1, immL13 src2) %{
7591 effect(DEF dst, USE src1, USE src2);
7592 size(4);
7593 format %{ "MULX $src1,$src2,$dst" %}
7594 opcode(Assembler::mulx_op3, Assembler::arith_op);
7595 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7596 ins_pipe(mulL_reg_imm);
7597 %}
7598
7599 instruct subL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{
7600 effect(DEF dst, USE src1, USE src2);
7601 size(4);
7602 format %{ "SUB $src1,$src2,$dst\t! long" %}
7603 opcode(Assembler::sub_op3, Assembler::arith_op);
7604 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7605 ins_pipe(ialu_reg_reg);
7606 %}
7607
7608 instruct subL_reg_reg_2(iRegL dst, iRegL src1, iRegL src2) %{
7609 effect(DEF dst, USE src1, USE src2);
7610 size(4);
7611 format %{ "SUB $src1,$src2,$dst\t! long" %}
7612 opcode(Assembler::sub_op3, Assembler::arith_op);
7613 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7614 ins_pipe(ialu_reg_reg);
7615 %}
7616
7617 // Register Long Remainder
7618 instruct modL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7619 match(Set dst (ModL src1 src2));
7620 ins_cost(DEFAULT_COST*(71 + 6 + 1));
7621 expand %{
7622 iRegL tmp1;
7623 iRegL tmp2;
7624 divL_reg_reg_1(tmp1, src1, src2);
7625 mulL_reg_reg_1(tmp2, tmp1, src2);
7626 subL_reg_reg_1(dst, src1, tmp2);
7627 %}
7628 %}
7629
7630 // Register Long Remainder
7631 instruct modL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{
7632 match(Set dst (ModL src1 src2));
7633 ins_cost(DEFAULT_COST*(71 + 6 + 1));
7634 expand %{
7635 iRegL tmp1;
7636 iRegL tmp2;
7637 divL_reg_imm13_1(tmp1, src1, src2);
7638 mulL_reg_imm13_1(tmp2, tmp1, src2);
7639 subL_reg_reg_2 (dst, src1, tmp2);
7640 %}
7641 %}
7642
7643 // Integer Shift Instructions
7644 // Register Shift Left
7645 instruct shlI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7646 match(Set dst (LShiftI src1 src2));
7647
7648 size(4);
7649 format %{ "SLL $src1,$src2,$dst" %}
7650 opcode(Assembler::sll_op3, Assembler::arith_op);
7651 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7652 ins_pipe(ialu_reg_reg);
7653 %}
7654
7655 // Register Shift Left Immediate
7656 instruct shlI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{
7657 match(Set dst (LShiftI src1 src2));
7658
7659 size(4);
7660 format %{ "SLL $src1,$src2,$dst" %}
7661 opcode(Assembler::sll_op3, Assembler::arith_op);
7662 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7663 ins_pipe(ialu_reg_imm);
7664 %}
7665
7666 // Register Shift Left
7667 instruct shlL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
7668 match(Set dst (LShiftL src1 src2));
7669
7670 size(4);
7671 format %{ "SLLX $src1,$src2,$dst" %}
7672 opcode(Assembler::sllx_op3, Assembler::arith_op);
7673 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) );
7674 ins_pipe(ialu_reg_reg);
7675 %}
7676
7677 // Register Shift Left Immediate
7678 instruct shlL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{
7679 match(Set dst (LShiftL src1 src2));
7680
7681 size(4);
7682 format %{ "SLLX $src1,$src2,$dst" %}
7683 opcode(Assembler::sllx_op3, Assembler::arith_op);
7684 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7685 ins_pipe(ialu_reg_imm);
7686 %}
7687
7688 // Register Arithmetic Shift Right
7689 instruct sarI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7690 match(Set dst (RShiftI src1 src2));
7691 size(4);
7692 format %{ "SRA $src1,$src2,$dst" %}
7693 opcode(Assembler::sra_op3, Assembler::arith_op);
7694 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7695 ins_pipe(ialu_reg_reg);
7696 %}
7697
7698 // Register Arithmetic Shift Right Immediate
7699 instruct sarI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{
7700 match(Set dst (RShiftI src1 src2));
7701
7702 size(4);
7703 format %{ "SRA $src1,$src2,$dst" %}
7704 opcode(Assembler::sra_op3, Assembler::arith_op);
7705 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7706 ins_pipe(ialu_reg_imm);
7707 %}
7708
7709 // Register Shift Right Arithmatic Long
7710 instruct sarL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
7711 match(Set dst (RShiftL src1 src2));
7712
7713 size(4);
7714 format %{ "SRAX $src1,$src2,$dst" %}
7715 opcode(Assembler::srax_op3, Assembler::arith_op);
7716 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) );
7717 ins_pipe(ialu_reg_reg);
7718 %}
7719
7720 // Register Shift Left Immediate
7721 instruct sarL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{
7722 match(Set dst (RShiftL src1 src2));
7723
7724 size(4);
7725 format %{ "SRAX $src1,$src2,$dst" %}
7726 opcode(Assembler::srax_op3, Assembler::arith_op);
7727 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7728 ins_pipe(ialu_reg_imm);
7729 %}
7730
7731 // Register Shift Right
7732 instruct shrI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7733 match(Set dst (URShiftI src1 src2));
7734
7735 size(4);
7736 format %{ "SRL $src1,$src2,$dst" %}
7737 opcode(Assembler::srl_op3, Assembler::arith_op);
7738 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7739 ins_pipe(ialu_reg_reg);
7740 %}
7741
7742 // Register Shift Right Immediate
7743 instruct shrI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{
7744 match(Set dst (URShiftI src1 src2));
7745
7746 size(4);
7747 format %{ "SRL $src1,$src2,$dst" %}
7748 opcode(Assembler::srl_op3, Assembler::arith_op);
7749 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7750 ins_pipe(ialu_reg_imm);
7751 %}
7752
7753 // Register Shift Right
7754 instruct shrL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
7755 match(Set dst (URShiftL src1 src2));
7756
7757 size(4);
7758 format %{ "SRLX $src1,$src2,$dst" %}
7759 opcode(Assembler::srlx_op3, Assembler::arith_op);
7760 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) );
7761 ins_pipe(ialu_reg_reg);
7762 %}
7763
7764 // Register Shift Right Immediate
7765 instruct shrL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{
7766 match(Set dst (URShiftL src1 src2));
7767
7768 size(4);
7769 format %{ "SRLX $src1,$src2,$dst" %}
7770 opcode(Assembler::srlx_op3, Assembler::arith_op);
7771 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7772 ins_pipe(ialu_reg_imm);
7773 %}
7774
7775 // Register Shift Right Immediate with a CastP2X
7776 #ifdef _LP64
7777 instruct shrP_reg_imm6(iRegL dst, iRegP src1, immU6 src2) %{
7778 match(Set dst (URShiftL (CastP2X src1) src2));
7779 size(4);
7780 format %{ "SRLX $src1,$src2,$dst\t! Cast ptr $src1 to long and shift" %}
7781 opcode(Assembler::srlx_op3, Assembler::arith_op);
7782 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7783 ins_pipe(ialu_reg_imm);
7784 %}
7785 #else
7786 instruct shrP_reg_imm5(iRegI dst, iRegP src1, immU5 src2) %{
7787 match(Set dst (URShiftI (CastP2X src1) src2));
7788 size(4);
7789 format %{ "SRL $src1,$src2,$dst\t! Cast ptr $src1 to int and shift" %}
7790 opcode(Assembler::srl_op3, Assembler::arith_op);
7791 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7792 ins_pipe(ialu_reg_imm);
7793 %}
7794 #endif
7795
7796
7797 //----------Floating Point Arithmetic Instructions-----------------------------
7798
7799 // Add float single precision
7800 instruct addF_reg_reg(regF dst, regF src1, regF src2) %{
7801 match(Set dst (AddF src1 src2));
7802
7803 size(4);
7804 format %{ "FADDS $src1,$src2,$dst" %}
7805 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fadds_opf);
7806 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7807 ins_pipe(faddF_reg_reg);
7808 %}
7809
7810 // Add float double precision
7811 instruct addD_reg_reg(regD dst, regD src1, regD src2) %{
7812 match(Set dst (AddD src1 src2));
7813
7814 size(4);
7815 format %{ "FADDD $src1,$src2,$dst" %}
7816 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::faddd_opf);
7817 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7818 ins_pipe(faddD_reg_reg);
7819 %}
7820
7821 // Sub float single precision
7822 instruct subF_reg_reg(regF dst, regF src1, regF src2) %{
7823 match(Set dst (SubF src1 src2));
7824
7825 size(4);
7826 format %{ "FSUBS $src1,$src2,$dst" %}
7827 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubs_opf);
7828 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7829 ins_pipe(faddF_reg_reg);
7830 %}
7831
7832 // Sub float double precision
7833 instruct subD_reg_reg(regD dst, regD src1, regD src2) %{
7834 match(Set dst (SubD src1 src2));
7835
7836 size(4);
7837 format %{ "FSUBD $src1,$src2,$dst" %}
7838 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubd_opf);
7839 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7840 ins_pipe(faddD_reg_reg);
7841 %}
7842
7843 // Mul float single precision
7844 instruct mulF_reg_reg(regF dst, regF src1, regF src2) %{
7845 match(Set dst (MulF src1 src2));
7846
7847 size(4);
7848 format %{ "FMULS $src1,$src2,$dst" %}
7849 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuls_opf);
7850 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7851 ins_pipe(fmulF_reg_reg);
7852 %}
7853
7854 // Mul float double precision
7855 instruct mulD_reg_reg(regD dst, regD src1, regD src2) %{
7856 match(Set dst (MulD src1 src2));
7857
7858 size(4);
7859 format %{ "FMULD $src1,$src2,$dst" %}
7860 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuld_opf);
7861 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7862 ins_pipe(fmulD_reg_reg);
7863 %}
7864
7865 // Div float single precision
7866 instruct divF_reg_reg(regF dst, regF src1, regF src2) %{
7867 match(Set dst (DivF src1 src2));
7868
7869 size(4);
7870 format %{ "FDIVS $src1,$src2,$dst" %}
7871 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdivs_opf);
7872 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7873 ins_pipe(fdivF_reg_reg);
7874 %}
7875
7876 // Div float double precision
7877 instruct divD_reg_reg(regD dst, regD src1, regD src2) %{
7878 match(Set dst (DivD src1 src2));
7879
7880 size(4);
7881 format %{ "FDIVD $src1,$src2,$dst" %}
7882 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdivd_opf);
7883 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7884 ins_pipe(fdivD_reg_reg);
7885 %}
7886
7887 // Absolute float double precision
7888 instruct absD_reg(regD dst, regD src) %{
7889 match(Set dst (AbsD src));
7890
7891 format %{ "FABSd $src,$dst" %}
7892 ins_encode(fabsd(dst, src));
7893 ins_pipe(faddD_reg);
7894 %}
7895
7896 // Absolute float single precision
7897 instruct absF_reg(regF dst, regF src) %{
7898 match(Set dst (AbsF src));
7899
7900 format %{ "FABSs $src,$dst" %}
7901 ins_encode(fabss(dst, src));
7902 ins_pipe(faddF_reg);
7903 %}
7904
7905 instruct negF_reg(regF dst, regF src) %{
7906 match(Set dst (NegF src));
7907
7908 size(4);
7909 format %{ "FNEGs $src,$dst" %}
7910 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fnegs_opf);
7911 ins_encode(form3_opf_rs2F_rdF(src, dst));
7912 ins_pipe(faddF_reg);
7913 %}
7914
7915 instruct negD_reg(regD dst, regD src) %{
7916 match(Set dst (NegD src));
7917
7918 format %{ "FNEGd $src,$dst" %}
7919 ins_encode(fnegd(dst, src));
7920 ins_pipe(faddD_reg);
7921 %}
7922
7923 // Sqrt float double precision
7924 instruct sqrtF_reg_reg(regF dst, regF src) %{
7925 match(Set dst (ConvD2F (SqrtD (ConvF2D src))));
7926
7927 size(4);
7928 format %{ "FSQRTS $src,$dst" %}
7929 ins_encode(fsqrts(dst, src));
7930 ins_pipe(fdivF_reg_reg);
7931 %}
7932
7933 // Sqrt float double precision
7934 instruct sqrtD_reg_reg(regD dst, regD src) %{
7935 match(Set dst (SqrtD src));
7936
7937 size(4);
7938 format %{ "FSQRTD $src,$dst" %}
7939 ins_encode(fsqrtd(dst, src));
7940 ins_pipe(fdivD_reg_reg);
7941 %}
7942
7943 //----------Logical Instructions-----------------------------------------------
7944 // And Instructions
7945 // Register And
7946 instruct andI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7947 match(Set dst (AndI src1 src2));
7948
7949 size(4);
7950 format %{ "AND $src1,$src2,$dst" %}
7951 opcode(Assembler::and_op3, Assembler::arith_op);
7952 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7953 ins_pipe(ialu_reg_reg);
7954 %}
7955
7956 // Immediate And
7957 instruct andI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7958 match(Set dst (AndI src1 src2));
7959
7960 size(4);
7961 format %{ "AND $src1,$src2,$dst" %}
7962 opcode(Assembler::and_op3, Assembler::arith_op);
7963 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7964 ins_pipe(ialu_reg_imm);
7965 %}
7966
7967 // Register And Long
7968 instruct andL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7969 match(Set dst (AndL src1 src2));
7970
7971 ins_cost(DEFAULT_COST);
7972 size(4);
7973 format %{ "AND $src1,$src2,$dst\t! long" %}
7974 opcode(Assembler::and_op3, Assembler::arith_op);
7975 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7976 ins_pipe(ialu_reg_reg);
7977 %}
7978
7979 instruct andL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
7980 match(Set dst (AndL src1 con));
7981
7982 ins_cost(DEFAULT_COST);
7983 size(4);
7984 format %{ "AND $src1,$con,$dst\t! long" %}
7985 opcode(Assembler::and_op3, Assembler::arith_op);
7986 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
7987 ins_pipe(ialu_reg_imm);
7988 %}
7989
7990 // Or Instructions
7991 // Register Or
7992 instruct orI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7993 match(Set dst (OrI src1 src2));
7994
7995 size(4);
7996 format %{ "OR $src1,$src2,$dst" %}
7997 opcode(Assembler::or_op3, Assembler::arith_op);
7998 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7999 ins_pipe(ialu_reg_reg);
8000 %}
8001
8002 // Immediate Or
8003 instruct orI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
8004 match(Set dst (OrI src1 src2));
8005
8006 size(4);
8007 format %{ "OR $src1,$src2,$dst" %}
8008 opcode(Assembler::or_op3, Assembler::arith_op);
8009 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
8010 ins_pipe(ialu_reg_imm);
8011 %}
8012
8013 // Register Or Long
8014 instruct orL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
8015 match(Set dst (OrL src1 src2));
8016
8017 ins_cost(DEFAULT_COST);
8018 size(4);
8019 format %{ "OR $src1,$src2,$dst\t! long" %}
8020 opcode(Assembler::or_op3, Assembler::arith_op);
8021 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
8022 ins_pipe(ialu_reg_reg);
8023 %}
8024
8025 instruct orL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
8026 match(Set dst (OrL src1 con));
8027 ins_cost(DEFAULT_COST*2);
8028
8029 ins_cost(DEFAULT_COST);
8030 size(4);
8031 format %{ "OR $src1,$con,$dst\t! long" %}
8032 opcode(Assembler::or_op3, Assembler::arith_op);
8033 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
8034 ins_pipe(ialu_reg_imm);
8035 %}
8036
8037 #ifndef _LP64
8038
8039 // Use sp_ptr_RegP to match G2 (TLS register) without spilling.
8040 instruct orI_reg_castP2X(iRegI dst, iRegI src1, sp_ptr_RegP src2) %{
8041 match(Set dst (OrI src1 (CastP2X src2)));
8042
8043 size(4);
8044 format %{ "OR $src1,$src2,$dst" %}
8045 opcode(Assembler::or_op3, Assembler::arith_op);
8046 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
8047 ins_pipe(ialu_reg_reg);
8048 %}
8049
8050 #else
8051
8052 instruct orL_reg_castP2X(iRegL dst, iRegL src1, sp_ptr_RegP src2) %{
8053 match(Set dst (OrL src1 (CastP2X src2)));
8054
8055 ins_cost(DEFAULT_COST);
8056 size(4);
8057 format %{ "OR $src1,$src2,$dst\t! long" %}
8058 opcode(Assembler::or_op3, Assembler::arith_op);
8059 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
8060 ins_pipe(ialu_reg_reg);
8061 %}
8062
8063 #endif
8064
8065 // Xor Instructions
8066 // Register Xor
8067 instruct xorI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
8068 match(Set dst (XorI src1 src2));
8069
8070 size(4);
8071 format %{ "XOR $src1,$src2,$dst" %}
8072 opcode(Assembler::xor_op3, Assembler::arith_op);
8073 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
8074 ins_pipe(ialu_reg_reg);
8075 %}
8076
8077 // Immediate Xor
8078 instruct xorI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
8079 match(Set dst (XorI src1 src2));
8080
8081 size(4);
8082 format %{ "XOR $src1,$src2,$dst" %}
8083 opcode(Assembler::xor_op3, Assembler::arith_op);
8084 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
8085 ins_pipe(ialu_reg_imm);
8086 %}
8087
8088 // Register Xor Long
8089 instruct xorL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
8090 match(Set dst (XorL src1 src2));
8091
8092 ins_cost(DEFAULT_COST);
8093 size(4);
8094 format %{ "XOR $src1,$src2,$dst\t! long" %}
8095 opcode(Assembler::xor_op3, Assembler::arith_op);
8096 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
8097 ins_pipe(ialu_reg_reg);
8098 %}
8099
8100 instruct xorL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
8101 match(Set dst (XorL src1 con));
8102
8103 ins_cost(DEFAULT_COST);
8104 size(4);
8105 format %{ "XOR $src1,$con,$dst\t! long" %}
8106 opcode(Assembler::xor_op3, Assembler::arith_op);
8107 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
8108 ins_pipe(ialu_reg_imm);
8109 %}
8110
8111 //----------Convert to Boolean-------------------------------------------------
8112 // Nice hack for 32-bit tests but doesn't work for
8113 // 64-bit pointers.
8114 instruct convI2B( iRegI dst, iRegI src, flagsReg ccr ) %{
8115 match(Set dst (Conv2B src));
8116 effect( KILL ccr );
8117 ins_cost(DEFAULT_COST*2);
8118 format %{ "CMP R_G0,$src\n\t"
8119 "ADDX R_G0,0,$dst" %}
8120 ins_encode( enc_to_bool( src, dst ) );
8121 ins_pipe(ialu_reg_ialu);
8122 %}
8123
8124 #ifndef _LP64
8125 instruct convP2B( iRegI dst, iRegP src, flagsReg ccr ) %{
8126 match(Set dst (Conv2B src));
8127 effect( KILL ccr );
8128 ins_cost(DEFAULT_COST*2);
8129 format %{ "CMP R_G0,$src\n\t"
8130 "ADDX R_G0,0,$dst" %}
8131 ins_encode( enc_to_bool( src, dst ) );
8132 ins_pipe(ialu_reg_ialu);
8133 %}
8134 #else
8135 instruct convP2B( iRegI dst, iRegP src ) %{
8136 match(Set dst (Conv2B src));
8137 ins_cost(DEFAULT_COST*2);
8138 format %{ "MOV $src,$dst\n\t"
8139 "MOVRNZ $src,1,$dst" %}
8140 ins_encode( form3_g0_rs2_rd_move( src, dst ), enc_convP2B( dst, src ) );
8141 ins_pipe(ialu_clr_and_mover);
8142 %}
8143 #endif
8144
8145 instruct cmpLTMask0( iRegI dst, iRegI src, immI0 zero, flagsReg ccr ) %{
8146 match(Set dst (CmpLTMask src zero));
8147 effect(KILL ccr);
8148 size(4);
8149 format %{ "SRA $src,#31,$dst\t# cmpLTMask0" %}
8150 ins_encode %{
8151 __ sra($src$$Register, 31, $dst$$Register);
8152 %}
8153 ins_pipe(ialu_reg_imm);
8154 %}
8155
8156 instruct cmpLTMask_reg_reg( iRegI dst, iRegI p, iRegI q, flagsReg ccr ) %{
8157 match(Set dst (CmpLTMask p q));
8158 effect( KILL ccr );
8159 ins_cost(DEFAULT_COST*4);
8160 format %{ "CMP $p,$q\n\t"
8161 "MOV #0,$dst\n\t"
8162 "BLT,a .+8\n\t"
8163 "MOV #-1,$dst" %}
8164 ins_encode( enc_ltmask(p,q,dst) );
8165 ins_pipe(ialu_reg_reg_ialu);
8166 %}
8167
8168 instruct cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp, flagsReg ccr ) %{
8169 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)));
8170 effect(KILL ccr, TEMP tmp);
8171 ins_cost(DEFAULT_COST*3);
8172
8173 format %{ "SUBcc $p,$q,$p\t! p' = p-q\n\t"
8174 "ADD $p,$y,$tmp\t! g3=p-q+y\n\t"
8175 "MOVlt $tmp,$p\t! p' < 0 ? p'+y : p'" %}
8176 ins_encode(enc_cadd_cmpLTMask(p, q, y, tmp));
8177 ins_pipe(cadd_cmpltmask);
8178 %}
8179
8180 instruct and_cmpLTMask(iRegI p, iRegI q, iRegI y, flagsReg ccr) %{
8181 match(Set p (AndI (CmpLTMask p q) y));
8182 effect(KILL ccr);
8183 ins_cost(DEFAULT_COST*3);
8184
8185 format %{ "CMP $p,$q\n\t"
8186 "MOV $y,$p\n\t"
8187 "MOVge G0,$p" %}
8188 ins_encode %{
8189 __ cmp($p$$Register, $q$$Register);
8190 __ mov($y$$Register, $p$$Register);
8191 __ movcc(Assembler::greaterEqual, false, Assembler::icc, G0, $p$$Register);
8192 %}
8193 ins_pipe(ialu_reg_reg_ialu);
8194 %}
8195
8196 //-----------------------------------------------------------------
8197 // Direct raw moves between float and general registers using VIS3.
8198
8199 // ins_pipe(faddF_reg);
8200 instruct MoveF2I_reg_reg(iRegI dst, regF src) %{
8201 predicate(UseVIS >= 3);
8202 match(Set dst (MoveF2I src));
8203
8204 format %{ "MOVSTOUW $src,$dst\t! MoveF2I" %}
8205 ins_encode %{
8206 __ movstouw($src$$FloatRegister, $dst$$Register);
8207 %}
8208 ins_pipe(ialu_reg_reg);
8209 %}
8210
8211 instruct MoveI2F_reg_reg(regF dst, iRegI src) %{
8212 predicate(UseVIS >= 3);
8213 match(Set dst (MoveI2F src));
8214
8215 format %{ "MOVWTOS $src,$dst\t! MoveI2F" %}
8216 ins_encode %{
8217 __ movwtos($src$$Register, $dst$$FloatRegister);
8218 %}
8219 ins_pipe(ialu_reg_reg);
8220 %}
8221
8222 instruct MoveD2L_reg_reg(iRegL dst, regD src) %{
8223 predicate(UseVIS >= 3);
8224 match(Set dst (MoveD2L src));
8225
8226 format %{ "MOVDTOX $src,$dst\t! MoveD2L" %}
8227 ins_encode %{
8228 __ movdtox(as_DoubleFloatRegister($src$$reg), $dst$$Register);
8229 %}
8230 ins_pipe(ialu_reg_reg);
8231 %}
8232
8233 instruct MoveL2D_reg_reg(regD dst, iRegL src) %{
8234 predicate(UseVIS >= 3);
8235 match(Set dst (MoveL2D src));
8236
8237 format %{ "MOVXTOD $src,$dst\t! MoveL2D" %}
8238 ins_encode %{
8239 __ movxtod($src$$Register, as_DoubleFloatRegister($dst$$reg));
8240 %}
8241 ins_pipe(ialu_reg_reg);
8242 %}
8243
8244
8245 // Raw moves between float and general registers using stack.
8246
8247 instruct MoveF2I_stack_reg(iRegI dst, stackSlotF src) %{
8248 match(Set dst (MoveF2I src));
8249 effect(DEF dst, USE src);
8250 ins_cost(MEMORY_REF_COST);
8251
8252 size(4);
8253 format %{ "LDUW $src,$dst\t! MoveF2I" %}
8254 opcode(Assembler::lduw_op3);
8255 ins_encode(simple_form3_mem_reg( src, dst ) );
8256 ins_pipe(iload_mem);
8257 %}
8258
8259 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{
8260 match(Set dst (MoveI2F src));
8261 effect(DEF dst, USE src);
8262 ins_cost(MEMORY_REF_COST);
8263
8264 size(4);
8265 format %{ "LDF $src,$dst\t! MoveI2F" %}
8266 opcode(Assembler::ldf_op3);
8267 ins_encode(simple_form3_mem_reg(src, dst));
8268 ins_pipe(floadF_stk);
8269 %}
8270
8271 instruct MoveD2L_stack_reg(iRegL dst, stackSlotD src) %{
8272 match(Set dst (MoveD2L src));
8273 effect(DEF dst, USE src);
8274 ins_cost(MEMORY_REF_COST);
8275
8276 size(4);
8277 format %{ "LDX $src,$dst\t! MoveD2L" %}
8278 opcode(Assembler::ldx_op3);
8279 ins_encode(simple_form3_mem_reg( src, dst ) );
8280 ins_pipe(iload_mem);
8281 %}
8282
8283 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{
8284 match(Set dst (MoveL2D src));
8285 effect(DEF dst, USE src);
8286 ins_cost(MEMORY_REF_COST);
8287
8288 size(4);
8289 format %{ "LDDF $src,$dst\t! MoveL2D" %}
8290 opcode(Assembler::lddf_op3);
8291 ins_encode(simple_form3_mem_reg(src, dst));
8292 ins_pipe(floadD_stk);
8293 %}
8294
8295 instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{
8296 match(Set dst (MoveF2I src));
8297 effect(DEF dst, USE src);
8298 ins_cost(MEMORY_REF_COST);
8299
8300 size(4);
8301 format %{ "STF $src,$dst\t! MoveF2I" %}
8302 opcode(Assembler::stf_op3);
8303 ins_encode(simple_form3_mem_reg(dst, src));
8304 ins_pipe(fstoreF_stk_reg);
8305 %}
8306
8307 instruct MoveI2F_reg_stack(stackSlotF dst, iRegI src) %{
8308 match(Set dst (MoveI2F src));
8309 effect(DEF dst, USE src);
8310 ins_cost(MEMORY_REF_COST);
8311
8312 size(4);
8313 format %{ "STW $src,$dst\t! MoveI2F" %}
8314 opcode(Assembler::stw_op3);
8315 ins_encode(simple_form3_mem_reg( dst, src ) );
8316 ins_pipe(istore_mem_reg);
8317 %}
8318
8319 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{
8320 match(Set dst (MoveD2L src));
8321 effect(DEF dst, USE src);
8322 ins_cost(MEMORY_REF_COST);
8323
8324 size(4);
8325 format %{ "STDF $src,$dst\t! MoveD2L" %}
8326 opcode(Assembler::stdf_op3);
8327 ins_encode(simple_form3_mem_reg(dst, src));
8328 ins_pipe(fstoreD_stk_reg);
8329 %}
8330
8331 instruct MoveL2D_reg_stack(stackSlotD dst, iRegL src) %{
8332 match(Set dst (MoveL2D src));
8333 effect(DEF dst, USE src);
8334 ins_cost(MEMORY_REF_COST);
8335
8336 size(4);
8337 format %{ "STX $src,$dst\t! MoveL2D" %}
8338 opcode(Assembler::stx_op3);
8339 ins_encode(simple_form3_mem_reg( dst, src ) );
8340 ins_pipe(istore_mem_reg);
8341 %}
8342
8343
8344 //----------Arithmetic Conversion Instructions---------------------------------
8345 // The conversions operations are all Alpha sorted. Please keep it that way!
8346
8347 instruct convD2F_reg(regF dst, regD src) %{
8348 match(Set dst (ConvD2F src));
8349 size(4);
8350 format %{ "FDTOS $src,$dst" %}
8351 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdtos_opf);
8352 ins_encode(form3_opf_rs2D_rdF(src, dst));
8353 ins_pipe(fcvtD2F);
8354 %}
8355
8356
8357 // Convert a double to an int in a float register.
8358 // If the double is a NAN, stuff a zero in instead.
8359 instruct convD2I_helper(regF dst, regD src, flagsRegF0 fcc0) %{
8360 effect(DEF dst, USE src, KILL fcc0);
8361 format %{ "FCMPd fcc0,$src,$src\t! check for NAN\n\t"
8362 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
8363 "FDTOI $src,$dst\t! convert in delay slot\n\t"
8364 "FITOS $dst,$dst\t! change NaN/max-int to valid float\n\t"
8365 "FSUBs $dst,$dst,$dst\t! cleared only if nan\n"
8366 "skip:" %}
8367 ins_encode(form_d2i_helper(src,dst));
8368 ins_pipe(fcvtD2I);
8369 %}
8370
8371 instruct convD2I_stk(stackSlotI dst, regD src) %{
8372 match(Set dst (ConvD2I src));
8373 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
8374 expand %{
8375 regF tmp;
8376 convD2I_helper(tmp, src);
8377 regF_to_stkI(dst, tmp);
8378 %}
8379 %}
8380
8381 instruct convD2I_reg(iRegI dst, regD src) %{
8382 predicate(UseVIS >= 3);
8383 match(Set dst (ConvD2I src));
8384 ins_cost(DEFAULT_COST*2 + BRANCH_COST);
8385 expand %{
8386 regF tmp;
8387 convD2I_helper(tmp, src);
8388 MoveF2I_reg_reg(dst, tmp);
8389 %}
8390 %}
8391
8392
8393 // Convert a double to a long in a double register.
8394 // If the double is a NAN, stuff a zero in instead.
8395 instruct convD2L_helper(regD dst, regD src, flagsRegF0 fcc0) %{
8396 effect(DEF dst, USE src, KILL fcc0);
8397 format %{ "FCMPd fcc0,$src,$src\t! check for NAN\n\t"
8398 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
8399 "FDTOX $src,$dst\t! convert in delay slot\n\t"
8400 "FXTOD $dst,$dst\t! change NaN/max-long to valid double\n\t"
8401 "FSUBd $dst,$dst,$dst\t! cleared only if nan\n"
8402 "skip:" %}
8403 ins_encode(form_d2l_helper(src,dst));
8404 ins_pipe(fcvtD2L);
8405 %}
8406
8407 instruct convD2L_stk(stackSlotL dst, regD src) %{
8408 match(Set dst (ConvD2L src));
8409 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
8410 expand %{
8411 regD tmp;
8412 convD2L_helper(tmp, src);
8413 regD_to_stkL(dst, tmp);
8414 %}
8415 %}
8416
8417 instruct convD2L_reg(iRegL dst, regD src) %{
8418 predicate(UseVIS >= 3);
8419 match(Set dst (ConvD2L src));
8420 ins_cost(DEFAULT_COST*2 + BRANCH_COST);
8421 expand %{
8422 regD tmp;
8423 convD2L_helper(tmp, src);
8424 MoveD2L_reg_reg(dst, tmp);
8425 %}
8426 %}
8427
8428
8429 instruct convF2D_reg(regD dst, regF src) %{
8430 match(Set dst (ConvF2D src));
8431 format %{ "FSTOD $src,$dst" %}
8432 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fstod_opf);
8433 ins_encode(form3_opf_rs2F_rdD(src, dst));
8434 ins_pipe(fcvtF2D);
8435 %}
8436
8437
8438 // Convert a float to an int in a float register.
8439 // If the float is a NAN, stuff a zero in instead.
8440 instruct convF2I_helper(regF dst, regF src, flagsRegF0 fcc0) %{
8441 effect(DEF dst, USE src, KILL fcc0);
8442 format %{ "FCMPs fcc0,$src,$src\t! check for NAN\n\t"
8443 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
8444 "FSTOI $src,$dst\t! convert in delay slot\n\t"
8445 "FITOS $dst,$dst\t! change NaN/max-int to valid float\n\t"
8446 "FSUBs $dst,$dst,$dst\t! cleared only if nan\n"
8447 "skip:" %}
8448 ins_encode(form_f2i_helper(src,dst));
8449 ins_pipe(fcvtF2I);
8450 %}
8451
8452 instruct convF2I_stk(stackSlotI dst, regF src) %{
8453 match(Set dst (ConvF2I src));
8454 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
8455 expand %{
8456 regF tmp;
8457 convF2I_helper(tmp, src);
8458 regF_to_stkI(dst, tmp);
8459 %}
8460 %}
8461
8462 instruct convF2I_reg(iRegI dst, regF src) %{
8463 predicate(UseVIS >= 3);
8464 match(Set dst (ConvF2I src));
8465 ins_cost(DEFAULT_COST*2 + BRANCH_COST);
8466 expand %{
8467 regF tmp;
8468 convF2I_helper(tmp, src);
8469 MoveF2I_reg_reg(dst, tmp);
8470 %}
8471 %}
8472
8473
8474 // Convert a float to a long in a float register.
8475 // If the float is a NAN, stuff a zero in instead.
8476 instruct convF2L_helper(regD dst, regF src, flagsRegF0 fcc0) %{
8477 effect(DEF dst, USE src, KILL fcc0);
8478 format %{ "FCMPs fcc0,$src,$src\t! check for NAN\n\t"
8479 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
8480 "FSTOX $src,$dst\t! convert in delay slot\n\t"
8481 "FXTOD $dst,$dst\t! change NaN/max-long to valid double\n\t"
8482 "FSUBd $dst,$dst,$dst\t! cleared only if nan\n"
8483 "skip:" %}
8484 ins_encode(form_f2l_helper(src,dst));
8485 ins_pipe(fcvtF2L);
8486 %}
8487
8488 instruct convF2L_stk(stackSlotL dst, regF src) %{
8489 match(Set dst (ConvF2L src));
8490 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
8491 expand %{
8492 regD tmp;
8493 convF2L_helper(tmp, src);
8494 regD_to_stkL(dst, tmp);
8495 %}
8496 %}
8497
8498 instruct convF2L_reg(iRegL dst, regF src) %{
8499 predicate(UseVIS >= 3);
8500 match(Set dst (ConvF2L src));
8501 ins_cost(DEFAULT_COST*2 + BRANCH_COST);
8502 expand %{
8503 regD tmp;
8504 convF2L_helper(tmp, src);
8505 MoveD2L_reg_reg(dst, tmp);
8506 %}
8507 %}
8508
8509
8510 instruct convI2D_helper(regD dst, regF tmp) %{
8511 effect(USE tmp, DEF dst);
8512 format %{ "FITOD $tmp,$dst" %}
8513 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf);
8514 ins_encode(form3_opf_rs2F_rdD(tmp, dst));
8515 ins_pipe(fcvtI2D);
8516 %}
8517
8518 instruct convI2D_stk(stackSlotI src, regD dst) %{
8519 match(Set dst (ConvI2D src));
8520 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8521 expand %{
8522 regF tmp;
8523 stkI_to_regF(tmp, src);
8524 convI2D_helper(dst, tmp);
8525 %}
8526 %}
8527
8528 instruct convI2D_reg(regD_low dst, iRegI src) %{
8529 predicate(UseVIS >= 3);
8530 match(Set dst (ConvI2D src));
8531 expand %{
8532 regF tmp;
8533 MoveI2F_reg_reg(tmp, src);
8534 convI2D_helper(dst, tmp);
8535 %}
8536 %}
8537
8538 instruct convI2D_mem(regD_low dst, memory mem) %{
8539 match(Set dst (ConvI2D (LoadI mem)));
8540 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8541 size(8);
8542 format %{ "LDF $mem,$dst\n\t"
8543 "FITOD $dst,$dst" %}
8544 opcode(Assembler::ldf_op3, Assembler::fitod_opf);
8545 ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst));
8546 ins_pipe(floadF_mem);
8547 %}
8548
8549
8550 instruct convI2F_helper(regF dst, regF tmp) %{
8551 effect(DEF dst, USE tmp);
8552 format %{ "FITOS $tmp,$dst" %}
8553 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitos_opf);
8554 ins_encode(form3_opf_rs2F_rdF(tmp, dst));
8555 ins_pipe(fcvtI2F);
8556 %}
8557
8558 instruct convI2F_stk(regF dst, stackSlotI src) %{
8559 match(Set dst (ConvI2F src));
8560 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8561 expand %{
8562 regF tmp;
8563 stkI_to_regF(tmp,src);
8564 convI2F_helper(dst, tmp);
8565 %}
8566 %}
8567
8568 instruct convI2F_reg(regF dst, iRegI src) %{
8569 predicate(UseVIS >= 3);
8570 match(Set dst (ConvI2F src));
8571 ins_cost(DEFAULT_COST);
8572 expand %{
8573 regF tmp;
8574 MoveI2F_reg_reg(tmp, src);
8575 convI2F_helper(dst, tmp);
8576 %}
8577 %}
8578
8579 instruct convI2F_mem( regF dst, memory mem ) %{
8580 match(Set dst (ConvI2F (LoadI mem)));
8581 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8582 size(8);
8583 format %{ "LDF $mem,$dst\n\t"
8584 "FITOS $dst,$dst" %}
8585 opcode(Assembler::ldf_op3, Assembler::fitos_opf);
8586 ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst));
8587 ins_pipe(floadF_mem);
8588 %}
8589
8590
8591 instruct convI2L_reg(iRegL dst, iRegI src) %{
8592 match(Set dst (ConvI2L src));
8593 size(4);
8594 format %{ "SRA $src,0,$dst\t! int->long" %}
8595 opcode(Assembler::sra_op3, Assembler::arith_op);
8596 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) );
8597 ins_pipe(ialu_reg_reg);
8598 %}
8599
8600 // Zero-extend convert int to long
8601 instruct convI2L_reg_zex(iRegL dst, iRegI src, immL_32bits mask ) %{
8602 match(Set dst (AndL (ConvI2L src) mask) );
8603 size(4);
8604 format %{ "SRL $src,0,$dst\t! zero-extend int to long" %}
8605 opcode(Assembler::srl_op3, Assembler::arith_op);
8606 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) );
8607 ins_pipe(ialu_reg_reg);
8608 %}
8609
8610 // Zero-extend long
8611 instruct zerox_long(iRegL dst, iRegL src, immL_32bits mask ) %{
8612 match(Set dst (AndL src mask) );
8613 size(4);
8614 format %{ "SRL $src,0,$dst\t! zero-extend long" %}
8615 opcode(Assembler::srl_op3, Assembler::arith_op);
8616 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) );
8617 ins_pipe(ialu_reg_reg);
8618 %}
8619
8620
8621 //-----------
8622 // Long to Double conversion using V8 opcodes.
8623 // Still useful because cheetah traps and becomes
8624 // amazingly slow for some common numbers.
8625
8626 // Magic constant, 0x43300000
8627 instruct loadConI_x43300000(iRegI dst) %{
8628 effect(DEF dst);
8629 size(4);
8630 format %{ "SETHI HI(0x43300000),$dst\t! 2^52" %}
8631 ins_encode(SetHi22(0x43300000, dst));
8632 ins_pipe(ialu_none);
8633 %}
8634
8635 // Magic constant, 0x41f00000
8636 instruct loadConI_x41f00000(iRegI dst) %{
8637 effect(DEF dst);
8638 size(4);
8639 format %{ "SETHI HI(0x41f00000),$dst\t! 2^32" %}
8640 ins_encode(SetHi22(0x41f00000, dst));
8641 ins_pipe(ialu_none);
8642 %}
8643
8644 // Construct a double from two float halves
8645 instruct regDHi_regDLo_to_regD(regD_low dst, regD_low src1, regD_low src2) %{
8646 effect(DEF dst, USE src1, USE src2);
8647 size(8);
8648 format %{ "FMOVS $src1.hi,$dst.hi\n\t"
8649 "FMOVS $src2.lo,$dst.lo" %}
8650 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmovs_opf);
8651 ins_encode(form3_opf_rs2D_hi_rdD_hi(src1, dst), form3_opf_rs2D_lo_rdD_lo(src2, dst));
8652 ins_pipe(faddD_reg_reg);
8653 %}
8654
8655 // Convert integer in high half of a double register (in the lower half of
8656 // the double register file) to double
8657 instruct convI2D_regDHi_regD(regD dst, regD_low src) %{
8658 effect(DEF dst, USE src);
8659 size(4);
8660 format %{ "FITOD $src,$dst" %}
8661 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf);
8662 ins_encode(form3_opf_rs2D_rdD(src, dst));
8663 ins_pipe(fcvtLHi2D);
8664 %}
8665
8666 // Add float double precision
8667 instruct addD_regD_regD(regD dst, regD src1, regD src2) %{
8668 effect(DEF dst, USE src1, USE src2);
8669 size(4);
8670 format %{ "FADDD $src1,$src2,$dst" %}
8671 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::faddd_opf);
8672 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
8673 ins_pipe(faddD_reg_reg);
8674 %}
8675
8676 // Sub float double precision
8677 instruct subD_regD_regD(regD dst, regD src1, regD src2) %{
8678 effect(DEF dst, USE src1, USE src2);
8679 size(4);
8680 format %{ "FSUBD $src1,$src2,$dst" %}
8681 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubd_opf);
8682 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
8683 ins_pipe(faddD_reg_reg);
8684 %}
8685
8686 // Mul float double precision
8687 instruct mulD_regD_regD(regD dst, regD src1, regD src2) %{
8688 effect(DEF dst, USE src1, USE src2);
8689 size(4);
8690 format %{ "FMULD $src1,$src2,$dst" %}
8691 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuld_opf);
8692 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
8693 ins_pipe(fmulD_reg_reg);
8694 %}
8695
8696 instruct convL2D_reg_slow_fxtof(regD dst, stackSlotL src) %{
8697 match(Set dst (ConvL2D src));
8698 ins_cost(DEFAULT_COST*8 + MEMORY_REF_COST*6);
8699
8700 expand %{
8701 regD_low tmpsrc;
8702 iRegI ix43300000;
8703 iRegI ix41f00000;
8704 stackSlotL lx43300000;
8705 stackSlotL lx41f00000;
8706 regD_low dx43300000;
8707 regD dx41f00000;
8708 regD tmp1;
8709 regD_low tmp2;
8710 regD tmp3;
8711 regD tmp4;
8712
8713 stkL_to_regD(tmpsrc, src);
8714
8715 loadConI_x43300000(ix43300000);
8716 loadConI_x41f00000(ix41f00000);
8717 regI_to_stkLHi(lx43300000, ix43300000);
8718 regI_to_stkLHi(lx41f00000, ix41f00000);
8719 stkL_to_regD(dx43300000, lx43300000);
8720 stkL_to_regD(dx41f00000, lx41f00000);
8721
8722 convI2D_regDHi_regD(tmp1, tmpsrc);
8723 regDHi_regDLo_to_regD(tmp2, dx43300000, tmpsrc);
8724 subD_regD_regD(tmp3, tmp2, dx43300000);
8725 mulD_regD_regD(tmp4, tmp1, dx41f00000);
8726 addD_regD_regD(dst, tmp3, tmp4);
8727 %}
8728 %}
8729
8730 // Long to Double conversion using fast fxtof
8731 instruct convL2D_helper(regD dst, regD tmp) %{
8732 effect(DEF dst, USE tmp);
8733 size(4);
8734 format %{ "FXTOD $tmp,$dst" %}
8735 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtod_opf);
8736 ins_encode(form3_opf_rs2D_rdD(tmp, dst));
8737 ins_pipe(fcvtL2D);
8738 %}
8739
8740 instruct convL2D_stk_fast_fxtof(regD dst, stackSlotL src) %{
8741 predicate(VM_Version::has_fast_fxtof());
8742 match(Set dst (ConvL2D src));
8743 ins_cost(DEFAULT_COST + 3 * MEMORY_REF_COST);
8744 expand %{
8745 regD tmp;
8746 stkL_to_regD(tmp, src);
8747 convL2D_helper(dst, tmp);
8748 %}
8749 %}
8750
8751 instruct convL2D_reg(regD dst, iRegL src) %{
8752 predicate(UseVIS >= 3);
8753 match(Set dst (ConvL2D src));
8754 expand %{
8755 regD tmp;
8756 MoveL2D_reg_reg(tmp, src);
8757 convL2D_helper(dst, tmp);
8758 %}
8759 %}
8760
8761 // Long to Float conversion using fast fxtof
8762 instruct convL2F_helper(regF dst, regD tmp) %{
8763 effect(DEF dst, USE tmp);
8764 size(4);
8765 format %{ "FXTOS $tmp,$dst" %}
8766 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtos_opf);
8767 ins_encode(form3_opf_rs2D_rdF(tmp, dst));
8768 ins_pipe(fcvtL2F);
8769 %}
8770
8771 instruct convL2F_stk_fast_fxtof(regF dst, stackSlotL src) %{
8772 match(Set dst (ConvL2F src));
8773 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8774 expand %{
8775 regD tmp;
8776 stkL_to_regD(tmp, src);
8777 convL2F_helper(dst, tmp);
8778 %}
8779 %}
8780
8781 instruct convL2F_reg(regF dst, iRegL src) %{
8782 predicate(UseVIS >= 3);
8783 match(Set dst (ConvL2F src));
8784 ins_cost(DEFAULT_COST);
8785 expand %{
8786 regD tmp;
8787 MoveL2D_reg_reg(tmp, src);
8788 convL2F_helper(dst, tmp);
8789 %}
8790 %}
8791
8792 //-----------
8793
8794 instruct convL2I_reg(iRegI dst, iRegL src) %{
8795 match(Set dst (ConvL2I src));
8796 #ifndef _LP64
8797 format %{ "MOV $src.lo,$dst\t! long->int" %}
8798 ins_encode( form3_g0_rs2_rd_move_lo2( src, dst ) );
8799 ins_pipe(ialu_move_reg_I_to_L);
8800 #else
8801 size(4);
8802 format %{ "SRA $src,R_G0,$dst\t! long->int" %}
8803 ins_encode( form3_rs1_rd_signextend_lo1( src, dst ) );
8804 ins_pipe(ialu_reg);
8805 #endif
8806 %}
8807
8808 // Register Shift Right Immediate
8809 instruct shrL_reg_imm6_L2I(iRegI dst, iRegL src, immI_32_63 cnt) %{
8810 match(Set dst (ConvL2I (RShiftL src cnt)));
8811
8812 size(4);
8813 format %{ "SRAX $src,$cnt,$dst" %}
8814 opcode(Assembler::srax_op3, Assembler::arith_op);
8815 ins_encode( form3_sd_rs1_imm6_rd( src, cnt, dst ) );
8816 ins_pipe(ialu_reg_imm);
8817 %}
8818
8819 //----------Control Flow Instructions------------------------------------------
8820 // Compare Instructions
8821 // Compare Integers
8822 instruct compI_iReg(flagsReg icc, iRegI op1, iRegI op2) %{
8823 match(Set icc (CmpI op1 op2));
8824 effect( DEF icc, USE op1, USE op2 );
8825
8826 size(4);
8827 format %{ "CMP $op1,$op2" %}
8828 opcode(Assembler::subcc_op3, Assembler::arith_op);
8829 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8830 ins_pipe(ialu_cconly_reg_reg);
8831 %}
8832
8833 instruct compU_iReg(flagsRegU icc, iRegI op1, iRegI op2) %{
8834 match(Set icc (CmpU op1 op2));
8835
8836 size(4);
8837 format %{ "CMP $op1,$op2\t! unsigned" %}
8838 opcode(Assembler::subcc_op3, Assembler::arith_op);
8839 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8840 ins_pipe(ialu_cconly_reg_reg);
8841 %}
8842
8843 instruct compI_iReg_imm13(flagsReg icc, iRegI op1, immI13 op2) %{
8844 match(Set icc (CmpI op1 op2));
8845 effect( DEF icc, USE op1 );
8846
8847 size(4);
8848 format %{ "CMP $op1,$op2" %}
8849 opcode(Assembler::subcc_op3, Assembler::arith_op);
8850 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8851 ins_pipe(ialu_cconly_reg_imm);
8852 %}
8853
8854 instruct testI_reg_reg( flagsReg icc, iRegI op1, iRegI op2, immI0 zero ) %{
8855 match(Set icc (CmpI (AndI op1 op2) zero));
8856
8857 size(4);
8858 format %{ "BTST $op2,$op1" %}
8859 opcode(Assembler::andcc_op3, Assembler::arith_op);
8860 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8861 ins_pipe(ialu_cconly_reg_reg_zero);
8862 %}
8863
8864 instruct testI_reg_imm( flagsReg icc, iRegI op1, immI13 op2, immI0 zero ) %{
8865 match(Set icc (CmpI (AndI op1 op2) zero));
8866
8867 size(4);
8868 format %{ "BTST $op2,$op1" %}
8869 opcode(Assembler::andcc_op3, Assembler::arith_op);
8870 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8871 ins_pipe(ialu_cconly_reg_imm_zero);
8872 %}
8873
8874 instruct compL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2 ) %{
8875 match(Set xcc (CmpL op1 op2));
8876 effect( DEF xcc, USE op1, USE op2 );
8877
8878 size(4);
8879 format %{ "CMP $op1,$op2\t\t! long" %}
8880 opcode(Assembler::subcc_op3, Assembler::arith_op);
8881 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8882 ins_pipe(ialu_cconly_reg_reg);
8883 %}
8884
8885 instruct compL_reg_con(flagsRegL xcc, iRegL op1, immL13 con) %{
8886 match(Set xcc (CmpL op1 con));
8887 effect( DEF xcc, USE op1, USE con );
8888
8889 size(4);
8890 format %{ "CMP $op1,$con\t\t! long" %}
8891 opcode(Assembler::subcc_op3, Assembler::arith_op);
8892 ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) );
8893 ins_pipe(ialu_cconly_reg_reg);
8894 %}
8895
8896 instruct testL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2, immL0 zero) %{
8897 match(Set xcc (CmpL (AndL op1 op2) zero));
8898 effect( DEF xcc, USE op1, USE op2 );
8899
8900 size(4);
8901 format %{ "BTST $op1,$op2\t\t! long" %}
8902 opcode(Assembler::andcc_op3, Assembler::arith_op);
8903 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8904 ins_pipe(ialu_cconly_reg_reg);
8905 %}
8906
8907 // useful for checking the alignment of a pointer:
8908 instruct testL_reg_con(flagsRegL xcc, iRegL op1, immL13 con, immL0 zero) %{
8909 match(Set xcc (CmpL (AndL op1 con) zero));
8910 effect( DEF xcc, USE op1, USE con );
8911
8912 size(4);
8913 format %{ "BTST $op1,$con\t\t! long" %}
8914 opcode(Assembler::andcc_op3, Assembler::arith_op);
8915 ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) );
8916 ins_pipe(ialu_cconly_reg_reg);
8917 %}
8918
8919 instruct compU_iReg_imm13(flagsRegU icc, iRegI op1, immU13 op2 ) %{
8920 match(Set icc (CmpU op1 op2));
8921
8922 size(4);
8923 format %{ "CMP $op1,$op2\t! unsigned" %}
8924 opcode(Assembler::subcc_op3, Assembler::arith_op);
8925 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8926 ins_pipe(ialu_cconly_reg_imm);
8927 %}
8928
8929 // Compare Pointers
8930 instruct compP_iRegP(flagsRegP pcc, iRegP op1, iRegP op2 ) %{
8931 match(Set pcc (CmpP op1 op2));
8932
8933 size(4);
8934 format %{ "CMP $op1,$op2\t! ptr" %}
8935 opcode(Assembler::subcc_op3, Assembler::arith_op);
8936 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8937 ins_pipe(ialu_cconly_reg_reg);
8938 %}
8939
8940 instruct compP_iRegP_imm13(flagsRegP pcc, iRegP op1, immP13 op2 ) %{
8941 match(Set pcc (CmpP op1 op2));
8942
8943 size(4);
8944 format %{ "CMP $op1,$op2\t! ptr" %}
8945 opcode(Assembler::subcc_op3, Assembler::arith_op);
8946 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8947 ins_pipe(ialu_cconly_reg_imm);
8948 %}
8949
8950 // Compare Narrow oops
8951 instruct compN_iRegN(flagsReg icc, iRegN op1, iRegN op2 ) %{
8952 match(Set icc (CmpN op1 op2));
8953
8954 size(4);
8955 format %{ "CMP $op1,$op2\t! compressed ptr" %}
8956 opcode(Assembler::subcc_op3, Assembler::arith_op);
8957 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8958 ins_pipe(ialu_cconly_reg_reg);
8959 %}
8960
8961 instruct compN_iRegN_immN0(flagsReg icc, iRegN op1, immN0 op2 ) %{
8962 match(Set icc (CmpN op1 op2));
8963
8964 size(4);
8965 format %{ "CMP $op1,$op2\t! compressed ptr" %}
8966 opcode(Assembler::subcc_op3, Assembler::arith_op);
8967 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8968 ins_pipe(ialu_cconly_reg_imm);
8969 %}
8970
8971 //----------Max and Min--------------------------------------------------------
8972 // Min Instructions
8973 // Conditional move for min
8974 instruct cmovI_reg_lt( iRegI op2, iRegI op1, flagsReg icc ) %{
8975 effect( USE_DEF op2, USE op1, USE icc );
8976
8977 size(4);
8978 format %{ "MOVlt icc,$op1,$op2\t! min" %}
8979 opcode(Assembler::less);
8980 ins_encode( enc_cmov_reg_minmax(op2,op1) );
8981 ins_pipe(ialu_reg_flags);
8982 %}
8983
8984 // Min Register with Register.
8985 instruct minI_eReg(iRegI op1, iRegI op2) %{
8986 match(Set op2 (MinI op1 op2));
8987 ins_cost(DEFAULT_COST*2);
8988 expand %{
8989 flagsReg icc;
8990 compI_iReg(icc,op1,op2);
8991 cmovI_reg_lt(op2,op1,icc);
8992 %}
8993 %}
8994
8995 // Max Instructions
8996 // Conditional move for max
8997 instruct cmovI_reg_gt( iRegI op2, iRegI op1, flagsReg icc ) %{
8998 effect( USE_DEF op2, USE op1, USE icc );
8999 format %{ "MOVgt icc,$op1,$op2\t! max" %}
9000 opcode(Assembler::greater);
9001 ins_encode( enc_cmov_reg_minmax(op2,op1) );
9002 ins_pipe(ialu_reg_flags);
9003 %}
9004
9005 // Max Register with Register
9006 instruct maxI_eReg(iRegI op1, iRegI op2) %{
9007 match(Set op2 (MaxI op1 op2));
9008 ins_cost(DEFAULT_COST*2);
9009 expand %{
9010 flagsReg icc;
9011 compI_iReg(icc,op1,op2);
9012 cmovI_reg_gt(op2,op1,icc);
9013 %}
9014 %}
9015
9016
9017 //----------Float Compares----------------------------------------------------
9018 // Compare floating, generate condition code
9019 instruct cmpF_cc(flagsRegF fcc, regF src1, regF src2) %{
9020 match(Set fcc (CmpF src1 src2));
9021
9022 size(4);
9023 format %{ "FCMPs $fcc,$src1,$src2" %}
9024 opcode(Assembler::fpop2_op3, Assembler::arith_op, Assembler::fcmps_opf);
9025 ins_encode( form3_opf_rs1F_rs2F_fcc( src1, src2, fcc ) );
9026 ins_pipe(faddF_fcc_reg_reg_zero);
9027 %}
9028
9029 instruct cmpD_cc(flagsRegF fcc, regD src1, regD src2) %{
9030 match(Set fcc (CmpD src1 src2));
9031
9032 size(4);
9033 format %{ "FCMPd $fcc,$src1,$src2" %}
9034 opcode(Assembler::fpop2_op3, Assembler::arith_op, Assembler::fcmpd_opf);
9035 ins_encode( form3_opf_rs1D_rs2D_fcc( src1, src2, fcc ) );
9036 ins_pipe(faddD_fcc_reg_reg_zero);
9037 %}
9038
9039
9040 // Compare floating, generate -1,0,1
9041 instruct cmpF_reg(iRegI dst, regF src1, regF src2, flagsRegF0 fcc0) %{
9042 match(Set dst (CmpF3 src1 src2));
9043 effect(KILL fcc0);
9044 ins_cost(DEFAULT_COST*3+BRANCH_COST*3);
9045 format %{ "fcmpl $dst,$src1,$src2" %}
9046 // Primary = float
9047 opcode( true );
9048 ins_encode( floating_cmp( dst, src1, src2 ) );
9049 ins_pipe( floating_cmp );
9050 %}
9051
9052 instruct cmpD_reg(iRegI dst, regD src1, regD src2, flagsRegF0 fcc0) %{
9053 match(Set dst (CmpD3 src1 src2));
9054 effect(KILL fcc0);
9055 ins_cost(DEFAULT_COST*3+BRANCH_COST*3);
9056 format %{ "dcmpl $dst,$src1,$src2" %}
9057 // Primary = double (not float)
9058 opcode( false );
9059 ins_encode( floating_cmp( dst, src1, src2 ) );
9060 ins_pipe( floating_cmp );
9061 %}
9062
9063 //----------Branches---------------------------------------------------------
9064 // Jump
9065 // (compare 'operand indIndex' and 'instruct addP_reg_reg' above)
9066 instruct jumpXtnd(iRegX switch_val, o7RegI table) %{
9067 match(Jump switch_val);
9068 effect(TEMP table);
9069
9070 ins_cost(350);
9071
9072 format %{ "ADD $constanttablebase, $constantoffset, O7\n\t"
9073 "LD [O7 + $switch_val], O7\n\t"
9074 "JUMP O7" %}
9075 ins_encode %{
9076 // Calculate table address into a register.
9077 Register table_reg;
9078 Register label_reg = O7;
9079 // If we are calculating the size of this instruction don't trust
9080 // zero offsets because they might change when
9081 // MachConstantBaseNode decides to optimize the constant table
9082 // base.
9083 if ((constant_offset() == 0) && !Compile::current()->in_scratch_emit_size()) {
9084 table_reg = $constanttablebase;
9085 } else {
9086 table_reg = O7;
9087 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset, O7);
9088 __ add($constanttablebase, con_offset, table_reg);
9089 }
9090
9091 // Jump to base address + switch value
9092 __ ld_ptr(table_reg, $switch_val$$Register, label_reg);
9093 __ jmp(label_reg, G0);
9094 __ delayed()->nop();
9095 %}
9096 ins_pipe(ialu_reg_reg);
9097 %}
9098
9099 // Direct Branch. Use V8 version with longer range.
9100 instruct branch(label labl) %{
9101 match(Goto);
9102 effect(USE labl);
9103
9104 size(8);
9105 ins_cost(BRANCH_COST);
9106 format %{ "BA $labl" %}
9107 ins_encode %{
9108 Label* L = $labl$$label;
9109 __ ba(*L);
9110 __ delayed()->nop();
9111 %}
9112 ins_pipe(br);
9113 %}
9114
9115 // Direct Branch, short with no delay slot
9116 instruct branch_short(label labl) %{
9117 match(Goto);
9118 predicate(UseCBCond);
9119 effect(USE labl);
9120
9121 size(4);
9122 ins_cost(BRANCH_COST);
9123 format %{ "BA $labl\t! short branch" %}
9124 ins_encode %{
9125 Label* L = $labl$$label;
9126 assert(__ use_cbcond(*L), "back to back cbcond");
9127 __ ba_short(*L);
9128 %}
9129 ins_short_branch(1);
9130 ins_avoid_back_to_back(1);
9131 ins_pipe(cbcond_reg_imm);
9132 %}
9133
9134 // Conditional Direct Branch
9135 instruct branchCon(cmpOp cmp, flagsReg icc, label labl) %{
9136 match(If cmp icc);
9137 effect(USE labl);
9138
9139 size(8);
9140 ins_cost(BRANCH_COST);
9141 format %{ "BP$cmp $icc,$labl" %}
9142 // Prim = bits 24-22, Secnd = bits 31-30
9143 ins_encode( enc_bp( labl, cmp, icc ) );
9144 ins_pipe(br_cc);
9145 %}
9146
9147 instruct branchConU(cmpOpU cmp, flagsRegU icc, label labl) %{
9148 match(If cmp icc);
9149 effect(USE labl);
9150
9151 ins_cost(BRANCH_COST);
9152 format %{ "BP$cmp $icc,$labl" %}
9153 // Prim = bits 24-22, Secnd = bits 31-30
9154 ins_encode( enc_bp( labl, cmp, icc ) );
9155 ins_pipe(br_cc);
9156 %}
9157
9158 instruct branchConP(cmpOpP cmp, flagsRegP pcc, label labl) %{
9159 match(If cmp pcc);
9160 effect(USE labl);
9161
9162 size(8);
9163 ins_cost(BRANCH_COST);
9164 format %{ "BP$cmp $pcc,$labl" %}
9165 ins_encode %{
9166 Label* L = $labl$$label;
9167 Assembler::Predict predict_taken =
9168 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9169
9170 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, *L);
9171 __ delayed()->nop();
9172 %}
9173 ins_pipe(br_cc);
9174 %}
9175
9176 instruct branchConF(cmpOpF cmp, flagsRegF fcc, label labl) %{
9177 match(If cmp fcc);
9178 effect(USE labl);
9179
9180 size(8);
9181 ins_cost(BRANCH_COST);
9182 format %{ "FBP$cmp $fcc,$labl" %}
9183 ins_encode %{
9184 Label* L = $labl$$label;
9185 Assembler::Predict predict_taken =
9186 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9187
9188 __ fbp( (Assembler::Condition)($cmp$$cmpcode), false, (Assembler::CC)($fcc$$reg), predict_taken, *L);
9189 __ delayed()->nop();
9190 %}
9191 ins_pipe(br_fcc);
9192 %}
9193
9194 instruct branchLoopEnd(cmpOp cmp, flagsReg icc, label labl) %{
9195 match(CountedLoopEnd cmp icc);
9196 effect(USE labl);
9197
9198 size(8);
9199 ins_cost(BRANCH_COST);
9200 format %{ "BP$cmp $icc,$labl\t! Loop end" %}
9201 // Prim = bits 24-22, Secnd = bits 31-30
9202 ins_encode( enc_bp( labl, cmp, icc ) );
9203 ins_pipe(br_cc);
9204 %}
9205
9206 instruct branchLoopEndU(cmpOpU cmp, flagsRegU icc, label labl) %{
9207 match(CountedLoopEnd cmp icc);
9208 effect(USE labl);
9209
9210 size(8);
9211 ins_cost(BRANCH_COST);
9212 format %{ "BP$cmp $icc,$labl\t! Loop end" %}
9213 // Prim = bits 24-22, Secnd = bits 31-30
9214 ins_encode( enc_bp( labl, cmp, icc ) );
9215 ins_pipe(br_cc);
9216 %}
9217
9218 // Compare and branch instructions
9219 instruct cmpI_reg_branch(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{
9220 match(If cmp (CmpI op1 op2));
9221 effect(USE labl, KILL icc);
9222
9223 size(12);
9224 ins_cost(BRANCH_COST);
9225 format %{ "CMP $op1,$op2\t! int\n\t"
9226 "BP$cmp $labl" %}
9227 ins_encode %{
9228 Label* L = $labl$$label;
9229 Assembler::Predict predict_taken =
9230 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9231 __ cmp($op1$$Register, $op2$$Register);
9232 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9233 __ delayed()->nop();
9234 %}
9235 ins_pipe(cmp_br_reg_reg);
9236 %}
9237
9238 instruct cmpI_imm_branch(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{
9239 match(If cmp (CmpI op1 op2));
9240 effect(USE labl, KILL icc);
9241
9242 size(12);
9243 ins_cost(BRANCH_COST);
9244 format %{ "CMP $op1,$op2\t! int\n\t"
9245 "BP$cmp $labl" %}
9246 ins_encode %{
9247 Label* L = $labl$$label;
9248 Assembler::Predict predict_taken =
9249 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9250 __ cmp($op1$$Register, $op2$$constant);
9251 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9252 __ delayed()->nop();
9253 %}
9254 ins_pipe(cmp_br_reg_imm);
9255 %}
9256
9257 instruct cmpU_reg_branch(cmpOpU cmp, iRegI op1, iRegI op2, label labl, flagsRegU icc) %{
9258 match(If cmp (CmpU op1 op2));
9259 effect(USE labl, KILL icc);
9260
9261 size(12);
9262 ins_cost(BRANCH_COST);
9263 format %{ "CMP $op1,$op2\t! unsigned\n\t"
9264 "BP$cmp $labl" %}
9265 ins_encode %{
9266 Label* L = $labl$$label;
9267 Assembler::Predict predict_taken =
9268 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9269 __ cmp($op1$$Register, $op2$$Register);
9270 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9271 __ delayed()->nop();
9272 %}
9273 ins_pipe(cmp_br_reg_reg);
9274 %}
9275
9276 instruct cmpU_imm_branch(cmpOpU cmp, iRegI op1, immI5 op2, label labl, flagsRegU icc) %{
9277 match(If cmp (CmpU op1 op2));
9278 effect(USE labl, KILL icc);
9279
9280 size(12);
9281 ins_cost(BRANCH_COST);
9282 format %{ "CMP $op1,$op2\t! unsigned\n\t"
9283 "BP$cmp $labl" %}
9284 ins_encode %{
9285 Label* L = $labl$$label;
9286 Assembler::Predict predict_taken =
9287 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9288 __ cmp($op1$$Register, $op2$$constant);
9289 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9290 __ delayed()->nop();
9291 %}
9292 ins_pipe(cmp_br_reg_imm);
9293 %}
9294
9295 instruct cmpL_reg_branch(cmpOp cmp, iRegL op1, iRegL op2, label labl, flagsRegL xcc) %{
9296 match(If cmp (CmpL op1 op2));
9297 effect(USE labl, KILL xcc);
9298
9299 size(12);
9300 ins_cost(BRANCH_COST);
9301 format %{ "CMP $op1,$op2\t! long\n\t"
9302 "BP$cmp $labl" %}
9303 ins_encode %{
9304 Label* L = $labl$$label;
9305 Assembler::Predict predict_taken =
9306 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9307 __ cmp($op1$$Register, $op2$$Register);
9308 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L);
9309 __ delayed()->nop();
9310 %}
9311 ins_pipe(cmp_br_reg_reg);
9312 %}
9313
9314 instruct cmpL_imm_branch(cmpOp cmp, iRegL op1, immL5 op2, label labl, flagsRegL xcc) %{
9315 match(If cmp (CmpL op1 op2));
9316 effect(USE labl, KILL xcc);
9317
9318 size(12);
9319 ins_cost(BRANCH_COST);
9320 format %{ "CMP $op1,$op2\t! long\n\t"
9321 "BP$cmp $labl" %}
9322 ins_encode %{
9323 Label* L = $labl$$label;
9324 Assembler::Predict predict_taken =
9325 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9326 __ cmp($op1$$Register, $op2$$constant);
9327 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L);
9328 __ delayed()->nop();
9329 %}
9330 ins_pipe(cmp_br_reg_imm);
9331 %}
9332
9333 // Compare Pointers and branch
9334 instruct cmpP_reg_branch(cmpOpP cmp, iRegP op1, iRegP op2, label labl, flagsRegP pcc) %{
9335 match(If cmp (CmpP op1 op2));
9336 effect(USE labl, KILL pcc);
9337
9338 size(12);
9339 ins_cost(BRANCH_COST);
9340 format %{ "CMP $op1,$op2\t! ptr\n\t"
9341 "B$cmp $labl" %}
9342 ins_encode %{
9343 Label* L = $labl$$label;
9344 Assembler::Predict predict_taken =
9345 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9346 __ cmp($op1$$Register, $op2$$Register);
9347 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, *L);
9348 __ delayed()->nop();
9349 %}
9350 ins_pipe(cmp_br_reg_reg);
9351 %}
9352
9353 instruct cmpP_null_branch(cmpOpP cmp, iRegP op1, immP0 null, label labl, flagsRegP pcc) %{
9354 match(If cmp (CmpP op1 null));
9355 effect(USE labl, KILL pcc);
9356
9357 size(12);
9358 ins_cost(BRANCH_COST);
9359 format %{ "CMP $op1,0\t! ptr\n\t"
9360 "B$cmp $labl" %}
9361 ins_encode %{
9362 Label* L = $labl$$label;
9363 Assembler::Predict predict_taken =
9364 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9365 __ cmp($op1$$Register, G0);
9366 // bpr() is not used here since it has shorter distance.
9367 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, *L);
9368 __ delayed()->nop();
9369 %}
9370 ins_pipe(cmp_br_reg_reg);
9371 %}
9372
9373 instruct cmpN_reg_branch(cmpOp cmp, iRegN op1, iRegN op2, label labl, flagsReg icc) %{
9374 match(If cmp (CmpN op1 op2));
9375 effect(USE labl, KILL icc);
9376
9377 size(12);
9378 ins_cost(BRANCH_COST);
9379 format %{ "CMP $op1,$op2\t! compressed ptr\n\t"
9380 "BP$cmp $labl" %}
9381 ins_encode %{
9382 Label* L = $labl$$label;
9383 Assembler::Predict predict_taken =
9384 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9385 __ cmp($op1$$Register, $op2$$Register);
9386 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9387 __ delayed()->nop();
9388 %}
9389 ins_pipe(cmp_br_reg_reg);
9390 %}
9391
9392 instruct cmpN_null_branch(cmpOp cmp, iRegN op1, immN0 null, label labl, flagsReg icc) %{
9393 match(If cmp (CmpN op1 null));
9394 effect(USE labl, KILL icc);
9395
9396 size(12);
9397 ins_cost(BRANCH_COST);
9398 format %{ "CMP $op1,0\t! compressed ptr\n\t"
9399 "BP$cmp $labl" %}
9400 ins_encode %{
9401 Label* L = $labl$$label;
9402 Assembler::Predict predict_taken =
9403 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9404 __ cmp($op1$$Register, G0);
9405 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9406 __ delayed()->nop();
9407 %}
9408 ins_pipe(cmp_br_reg_reg);
9409 %}
9410
9411 // Loop back branch
9412 instruct cmpI_reg_branchLoopEnd(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{
9413 match(CountedLoopEnd cmp (CmpI op1 op2));
9414 effect(USE labl, KILL icc);
9415
9416 size(12);
9417 ins_cost(BRANCH_COST);
9418 format %{ "CMP $op1,$op2\t! int\n\t"
9419 "BP$cmp $labl\t! Loop end" %}
9420 ins_encode %{
9421 Label* L = $labl$$label;
9422 Assembler::Predict predict_taken =
9423 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9424 __ cmp($op1$$Register, $op2$$Register);
9425 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9426 __ delayed()->nop();
9427 %}
9428 ins_pipe(cmp_br_reg_reg);
9429 %}
9430
9431 instruct cmpI_imm_branchLoopEnd(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{
9432 match(CountedLoopEnd cmp (CmpI op1 op2));
9433 effect(USE labl, KILL icc);
9434
9435 size(12);
9436 ins_cost(BRANCH_COST);
9437 format %{ "CMP $op1,$op2\t! int\n\t"
9438 "BP$cmp $labl\t! Loop end" %}
9439 ins_encode %{
9440 Label* L = $labl$$label;
9441 Assembler::Predict predict_taken =
9442 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9443 __ cmp($op1$$Register, $op2$$constant);
9444 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9445 __ delayed()->nop();
9446 %}
9447 ins_pipe(cmp_br_reg_imm);
9448 %}
9449
9450 // Short compare and branch instructions
9451 instruct cmpI_reg_branch_short(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{
9452 match(If cmp (CmpI op1 op2));
9453 predicate(UseCBCond);
9454 effect(USE labl, KILL icc);
9455
9456 size(4);
9457 ins_cost(BRANCH_COST);
9458 format %{ "CWB$cmp $op1,$op2,$labl\t! int" %}
9459 ins_encode %{
9460 Label* L = $labl$$label;
9461 assert(__ use_cbcond(*L), "back to back cbcond");
9462 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L);
9463 %}
9464 ins_short_branch(1);
9465 ins_avoid_back_to_back(1);
9466 ins_pipe(cbcond_reg_reg);
9467 %}
9468
9469 instruct cmpI_imm_branch_short(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{
9470 match(If cmp (CmpI op1 op2));
9471 predicate(UseCBCond);
9472 effect(USE labl, KILL icc);
9473
9474 size(4);
9475 ins_cost(BRANCH_COST);
9476 format %{ "CWB$cmp $op1,$op2,$labl\t! int" %}
9477 ins_encode %{
9478 Label* L = $labl$$label;
9479 assert(__ use_cbcond(*L), "back to back cbcond");
9480 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$constant, *L);
9481 %}
9482 ins_short_branch(1);
9483 ins_avoid_back_to_back(1);
9484 ins_pipe(cbcond_reg_imm);
9485 %}
9486
9487 instruct cmpU_reg_branch_short(cmpOpU cmp, iRegI op1, iRegI op2, label labl, flagsRegU icc) %{
9488 match(If cmp (CmpU op1 op2));
9489 predicate(UseCBCond);
9490 effect(USE labl, KILL icc);
9491
9492 size(4);
9493 ins_cost(BRANCH_COST);
9494 format %{ "CWB$cmp $op1,$op2,$labl\t! unsigned" %}
9495 ins_encode %{
9496 Label* L = $labl$$label;
9497 assert(__ use_cbcond(*L), "back to back cbcond");
9498 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L);
9499 %}
9500 ins_short_branch(1);
9501 ins_avoid_back_to_back(1);
9502 ins_pipe(cbcond_reg_reg);
9503 %}
9504
9505 instruct cmpU_imm_branch_short(cmpOpU cmp, iRegI op1, immI5 op2, label labl, flagsRegU icc) %{
9506 match(If cmp (CmpU op1 op2));
9507 predicate(UseCBCond);
9508 effect(USE labl, KILL icc);
9509
9510 size(4);
9511 ins_cost(BRANCH_COST);
9512 format %{ "CWB$cmp $op1,$op2,$labl\t! unsigned" %}
9513 ins_encode %{
9514 Label* L = $labl$$label;
9515 assert(__ use_cbcond(*L), "back to back cbcond");
9516 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$constant, *L);
9517 %}
9518 ins_short_branch(1);
9519 ins_avoid_back_to_back(1);
9520 ins_pipe(cbcond_reg_imm);
9521 %}
9522
9523 instruct cmpL_reg_branch_short(cmpOp cmp, iRegL op1, iRegL op2, label labl, flagsRegL xcc) %{
9524 match(If cmp (CmpL op1 op2));
9525 predicate(UseCBCond);
9526 effect(USE labl, KILL xcc);
9527
9528 size(4);
9529 ins_cost(BRANCH_COST);
9530 format %{ "CXB$cmp $op1,$op2,$labl\t! long" %}
9531 ins_encode %{
9532 Label* L = $labl$$label;
9533 assert(__ use_cbcond(*L), "back to back cbcond");
9534 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::xcc, $op1$$Register, $op2$$Register, *L);
9535 %}
9536 ins_short_branch(1);
9537 ins_avoid_back_to_back(1);
9538 ins_pipe(cbcond_reg_reg);
9539 %}
9540
9541 instruct cmpL_imm_branch_short(cmpOp cmp, iRegL op1, immL5 op2, label labl, flagsRegL xcc) %{
9542 match(If cmp (CmpL op1 op2));
9543 predicate(UseCBCond);
9544 effect(USE labl, KILL xcc);
9545
9546 size(4);
9547 ins_cost(BRANCH_COST);
9548 format %{ "CXB$cmp $op1,$op2,$labl\t! long" %}
9549 ins_encode %{
9550 Label* L = $labl$$label;
9551 assert(__ use_cbcond(*L), "back to back cbcond");
9552 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::xcc, $op1$$Register, $op2$$constant, *L);
9553 %}
9554 ins_short_branch(1);
9555 ins_avoid_back_to_back(1);
9556 ins_pipe(cbcond_reg_imm);
9557 %}
9558
9559 // Compare Pointers and branch
9560 instruct cmpP_reg_branch_short(cmpOpP cmp, iRegP op1, iRegP op2, label labl, flagsRegP pcc) %{
9561 match(If cmp (CmpP op1 op2));
9562 predicate(UseCBCond);
9563 effect(USE labl, KILL pcc);
9564
9565 size(4);
9566 ins_cost(BRANCH_COST);
9567 #ifdef _LP64
9568 format %{ "CXB$cmp $op1,$op2,$labl\t! ptr" %}
9569 #else
9570 format %{ "CWB$cmp $op1,$op2,$labl\t! ptr" %}
9571 #endif
9572 ins_encode %{
9573 Label* L = $labl$$label;
9574 assert(__ use_cbcond(*L), "back to back cbcond");
9575 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::ptr_cc, $op1$$Register, $op2$$Register, *L);
9576 %}
9577 ins_short_branch(1);
9578 ins_avoid_back_to_back(1);
9579 ins_pipe(cbcond_reg_reg);
9580 %}
9581
9582 instruct cmpP_null_branch_short(cmpOpP cmp, iRegP op1, immP0 null, label labl, flagsRegP pcc) %{
9583 match(If cmp (CmpP op1 null));
9584 predicate(UseCBCond);
9585 effect(USE labl, KILL pcc);
9586
9587 size(4);
9588 ins_cost(BRANCH_COST);
9589 #ifdef _LP64
9590 format %{ "CXB$cmp $op1,0,$labl\t! ptr" %}
9591 #else
9592 format %{ "CWB$cmp $op1,0,$labl\t! ptr" %}
9593 #endif
9594 ins_encode %{
9595 Label* L = $labl$$label;
9596 assert(__ use_cbcond(*L), "back to back cbcond");
9597 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::ptr_cc, $op1$$Register, G0, *L);
9598 %}
9599 ins_short_branch(1);
9600 ins_avoid_back_to_back(1);
9601 ins_pipe(cbcond_reg_reg);
9602 %}
9603
9604 instruct cmpN_reg_branch_short(cmpOp cmp, iRegN op1, iRegN op2, label labl, flagsReg icc) %{
9605 match(If cmp (CmpN op1 op2));
9606 predicate(UseCBCond);
9607 effect(USE labl, KILL icc);
9608
9609 size(4);
9610 ins_cost(BRANCH_COST);
9611 format %{ "CWB$cmp $op1,op2,$labl\t! compressed ptr" %}
9612 ins_encode %{
9613 Label* L = $labl$$label;
9614 assert(__ use_cbcond(*L), "back to back cbcond");
9615 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L);
9616 %}
9617 ins_short_branch(1);
9618 ins_avoid_back_to_back(1);
9619 ins_pipe(cbcond_reg_reg);
9620 %}
9621
9622 instruct cmpN_null_branch_short(cmpOp cmp, iRegN op1, immN0 null, label labl, flagsReg icc) %{
9623 match(If cmp (CmpN op1 null));
9624 predicate(UseCBCond);
9625 effect(USE labl, KILL icc);
9626
9627 size(4);
9628 ins_cost(BRANCH_COST);
9629 format %{ "CWB$cmp $op1,0,$labl\t! compressed ptr" %}
9630 ins_encode %{
9631 Label* L = $labl$$label;
9632 assert(__ use_cbcond(*L), "back to back cbcond");
9633 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, G0, *L);
9634 %}
9635 ins_short_branch(1);
9636 ins_avoid_back_to_back(1);
9637 ins_pipe(cbcond_reg_reg);
9638 %}
9639
9640 // Loop back branch
9641 instruct cmpI_reg_branchLoopEnd_short(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{
9642 match(CountedLoopEnd cmp (CmpI op1 op2));
9643 predicate(UseCBCond);
9644 effect(USE labl, KILL icc);
9645
9646 size(4);
9647 ins_cost(BRANCH_COST);
9648 format %{ "CWB$cmp $op1,$op2,$labl\t! Loop end" %}
9649 ins_encode %{
9650 Label* L = $labl$$label;
9651 assert(__ use_cbcond(*L), "back to back cbcond");
9652 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L);
9653 %}
9654 ins_short_branch(1);
9655 ins_avoid_back_to_back(1);
9656 ins_pipe(cbcond_reg_reg);
9657 %}
9658
9659 instruct cmpI_imm_branchLoopEnd_short(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{
9660 match(CountedLoopEnd cmp (CmpI op1 op2));
9661 predicate(UseCBCond);
9662 effect(USE labl, KILL icc);
9663
9664 size(4);
9665 ins_cost(BRANCH_COST);
9666 format %{ "CWB$cmp $op1,$op2,$labl\t! Loop end" %}
9667 ins_encode %{
9668 Label* L = $labl$$label;
9669 assert(__ use_cbcond(*L), "back to back cbcond");
9670 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$constant, *L);
9671 %}
9672 ins_short_branch(1);
9673 ins_avoid_back_to_back(1);
9674 ins_pipe(cbcond_reg_imm);
9675 %}
9676
9677 // Branch-on-register tests all 64 bits. We assume that values
9678 // in 64-bit registers always remains zero or sign extended
9679 // unless our code munges the high bits. Interrupts can chop
9680 // the high order bits to zero or sign at any time.
9681 instruct branchCon_regI(cmpOp_reg cmp, iRegI op1, immI0 zero, label labl) %{
9682 match(If cmp (CmpI op1 zero));
9683 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf));
9684 effect(USE labl);
9685
9686 size(8);
9687 ins_cost(BRANCH_COST);
9688 format %{ "BR$cmp $op1,$labl" %}
9689 ins_encode( enc_bpr( labl, cmp, op1 ) );
9690 ins_pipe(br_reg);
9691 %}
9692
9693 instruct branchCon_regP(cmpOp_reg cmp, iRegP op1, immP0 null, label labl) %{
9694 match(If cmp (CmpP op1 null));
9695 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf));
9696 effect(USE labl);
9697
9698 size(8);
9699 ins_cost(BRANCH_COST);
9700 format %{ "BR$cmp $op1,$labl" %}
9701 ins_encode( enc_bpr( labl, cmp, op1 ) );
9702 ins_pipe(br_reg);
9703 %}
9704
9705 instruct branchCon_regL(cmpOp_reg cmp, iRegL op1, immL0 zero, label labl) %{
9706 match(If cmp (CmpL op1 zero));
9707 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf));
9708 effect(USE labl);
9709
9710 size(8);
9711 ins_cost(BRANCH_COST);
9712 format %{ "BR$cmp $op1,$labl" %}
9713 ins_encode( enc_bpr( labl, cmp, op1 ) );
9714 ins_pipe(br_reg);
9715 %}
9716
9717
9718 // ============================================================================
9719 // Long Compare
9720 //
9721 // Currently we hold longs in 2 registers. Comparing such values efficiently
9722 // is tricky. The flavor of compare used depends on whether we are testing
9723 // for LT, LE, or EQ. For a simple LT test we can check just the sign bit.
9724 // The GE test is the negated LT test. The LE test can be had by commuting
9725 // the operands (yielding a GE test) and then negating; negate again for the
9726 // GT test. The EQ test is done by ORcc'ing the high and low halves, and the
9727 // NE test is negated from that.
9728
9729 // Due to a shortcoming in the ADLC, it mixes up expressions like:
9730 // (foo (CmpI (CmpL X Y) 0)) and (bar (CmpI (CmpL X 0L) 0)). Note the
9731 // difference between 'Y' and '0L'. The tree-matches for the CmpI sections
9732 // are collapsed internally in the ADLC's dfa-gen code. The match for
9733 // (CmpI (CmpL X Y) 0) is silently replaced with (CmpI (CmpL X 0L) 0) and the
9734 // foo match ends up with the wrong leaf. One fix is to not match both
9735 // reg-reg and reg-zero forms of long-compare. This is unfortunate because
9736 // both forms beat the trinary form of long-compare and both are very useful
9737 // on Intel which has so few registers.
9738
9739 instruct branchCon_long(cmpOp cmp, flagsRegL xcc, label labl) %{
9740 match(If cmp xcc);
9741 effect(USE labl);
9742
9743 size(8);
9744 ins_cost(BRANCH_COST);
9745 format %{ "BP$cmp $xcc,$labl" %}
9746 ins_encode %{
9747 Label* L = $labl$$label;
9748 Assembler::Predict predict_taken =
9749 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9750
9751 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L);
9752 __ delayed()->nop();
9753 %}
9754 ins_pipe(br_cc);
9755 %}
9756
9757 // Manifest a CmpL3 result in an integer register. Very painful.
9758 // This is the test to avoid.
9759 instruct cmpL3_reg_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg ccr ) %{
9760 match(Set dst (CmpL3 src1 src2) );
9761 effect( KILL ccr );
9762 ins_cost(6*DEFAULT_COST);
9763 size(24);
9764 format %{ "CMP $src1,$src2\t\t! long\n"
9765 "\tBLT,a,pn done\n"
9766 "\tMOV -1,$dst\t! delay slot\n"
9767 "\tBGT,a,pn done\n"
9768 "\tMOV 1,$dst\t! delay slot\n"
9769 "\tCLR $dst\n"
9770 "done:" %}
9771 ins_encode( cmpl_flag(src1,src2,dst) );
9772 ins_pipe(cmpL_reg);
9773 %}
9774
9775 // Conditional move
9776 instruct cmovLL_reg(cmpOp cmp, flagsRegL xcc, iRegL dst, iRegL src) %{
9777 match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src)));
9778 ins_cost(150);
9779 format %{ "MOV$cmp $xcc,$src,$dst\t! long" %}
9780 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
9781 ins_pipe(ialu_reg);
9782 %}
9783
9784 instruct cmovLL_imm(cmpOp cmp, flagsRegL xcc, iRegL dst, immL0 src) %{
9785 match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src)));
9786 ins_cost(140);
9787 format %{ "MOV$cmp $xcc,$src,$dst\t! long" %}
9788 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) );
9789 ins_pipe(ialu_imm);
9790 %}
9791
9792 instruct cmovIL_reg(cmpOp cmp, flagsRegL xcc, iRegI dst, iRegI src) %{
9793 match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src)));
9794 ins_cost(150);
9795 format %{ "MOV$cmp $xcc,$src,$dst" %}
9796 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
9797 ins_pipe(ialu_reg);
9798 %}
9799
9800 instruct cmovIL_imm(cmpOp cmp, flagsRegL xcc, iRegI dst, immI11 src) %{
9801 match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src)));
9802 ins_cost(140);
9803 format %{ "MOV$cmp $xcc,$src,$dst" %}
9804 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) );
9805 ins_pipe(ialu_imm);
9806 %}
9807
9808 instruct cmovNL_reg(cmpOp cmp, flagsRegL xcc, iRegN dst, iRegN src) %{
9809 match(Set dst (CMoveN (Binary cmp xcc) (Binary dst src)));
9810 ins_cost(150);
9811 format %{ "MOV$cmp $xcc,$src,$dst" %}
9812 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
9813 ins_pipe(ialu_reg);
9814 %}
9815
9816 instruct cmovPL_reg(cmpOp cmp, flagsRegL xcc, iRegP dst, iRegP src) %{
9817 match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src)));
9818 ins_cost(150);
9819 format %{ "MOV$cmp $xcc,$src,$dst" %}
9820 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
9821 ins_pipe(ialu_reg);
9822 %}
9823
9824 instruct cmovPL_imm(cmpOp cmp, flagsRegL xcc, iRegP dst, immP0 src) %{
9825 match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src)));
9826 ins_cost(140);
9827 format %{ "MOV$cmp $xcc,$src,$dst" %}
9828 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) );
9829 ins_pipe(ialu_imm);
9830 %}
9831
9832 instruct cmovFL_reg(cmpOp cmp, flagsRegL xcc, regF dst, regF src) %{
9833 match(Set dst (CMoveF (Binary cmp xcc) (Binary dst src)));
9834 ins_cost(150);
9835 opcode(0x101);
9836 format %{ "FMOVS$cmp $xcc,$src,$dst" %}
9837 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::xcc)) );
9838 ins_pipe(int_conditional_float_move);
9839 %}
9840
9841 instruct cmovDL_reg(cmpOp cmp, flagsRegL xcc, regD dst, regD src) %{
9842 match(Set dst (CMoveD (Binary cmp xcc) (Binary dst src)));
9843 ins_cost(150);
9844 opcode(0x102);
9845 format %{ "FMOVD$cmp $xcc,$src,$dst" %}
9846 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::xcc)) );
9847 ins_pipe(int_conditional_float_move);
9848 %}
9849
9850 // ============================================================================
9851 // Safepoint Instruction
9852 instruct safePoint_poll(iRegP poll) %{
9853 match(SafePoint poll);
9854 effect(USE poll);
9855
9856 size(4);
9857 #ifdef _LP64
9858 format %{ "LDX [$poll],R_G0\t! Safepoint: poll for GC" %}
9859 #else
9860 format %{ "LDUW [$poll],R_G0\t! Safepoint: poll for GC" %}
9861 #endif
9862 ins_encode %{
9863 __ relocate(relocInfo::poll_type);
9864 __ ld_ptr($poll$$Register, 0, G0);
9865 %}
9866 ins_pipe(loadPollP);
9867 %}
9868
9869 // ============================================================================
9870 // Call Instructions
9871 // Call Java Static Instruction
9872 instruct CallStaticJavaDirect( method meth ) %{
9873 match(CallStaticJava);
9874 predicate(! ((CallStaticJavaNode*)n)->is_method_handle_invoke());
9875 effect(USE meth);
9876
9877 size(8);
9878 ins_cost(CALL_COST);
9879 format %{ "CALL,static ; NOP ==> " %}
9880 ins_encode( Java_Static_Call( meth ), call_epilog );
9881 ins_pipe(simple_call);
9882 %}
9883
9884 // Call Java Static Instruction (method handle version)
9885 instruct CallStaticJavaHandle(method meth, l7RegP l7_mh_SP_save) %{
9886 match(CallStaticJava);
9887 predicate(((CallStaticJavaNode*)n)->is_method_handle_invoke());
9888 effect(USE meth, KILL l7_mh_SP_save);
9889
9890 size(16);
9891 ins_cost(CALL_COST);
9892 format %{ "CALL,static/MethodHandle" %}
9893 ins_encode(preserve_SP, Java_Static_Call(meth), restore_SP, call_epilog);
9894 ins_pipe(simple_call);
9895 %}
9896
9897 // Call Java Dynamic Instruction
9898 instruct CallDynamicJavaDirect( method meth ) %{
9899 match(CallDynamicJava);
9900 effect(USE meth);
9901
9902 ins_cost(CALL_COST);
9903 format %{ "SET (empty),R_G5\n\t"
9904 "CALL,dynamic ; NOP ==> " %}
9905 ins_encode( Java_Dynamic_Call( meth ), call_epilog );
9906 ins_pipe(call);
9907 %}
9908
9909 // Call Runtime Instruction
9910 instruct CallRuntimeDirect(method meth, l7RegP l7) %{
9911 match(CallRuntime);
9912 effect(USE meth, KILL l7);
9913 ins_cost(CALL_COST);
9914 format %{ "CALL,runtime" %}
9915 ins_encode( Java_To_Runtime( meth ),
9916 call_epilog, adjust_long_from_native_call );
9917 ins_pipe(simple_call);
9918 %}
9919
9920 // Call runtime without safepoint - same as CallRuntime
9921 instruct CallLeafDirect(method meth, l7RegP l7) %{
9922 match(CallLeaf);
9923 effect(USE meth, KILL l7);
9924 ins_cost(CALL_COST);
9925 format %{ "CALL,runtime leaf" %}
9926 ins_encode( Java_To_Runtime( meth ),
9927 call_epilog,
9928 adjust_long_from_native_call );
9929 ins_pipe(simple_call);
9930 %}
9931
9932 // Call runtime without safepoint - same as CallLeaf
9933 instruct CallLeafNoFPDirect(method meth, l7RegP l7) %{
9934 match(CallLeafNoFP);
9935 effect(USE meth, KILL l7);
9936 ins_cost(CALL_COST);
9937 format %{ "CALL,runtime leaf nofp" %}
9938 ins_encode( Java_To_Runtime( meth ),
9939 call_epilog,
9940 adjust_long_from_native_call );
9941 ins_pipe(simple_call);
9942 %}
9943
9944 // Tail Call; Jump from runtime stub to Java code.
9945 // Also known as an 'interprocedural jump'.
9946 // Target of jump will eventually return to caller.
9947 // TailJump below removes the return address.
9948 instruct TailCalljmpInd(g3RegP jump_target, inline_cache_regP method_oop) %{
9949 match(TailCall jump_target method_oop );
9950
9951 ins_cost(CALL_COST);
9952 format %{ "Jmp $jump_target ; NOP \t! $method_oop holds method oop" %}
9953 ins_encode(form_jmpl(jump_target));
9954 ins_pipe(tail_call);
9955 %}
9956
9957
9958 // Return Instruction
9959 instruct Ret() %{
9960 match(Return);
9961
9962 // The epilogue node did the ret already.
9963 size(0);
9964 format %{ "! return" %}
9965 ins_encode();
9966 ins_pipe(empty);
9967 %}
9968
9969
9970 // Tail Jump; remove the return address; jump to target.
9971 // TailCall above leaves the return address around.
9972 // TailJump is used in only one place, the rethrow_Java stub (fancy_jump=2).
9973 // ex_oop (Exception Oop) is needed in %o0 at the jump. As there would be a
9974 // "restore" before this instruction (in Epilogue), we need to materialize it
9975 // in %i0.
9976 instruct tailjmpInd(g1RegP jump_target, i0RegP ex_oop) %{
9977 match( TailJump jump_target ex_oop );
9978 ins_cost(CALL_COST);
9979 format %{ "! discard R_O7\n\t"
9980 "Jmp $jump_target ; ADD O7,8,O1 \t! $ex_oop holds exc. oop" %}
9981 ins_encode(form_jmpl_set_exception_pc(jump_target));
9982 // opcode(Assembler::jmpl_op3, Assembler::arith_op);
9983 // The hack duplicates the exception oop into G3, so that CreateEx can use it there.
9984 // ins_encode( form3_rs1_simm13_rd( jump_target, 0x00, R_G0 ), move_return_pc_to_o1() );
9985 ins_pipe(tail_call);
9986 %}
9987
9988 // Create exception oop: created by stack-crawling runtime code.
9989 // Created exception is now available to this handler, and is setup
9990 // just prior to jumping to this handler. No code emitted.
9991 instruct CreateException( o0RegP ex_oop )
9992 %{
9993 match(Set ex_oop (CreateEx));
9994 ins_cost(0);
9995
9996 size(0);
9997 // use the following format syntax
9998 format %{ "! exception oop is in R_O0; no code emitted" %}
9999 ins_encode();
10000 ins_pipe(empty);
10001 %}
10002
10003
10004 // Rethrow exception:
10005 // The exception oop will come in the first argument position.
10006 // Then JUMP (not call) to the rethrow stub code.
10007 instruct RethrowException()
10008 %{
10009 match(Rethrow);
10010 ins_cost(CALL_COST);
10011
10012 // use the following format syntax
10013 format %{ "Jmp rethrow_stub" %}
10014 ins_encode(enc_rethrow);
10015 ins_pipe(tail_call);
10016 %}
10017
10018
10019 // Die now
10020 instruct ShouldNotReachHere( )
10021 %{
10022 match(Halt);
10023 ins_cost(CALL_COST);
10024
10025 size(4);
10026 // Use the following format syntax
10027 format %{ "ILLTRAP ; ShouldNotReachHere" %}
10028 ins_encode( form2_illtrap() );
10029 ins_pipe(tail_call);
10030 %}
10031
10032 // ============================================================================
10033 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass
10034 // array for an instance of the superklass. Set a hidden internal cache on a
10035 // hit (cache is checked with exposed code in gen_subtype_check()). Return
10036 // not zero for a miss or zero for a hit. The encoding ALSO sets flags.
10037 instruct partialSubtypeCheck( o0RegP index, o1RegP sub, o2RegP super, flagsRegP pcc, o7RegP o7 ) %{
10038 match(Set index (PartialSubtypeCheck sub super));
10039 effect( KILL pcc, KILL o7 );
10040 ins_cost(DEFAULT_COST*10);
10041 format %{ "CALL PartialSubtypeCheck\n\tNOP" %}
10042 ins_encode( enc_PartialSubtypeCheck() );
10043 ins_pipe(partial_subtype_check_pipe);
10044 %}
10045
10046 instruct partialSubtypeCheck_vs_zero( flagsRegP pcc, o1RegP sub, o2RegP super, immP0 zero, o0RegP idx, o7RegP o7 ) %{
10047 match(Set pcc (CmpP (PartialSubtypeCheck sub super) zero));
10048 effect( KILL idx, KILL o7 );
10049 ins_cost(DEFAULT_COST*10);
10050 format %{ "CALL PartialSubtypeCheck\n\tNOP\t# (sets condition codes)" %}
10051 ins_encode( enc_PartialSubtypeCheck() );
10052 ins_pipe(partial_subtype_check_pipe);
10053 %}
10054
10055
10056 // ============================================================================
10057 // inlined locking and unlocking
10058
10059 instruct cmpFastLock(flagsRegP pcc, iRegP object, o1RegP box, iRegP scratch2, o7RegP scratch ) %{
10060 match(Set pcc (FastLock object box));
10061
10062 effect(TEMP scratch2, USE_KILL box, KILL scratch);
10063 ins_cost(100);
10064
10065 format %{ "FASTLOCK $object,$box\t! kills $box,$scratch,$scratch2" %}
10066 ins_encode( Fast_Lock(object, box, scratch, scratch2) );
10067 ins_pipe(long_memory_op);
10068 %}
10069
10070
10071 instruct cmpFastUnlock(flagsRegP pcc, iRegP object, o1RegP box, iRegP scratch2, o7RegP scratch ) %{
10072 match(Set pcc (FastUnlock object box));
10073 effect(TEMP scratch2, USE_KILL box, KILL scratch);
10074 ins_cost(100);
10075
10076 format %{ "FASTUNLOCK $object,$box\t! kills $box,$scratch,$scratch2" %}
10077 ins_encode( Fast_Unlock(object, box, scratch, scratch2) );
10078 ins_pipe(long_memory_op);
10079 %}
10080
10081 // The encodings are generic.
10082 instruct clear_array(iRegX cnt, iRegP base, iRegX temp, Universe dummy, flagsReg ccr) %{
10083 predicate(!use_block_zeroing(n->in(2)) );
10084 match(Set dummy (ClearArray cnt base));
10085 effect(TEMP temp, KILL ccr);
10086 ins_cost(300);
10087 format %{ "MOV $cnt,$temp\n"
10088 "loop: SUBcc $temp,8,$temp\t! Count down a dword of bytes\n"
10089 " BRge loop\t\t! Clearing loop\n"
10090 " STX G0,[$base+$temp]\t! delay slot" %}
10091
10092 ins_encode %{
10093 // Compiler ensures base is doubleword aligned and cnt is count of doublewords
10094 Register nof_bytes_arg = $cnt$$Register;
10095 Register nof_bytes_tmp = $temp$$Register;
10096 Register base_pointer_arg = $base$$Register;
10097
10098 Label loop;
10099 __ mov(nof_bytes_arg, nof_bytes_tmp);
10100
10101 // Loop and clear, walking backwards through the array.
10102 // nof_bytes_tmp (if >0) is always the number of bytes to zero
10103 __ bind(loop);
10104 __ deccc(nof_bytes_tmp, 8);
10105 __ br(Assembler::greaterEqual, true, Assembler::pt, loop);
10106 __ delayed()-> stx(G0, base_pointer_arg, nof_bytes_tmp);
10107 // %%%% this mini-loop must not cross a cache boundary!
10108 %}
10109 ins_pipe(long_memory_op);
10110 %}
10111
10112 instruct clear_array_bis(g1RegX cnt, o0RegP base, Universe dummy, flagsReg ccr) %{
10113 predicate(use_block_zeroing(n->in(2)));
10114 match(Set dummy (ClearArray cnt base));
10115 effect(USE_KILL cnt, USE_KILL base, KILL ccr);
10116 ins_cost(300);
10117 format %{ "CLEAR [$base, $cnt]\t! ClearArray" %}
10118
10119 ins_encode %{
10120
10121 assert(MinObjAlignmentInBytes >= BytesPerLong, "need alternate implementation");
10122 Register to = $base$$Register;
10123 Register count = $cnt$$Register;
10124
10125 Label Ldone;
10126 __ nop(); // Separate short branches
10127 // Use BIS for zeroing (temp is not used).
10128 __ bis_zeroing(to, count, G0, Ldone);
10129 __ bind(Ldone);
10130
10131 %}
10132 ins_pipe(long_memory_op);
10133 %}
10134
10135 instruct clear_array_bis_2(g1RegX cnt, o0RegP base, iRegX tmp, Universe dummy, flagsReg ccr) %{
10136 predicate(use_block_zeroing(n->in(2)) && !Assembler::is_simm13((int)BlockZeroingLowLimit));
10137 match(Set dummy (ClearArray cnt base));
10138 effect(TEMP tmp, USE_KILL cnt, USE_KILL base, KILL ccr);
10139 ins_cost(300);
10140 format %{ "CLEAR [$base, $cnt]\t! ClearArray" %}
10141
10142 ins_encode %{
10143
10144 assert(MinObjAlignmentInBytes >= BytesPerLong, "need alternate implementation");
10145 Register to = $base$$Register;
10146 Register count = $cnt$$Register;
10147 Register temp = $tmp$$Register;
10148
10149 Label Ldone;
10150 __ nop(); // Separate short branches
10151 // Use BIS for zeroing
10152 __ bis_zeroing(to, count, temp, Ldone);
10153 __ bind(Ldone);
10154
10155 %}
10156 ins_pipe(long_memory_op);
10157 %}
10158
10159 instruct string_compare(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result,
10160 o7RegI tmp, flagsReg ccr) %{
10161 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10162 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL ccr, KILL tmp);
10163 ins_cost(300);
10164 format %{ "String Compare $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp" %}
10165 ins_encode( enc_String_Compare(str1, str2, cnt1, cnt2, result) );
10166 ins_pipe(long_memory_op);
10167 %}
10168
10169 instruct string_equals(o0RegP str1, o1RegP str2, g3RegI cnt, notemp_iRegI result,
10170 o7RegI tmp, flagsReg ccr) %{
10171 match(Set result (StrEquals (Binary str1 str2) cnt));
10172 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp, KILL ccr);
10173 ins_cost(300);
10174 format %{ "String Equals $str1,$str2,$cnt -> $result // KILL $tmp" %}
10175 ins_encode( enc_String_Equals(str1, str2, cnt, result) );
10176 ins_pipe(long_memory_op);
10177 %}
10178
10179 instruct array_equals(o0RegP ary1, o1RegP ary2, g3RegI tmp1, notemp_iRegI result,
10180 o7RegI tmp2, flagsReg ccr) %{
10181 match(Set result (AryEq ary1 ary2));
10182 effect(USE_KILL ary1, USE_KILL ary2, KILL tmp1, KILL tmp2, KILL ccr);
10183 ins_cost(300);
10184 format %{ "Array Equals $ary1,$ary2 -> $result // KILL $tmp1,$tmp2" %}
10185 ins_encode( enc_Array_Equals(ary1, ary2, tmp1, result));
10186 ins_pipe(long_memory_op);
10187 %}
10188
10189
10190 //---------- Zeros Count Instructions ------------------------------------------
10191
10192 instruct countLeadingZerosI(iRegIsafe dst, iRegI src, iRegI tmp, flagsReg cr) %{
10193 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported
10194 match(Set dst (CountLeadingZerosI src));
10195 effect(TEMP dst, TEMP tmp, KILL cr);
10196
10197 // x |= (x >> 1);
10198 // x |= (x >> 2);
10199 // x |= (x >> 4);
10200 // x |= (x >> 8);
10201 // x |= (x >> 16);
10202 // return (WORDBITS - popc(x));
10203 format %{ "SRL $src,1,$tmp\t! count leading zeros (int)\n\t"
10204 "SRL $src,0,$dst\t! 32-bit zero extend\n\t"
10205 "OR $dst,$tmp,$dst\n\t"
10206 "SRL $dst,2,$tmp\n\t"
10207 "OR $dst,$tmp,$dst\n\t"
10208 "SRL $dst,4,$tmp\n\t"
10209 "OR $dst,$tmp,$dst\n\t"
10210 "SRL $dst,8,$tmp\n\t"
10211 "OR $dst,$tmp,$dst\n\t"
10212 "SRL $dst,16,$tmp\n\t"
10213 "OR $dst,$tmp,$dst\n\t"
10214 "POPC $dst,$dst\n\t"
10215 "MOV 32,$tmp\n\t"
10216 "SUB $tmp,$dst,$dst" %}
10217 ins_encode %{
10218 Register Rdst = $dst$$Register;
10219 Register Rsrc = $src$$Register;
10220 Register Rtmp = $tmp$$Register;
10221 __ srl(Rsrc, 1, Rtmp);
10222 __ srl(Rsrc, 0, Rdst);
10223 __ or3(Rdst, Rtmp, Rdst);
10224 __ srl(Rdst, 2, Rtmp);
10225 __ or3(Rdst, Rtmp, Rdst);
10226 __ srl(Rdst, 4, Rtmp);
10227 __ or3(Rdst, Rtmp, Rdst);
10228 __ srl(Rdst, 8, Rtmp);
10229 __ or3(Rdst, Rtmp, Rdst);
10230 __ srl(Rdst, 16, Rtmp);
10231 __ or3(Rdst, Rtmp, Rdst);
10232 __ popc(Rdst, Rdst);
10233 __ mov(BitsPerInt, Rtmp);
10234 __ sub(Rtmp, Rdst, Rdst);
10235 %}
10236 ins_pipe(ialu_reg);
10237 %}
10238
10239 instruct countLeadingZerosL(iRegIsafe dst, iRegL src, iRegL tmp, flagsReg cr) %{
10240 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported
10241 match(Set dst (CountLeadingZerosL src));
10242 effect(TEMP dst, TEMP tmp, KILL cr);
10243
10244 // x |= (x >> 1);
10245 // x |= (x >> 2);
10246 // x |= (x >> 4);
10247 // x |= (x >> 8);
10248 // x |= (x >> 16);
10249 // x |= (x >> 32);
10250 // return (WORDBITS - popc(x));
10251 format %{ "SRLX $src,1,$tmp\t! count leading zeros (long)\n\t"
10252 "OR $src,$tmp,$dst\n\t"
10253 "SRLX $dst,2,$tmp\n\t"
10254 "OR $dst,$tmp,$dst\n\t"
10255 "SRLX $dst,4,$tmp\n\t"
10256 "OR $dst,$tmp,$dst\n\t"
10257 "SRLX $dst,8,$tmp\n\t"
10258 "OR $dst,$tmp,$dst\n\t"
10259 "SRLX $dst,16,$tmp\n\t"
10260 "OR $dst,$tmp,$dst\n\t"
10261 "SRLX $dst,32,$tmp\n\t"
10262 "OR $dst,$tmp,$dst\n\t"
10263 "POPC $dst,$dst\n\t"
10264 "MOV 64,$tmp\n\t"
10265 "SUB $tmp,$dst,$dst" %}
10266 ins_encode %{
10267 Register Rdst = $dst$$Register;
10268 Register Rsrc = $src$$Register;
10269 Register Rtmp = $tmp$$Register;
10270 __ srlx(Rsrc, 1, Rtmp);
10271 __ or3( Rsrc, Rtmp, Rdst);
10272 __ srlx(Rdst, 2, Rtmp);
10273 __ or3( Rdst, Rtmp, Rdst);
10274 __ srlx(Rdst, 4, Rtmp);
10275 __ or3( Rdst, Rtmp, Rdst);
10276 __ srlx(Rdst, 8, Rtmp);
10277 __ or3( Rdst, Rtmp, Rdst);
10278 __ srlx(Rdst, 16, Rtmp);
10279 __ or3( Rdst, Rtmp, Rdst);
10280 __ srlx(Rdst, 32, Rtmp);
10281 __ or3( Rdst, Rtmp, Rdst);
10282 __ popc(Rdst, Rdst);
10283 __ mov(BitsPerLong, Rtmp);
10284 __ sub(Rtmp, Rdst, Rdst);
10285 %}
10286 ins_pipe(ialu_reg);
10287 %}
10288
10289 instruct countTrailingZerosI(iRegIsafe dst, iRegI src, flagsReg cr) %{
10290 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported
10291 match(Set dst (CountTrailingZerosI src));
10292 effect(TEMP dst, KILL cr);
10293
10294 // return popc(~x & (x - 1));
10295 format %{ "SUB $src,1,$dst\t! count trailing zeros (int)\n\t"
10296 "ANDN $dst,$src,$dst\n\t"
10297 "SRL $dst,R_G0,$dst\n\t"
10298 "POPC $dst,$dst" %}
10299 ins_encode %{
10300 Register Rdst = $dst$$Register;
10301 Register Rsrc = $src$$Register;
10302 __ sub(Rsrc, 1, Rdst);
10303 __ andn(Rdst, Rsrc, Rdst);
10304 __ srl(Rdst, G0, Rdst);
10305 __ popc(Rdst, Rdst);
10306 %}
10307 ins_pipe(ialu_reg);
10308 %}
10309
10310 instruct countTrailingZerosL(iRegIsafe dst, iRegL src, flagsReg cr) %{
10311 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported
10312 match(Set dst (CountTrailingZerosL src));
10313 effect(TEMP dst, KILL cr);
10314
10315 // return popc(~x & (x - 1));
10316 format %{ "SUB $src,1,$dst\t! count trailing zeros (long)\n\t"
10317 "ANDN $dst,$src,$dst\n\t"
10318 "POPC $dst,$dst" %}
10319 ins_encode %{
10320 Register Rdst = $dst$$Register;
10321 Register Rsrc = $src$$Register;
10322 __ sub(Rsrc, 1, Rdst);
10323 __ andn(Rdst, Rsrc, Rdst);
10324 __ popc(Rdst, Rdst);
10325 %}
10326 ins_pipe(ialu_reg);
10327 %}
10328
10329
10330 //---------- Population Count Instructions -------------------------------------
10331
10332 instruct popCountI(iRegIsafe dst, iRegI src) %{
10333 predicate(UsePopCountInstruction);
10334 match(Set dst (PopCountI src));
10335
10336 format %{ "SRL $src, G0, $dst\t! clear upper word for 64 bit POPC\n\t"
10337 "POPC $dst, $dst" %}
10338 ins_encode %{
10339 __ srl($src$$Register, G0, $dst$$Register);
10340 __ popc($dst$$Register, $dst$$Register);
10341 %}
10342 ins_pipe(ialu_reg);
10343 %}
10344
10345 // Note: Long.bitCount(long) returns an int.
10346 instruct popCountL(iRegIsafe dst, iRegL src) %{
10347 predicate(UsePopCountInstruction);
10348 match(Set dst (PopCountL src));
10349
10350 format %{ "POPC $src, $dst" %}
10351 ins_encode %{
10352 __ popc($src$$Register, $dst$$Register);
10353 %}
10354 ins_pipe(ialu_reg);
10355 %}
10356
10357
10358 // ============================================================================
10359 //------------Bytes reverse--------------------------------------------------
10360
10361 instruct bytes_reverse_int(iRegI dst, stackSlotI src) %{
10362 match(Set dst (ReverseBytesI src));
10363
10364 // Op cost is artificially doubled to make sure that load or store
10365 // instructions are preferred over this one which requires a spill
10366 // onto a stack slot.
10367 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
10368 format %{ "LDUWA $src, $dst\t!asi=primary_little" %}
10369
10370 ins_encode %{
10371 __ set($src$$disp + STACK_BIAS, O7);
10372 __ lduwa($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10373 %}
10374 ins_pipe( iload_mem );
10375 %}
10376
10377 instruct bytes_reverse_long(iRegL dst, stackSlotL src) %{
10378 match(Set dst (ReverseBytesL src));
10379
10380 // Op cost is artificially doubled to make sure that load or store
10381 // instructions are preferred over this one which requires a spill
10382 // onto a stack slot.
10383 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
10384 format %{ "LDXA $src, $dst\t!asi=primary_little" %}
10385
10386 ins_encode %{
10387 __ set($src$$disp + STACK_BIAS, O7);
10388 __ ldxa($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10389 %}
10390 ins_pipe( iload_mem );
10391 %}
10392
10393 instruct bytes_reverse_unsigned_short(iRegI dst, stackSlotI src) %{
10394 match(Set dst (ReverseBytesUS src));
10395
10396 // Op cost is artificially doubled to make sure that load or store
10397 // instructions are preferred over this one which requires a spill
10398 // onto a stack slot.
10399 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
10400 format %{ "LDUHA $src, $dst\t!asi=primary_little\n\t" %}
10401
10402 ins_encode %{
10403 // the value was spilled as an int so bias the load
10404 __ set($src$$disp + STACK_BIAS + 2, O7);
10405 __ lduha($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10406 %}
10407 ins_pipe( iload_mem );
10408 %}
10409
10410 instruct bytes_reverse_short(iRegI dst, stackSlotI src) %{
10411 match(Set dst (ReverseBytesS src));
10412
10413 // Op cost is artificially doubled to make sure that load or store
10414 // instructions are preferred over this one which requires a spill
10415 // onto a stack slot.
10416 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
10417 format %{ "LDSHA $src, $dst\t!asi=primary_little\n\t" %}
10418
10419 ins_encode %{
10420 // the value was spilled as an int so bias the load
10421 __ set($src$$disp + STACK_BIAS + 2, O7);
10422 __ ldsha($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10423 %}
10424 ins_pipe( iload_mem );
10425 %}
10426
10427 // Load Integer reversed byte order
10428 instruct loadI_reversed(iRegI dst, indIndexMemory src) %{
10429 match(Set dst (ReverseBytesI (LoadI src)));
10430
10431 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
10432 size(4);
10433 format %{ "LDUWA $src, $dst\t!asi=primary_little" %}
10434
10435 ins_encode %{
10436 __ lduwa($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10437 %}
10438 ins_pipe(iload_mem);
10439 %}
10440
10441 // Load Long - aligned and reversed
10442 instruct loadL_reversed(iRegL dst, indIndexMemory src) %{
10443 match(Set dst (ReverseBytesL (LoadL src)));
10444
10445 ins_cost(MEMORY_REF_COST);
10446 size(4);
10447 format %{ "LDXA $src, $dst\t!asi=primary_little" %}
10448
10449 ins_encode %{
10450 __ ldxa($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10451 %}
10452 ins_pipe(iload_mem);
10453 %}
10454
10455 // Load unsigned short / char reversed byte order
10456 instruct loadUS_reversed(iRegI dst, indIndexMemory src) %{
10457 match(Set dst (ReverseBytesUS (LoadUS src)));
10458
10459 ins_cost(MEMORY_REF_COST);
10460 size(4);
10461 format %{ "LDUHA $src, $dst\t!asi=primary_little" %}
10462
10463 ins_encode %{
10464 __ lduha($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10465 %}
10466 ins_pipe(iload_mem);
10467 %}
10468
10469 // Load short reversed byte order
10470 instruct loadS_reversed(iRegI dst, indIndexMemory src) %{
10471 match(Set dst (ReverseBytesS (LoadS src)));
10472
10473 ins_cost(MEMORY_REF_COST);
10474 size(4);
10475 format %{ "LDSHA $src, $dst\t!asi=primary_little" %}
10476
10477 ins_encode %{
10478 __ ldsha($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10479 %}
10480 ins_pipe(iload_mem);
10481 %}
10482
10483 // Store Integer reversed byte order
10484 instruct storeI_reversed(indIndexMemory dst, iRegI src) %{
10485 match(Set dst (StoreI dst (ReverseBytesI src)));
10486
10487 ins_cost(MEMORY_REF_COST);
10488 size(4);
10489 format %{ "STWA $src, $dst\t!asi=primary_little" %}
10490
10491 ins_encode %{
10492 __ stwa($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE);
10493 %}
10494 ins_pipe(istore_mem_reg);
10495 %}
10496
10497 // Store Long reversed byte order
10498 instruct storeL_reversed(indIndexMemory dst, iRegL src) %{
10499 match(Set dst (StoreL dst (ReverseBytesL src)));
10500
10501 ins_cost(MEMORY_REF_COST);
10502 size(4);
10503 format %{ "STXA $src, $dst\t!asi=primary_little" %}
10504
10505 ins_encode %{
10506 __ stxa($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE);
10507 %}
10508 ins_pipe(istore_mem_reg);
10509 %}
10510
10511 // Store unsighed short/char reversed byte order
10512 instruct storeUS_reversed(indIndexMemory dst, iRegI src) %{
10513 match(Set dst (StoreC dst (ReverseBytesUS src)));
10514
10515 ins_cost(MEMORY_REF_COST);
10516 size(4);
10517 format %{ "STHA $src, $dst\t!asi=primary_little" %}
10518
10519 ins_encode %{
10520 __ stha($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE);
10521 %}
10522 ins_pipe(istore_mem_reg);
10523 %}
10524
10525 // Store short reversed byte order
10526 instruct storeS_reversed(indIndexMemory dst, iRegI src) %{
10527 match(Set dst (StoreC dst (ReverseBytesS src)));
10528
10529 ins_cost(MEMORY_REF_COST);
10530 size(4);
10531 format %{ "STHA $src, $dst\t!asi=primary_little" %}
10532
10533 ins_encode %{
10534 __ stha($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE);
10535 %}
10536 ins_pipe(istore_mem_reg);
10537 %}
10538
10539 // ====================VECTOR INSTRUCTIONS=====================================
10540
10541 // Load Aligned Packed values into a Double Register
10542 instruct loadV8(regD dst, memory mem) %{
10543 predicate(n->as_LoadVector()->memory_size() == 8);
10544 match(Set dst (LoadVector mem));
10545 ins_cost(MEMORY_REF_COST);
10546 size(4);
10547 format %{ "LDDF $mem,$dst\t! load vector (8 bytes)" %}
10548 ins_encode %{
10549 __ ldf(FloatRegisterImpl::D, $mem$$Address, as_DoubleFloatRegister($dst$$reg));
10550 %}
10551 ins_pipe(floadD_mem);
10552 %}
10553
10554 // Store Vector in Double register to memory
10555 instruct storeV8(memory mem, regD src) %{
10556 predicate(n->as_StoreVector()->memory_size() == 8);
10557 match(Set mem (StoreVector mem src));
10558 ins_cost(MEMORY_REF_COST);
10559 size(4);
10560 format %{ "STDF $src,$mem\t! store vector (8 bytes)" %}
10561 ins_encode %{
10562 __ stf(FloatRegisterImpl::D, as_DoubleFloatRegister($src$$reg), $mem$$Address);
10563 %}
10564 ins_pipe(fstoreD_mem_reg);
10565 %}
10566
10567 // Store Zero into vector in memory
10568 instruct storeV8B_zero(memory mem, immI0 zero) %{
10569 predicate(n->as_StoreVector()->memory_size() == 8);
10570 match(Set mem (StoreVector mem (ReplicateB zero)));
10571 ins_cost(MEMORY_REF_COST);
10572 size(4);
10573 format %{ "STX $zero,$mem\t! store zero vector (8 bytes)" %}
10574 ins_encode %{
10575 __ stx(G0, $mem$$Address);
10576 %}
10577 ins_pipe(fstoreD_mem_zero);
10578 %}
10579
10580 instruct storeV4S_zero(memory mem, immI0 zero) %{
10581 predicate(n->as_StoreVector()->memory_size() == 8);
10582 match(Set mem (StoreVector mem (ReplicateS zero)));
10583 ins_cost(MEMORY_REF_COST);
10584 size(4);
10585 format %{ "STX $zero,$mem\t! store zero vector (4 shorts)" %}
10586 ins_encode %{
10587 __ stx(G0, $mem$$Address);
10588 %}
10589 ins_pipe(fstoreD_mem_zero);
10590 %}
10591
10592 instruct storeV2I_zero(memory mem, immI0 zero) %{
10593 predicate(n->as_StoreVector()->memory_size() == 8);
10594 match(Set mem (StoreVector mem (ReplicateI zero)));
10595 ins_cost(MEMORY_REF_COST);
10596 size(4);
10597 format %{ "STX $zero,$mem\t! store zero vector (2 ints)" %}
10598 ins_encode %{
10599 __ stx(G0, $mem$$Address);
10600 %}
10601 ins_pipe(fstoreD_mem_zero);
10602 %}
10603
10604 instruct storeV2F_zero(memory mem, immF0 zero) %{
10605 predicate(n->as_StoreVector()->memory_size() == 8);
10606 match(Set mem (StoreVector mem (ReplicateF zero)));
10607 ins_cost(MEMORY_REF_COST);
10608 size(4);
10609 format %{ "STX $zero,$mem\t! store zero vector (2 floats)" %}
10610 ins_encode %{
10611 __ stx(G0, $mem$$Address);
10612 %}
10613 ins_pipe(fstoreD_mem_zero);
10614 %}
10615
10616 // Replicate scalar to packed byte values into Double register
10617 instruct Repl8B_reg(regD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
10618 predicate(n->as_Vector()->length() == 8 && UseVIS >= 3);
10619 match(Set dst (ReplicateB src));
10620 effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
10621 format %{ "SLLX $src,56,$tmp\n\t"
10622 "SRLX $tmp, 8,$tmp2\n\t"
10623 "OR $tmp,$tmp2,$tmp\n\t"
10624 "SRLX $tmp,16,$tmp2\n\t"
10625 "OR $tmp,$tmp2,$tmp\n\t"
10626 "SRLX $tmp,32,$tmp2\n\t"
10627 "OR $tmp,$tmp2,$tmp\t! replicate8B\n\t"
10628 "MOVXTOD $tmp,$dst\t! MoveL2D" %}
10629 ins_encode %{
10630 Register Rsrc = $src$$Register;
10631 Register Rtmp = $tmp$$Register;
10632 Register Rtmp2 = $tmp2$$Register;
10633 __ sllx(Rsrc, 56, Rtmp);
10634 __ srlx(Rtmp, 8, Rtmp2);
10635 __ or3 (Rtmp, Rtmp2, Rtmp);
10636 __ srlx(Rtmp, 16, Rtmp2);
10637 __ or3 (Rtmp, Rtmp2, Rtmp);
10638 __ srlx(Rtmp, 32, Rtmp2);
10639 __ or3 (Rtmp, Rtmp2, Rtmp);
10640 __ movxtod(Rtmp, as_DoubleFloatRegister($dst$$reg));
10641 %}
10642 ins_pipe(ialu_reg);
10643 %}
10644
10645 // Replicate scalar to packed byte values into Double stack
10646 instruct Repl8B_stk(stackSlotD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
10647 predicate(n->as_Vector()->length() == 8 && UseVIS < 3);
10648 match(Set dst (ReplicateB src));
10649 effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
10650 format %{ "SLLX $src,56,$tmp\n\t"
10651 "SRLX $tmp, 8,$tmp2\n\t"
10652 "OR $tmp,$tmp2,$tmp\n\t"
10653 "SRLX $tmp,16,$tmp2\n\t"
10654 "OR $tmp,$tmp2,$tmp\n\t"
10655 "SRLX $tmp,32,$tmp2\n\t"
10656 "OR $tmp,$tmp2,$tmp\t! replicate8B\n\t"
10657 "STX $tmp,$dst\t! regL to stkD" %}
10658 ins_encode %{
10659 Register Rsrc = $src$$Register;
10660 Register Rtmp = $tmp$$Register;
10661 Register Rtmp2 = $tmp2$$Register;
10662 __ sllx(Rsrc, 56, Rtmp);
10663 __ srlx(Rtmp, 8, Rtmp2);
10664 __ or3 (Rtmp, Rtmp2, Rtmp);
10665 __ srlx(Rtmp, 16, Rtmp2);
10666 __ or3 (Rtmp, Rtmp2, Rtmp);
10667 __ srlx(Rtmp, 32, Rtmp2);
10668 __ or3 (Rtmp, Rtmp2, Rtmp);
10669 __ set ($dst$$disp + STACK_BIAS, Rtmp2);
10670 __ stx (Rtmp, Rtmp2, $dst$$base$$Register);
10671 %}
10672 ins_pipe(ialu_reg);
10673 %}
10674
10675 // Replicate scalar constant to packed byte values in Double register
10676 instruct Repl8B_immI(regD dst, immI13 con, o7RegI tmp) %{
10677 predicate(n->as_Vector()->length() == 8);
10678 match(Set dst (ReplicateB con));
10679 effect(KILL tmp);
10680 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl8B($con)" %}
10681 ins_encode %{
10682 // XXX This is a quick fix for 6833573.
10683 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 8, 1)), $dst$$FloatRegister);
10684 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 8, 1)), $tmp$$Register);
10685 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
10686 %}
10687 ins_pipe(loadConFD);
10688 %}
10689
10690 // Replicate scalar to packed char/short values into Double register
10691 instruct Repl4S_reg(regD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
10692 predicate(n->as_Vector()->length() == 4 && UseVIS >= 3);
10693 match(Set dst (ReplicateS src));
10694 effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
10695 format %{ "SLLX $src,48,$tmp\n\t"
10696 "SRLX $tmp,16,$tmp2\n\t"
10697 "OR $tmp,$tmp2,$tmp\n\t"
10698 "SRLX $tmp,32,$tmp2\n\t"
10699 "OR $tmp,$tmp2,$tmp\t! replicate4S\n\t"
10700 "MOVXTOD $tmp,$dst\t! MoveL2D" %}
10701 ins_encode %{
10702 Register Rsrc = $src$$Register;
10703 Register Rtmp = $tmp$$Register;
10704 Register Rtmp2 = $tmp2$$Register;
10705 __ sllx(Rsrc, 48, Rtmp);
10706 __ srlx(Rtmp, 16, Rtmp2);
10707 __ or3 (Rtmp, Rtmp2, Rtmp);
10708 __ srlx(Rtmp, 32, Rtmp2);
10709 __ or3 (Rtmp, Rtmp2, Rtmp);
10710 __ movxtod(Rtmp, as_DoubleFloatRegister($dst$$reg));
10711 %}
10712 ins_pipe(ialu_reg);
10713 %}
10714
10715 // Replicate scalar to packed char/short values into Double stack
10716 instruct Repl4S_stk(stackSlotD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
10717 predicate(n->as_Vector()->length() == 4 && UseVIS < 3);
10718 match(Set dst (ReplicateS src));
10719 effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
10720 format %{ "SLLX $src,48,$tmp\n\t"
10721 "SRLX $tmp,16,$tmp2\n\t"
10722 "OR $tmp,$tmp2,$tmp\n\t"
10723 "SRLX $tmp,32,$tmp2\n\t"
10724 "OR $tmp,$tmp2,$tmp\t! replicate4S\n\t"
10725 "STX $tmp,$dst\t! regL to stkD" %}
10726 ins_encode %{
10727 Register Rsrc = $src$$Register;
10728 Register Rtmp = $tmp$$Register;
10729 Register Rtmp2 = $tmp2$$Register;
10730 __ sllx(Rsrc, 48, Rtmp);
10731 __ srlx(Rtmp, 16, Rtmp2);
10732 __ or3 (Rtmp, Rtmp2, Rtmp);
10733 __ srlx(Rtmp, 32, Rtmp2);
10734 __ or3 (Rtmp, Rtmp2, Rtmp);
10735 __ set ($dst$$disp + STACK_BIAS, Rtmp2);
10736 __ stx (Rtmp, Rtmp2, $dst$$base$$Register);
10737 %}
10738 ins_pipe(ialu_reg);
10739 %}
10740
10741 // Replicate scalar constant to packed char/short values in Double register
10742 instruct Repl4S_immI(regD dst, immI con, o7RegI tmp) %{
10743 predicate(n->as_Vector()->length() == 4);
10744 match(Set dst (ReplicateS con));
10745 effect(KILL tmp);
10746 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl4S($con)" %}
10747 ins_encode %{
10748 // XXX This is a quick fix for 6833573.
10749 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 4, 2)), $dst$$FloatRegister);
10750 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 4, 2)), $tmp$$Register);
10751 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
10752 %}
10753 ins_pipe(loadConFD);
10754 %}
10755
10756 // Replicate scalar to packed int values into Double register
10757 instruct Repl2I_reg(regD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
10758 predicate(n->as_Vector()->length() == 2 && UseVIS >= 3);
10759 match(Set dst (ReplicateI src));
10760 effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
10761 format %{ "SLLX $src,32,$tmp\n\t"
10762 "SRLX $tmp,32,$tmp2\n\t"
10763 "OR $tmp,$tmp2,$tmp\t! replicate2I\n\t"
10764 "MOVXTOD $tmp,$dst\t! MoveL2D" %}
10765 ins_encode %{
10766 Register Rsrc = $src$$Register;
10767 Register Rtmp = $tmp$$Register;
10768 Register Rtmp2 = $tmp2$$Register;
10769 __ sllx(Rsrc, 32, Rtmp);
10770 __ srlx(Rtmp, 32, Rtmp2);
10771 __ or3 (Rtmp, Rtmp2, Rtmp);
10772 __ movxtod(Rtmp, as_DoubleFloatRegister($dst$$reg));
10773 %}
10774 ins_pipe(ialu_reg);
10775 %}
10776
10777 // Replicate scalar to packed int values into Double stack
10778 instruct Repl2I_stk(stackSlotD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
10779 predicate(n->as_Vector()->length() == 2 && UseVIS < 3);
10780 match(Set dst (ReplicateI src));
10781 effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
10782 format %{ "SLLX $src,32,$tmp\n\t"
10783 "SRLX $tmp,32,$tmp2\n\t"
10784 "OR $tmp,$tmp2,$tmp\t! replicate2I\n\t"
10785 "STX $tmp,$dst\t! regL to stkD" %}
10786 ins_encode %{
10787 Register Rsrc = $src$$Register;
10788 Register Rtmp = $tmp$$Register;
10789 Register Rtmp2 = $tmp2$$Register;
10790 __ sllx(Rsrc, 32, Rtmp);
10791 __ srlx(Rtmp, 32, Rtmp2);
10792 __ or3 (Rtmp, Rtmp2, Rtmp);
10793 __ set ($dst$$disp + STACK_BIAS, Rtmp2);
10794 __ stx (Rtmp, Rtmp2, $dst$$base$$Register);
10795 %}
10796 ins_pipe(ialu_reg);
10797 %}
10798
10799 // Replicate scalar zero constant to packed int values in Double register
10800 instruct Repl2I_immI(regD dst, immI con, o7RegI tmp) %{
10801 predicate(n->as_Vector()->length() == 2);
10802 match(Set dst (ReplicateI con));
10803 effect(KILL tmp);
10804 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl2I($con)" %}
10805 ins_encode %{
10806 // XXX This is a quick fix for 6833573.
10807 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 2, 4)), $dst$$FloatRegister);
10808 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 2, 4)), $tmp$$Register);
10809 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
10810 %}
10811 ins_pipe(loadConFD);
10812 %}
10813
10814 // Replicate scalar to packed float values into Double stack
10815 instruct Repl2F_stk(stackSlotD dst, regF src) %{
10816 predicate(n->as_Vector()->length() == 2);
10817 match(Set dst (ReplicateF src));
10818 ins_cost(MEMORY_REF_COST*2);
10819 format %{ "STF $src,$dst.hi\t! packed2F\n\t"
10820 "STF $src,$dst.lo" %}
10821 opcode(Assembler::stf_op3);
10822 ins_encode(simple_form3_mem_reg(dst, src), form3_mem_plus_4_reg(dst, src));
10823 ins_pipe(fstoreF_stk_reg);
10824 %}
10825
10826 // Replicate scalar zero constant to packed float values in Double register
10827 instruct Repl2F_immF(regD dst, immF con, o7RegI tmp) %{
10828 predicate(n->as_Vector()->length() == 2);
10829 match(Set dst (ReplicateF con));
10830 effect(KILL tmp);
10831 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl2F($con)" %}
10832 ins_encode %{
10833 // XXX This is a quick fix for 6833573.
10834 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immF($con$$constant)), $dst$$FloatRegister);
10835 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immF($con$$constant)), $tmp$$Register);
10836 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
10837 %}
10838 ins_pipe(loadConFD);
10839 %}
10840
10841 //----------PEEPHOLE RULES-----------------------------------------------------
10842 // These must follow all instruction definitions as they use the names
10843 // defined in the instructions definitions.
10844 //
10845 // peepmatch ( root_instr_name [preceding_instruction]* );
10846 //
10847 // peepconstraint %{
10848 // (instruction_number.operand_name relational_op instruction_number.operand_name
10849 // [, ...] );
10850 // // instruction numbers are zero-based using left to right order in peepmatch
10851 //
10852 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
10853 // // provide an instruction_number.operand_name for each operand that appears
10854 // // in the replacement instruction's match rule
10855 //
10856 // ---------VM FLAGS---------------------------------------------------------
10857 //
10858 // All peephole optimizations can be turned off using -XX:-OptoPeephole
10859 //
10860 // Each peephole rule is given an identifying number starting with zero and
10861 // increasing by one in the order seen by the parser. An individual peephole
10862 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
10863 // on the command-line.
10864 //
10865 // ---------CURRENT LIMITATIONS----------------------------------------------
10866 //
10867 // Only match adjacent instructions in same basic block
10868 // Only equality constraints
10869 // Only constraints between operands, not (0.dest_reg == EAX_enc)
10870 // Only one replacement instruction
10871 //
10872 // ---------EXAMPLE----------------------------------------------------------
10873 //
10874 // // pertinent parts of existing instructions in architecture description
10875 // instruct movI(eRegI dst, eRegI src) %{
10876 // match(Set dst (CopyI src));
10877 // %}
10878 //
10879 // instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{
10880 // match(Set dst (AddI dst src));
10881 // effect(KILL cr);
10882 // %}
10883 //
10884 // // Change (inc mov) to lea
10885 // peephole %{
10886 // // increment preceeded by register-register move
10887 // peepmatch ( incI_eReg movI );
10888 // // require that the destination register of the increment
10889 // // match the destination register of the move
10890 // peepconstraint ( 0.dst == 1.dst );
10891 // // construct a replacement instruction that sets
10892 // // the destination to ( move's source register + one )
10893 // peepreplace ( incI_eReg_immI1( 0.dst 1.src 0.src ) );
10894 // %}
10895 //
10896
10897 // // Change load of spilled value to only a spill
10898 // instruct storeI(memory mem, eRegI src) %{
10899 // match(Set mem (StoreI mem src));
10900 // %}
10901 //
10902 // instruct loadI(eRegI dst, memory mem) %{
10903 // match(Set dst (LoadI mem));
10904 // %}
10905 //
10906 // peephole %{
10907 // peepmatch ( loadI storeI );
10908 // peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem );
10909 // peepreplace ( storeI( 1.mem 1.mem 1.src ) );
10910 // %}
10911
10912 //----------SMARTSPILL RULES---------------------------------------------------
10913 // These must follow all instruction definitions as they use the names
10914 // defined in the instructions definitions.
10915 //
10916 // SPARC will probably not have any of these rules due to RISC instruction set.
10917
10918 //----------PIPELINE-----------------------------------------------------------
10919 // Rules which define the behavior of the target architectures pipeline.