1 /*
2 * Copyright (c) 1997, 2017, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "asm/assembler.hpp"
27 #include "asm/assembler.inline.hpp"
28 #include "compiler/disassembler.hpp"
29 #include "gc/shared/cardTableModRefBS.hpp"
30 #include "gc/shared/collectedHeap.inline.hpp"
31 #include "interpreter/interpreter.hpp"
32 #include "memory/resourceArea.hpp"
33 #include "memory/universe.hpp"
34 #include "oops/klass.inline.hpp"
35 #include "prims/methodHandles.hpp"
36 #include "runtime/biasedLocking.hpp"
37 #include "runtime/interfaceSupport.hpp"
38 #include "runtime/objectMonitor.hpp"
39 #include "runtime/os.hpp"
40 #include "runtime/sharedRuntime.hpp"
41 #include "runtime/stubRoutines.hpp"
42 #include "runtime/thread.hpp"
43 #include "utilities/macros.hpp"
44 #if INCLUDE_ALL_GCS
45 #include "gc/g1/g1CollectedHeap.inline.hpp"
46 #include "gc/g1/g1SATBCardTableModRefBS.hpp"
47 #include "gc/g1/heapRegion.hpp"
48 #endif // INCLUDE_ALL_GCS
49 #include "crc32c.h"
50 #ifdef COMPILER2
51 #include "opto/intrinsicnode.hpp"
52 #endif
53
54 #ifdef PRODUCT
55 #define BLOCK_COMMENT(str) /* nothing */
56 #define STOP(error) stop(error)
57 #else
58 #define BLOCK_COMMENT(str) block_comment(str)
59 #define STOP(error) block_comment(error); stop(error)
60 #endif
61
62 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":")
63
64 #ifdef ASSERT
65 bool AbstractAssembler::pd_check_instruction_mark() { return true; }
66 #endif
67
68 static Assembler::Condition reverse[] = {
69 Assembler::noOverflow /* overflow = 0x0 */ ,
70 Assembler::overflow /* noOverflow = 0x1 */ ,
71 Assembler::aboveEqual /* carrySet = 0x2, below = 0x2 */ ,
72 Assembler::below /* aboveEqual = 0x3, carryClear = 0x3 */ ,
73 Assembler::notZero /* zero = 0x4, equal = 0x4 */ ,
74 Assembler::zero /* notZero = 0x5, notEqual = 0x5 */ ,
75 Assembler::above /* belowEqual = 0x6 */ ,
76 Assembler::belowEqual /* above = 0x7 */ ,
77 Assembler::positive /* negative = 0x8 */ ,
78 Assembler::negative /* positive = 0x9 */ ,
79 Assembler::noParity /* parity = 0xa */ ,
80 Assembler::parity /* noParity = 0xb */ ,
81 Assembler::greaterEqual /* less = 0xc */ ,
82 Assembler::less /* greaterEqual = 0xd */ ,
83 Assembler::greater /* lessEqual = 0xe */ ,
84 Assembler::lessEqual /* greater = 0xf, */
85
86 };
87
88
89 // Implementation of MacroAssembler
90
91 // First all the versions that have distinct versions depending on 32/64 bit
92 // Unless the difference is trivial (1 line or so).
93
94 #ifndef _LP64
95
96 // 32bit versions
97
98 Address MacroAssembler::as_Address(AddressLiteral adr) {
99 return Address(adr.target(), adr.rspec());
100 }
101
102 Address MacroAssembler::as_Address(ArrayAddress adr) {
103 return Address::make_array(adr);
104 }
105
106 void MacroAssembler::call_VM_leaf_base(address entry_point,
107 int number_of_arguments) {
108 call(RuntimeAddress(entry_point));
109 increment(rsp, number_of_arguments * wordSize);
110 }
111
112 void MacroAssembler::cmpklass(Address src1, Metadata* obj) {
113 cmp_literal32(src1, (int32_t)obj, metadata_Relocation::spec_for_immediate());
114 }
115
116 void MacroAssembler::cmpklass(Register src1, Metadata* obj) {
117 cmp_literal32(src1, (int32_t)obj, metadata_Relocation::spec_for_immediate());
118 }
119
120 void MacroAssembler::cmpoop(Address src1, jobject obj) {
121 cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate());
122 }
123
124 void MacroAssembler::cmpoop(Register src1, jobject obj) {
125 cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate());
126 }
127
128 void MacroAssembler::extend_sign(Register hi, Register lo) {
129 // According to Intel Doc. AP-526, "Integer Divide", p.18.
130 if (VM_Version::is_P6() && hi == rdx && lo == rax) {
131 cdql();
132 } else {
133 movl(hi, lo);
134 sarl(hi, 31);
135 }
136 }
137
138 void MacroAssembler::jC2(Register tmp, Label& L) {
139 // set parity bit if FPU flag C2 is set (via rax)
140 save_rax(tmp);
141 fwait(); fnstsw_ax();
142 sahf();
143 restore_rax(tmp);
144 // branch
145 jcc(Assembler::parity, L);
146 }
147
148 void MacroAssembler::jnC2(Register tmp, Label& L) {
149 // set parity bit if FPU flag C2 is set (via rax)
150 save_rax(tmp);
151 fwait(); fnstsw_ax();
152 sahf();
153 restore_rax(tmp);
154 // branch
155 jcc(Assembler::noParity, L);
156 }
157
158 // 32bit can do a case table jump in one instruction but we no longer allow the base
159 // to be installed in the Address class
160 void MacroAssembler::jump(ArrayAddress entry) {
161 jmp(as_Address(entry));
162 }
163
164 // Note: y_lo will be destroyed
165 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) {
166 // Long compare for Java (semantics as described in JVM spec.)
167 Label high, low, done;
168
169 cmpl(x_hi, y_hi);
170 jcc(Assembler::less, low);
171 jcc(Assembler::greater, high);
172 // x_hi is the return register
173 xorl(x_hi, x_hi);
174 cmpl(x_lo, y_lo);
175 jcc(Assembler::below, low);
176 jcc(Assembler::equal, done);
177
178 bind(high);
179 xorl(x_hi, x_hi);
180 increment(x_hi);
181 jmp(done);
182
183 bind(low);
184 xorl(x_hi, x_hi);
185 decrementl(x_hi);
186
187 bind(done);
188 }
189
190 void MacroAssembler::lea(Register dst, AddressLiteral src) {
191 mov_literal32(dst, (int32_t)src.target(), src.rspec());
192 }
193
194 void MacroAssembler::lea(Address dst, AddressLiteral adr) {
195 // leal(dst, as_Address(adr));
196 // see note in movl as to why we must use a move
197 mov_literal32(dst, (int32_t) adr.target(), adr.rspec());
198 }
199
200 void MacroAssembler::leave() {
201 mov(rsp, rbp);
202 pop(rbp);
203 }
204
205 void MacroAssembler::lmul(int x_rsp_offset, int y_rsp_offset) {
206 // Multiplication of two Java long values stored on the stack
207 // as illustrated below. Result is in rdx:rax.
208 //
209 // rsp ---> [ ?? ] \ \
210 // .... | y_rsp_offset |
211 // [ y_lo ] / (in bytes) | x_rsp_offset
212 // [ y_hi ] | (in bytes)
213 // .... |
214 // [ x_lo ] /
215 // [ x_hi ]
216 // ....
217 //
218 // Basic idea: lo(result) = lo(x_lo * y_lo)
219 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi)
220 Address x_hi(rsp, x_rsp_offset + wordSize); Address x_lo(rsp, x_rsp_offset);
221 Address y_hi(rsp, y_rsp_offset + wordSize); Address y_lo(rsp, y_rsp_offset);
222 Label quick;
223 // load x_hi, y_hi and check if quick
224 // multiplication is possible
225 movl(rbx, x_hi);
226 movl(rcx, y_hi);
227 movl(rax, rbx);
228 orl(rbx, rcx); // rbx, = 0 <=> x_hi = 0 and y_hi = 0
229 jcc(Assembler::zero, quick); // if rbx, = 0 do quick multiply
230 // do full multiplication
231 // 1st step
232 mull(y_lo); // x_hi * y_lo
233 movl(rbx, rax); // save lo(x_hi * y_lo) in rbx,
234 // 2nd step
235 movl(rax, x_lo);
236 mull(rcx); // x_lo * y_hi
237 addl(rbx, rax); // add lo(x_lo * y_hi) to rbx,
238 // 3rd step
239 bind(quick); // note: rbx, = 0 if quick multiply!
240 movl(rax, x_lo);
241 mull(y_lo); // x_lo * y_lo
242 addl(rdx, rbx); // correct hi(x_lo * y_lo)
243 }
244
245 void MacroAssembler::lneg(Register hi, Register lo) {
246 negl(lo);
247 adcl(hi, 0);
248 negl(hi);
249 }
250
251 void MacroAssembler::lshl(Register hi, Register lo) {
252 // Java shift left long support (semantics as described in JVM spec., p.305)
253 // (basic idea for shift counts s >= n: x << s == (x << n) << (s - n))
254 // shift value is in rcx !
255 assert(hi != rcx, "must not use rcx");
256 assert(lo != rcx, "must not use rcx");
257 const Register s = rcx; // shift count
258 const int n = BitsPerWord;
259 Label L;
260 andl(s, 0x3f); // s := s & 0x3f (s < 0x40)
261 cmpl(s, n); // if (s < n)
262 jcc(Assembler::less, L); // else (s >= n)
263 movl(hi, lo); // x := x << n
264 xorl(lo, lo);
265 // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n!
266 bind(L); // s (mod n) < n
267 shldl(hi, lo); // x := x << s
268 shll(lo);
269 }
270
271
272 void MacroAssembler::lshr(Register hi, Register lo, bool sign_extension) {
273 // Java shift right long support (semantics as described in JVM spec., p.306 & p.310)
274 // (basic idea for shift counts s >= n: x >> s == (x >> n) >> (s - n))
275 assert(hi != rcx, "must not use rcx");
276 assert(lo != rcx, "must not use rcx");
277 const Register s = rcx; // shift count
278 const int n = BitsPerWord;
279 Label L;
280 andl(s, 0x3f); // s := s & 0x3f (s < 0x40)
281 cmpl(s, n); // if (s < n)
282 jcc(Assembler::less, L); // else (s >= n)
283 movl(lo, hi); // x := x >> n
284 if (sign_extension) sarl(hi, 31);
285 else xorl(hi, hi);
286 // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n!
287 bind(L); // s (mod n) < n
288 shrdl(lo, hi); // x := x >> s
289 if (sign_extension) sarl(hi);
290 else shrl(hi);
291 }
292
293 void MacroAssembler::movoop(Register dst, jobject obj) {
294 mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate());
295 }
296
297 void MacroAssembler::movoop(Address dst, jobject obj) {
298 mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate());
299 }
300
301 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) {
302 mov_literal32(dst, (int32_t)obj, metadata_Relocation::spec_for_immediate());
303 }
304
305 void MacroAssembler::mov_metadata(Address dst, Metadata* obj) {
306 mov_literal32(dst, (int32_t)obj, metadata_Relocation::spec_for_immediate());
307 }
308
309 void MacroAssembler::movptr(Register dst, AddressLiteral src, Register scratch) {
310 // scratch register is not used,
311 // it is defined to match parameters of 64-bit version of this method.
312 if (src.is_lval()) {
313 mov_literal32(dst, (intptr_t)src.target(), src.rspec());
314 } else {
315 movl(dst, as_Address(src));
316 }
317 }
318
319 void MacroAssembler::movptr(ArrayAddress dst, Register src) {
320 movl(as_Address(dst), src);
321 }
322
323 void MacroAssembler::movptr(Register dst, ArrayAddress src) {
324 movl(dst, as_Address(src));
325 }
326
327 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
328 void MacroAssembler::movptr(Address dst, intptr_t src) {
329 movl(dst, src);
330 }
331
332
333 void MacroAssembler::pop_callee_saved_registers() {
334 pop(rcx);
335 pop(rdx);
336 pop(rdi);
337 pop(rsi);
338 }
339
340 void MacroAssembler::pop_fTOS() {
341 fld_d(Address(rsp, 0));
342 addl(rsp, 2 * wordSize);
343 }
344
345 void MacroAssembler::push_callee_saved_registers() {
346 push(rsi);
347 push(rdi);
348 push(rdx);
349 push(rcx);
350 }
351
352 void MacroAssembler::push_fTOS() {
353 subl(rsp, 2 * wordSize);
354 fstp_d(Address(rsp, 0));
355 }
356
357
358 void MacroAssembler::pushoop(jobject obj) {
359 push_literal32((int32_t)obj, oop_Relocation::spec_for_immediate());
360 }
361
362 void MacroAssembler::pushklass(Metadata* obj) {
363 push_literal32((int32_t)obj, metadata_Relocation::spec_for_immediate());
364 }
365
366 void MacroAssembler::pushptr(AddressLiteral src) {
367 if (src.is_lval()) {
368 push_literal32((int32_t)src.target(), src.rspec());
369 } else {
370 pushl(as_Address(src));
371 }
372 }
373
374 void MacroAssembler::set_word_if_not_zero(Register dst) {
375 xorl(dst, dst);
376 set_byte_if_not_zero(dst);
377 }
378
379 static void pass_arg0(MacroAssembler* masm, Register arg) {
380 masm->push(arg);
381 }
382
383 static void pass_arg1(MacroAssembler* masm, Register arg) {
384 masm->push(arg);
385 }
386
387 static void pass_arg2(MacroAssembler* masm, Register arg) {
388 masm->push(arg);
389 }
390
391 static void pass_arg3(MacroAssembler* masm, Register arg) {
392 masm->push(arg);
393 }
394
395 #ifndef PRODUCT
396 extern "C" void findpc(intptr_t x);
397 #endif
398
399 void MacroAssembler::debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg) {
400 // In order to get locks to work, we need to fake a in_VM state
401 JavaThread* thread = JavaThread::current();
402 JavaThreadState saved_state = thread->thread_state();
403 thread->set_thread_state(_thread_in_vm);
404 if (ShowMessageBoxOnError) {
405 JavaThread* thread = JavaThread::current();
406 JavaThreadState saved_state = thread->thread_state();
407 thread->set_thread_state(_thread_in_vm);
408 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {
409 ttyLocker ttyl;
410 BytecodeCounter::print();
411 }
412 // To see where a verify_oop failed, get $ebx+40/X for this frame.
413 // This is the value of eip which points to where verify_oop will return.
414 if (os::message_box(msg, "Execution stopped, print registers?")) {
415 print_state32(rdi, rsi, rbp, rsp, rbx, rdx, rcx, rax, eip);
416 BREAKPOINT;
417 }
418 } else {
419 ttyLocker ttyl;
420 ::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n", msg);
421 }
422 // Don't assert holding the ttyLock
423 assert(false, "DEBUG MESSAGE: %s", msg);
424 ThreadStateTransition::transition(thread, _thread_in_vm, saved_state);
425 }
426
427 void MacroAssembler::print_state32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip) {
428 ttyLocker ttyl;
429 FlagSetting fs(Debugging, true);
430 tty->print_cr("eip = 0x%08x", eip);
431 #ifndef PRODUCT
432 if ((WizardMode || Verbose) && PrintMiscellaneous) {
433 tty->cr();
434 findpc(eip);
435 tty->cr();
436 }
437 #endif
438 #define PRINT_REG(rax) \
439 { tty->print("%s = ", #rax); os::print_location(tty, rax); }
440 PRINT_REG(rax);
441 PRINT_REG(rbx);
442 PRINT_REG(rcx);
443 PRINT_REG(rdx);
444 PRINT_REG(rdi);
445 PRINT_REG(rsi);
446 PRINT_REG(rbp);
447 PRINT_REG(rsp);
448 #undef PRINT_REG
449 // Print some words near top of staack.
450 int* dump_sp = (int*) rsp;
451 for (int col1 = 0; col1 < 8; col1++) {
452 tty->print("(rsp+0x%03x) 0x%08x: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
453 os::print_location(tty, *dump_sp++);
454 }
455 for (int row = 0; row < 16; row++) {
456 tty->print("(rsp+0x%03x) 0x%08x: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
457 for (int col = 0; col < 8; col++) {
458 tty->print(" 0x%08x", *dump_sp++);
459 }
460 tty->cr();
461 }
462 // Print some instructions around pc:
463 Disassembler::decode((address)eip-64, (address)eip);
464 tty->print_cr("--------");
465 Disassembler::decode((address)eip, (address)eip+32);
466 }
467
468 void MacroAssembler::stop(const char* msg) {
469 ExternalAddress message((address)msg);
470 // push address of message
471 pushptr(message.addr());
472 { Label L; call(L, relocInfo::none); bind(L); } // push eip
473 pusha(); // push registers
474 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug32)));
475 hlt();
476 }
477
478 void MacroAssembler::warn(const char* msg) {
479 push_CPU_state();
480
481 ExternalAddress message((address) msg);
482 // push address of message
483 pushptr(message.addr());
484
485 call(RuntimeAddress(CAST_FROM_FN_PTR(address, warning)));
486 addl(rsp, wordSize); // discard argument
487 pop_CPU_state();
488 }
489
490 void MacroAssembler::print_state() {
491 { Label L; call(L, relocInfo::none); bind(L); } // push eip
492 pusha(); // push registers
493
494 push_CPU_state();
495 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::print_state32)));
496 pop_CPU_state();
497
498 popa();
499 addl(rsp, wordSize);
500 }
501
502 #else // _LP64
503
504 // 64 bit versions
505
506 Address MacroAssembler::as_Address(AddressLiteral adr) {
507 // amd64 always does this as a pc-rel
508 // we can be absolute or disp based on the instruction type
509 // jmp/call are displacements others are absolute
510 assert(!adr.is_lval(), "must be rval");
511 assert(reachable(adr), "must be");
512 return Address((int32_t)(intptr_t)(adr.target() - pc()), adr.target(), adr.reloc());
513
514 }
515
516 Address MacroAssembler::as_Address(ArrayAddress adr) {
517 AddressLiteral base = adr.base();
518 lea(rscratch1, base);
519 Address index = adr.index();
520 assert(index._disp == 0, "must not have disp"); // maybe it can?
521 Address array(rscratch1, index._index, index._scale, index._disp);
522 return array;
523 }
524
525 void MacroAssembler::call_VM_leaf_base(address entry_point, int num_args) {
526 Label L, E;
527
528 #ifdef _WIN64
529 // Windows always allocates space for it's register args
530 assert(num_args <= 4, "only register arguments supported");
531 subq(rsp, frame::arg_reg_save_area_bytes);
532 #endif
533
534 // Align stack if necessary
535 testl(rsp, 15);
536 jcc(Assembler::zero, L);
537
538 subq(rsp, 8);
539 {
540 call(RuntimeAddress(entry_point));
541 }
542 addq(rsp, 8);
543 jmp(E);
544
545 bind(L);
546 {
547 call(RuntimeAddress(entry_point));
548 }
549
550 bind(E);
551
552 #ifdef _WIN64
553 // restore stack pointer
554 addq(rsp, frame::arg_reg_save_area_bytes);
555 #endif
556
557 }
558
559 void MacroAssembler::cmp64(Register src1, AddressLiteral src2) {
560 assert(!src2.is_lval(), "should use cmpptr");
561
562 if (reachable(src2)) {
563 cmpq(src1, as_Address(src2));
564 } else {
565 lea(rscratch1, src2);
566 Assembler::cmpq(src1, Address(rscratch1, 0));
567 }
568 }
569
570 int MacroAssembler::corrected_idivq(Register reg) {
571 // Full implementation of Java ldiv and lrem; checks for special
572 // case as described in JVM spec., p.243 & p.271. The function
573 // returns the (pc) offset of the idivl instruction - may be needed
574 // for implicit exceptions.
575 //
576 // normal case special case
577 //
578 // input : rax: dividend min_long
579 // reg: divisor (may not be eax/edx) -1
580 //
581 // output: rax: quotient (= rax idiv reg) min_long
582 // rdx: remainder (= rax irem reg) 0
583 assert(reg != rax && reg != rdx, "reg cannot be rax or rdx register");
584 static const int64_t min_long = 0x8000000000000000;
585 Label normal_case, special_case;
586
587 // check for special case
588 cmp64(rax, ExternalAddress((address) &min_long));
589 jcc(Assembler::notEqual, normal_case);
590 xorl(rdx, rdx); // prepare rdx for possible special case (where
591 // remainder = 0)
592 cmpq(reg, -1);
593 jcc(Assembler::equal, special_case);
594
595 // handle normal case
596 bind(normal_case);
597 cdqq();
598 int idivq_offset = offset();
599 idivq(reg);
600
601 // normal and special case exit
602 bind(special_case);
603
604 return idivq_offset;
605 }
606
607 void MacroAssembler::decrementq(Register reg, int value) {
608 if (value == min_jint) { subq(reg, value); return; }
609 if (value < 0) { incrementq(reg, -value); return; }
610 if (value == 0) { ; return; }
611 if (value == 1 && UseIncDec) { decq(reg) ; return; }
612 /* else */ { subq(reg, value) ; return; }
613 }
614
615 void MacroAssembler::decrementq(Address dst, int value) {
616 if (value == min_jint) { subq(dst, value); return; }
617 if (value < 0) { incrementq(dst, -value); return; }
618 if (value == 0) { ; return; }
619 if (value == 1 && UseIncDec) { decq(dst) ; return; }
620 /* else */ { subq(dst, value) ; return; }
621 }
622
623 void MacroAssembler::incrementq(AddressLiteral dst) {
624 if (reachable(dst)) {
625 incrementq(as_Address(dst));
626 } else {
627 lea(rscratch1, dst);
628 incrementq(Address(rscratch1, 0));
629 }
630 }
631
632 void MacroAssembler::incrementq(Register reg, int value) {
633 if (value == min_jint) { addq(reg, value); return; }
634 if (value < 0) { decrementq(reg, -value); return; }
635 if (value == 0) { ; return; }
636 if (value == 1 && UseIncDec) { incq(reg) ; return; }
637 /* else */ { addq(reg, value) ; return; }
638 }
639
640 void MacroAssembler::incrementq(Address dst, int value) {
641 if (value == min_jint) { addq(dst, value); return; }
642 if (value < 0) { decrementq(dst, -value); return; }
643 if (value == 0) { ; return; }
644 if (value == 1 && UseIncDec) { incq(dst) ; return; }
645 /* else */ { addq(dst, value) ; return; }
646 }
647
648 // 32bit can do a case table jump in one instruction but we no longer allow the base
649 // to be installed in the Address class
650 void MacroAssembler::jump(ArrayAddress entry) {
651 lea(rscratch1, entry.base());
652 Address dispatch = entry.index();
653 assert(dispatch._base == noreg, "must be");
654 dispatch._base = rscratch1;
655 jmp(dispatch);
656 }
657
658 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) {
659 ShouldNotReachHere(); // 64bit doesn't use two regs
660 cmpq(x_lo, y_lo);
661 }
662
663 void MacroAssembler::lea(Register dst, AddressLiteral src) {
664 mov_literal64(dst, (intptr_t)src.target(), src.rspec());
665 }
666
667 void MacroAssembler::lea(Address dst, AddressLiteral adr) {
668 mov_literal64(rscratch1, (intptr_t)adr.target(), adr.rspec());
669 movptr(dst, rscratch1);
670 }
671
672 void MacroAssembler::leave() {
673 // %%% is this really better? Why not on 32bit too?
674 emit_int8((unsigned char)0xC9); // LEAVE
675 }
676
677 void MacroAssembler::lneg(Register hi, Register lo) {
678 ShouldNotReachHere(); // 64bit doesn't use two regs
679 negq(lo);
680 }
681
682 void MacroAssembler::movoop(Register dst, jobject obj) {
683 mov_literal64(dst, (intptr_t)obj, oop_Relocation::spec_for_immediate());
684 }
685
686 void MacroAssembler::movoop(Address dst, jobject obj) {
687 mov_literal64(rscratch1, (intptr_t)obj, oop_Relocation::spec_for_immediate());
688 movq(dst, rscratch1);
689 }
690
691 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) {
692 mov_literal64(dst, (intptr_t)obj, metadata_Relocation::spec_for_immediate());
693 }
694
695 void MacroAssembler::mov_metadata(Address dst, Metadata* obj) {
696 mov_literal64(rscratch1, (intptr_t)obj, metadata_Relocation::spec_for_immediate());
697 movq(dst, rscratch1);
698 }
699
700 void MacroAssembler::movptr(Register dst, AddressLiteral src, Register scratch) {
701 if (src.is_lval()) {
702 mov_literal64(dst, (intptr_t)src.target(), src.rspec());
703 } else {
704 if (reachable(src)) {
705 movq(dst, as_Address(src));
706 } else {
707 lea(scratch, src);
708 movq(dst, Address(scratch, 0));
709 }
710 }
711 }
712
713 void MacroAssembler::movptr(ArrayAddress dst, Register src) {
714 movq(as_Address(dst), src);
715 }
716
717 void MacroAssembler::movptr(Register dst, ArrayAddress src) {
718 movq(dst, as_Address(src));
719 }
720
721 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
722 void MacroAssembler::movptr(Address dst, intptr_t src) {
723 mov64(rscratch1, src);
724 movq(dst, rscratch1);
725 }
726
727 // These are mostly for initializing NULL
728 void MacroAssembler::movptr(Address dst, int32_t src) {
729 movslq(dst, src);
730 }
731
732 void MacroAssembler::movptr(Register dst, int32_t src) {
733 mov64(dst, (intptr_t)src);
734 }
735
736 void MacroAssembler::pushoop(jobject obj) {
737 movoop(rscratch1, obj);
738 push(rscratch1);
739 }
740
741 void MacroAssembler::pushklass(Metadata* obj) {
742 mov_metadata(rscratch1, obj);
743 push(rscratch1);
744 }
745
746 void MacroAssembler::pushptr(AddressLiteral src) {
747 lea(rscratch1, src);
748 if (src.is_lval()) {
749 push(rscratch1);
750 } else {
751 pushq(Address(rscratch1, 0));
752 }
753 }
754
755 void MacroAssembler::reset_last_Java_frame(bool clear_fp) {
756 // we must set sp to zero to clear frame
757 movptr(Address(r15_thread, JavaThread::last_Java_sp_offset()), NULL_WORD);
758 // must clear fp, so that compiled frames are not confused; it is
759 // possible that we need it only for debugging
760 if (clear_fp) {
761 movptr(Address(r15_thread, JavaThread::last_Java_fp_offset()), NULL_WORD);
762 }
763
764 // Always clear the pc because it could have been set by make_walkable()
765 movptr(Address(r15_thread, JavaThread::last_Java_pc_offset()), NULL_WORD);
766 vzeroupper();
767 }
768
769 void MacroAssembler::set_last_Java_frame(Register last_java_sp,
770 Register last_java_fp,
771 address last_java_pc) {
772 vzeroupper();
773 // determine last_java_sp register
774 if (!last_java_sp->is_valid()) {
775 last_java_sp = rsp;
776 }
777
778 // last_java_fp is optional
779 if (last_java_fp->is_valid()) {
780 movptr(Address(r15_thread, JavaThread::last_Java_fp_offset()),
781 last_java_fp);
782 }
783
784 // last_java_pc is optional
785 if (last_java_pc != NULL) {
786 Address java_pc(r15_thread,
787 JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset());
788 lea(rscratch1, InternalAddress(last_java_pc));
789 movptr(java_pc, rscratch1);
790 }
791
792 movptr(Address(r15_thread, JavaThread::last_Java_sp_offset()), last_java_sp);
793 }
794
795 static void pass_arg0(MacroAssembler* masm, Register arg) {
796 if (c_rarg0 != arg ) {
797 masm->mov(c_rarg0, arg);
798 }
799 }
800
801 static void pass_arg1(MacroAssembler* masm, Register arg) {
802 if (c_rarg1 != arg ) {
803 masm->mov(c_rarg1, arg);
804 }
805 }
806
807 static void pass_arg2(MacroAssembler* masm, Register arg) {
808 if (c_rarg2 != arg ) {
809 masm->mov(c_rarg2, arg);
810 }
811 }
812
813 static void pass_arg3(MacroAssembler* masm, Register arg) {
814 if (c_rarg3 != arg ) {
815 masm->mov(c_rarg3, arg);
816 }
817 }
818
819 void MacroAssembler::stop(const char* msg) {
820 address rip = pc();
821 pusha(); // get regs on stack
822 lea(c_rarg0, ExternalAddress((address) msg));
823 lea(c_rarg1, InternalAddress(rip));
824 movq(c_rarg2, rsp); // pass pointer to regs array
825 andq(rsp, -16); // align stack as required by ABI
826 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug64)));
827 hlt();
828 }
829
830 void MacroAssembler::warn(const char* msg) {
831 push(rbp);
832 movq(rbp, rsp);
833 andq(rsp, -16); // align stack as required by push_CPU_state and call
834 push_CPU_state(); // keeps alignment at 16 bytes
835 lea(c_rarg0, ExternalAddress((address) msg));
836 call_VM_leaf(CAST_FROM_FN_PTR(address, warning), c_rarg0);
837 pop_CPU_state();
838 mov(rsp, rbp);
839 pop(rbp);
840 }
841
842 void MacroAssembler::print_state() {
843 address rip = pc();
844 pusha(); // get regs on stack
845 push(rbp);
846 movq(rbp, rsp);
847 andq(rsp, -16); // align stack as required by push_CPU_state and call
848 push_CPU_state(); // keeps alignment at 16 bytes
849
850 lea(c_rarg0, InternalAddress(rip));
851 lea(c_rarg1, Address(rbp, wordSize)); // pass pointer to regs array
852 call_VM_leaf(CAST_FROM_FN_PTR(address, MacroAssembler::print_state64), c_rarg0, c_rarg1);
853
854 pop_CPU_state();
855 mov(rsp, rbp);
856 pop(rbp);
857 popa();
858 }
859
860 #ifndef PRODUCT
861 extern "C" void findpc(intptr_t x);
862 #endif
863
864 void MacroAssembler::debug64(char* msg, int64_t pc, int64_t regs[]) {
865 // In order to get locks to work, we need to fake a in_VM state
866 if (ShowMessageBoxOnError) {
867 JavaThread* thread = JavaThread::current();
868 JavaThreadState saved_state = thread->thread_state();
869 thread->set_thread_state(_thread_in_vm);
870 #ifndef PRODUCT
871 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {
872 ttyLocker ttyl;
873 BytecodeCounter::print();
874 }
875 #endif
876 // To see where a verify_oop failed, get $ebx+40/X for this frame.
877 // XXX correct this offset for amd64
878 // This is the value of eip which points to where verify_oop will return.
879 if (os::message_box(msg, "Execution stopped, print registers?")) {
880 print_state64(pc, regs);
881 BREAKPOINT;
882 assert(false, "start up GDB");
883 }
884 ThreadStateTransition::transition(thread, _thread_in_vm, saved_state);
885 } else {
886 ttyLocker ttyl;
887 ::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n",
888 msg);
889 assert(false, "DEBUG MESSAGE: %s", msg);
890 }
891 }
892
893 void MacroAssembler::print_state64(int64_t pc, int64_t regs[]) {
894 ttyLocker ttyl;
895 FlagSetting fs(Debugging, true);
896 tty->print_cr("rip = 0x%016lx", pc);
897 #ifndef PRODUCT
898 tty->cr();
899 findpc(pc);
900 tty->cr();
901 #endif
902 #define PRINT_REG(rax, value) \
903 { tty->print("%s = ", #rax); os::print_location(tty, value); }
904 PRINT_REG(rax, regs[15]);
905 PRINT_REG(rbx, regs[12]);
906 PRINT_REG(rcx, regs[14]);
907 PRINT_REG(rdx, regs[13]);
908 PRINT_REG(rdi, regs[8]);
909 PRINT_REG(rsi, regs[9]);
910 PRINT_REG(rbp, regs[10]);
911 PRINT_REG(rsp, regs[11]);
912 PRINT_REG(r8 , regs[7]);
913 PRINT_REG(r9 , regs[6]);
914 PRINT_REG(r10, regs[5]);
915 PRINT_REG(r11, regs[4]);
916 PRINT_REG(r12, regs[3]);
917 PRINT_REG(r13, regs[2]);
918 PRINT_REG(r14, regs[1]);
919 PRINT_REG(r15, regs[0]);
920 #undef PRINT_REG
921 // Print some words near top of staack.
922 int64_t* rsp = (int64_t*) regs[11];
923 int64_t* dump_sp = rsp;
924 for (int col1 = 0; col1 < 8; col1++) {
925 tty->print("(rsp+0x%03x) 0x%016lx: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (int64_t)dump_sp);
926 os::print_location(tty, *dump_sp++);
927 }
928 for (int row = 0; row < 25; row++) {
929 tty->print("(rsp+0x%03x) 0x%016lx: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (int64_t)dump_sp);
930 for (int col = 0; col < 4; col++) {
931 tty->print(" 0x%016lx", *dump_sp++);
932 }
933 tty->cr();
934 }
935 // Print some instructions around pc:
936 Disassembler::decode((address)pc-64, (address)pc);
937 tty->print_cr("--------");
938 Disassembler::decode((address)pc, (address)pc+32);
939 }
940
941 #endif // _LP64
942
943 // Now versions that are common to 32/64 bit
944
945 void MacroAssembler::addptr(Register dst, int32_t imm32) {
946 LP64_ONLY(addq(dst, imm32)) NOT_LP64(addl(dst, imm32));
947 }
948
949 void MacroAssembler::addptr(Register dst, Register src) {
950 LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src));
951 }
952
953 void MacroAssembler::addptr(Address dst, Register src) {
954 LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src));
955 }
956
957 void MacroAssembler::addsd(XMMRegister dst, AddressLiteral src) {
958 if (reachable(src)) {
959 Assembler::addsd(dst, as_Address(src));
960 } else {
961 lea(rscratch1, src);
962 Assembler::addsd(dst, Address(rscratch1, 0));
963 }
964 }
965
966 void MacroAssembler::addss(XMMRegister dst, AddressLiteral src) {
967 if (reachable(src)) {
968 addss(dst, as_Address(src));
969 } else {
970 lea(rscratch1, src);
971 addss(dst, Address(rscratch1, 0));
972 }
973 }
974
975 void MacroAssembler::addpd(XMMRegister dst, AddressLiteral src) {
976 if (reachable(src)) {
977 Assembler::addpd(dst, as_Address(src));
978 } else {
979 lea(rscratch1, src);
980 Assembler::addpd(dst, Address(rscratch1, 0));
981 }
982 }
983
984 void MacroAssembler::align(int modulus) {
985 align(modulus, offset());
986 }
987
988 void MacroAssembler::align(int modulus, int target) {
989 if (target % modulus != 0) {
990 nop(modulus - (target % modulus));
991 }
992 }
993
994 void MacroAssembler::andpd(XMMRegister dst, AddressLiteral src) {
995 // Used in sign-masking with aligned address.
996 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
997 if (reachable(src)) {
998 Assembler::andpd(dst, as_Address(src));
999 } else {
1000 lea(rscratch1, src);
1001 Assembler::andpd(dst, Address(rscratch1, 0));
1002 }
1003 }
1004
1005 void MacroAssembler::andps(XMMRegister dst, AddressLiteral src) {
1006 // Used in sign-masking with aligned address.
1007 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
1008 if (reachable(src)) {
1009 Assembler::andps(dst, as_Address(src));
1010 } else {
1011 lea(rscratch1, src);
1012 Assembler::andps(dst, Address(rscratch1, 0));
1013 }
1014 }
1015
1016 void MacroAssembler::andptr(Register dst, int32_t imm32) {
1017 LP64_ONLY(andq(dst, imm32)) NOT_LP64(andl(dst, imm32));
1018 }
1019
1020 void MacroAssembler::atomic_incl(Address counter_addr) {
1021 if (os::is_MP())
1022 lock();
1023 incrementl(counter_addr);
1024 }
1025
1026 void MacroAssembler::atomic_incl(AddressLiteral counter_addr, Register scr) {
1027 if (reachable(counter_addr)) {
1028 atomic_incl(as_Address(counter_addr));
1029 } else {
1030 lea(scr, counter_addr);
1031 atomic_incl(Address(scr, 0));
1032 }
1033 }
1034
1035 #ifdef _LP64
1036 void MacroAssembler::atomic_incq(Address counter_addr) {
1037 if (os::is_MP())
1038 lock();
1039 incrementq(counter_addr);
1040 }
1041
1042 void MacroAssembler::atomic_incq(AddressLiteral counter_addr, Register scr) {
1043 if (reachable(counter_addr)) {
1044 atomic_incq(as_Address(counter_addr));
1045 } else {
1046 lea(scr, counter_addr);
1047 atomic_incq(Address(scr, 0));
1048 }
1049 }
1050 #endif
1051
1052 // Writes to stack successive pages until offset reached to check for
1053 // stack overflow + shadow pages. This clobbers tmp.
1054 void MacroAssembler::bang_stack_size(Register size, Register tmp) {
1055 movptr(tmp, rsp);
1056 // Bang stack for total size given plus shadow page size.
1057 // Bang one page at a time because large size can bang beyond yellow and
1058 // red zones.
1059 Label loop;
1060 bind(loop);
1061 movl(Address(tmp, (-os::vm_page_size())), size );
1062 subptr(tmp, os::vm_page_size());
1063 subl(size, os::vm_page_size());
1064 jcc(Assembler::greater, loop);
1065
1066 // Bang down shadow pages too.
1067 // At this point, (tmp-0) is the last address touched, so don't
1068 // touch it again. (It was touched as (tmp-pagesize) but then tmp
1069 // was post-decremented.) Skip this address by starting at i=1, and
1070 // touch a few more pages below. N.B. It is important to touch all
1071 // the way down including all pages in the shadow zone.
1072 for (int i = 1; i < ((int)JavaThread::stack_shadow_zone_size() / os::vm_page_size()); i++) {
1073 // this could be any sized move but this is can be a debugging crumb
1074 // so the bigger the better.
1075 movptr(Address(tmp, (-i*os::vm_page_size())), size );
1076 }
1077 }
1078
1079 void MacroAssembler::reserved_stack_check() {
1080 // testing if reserved zone needs to be enabled
1081 Label no_reserved_zone_enabling;
1082 Register thread = NOT_LP64(rsi) LP64_ONLY(r15_thread);
1083 NOT_LP64(get_thread(rsi);)
1084
1085 cmpptr(rsp, Address(thread, JavaThread::reserved_stack_activation_offset()));
1086 jcc(Assembler::below, no_reserved_zone_enabling);
1087
1088 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::enable_stack_reserved_zone), thread);
1089 jump(RuntimeAddress(StubRoutines::throw_delayed_StackOverflowError_entry()));
1090 should_not_reach_here();
1091
1092 bind(no_reserved_zone_enabling);
1093 }
1094
1095 int MacroAssembler::biased_locking_enter(Register lock_reg,
1096 Register obj_reg,
1097 Register swap_reg,
1098 Register tmp_reg,
1099 bool swap_reg_contains_mark,
1100 Label& done,
1101 Label* slow_case,
1102 BiasedLockingCounters* counters) {
1103 assert(UseBiasedLocking, "why call this otherwise?");
1104 assert(swap_reg == rax, "swap_reg must be rax for cmpxchgq");
1105 assert(tmp_reg != noreg, "tmp_reg must be supplied");
1106 assert_different_registers(lock_reg, obj_reg, swap_reg, tmp_reg);
1107 assert(markOopDesc::age_shift == markOopDesc::lock_bits + markOopDesc::biased_lock_bits, "biased locking makes assumptions about bit layout");
1108 Address mark_addr (obj_reg, oopDesc::mark_offset_in_bytes());
1109 NOT_LP64( Address saved_mark_addr(lock_reg, 0); )
1110
1111 if (PrintBiasedLockingStatistics && counters == NULL) {
1112 counters = BiasedLocking::counters();
1113 }
1114 // Biased locking
1115 // See whether the lock is currently biased toward our thread and
1116 // whether the epoch is still valid
1117 // Note that the runtime guarantees sufficient alignment of JavaThread
1118 // pointers to allow age to be placed into low bits
1119 // First check to see whether biasing is even enabled for this object
1120 Label cas_label;
1121 int null_check_offset = -1;
1122 if (!swap_reg_contains_mark) {
1123 null_check_offset = offset();
1124 movptr(swap_reg, mark_addr);
1125 }
1126 movptr(tmp_reg, swap_reg);
1127 andptr(tmp_reg, markOopDesc::biased_lock_mask_in_place);
1128 cmpptr(tmp_reg, markOopDesc::biased_lock_pattern);
1129 jcc(Assembler::notEqual, cas_label);
1130 // The bias pattern is present in the object's header. Need to check
1131 // whether the bias owner and the epoch are both still current.
1132 #ifndef _LP64
1133 // Note that because there is no current thread register on x86_32 we
1134 // need to store off the mark word we read out of the object to
1135 // avoid reloading it and needing to recheck invariants below. This
1136 // store is unfortunate but it makes the overall code shorter and
1137 // simpler.
1138 movptr(saved_mark_addr, swap_reg);
1139 #endif
1140 if (swap_reg_contains_mark) {
1141 null_check_offset = offset();
1142 }
1143 load_prototype_header(tmp_reg, obj_reg);
1144 #ifdef _LP64
1145 orptr(tmp_reg, r15_thread);
1146 xorptr(tmp_reg, swap_reg);
1147 Register header_reg = tmp_reg;
1148 #else
1149 xorptr(tmp_reg, swap_reg);
1150 get_thread(swap_reg);
1151 xorptr(swap_reg, tmp_reg);
1152 Register header_reg = swap_reg;
1153 #endif
1154 andptr(header_reg, ~((int) markOopDesc::age_mask_in_place));
1155 if (counters != NULL) {
1156 cond_inc32(Assembler::zero,
1157 ExternalAddress((address) counters->biased_lock_entry_count_addr()));
1158 }
1159 jcc(Assembler::equal, done);
1160
1161 Label try_revoke_bias;
1162 Label try_rebias;
1163
1164 // At this point we know that the header has the bias pattern and
1165 // that we are not the bias owner in the current epoch. We need to
1166 // figure out more details about the state of the header in order to
1167 // know what operations can be legally performed on the object's
1168 // header.
1169
1170 // If the low three bits in the xor result aren't clear, that means
1171 // the prototype header is no longer biased and we have to revoke
1172 // the bias on this object.
1173 testptr(header_reg, markOopDesc::biased_lock_mask_in_place);
1174 jccb(Assembler::notZero, try_revoke_bias);
1175
1176 // Biasing is still enabled for this data type. See whether the
1177 // epoch of the current bias is still valid, meaning that the epoch
1178 // bits of the mark word are equal to the epoch bits of the
1179 // prototype header. (Note that the prototype header's epoch bits
1180 // only change at a safepoint.) If not, attempt to rebias the object
1181 // toward the current thread. Note that we must be absolutely sure
1182 // that the current epoch is invalid in order to do this because
1183 // otherwise the manipulations it performs on the mark word are
1184 // illegal.
1185 testptr(header_reg, markOopDesc::epoch_mask_in_place);
1186 jccb(Assembler::notZero, try_rebias);
1187
1188 // The epoch of the current bias is still valid but we know nothing
1189 // about the owner; it might be set or it might be clear. Try to
1190 // acquire the bias of the object using an atomic operation. If this
1191 // fails we will go in to the runtime to revoke the object's bias.
1192 // Note that we first construct the presumed unbiased header so we
1193 // don't accidentally blow away another thread's valid bias.
1194 NOT_LP64( movptr(swap_reg, saved_mark_addr); )
1195 andptr(swap_reg,
1196 markOopDesc::biased_lock_mask_in_place | markOopDesc::age_mask_in_place | markOopDesc::epoch_mask_in_place);
1197 #ifdef _LP64
1198 movptr(tmp_reg, swap_reg);
1199 orptr(tmp_reg, r15_thread);
1200 #else
1201 get_thread(tmp_reg);
1202 orptr(tmp_reg, swap_reg);
1203 #endif
1204 if (os::is_MP()) {
1205 lock();
1206 }
1207 cmpxchgptr(tmp_reg, mark_addr); // compare tmp_reg and swap_reg
1208 // If the biasing toward our thread failed, this means that
1209 // another thread succeeded in biasing it toward itself and we
1210 // need to revoke that bias. The revocation will occur in the
1211 // interpreter runtime in the slow case.
1212 if (counters != NULL) {
1213 cond_inc32(Assembler::zero,
1214 ExternalAddress((address) counters->anonymously_biased_lock_entry_count_addr()));
1215 }
1216 if (slow_case != NULL) {
1217 jcc(Assembler::notZero, *slow_case);
1218 }
1219 jmp(done);
1220
1221 bind(try_rebias);
1222 // At this point we know the epoch has expired, meaning that the
1223 // current "bias owner", if any, is actually invalid. Under these
1224 // circumstances _only_, we are allowed to use the current header's
1225 // value as the comparison value when doing the cas to acquire the
1226 // bias in the current epoch. In other words, we allow transfer of
1227 // the bias from one thread to another directly in this situation.
1228 //
1229 // FIXME: due to a lack of registers we currently blow away the age
1230 // bits in this situation. Should attempt to preserve them.
1231 load_prototype_header(tmp_reg, obj_reg);
1232 #ifdef _LP64
1233 orptr(tmp_reg, r15_thread);
1234 #else
1235 get_thread(swap_reg);
1236 orptr(tmp_reg, swap_reg);
1237 movptr(swap_reg, saved_mark_addr);
1238 #endif
1239 if (os::is_MP()) {
1240 lock();
1241 }
1242 cmpxchgptr(tmp_reg, mark_addr); // compare tmp_reg and swap_reg
1243 // If the biasing toward our thread failed, then another thread
1244 // succeeded in biasing it toward itself and we need to revoke that
1245 // bias. The revocation will occur in the runtime in the slow case.
1246 if (counters != NULL) {
1247 cond_inc32(Assembler::zero,
1248 ExternalAddress((address) counters->rebiased_lock_entry_count_addr()));
1249 }
1250 if (slow_case != NULL) {
1251 jcc(Assembler::notZero, *slow_case);
1252 }
1253 jmp(done);
1254
1255 bind(try_revoke_bias);
1256 // The prototype mark in the klass doesn't have the bias bit set any
1257 // more, indicating that objects of this data type are not supposed
1258 // to be biased any more. We are going to try to reset the mark of
1259 // this object to the prototype value and fall through to the
1260 // CAS-based locking scheme. Note that if our CAS fails, it means
1261 // that another thread raced us for the privilege of revoking the
1262 // bias of this particular object, so it's okay to continue in the
1263 // normal locking code.
1264 //
1265 // FIXME: due to a lack of registers we currently blow away the age
1266 // bits in this situation. Should attempt to preserve them.
1267 NOT_LP64( movptr(swap_reg, saved_mark_addr); )
1268 load_prototype_header(tmp_reg, obj_reg);
1269 if (os::is_MP()) {
1270 lock();
1271 }
1272 cmpxchgptr(tmp_reg, mark_addr); // compare tmp_reg and swap_reg
1273 // Fall through to the normal CAS-based lock, because no matter what
1274 // the result of the above CAS, some thread must have succeeded in
1275 // removing the bias bit from the object's header.
1276 if (counters != NULL) {
1277 cond_inc32(Assembler::zero,
1278 ExternalAddress((address) counters->revoked_lock_entry_count_addr()));
1279 }
1280
1281 bind(cas_label);
1282
1283 return null_check_offset;
1284 }
1285
1286 void MacroAssembler::biased_locking_exit(Register obj_reg, Register temp_reg, Label& done) {
1287 assert(UseBiasedLocking, "why call this otherwise?");
1288
1289 // Check for biased locking unlock case, which is a no-op
1290 // Note: we do not have to check the thread ID for two reasons.
1291 // First, the interpreter checks for IllegalMonitorStateException at
1292 // a higher level. Second, if the bias was revoked while we held the
1293 // lock, the object could not be rebiased toward another thread, so
1294 // the bias bit would be clear.
1295 movptr(temp_reg, Address(obj_reg, oopDesc::mark_offset_in_bytes()));
1296 andptr(temp_reg, markOopDesc::biased_lock_mask_in_place);
1297 cmpptr(temp_reg, markOopDesc::biased_lock_pattern);
1298 jcc(Assembler::equal, done);
1299 }
1300
1301 #ifdef COMPILER2
1302
1303 #if INCLUDE_RTM_OPT
1304
1305 // Update rtm_counters based on abort status
1306 // input: abort_status
1307 // rtm_counters (RTMLockingCounters*)
1308 // flags are killed
1309 void MacroAssembler::rtm_counters_update(Register abort_status, Register rtm_counters) {
1310
1311 atomic_incptr(Address(rtm_counters, RTMLockingCounters::abort_count_offset()));
1312 if (PrintPreciseRTMLockingStatistics) {
1313 for (int i = 0; i < RTMLockingCounters::ABORT_STATUS_LIMIT; i++) {
1314 Label check_abort;
1315 testl(abort_status, (1<<i));
1316 jccb(Assembler::equal, check_abort);
1317 atomic_incptr(Address(rtm_counters, RTMLockingCounters::abortX_count_offset() + (i * sizeof(uintx))));
1318 bind(check_abort);
1319 }
1320 }
1321 }
1322
1323 // Branch if (random & (count-1) != 0), count is 2^n
1324 // tmp, scr and flags are killed
1325 void MacroAssembler::branch_on_random_using_rdtsc(Register tmp, Register scr, int count, Label& brLabel) {
1326 assert(tmp == rax, "");
1327 assert(scr == rdx, "");
1328 rdtsc(); // modifies EDX:EAX
1329 andptr(tmp, count-1);
1330 jccb(Assembler::notZero, brLabel);
1331 }
1332
1333 // Perform abort ratio calculation, set no_rtm bit if high ratio
1334 // input: rtm_counters_Reg (RTMLockingCounters* address)
1335 // tmpReg, rtm_counters_Reg and flags are killed
1336 void MacroAssembler::rtm_abort_ratio_calculation(Register tmpReg,
1337 Register rtm_counters_Reg,
1338 RTMLockingCounters* rtm_counters,
1339 Metadata* method_data) {
1340 Label L_done, L_check_always_rtm1, L_check_always_rtm2;
1341
1342 if (RTMLockingCalculationDelay > 0) {
1343 // Delay calculation
1344 movptr(tmpReg, ExternalAddress((address) RTMLockingCounters::rtm_calculation_flag_addr()), tmpReg);
1345 testptr(tmpReg, tmpReg);
1346 jccb(Assembler::equal, L_done);
1347 }
1348 // Abort ratio calculation only if abort_count > RTMAbortThreshold
1349 // Aborted transactions = abort_count * 100
1350 // All transactions = total_count * RTMTotalCountIncrRate
1351 // Set no_rtm bit if (Aborted transactions >= All transactions * RTMAbortRatio)
1352
1353 movptr(tmpReg, Address(rtm_counters_Reg, RTMLockingCounters::abort_count_offset()));
1354 cmpptr(tmpReg, RTMAbortThreshold);
1355 jccb(Assembler::below, L_check_always_rtm2);
1356 imulptr(tmpReg, tmpReg, 100);
1357
1358 Register scrReg = rtm_counters_Reg;
1359 movptr(scrReg, Address(rtm_counters_Reg, RTMLockingCounters::total_count_offset()));
1360 imulptr(scrReg, scrReg, RTMTotalCountIncrRate);
1361 imulptr(scrReg, scrReg, RTMAbortRatio);
1362 cmpptr(tmpReg, scrReg);
1363 jccb(Assembler::below, L_check_always_rtm1);
1364 if (method_data != NULL) {
1365 // set rtm_state to "no rtm" in MDO
1366 mov_metadata(tmpReg, method_data);
1367 if (os::is_MP()) {
1368 lock();
1369 }
1370 orl(Address(tmpReg, MethodData::rtm_state_offset_in_bytes()), NoRTM);
1371 }
1372 jmpb(L_done);
1373 bind(L_check_always_rtm1);
1374 // Reload RTMLockingCounters* address
1375 lea(rtm_counters_Reg, ExternalAddress((address)rtm_counters));
1376 bind(L_check_always_rtm2);
1377 movptr(tmpReg, Address(rtm_counters_Reg, RTMLockingCounters::total_count_offset()));
1378 cmpptr(tmpReg, RTMLockingThreshold / RTMTotalCountIncrRate);
1379 jccb(Assembler::below, L_done);
1380 if (method_data != NULL) {
1381 // set rtm_state to "always rtm" in MDO
1382 mov_metadata(tmpReg, method_data);
1383 if (os::is_MP()) {
1384 lock();
1385 }
1386 orl(Address(tmpReg, MethodData::rtm_state_offset_in_bytes()), UseRTM);
1387 }
1388 bind(L_done);
1389 }
1390
1391 // Update counters and perform abort ratio calculation
1392 // input: abort_status_Reg
1393 // rtm_counters_Reg, flags are killed
1394 void MacroAssembler::rtm_profiling(Register abort_status_Reg,
1395 Register rtm_counters_Reg,
1396 RTMLockingCounters* rtm_counters,
1397 Metadata* method_data,
1398 bool profile_rtm) {
1399
1400 assert(rtm_counters != NULL, "should not be NULL when profiling RTM");
1401 // update rtm counters based on rax value at abort
1402 // reads abort_status_Reg, updates flags
1403 lea(rtm_counters_Reg, ExternalAddress((address)rtm_counters));
1404 rtm_counters_update(abort_status_Reg, rtm_counters_Reg);
1405 if (profile_rtm) {
1406 // Save abort status because abort_status_Reg is used by following code.
1407 if (RTMRetryCount > 0) {
1408 push(abort_status_Reg);
1409 }
1410 assert(rtm_counters != NULL, "should not be NULL when profiling RTM");
1411 rtm_abort_ratio_calculation(abort_status_Reg, rtm_counters_Reg, rtm_counters, method_data);
1412 // restore abort status
1413 if (RTMRetryCount > 0) {
1414 pop(abort_status_Reg);
1415 }
1416 }
1417 }
1418
1419 // Retry on abort if abort's status is 0x6: can retry (0x2) | memory conflict (0x4)
1420 // inputs: retry_count_Reg
1421 // : abort_status_Reg
1422 // output: retry_count_Reg decremented by 1
1423 // flags are killed
1424 void MacroAssembler::rtm_retry_lock_on_abort(Register retry_count_Reg, Register abort_status_Reg, Label& retryLabel) {
1425 Label doneRetry;
1426 assert(abort_status_Reg == rax, "");
1427 // The abort reason bits are in eax (see all states in rtmLocking.hpp)
1428 // 0x6 = conflict on which we can retry (0x2) | memory conflict (0x4)
1429 // if reason is in 0x6 and retry count != 0 then retry
1430 andptr(abort_status_Reg, 0x6);
1431 jccb(Assembler::zero, doneRetry);
1432 testl(retry_count_Reg, retry_count_Reg);
1433 jccb(Assembler::zero, doneRetry);
1434 pause();
1435 decrementl(retry_count_Reg);
1436 jmp(retryLabel);
1437 bind(doneRetry);
1438 }
1439
1440 // Spin and retry if lock is busy,
1441 // inputs: box_Reg (monitor address)
1442 // : retry_count_Reg
1443 // output: retry_count_Reg decremented by 1
1444 // : clear z flag if retry count exceeded
1445 // tmp_Reg, scr_Reg, flags are killed
1446 void MacroAssembler::rtm_retry_lock_on_busy(Register retry_count_Reg, Register box_Reg,
1447 Register tmp_Reg, Register scr_Reg, Label& retryLabel) {
1448 Label SpinLoop, SpinExit, doneRetry;
1449 int owner_offset = OM_OFFSET_NO_MONITOR_VALUE_TAG(owner);
1450
1451 testl(retry_count_Reg, retry_count_Reg);
1452 jccb(Assembler::zero, doneRetry);
1453 decrementl(retry_count_Reg);
1454 movptr(scr_Reg, RTMSpinLoopCount);
1455
1456 bind(SpinLoop);
1457 pause();
1458 decrementl(scr_Reg);
1459 jccb(Assembler::lessEqual, SpinExit);
1460 movptr(tmp_Reg, Address(box_Reg, owner_offset));
1461 testptr(tmp_Reg, tmp_Reg);
1462 jccb(Assembler::notZero, SpinLoop);
1463
1464 bind(SpinExit);
1465 jmp(retryLabel);
1466 bind(doneRetry);
1467 incrementl(retry_count_Reg); // clear z flag
1468 }
1469
1470 // Use RTM for normal stack locks
1471 // Input: objReg (object to lock)
1472 void MacroAssembler::rtm_stack_locking(Register objReg, Register tmpReg, Register scrReg,
1473 Register retry_on_abort_count_Reg,
1474 RTMLockingCounters* stack_rtm_counters,
1475 Metadata* method_data, bool profile_rtm,
1476 Label& DONE_LABEL, Label& IsInflated) {
1477 assert(UseRTMForStackLocks, "why call this otherwise?");
1478 assert(!UseBiasedLocking, "Biased locking is not supported with RTM locking");
1479 assert(tmpReg == rax, "");
1480 assert(scrReg == rdx, "");
1481 Label L_rtm_retry, L_decrement_retry, L_on_abort;
1482
1483 if (RTMRetryCount > 0) {
1484 movl(retry_on_abort_count_Reg, RTMRetryCount); // Retry on abort
1485 bind(L_rtm_retry);
1486 }
1487 movptr(tmpReg, Address(objReg, oopDesc::mark_offset_in_bytes()));
1488 testptr(tmpReg, markOopDesc::monitor_value); // inflated vs stack-locked|neutral|biased
1489 jcc(Assembler::notZero, IsInflated);
1490
1491 if (PrintPreciseRTMLockingStatistics || profile_rtm) {
1492 Label L_noincrement;
1493 if (RTMTotalCountIncrRate > 1) {
1494 // tmpReg, scrReg and flags are killed
1495 branch_on_random_using_rdtsc(tmpReg, scrReg, (int)RTMTotalCountIncrRate, L_noincrement);
1496 }
1497 assert(stack_rtm_counters != NULL, "should not be NULL when profiling RTM");
1498 atomic_incptr(ExternalAddress((address)stack_rtm_counters->total_count_addr()), scrReg);
1499 bind(L_noincrement);
1500 }
1501 xbegin(L_on_abort);
1502 movptr(tmpReg, Address(objReg, oopDesc::mark_offset_in_bytes())); // fetch markword
1503 andptr(tmpReg, markOopDesc::biased_lock_mask_in_place); // look at 3 lock bits
1504 cmpptr(tmpReg, markOopDesc::unlocked_value); // bits = 001 unlocked
1505 jcc(Assembler::equal, DONE_LABEL); // all done if unlocked
1506
1507 Register abort_status_Reg = tmpReg; // status of abort is stored in RAX
1508 if (UseRTMXendForLockBusy) {
1509 xend();
1510 movptr(abort_status_Reg, 0x2); // Set the abort status to 2 (so we can retry)
1511 jmp(L_decrement_retry);
1512 }
1513 else {
1514 xabort(0);
1515 }
1516 bind(L_on_abort);
1517 if (PrintPreciseRTMLockingStatistics || profile_rtm) {
1518 rtm_profiling(abort_status_Reg, scrReg, stack_rtm_counters, method_data, profile_rtm);
1519 }
1520 bind(L_decrement_retry);
1521 if (RTMRetryCount > 0) {
1522 // retry on lock abort if abort status is 'can retry' (0x2) or 'memory conflict' (0x4)
1523 rtm_retry_lock_on_abort(retry_on_abort_count_Reg, abort_status_Reg, L_rtm_retry);
1524 }
1525 }
1526
1527 // Use RTM for inflating locks
1528 // inputs: objReg (object to lock)
1529 // boxReg (on-stack box address (displaced header location) - KILLED)
1530 // tmpReg (ObjectMonitor address + markOopDesc::monitor_value)
1531 void MacroAssembler::rtm_inflated_locking(Register objReg, Register boxReg, Register tmpReg,
1532 Register scrReg, Register retry_on_busy_count_Reg,
1533 Register retry_on_abort_count_Reg,
1534 RTMLockingCounters* rtm_counters,
1535 Metadata* method_data, bool profile_rtm,
1536 Label& DONE_LABEL) {
1537 assert(UseRTMLocking, "why call this otherwise?");
1538 assert(tmpReg == rax, "");
1539 assert(scrReg == rdx, "");
1540 Label L_rtm_retry, L_decrement_retry, L_on_abort;
1541 int owner_offset = OM_OFFSET_NO_MONITOR_VALUE_TAG(owner);
1542
1543 // Without cast to int32_t a movptr will destroy r10 which is typically obj
1544 movptr(Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark()));
1545 movptr(boxReg, tmpReg); // Save ObjectMonitor address
1546
1547 if (RTMRetryCount > 0) {
1548 movl(retry_on_busy_count_Reg, RTMRetryCount); // Retry on lock busy
1549 movl(retry_on_abort_count_Reg, RTMRetryCount); // Retry on abort
1550 bind(L_rtm_retry);
1551 }
1552 if (PrintPreciseRTMLockingStatistics || profile_rtm) {
1553 Label L_noincrement;
1554 if (RTMTotalCountIncrRate > 1) {
1555 // tmpReg, scrReg and flags are killed
1556 branch_on_random_using_rdtsc(tmpReg, scrReg, (int)RTMTotalCountIncrRate, L_noincrement);
1557 }
1558 assert(rtm_counters != NULL, "should not be NULL when profiling RTM");
1559 atomic_incptr(ExternalAddress((address)rtm_counters->total_count_addr()), scrReg);
1560 bind(L_noincrement);
1561 }
1562 xbegin(L_on_abort);
1563 movptr(tmpReg, Address(objReg, oopDesc::mark_offset_in_bytes()));
1564 movptr(tmpReg, Address(tmpReg, owner_offset));
1565 testptr(tmpReg, tmpReg);
1566 jcc(Assembler::zero, DONE_LABEL);
1567 if (UseRTMXendForLockBusy) {
1568 xend();
1569 jmp(L_decrement_retry);
1570 }
1571 else {
1572 xabort(0);
1573 }
1574 bind(L_on_abort);
1575 Register abort_status_Reg = tmpReg; // status of abort is stored in RAX
1576 if (PrintPreciseRTMLockingStatistics || profile_rtm) {
1577 rtm_profiling(abort_status_Reg, scrReg, rtm_counters, method_data, profile_rtm);
1578 }
1579 if (RTMRetryCount > 0) {
1580 // retry on lock abort if abort status is 'can retry' (0x2) or 'memory conflict' (0x4)
1581 rtm_retry_lock_on_abort(retry_on_abort_count_Reg, abort_status_Reg, L_rtm_retry);
1582 }
1583
1584 movptr(tmpReg, Address(boxReg, owner_offset)) ;
1585 testptr(tmpReg, tmpReg) ;
1586 jccb(Assembler::notZero, L_decrement_retry) ;
1587
1588 // Appears unlocked - try to swing _owner from null to non-null.
1589 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand.
1590 #ifdef _LP64
1591 Register threadReg = r15_thread;
1592 #else
1593 get_thread(scrReg);
1594 Register threadReg = scrReg;
1595 #endif
1596 if (os::is_MP()) {
1597 lock();
1598 }
1599 cmpxchgptr(threadReg, Address(boxReg, owner_offset)); // Updates tmpReg
1600
1601 if (RTMRetryCount > 0) {
1602 // success done else retry
1603 jccb(Assembler::equal, DONE_LABEL) ;
1604 bind(L_decrement_retry);
1605 // Spin and retry if lock is busy.
1606 rtm_retry_lock_on_busy(retry_on_busy_count_Reg, boxReg, tmpReg, scrReg, L_rtm_retry);
1607 }
1608 else {
1609 bind(L_decrement_retry);
1610 }
1611 }
1612
1613 #endif // INCLUDE_RTM_OPT
1614
1615 // Fast_Lock and Fast_Unlock used by C2
1616
1617 // Because the transitions from emitted code to the runtime
1618 // monitorenter/exit helper stubs are so slow it's critical that
1619 // we inline both the stack-locking fast-path and the inflated fast path.
1620 //
1621 // See also: cmpFastLock and cmpFastUnlock.
1622 //
1623 // What follows is a specialized inline transliteration of the code
1624 // in slow_enter() and slow_exit(). If we're concerned about I$ bloat
1625 // another option would be to emit TrySlowEnter and TrySlowExit methods
1626 // at startup-time. These methods would accept arguments as
1627 // (rax,=Obj, rbx=Self, rcx=box, rdx=Scratch) and return success-failure
1628 // indications in the icc.ZFlag. Fast_Lock and Fast_Unlock would simply
1629 // marshal the arguments and emit calls to TrySlowEnter and TrySlowExit.
1630 // In practice, however, the # of lock sites is bounded and is usually small.
1631 // Besides the call overhead, TrySlowEnter and TrySlowExit might suffer
1632 // if the processor uses simple bimodal branch predictors keyed by EIP
1633 // Since the helper routines would be called from multiple synchronization
1634 // sites.
1635 //
1636 // An even better approach would be write "MonitorEnter()" and "MonitorExit()"
1637 // in java - using j.u.c and unsafe - and just bind the lock and unlock sites
1638 // to those specialized methods. That'd give us a mostly platform-independent
1639 // implementation that the JITs could optimize and inline at their pleasure.
1640 // Done correctly, the only time we'd need to cross to native could would be
1641 // to park() or unpark() threads. We'd also need a few more unsafe operators
1642 // to (a) prevent compiler-JIT reordering of non-volatile accesses, and
1643 // (b) explicit barriers or fence operations.
1644 //
1645 // TODO:
1646 //
1647 // * Arrange for C2 to pass "Self" into Fast_Lock and Fast_Unlock in one of the registers (scr).
1648 // This avoids manifesting the Self pointer in the Fast_Lock and Fast_Unlock terminals.
1649 // Given TLAB allocation, Self is usually manifested in a register, so passing it into
1650 // the lock operators would typically be faster than reifying Self.
1651 //
1652 // * Ideally I'd define the primitives as:
1653 // fast_lock (nax Obj, nax box, EAX tmp, nax scr) where box, tmp and scr are KILLED.
1654 // fast_unlock (nax Obj, EAX box, nax tmp) where box and tmp are KILLED
1655 // Unfortunately ADLC bugs prevent us from expressing the ideal form.
1656 // Instead, we're stuck with a rather awkward and brittle register assignments below.
1657 // Furthermore the register assignments are overconstrained, possibly resulting in
1658 // sub-optimal code near the synchronization site.
1659 //
1660 // * Eliminate the sp-proximity tests and just use "== Self" tests instead.
1661 // Alternately, use a better sp-proximity test.
1662 //
1663 // * Currently ObjectMonitor._Owner can hold either an sp value or a (THREAD *) value.
1664 // Either one is sufficient to uniquely identify a thread.
1665 // TODO: eliminate use of sp in _owner and use get_thread(tr) instead.
1666 //
1667 // * Intrinsify notify() and notifyAll() for the common cases where the
1668 // object is locked by the calling thread but the waitlist is empty.
1669 // avoid the expensive JNI call to JVM_Notify() and JVM_NotifyAll().
1670 //
1671 // * use jccb and jmpb instead of jcc and jmp to improve code density.
1672 // But beware of excessive branch density on AMD Opterons.
1673 //
1674 // * Both Fast_Lock and Fast_Unlock set the ICC.ZF to indicate success
1675 // or failure of the fast-path. If the fast-path fails then we pass
1676 // control to the slow-path, typically in C. In Fast_Lock and
1677 // Fast_Unlock we often branch to DONE_LABEL, just to find that C2
1678 // will emit a conditional branch immediately after the node.
1679 // So we have branches to branches and lots of ICC.ZF games.
1680 // Instead, it might be better to have C2 pass a "FailureLabel"
1681 // into Fast_Lock and Fast_Unlock. In the case of success, control
1682 // will drop through the node. ICC.ZF is undefined at exit.
1683 // In the case of failure, the node will branch directly to the
1684 // FailureLabel
1685
1686
1687 // obj: object to lock
1688 // box: on-stack box address (displaced header location) - KILLED
1689 // rax,: tmp -- KILLED
1690 // scr: tmp -- KILLED
1691 void MacroAssembler::fast_lock(Register objReg, Register boxReg, Register tmpReg,
1692 Register scrReg, Register cx1Reg, Register cx2Reg,
1693 BiasedLockingCounters* counters,
1694 RTMLockingCounters* rtm_counters,
1695 RTMLockingCounters* stack_rtm_counters,
1696 Metadata* method_data,
1697 bool use_rtm, bool profile_rtm) {
1698 // Ensure the register assignments are disjoint
1699 assert(tmpReg == rax, "");
1700
1701 if (use_rtm) {
1702 assert_different_registers(objReg, boxReg, tmpReg, scrReg, cx1Reg, cx2Reg);
1703 } else {
1704 assert(cx1Reg == noreg, "");
1705 assert(cx2Reg == noreg, "");
1706 assert_different_registers(objReg, boxReg, tmpReg, scrReg);
1707 }
1708
1709 if (counters != NULL) {
1710 atomic_incl(ExternalAddress((address)counters->total_entry_count_addr()), scrReg);
1711 }
1712 if (EmitSync & 1) {
1713 // set box->dhw = markOopDesc::unused_mark()
1714 // Force all sync thru slow-path: slow_enter() and slow_exit()
1715 movptr (Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark()));
1716 cmpptr (rsp, (int32_t)NULL_WORD);
1717 } else {
1718 // Possible cases that we'll encounter in fast_lock
1719 // ------------------------------------------------
1720 // * Inflated
1721 // -- unlocked
1722 // -- Locked
1723 // = by self
1724 // = by other
1725 // * biased
1726 // -- by Self
1727 // -- by other
1728 // * neutral
1729 // * stack-locked
1730 // -- by self
1731 // = sp-proximity test hits
1732 // = sp-proximity test generates false-negative
1733 // -- by other
1734 //
1735
1736 Label IsInflated, DONE_LABEL;
1737
1738 // it's stack-locked, biased or neutral
1739 // TODO: optimize away redundant LDs of obj->mark and improve the markword triage
1740 // order to reduce the number of conditional branches in the most common cases.
1741 // Beware -- there's a subtle invariant that fetch of the markword
1742 // at [FETCH], below, will never observe a biased encoding (*101b).
1743 // If this invariant is not held we risk exclusion (safety) failure.
1744 if (UseBiasedLocking && !UseOptoBiasInlining) {
1745 biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, counters);
1746 }
1747
1748 #if INCLUDE_RTM_OPT
1749 if (UseRTMForStackLocks && use_rtm) {
1750 rtm_stack_locking(objReg, tmpReg, scrReg, cx2Reg,
1751 stack_rtm_counters, method_data, profile_rtm,
1752 DONE_LABEL, IsInflated);
1753 }
1754 #endif // INCLUDE_RTM_OPT
1755
1756 movptr(tmpReg, Address(objReg, oopDesc::mark_offset_in_bytes())); // [FETCH]
1757 testptr(tmpReg, markOopDesc::monitor_value); // inflated vs stack-locked|neutral|biased
1758 jccb(Assembler::notZero, IsInflated);
1759
1760 // Attempt stack-locking ...
1761 orptr (tmpReg, markOopDesc::unlocked_value);
1762 movptr(Address(boxReg, 0), tmpReg); // Anticipate successful CAS
1763 if (os::is_MP()) {
1764 lock();
1765 }
1766 cmpxchgptr(boxReg, Address(objReg, oopDesc::mark_offset_in_bytes())); // Updates tmpReg
1767 if (counters != NULL) {
1768 cond_inc32(Assembler::equal,
1769 ExternalAddress((address)counters->fast_path_entry_count_addr()));
1770 }
1771 jcc(Assembler::equal, DONE_LABEL); // Success
1772
1773 // Recursive locking.
1774 // The object is stack-locked: markword contains stack pointer to BasicLock.
1775 // Locked by current thread if difference with current SP is less than one page.
1776 subptr(tmpReg, rsp);
1777 // Next instruction set ZFlag == 1 (Success) if difference is less then one page.
1778 andptr(tmpReg, (int32_t) (NOT_LP64(0xFFFFF003) LP64_ONLY(7 - os::vm_page_size())) );
1779 movptr(Address(boxReg, 0), tmpReg);
1780 if (counters != NULL) {
1781 cond_inc32(Assembler::equal,
1782 ExternalAddress((address)counters->fast_path_entry_count_addr()));
1783 }
1784 jmp(DONE_LABEL);
1785
1786 bind(IsInflated);
1787 // The object is inflated. tmpReg contains pointer to ObjectMonitor* + markOopDesc::monitor_value
1788
1789 #if INCLUDE_RTM_OPT
1790 // Use the same RTM locking code in 32- and 64-bit VM.
1791 if (use_rtm) {
1792 rtm_inflated_locking(objReg, boxReg, tmpReg, scrReg, cx1Reg, cx2Reg,
1793 rtm_counters, method_data, profile_rtm, DONE_LABEL);
1794 } else {
1795 #endif // INCLUDE_RTM_OPT
1796
1797 #ifndef _LP64
1798 // The object is inflated.
1799
1800 // boxReg refers to the on-stack BasicLock in the current frame.
1801 // We'd like to write:
1802 // set box->_displaced_header = markOopDesc::unused_mark(). Any non-0 value suffices.
1803 // This is convenient but results a ST-before-CAS penalty. The following CAS suffers
1804 // additional latency as we have another ST in the store buffer that must drain.
1805
1806 if (EmitSync & 8192) {
1807 movptr(Address(boxReg, 0), 3); // results in ST-before-CAS penalty
1808 get_thread (scrReg);
1809 movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2]
1810 movptr(tmpReg, NULL_WORD); // consider: xor vs mov
1811 if (os::is_MP()) {
1812 lock();
1813 }
1814 cmpxchgptr(scrReg, Address(boxReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
1815 } else
1816 if ((EmitSync & 128) == 0) { // avoid ST-before-CAS
1817 // register juggle because we need tmpReg for cmpxchgptr below
1818 movptr(scrReg, boxReg);
1819 movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2]
1820
1821 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes
1822 if ((EmitSync & 2048) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) {
1823 // prefetchw [eax + Offset(_owner)-2]
1824 prefetchw(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
1825 }
1826
1827 if ((EmitSync & 64) == 0) {
1828 // Optimistic form: consider XORL tmpReg,tmpReg
1829 movptr(tmpReg, NULL_WORD);
1830 } else {
1831 // Can suffer RTS->RTO upgrades on shared or cold $ lines
1832 // Test-And-CAS instead of CAS
1833 movptr(tmpReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); // rax, = m->_owner
1834 testptr(tmpReg, tmpReg); // Locked ?
1835 jccb (Assembler::notZero, DONE_LABEL);
1836 }
1837
1838 // Appears unlocked - try to swing _owner from null to non-null.
1839 // Ideally, I'd manifest "Self" with get_thread and then attempt
1840 // to CAS the register containing Self into m->Owner.
1841 // But we don't have enough registers, so instead we can either try to CAS
1842 // rsp or the address of the box (in scr) into &m->owner. If the CAS succeeds
1843 // we later store "Self" into m->Owner. Transiently storing a stack address
1844 // (rsp or the address of the box) into m->owner is harmless.
1845 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand.
1846 if (os::is_MP()) {
1847 lock();
1848 }
1849 cmpxchgptr(scrReg, Address(boxReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
1850 movptr(Address(scrReg, 0), 3); // box->_displaced_header = 3
1851 // If we weren't able to swing _owner from NULL to the BasicLock
1852 // then take the slow path.
1853 jccb (Assembler::notZero, DONE_LABEL);
1854 // update _owner from BasicLock to thread
1855 get_thread (scrReg); // beware: clobbers ICCs
1856 movptr(Address(boxReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), scrReg);
1857 xorptr(boxReg, boxReg); // set icc.ZFlag = 1 to indicate success
1858
1859 // If the CAS fails we can either retry or pass control to the slow-path.
1860 // We use the latter tactic.
1861 // Pass the CAS result in the icc.ZFlag into DONE_LABEL
1862 // If the CAS was successful ...
1863 // Self has acquired the lock
1864 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it.
1865 // Intentional fall-through into DONE_LABEL ...
1866 } else {
1867 movptr(Address(boxReg, 0), intptr_t(markOopDesc::unused_mark())); // results in ST-before-CAS penalty
1868 movptr(boxReg, tmpReg);
1869
1870 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes
1871 if ((EmitSync & 2048) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) {
1872 // prefetchw [eax + Offset(_owner)-2]
1873 prefetchw(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
1874 }
1875
1876 if ((EmitSync & 64) == 0) {
1877 // Optimistic form
1878 xorptr (tmpReg, tmpReg);
1879 } else {
1880 // Can suffer RTS->RTO upgrades on shared or cold $ lines
1881 movptr(tmpReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); // rax, = m->_owner
1882 testptr(tmpReg, tmpReg); // Locked ?
1883 jccb (Assembler::notZero, DONE_LABEL);
1884 }
1885
1886 // Appears unlocked - try to swing _owner from null to non-null.
1887 // Use either "Self" (in scr) or rsp as thread identity in _owner.
1888 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand.
1889 get_thread (scrReg);
1890 if (os::is_MP()) {
1891 lock();
1892 }
1893 cmpxchgptr(scrReg, Address(boxReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
1894
1895 // If the CAS fails we can either retry or pass control to the slow-path.
1896 // We use the latter tactic.
1897 // Pass the CAS result in the icc.ZFlag into DONE_LABEL
1898 // If the CAS was successful ...
1899 // Self has acquired the lock
1900 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it.
1901 // Intentional fall-through into DONE_LABEL ...
1902 }
1903 #else // _LP64
1904 // It's inflated
1905 movq(scrReg, tmpReg);
1906 xorq(tmpReg, tmpReg);
1907
1908 if (os::is_MP()) {
1909 lock();
1910 }
1911 cmpxchgptr(r15_thread, Address(scrReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
1912 // Unconditionally set box->_displaced_header = markOopDesc::unused_mark().
1913 // Without cast to int32_t movptr will destroy r10 which is typically obj.
1914 movptr(Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark()));
1915 // Intentional fall-through into DONE_LABEL ...
1916 // Propagate ICC.ZF from CAS above into DONE_LABEL.
1917 #endif // _LP64
1918 #if INCLUDE_RTM_OPT
1919 } // use_rtm()
1920 #endif
1921 // DONE_LABEL is a hot target - we'd really like to place it at the
1922 // start of cache line by padding with NOPs.
1923 // See the AMD and Intel software optimization manuals for the
1924 // most efficient "long" NOP encodings.
1925 // Unfortunately none of our alignment mechanisms suffice.
1926 bind(DONE_LABEL);
1927
1928 // At DONE_LABEL the icc ZFlag is set as follows ...
1929 // Fast_Unlock uses the same protocol.
1930 // ZFlag == 1 -> Success
1931 // ZFlag == 0 -> Failure - force control through the slow-path
1932 }
1933 }
1934
1935 // obj: object to unlock
1936 // box: box address (displaced header location), killed. Must be EAX.
1937 // tmp: killed, cannot be obj nor box.
1938 //
1939 // Some commentary on balanced locking:
1940 //
1941 // Fast_Lock and Fast_Unlock are emitted only for provably balanced lock sites.
1942 // Methods that don't have provably balanced locking are forced to run in the
1943 // interpreter - such methods won't be compiled to use fast_lock and fast_unlock.
1944 // The interpreter provides two properties:
1945 // I1: At return-time the interpreter automatically and quietly unlocks any
1946 // objects acquired the current activation (frame). Recall that the
1947 // interpreter maintains an on-stack list of locks currently held by
1948 // a frame.
1949 // I2: If a method attempts to unlock an object that is not held by the
1950 // the frame the interpreter throws IMSX.
1951 //
1952 // Lets say A(), which has provably balanced locking, acquires O and then calls B().
1953 // B() doesn't have provably balanced locking so it runs in the interpreter.
1954 // Control returns to A() and A() unlocks O. By I1 and I2, above, we know that O
1955 // is still locked by A().
1956 //
1957 // The only other source of unbalanced locking would be JNI. The "Java Native Interface:
1958 // Programmer's Guide and Specification" claims that an object locked by jni_monitorenter
1959 // should not be unlocked by "normal" java-level locking and vice-versa. The specification
1960 // doesn't specify what will occur if a program engages in such mixed-mode locking, however.
1961 // Arguably given that the spec legislates the JNI case as undefined our implementation
1962 // could reasonably *avoid* checking owner in Fast_Unlock().
1963 // In the interest of performance we elide m->Owner==Self check in unlock.
1964 // A perfectly viable alternative is to elide the owner check except when
1965 // Xcheck:jni is enabled.
1966
1967 void MacroAssembler::fast_unlock(Register objReg, Register boxReg, Register tmpReg, bool use_rtm) {
1968 assert(boxReg == rax, "");
1969 assert_different_registers(objReg, boxReg, tmpReg);
1970
1971 if (EmitSync & 4) {
1972 // Disable - inhibit all inlining. Force control through the slow-path
1973 cmpptr (rsp, 0);
1974 } else {
1975 Label DONE_LABEL, Stacked, CheckSucc;
1976
1977 // Critically, the biased locking test must have precedence over
1978 // and appear before the (box->dhw == 0) recursive stack-lock test.
1979 if (UseBiasedLocking && !UseOptoBiasInlining) {
1980 biased_locking_exit(objReg, tmpReg, DONE_LABEL);
1981 }
1982
1983 #if INCLUDE_RTM_OPT
1984 if (UseRTMForStackLocks && use_rtm) {
1985 assert(!UseBiasedLocking, "Biased locking is not supported with RTM locking");
1986 Label L_regular_unlock;
1987 movptr(tmpReg, Address(objReg, oopDesc::mark_offset_in_bytes())); // fetch markword
1988 andptr(tmpReg, markOopDesc::biased_lock_mask_in_place); // look at 3 lock bits
1989 cmpptr(tmpReg, markOopDesc::unlocked_value); // bits = 001 unlocked
1990 jccb(Assembler::notEqual, L_regular_unlock); // if !HLE RegularLock
1991 xend(); // otherwise end...
1992 jmp(DONE_LABEL); // ... and we're done
1993 bind(L_regular_unlock);
1994 }
1995 #endif
1996
1997 cmpptr(Address(boxReg, 0), (int32_t)NULL_WORD); // Examine the displaced header
1998 jcc (Assembler::zero, DONE_LABEL); // 0 indicates recursive stack-lock
1999 movptr(tmpReg, Address(objReg, oopDesc::mark_offset_in_bytes())); // Examine the object's markword
2000 testptr(tmpReg, markOopDesc::monitor_value); // Inflated?
2001 jccb (Assembler::zero, Stacked);
2002
2003 // It's inflated.
2004 #if INCLUDE_RTM_OPT
2005 if (use_rtm) {
2006 Label L_regular_inflated_unlock;
2007 int owner_offset = OM_OFFSET_NO_MONITOR_VALUE_TAG(owner);
2008 movptr(boxReg, Address(tmpReg, owner_offset));
2009 testptr(boxReg, boxReg);
2010 jccb(Assembler::notZero, L_regular_inflated_unlock);
2011 xend();
2012 jmpb(DONE_LABEL);
2013 bind(L_regular_inflated_unlock);
2014 }
2015 #endif
2016
2017 // Despite our balanced locking property we still check that m->_owner == Self
2018 // as java routines or native JNI code called by this thread might
2019 // have released the lock.
2020 // Refer to the comments in synchronizer.cpp for how we might encode extra
2021 // state in _succ so we can avoid fetching EntryList|cxq.
2022 //
2023 // I'd like to add more cases in fast_lock() and fast_unlock() --
2024 // such as recursive enter and exit -- but we have to be wary of
2025 // I$ bloat, T$ effects and BP$ effects.
2026 //
2027 // If there's no contention try a 1-0 exit. That is, exit without
2028 // a costly MEMBAR or CAS. See synchronizer.cpp for details on how
2029 // we detect and recover from the race that the 1-0 exit admits.
2030 //
2031 // Conceptually Fast_Unlock() must execute a STST|LDST "release" barrier
2032 // before it STs null into _owner, releasing the lock. Updates
2033 // to data protected by the critical section must be visible before
2034 // we drop the lock (and thus before any other thread could acquire
2035 // the lock and observe the fields protected by the lock).
2036 // IA32's memory-model is SPO, so STs are ordered with respect to
2037 // each other and there's no need for an explicit barrier (fence).
2038 // See also http://gee.cs.oswego.edu/dl/jmm/cookbook.html.
2039 #ifndef _LP64
2040 get_thread (boxReg);
2041 if ((EmitSync & 4096) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) {
2042 // prefetchw [ebx + Offset(_owner)-2]
2043 prefetchw(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
2044 }
2045
2046 // Note that we could employ various encoding schemes to reduce
2047 // the number of loads below (currently 4) to just 2 or 3.
2048 // Refer to the comments in synchronizer.cpp.
2049 // In practice the chain of fetches doesn't seem to impact performance, however.
2050 xorptr(boxReg, boxReg);
2051 if ((EmitSync & 65536) == 0 && (EmitSync & 256)) {
2052 // Attempt to reduce branch density - AMD's branch predictor.
2053 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(recursions)));
2054 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(EntryList)));
2055 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(cxq)));
2056 jccb (Assembler::notZero, DONE_LABEL);
2057 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), NULL_WORD);
2058 jmpb (DONE_LABEL);
2059 } else {
2060 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(recursions)));
2061 jccb (Assembler::notZero, DONE_LABEL);
2062 movptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(EntryList)));
2063 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(cxq)));
2064 jccb (Assembler::notZero, CheckSucc);
2065 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), NULL_WORD);
2066 jmpb (DONE_LABEL);
2067 }
2068
2069 // The Following code fragment (EmitSync & 65536) improves the performance of
2070 // contended applications and contended synchronization microbenchmarks.
2071 // Unfortunately the emission of the code - even though not executed - causes regressions
2072 // in scimark and jetstream, evidently because of $ effects. Replacing the code
2073 // with an equal number of never-executed NOPs results in the same regression.
2074 // We leave it off by default.
2075
2076 if ((EmitSync & 65536) != 0) {
2077 Label LSuccess, LGoSlowPath ;
2078
2079 bind (CheckSucc);
2080
2081 // Optional pre-test ... it's safe to elide this
2082 cmpptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(succ)), (int32_t)NULL_WORD);
2083 jccb(Assembler::zero, LGoSlowPath);
2084
2085 // We have a classic Dekker-style idiom:
2086 // ST m->_owner = 0 ; MEMBAR; LD m->_succ
2087 // There are a number of ways to implement the barrier:
2088 // (1) lock:andl &m->_owner, 0
2089 // is fast, but mask doesn't currently support the "ANDL M,IMM32" form.
2090 // LOCK: ANDL [ebx+Offset(_Owner)-2], 0
2091 // Encodes as 81 31 OFF32 IMM32 or 83 63 OFF8 IMM8
2092 // (2) If supported, an explicit MFENCE is appealing.
2093 // In older IA32 processors MFENCE is slower than lock:add or xchg
2094 // particularly if the write-buffer is full as might be the case if
2095 // if stores closely precede the fence or fence-equivalent instruction.
2096 // See https://blogs.oracle.com/dave/entry/instruction_selection_for_volatile_fences
2097 // as the situation has changed with Nehalem and Shanghai.
2098 // (3) In lieu of an explicit fence, use lock:addl to the top-of-stack
2099 // The $lines underlying the top-of-stack should be in M-state.
2100 // The locked add instruction is serializing, of course.
2101 // (4) Use xchg, which is serializing
2102 // mov boxReg, 0; xchgl boxReg, [tmpReg + Offset(_owner)-2] also works
2103 // (5) ST m->_owner = 0 and then execute lock:orl &m->_succ, 0.
2104 // The integer condition codes will tell us if succ was 0.
2105 // Since _succ and _owner should reside in the same $line and
2106 // we just stored into _owner, it's likely that the $line
2107 // remains in M-state for the lock:orl.
2108 //
2109 // We currently use (3), although it's likely that switching to (2)
2110 // is correct for the future.
2111
2112 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), NULL_WORD);
2113 if (os::is_MP()) {
2114 lock(); addptr(Address(rsp, 0), 0);
2115 }
2116 // Ratify _succ remains non-null
2117 cmpptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(succ)), 0);
2118 jccb (Assembler::notZero, LSuccess);
2119
2120 xorptr(boxReg, boxReg); // box is really EAX
2121 if (os::is_MP()) { lock(); }
2122 cmpxchgptr(rsp, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
2123 // There's no successor so we tried to regrab the lock with the
2124 // placeholder value. If that didn't work, then another thread
2125 // grabbed the lock so we're done (and exit was a success).
2126 jccb (Assembler::notEqual, LSuccess);
2127 // Since we're low on registers we installed rsp as a placeholding in _owner.
2128 // Now install Self over rsp. This is safe as we're transitioning from
2129 // non-null to non=null
2130 get_thread (boxReg);
2131 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), boxReg);
2132 // Intentional fall-through into LGoSlowPath ...
2133
2134 bind (LGoSlowPath);
2135 orptr(boxReg, 1); // set ICC.ZF=0 to indicate failure
2136 jmpb (DONE_LABEL);
2137
2138 bind (LSuccess);
2139 xorptr(boxReg, boxReg); // set ICC.ZF=1 to indicate success
2140 jmpb (DONE_LABEL);
2141 }
2142
2143 bind (Stacked);
2144 // It's not inflated and it's not recursively stack-locked and it's not biased.
2145 // It must be stack-locked.
2146 // Try to reset the header to displaced header.
2147 // The "box" value on the stack is stable, so we can reload
2148 // and be assured we observe the same value as above.
2149 movptr(tmpReg, Address(boxReg, 0));
2150 if (os::is_MP()) {
2151 lock();
2152 }
2153 cmpxchgptr(tmpReg, Address(objReg, oopDesc::mark_offset_in_bytes())); // Uses RAX which is box
2154 // Intention fall-thru into DONE_LABEL
2155
2156 // DONE_LABEL is a hot target - we'd really like to place it at the
2157 // start of cache line by padding with NOPs.
2158 // See the AMD and Intel software optimization manuals for the
2159 // most efficient "long" NOP encodings.
2160 // Unfortunately none of our alignment mechanisms suffice.
2161 if ((EmitSync & 65536) == 0) {
2162 bind (CheckSucc);
2163 }
2164 #else // _LP64
2165 // It's inflated
2166 if (EmitSync & 1024) {
2167 // Emit code to check that _owner == Self
2168 // We could fold the _owner test into subsequent code more efficiently
2169 // than using a stand-alone check, but since _owner checking is off by
2170 // default we don't bother. We also might consider predicating the
2171 // _owner==Self check on Xcheck:jni or running on a debug build.
2172 movptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
2173 xorptr(boxReg, r15_thread);
2174 } else {
2175 xorptr(boxReg, boxReg);
2176 }
2177 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(recursions)));
2178 jccb (Assembler::notZero, DONE_LABEL);
2179 movptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(cxq)));
2180 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(EntryList)));
2181 jccb (Assembler::notZero, CheckSucc);
2182 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), (int32_t)NULL_WORD);
2183 jmpb (DONE_LABEL);
2184
2185 if ((EmitSync & 65536) == 0) {
2186 // Try to avoid passing control into the slow_path ...
2187 Label LSuccess, LGoSlowPath ;
2188 bind (CheckSucc);
2189
2190 // The following optional optimization can be elided if necessary
2191 // Effectively: if (succ == null) goto SlowPath
2192 // The code reduces the window for a race, however,
2193 // and thus benefits performance.
2194 cmpptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(succ)), (int32_t)NULL_WORD);
2195 jccb (Assembler::zero, LGoSlowPath);
2196
2197 xorptr(boxReg, boxReg);
2198 if ((EmitSync & 16) && os::is_MP()) {
2199 xchgptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
2200 } else {
2201 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), (int32_t)NULL_WORD);
2202 if (os::is_MP()) {
2203 // Memory barrier/fence
2204 // Dekker pivot point -- fulcrum : ST Owner; MEMBAR; LD Succ
2205 // Instead of MFENCE we use a dummy locked add of 0 to the top-of-stack.
2206 // This is faster on Nehalem and AMD Shanghai/Barcelona.
2207 // See https://blogs.oracle.com/dave/entry/instruction_selection_for_volatile_fences
2208 // We might also restructure (ST Owner=0;barrier;LD _Succ) to
2209 // (mov box,0; xchgq box, &m->Owner; LD _succ) .
2210 lock(); addl(Address(rsp, 0), 0);
2211 }
2212 }
2213 cmpptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(succ)), (int32_t)NULL_WORD);
2214 jccb (Assembler::notZero, LSuccess);
2215
2216 // Rare inopportune interleaving - race.
2217 // The successor vanished in the small window above.
2218 // The lock is contended -- (cxq|EntryList) != null -- and there's no apparent successor.
2219 // We need to ensure progress and succession.
2220 // Try to reacquire the lock.
2221 // If that fails then the new owner is responsible for succession and this
2222 // thread needs to take no further action and can exit via the fast path (success).
2223 // If the re-acquire succeeds then pass control into the slow path.
2224 // As implemented, this latter mode is horrible because we generated more
2225 // coherence traffic on the lock *and* artifically extended the critical section
2226 // length while by virtue of passing control into the slow path.
2227
2228 // box is really RAX -- the following CMPXCHG depends on that binding
2229 // cmpxchg R,[M] is equivalent to rax = CAS(M,rax,R)
2230 if (os::is_MP()) { lock(); }
2231 cmpxchgptr(r15_thread, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
2232 // There's no successor so we tried to regrab the lock.
2233 // If that didn't work, then another thread grabbed the
2234 // lock so we're done (and exit was a success).
2235 jccb (Assembler::notEqual, LSuccess);
2236 // Intentional fall-through into slow-path
2237
2238 bind (LGoSlowPath);
2239 orl (boxReg, 1); // set ICC.ZF=0 to indicate failure
2240 jmpb (DONE_LABEL);
2241
2242 bind (LSuccess);
2243 testl (boxReg, 0); // set ICC.ZF=1 to indicate success
2244 jmpb (DONE_LABEL);
2245 }
2246
2247 bind (Stacked);
2248 movptr(tmpReg, Address (boxReg, 0)); // re-fetch
2249 if (os::is_MP()) { lock(); }
2250 cmpxchgptr(tmpReg, Address(objReg, oopDesc::mark_offset_in_bytes())); // Uses RAX which is box
2251
2252 if (EmitSync & 65536) {
2253 bind (CheckSucc);
2254 }
2255 #endif
2256 bind(DONE_LABEL);
2257 }
2258 }
2259 #endif // COMPILER2
2260
2261 void MacroAssembler::c2bool(Register x) {
2262 // implements x == 0 ? 0 : 1
2263 // note: must only look at least-significant byte of x
2264 // since C-style booleans are stored in one byte
2265 // only! (was bug)
2266 andl(x, 0xFF);
2267 setb(Assembler::notZero, x);
2268 }
2269
2270 // Wouldn't need if AddressLiteral version had new name
2271 void MacroAssembler::call(Label& L, relocInfo::relocType rtype) {
2272 Assembler::call(L, rtype);
2273 }
2274
2275 void MacroAssembler::call(Register entry) {
2276 Assembler::call(entry);
2277 }
2278
2279 void MacroAssembler::call(AddressLiteral entry) {
2280 if (reachable(entry)) {
2281 Assembler::call_literal(entry.target(), entry.rspec());
2282 } else {
2283 lea(rscratch1, entry);
2284 Assembler::call(rscratch1);
2285 }
2286 }
2287
2288 void MacroAssembler::ic_call(address entry, jint method_index) {
2289 RelocationHolder rh = virtual_call_Relocation::spec(pc(), method_index);
2290 movptr(rax, (intptr_t)Universe::non_oop_word());
2291 call(AddressLiteral(entry, rh));
2292 }
2293
2294 // Implementation of call_VM versions
2295
2296 void MacroAssembler::call_VM(Register oop_result,
2297 address entry_point,
2298 bool check_exceptions) {
2299 Label C, E;
2300 call(C, relocInfo::none);
2301 jmp(E);
2302
2303 bind(C);
2304 call_VM_helper(oop_result, entry_point, 0, check_exceptions);
2305 ret(0);
2306
2307 bind(E);
2308 }
2309
2310 void MacroAssembler::call_VM(Register oop_result,
2311 address entry_point,
2312 Register arg_1,
2313 bool check_exceptions) {
2314 Label C, E;
2315 call(C, relocInfo::none);
2316 jmp(E);
2317
2318 bind(C);
2319 pass_arg1(this, arg_1);
2320 call_VM_helper(oop_result, entry_point, 1, check_exceptions);
2321 ret(0);
2322
2323 bind(E);
2324 }
2325
2326 void MacroAssembler::call_VM(Register oop_result,
2327 address entry_point,
2328 Register arg_1,
2329 Register arg_2,
2330 bool check_exceptions) {
2331 Label C, E;
2332 call(C, relocInfo::none);
2333 jmp(E);
2334
2335 bind(C);
2336
2337 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2338
2339 pass_arg2(this, arg_2);
2340 pass_arg1(this, arg_1);
2341 call_VM_helper(oop_result, entry_point, 2, check_exceptions);
2342 ret(0);
2343
2344 bind(E);
2345 }
2346
2347 void MacroAssembler::call_VM(Register oop_result,
2348 address entry_point,
2349 Register arg_1,
2350 Register arg_2,
2351 Register arg_3,
2352 bool check_exceptions) {
2353 Label C, E;
2354 call(C, relocInfo::none);
2355 jmp(E);
2356
2357 bind(C);
2358
2359 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
2360 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
2361 pass_arg3(this, arg_3);
2362
2363 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2364 pass_arg2(this, arg_2);
2365
2366 pass_arg1(this, arg_1);
2367 call_VM_helper(oop_result, entry_point, 3, check_exceptions);
2368 ret(0);
2369
2370 bind(E);
2371 }
2372
2373 void MacroAssembler::call_VM(Register oop_result,
2374 Register last_java_sp,
2375 address entry_point,
2376 int number_of_arguments,
2377 bool check_exceptions) {
2378 Register thread = LP64_ONLY(r15_thread) NOT_LP64(noreg);
2379 call_VM_base(oop_result, thread, last_java_sp, entry_point, number_of_arguments, check_exceptions);
2380 }
2381
2382 void MacroAssembler::call_VM(Register oop_result,
2383 Register last_java_sp,
2384 address entry_point,
2385 Register arg_1,
2386 bool check_exceptions) {
2387 pass_arg1(this, arg_1);
2388 call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
2389 }
2390
2391 void MacroAssembler::call_VM(Register oop_result,
2392 Register last_java_sp,
2393 address entry_point,
2394 Register arg_1,
2395 Register arg_2,
2396 bool check_exceptions) {
2397
2398 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2399 pass_arg2(this, arg_2);
2400 pass_arg1(this, arg_1);
2401 call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
2402 }
2403
2404 void MacroAssembler::call_VM(Register oop_result,
2405 Register last_java_sp,
2406 address entry_point,
2407 Register arg_1,
2408 Register arg_2,
2409 Register arg_3,
2410 bool check_exceptions) {
2411 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
2412 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
2413 pass_arg3(this, arg_3);
2414 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2415 pass_arg2(this, arg_2);
2416 pass_arg1(this, arg_1);
2417 call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
2418 }
2419
2420 void MacroAssembler::super_call_VM(Register oop_result,
2421 Register last_java_sp,
2422 address entry_point,
2423 int number_of_arguments,
2424 bool check_exceptions) {
2425 Register thread = LP64_ONLY(r15_thread) NOT_LP64(noreg);
2426 MacroAssembler::call_VM_base(oop_result, thread, last_java_sp, entry_point, number_of_arguments, check_exceptions);
2427 }
2428
2429 void MacroAssembler::super_call_VM(Register oop_result,
2430 Register last_java_sp,
2431 address entry_point,
2432 Register arg_1,
2433 bool check_exceptions) {
2434 pass_arg1(this, arg_1);
2435 super_call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
2436 }
2437
2438 void MacroAssembler::super_call_VM(Register oop_result,
2439 Register last_java_sp,
2440 address entry_point,
2441 Register arg_1,
2442 Register arg_2,
2443 bool check_exceptions) {
2444
2445 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2446 pass_arg2(this, arg_2);
2447 pass_arg1(this, arg_1);
2448 super_call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
2449 }
2450
2451 void MacroAssembler::super_call_VM(Register oop_result,
2452 Register last_java_sp,
2453 address entry_point,
2454 Register arg_1,
2455 Register arg_2,
2456 Register arg_3,
2457 bool check_exceptions) {
2458 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
2459 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
2460 pass_arg3(this, arg_3);
2461 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2462 pass_arg2(this, arg_2);
2463 pass_arg1(this, arg_1);
2464 super_call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
2465 }
2466
2467 void MacroAssembler::call_VM_base(Register oop_result,
2468 Register java_thread,
2469 Register last_java_sp,
2470 address entry_point,
2471 int number_of_arguments,
2472 bool check_exceptions) {
2473 // determine java_thread register
2474 if (!java_thread->is_valid()) {
2475 #ifdef _LP64
2476 java_thread = r15_thread;
2477 #else
2478 java_thread = rdi;
2479 get_thread(java_thread);
2480 #endif // LP64
2481 }
2482 // determine last_java_sp register
2483 if (!last_java_sp->is_valid()) {
2484 last_java_sp = rsp;
2485 }
2486 // debugging support
2487 assert(number_of_arguments >= 0 , "cannot have negative number of arguments");
2488 LP64_ONLY(assert(java_thread == r15_thread, "unexpected register"));
2489 #ifdef ASSERT
2490 // TraceBytecodes does not use r12 but saves it over the call, so don't verify
2491 // r12 is the heapbase.
2492 LP64_ONLY(if ((UseCompressedOops || UseCompressedClassPointers) && !TraceBytecodes) verify_heapbase("call_VM_base: heap base corrupted?");)
2493 #endif // ASSERT
2494
2495 assert(java_thread != oop_result , "cannot use the same register for java_thread & oop_result");
2496 assert(java_thread != last_java_sp, "cannot use the same register for java_thread & last_java_sp");
2497
2498 // push java thread (becomes first argument of C function)
2499
2500 NOT_LP64(push(java_thread); number_of_arguments++);
2501 LP64_ONLY(mov(c_rarg0, r15_thread));
2502
2503 // set last Java frame before call
2504 assert(last_java_sp != rbp, "can't use ebp/rbp");
2505
2506 // Only interpreter should have to set fp
2507 set_last_Java_frame(java_thread, last_java_sp, rbp, NULL);
2508
2509 // do the call, remove parameters
2510 MacroAssembler::call_VM_leaf_base(entry_point, number_of_arguments);
2511
2512 // restore the thread (cannot use the pushed argument since arguments
2513 // may be overwritten by C code generated by an optimizing compiler);
2514 // however can use the register value directly if it is callee saved.
2515 if (LP64_ONLY(true ||) java_thread == rdi || java_thread == rsi) {
2516 // rdi & rsi (also r15) are callee saved -> nothing to do
2517 #ifdef ASSERT
2518 guarantee(java_thread != rax, "change this code");
2519 push(rax);
2520 { Label L;
2521 get_thread(rax);
2522 cmpptr(java_thread, rax);
2523 jcc(Assembler::equal, L);
2524 STOP("MacroAssembler::call_VM_base: rdi not callee saved?");
2525 bind(L);
2526 }
2527 pop(rax);
2528 #endif
2529 } else {
2530 get_thread(java_thread);
2531 }
2532 // reset last Java frame
2533 // Only interpreter should have to clear fp
2534 reset_last_Java_frame(java_thread, true);
2535
2536 // C++ interp handles this in the interpreter
2537 check_and_handle_popframe(java_thread);
2538 check_and_handle_earlyret(java_thread);
2539
2540 if (check_exceptions) {
2541 // check for pending exceptions (java_thread is set upon return)
2542 cmpptr(Address(java_thread, Thread::pending_exception_offset()), (int32_t) NULL_WORD);
2543 #ifndef _LP64
2544 jump_cc(Assembler::notEqual,
2545 RuntimeAddress(StubRoutines::forward_exception_entry()));
2546 #else
2547 // This used to conditionally jump to forward_exception however it is
2548 // possible if we relocate that the branch will not reach. So we must jump
2549 // around so we can always reach
2550
2551 Label ok;
2552 jcc(Assembler::equal, ok);
2553 jump(RuntimeAddress(StubRoutines::forward_exception_entry()));
2554 bind(ok);
2555 #endif // LP64
2556 }
2557
2558 // get oop result if there is one and reset the value in the thread
2559 if (oop_result->is_valid()) {
2560 get_vm_result(oop_result, java_thread);
2561 }
2562 }
2563
2564 void MacroAssembler::call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions) {
2565
2566 // Calculate the value for last_Java_sp
2567 // somewhat subtle. call_VM does an intermediate call
2568 // which places a return address on the stack just under the
2569 // stack pointer as the user finsihed with it. This allows
2570 // use to retrieve last_Java_pc from last_Java_sp[-1].
2571 // On 32bit we then have to push additional args on the stack to accomplish
2572 // the actual requested call. On 64bit call_VM only can use register args
2573 // so the only extra space is the return address that call_VM created.
2574 // This hopefully explains the calculations here.
2575
2576 #ifdef _LP64
2577 // We've pushed one address, correct last_Java_sp
2578 lea(rax, Address(rsp, wordSize));
2579 #else
2580 lea(rax, Address(rsp, (1 + number_of_arguments) * wordSize));
2581 #endif // LP64
2582
2583 call_VM_base(oop_result, noreg, rax, entry_point, number_of_arguments, check_exceptions);
2584
2585 }
2586
2587 // Use this method when MacroAssembler version of call_VM_leaf_base() should be called from Interpreter.
2588 void MacroAssembler::call_VM_leaf0(address entry_point) {
2589 MacroAssembler::call_VM_leaf_base(entry_point, 0);
2590 }
2591
2592 void MacroAssembler::call_VM_leaf(address entry_point, int number_of_arguments) {
2593 call_VM_leaf_base(entry_point, number_of_arguments);
2594 }
2595
2596 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0) {
2597 pass_arg0(this, arg_0);
2598 call_VM_leaf(entry_point, 1);
2599 }
2600
2601 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
2602
2603 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
2604 pass_arg1(this, arg_1);
2605 pass_arg0(this, arg_0);
2606 call_VM_leaf(entry_point, 2);
2607 }
2608
2609 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
2610 LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg"));
2611 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2612 pass_arg2(this, arg_2);
2613 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
2614 pass_arg1(this, arg_1);
2615 pass_arg0(this, arg_0);
2616 call_VM_leaf(entry_point, 3);
2617 }
2618
2619 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0) {
2620 pass_arg0(this, arg_0);
2621 MacroAssembler::call_VM_leaf_base(entry_point, 1);
2622 }
2623
2624 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
2625
2626 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
2627 pass_arg1(this, arg_1);
2628 pass_arg0(this, arg_0);
2629 MacroAssembler::call_VM_leaf_base(entry_point, 2);
2630 }
2631
2632 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
2633 LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg"));
2634 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2635 pass_arg2(this, arg_2);
2636 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
2637 pass_arg1(this, arg_1);
2638 pass_arg0(this, arg_0);
2639 MacroAssembler::call_VM_leaf_base(entry_point, 3);
2640 }
2641
2642 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2, Register arg_3) {
2643 LP64_ONLY(assert(arg_0 != c_rarg3, "smashed arg"));
2644 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
2645 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
2646 pass_arg3(this, arg_3);
2647 LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg"));
2648 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2649 pass_arg2(this, arg_2);
2650 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
2651 pass_arg1(this, arg_1);
2652 pass_arg0(this, arg_0);
2653 MacroAssembler::call_VM_leaf_base(entry_point, 4);
2654 }
2655
2656 void MacroAssembler::get_vm_result(Register oop_result, Register java_thread) {
2657 movptr(oop_result, Address(java_thread, JavaThread::vm_result_offset()));
2658 movptr(Address(java_thread, JavaThread::vm_result_offset()), NULL_WORD);
2659 verify_oop(oop_result, "broken oop in call_VM_base");
2660 }
2661
2662 void MacroAssembler::get_vm_result_2(Register metadata_result, Register java_thread) {
2663 movptr(metadata_result, Address(java_thread, JavaThread::vm_result_2_offset()));
2664 movptr(Address(java_thread, JavaThread::vm_result_2_offset()), NULL_WORD);
2665 }
2666
2667 void MacroAssembler::check_and_handle_earlyret(Register java_thread) {
2668 }
2669
2670 void MacroAssembler::check_and_handle_popframe(Register java_thread) {
2671 }
2672
2673 void MacroAssembler::cmp32(AddressLiteral src1, int32_t imm) {
2674 if (reachable(src1)) {
2675 cmpl(as_Address(src1), imm);
2676 } else {
2677 lea(rscratch1, src1);
2678 cmpl(Address(rscratch1, 0), imm);
2679 }
2680 }
2681
2682 void MacroAssembler::cmp32(Register src1, AddressLiteral src2) {
2683 assert(!src2.is_lval(), "use cmpptr");
2684 if (reachable(src2)) {
2685 cmpl(src1, as_Address(src2));
2686 } else {
2687 lea(rscratch1, src2);
2688 cmpl(src1, Address(rscratch1, 0));
2689 }
2690 }
2691
2692 void MacroAssembler::cmp32(Register src1, int32_t imm) {
2693 Assembler::cmpl(src1, imm);
2694 }
2695
2696 void MacroAssembler::cmp32(Register src1, Address src2) {
2697 Assembler::cmpl(src1, src2);
2698 }
2699
2700 void MacroAssembler::cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) {
2701 ucomisd(opr1, opr2);
2702
2703 Label L;
2704 if (unordered_is_less) {
2705 movl(dst, -1);
2706 jcc(Assembler::parity, L);
2707 jcc(Assembler::below , L);
2708 movl(dst, 0);
2709 jcc(Assembler::equal , L);
2710 increment(dst);
2711 } else { // unordered is greater
2712 movl(dst, 1);
2713 jcc(Assembler::parity, L);
2714 jcc(Assembler::above , L);
2715 movl(dst, 0);
2716 jcc(Assembler::equal , L);
2717 decrementl(dst);
2718 }
2719 bind(L);
2720 }
2721
2722 void MacroAssembler::cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) {
2723 ucomiss(opr1, opr2);
2724
2725 Label L;
2726 if (unordered_is_less) {
2727 movl(dst, -1);
2728 jcc(Assembler::parity, L);
2729 jcc(Assembler::below , L);
2730 movl(dst, 0);
2731 jcc(Assembler::equal , L);
2732 increment(dst);
2733 } else { // unordered is greater
2734 movl(dst, 1);
2735 jcc(Assembler::parity, L);
2736 jcc(Assembler::above , L);
2737 movl(dst, 0);
2738 jcc(Assembler::equal , L);
2739 decrementl(dst);
2740 }
2741 bind(L);
2742 }
2743
2744
2745 void MacroAssembler::cmp8(AddressLiteral src1, int imm) {
2746 if (reachable(src1)) {
2747 cmpb(as_Address(src1), imm);
2748 } else {
2749 lea(rscratch1, src1);
2750 cmpb(Address(rscratch1, 0), imm);
2751 }
2752 }
2753
2754 void MacroAssembler::cmpptr(Register src1, AddressLiteral src2) {
2755 #ifdef _LP64
2756 if (src2.is_lval()) {
2757 movptr(rscratch1, src2);
2758 Assembler::cmpq(src1, rscratch1);
2759 } else if (reachable(src2)) {
2760 cmpq(src1, as_Address(src2));
2761 } else {
2762 lea(rscratch1, src2);
2763 Assembler::cmpq(src1, Address(rscratch1, 0));
2764 }
2765 #else
2766 if (src2.is_lval()) {
2767 cmp_literal32(src1, (int32_t) src2.target(), src2.rspec());
2768 } else {
2769 cmpl(src1, as_Address(src2));
2770 }
2771 #endif // _LP64
2772 }
2773
2774 void MacroAssembler::cmpptr(Address src1, AddressLiteral src2) {
2775 assert(src2.is_lval(), "not a mem-mem compare");
2776 #ifdef _LP64
2777 // moves src2's literal address
2778 movptr(rscratch1, src2);
2779 Assembler::cmpq(src1, rscratch1);
2780 #else
2781 cmp_literal32(src1, (int32_t) src2.target(), src2.rspec());
2782 #endif // _LP64
2783 }
2784
2785 void MacroAssembler::locked_cmpxchgptr(Register reg, AddressLiteral adr) {
2786 if (reachable(adr)) {
2787 if (os::is_MP())
2788 lock();
2789 cmpxchgptr(reg, as_Address(adr));
2790 } else {
2791 lea(rscratch1, adr);
2792 if (os::is_MP())
2793 lock();
2794 cmpxchgptr(reg, Address(rscratch1, 0));
2795 }
2796 }
2797
2798 void MacroAssembler::cmpxchgptr(Register reg, Address adr) {
2799 LP64_ONLY(cmpxchgq(reg, adr)) NOT_LP64(cmpxchgl(reg, adr));
2800 }
2801
2802 void MacroAssembler::comisd(XMMRegister dst, AddressLiteral src) {
2803 if (reachable(src)) {
2804 Assembler::comisd(dst, as_Address(src));
2805 } else {
2806 lea(rscratch1, src);
2807 Assembler::comisd(dst, Address(rscratch1, 0));
2808 }
2809 }
2810
2811 void MacroAssembler::comiss(XMMRegister dst, AddressLiteral src) {
2812 if (reachable(src)) {
2813 Assembler::comiss(dst, as_Address(src));
2814 } else {
2815 lea(rscratch1, src);
2816 Assembler::comiss(dst, Address(rscratch1, 0));
2817 }
2818 }
2819
2820
2821 void MacroAssembler::cond_inc32(Condition cond, AddressLiteral counter_addr) {
2822 Condition negated_cond = negate_condition(cond);
2823 Label L;
2824 jcc(negated_cond, L);
2825 pushf(); // Preserve flags
2826 atomic_incl(counter_addr);
2827 popf();
2828 bind(L);
2829 }
2830
2831 int MacroAssembler::corrected_idivl(Register reg) {
2832 // Full implementation of Java idiv and irem; checks for
2833 // special case as described in JVM spec., p.243 & p.271.
2834 // The function returns the (pc) offset of the idivl
2835 // instruction - may be needed for implicit exceptions.
2836 //
2837 // normal case special case
2838 //
2839 // input : rax,: dividend min_int
2840 // reg: divisor (may not be rax,/rdx) -1
2841 //
2842 // output: rax,: quotient (= rax, idiv reg) min_int
2843 // rdx: remainder (= rax, irem reg) 0
2844 assert(reg != rax && reg != rdx, "reg cannot be rax, or rdx register");
2845 const int min_int = 0x80000000;
2846 Label normal_case, special_case;
2847
2848 // check for special case
2849 cmpl(rax, min_int);
2850 jcc(Assembler::notEqual, normal_case);
2851 xorl(rdx, rdx); // prepare rdx for possible special case (where remainder = 0)
2852 cmpl(reg, -1);
2853 jcc(Assembler::equal, special_case);
2854
2855 // handle normal case
2856 bind(normal_case);
2857 cdql();
2858 int idivl_offset = offset();
2859 idivl(reg);
2860
2861 // normal and special case exit
2862 bind(special_case);
2863
2864 return idivl_offset;
2865 }
2866
2867
2868
2869 void MacroAssembler::decrementl(Register reg, int value) {
2870 if (value == min_jint) {subl(reg, value) ; return; }
2871 if (value < 0) { incrementl(reg, -value); return; }
2872 if (value == 0) { ; return; }
2873 if (value == 1 && UseIncDec) { decl(reg) ; return; }
2874 /* else */ { subl(reg, value) ; return; }
2875 }
2876
2877 void MacroAssembler::decrementl(Address dst, int value) {
2878 if (value == min_jint) {subl(dst, value) ; return; }
2879 if (value < 0) { incrementl(dst, -value); return; }
2880 if (value == 0) { ; return; }
2881 if (value == 1 && UseIncDec) { decl(dst) ; return; }
2882 /* else */ { subl(dst, value) ; return; }
2883 }
2884
2885 void MacroAssembler::division_with_shift (Register reg, int shift_value) {
2886 assert (shift_value > 0, "illegal shift value");
2887 Label _is_positive;
2888 testl (reg, reg);
2889 jcc (Assembler::positive, _is_positive);
2890 int offset = (1 << shift_value) - 1 ;
2891
2892 if (offset == 1) {
2893 incrementl(reg);
2894 } else {
2895 addl(reg, offset);
2896 }
2897
2898 bind (_is_positive);
2899 sarl(reg, shift_value);
2900 }
2901
2902 void MacroAssembler::divsd(XMMRegister dst, AddressLiteral src) {
2903 if (reachable(src)) {
2904 Assembler::divsd(dst, as_Address(src));
2905 } else {
2906 lea(rscratch1, src);
2907 Assembler::divsd(dst, Address(rscratch1, 0));
2908 }
2909 }
2910
2911 void MacroAssembler::divss(XMMRegister dst, AddressLiteral src) {
2912 if (reachable(src)) {
2913 Assembler::divss(dst, as_Address(src));
2914 } else {
2915 lea(rscratch1, src);
2916 Assembler::divss(dst, Address(rscratch1, 0));
2917 }
2918 }
2919
2920 // !defined(COMPILER2) is because of stupid core builds
2921 #if !defined(_LP64) || defined(COMPILER1) || !defined(COMPILER2) || INCLUDE_JVMCI
2922 void MacroAssembler::empty_FPU_stack() {
2923 if (VM_Version::supports_mmx()) {
2924 emms();
2925 } else {
2926 for (int i = 8; i-- > 0; ) ffree(i);
2927 }
2928 }
2929 #endif // !LP64 || C1 || !C2 || INCLUDE_JVMCI
2930
2931
2932 // Defines obj, preserves var_size_in_bytes
2933 void MacroAssembler::eden_allocate(Register obj,
2934 Register var_size_in_bytes,
2935 int con_size_in_bytes,
2936 Register t1,
2937 Label& slow_case) {
2938 assert(obj == rax, "obj must be in rax, for cmpxchg");
2939 assert_different_registers(obj, var_size_in_bytes, t1);
2940 if (!Universe::heap()->supports_inline_contig_alloc()) {
2941 jmp(slow_case);
2942 } else {
2943 Register end = t1;
2944 Label retry;
2945 bind(retry);
2946 ExternalAddress heap_top((address) Universe::heap()->top_addr());
2947 movptr(obj, heap_top);
2948 if (var_size_in_bytes == noreg) {
2949 lea(end, Address(obj, con_size_in_bytes));
2950 } else {
2951 lea(end, Address(obj, var_size_in_bytes, Address::times_1));
2952 }
2953 // if end < obj then we wrapped around => object too long => slow case
2954 cmpptr(end, obj);
2955 jcc(Assembler::below, slow_case);
2956 cmpptr(end, ExternalAddress((address) Universe::heap()->end_addr()));
2957 jcc(Assembler::above, slow_case);
2958 // Compare obj with the top addr, and if still equal, store the new top addr in
2959 // end at the address of the top addr pointer. Sets ZF if was equal, and clears
2960 // it otherwise. Use lock prefix for atomicity on MPs.
2961 locked_cmpxchgptr(end, heap_top);
2962 jcc(Assembler::notEqual, retry);
2963 }
2964 }
2965
2966 void MacroAssembler::enter() {
2967 push(rbp);
2968 mov(rbp, rsp);
2969 }
2970
2971 // A 5 byte nop that is safe for patching (see patch_verified_entry)
2972 void MacroAssembler::fat_nop() {
2973 if (UseAddressNop) {
2974 addr_nop_5();
2975 } else {
2976 emit_int8(0x26); // es:
2977 emit_int8(0x2e); // cs:
2978 emit_int8(0x64); // fs:
2979 emit_int8(0x65); // gs:
2980 emit_int8((unsigned char)0x90);
2981 }
2982 }
2983
2984 void MacroAssembler::fcmp(Register tmp) {
2985 fcmp(tmp, 1, true, true);
2986 }
2987
2988 void MacroAssembler::fcmp(Register tmp, int index, bool pop_left, bool pop_right) {
2989 assert(!pop_right || pop_left, "usage error");
2990 if (VM_Version::supports_cmov()) {
2991 assert(tmp == noreg, "unneeded temp");
2992 if (pop_left) {
2993 fucomip(index);
2994 } else {
2995 fucomi(index);
2996 }
2997 if (pop_right) {
2998 fpop();
2999 }
3000 } else {
3001 assert(tmp != noreg, "need temp");
3002 if (pop_left) {
3003 if (pop_right) {
3004 fcompp();
3005 } else {
3006 fcomp(index);
3007 }
3008 } else {
3009 fcom(index);
3010 }
3011 // convert FPU condition into eflags condition via rax,
3012 save_rax(tmp);
3013 fwait(); fnstsw_ax();
3014 sahf();
3015 restore_rax(tmp);
3016 }
3017 // condition codes set as follows:
3018 //
3019 // CF (corresponds to C0) if x < y
3020 // PF (corresponds to C2) if unordered
3021 // ZF (corresponds to C3) if x = y
3022 }
3023
3024 void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less) {
3025 fcmp2int(dst, unordered_is_less, 1, true, true);
3026 }
3027
3028 void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right) {
3029 fcmp(VM_Version::supports_cmov() ? noreg : dst, index, pop_left, pop_right);
3030 Label L;
3031 if (unordered_is_less) {
3032 movl(dst, -1);
3033 jcc(Assembler::parity, L);
3034 jcc(Assembler::below , L);
3035 movl(dst, 0);
3036 jcc(Assembler::equal , L);
3037 increment(dst);
3038 } else { // unordered is greater
3039 movl(dst, 1);
3040 jcc(Assembler::parity, L);
3041 jcc(Assembler::above , L);
3042 movl(dst, 0);
3043 jcc(Assembler::equal , L);
3044 decrementl(dst);
3045 }
3046 bind(L);
3047 }
3048
3049 void MacroAssembler::fld_d(AddressLiteral src) {
3050 fld_d(as_Address(src));
3051 }
3052
3053 void MacroAssembler::fld_s(AddressLiteral src) {
3054 fld_s(as_Address(src));
3055 }
3056
3057 void MacroAssembler::fld_x(AddressLiteral src) {
3058 Assembler::fld_x(as_Address(src));
3059 }
3060
3061 void MacroAssembler::fldcw(AddressLiteral src) {
3062 Assembler::fldcw(as_Address(src));
3063 }
3064
3065 void MacroAssembler::mulpd(XMMRegister dst, AddressLiteral src) {
3066 if (reachable(src)) {
3067 Assembler::mulpd(dst, as_Address(src));
3068 } else {
3069 lea(rscratch1, src);
3070 Assembler::mulpd(dst, Address(rscratch1, 0));
3071 }
3072 }
3073
3074 void MacroAssembler::increase_precision() {
3075 subptr(rsp, BytesPerWord);
3076 fnstcw(Address(rsp, 0));
3077 movl(rax, Address(rsp, 0));
3078 orl(rax, 0x300);
3079 push(rax);
3080 fldcw(Address(rsp, 0));
3081 pop(rax);
3082 }
3083
3084 void MacroAssembler::restore_precision() {
3085 fldcw(Address(rsp, 0));
3086 addptr(rsp, BytesPerWord);
3087 }
3088
3089 void MacroAssembler::fpop() {
3090 ffree();
3091 fincstp();
3092 }
3093
3094 void MacroAssembler::load_float(Address src) {
3095 if (UseSSE >= 1) {
3096 movflt(xmm0, src);
3097 } else {
3098 LP64_ONLY(ShouldNotReachHere());
3099 NOT_LP64(fld_s(src));
3100 }
3101 }
3102
3103 void MacroAssembler::store_float(Address dst) {
3104 if (UseSSE >= 1) {
3105 movflt(dst, xmm0);
3106 } else {
3107 LP64_ONLY(ShouldNotReachHere());
3108 NOT_LP64(fstp_s(dst));
3109 }
3110 }
3111
3112 void MacroAssembler::load_double(Address src) {
3113 if (UseSSE >= 2) {
3114 movdbl(xmm0, src);
3115 } else {
3116 LP64_ONLY(ShouldNotReachHere());
3117 NOT_LP64(fld_d(src));
3118 }
3119 }
3120
3121 void MacroAssembler::store_double(Address dst) {
3122 if (UseSSE >= 2) {
3123 movdbl(dst, xmm0);
3124 } else {
3125 LP64_ONLY(ShouldNotReachHere());
3126 NOT_LP64(fstp_d(dst));
3127 }
3128 }
3129
3130 void MacroAssembler::fremr(Register tmp) {
3131 save_rax(tmp);
3132 { Label L;
3133 bind(L);
3134 fprem();
3135 fwait(); fnstsw_ax();
3136 #ifdef _LP64
3137 testl(rax, 0x400);
3138 jcc(Assembler::notEqual, L);
3139 #else
3140 sahf();
3141 jcc(Assembler::parity, L);
3142 #endif // _LP64
3143 }
3144 restore_rax(tmp);
3145 // Result is in ST0.
3146 // Note: fxch & fpop to get rid of ST1
3147 // (otherwise FPU stack could overflow eventually)
3148 fxch(1);
3149 fpop();
3150 }
3151
3152 // dst = c = a * b + c
3153 void MacroAssembler::fmad(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c) {
3154 Assembler::vfmadd231sd(c, a, b);
3155 if (dst != c) {
3156 movdbl(dst, c);
3157 }
3158 }
3159
3160 // dst = c = a * b + c
3161 void MacroAssembler::fmaf(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c) {
3162 Assembler::vfmadd231ss(c, a, b);
3163 if (dst != c) {
3164 movflt(dst, c);
3165 }
3166 }
3167
3168
3169
3170
3171 void MacroAssembler::incrementl(AddressLiteral dst) {
3172 if (reachable(dst)) {
3173 incrementl(as_Address(dst));
3174 } else {
3175 lea(rscratch1, dst);
3176 incrementl(Address(rscratch1, 0));
3177 }
3178 }
3179
3180 void MacroAssembler::incrementl(ArrayAddress dst) {
3181 incrementl(as_Address(dst));
3182 }
3183
3184 void MacroAssembler::incrementl(Register reg, int value) {
3185 if (value == min_jint) {addl(reg, value) ; return; }
3186 if (value < 0) { decrementl(reg, -value); return; }
3187 if (value == 0) { ; return; }
3188 if (value == 1 && UseIncDec) { incl(reg) ; return; }
3189 /* else */ { addl(reg, value) ; return; }
3190 }
3191
3192 void MacroAssembler::incrementl(Address dst, int value) {
3193 if (value == min_jint) {addl(dst, value) ; return; }
3194 if (value < 0) { decrementl(dst, -value); return; }
3195 if (value == 0) { ; return; }
3196 if (value == 1 && UseIncDec) { incl(dst) ; return; }
3197 /* else */ { addl(dst, value) ; return; }
3198 }
3199
3200 void MacroAssembler::jump(AddressLiteral dst) {
3201 if (reachable(dst)) {
3202 jmp_literal(dst.target(), dst.rspec());
3203 } else {
3204 lea(rscratch1, dst);
3205 jmp(rscratch1);
3206 }
3207 }
3208
3209 void MacroAssembler::jump_cc(Condition cc, AddressLiteral dst) {
3210 if (reachable(dst)) {
3211 InstructionMark im(this);
3212 relocate(dst.reloc());
3213 const int short_size = 2;
3214 const int long_size = 6;
3215 int offs = (intptr_t)dst.target() - ((intptr_t)pc());
3216 if (dst.reloc() == relocInfo::none && is8bit(offs - short_size)) {
3217 // 0111 tttn #8-bit disp
3218 emit_int8(0x70 | cc);
3219 emit_int8((offs - short_size) & 0xFF);
3220 } else {
3221 // 0000 1111 1000 tttn #32-bit disp
3222 emit_int8(0x0F);
3223 emit_int8((unsigned char)(0x80 | cc));
3224 emit_int32(offs - long_size);
3225 }
3226 } else {
3227 #ifdef ASSERT
3228 warning("reversing conditional branch");
3229 #endif /* ASSERT */
3230 Label skip;
3231 jccb(reverse[cc], skip);
3232 lea(rscratch1, dst);
3233 Assembler::jmp(rscratch1);
3234 bind(skip);
3235 }
3236 }
3237
3238 void MacroAssembler::ldmxcsr(AddressLiteral src) {
3239 if (reachable(src)) {
3240 Assembler::ldmxcsr(as_Address(src));
3241 } else {
3242 lea(rscratch1, src);
3243 Assembler::ldmxcsr(Address(rscratch1, 0));
3244 }
3245 }
3246
3247 int MacroAssembler::load_signed_byte(Register dst, Address src) {
3248 int off;
3249 if (LP64_ONLY(true ||) VM_Version::is_P6()) {
3250 off = offset();
3251 movsbl(dst, src); // movsxb
3252 } else {
3253 off = load_unsigned_byte(dst, src);
3254 shll(dst, 24);
3255 sarl(dst, 24);
3256 }
3257 return off;
3258 }
3259
3260 // Note: load_signed_short used to be called load_signed_word.
3261 // Although the 'w' in x86 opcodes refers to the term "word" in the assembler
3262 // manual, which means 16 bits, that usage is found nowhere in HotSpot code.
3263 // The term "word" in HotSpot means a 32- or 64-bit machine word.
3264 int MacroAssembler::load_signed_short(Register dst, Address src) {
3265 int off;
3266 if (LP64_ONLY(true ||) VM_Version::is_P6()) {
3267 // This is dubious to me since it seems safe to do a signed 16 => 64 bit
3268 // version but this is what 64bit has always done. This seems to imply
3269 // that users are only using 32bits worth.
3270 off = offset();
3271 movswl(dst, src); // movsxw
3272 } else {
3273 off = load_unsigned_short(dst, src);
3274 shll(dst, 16);
3275 sarl(dst, 16);
3276 }
3277 return off;
3278 }
3279
3280 int MacroAssembler::load_unsigned_byte(Register dst, Address src) {
3281 // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16,
3282 // and "3.9 Partial Register Penalties", p. 22).
3283 int off;
3284 if (LP64_ONLY(true || ) VM_Version::is_P6() || src.uses(dst)) {
3285 off = offset();
3286 movzbl(dst, src); // movzxb
3287 } else {
3288 xorl(dst, dst);
3289 off = offset();
3290 movb(dst, src);
3291 }
3292 return off;
3293 }
3294
3295 // Note: load_unsigned_short used to be called load_unsigned_word.
3296 int MacroAssembler::load_unsigned_short(Register dst, Address src) {
3297 // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16,
3298 // and "3.9 Partial Register Penalties", p. 22).
3299 int off;
3300 if (LP64_ONLY(true ||) VM_Version::is_P6() || src.uses(dst)) {
3301 off = offset();
3302 movzwl(dst, src); // movzxw
3303 } else {
3304 xorl(dst, dst);
3305 off = offset();
3306 movw(dst, src);
3307 }
3308 return off;
3309 }
3310
3311 void MacroAssembler::load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2) {
3312 switch (size_in_bytes) {
3313 #ifndef _LP64
3314 case 8:
3315 assert(dst2 != noreg, "second dest register required");
3316 movl(dst, src);
3317 movl(dst2, src.plus_disp(BytesPerInt));
3318 break;
3319 #else
3320 case 8: movq(dst, src); break;
3321 #endif
3322 case 4: movl(dst, src); break;
3323 case 2: is_signed ? load_signed_short(dst, src) : load_unsigned_short(dst, src); break;
3324 case 1: is_signed ? load_signed_byte( dst, src) : load_unsigned_byte( dst, src); break;
3325 default: ShouldNotReachHere();
3326 }
3327 }
3328
3329 void MacroAssembler::store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2) {
3330 switch (size_in_bytes) {
3331 #ifndef _LP64
3332 case 8:
3333 assert(src2 != noreg, "second source register required");
3334 movl(dst, src);
3335 movl(dst.plus_disp(BytesPerInt), src2);
3336 break;
3337 #else
3338 case 8: movq(dst, src); break;
3339 #endif
3340 case 4: movl(dst, src); break;
3341 case 2: movw(dst, src); break;
3342 case 1: movb(dst, src); break;
3343 default: ShouldNotReachHere();
3344 }
3345 }
3346
3347 void MacroAssembler::mov32(AddressLiteral dst, Register src) {
3348 if (reachable(dst)) {
3349 movl(as_Address(dst), src);
3350 } else {
3351 lea(rscratch1, dst);
3352 movl(Address(rscratch1, 0), src);
3353 }
3354 }
3355
3356 void MacroAssembler::mov32(Register dst, AddressLiteral src) {
3357 if (reachable(src)) {
3358 movl(dst, as_Address(src));
3359 } else {
3360 lea(rscratch1, src);
3361 movl(dst, Address(rscratch1, 0));
3362 }
3363 }
3364
3365 // C++ bool manipulation
3366
3367 void MacroAssembler::movbool(Register dst, Address src) {
3368 if(sizeof(bool) == 1)
3369 movb(dst, src);
3370 else if(sizeof(bool) == 2)
3371 movw(dst, src);
3372 else if(sizeof(bool) == 4)
3373 movl(dst, src);
3374 else
3375 // unsupported
3376 ShouldNotReachHere();
3377 }
3378
3379 void MacroAssembler::movbool(Address dst, bool boolconst) {
3380 if(sizeof(bool) == 1)
3381 movb(dst, (int) boolconst);
3382 else if(sizeof(bool) == 2)
3383 movw(dst, (int) boolconst);
3384 else if(sizeof(bool) == 4)
3385 movl(dst, (int) boolconst);
3386 else
3387 // unsupported
3388 ShouldNotReachHere();
3389 }
3390
3391 void MacroAssembler::movbool(Address dst, Register src) {
3392 if(sizeof(bool) == 1)
3393 movb(dst, src);
3394 else if(sizeof(bool) == 2)
3395 movw(dst, src);
3396 else if(sizeof(bool) == 4)
3397 movl(dst, src);
3398 else
3399 // unsupported
3400 ShouldNotReachHere();
3401 }
3402
3403 void MacroAssembler::movbyte(ArrayAddress dst, int src) {
3404 movb(as_Address(dst), src);
3405 }
3406
3407 void MacroAssembler::movdl(XMMRegister dst, AddressLiteral src) {
3408 if (reachable(src)) {
3409 movdl(dst, as_Address(src));
3410 } else {
3411 lea(rscratch1, src);
3412 movdl(dst, Address(rscratch1, 0));
3413 }
3414 }
3415
3416 void MacroAssembler::movq(XMMRegister dst, AddressLiteral src) {
3417 if (reachable(src)) {
3418 movq(dst, as_Address(src));
3419 } else {
3420 lea(rscratch1, src);
3421 movq(dst, Address(rscratch1, 0));
3422 }
3423 }
3424
3425 void MacroAssembler::setvectmask(Register dst, Register src) {
3426 Assembler::movl(dst, 1);
3427 Assembler::shlxl(dst, dst, src);
3428 Assembler::decl(dst);
3429 Assembler::kmovdl(k1, dst);
3430 Assembler::movl(dst, src);
3431 }
3432
3433 void MacroAssembler::restorevectmask() {
3434 Assembler::knotwl(k1, k0);
3435 }
3436
3437 void MacroAssembler::movdbl(XMMRegister dst, AddressLiteral src) {
3438 if (reachable(src)) {
3439 if (UseXmmLoadAndClearUpper) {
3440 movsd (dst, as_Address(src));
3441 } else {
3442 movlpd(dst, as_Address(src));
3443 }
3444 } else {
3445 lea(rscratch1, src);
3446 if (UseXmmLoadAndClearUpper) {
3447 movsd (dst, Address(rscratch1, 0));
3448 } else {
3449 movlpd(dst, Address(rscratch1, 0));
3450 }
3451 }
3452 }
3453
3454 void MacroAssembler::movflt(XMMRegister dst, AddressLiteral src) {
3455 if (reachable(src)) {
3456 movss(dst, as_Address(src));
3457 } else {
3458 lea(rscratch1, src);
3459 movss(dst, Address(rscratch1, 0));
3460 }
3461 }
3462
3463 void MacroAssembler::movptr(Register dst, Register src) {
3464 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
3465 }
3466
3467 void MacroAssembler::movptr(Register dst, Address src) {
3468 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
3469 }
3470
3471 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
3472 void MacroAssembler::movptr(Register dst, intptr_t src) {
3473 LP64_ONLY(mov64(dst, src)) NOT_LP64(movl(dst, src));
3474 }
3475
3476 void MacroAssembler::movptr(Address dst, Register src) {
3477 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
3478 }
3479
3480 void MacroAssembler::movdqu(Address dst, XMMRegister src) {
3481 if (UseAVX > 2 && !VM_Version::supports_avx512vl() && (src->encoding() > 15)) {
3482 Assembler::vextractf32x4(dst, src, 0);
3483 } else {
3484 Assembler::movdqu(dst, src);
3485 }
3486 }
3487
3488 void MacroAssembler::movdqu(XMMRegister dst, Address src) {
3489 if (UseAVX > 2 && !VM_Version::supports_avx512vl() && (dst->encoding() > 15)) {
3490 Assembler::vinsertf32x4(dst, dst, src, 0);
3491 } else {
3492 Assembler::movdqu(dst, src);
3493 }
3494 }
3495
3496 void MacroAssembler::movdqu(XMMRegister dst, XMMRegister src) {
3497 if (UseAVX > 2 && !VM_Version::supports_avx512vl()) {
3498 Assembler::evmovdqul(dst, src, Assembler::AVX_512bit);
3499 } else {
3500 Assembler::movdqu(dst, src);
3501 }
3502 }
3503
3504 void MacroAssembler::movdqu(XMMRegister dst, AddressLiteral src, Register scratchReg) {
3505 if (reachable(src)) {
3506 movdqu(dst, as_Address(src));
3507 } else {
3508 lea(scratchReg, src);
3509 movdqu(dst, Address(scratchReg, 0));
3510 }
3511 }
3512
3513 void MacroAssembler::vmovdqu(Address dst, XMMRegister src) {
3514 if (UseAVX > 2 && !VM_Version::supports_avx512vl() && (src->encoding() > 15)) {
3515 vextractf64x4_low(dst, src);
3516 } else {
3517 Assembler::vmovdqu(dst, src);
3518 }
3519 }
3520
3521 void MacroAssembler::vmovdqu(XMMRegister dst, Address src) {
3522 if (UseAVX > 2 && !VM_Version::supports_avx512vl() && (dst->encoding() > 15)) {
3523 vinsertf64x4_low(dst, src);
3524 } else {
3525 Assembler::vmovdqu(dst, src);
3526 }
3527 }
3528
3529 void MacroAssembler::vmovdqu(XMMRegister dst, XMMRegister src) {
3530 if (UseAVX > 2 && !VM_Version::supports_avx512vl()) {
3531 Assembler::evmovdqul(dst, src, Assembler::AVX_512bit);
3532 }
3533 else {
3534 Assembler::vmovdqu(dst, src);
3535 }
3536 }
3537
3538 void MacroAssembler::vmovdqu(XMMRegister dst, AddressLiteral src) {
3539 if (reachable(src)) {
3540 vmovdqu(dst, as_Address(src));
3541 }
3542 else {
3543 lea(rscratch1, src);
3544 vmovdqu(dst, Address(rscratch1, 0));
3545 }
3546 }
3547
3548 void MacroAssembler::movdqa(XMMRegister dst, AddressLiteral src) {
3549 if (reachable(src)) {
3550 Assembler::movdqa(dst, as_Address(src));
3551 } else {
3552 lea(rscratch1, src);
3553 Assembler::movdqa(dst, Address(rscratch1, 0));
3554 }
3555 }
3556
3557 void MacroAssembler::movsd(XMMRegister dst, AddressLiteral src) {
3558 if (reachable(src)) {
3559 Assembler::movsd(dst, as_Address(src));
3560 } else {
3561 lea(rscratch1, src);
3562 Assembler::movsd(dst, Address(rscratch1, 0));
3563 }
3564 }
3565
3566 void MacroAssembler::movss(XMMRegister dst, AddressLiteral src) {
3567 if (reachable(src)) {
3568 Assembler::movss(dst, as_Address(src));
3569 } else {
3570 lea(rscratch1, src);
3571 Assembler::movss(dst, Address(rscratch1, 0));
3572 }
3573 }
3574
3575 void MacroAssembler::mulsd(XMMRegister dst, AddressLiteral src) {
3576 if (reachable(src)) {
3577 Assembler::mulsd(dst, as_Address(src));
3578 } else {
3579 lea(rscratch1, src);
3580 Assembler::mulsd(dst, Address(rscratch1, 0));
3581 }
3582 }
3583
3584 void MacroAssembler::mulss(XMMRegister dst, AddressLiteral src) {
3585 if (reachable(src)) {
3586 Assembler::mulss(dst, as_Address(src));
3587 } else {
3588 lea(rscratch1, src);
3589 Assembler::mulss(dst, Address(rscratch1, 0));
3590 }
3591 }
3592
3593 void MacroAssembler::null_check(Register reg, int offset) {
3594 if (needs_explicit_null_check(offset)) {
3595 // provoke OS NULL exception if reg = NULL by
3596 // accessing M[reg] w/o changing any (non-CC) registers
3597 // NOTE: cmpl is plenty here to provoke a segv
3598 cmpptr(rax, Address(reg, 0));
3599 // Note: should probably use testl(rax, Address(reg, 0));
3600 // may be shorter code (however, this version of
3601 // testl needs to be implemented first)
3602 } else {
3603 // nothing to do, (later) access of M[reg + offset]
3604 // will provoke OS NULL exception if reg = NULL
3605 }
3606 }
3607
3608 void MacroAssembler::os_breakpoint() {
3609 // instead of directly emitting a breakpoint, call os:breakpoint for better debugability
3610 // (e.g., MSVC can't call ps() otherwise)
3611 call(RuntimeAddress(CAST_FROM_FN_PTR(address, os::breakpoint)));
3612 }
3613
3614 #ifdef _LP64
3615 #define XSTATE_BV 0x200
3616 #endif
3617
3618 void MacroAssembler::pop_CPU_state() {
3619 pop_FPU_state();
3620 pop_IU_state();
3621 }
3622
3623 void MacroAssembler::pop_FPU_state() {
3624 #ifndef _LP64
3625 frstor(Address(rsp, 0));
3626 #else
3627 fxrstor(Address(rsp, 0));
3628 #endif
3629 addptr(rsp, FPUStateSizeInWords * wordSize);
3630 }
3631
3632 void MacroAssembler::pop_IU_state() {
3633 popa();
3634 LP64_ONLY(addq(rsp, 8));
3635 popf();
3636 }
3637
3638 // Save Integer and Float state
3639 // Warning: Stack must be 16 byte aligned (64bit)
3640 void MacroAssembler::push_CPU_state() {
3641 push_IU_state();
3642 push_FPU_state();
3643 }
3644
3645 void MacroAssembler::push_FPU_state() {
3646 subptr(rsp, FPUStateSizeInWords * wordSize);
3647 #ifndef _LP64
3648 fnsave(Address(rsp, 0));
3649 fwait();
3650 #else
3651 fxsave(Address(rsp, 0));
3652 #endif // LP64
3653 }
3654
3655 void MacroAssembler::push_IU_state() {
3656 // Push flags first because pusha kills them
3657 pushf();
3658 // Make sure rsp stays 16-byte aligned
3659 LP64_ONLY(subq(rsp, 8));
3660 pusha();
3661 }
3662
3663 void MacroAssembler::reset_last_Java_frame(Register java_thread, bool clear_fp) { // determine java_thread register
3664 if (!java_thread->is_valid()) {
3665 java_thread = rdi;
3666 get_thread(java_thread);
3667 }
3668 // we must set sp to zero to clear frame
3669 movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), NULL_WORD);
3670 if (clear_fp) {
3671 movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), NULL_WORD);
3672 }
3673
3674 // Always clear the pc because it could have been set by make_walkable()
3675 movptr(Address(java_thread, JavaThread::last_Java_pc_offset()), NULL_WORD);
3676
3677 vzeroupper();
3678 }
3679
3680 void MacroAssembler::restore_rax(Register tmp) {
3681 if (tmp == noreg) pop(rax);
3682 else if (tmp != rax) mov(rax, tmp);
3683 }
3684
3685 void MacroAssembler::round_to(Register reg, int modulus) {
3686 addptr(reg, modulus - 1);
3687 andptr(reg, -modulus);
3688 }
3689
3690 void MacroAssembler::save_rax(Register tmp) {
3691 if (tmp == noreg) push(rax);
3692 else if (tmp != rax) mov(tmp, rax);
3693 }
3694
3695 // Write serialization page so VM thread can do a pseudo remote membar.
3696 // We use the current thread pointer to calculate a thread specific
3697 // offset to write to within the page. This minimizes bus traffic
3698 // due to cache line collision.
3699 void MacroAssembler::serialize_memory(Register thread, Register tmp) {
3700 movl(tmp, thread);
3701 shrl(tmp, os::get_serialize_page_shift_count());
3702 andl(tmp, (os::vm_page_size() - sizeof(int)));
3703
3704 Address index(noreg, tmp, Address::times_1);
3705 ExternalAddress page(os::get_memory_serialize_page());
3706
3707 // Size of store must match masking code above
3708 movl(as_Address(ArrayAddress(page, index)), tmp);
3709 }
3710
3711 // Calls to C land
3712 //
3713 // When entering C land, the rbp, & rsp of the last Java frame have to be recorded
3714 // in the (thread-local) JavaThread object. When leaving C land, the last Java fp
3715 // has to be reset to 0. This is required to allow proper stack traversal.
3716 void MacroAssembler::set_last_Java_frame(Register java_thread,
3717 Register last_java_sp,
3718 Register last_java_fp,
3719 address last_java_pc) {
3720 vzeroupper();
3721 // determine java_thread register
3722 if (!java_thread->is_valid()) {
3723 java_thread = rdi;
3724 get_thread(java_thread);
3725 }
3726 // determine last_java_sp register
3727 if (!last_java_sp->is_valid()) {
3728 last_java_sp = rsp;
3729 }
3730
3731 // last_java_fp is optional
3732
3733 if (last_java_fp->is_valid()) {
3734 movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), last_java_fp);
3735 }
3736
3737 // last_java_pc is optional
3738
3739 if (last_java_pc != NULL) {
3740 lea(Address(java_thread,
3741 JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset()),
3742 InternalAddress(last_java_pc));
3743
3744 }
3745 movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), last_java_sp);
3746 }
3747
3748 void MacroAssembler::shlptr(Register dst, int imm8) {
3749 LP64_ONLY(shlq(dst, imm8)) NOT_LP64(shll(dst, imm8));
3750 }
3751
3752 void MacroAssembler::shrptr(Register dst, int imm8) {
3753 LP64_ONLY(shrq(dst, imm8)) NOT_LP64(shrl(dst, imm8));
3754 }
3755
3756 void MacroAssembler::sign_extend_byte(Register reg) {
3757 if (LP64_ONLY(true ||) (VM_Version::is_P6() && reg->has_byte_register())) {
3758 movsbl(reg, reg); // movsxb
3759 } else {
3760 shll(reg, 24);
3761 sarl(reg, 24);
3762 }
3763 }
3764
3765 void MacroAssembler::sign_extend_short(Register reg) {
3766 if (LP64_ONLY(true ||) VM_Version::is_P6()) {
3767 movswl(reg, reg); // movsxw
3768 } else {
3769 shll(reg, 16);
3770 sarl(reg, 16);
3771 }
3772 }
3773
3774 void MacroAssembler::testl(Register dst, AddressLiteral src) {
3775 assert(reachable(src), "Address should be reachable");
3776 testl(dst, as_Address(src));
3777 }
3778
3779 void MacroAssembler::pcmpeqb(XMMRegister dst, XMMRegister src) {
3780 int dst_enc = dst->encoding();
3781 int src_enc = src->encoding();
3782 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
3783 Assembler::pcmpeqb(dst, src);
3784 } else if ((dst_enc < 16) && (src_enc < 16)) {
3785 Assembler::pcmpeqb(dst, src);
3786 } else if (src_enc < 16) {
3787 subptr(rsp, 64);
3788 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3789 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
3790 Assembler::pcmpeqb(xmm0, src);
3791 movdqu(dst, xmm0);
3792 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3793 addptr(rsp, 64);
3794 } else if (dst_enc < 16) {
3795 subptr(rsp, 64);
3796 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3797 evmovdqul(xmm0, src, Assembler::AVX_512bit);
3798 Assembler::pcmpeqb(dst, xmm0);
3799 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3800 addptr(rsp, 64);
3801 } else {
3802 subptr(rsp, 64);
3803 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3804 subptr(rsp, 64);
3805 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
3806 movdqu(xmm0, src);
3807 movdqu(xmm1, dst);
3808 Assembler::pcmpeqb(xmm1, xmm0);
3809 movdqu(dst, xmm1);
3810 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
3811 addptr(rsp, 64);
3812 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3813 addptr(rsp, 64);
3814 }
3815 }
3816
3817 void MacroAssembler::pcmpeqw(XMMRegister dst, XMMRegister src) {
3818 int dst_enc = dst->encoding();
3819 int src_enc = src->encoding();
3820 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
3821 Assembler::pcmpeqw(dst, src);
3822 } else if ((dst_enc < 16) && (src_enc < 16)) {
3823 Assembler::pcmpeqw(dst, src);
3824 } else if (src_enc < 16) {
3825 subptr(rsp, 64);
3826 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3827 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
3828 Assembler::pcmpeqw(xmm0, src);
3829 movdqu(dst, xmm0);
3830 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3831 addptr(rsp, 64);
3832 } else if (dst_enc < 16) {
3833 subptr(rsp, 64);
3834 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3835 evmovdqul(xmm0, src, Assembler::AVX_512bit);
3836 Assembler::pcmpeqw(dst, xmm0);
3837 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3838 addptr(rsp, 64);
3839 } else {
3840 subptr(rsp, 64);
3841 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3842 subptr(rsp, 64);
3843 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
3844 movdqu(xmm0, src);
3845 movdqu(xmm1, dst);
3846 Assembler::pcmpeqw(xmm1, xmm0);
3847 movdqu(dst, xmm1);
3848 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
3849 addptr(rsp, 64);
3850 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3851 addptr(rsp, 64);
3852 }
3853 }
3854
3855 void MacroAssembler::pcmpestri(XMMRegister dst, Address src, int imm8) {
3856 int dst_enc = dst->encoding();
3857 if (dst_enc < 16) {
3858 Assembler::pcmpestri(dst, src, imm8);
3859 } else {
3860 subptr(rsp, 64);
3861 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3862 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
3863 Assembler::pcmpestri(xmm0, src, imm8);
3864 movdqu(dst, xmm0);
3865 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3866 addptr(rsp, 64);
3867 }
3868 }
3869
3870 void MacroAssembler::pcmpestri(XMMRegister dst, XMMRegister src, int imm8) {
3871 int dst_enc = dst->encoding();
3872 int src_enc = src->encoding();
3873 if ((dst_enc < 16) && (src_enc < 16)) {
3874 Assembler::pcmpestri(dst, src, imm8);
3875 } else if (src_enc < 16) {
3876 subptr(rsp, 64);
3877 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3878 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
3879 Assembler::pcmpestri(xmm0, src, imm8);
3880 movdqu(dst, xmm0);
3881 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3882 addptr(rsp, 64);
3883 } else if (dst_enc < 16) {
3884 subptr(rsp, 64);
3885 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3886 evmovdqul(xmm0, src, Assembler::AVX_512bit);
3887 Assembler::pcmpestri(dst, xmm0, imm8);
3888 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3889 addptr(rsp, 64);
3890 } else {
3891 subptr(rsp, 64);
3892 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3893 subptr(rsp, 64);
3894 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
3895 movdqu(xmm0, src);
3896 movdqu(xmm1, dst);
3897 Assembler::pcmpestri(xmm1, xmm0, imm8);
3898 movdqu(dst, xmm1);
3899 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
3900 addptr(rsp, 64);
3901 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3902 addptr(rsp, 64);
3903 }
3904 }
3905
3906 void MacroAssembler::pmovzxbw(XMMRegister dst, XMMRegister src) {
3907 int dst_enc = dst->encoding();
3908 int src_enc = src->encoding();
3909 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
3910 Assembler::pmovzxbw(dst, src);
3911 } else if ((dst_enc < 16) && (src_enc < 16)) {
3912 Assembler::pmovzxbw(dst, src);
3913 } else if (src_enc < 16) {
3914 subptr(rsp, 64);
3915 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3916 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
3917 Assembler::pmovzxbw(xmm0, src);
3918 movdqu(dst, xmm0);
3919 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3920 addptr(rsp, 64);
3921 } else if (dst_enc < 16) {
3922 subptr(rsp, 64);
3923 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3924 evmovdqul(xmm0, src, Assembler::AVX_512bit);
3925 Assembler::pmovzxbw(dst, xmm0);
3926 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3927 addptr(rsp, 64);
3928 } else {
3929 subptr(rsp, 64);
3930 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3931 subptr(rsp, 64);
3932 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
3933 movdqu(xmm0, src);
3934 movdqu(xmm1, dst);
3935 Assembler::pmovzxbw(xmm1, xmm0);
3936 movdqu(dst, xmm1);
3937 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
3938 addptr(rsp, 64);
3939 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3940 addptr(rsp, 64);
3941 }
3942 }
3943
3944 void MacroAssembler::pmovzxbw(XMMRegister dst, Address src) {
3945 int dst_enc = dst->encoding();
3946 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
3947 Assembler::pmovzxbw(dst, src);
3948 } else if (dst_enc < 16) {
3949 Assembler::pmovzxbw(dst, src);
3950 } else {
3951 subptr(rsp, 64);
3952 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3953 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
3954 Assembler::pmovzxbw(xmm0, src);
3955 movdqu(dst, xmm0);
3956 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3957 addptr(rsp, 64);
3958 }
3959 }
3960
3961 void MacroAssembler::pmovmskb(Register dst, XMMRegister src) {
3962 int src_enc = src->encoding();
3963 if (src_enc < 16) {
3964 Assembler::pmovmskb(dst, src);
3965 } else {
3966 subptr(rsp, 64);
3967 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3968 evmovdqul(xmm0, src, Assembler::AVX_512bit);
3969 Assembler::pmovmskb(dst, xmm0);
3970 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3971 addptr(rsp, 64);
3972 }
3973 }
3974
3975 void MacroAssembler::ptest(XMMRegister dst, XMMRegister src) {
3976 int dst_enc = dst->encoding();
3977 int src_enc = src->encoding();
3978 if ((dst_enc < 16) && (src_enc < 16)) {
3979 Assembler::ptest(dst, src);
3980 } else if (src_enc < 16) {
3981 subptr(rsp, 64);
3982 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3983 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
3984 Assembler::ptest(xmm0, src);
3985 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3986 addptr(rsp, 64);
3987 } else if (dst_enc < 16) {
3988 subptr(rsp, 64);
3989 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3990 evmovdqul(xmm0, src, Assembler::AVX_512bit);
3991 Assembler::ptest(dst, xmm0);
3992 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3993 addptr(rsp, 64);
3994 } else {
3995 subptr(rsp, 64);
3996 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3997 subptr(rsp, 64);
3998 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
3999 movdqu(xmm0, src);
4000 movdqu(xmm1, dst);
4001 Assembler::ptest(xmm1, xmm0);
4002 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
4003 addptr(rsp, 64);
4004 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4005 addptr(rsp, 64);
4006 }
4007 }
4008
4009 void MacroAssembler::sqrtsd(XMMRegister dst, AddressLiteral src) {
4010 if (reachable(src)) {
4011 Assembler::sqrtsd(dst, as_Address(src));
4012 } else {
4013 lea(rscratch1, src);
4014 Assembler::sqrtsd(dst, Address(rscratch1, 0));
4015 }
4016 }
4017
4018 void MacroAssembler::sqrtss(XMMRegister dst, AddressLiteral src) {
4019 if (reachable(src)) {
4020 Assembler::sqrtss(dst, as_Address(src));
4021 } else {
4022 lea(rscratch1, src);
4023 Assembler::sqrtss(dst, Address(rscratch1, 0));
4024 }
4025 }
4026
4027 void MacroAssembler::subsd(XMMRegister dst, AddressLiteral src) {
4028 if (reachable(src)) {
4029 Assembler::subsd(dst, as_Address(src));
4030 } else {
4031 lea(rscratch1, src);
4032 Assembler::subsd(dst, Address(rscratch1, 0));
4033 }
4034 }
4035
4036 void MacroAssembler::subss(XMMRegister dst, AddressLiteral src) {
4037 if (reachable(src)) {
4038 Assembler::subss(dst, as_Address(src));
4039 } else {
4040 lea(rscratch1, src);
4041 Assembler::subss(dst, Address(rscratch1, 0));
4042 }
4043 }
4044
4045 void MacroAssembler::ucomisd(XMMRegister dst, AddressLiteral src) {
4046 if (reachable(src)) {
4047 Assembler::ucomisd(dst, as_Address(src));
4048 } else {
4049 lea(rscratch1, src);
4050 Assembler::ucomisd(dst, Address(rscratch1, 0));
4051 }
4052 }
4053
4054 void MacroAssembler::ucomiss(XMMRegister dst, AddressLiteral src) {
4055 if (reachable(src)) {
4056 Assembler::ucomiss(dst, as_Address(src));
4057 } else {
4058 lea(rscratch1, src);
4059 Assembler::ucomiss(dst, Address(rscratch1, 0));
4060 }
4061 }
4062
4063 void MacroAssembler::xorpd(XMMRegister dst, AddressLiteral src) {
4064 // Used in sign-bit flipping with aligned address.
4065 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
4066 if (reachable(src)) {
4067 Assembler::xorpd(dst, as_Address(src));
4068 } else {
4069 lea(rscratch1, src);
4070 Assembler::xorpd(dst, Address(rscratch1, 0));
4071 }
4072 }
4073
4074 void MacroAssembler::xorpd(XMMRegister dst, XMMRegister src) {
4075 if (UseAVX > 2 && !VM_Version::supports_avx512dq() && (dst->encoding() == src->encoding())) {
4076 Assembler::vpxor(dst, dst, src, Assembler::AVX_512bit);
4077 }
4078 else {
4079 Assembler::xorpd(dst, src);
4080 }
4081 }
4082
4083 void MacroAssembler::xorps(XMMRegister dst, XMMRegister src) {
4084 if (UseAVX > 2 && !VM_Version::supports_avx512dq() && (dst->encoding() == src->encoding())) {
4085 Assembler::vpxor(dst, dst, src, Assembler::AVX_512bit);
4086 } else {
4087 Assembler::xorps(dst, src);
4088 }
4089 }
4090
4091 void MacroAssembler::xorps(XMMRegister dst, AddressLiteral src) {
4092 // Used in sign-bit flipping with aligned address.
4093 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
4094 if (reachable(src)) {
4095 Assembler::xorps(dst, as_Address(src));
4096 } else {
4097 lea(rscratch1, src);
4098 Assembler::xorps(dst, Address(rscratch1, 0));
4099 }
4100 }
4101
4102 void MacroAssembler::pshufb(XMMRegister dst, AddressLiteral src) {
4103 // Used in sign-bit flipping with aligned address.
4104 bool aligned_adr = (((intptr_t)src.target() & 15) == 0);
4105 assert((UseAVX > 0) || aligned_adr, "SSE mode requires address alignment 16 bytes");
4106 if (reachable(src)) {
4107 Assembler::pshufb(dst, as_Address(src));
4108 } else {
4109 lea(rscratch1, src);
4110 Assembler::pshufb(dst, Address(rscratch1, 0));
4111 }
4112 }
4113
4114 // AVX 3-operands instructions
4115
4116 void MacroAssembler::vaddsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
4117 if (reachable(src)) {
4118 vaddsd(dst, nds, as_Address(src));
4119 } else {
4120 lea(rscratch1, src);
4121 vaddsd(dst, nds, Address(rscratch1, 0));
4122 }
4123 }
4124
4125 void MacroAssembler::vaddss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
4126 if (reachable(src)) {
4127 vaddss(dst, nds, as_Address(src));
4128 } else {
4129 lea(rscratch1, src);
4130 vaddss(dst, nds, Address(rscratch1, 0));
4131 }
4132 }
4133
4134 void MacroAssembler::vabsss(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len) {
4135 int dst_enc = dst->encoding();
4136 int nds_enc = nds->encoding();
4137 int src_enc = src->encoding();
4138 if ((dst_enc < 16) && (nds_enc < 16)) {
4139 vandps(dst, nds, negate_field, vector_len);
4140 } else if ((src_enc < 16) && (dst_enc < 16)) {
4141 movss(src, nds);
4142 vandps(dst, src, negate_field, vector_len);
4143 } else if (src_enc < 16) {
4144 movss(src, nds);
4145 vandps(src, src, negate_field, vector_len);
4146 movss(dst, src);
4147 } else if (dst_enc < 16) {
4148 movdqu(src, xmm0);
4149 movss(xmm0, nds);
4150 vandps(dst, xmm0, negate_field, vector_len);
4151 movdqu(xmm0, src);
4152 } else if (nds_enc < 16) {
4153 movdqu(src, xmm0);
4154 vandps(xmm0, nds, negate_field, vector_len);
4155 movss(dst, xmm0);
4156 movdqu(xmm0, src);
4157 } else {
4158 movdqu(src, xmm0);
4159 movss(xmm0, nds);
4160 vandps(xmm0, xmm0, negate_field, vector_len);
4161 movss(dst, xmm0);
4162 movdqu(xmm0, src);
4163 }
4164 }
4165
4166 void MacroAssembler::vabssd(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len) {
4167 int dst_enc = dst->encoding();
4168 int nds_enc = nds->encoding();
4169 int src_enc = src->encoding();
4170 if ((dst_enc < 16) && (nds_enc < 16)) {
4171 vandpd(dst, nds, negate_field, vector_len);
4172 } else if ((src_enc < 16) && (dst_enc < 16)) {
4173 movsd(src, nds);
4174 vandpd(dst, src, negate_field, vector_len);
4175 } else if (src_enc < 16) {
4176 movsd(src, nds);
4177 vandpd(src, src, negate_field, vector_len);
4178 movsd(dst, src);
4179 } else if (dst_enc < 16) {
4180 movdqu(src, xmm0);
4181 movsd(xmm0, nds);
4182 vandpd(dst, xmm0, negate_field, vector_len);
4183 movdqu(xmm0, src);
4184 } else if (nds_enc < 16) {
4185 movdqu(src, xmm0);
4186 vandpd(xmm0, nds, negate_field, vector_len);
4187 movsd(dst, xmm0);
4188 movdqu(xmm0, src);
4189 } else {
4190 movdqu(src, xmm0);
4191 movsd(xmm0, nds);
4192 vandpd(xmm0, xmm0, negate_field, vector_len);
4193 movsd(dst, xmm0);
4194 movdqu(xmm0, src);
4195 }
4196 }
4197
4198 void MacroAssembler::vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4199 int dst_enc = dst->encoding();
4200 int nds_enc = nds->encoding();
4201 int src_enc = src->encoding();
4202 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4203 Assembler::vpaddb(dst, nds, src, vector_len);
4204 } else if ((dst_enc < 16) && (src_enc < 16)) {
4205 Assembler::vpaddb(dst, dst, src, vector_len);
4206 } else if ((dst_enc < 16) && (nds_enc < 16)) {
4207 // use nds as scratch for src
4208 evmovdqul(nds, src, Assembler::AVX_512bit);
4209 Assembler::vpaddb(dst, dst, nds, vector_len);
4210 } else if ((src_enc < 16) && (nds_enc < 16)) {
4211 // use nds as scratch for dst
4212 evmovdqul(nds, dst, Assembler::AVX_512bit);
4213 Assembler::vpaddb(nds, nds, src, vector_len);
4214 evmovdqul(dst, nds, Assembler::AVX_512bit);
4215 } else if (dst_enc < 16) {
4216 // use nds as scatch for xmm0 to hold src
4217 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4218 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4219 Assembler::vpaddb(dst, dst, xmm0, vector_len);
4220 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4221 } else {
4222 // worse case scenario, all regs are in the upper bank
4223 subptr(rsp, 64);
4224 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
4225 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4226 evmovdqul(xmm1, src, Assembler::AVX_512bit);
4227 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4228 Assembler::vpaddb(xmm0, xmm0, xmm1, vector_len);
4229 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4230 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4231 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
4232 addptr(rsp, 64);
4233 }
4234 }
4235
4236 void MacroAssembler::vpaddb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4237 int dst_enc = dst->encoding();
4238 int nds_enc = nds->encoding();
4239 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4240 Assembler::vpaddb(dst, nds, src, vector_len);
4241 } else if (dst_enc < 16) {
4242 Assembler::vpaddb(dst, dst, src, vector_len);
4243 } else if (nds_enc < 16) {
4244 // implies dst_enc in upper bank with src as scratch
4245 evmovdqul(nds, dst, Assembler::AVX_512bit);
4246 Assembler::vpaddb(nds, nds, src, vector_len);
4247 evmovdqul(dst, nds, Assembler::AVX_512bit);
4248 } else {
4249 // worse case scenario, all regs in upper bank
4250 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4251 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4252 Assembler::vpaddb(xmm0, xmm0, src, vector_len);
4253 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4254 }
4255 }
4256
4257 void MacroAssembler::vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4258 int dst_enc = dst->encoding();
4259 int nds_enc = nds->encoding();
4260 int src_enc = src->encoding();
4261 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4262 Assembler::vpaddw(dst, nds, src, vector_len);
4263 } else if ((dst_enc < 16) && (src_enc < 16)) {
4264 Assembler::vpaddw(dst, dst, src, vector_len);
4265 } else if ((dst_enc < 16) && (nds_enc < 16)) {
4266 // use nds as scratch for src
4267 evmovdqul(nds, src, Assembler::AVX_512bit);
4268 Assembler::vpaddw(dst, dst, nds, vector_len);
4269 } else if ((src_enc < 16) && (nds_enc < 16)) {
4270 // use nds as scratch for dst
4271 evmovdqul(nds, dst, Assembler::AVX_512bit);
4272 Assembler::vpaddw(nds, nds, src, vector_len);
4273 evmovdqul(dst, nds, Assembler::AVX_512bit);
4274 } else if (dst_enc < 16) {
4275 // use nds as scatch for xmm0 to hold src
4276 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4277 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4278 Assembler::vpaddw(dst, dst, xmm0, vector_len);
4279 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4280 } else {
4281 // worse case scenario, all regs are in the upper bank
4282 subptr(rsp, 64);
4283 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
4284 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4285 evmovdqul(xmm1, src, Assembler::AVX_512bit);
4286 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4287 Assembler::vpaddw(xmm0, xmm0, xmm1, vector_len);
4288 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4289 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4290 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
4291 addptr(rsp, 64);
4292 }
4293 }
4294
4295 void MacroAssembler::vpaddw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4296 int dst_enc = dst->encoding();
4297 int nds_enc = nds->encoding();
4298 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4299 Assembler::vpaddw(dst, nds, src, vector_len);
4300 } else if (dst_enc < 16) {
4301 Assembler::vpaddw(dst, dst, src, vector_len);
4302 } else if (nds_enc < 16) {
4303 // implies dst_enc in upper bank with src as scratch
4304 evmovdqul(nds, dst, Assembler::AVX_512bit);
4305 Assembler::vpaddw(nds, nds, src, vector_len);
4306 evmovdqul(dst, nds, Assembler::AVX_512bit);
4307 } else {
4308 // worse case scenario, all regs in upper bank
4309 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4310 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4311 Assembler::vpaddw(xmm0, xmm0, src, vector_len);
4312 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4313 }
4314 }
4315
4316 void MacroAssembler::vpand(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len) {
4317 if (reachable(src)) {
4318 Assembler::vpand(dst, nds, as_Address(src), vector_len);
4319 } else {
4320 lea(rscratch1, src);
4321 Assembler::vpand(dst, nds, Address(rscratch1, 0), vector_len);
4322 }
4323 }
4324
4325 void MacroAssembler::vpbroadcastw(XMMRegister dst, XMMRegister src) {
4326 int dst_enc = dst->encoding();
4327 int src_enc = src->encoding();
4328 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4329 Assembler::vpbroadcastw(dst, src);
4330 } else if ((dst_enc < 16) && (src_enc < 16)) {
4331 Assembler::vpbroadcastw(dst, src);
4332 } else if (src_enc < 16) {
4333 subptr(rsp, 64);
4334 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4335 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4336 Assembler::vpbroadcastw(xmm0, src);
4337 movdqu(dst, xmm0);
4338 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4339 addptr(rsp, 64);
4340 } else if (dst_enc < 16) {
4341 subptr(rsp, 64);
4342 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4343 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4344 Assembler::vpbroadcastw(dst, xmm0);
4345 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4346 addptr(rsp, 64);
4347 } else {
4348 subptr(rsp, 64);
4349 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4350 subptr(rsp, 64);
4351 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
4352 movdqu(xmm0, src);
4353 movdqu(xmm1, dst);
4354 Assembler::vpbroadcastw(xmm1, xmm0);
4355 movdqu(dst, xmm1);
4356 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
4357 addptr(rsp, 64);
4358 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4359 addptr(rsp, 64);
4360 }
4361 }
4362
4363 void MacroAssembler::vpcmpeqb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4364 int dst_enc = dst->encoding();
4365 int nds_enc = nds->encoding();
4366 int src_enc = src->encoding();
4367 assert(dst_enc == nds_enc, "");
4368 if ((dst_enc < 16) && (src_enc < 16)) {
4369 Assembler::vpcmpeqb(dst, nds, src, vector_len);
4370 } else if (src_enc < 16) {
4371 subptr(rsp, 64);
4372 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4373 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4374 Assembler::vpcmpeqb(xmm0, xmm0, src, vector_len);
4375 movdqu(dst, xmm0);
4376 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4377 addptr(rsp, 64);
4378 } else if (dst_enc < 16) {
4379 subptr(rsp, 64);
4380 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4381 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4382 Assembler::vpcmpeqb(dst, dst, xmm0, vector_len);
4383 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4384 addptr(rsp, 64);
4385 } else {
4386 subptr(rsp, 64);
4387 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4388 subptr(rsp, 64);
4389 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
4390 movdqu(xmm0, src);
4391 movdqu(xmm1, dst);
4392 Assembler::vpcmpeqb(xmm1, xmm1, xmm0, vector_len);
4393 movdqu(dst, xmm1);
4394 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
4395 addptr(rsp, 64);
4396 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4397 addptr(rsp, 64);
4398 }
4399 }
4400
4401 void MacroAssembler::vpcmpeqw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4402 int dst_enc = dst->encoding();
4403 int nds_enc = nds->encoding();
4404 int src_enc = src->encoding();
4405 assert(dst_enc == nds_enc, "");
4406 if ((dst_enc < 16) && (src_enc < 16)) {
4407 Assembler::vpcmpeqw(dst, nds, src, vector_len);
4408 } else if (src_enc < 16) {
4409 subptr(rsp, 64);
4410 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4411 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4412 Assembler::vpcmpeqw(xmm0, xmm0, src, vector_len);
4413 movdqu(dst, xmm0);
4414 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4415 addptr(rsp, 64);
4416 } else if (dst_enc < 16) {
4417 subptr(rsp, 64);
4418 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4419 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4420 Assembler::vpcmpeqw(dst, dst, xmm0, vector_len);
4421 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4422 addptr(rsp, 64);
4423 } else {
4424 subptr(rsp, 64);
4425 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4426 subptr(rsp, 64);
4427 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
4428 movdqu(xmm0, src);
4429 movdqu(xmm1, dst);
4430 Assembler::vpcmpeqw(xmm1, xmm1, xmm0, vector_len);
4431 movdqu(dst, xmm1);
4432 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
4433 addptr(rsp, 64);
4434 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4435 addptr(rsp, 64);
4436 }
4437 }
4438
4439 void MacroAssembler::vpmovzxbw(XMMRegister dst, Address src, int vector_len) {
4440 int dst_enc = dst->encoding();
4441 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4442 Assembler::vpmovzxbw(dst, src, vector_len);
4443 } else if (dst_enc < 16) {
4444 Assembler::vpmovzxbw(dst, src, vector_len);
4445 } else {
4446 subptr(rsp, 64);
4447 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4448 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4449 Assembler::vpmovzxbw(xmm0, src, vector_len);
4450 movdqu(dst, xmm0);
4451 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4452 addptr(rsp, 64);
4453 }
4454 }
4455
4456 void MacroAssembler::vpmovmskb(Register dst, XMMRegister src) {
4457 int src_enc = src->encoding();
4458 if (src_enc < 16) {
4459 Assembler::vpmovmskb(dst, src);
4460 } else {
4461 subptr(rsp, 64);
4462 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4463 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4464 Assembler::vpmovmskb(dst, xmm0);
4465 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4466 addptr(rsp, 64);
4467 }
4468 }
4469
4470 void MacroAssembler::vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4471 int dst_enc = dst->encoding();
4472 int nds_enc = nds->encoding();
4473 int src_enc = src->encoding();
4474 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4475 Assembler::vpmullw(dst, nds, src, vector_len);
4476 } else if ((dst_enc < 16) && (src_enc < 16)) {
4477 Assembler::vpmullw(dst, dst, src, vector_len);
4478 } else if ((dst_enc < 16) && (nds_enc < 16)) {
4479 // use nds as scratch for src
4480 evmovdqul(nds, src, Assembler::AVX_512bit);
4481 Assembler::vpmullw(dst, dst, nds, vector_len);
4482 } else if ((src_enc < 16) && (nds_enc < 16)) {
4483 // use nds as scratch for dst
4484 evmovdqul(nds, dst, Assembler::AVX_512bit);
4485 Assembler::vpmullw(nds, nds, src, vector_len);
4486 evmovdqul(dst, nds, Assembler::AVX_512bit);
4487 } else if (dst_enc < 16) {
4488 // use nds as scatch for xmm0 to hold src
4489 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4490 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4491 Assembler::vpmullw(dst, dst, xmm0, vector_len);
4492 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4493 } else {
4494 // worse case scenario, all regs are in the upper bank
4495 subptr(rsp, 64);
4496 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
4497 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4498 evmovdqul(xmm1, src, Assembler::AVX_512bit);
4499 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4500 Assembler::vpmullw(xmm0, xmm0, xmm1, vector_len);
4501 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4502 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4503 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
4504 addptr(rsp, 64);
4505 }
4506 }
4507
4508 void MacroAssembler::vpmullw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4509 int dst_enc = dst->encoding();
4510 int nds_enc = nds->encoding();
4511 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4512 Assembler::vpmullw(dst, nds, src, vector_len);
4513 } else if (dst_enc < 16) {
4514 Assembler::vpmullw(dst, dst, src, vector_len);
4515 } else if (nds_enc < 16) {
4516 // implies dst_enc in upper bank with src as scratch
4517 evmovdqul(nds, dst, Assembler::AVX_512bit);
4518 Assembler::vpmullw(nds, nds, src, vector_len);
4519 evmovdqul(dst, nds, Assembler::AVX_512bit);
4520 } else {
4521 // worse case scenario, all regs in upper bank
4522 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4523 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4524 Assembler::vpmullw(xmm0, xmm0, src, vector_len);
4525 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4526 }
4527 }
4528
4529 void MacroAssembler::vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4530 int dst_enc = dst->encoding();
4531 int nds_enc = nds->encoding();
4532 int src_enc = src->encoding();
4533 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4534 Assembler::vpsubb(dst, nds, src, vector_len);
4535 } else if ((dst_enc < 16) && (src_enc < 16)) {
4536 Assembler::vpsubb(dst, dst, src, vector_len);
4537 } else if ((dst_enc < 16) && (nds_enc < 16)) {
4538 // use nds as scratch for src
4539 evmovdqul(nds, src, Assembler::AVX_512bit);
4540 Assembler::vpsubb(dst, dst, nds, vector_len);
4541 } else if ((src_enc < 16) && (nds_enc < 16)) {
4542 // use nds as scratch for dst
4543 evmovdqul(nds, dst, Assembler::AVX_512bit);
4544 Assembler::vpsubb(nds, nds, src, vector_len);
4545 evmovdqul(dst, nds, Assembler::AVX_512bit);
4546 } else if (dst_enc < 16) {
4547 // use nds as scatch for xmm0 to hold src
4548 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4549 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4550 Assembler::vpsubb(dst, dst, xmm0, vector_len);
4551 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4552 } else {
4553 // worse case scenario, all regs are in the upper bank
4554 subptr(rsp, 64);
4555 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
4556 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4557 evmovdqul(xmm1, src, Assembler::AVX_512bit);
4558 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4559 Assembler::vpsubb(xmm0, xmm0, xmm1, vector_len);
4560 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4561 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4562 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
4563 addptr(rsp, 64);
4564 }
4565 }
4566
4567 void MacroAssembler::vpsubb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4568 int dst_enc = dst->encoding();
4569 int nds_enc = nds->encoding();
4570 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4571 Assembler::vpsubb(dst, nds, src, vector_len);
4572 } else if (dst_enc < 16) {
4573 Assembler::vpsubb(dst, dst, src, vector_len);
4574 } else if (nds_enc < 16) {
4575 // implies dst_enc in upper bank with src as scratch
4576 evmovdqul(nds, dst, Assembler::AVX_512bit);
4577 Assembler::vpsubb(nds, nds, src, vector_len);
4578 evmovdqul(dst, nds, Assembler::AVX_512bit);
4579 } else {
4580 // worse case scenario, all regs in upper bank
4581 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4582 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4583 Assembler::vpsubw(xmm0, xmm0, src, vector_len);
4584 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4585 }
4586 }
4587
4588 void MacroAssembler::vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4589 int dst_enc = dst->encoding();
4590 int nds_enc = nds->encoding();
4591 int src_enc = src->encoding();
4592 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4593 Assembler::vpsubw(dst, nds, src, vector_len);
4594 } else if ((dst_enc < 16) && (src_enc < 16)) {
4595 Assembler::vpsubw(dst, dst, src, vector_len);
4596 } else if ((dst_enc < 16) && (nds_enc < 16)) {
4597 // use nds as scratch for src
4598 evmovdqul(nds, src, Assembler::AVX_512bit);
4599 Assembler::vpsubw(dst, dst, nds, vector_len);
4600 } else if ((src_enc < 16) && (nds_enc < 16)) {
4601 // use nds as scratch for dst
4602 evmovdqul(nds, dst, Assembler::AVX_512bit);
4603 Assembler::vpsubw(nds, nds, src, vector_len);
4604 evmovdqul(dst, nds, Assembler::AVX_512bit);
4605 } else if (dst_enc < 16) {
4606 // use nds as scatch for xmm0 to hold src
4607 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4608 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4609 Assembler::vpsubw(dst, dst, xmm0, vector_len);
4610 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4611 } else {
4612 // worse case scenario, all regs are in the upper bank
4613 subptr(rsp, 64);
4614 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
4615 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4616 evmovdqul(xmm1, src, Assembler::AVX_512bit);
4617 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4618 Assembler::vpsubw(xmm0, xmm0, xmm1, vector_len);
4619 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4620 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4621 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
4622 addptr(rsp, 64);
4623 }
4624 }
4625
4626 void MacroAssembler::vpsubw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4627 int dst_enc = dst->encoding();
4628 int nds_enc = nds->encoding();
4629 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4630 Assembler::vpsubw(dst, nds, src, vector_len);
4631 } else if (dst_enc < 16) {
4632 Assembler::vpsubw(dst, dst, src, vector_len);
4633 } else if (nds_enc < 16) {
4634 // implies dst_enc in upper bank with src as scratch
4635 evmovdqul(nds, dst, Assembler::AVX_512bit);
4636 Assembler::vpsubw(nds, nds, src, vector_len);
4637 evmovdqul(dst, nds, Assembler::AVX_512bit);
4638 } else {
4639 // worse case scenario, all regs in upper bank
4640 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4641 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4642 Assembler::vpsubw(xmm0, xmm0, src, vector_len);
4643 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4644 }
4645 }
4646
4647 void MacroAssembler::vpsraw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
4648 int dst_enc = dst->encoding();
4649 int nds_enc = nds->encoding();
4650 int shift_enc = shift->encoding();
4651 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4652 Assembler::vpsraw(dst, nds, shift, vector_len);
4653 } else if ((dst_enc < 16) && (shift_enc < 16)) {
4654 Assembler::vpsraw(dst, dst, shift, vector_len);
4655 } else if ((dst_enc < 16) && (nds_enc < 16)) {
4656 // use nds_enc as scratch with shift
4657 evmovdqul(nds, shift, Assembler::AVX_512bit);
4658 Assembler::vpsraw(dst, dst, nds, vector_len);
4659 } else if ((shift_enc < 16) && (nds_enc < 16)) {
4660 // use nds as scratch with dst
4661 evmovdqul(nds, dst, Assembler::AVX_512bit);
4662 Assembler::vpsraw(nds, nds, shift, vector_len);
4663 evmovdqul(dst, nds, Assembler::AVX_512bit);
4664 } else if (dst_enc < 16) {
4665 // use nds to save a copy of xmm0 and hold shift
4666 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4667 evmovdqul(xmm0, shift, Assembler::AVX_512bit);
4668 Assembler::vpsraw(dst, dst, xmm0, vector_len);
4669 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4670 } else if (nds_enc < 16) {
4671 // use nds as dest as temps
4672 evmovdqul(nds, dst, Assembler::AVX_512bit);
4673 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4674 evmovdqul(xmm0, shift, Assembler::AVX_512bit);
4675 Assembler::vpsraw(nds, nds, xmm0, vector_len);
4676 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4677 evmovdqul(dst, nds, Assembler::AVX_512bit);
4678 } else {
4679 // worse case scenario, all regs are in the upper bank
4680 subptr(rsp, 64);
4681 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
4682 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4683 evmovdqul(xmm1, shift, Assembler::AVX_512bit);
4684 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4685 Assembler::vpsllw(xmm0, xmm0, xmm1, vector_len);
4686 evmovdqul(xmm1, dst, Assembler::AVX_512bit);
4687 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4688 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4689 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
4690 addptr(rsp, 64);
4691 }
4692 }
4693
4694 void MacroAssembler::vpsraw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
4695 int dst_enc = dst->encoding();
4696 int nds_enc = nds->encoding();
4697 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4698 Assembler::vpsraw(dst, nds, shift, vector_len);
4699 } else if (dst_enc < 16) {
4700 Assembler::vpsraw(dst, dst, shift, vector_len);
4701 } else if (nds_enc < 16) {
4702 // use nds as scratch
4703 evmovdqul(nds, dst, Assembler::AVX_512bit);
4704 Assembler::vpsraw(nds, nds, shift, vector_len);
4705 evmovdqul(dst, nds, Assembler::AVX_512bit);
4706 } else {
4707 // use nds as scratch for xmm0
4708 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4709 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4710 Assembler::vpsraw(xmm0, xmm0, shift, vector_len);
4711 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4712 }
4713 }
4714
4715 void MacroAssembler::vpsrlw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
4716 int dst_enc = dst->encoding();
4717 int nds_enc = nds->encoding();
4718 int shift_enc = shift->encoding();
4719 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4720 Assembler::vpsrlw(dst, nds, shift, vector_len);
4721 } else if ((dst_enc < 16) && (shift_enc < 16)) {
4722 Assembler::vpsrlw(dst, dst, shift, vector_len);
4723 } else if ((dst_enc < 16) && (nds_enc < 16)) {
4724 // use nds_enc as scratch with shift
4725 evmovdqul(nds, shift, Assembler::AVX_512bit);
4726 Assembler::vpsrlw(dst, dst, nds, vector_len);
4727 } else if ((shift_enc < 16) && (nds_enc < 16)) {
4728 // use nds as scratch with dst
4729 evmovdqul(nds, dst, Assembler::AVX_512bit);
4730 Assembler::vpsrlw(nds, nds, shift, vector_len);
4731 evmovdqul(dst, nds, Assembler::AVX_512bit);
4732 } else if (dst_enc < 16) {
4733 // use nds to save a copy of xmm0 and hold shift
4734 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4735 evmovdqul(xmm0, shift, Assembler::AVX_512bit);
4736 Assembler::vpsrlw(dst, dst, xmm0, vector_len);
4737 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4738 } else if (nds_enc < 16) {
4739 // use nds as dest as temps
4740 evmovdqul(nds, dst, Assembler::AVX_512bit);
4741 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4742 evmovdqul(xmm0, shift, Assembler::AVX_512bit);
4743 Assembler::vpsrlw(nds, nds, xmm0, vector_len);
4744 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4745 evmovdqul(dst, nds, Assembler::AVX_512bit);
4746 } else {
4747 // worse case scenario, all regs are in the upper bank
4748 subptr(rsp, 64);
4749 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
4750 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4751 evmovdqul(xmm1, shift, Assembler::AVX_512bit);
4752 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4753 Assembler::vpsllw(xmm0, xmm0, xmm1, vector_len);
4754 evmovdqul(xmm1, dst, Assembler::AVX_512bit);
4755 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4756 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4757 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
4758 addptr(rsp, 64);
4759 }
4760 }
4761
4762 void MacroAssembler::vpsrlw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
4763 int dst_enc = dst->encoding();
4764 int nds_enc = nds->encoding();
4765 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4766 Assembler::vpsrlw(dst, nds, shift, vector_len);
4767 } else if (dst_enc < 16) {
4768 Assembler::vpsrlw(dst, dst, shift, vector_len);
4769 } else if (nds_enc < 16) {
4770 // use nds as scratch
4771 evmovdqul(nds, dst, Assembler::AVX_512bit);
4772 Assembler::vpsrlw(nds, nds, shift, vector_len);
4773 evmovdqul(dst, nds, Assembler::AVX_512bit);
4774 } else {
4775 // use nds as scratch for xmm0
4776 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4777 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4778 Assembler::vpsrlw(xmm0, xmm0, shift, vector_len);
4779 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4780 }
4781 }
4782
4783 void MacroAssembler::vpsllw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
4784 int dst_enc = dst->encoding();
4785 int nds_enc = nds->encoding();
4786 int shift_enc = shift->encoding();
4787 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4788 Assembler::vpsllw(dst, nds, shift, vector_len);
4789 } else if ((dst_enc < 16) && (shift_enc < 16)) {
4790 Assembler::vpsllw(dst, dst, shift, vector_len);
4791 } else if ((dst_enc < 16) && (nds_enc < 16)) {
4792 // use nds_enc as scratch with shift
4793 evmovdqul(nds, shift, Assembler::AVX_512bit);
4794 Assembler::vpsllw(dst, dst, nds, vector_len);
4795 } else if ((shift_enc < 16) && (nds_enc < 16)) {
4796 // use nds as scratch with dst
4797 evmovdqul(nds, dst, Assembler::AVX_512bit);
4798 Assembler::vpsllw(nds, nds, shift, vector_len);
4799 evmovdqul(dst, nds, Assembler::AVX_512bit);
4800 } else if (dst_enc < 16) {
4801 // use nds to save a copy of xmm0 and hold shift
4802 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4803 evmovdqul(xmm0, shift, Assembler::AVX_512bit);
4804 Assembler::vpsllw(dst, dst, xmm0, vector_len);
4805 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4806 } else if (nds_enc < 16) {
4807 // use nds as dest as temps
4808 evmovdqul(nds, dst, Assembler::AVX_512bit);
4809 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4810 evmovdqul(xmm0, shift, Assembler::AVX_512bit);
4811 Assembler::vpsllw(nds, nds, xmm0, vector_len);
4812 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4813 evmovdqul(dst, nds, Assembler::AVX_512bit);
4814 } else {
4815 // worse case scenario, all regs are in the upper bank
4816 subptr(rsp, 64);
4817 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
4818 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4819 evmovdqul(xmm1, shift, Assembler::AVX_512bit);
4820 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4821 Assembler::vpsllw(xmm0, xmm0, xmm1, vector_len);
4822 evmovdqul(xmm1, dst, Assembler::AVX_512bit);
4823 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4824 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4825 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
4826 addptr(rsp, 64);
4827 }
4828 }
4829
4830 void MacroAssembler::vpsllw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
4831 int dst_enc = dst->encoding();
4832 int nds_enc = nds->encoding();
4833 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4834 Assembler::vpsllw(dst, nds, shift, vector_len);
4835 } else if (dst_enc < 16) {
4836 Assembler::vpsllw(dst, dst, shift, vector_len);
4837 } else if (nds_enc < 16) {
4838 // use nds as scratch
4839 evmovdqul(nds, dst, Assembler::AVX_512bit);
4840 Assembler::vpsllw(nds, nds, shift, vector_len);
4841 evmovdqul(dst, nds, Assembler::AVX_512bit);
4842 } else {
4843 // use nds as scratch for xmm0
4844 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4845 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4846 Assembler::vpsllw(xmm0, xmm0, shift, vector_len);
4847 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4848 }
4849 }
4850
4851 void MacroAssembler::vptest(XMMRegister dst, XMMRegister src) {
4852 int dst_enc = dst->encoding();
4853 int src_enc = src->encoding();
4854 if ((dst_enc < 16) && (src_enc < 16)) {
4855 Assembler::vptest(dst, src);
4856 } else if (src_enc < 16) {
4857 subptr(rsp, 64);
4858 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4859 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4860 Assembler::vptest(xmm0, src);
4861 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4862 addptr(rsp, 64);
4863 } else if (dst_enc < 16) {
4864 subptr(rsp, 64);
4865 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4866 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4867 Assembler::vptest(dst, xmm0);
4868 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4869 addptr(rsp, 64);
4870 } else {
4871 subptr(rsp, 64);
4872 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4873 subptr(rsp, 64);
4874 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
4875 movdqu(xmm0, src);
4876 movdqu(xmm1, dst);
4877 Assembler::vptest(xmm1, xmm0);
4878 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
4879 addptr(rsp, 64);
4880 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4881 addptr(rsp, 64);
4882 }
4883 }
4884
4885 // This instruction exists within macros, ergo we cannot control its input
4886 // when emitted through those patterns.
4887 void MacroAssembler::punpcklbw(XMMRegister dst, XMMRegister src) {
4888 if (VM_Version::supports_avx512nobw()) {
4889 int dst_enc = dst->encoding();
4890 int src_enc = src->encoding();
4891 if (dst_enc == src_enc) {
4892 if (dst_enc < 16) {
4893 Assembler::punpcklbw(dst, src);
4894 } else {
4895 subptr(rsp, 64);
4896 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4897 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4898 Assembler::punpcklbw(xmm0, xmm0);
4899 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4900 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4901 addptr(rsp, 64);
4902 }
4903 } else {
4904 if ((src_enc < 16) && (dst_enc < 16)) {
4905 Assembler::punpcklbw(dst, src);
4906 } else if (src_enc < 16) {
4907 subptr(rsp, 64);
4908 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4909 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4910 Assembler::punpcklbw(xmm0, src);
4911 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4912 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4913 addptr(rsp, 64);
4914 } else if (dst_enc < 16) {
4915 subptr(rsp, 64);
4916 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4917 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4918 Assembler::punpcklbw(dst, xmm0);
4919 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4920 addptr(rsp, 64);
4921 } else {
4922 subptr(rsp, 64);
4923 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4924 subptr(rsp, 64);
4925 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
4926 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4927 evmovdqul(xmm1, src, Assembler::AVX_512bit);
4928 Assembler::punpcklbw(xmm0, xmm1);
4929 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4930 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
4931 addptr(rsp, 64);
4932 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4933 addptr(rsp, 64);
4934 }
4935 }
4936 } else {
4937 Assembler::punpcklbw(dst, src);
4938 }
4939 }
4940
4941 // This instruction exists within macros, ergo we cannot control its input
4942 // when emitted through those patterns.
4943 void MacroAssembler::pshuflw(XMMRegister dst, XMMRegister src, int mode) {
4944 if (VM_Version::supports_avx512nobw()) {
4945 int dst_enc = dst->encoding();
4946 int src_enc = src->encoding();
4947 if (dst_enc == src_enc) {
4948 if (dst_enc < 16) {
4949 Assembler::pshuflw(dst, src, mode);
4950 } else {
4951 subptr(rsp, 64);
4952 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4953 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4954 Assembler::pshuflw(xmm0, xmm0, mode);
4955 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4956 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4957 addptr(rsp, 64);
4958 }
4959 } else {
4960 if ((src_enc < 16) && (dst_enc < 16)) {
4961 Assembler::pshuflw(dst, src, mode);
4962 } else if (src_enc < 16) {
4963 subptr(rsp, 64);
4964 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4965 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4966 Assembler::pshuflw(xmm0, src, mode);
4967 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4968 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4969 addptr(rsp, 64);
4970 } else if (dst_enc < 16) {
4971 subptr(rsp, 64);
4972 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4973 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4974 Assembler::pshuflw(dst, xmm0, mode);
4975 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4976 addptr(rsp, 64);
4977 } else {
4978 subptr(rsp, 64);
4979 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4980 subptr(rsp, 64);
4981 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
4982 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4983 evmovdqul(xmm1, src, Assembler::AVX_512bit);
4984 Assembler::pshuflw(xmm0, xmm1, mode);
4985 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4986 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
4987 addptr(rsp, 64);
4988 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4989 addptr(rsp, 64);
4990 }
4991 }
4992 } else {
4993 Assembler::pshuflw(dst, src, mode);
4994 }
4995 }
4996
4997 void MacroAssembler::vandpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len) {
4998 if (reachable(src)) {
4999 vandpd(dst, nds, as_Address(src), vector_len);
5000 } else {
5001 lea(rscratch1, src);
5002 vandpd(dst, nds, Address(rscratch1, 0), vector_len);
5003 }
5004 }
5005
5006 void MacroAssembler::vandps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len) {
5007 if (reachable(src)) {
5008 vandps(dst, nds, as_Address(src), vector_len);
5009 } else {
5010 lea(rscratch1, src);
5011 vandps(dst, nds, Address(rscratch1, 0), vector_len);
5012 }
5013 }
5014
5015 void MacroAssembler::vdivsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
5016 if (reachable(src)) {
5017 vdivsd(dst, nds, as_Address(src));
5018 } else {
5019 lea(rscratch1, src);
5020 vdivsd(dst, nds, Address(rscratch1, 0));
5021 }
5022 }
5023
5024 void MacroAssembler::vdivss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
5025 if (reachable(src)) {
5026 vdivss(dst, nds, as_Address(src));
5027 } else {
5028 lea(rscratch1, src);
5029 vdivss(dst, nds, Address(rscratch1, 0));
5030 }
5031 }
5032
5033 void MacroAssembler::vmulsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
5034 if (reachable(src)) {
5035 vmulsd(dst, nds, as_Address(src));
5036 } else {
5037 lea(rscratch1, src);
5038 vmulsd(dst, nds, Address(rscratch1, 0));
5039 }
5040 }
5041
5042 void MacroAssembler::vmulss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
5043 if (reachable(src)) {
5044 vmulss(dst, nds, as_Address(src));
5045 } else {
5046 lea(rscratch1, src);
5047 vmulss(dst, nds, Address(rscratch1, 0));
5048 }
5049 }
5050
5051 void MacroAssembler::vsubsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
5052 if (reachable(src)) {
5053 vsubsd(dst, nds, as_Address(src));
5054 } else {
5055 lea(rscratch1, src);
5056 vsubsd(dst, nds, Address(rscratch1, 0));
5057 }
5058 }
5059
5060 void MacroAssembler::vsubss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
5061 if (reachable(src)) {
5062 vsubss(dst, nds, as_Address(src));
5063 } else {
5064 lea(rscratch1, src);
5065 vsubss(dst, nds, Address(rscratch1, 0));
5066 }
5067 }
5068
5069 void MacroAssembler::vnegatess(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
5070 int nds_enc = nds->encoding();
5071 int dst_enc = dst->encoding();
5072 bool dst_upper_bank = (dst_enc > 15);
5073 bool nds_upper_bank = (nds_enc > 15);
5074 if (VM_Version::supports_avx512novl() &&
5075 (nds_upper_bank || dst_upper_bank)) {
5076 if (dst_upper_bank) {
5077 subptr(rsp, 64);
5078 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
5079 movflt(xmm0, nds);
5080 vxorps(xmm0, xmm0, src, Assembler::AVX_128bit);
5081 movflt(dst, xmm0);
5082 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
5083 addptr(rsp, 64);
5084 } else {
5085 movflt(dst, nds);
5086 vxorps(dst, dst, src, Assembler::AVX_128bit);
5087 }
5088 } else {
5089 vxorps(dst, nds, src, Assembler::AVX_128bit);
5090 }
5091 }
5092
5093 void MacroAssembler::vnegatesd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
5094 int nds_enc = nds->encoding();
5095 int dst_enc = dst->encoding();
5096 bool dst_upper_bank = (dst_enc > 15);
5097 bool nds_upper_bank = (nds_enc > 15);
5098 if (VM_Version::supports_avx512novl() &&
5099 (nds_upper_bank || dst_upper_bank)) {
5100 if (dst_upper_bank) {
5101 subptr(rsp, 64);
5102 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
5103 movdbl(xmm0, nds);
5104 vxorpd(xmm0, xmm0, src, Assembler::AVX_128bit);
5105 movdbl(dst, xmm0);
5106 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
5107 addptr(rsp, 64);
5108 } else {
5109 movdbl(dst, nds);
5110 vxorpd(dst, dst, src, Assembler::AVX_128bit);
5111 }
5112 } else {
5113 vxorpd(dst, nds, src, Assembler::AVX_128bit);
5114 }
5115 }
5116
5117 void MacroAssembler::vxorpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len) {
5118 if (reachable(src)) {
5119 vxorpd(dst, nds, as_Address(src), vector_len);
5120 } else {
5121 lea(rscratch1, src);
5122 vxorpd(dst, nds, Address(rscratch1, 0), vector_len);
5123 }
5124 }
5125
5126 void MacroAssembler::vxorps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len) {
5127 if (reachable(src)) {
5128 vxorps(dst, nds, as_Address(src), vector_len);
5129 } else {
5130 lea(rscratch1, src);
5131 vxorps(dst, nds, Address(rscratch1, 0), vector_len);
5132 }
5133 }
5134
5135
5136 void MacroAssembler::resolve_jobject(Register value,
5137 Register thread,
5138 Register tmp) {
5139 assert_different_registers(value, thread, tmp);
5140 Label done, not_weak;
5141 testptr(value, value);
5142 jcc(Assembler::zero, done); // Use NULL as-is.
5143 testptr(value, JNIHandles::weak_tag_mask); // Test for jweak tag.
5144 jcc(Assembler::zero, not_weak);
5145 // Resolve jweak.
5146 movptr(value, Address(value, -JNIHandles::weak_tag_value));
5147 verify_oop(value);
5148 #if INCLUDE_ALL_GCS
5149 if (UseG1GC) {
5150 g1_write_barrier_pre(noreg /* obj */,
5151 value /* pre_val */,
5152 thread /* thread */,
5153 tmp /* tmp */,
5154 true /* tosca_live */,
5155 true /* expand_call */);
5156 }
5157 #endif // INCLUDE_ALL_GCS
5158 jmp(done);
5159 bind(not_weak);
5160 // Resolve (untagged) jobject.
5161 movptr(value, Address(value, 0));
5162 verify_oop(value);
5163 bind(done);
5164 }
5165
5166 void MacroAssembler::clear_jweak_tag(Register possibly_jweak) {
5167 const int32_t inverted_jweak_mask = ~static_cast<int32_t>(JNIHandles::weak_tag_mask);
5168 STATIC_ASSERT(inverted_jweak_mask == -2); // otherwise check this code
5169 // The inverted mask is sign-extended
5170 andptr(possibly_jweak, inverted_jweak_mask);
5171 }
5172
5173 //////////////////////////////////////////////////////////////////////////////////
5174 #if INCLUDE_ALL_GCS
5175
5176 void MacroAssembler::g1_write_barrier_pre(Register obj,
5177 Register pre_val,
5178 Register thread,
5179 Register tmp,
5180 bool tosca_live,
5181 bool expand_call) {
5182
5183 // If expand_call is true then we expand the call_VM_leaf macro
5184 // directly to skip generating the check by
5185 // InterpreterMacroAssembler::call_VM_leaf_base that checks _last_sp.
5186
5187 #ifdef _LP64
5188 assert(thread == r15_thread, "must be");
5189 #endif // _LP64
5190
5191 Label done;
5192 Label runtime;
5193
5194 assert(pre_val != noreg, "check this code");
5195
5196 if (obj != noreg) {
5197 assert_different_registers(obj, pre_val, tmp);
5198 assert(pre_val != rax, "check this code");
5199 }
5200
5201 Address in_progress(thread, in_bytes(JavaThread::satb_mark_queue_offset() +
5202 SATBMarkQueue::byte_offset_of_active()));
5203 Address index(thread, in_bytes(JavaThread::satb_mark_queue_offset() +
5204 SATBMarkQueue::byte_offset_of_index()));
5205 Address buffer(thread, in_bytes(JavaThread::satb_mark_queue_offset() +
5206 SATBMarkQueue::byte_offset_of_buf()));
5207
5208
5209 // Is marking active?
5210 if (in_bytes(SATBMarkQueue::byte_width_of_active()) == 4) {
5211 cmpl(in_progress, 0);
5212 } else {
5213 assert(in_bytes(SATBMarkQueue::byte_width_of_active()) == 1, "Assumption");
5214 cmpb(in_progress, 0);
5215 }
5216 jcc(Assembler::equal, done);
5217
5218 // Do we need to load the previous value?
5219 if (obj != noreg) {
5220 load_heap_oop(pre_val, Address(obj, 0));
5221 }
5222
5223 // Is the previous value null?
5224 cmpptr(pre_val, (int32_t) NULL_WORD);
5225 jcc(Assembler::equal, done);
5226
5227 // Can we store original value in the thread's buffer?
5228 // Is index == 0?
5229 // (The index field is typed as size_t.)
5230
5231 movptr(tmp, index); // tmp := *index_adr
5232 cmpptr(tmp, 0); // tmp == 0?
5233 jcc(Assembler::equal, runtime); // If yes, goto runtime
5234
5235 subptr(tmp, wordSize); // tmp := tmp - wordSize
5236 movptr(index, tmp); // *index_adr := tmp
5237 addptr(tmp, buffer); // tmp := tmp + *buffer_adr
5238
5239 // Record the previous value
5240 movptr(Address(tmp, 0), pre_val);
5241 jmp(done);
5242
5243 bind(runtime);
5244 // save the live input values
5245 if(tosca_live) push(rax);
5246
5247 if (obj != noreg && obj != rax)
5248 push(obj);
5249
5250 if (pre_val != rax)
5251 push(pre_val);
5252
5253 // Calling the runtime using the regular call_VM_leaf mechanism generates
5254 // code (generated by InterpreterMacroAssember::call_VM_leaf_base)
5255 // that checks that the *(ebp+frame::interpreter_frame_last_sp) == NULL.
5256 //
5257 // If we care generating the pre-barrier without a frame (e.g. in the
5258 // intrinsified Reference.get() routine) then ebp might be pointing to
5259 // the caller frame and so this check will most likely fail at runtime.
5260 //
5261 // Expanding the call directly bypasses the generation of the check.
5262 // So when we do not have have a full interpreter frame on the stack
5263 // expand_call should be passed true.
5264
5265 NOT_LP64( push(thread); )
5266
5267 if (expand_call) {
5268 LP64_ONLY( assert(pre_val != c_rarg1, "smashed arg"); )
5269 pass_arg1(this, thread);
5270 pass_arg0(this, pre_val);
5271 MacroAssembler::call_VM_leaf_base(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_pre), 2);
5272 } else {
5273 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_pre), pre_val, thread);
5274 }
5275
5276 NOT_LP64( pop(thread); )
5277
5278 // save the live input values
5279 if (pre_val != rax)
5280 pop(pre_val);
5281
5282 if (obj != noreg && obj != rax)
5283 pop(obj);
5284
5285 if(tosca_live) pop(rax);
5286
5287 bind(done);
5288 }
5289
5290 void MacroAssembler::g1_write_barrier_post(Register store_addr,
5291 Register new_val,
5292 Register thread,
5293 Register tmp,
5294 Register tmp2) {
5295 #ifdef _LP64
5296 assert(thread == r15_thread, "must be");
5297 #endif // _LP64
5298
5299 Address queue_index(thread, in_bytes(JavaThread::dirty_card_queue_offset() +
5300 DirtyCardQueue::byte_offset_of_index()));
5301 Address buffer(thread, in_bytes(JavaThread::dirty_card_queue_offset() +
5302 DirtyCardQueue::byte_offset_of_buf()));
5303
5304 CardTableModRefBS* ct =
5305 barrier_set_cast<CardTableModRefBS>(Universe::heap()->barrier_set());
5306 assert(sizeof(*ct->byte_map_base) == sizeof(jbyte), "adjust this code");
5307
5308 Label done;
5309 Label runtime;
5310
5311 // Does store cross heap regions?
5312
5313 movptr(tmp, store_addr);
5314 xorptr(tmp, new_val);
5315 shrptr(tmp, HeapRegion::LogOfHRGrainBytes);
5316 jcc(Assembler::equal, done);
5317
5318 // crosses regions, storing NULL?
5319
5320 cmpptr(new_val, (int32_t) NULL_WORD);
5321 jcc(Assembler::equal, done);
5322
5323 // storing region crossing non-NULL, is card already dirty?
5324
5325 const Register card_addr = tmp;
5326 const Register cardtable = tmp2;
5327
5328 movptr(card_addr, store_addr);
5329 shrptr(card_addr, CardTableModRefBS::card_shift);
5330 // Do not use ExternalAddress to load 'byte_map_base', since 'byte_map_base' is NOT
5331 // a valid address and therefore is not properly handled by the relocation code.
5332 movptr(cardtable, (intptr_t)ct->byte_map_base);
5333 addptr(card_addr, cardtable);
5334
5335 cmpb(Address(card_addr, 0), (int)G1SATBCardTableModRefBS::g1_young_card_val());
5336 jcc(Assembler::equal, done);
5337
5338 membar(Assembler::Membar_mask_bits(Assembler::StoreLoad));
5339 cmpb(Address(card_addr, 0), (int)CardTableModRefBS::dirty_card_val());
5340 jcc(Assembler::equal, done);
5341
5342
5343 // storing a region crossing, non-NULL oop, card is clean.
5344 // dirty card and log.
5345
5346 movb(Address(card_addr, 0), (int)CardTableModRefBS::dirty_card_val());
5347
5348 cmpl(queue_index, 0);
5349 jcc(Assembler::equal, runtime);
5350 subl(queue_index, wordSize);
5351 movptr(tmp2, buffer);
5352 #ifdef _LP64
5353 movslq(rscratch1, queue_index);
5354 addq(tmp2, rscratch1);
5355 movq(Address(tmp2, 0), card_addr);
5356 #else
5357 addl(tmp2, queue_index);
5358 movl(Address(tmp2, 0), card_addr);
5359 #endif
5360 jmp(done);
5361
5362 bind(runtime);
5363 // save the live input values
5364 push(store_addr);
5365 push(new_val);
5366 #ifdef _LP64
5367 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_post), card_addr, r15_thread);
5368 #else
5369 push(thread);
5370 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_post), card_addr, thread);
5371 pop(thread);
5372 #endif
5373 pop(new_val);
5374 pop(store_addr);
5375
5376 bind(done);
5377 }
5378
5379 #endif // INCLUDE_ALL_GCS
5380 //////////////////////////////////////////////////////////////////////////////////
5381
5382
5383 void MacroAssembler::store_check(Register obj, Address dst) {
5384 store_check(obj);
5385 }
5386
5387 void MacroAssembler::store_check(Register obj) {
5388 // Does a store check for the oop in register obj. The content of
5389 // register obj is destroyed afterwards.
5390 BarrierSet* bs = Universe::heap()->barrier_set();
5391 assert(bs->kind() == BarrierSet::CardTableForRS ||
5392 bs->kind() == BarrierSet::CardTableExtension,
5393 "Wrong barrier set kind");
5394
5395 CardTableModRefBS* ct = barrier_set_cast<CardTableModRefBS>(bs);
5396 assert(sizeof(*ct->byte_map_base) == sizeof(jbyte), "adjust this code");
5397
5398 shrptr(obj, CardTableModRefBS::card_shift);
5399
5400 Address card_addr;
5401
5402 // The calculation for byte_map_base is as follows:
5403 // byte_map_base = _byte_map - (uintptr_t(low_bound) >> card_shift);
5404 // So this essentially converts an address to a displacement and it will
5405 // never need to be relocated. On 64bit however the value may be too
5406 // large for a 32bit displacement.
5407 intptr_t disp = (intptr_t) ct->byte_map_base;
5408 if (is_simm32(disp)) {
5409 card_addr = Address(noreg, obj, Address::times_1, disp);
5410 } else {
5411 // By doing it as an ExternalAddress 'disp' could be converted to a rip-relative
5412 // displacement and done in a single instruction given favorable mapping and a
5413 // smarter version of as_Address. However, 'ExternalAddress' generates a relocation
5414 // entry and that entry is not properly handled by the relocation code.
5415 AddressLiteral cardtable((address)ct->byte_map_base, relocInfo::none);
5416 Address index(noreg, obj, Address::times_1);
5417 card_addr = as_Address(ArrayAddress(cardtable, index));
5418 }
5419
5420 int dirty = CardTableModRefBS::dirty_card_val();
5421 if (UseCondCardMark) {
5422 Label L_already_dirty;
5423 if (UseConcMarkSweepGC) {
5424 membar(Assembler::StoreLoad);
5425 }
5426 cmpb(card_addr, dirty);
5427 jcc(Assembler::equal, L_already_dirty);
5428 movb(card_addr, dirty);
5429 bind(L_already_dirty);
5430 } else {
5431 movb(card_addr, dirty);
5432 }
5433 }
5434
5435 void MacroAssembler::subptr(Register dst, int32_t imm32) {
5436 LP64_ONLY(subq(dst, imm32)) NOT_LP64(subl(dst, imm32));
5437 }
5438
5439 // Force generation of a 4 byte immediate value even if it fits into 8bit
5440 void MacroAssembler::subptr_imm32(Register dst, int32_t imm32) {
5441 LP64_ONLY(subq_imm32(dst, imm32)) NOT_LP64(subl_imm32(dst, imm32));
5442 }
5443
5444 void MacroAssembler::subptr(Register dst, Register src) {
5445 LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src));
5446 }
5447
5448 // C++ bool manipulation
5449 void MacroAssembler::testbool(Register dst) {
5450 if(sizeof(bool) == 1)
5451 testb(dst, 0xff);
5452 else if(sizeof(bool) == 2) {
5453 // testw implementation needed for two byte bools
5454 ShouldNotReachHere();
5455 } else if(sizeof(bool) == 4)
5456 testl(dst, dst);
5457 else
5458 // unsupported
5459 ShouldNotReachHere();
5460 }
5461
5462 void MacroAssembler::testptr(Register dst, Register src) {
5463 LP64_ONLY(testq(dst, src)) NOT_LP64(testl(dst, src));
5464 }
5465
5466 // Defines obj, preserves var_size_in_bytes, okay for t2 == var_size_in_bytes.
5467 void MacroAssembler::tlab_allocate(Register obj,
5468 Register var_size_in_bytes,
5469 int con_size_in_bytes,
5470 Register t1,
5471 Register t2,
5472 Label& slow_case) {
5473 assert_different_registers(obj, t1, t2);
5474 assert_different_registers(obj, var_size_in_bytes, t1);
5475 Register end = t2;
5476 Register thread = NOT_LP64(t1) LP64_ONLY(r15_thread);
5477
5478 verify_tlab();
5479
5480 NOT_LP64(get_thread(thread));
5481
5482 movptr(obj, Address(thread, JavaThread::tlab_top_offset()));
5483 if (var_size_in_bytes == noreg) {
5484 lea(end, Address(obj, con_size_in_bytes));
5485 } else {
5486 lea(end, Address(obj, var_size_in_bytes, Address::times_1));
5487 }
5488 cmpptr(end, Address(thread, JavaThread::tlab_end_offset()));
5489 jcc(Assembler::above, slow_case);
5490
5491 // update the tlab top pointer
5492 movptr(Address(thread, JavaThread::tlab_top_offset()), end);
5493
5494 // recover var_size_in_bytes if necessary
5495 if (var_size_in_bytes == end) {
5496 subptr(var_size_in_bytes, obj);
5497 }
5498 verify_tlab();
5499 }
5500
5501 // Preserves rbx, and rdx.
5502 Register MacroAssembler::tlab_refill(Label& retry,
5503 Label& try_eden,
5504 Label& slow_case) {
5505 Register top = rax;
5506 Register t1 = rcx; // object size
5507 Register t2 = rsi;
5508 Register thread_reg = NOT_LP64(rdi) LP64_ONLY(r15_thread);
5509 assert_different_registers(top, thread_reg, t1, t2, /* preserve: */ rbx, rdx);
5510 Label do_refill, discard_tlab;
5511
5512 if (!Universe::heap()->supports_inline_contig_alloc()) {
5513 // No allocation in the shared eden.
5514 jmp(slow_case);
5515 }
5516
5517 NOT_LP64(get_thread(thread_reg));
5518
5519 movptr(top, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())));
5520 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_end_offset())));
5521
5522 // calculate amount of free space
5523 subptr(t1, top);
5524 shrptr(t1, LogHeapWordSize);
5525
5526 // Retain tlab and allocate object in shared space if
5527 // the amount free in the tlab is too large to discard.
5528 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_refill_waste_limit_offset())));
5529 jcc(Assembler::lessEqual, discard_tlab);
5530
5531 // Retain
5532 // %%% yuck as movptr...
5533 movptr(t2, (int32_t) ThreadLocalAllocBuffer::refill_waste_limit_increment());
5534 addptr(Address(thread_reg, in_bytes(JavaThread::tlab_refill_waste_limit_offset())), t2);
5535 if (TLABStats) {
5536 // increment number of slow_allocations
5537 addl(Address(thread_reg, in_bytes(JavaThread::tlab_slow_allocations_offset())), 1);
5538 }
5539 jmp(try_eden);
5540
5541 bind(discard_tlab);
5542 if (TLABStats) {
5543 // increment number of refills
5544 addl(Address(thread_reg, in_bytes(JavaThread::tlab_number_of_refills_offset())), 1);
5545 // accumulate wastage -- t1 is amount free in tlab
5546 addl(Address(thread_reg, in_bytes(JavaThread::tlab_fast_refill_waste_offset())), t1);
5547 }
5548
5549 // if tlab is currently allocated (top or end != null) then
5550 // fill [top, end + alignment_reserve) with array object
5551 testptr(top, top);
5552 jcc(Assembler::zero, do_refill);
5553
5554 // set up the mark word
5555 movptr(Address(top, oopDesc::mark_offset_in_bytes()), (intptr_t)markOopDesc::prototype()->copy_set_hash(0x2));
5556 // set the length to the remaining space
5557 subptr(t1, typeArrayOopDesc::header_size(T_INT));
5558 addptr(t1, (int32_t)ThreadLocalAllocBuffer::alignment_reserve());
5559 shlptr(t1, log2_intptr(HeapWordSize/sizeof(jint)));
5560 movl(Address(top, arrayOopDesc::length_offset_in_bytes()), t1);
5561 // set klass to intArrayKlass
5562 // dubious reloc why not an oop reloc?
5563 movptr(t1, ExternalAddress((address)Universe::intArrayKlassObj_addr()));
5564 // store klass last. concurrent gcs assumes klass length is valid if
5565 // klass field is not null.
5566 store_klass(top, t1);
5567
5568 movptr(t1, top);
5569 subptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_start_offset())));
5570 incr_allocated_bytes(thread_reg, t1, 0);
5571
5572 // refill the tlab with an eden allocation
5573 bind(do_refill);
5574 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_size_offset())));
5575 shlptr(t1, LogHeapWordSize);
5576 // allocate new tlab, address returned in top
5577 eden_allocate(top, t1, 0, t2, slow_case);
5578
5579 // Check that t1 was preserved in eden_allocate.
5580 #ifdef ASSERT
5581 if (UseTLAB) {
5582 Label ok;
5583 Register tsize = rsi;
5584 assert_different_registers(tsize, thread_reg, t1);
5585 push(tsize);
5586 movptr(tsize, Address(thread_reg, in_bytes(JavaThread::tlab_size_offset())));
5587 shlptr(tsize, LogHeapWordSize);
5588 cmpptr(t1, tsize);
5589 jcc(Assembler::equal, ok);
5590 STOP("assert(t1 != tlab size)");
5591 should_not_reach_here();
5592
5593 bind(ok);
5594 pop(tsize);
5595 }
5596 #endif
5597 movptr(Address(thread_reg, in_bytes(JavaThread::tlab_start_offset())), top);
5598 movptr(Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())), top);
5599 addptr(top, t1);
5600 subptr(top, (int32_t)ThreadLocalAllocBuffer::alignment_reserve_in_bytes());
5601 movptr(Address(thread_reg, in_bytes(JavaThread::tlab_end_offset())), top);
5602
5603 // Currently, if this happens, just set back the actual end to where it was.
5604 movptr(Address(thread_reg, in_bytes(JavaThread::tlab_actual_end_offset())), top);
5605
5606 if (ZeroTLAB) {
5607 // This is a fast TLAB refill, therefore the GC is not notified of it.
5608 // So compiled code must fill the new TLAB with zeroes.
5609 movptr(top, Address(thread_reg, in_bytes(JavaThread::tlab_start_offset())));
5610 zero_memory(top, t1, 0, t2);
5611 }
5612
5613 verify_tlab();
5614 jmp(retry);
5615
5616 return thread_reg; // for use by caller
5617 }
5618
5619 // Preserves the contents of address, destroys the contents length_in_bytes and temp.
5620 void MacroAssembler::zero_memory(Register address, Register length_in_bytes, int offset_in_bytes, Register temp) {
5621 assert(address != length_in_bytes && address != temp && temp != length_in_bytes, "registers must be different");
5622 assert((offset_in_bytes & (BytesPerWord - 1)) == 0, "offset must be a multiple of BytesPerWord");
5623 Label done;
5624
5625 testptr(length_in_bytes, length_in_bytes);
5626 jcc(Assembler::zero, done);
5627
5628 // initialize topmost word, divide index by 2, check if odd and test if zero
5629 // note: for the remaining code to work, index must be a multiple of BytesPerWord
5630 #ifdef ASSERT
5631 {
5632 Label L;
5633 testptr(length_in_bytes, BytesPerWord - 1);
5634 jcc(Assembler::zero, L);
5635 stop("length must be a multiple of BytesPerWord");
5636 bind(L);
5637 }
5638 #endif
5639 Register index = length_in_bytes;
5640 xorptr(temp, temp); // use _zero reg to clear memory (shorter code)
5641 if (UseIncDec) {
5642 shrptr(index, 3); // divide by 8/16 and set carry flag if bit 2 was set
5643 } else {
5644 shrptr(index, 2); // use 2 instructions to avoid partial flag stall
5645 shrptr(index, 1);
5646 }
5647 #ifndef _LP64
5648 // index could have not been a multiple of 8 (i.e., bit 2 was set)
5649 {
5650 Label even;
5651 // note: if index was a multiple of 8, then it cannot
5652 // be 0 now otherwise it must have been 0 before
5653 // => if it is even, we don't need to check for 0 again
5654 jcc(Assembler::carryClear, even);
5655 // clear topmost word (no jump would be needed if conditional assignment worked here)
5656 movptr(Address(address, index, Address::times_8, offset_in_bytes - 0*BytesPerWord), temp);
5657 // index could be 0 now, must check again
5658 jcc(Assembler::zero, done);
5659 bind(even);
5660 }
5661 #endif // !_LP64
5662 // initialize remaining object fields: index is a multiple of 2 now
5663 {
5664 Label loop;
5665 bind(loop);
5666 movptr(Address(address, index, Address::times_8, offset_in_bytes - 1*BytesPerWord), temp);
5667 NOT_LP64(movptr(Address(address, index, Address::times_8, offset_in_bytes - 2*BytesPerWord), temp);)
5668 decrement(index);
5669 jcc(Assembler::notZero, loop);
5670 }
5671
5672 bind(done);
5673 }
5674
5675 void MacroAssembler::incr_allocated_bytes(Register thread,
5676 Register var_size_in_bytes,
5677 int con_size_in_bytes,
5678 Register t1) {
5679 if (!thread->is_valid()) {
5680 #ifdef _LP64
5681 thread = r15_thread;
5682 #else
5683 assert(t1->is_valid(), "need temp reg");
5684 thread = t1;
5685 get_thread(thread);
5686 #endif
5687 }
5688
5689 #ifdef _LP64
5690 if (var_size_in_bytes->is_valid()) {
5691 addq(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), var_size_in_bytes);
5692 } else {
5693 addq(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), con_size_in_bytes);
5694 }
5695 #else
5696 if (var_size_in_bytes->is_valid()) {
5697 addl(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), var_size_in_bytes);
5698 } else {
5699 addl(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), con_size_in_bytes);
5700 }
5701 adcl(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())+4), 0);
5702 #endif
5703 }
5704
5705 // Look up the method for a megamorphic invokeinterface call.
5706 // The target method is determined by <intf_klass, itable_index>.
5707 // The receiver klass is in recv_klass.
5708 // On success, the result will be in method_result, and execution falls through.
5709 // On failure, execution transfers to the given label.
5710 void MacroAssembler::lookup_interface_method(Register recv_klass,
5711 Register intf_klass,
5712 RegisterOrConstant itable_index,
5713 Register method_result,
5714 Register scan_temp,
5715 Label& L_no_such_interface) {
5716 assert_different_registers(recv_klass, intf_klass, method_result, scan_temp);
5717 assert(itable_index.is_constant() || itable_index.as_register() == method_result,
5718 "caller must use same register for non-constant itable index as for method");
5719
5720 // Compute start of first itableOffsetEntry (which is at the end of the vtable)
5721 int vtable_base = in_bytes(Klass::vtable_start_offset());
5722 int itentry_off = itableMethodEntry::method_offset_in_bytes();
5723 int scan_step = itableOffsetEntry::size() * wordSize;
5724 int vte_size = vtableEntry::size_in_bytes();
5725 Address::ScaleFactor times_vte_scale = Address::times_ptr;
5726 assert(vte_size == wordSize, "else adjust times_vte_scale");
5727
5728 movl(scan_temp, Address(recv_klass, Klass::vtable_length_offset()));
5729
5730 // %%% Could store the aligned, prescaled offset in the klassoop.
5731 lea(scan_temp, Address(recv_klass, scan_temp, times_vte_scale, vtable_base));
5732
5733 // Adjust recv_klass by scaled itable_index, so we can free itable_index.
5734 assert(itableMethodEntry::size() * wordSize == wordSize, "adjust the scaling in the code below");
5735 lea(recv_klass, Address(recv_klass, itable_index, Address::times_ptr, itentry_off));
5736
5737 // for (scan = klass->itable(); scan->interface() != NULL; scan += scan_step) {
5738 // if (scan->interface() == intf) {
5739 // result = (klass + scan->offset() + itable_index);
5740 // }
5741 // }
5742 Label search, found_method;
5743
5744 for (int peel = 1; peel >= 0; peel--) {
5745 movptr(method_result, Address(scan_temp, itableOffsetEntry::interface_offset_in_bytes()));
5746 cmpptr(intf_klass, method_result);
5747
5748 if (peel) {
5749 jccb(Assembler::equal, found_method);
5750 } else {
5751 jccb(Assembler::notEqual, search);
5752 // (invert the test to fall through to found_method...)
5753 }
5754
5755 if (!peel) break;
5756
5757 bind(search);
5758
5759 // Check that the previous entry is non-null. A null entry means that
5760 // the receiver class doesn't implement the interface, and wasn't the
5761 // same as when the caller was compiled.
5762 testptr(method_result, method_result);
5763 jcc(Assembler::zero, L_no_such_interface);
5764 addptr(scan_temp, scan_step);
5765 }
5766
5767 bind(found_method);
5768
5769 // Got a hit.
5770 movl(scan_temp, Address(scan_temp, itableOffsetEntry::offset_offset_in_bytes()));
5771 movptr(method_result, Address(recv_klass, scan_temp, Address::times_1));
5772 }
5773
5774
5775 // virtual method calling
5776 void MacroAssembler::lookup_virtual_method(Register recv_klass,
5777 RegisterOrConstant vtable_index,
5778 Register method_result) {
5779 const int base = in_bytes(Klass::vtable_start_offset());
5780 assert(vtableEntry::size() * wordSize == wordSize, "else adjust the scaling in the code below");
5781 Address vtable_entry_addr(recv_klass,
5782 vtable_index, Address::times_ptr,
5783 base + vtableEntry::method_offset_in_bytes());
5784 movptr(method_result, vtable_entry_addr);
5785 }
5786
5787
5788 void MacroAssembler::check_klass_subtype(Register sub_klass,
5789 Register super_klass,
5790 Register temp_reg,
5791 Label& L_success) {
5792 Label L_failure;
5793 check_klass_subtype_fast_path(sub_klass, super_klass, temp_reg, &L_success, &L_failure, NULL);
5794 check_klass_subtype_slow_path(sub_klass, super_klass, temp_reg, noreg, &L_success, NULL);
5795 bind(L_failure);
5796 }
5797
5798
5799 void MacroAssembler::check_klass_subtype_fast_path(Register sub_klass,
5800 Register super_klass,
5801 Register temp_reg,
5802 Label* L_success,
5803 Label* L_failure,
5804 Label* L_slow_path,
5805 RegisterOrConstant super_check_offset) {
5806 assert_different_registers(sub_klass, super_klass, temp_reg);
5807 bool must_load_sco = (super_check_offset.constant_or_zero() == -1);
5808 if (super_check_offset.is_register()) {
5809 assert_different_registers(sub_klass, super_klass,
5810 super_check_offset.as_register());
5811 } else if (must_load_sco) {
5812 assert(temp_reg != noreg, "supply either a temp or a register offset");
5813 }
5814
5815 Label L_fallthrough;
5816 int label_nulls = 0;
5817 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; }
5818 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; }
5819 if (L_slow_path == NULL) { L_slow_path = &L_fallthrough; label_nulls++; }
5820 assert(label_nulls <= 1, "at most one NULL in the batch");
5821
5822 int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
5823 int sco_offset = in_bytes(Klass::super_check_offset_offset());
5824 Address super_check_offset_addr(super_klass, sco_offset);
5825
5826 // Hacked jcc, which "knows" that L_fallthrough, at least, is in
5827 // range of a jccb. If this routine grows larger, reconsider at
5828 // least some of these.
5829 #define local_jcc(assembler_cond, label) \
5830 if (&(label) == &L_fallthrough) jccb(assembler_cond, label); \
5831 else jcc( assembler_cond, label) /*omit semi*/
5832
5833 // Hacked jmp, which may only be used just before L_fallthrough.
5834 #define final_jmp(label) \
5835 if (&(label) == &L_fallthrough) { /*do nothing*/ } \
5836 else jmp(label) /*omit semi*/
5837
5838 // If the pointers are equal, we are done (e.g., String[] elements).
5839 // This self-check enables sharing of secondary supertype arrays among
5840 // non-primary types such as array-of-interface. Otherwise, each such
5841 // type would need its own customized SSA.
5842 // We move this check to the front of the fast path because many
5843 // type checks are in fact trivially successful in this manner,
5844 // so we get a nicely predicted branch right at the start of the check.
5845 cmpptr(sub_klass, super_klass);
5846 local_jcc(Assembler::equal, *L_success);
5847
5848 // Check the supertype display:
5849 if (must_load_sco) {
5850 // Positive movl does right thing on LP64.
5851 movl(temp_reg, super_check_offset_addr);
5852 super_check_offset = RegisterOrConstant(temp_reg);
5853 }
5854 Address super_check_addr(sub_klass, super_check_offset, Address::times_1, 0);
5855 cmpptr(super_klass, super_check_addr); // load displayed supertype
5856
5857 // This check has worked decisively for primary supers.
5858 // Secondary supers are sought in the super_cache ('super_cache_addr').
5859 // (Secondary supers are interfaces and very deeply nested subtypes.)
5860 // This works in the same check above because of a tricky aliasing
5861 // between the super_cache and the primary super display elements.
5862 // (The 'super_check_addr' can address either, as the case requires.)
5863 // Note that the cache is updated below if it does not help us find
5864 // what we need immediately.
5865 // So if it was a primary super, we can just fail immediately.
5866 // Otherwise, it's the slow path for us (no success at this point).
5867
5868 if (super_check_offset.is_register()) {
5869 local_jcc(Assembler::equal, *L_success);
5870 cmpl(super_check_offset.as_register(), sc_offset);
5871 if (L_failure == &L_fallthrough) {
5872 local_jcc(Assembler::equal, *L_slow_path);
5873 } else {
5874 local_jcc(Assembler::notEqual, *L_failure);
5875 final_jmp(*L_slow_path);
5876 }
5877 } else if (super_check_offset.as_constant() == sc_offset) {
5878 // Need a slow path; fast failure is impossible.
5879 if (L_slow_path == &L_fallthrough) {
5880 local_jcc(Assembler::equal, *L_success);
5881 } else {
5882 local_jcc(Assembler::notEqual, *L_slow_path);
5883 final_jmp(*L_success);
5884 }
5885 } else {
5886 // No slow path; it's a fast decision.
5887 if (L_failure == &L_fallthrough) {
5888 local_jcc(Assembler::equal, *L_success);
5889 } else {
5890 local_jcc(Assembler::notEqual, *L_failure);
5891 final_jmp(*L_success);
5892 }
5893 }
5894
5895 bind(L_fallthrough);
5896
5897 #undef local_jcc
5898 #undef final_jmp
5899 }
5900
5901
5902 void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass,
5903 Register super_klass,
5904 Register temp_reg,
5905 Register temp2_reg,
5906 Label* L_success,
5907 Label* L_failure,
5908 bool set_cond_codes) {
5909 assert_different_registers(sub_klass, super_klass, temp_reg);
5910 if (temp2_reg != noreg)
5911 assert_different_registers(sub_klass, super_klass, temp_reg, temp2_reg);
5912 #define IS_A_TEMP(reg) ((reg) == temp_reg || (reg) == temp2_reg)
5913
5914 Label L_fallthrough;
5915 int label_nulls = 0;
5916 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; }
5917 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; }
5918 assert(label_nulls <= 1, "at most one NULL in the batch");
5919
5920 // a couple of useful fields in sub_klass:
5921 int ss_offset = in_bytes(Klass::secondary_supers_offset());
5922 int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
5923 Address secondary_supers_addr(sub_klass, ss_offset);
5924 Address super_cache_addr( sub_klass, sc_offset);
5925
5926 // Do a linear scan of the secondary super-klass chain.
5927 // This code is rarely used, so simplicity is a virtue here.
5928 // The repne_scan instruction uses fixed registers, which we must spill.
5929 // Don't worry too much about pre-existing connections with the input regs.
5930
5931 assert(sub_klass != rax, "killed reg"); // killed by mov(rax, super)
5932 assert(sub_klass != rcx, "killed reg"); // killed by lea(rcx, &pst_counter)
5933
5934 // Get super_klass value into rax (even if it was in rdi or rcx).
5935 bool pushed_rax = false, pushed_rcx = false, pushed_rdi = false;
5936 if (super_klass != rax || UseCompressedOops) {
5937 if (!IS_A_TEMP(rax)) { push(rax); pushed_rax = true; }
5938 mov(rax, super_klass);
5939 }
5940 if (!IS_A_TEMP(rcx)) { push(rcx); pushed_rcx = true; }
5941 if (!IS_A_TEMP(rdi)) { push(rdi); pushed_rdi = true; }
5942
5943 #ifndef PRODUCT
5944 int* pst_counter = &SharedRuntime::_partial_subtype_ctr;
5945 ExternalAddress pst_counter_addr((address) pst_counter);
5946 NOT_LP64( incrementl(pst_counter_addr) );
5947 LP64_ONLY( lea(rcx, pst_counter_addr) );
5948 LP64_ONLY( incrementl(Address(rcx, 0)) );
5949 #endif //PRODUCT
5950
5951 // We will consult the secondary-super array.
5952 movptr(rdi, secondary_supers_addr);
5953 // Load the array length. (Positive movl does right thing on LP64.)
5954 movl(rcx, Address(rdi, Array<Klass*>::length_offset_in_bytes()));
5955 // Skip to start of data.
5956 addptr(rdi, Array<Klass*>::base_offset_in_bytes());
5957
5958 // Scan RCX words at [RDI] for an occurrence of RAX.
5959 // Set NZ/Z based on last compare.
5960 // Z flag value will not be set by 'repne' if RCX == 0 since 'repne' does
5961 // not change flags (only scas instruction which is repeated sets flags).
5962 // Set Z = 0 (not equal) before 'repne' to indicate that class was not found.
5963
5964 testptr(rax,rax); // Set Z = 0
5965 repne_scan();
5966
5967 // Unspill the temp. registers:
5968 if (pushed_rdi) pop(rdi);
5969 if (pushed_rcx) pop(rcx);
5970 if (pushed_rax) pop(rax);
5971
5972 if (set_cond_codes) {
5973 // Special hack for the AD files: rdi is guaranteed non-zero.
5974 assert(!pushed_rdi, "rdi must be left non-NULL");
5975 // Also, the condition codes are properly set Z/NZ on succeed/failure.
5976 }
5977
5978 if (L_failure == &L_fallthrough)
5979 jccb(Assembler::notEqual, *L_failure);
5980 else jcc(Assembler::notEqual, *L_failure);
5981
5982 // Success. Cache the super we found and proceed in triumph.
5983 movptr(super_cache_addr, super_klass);
5984
5985 if (L_success != &L_fallthrough) {
5986 jmp(*L_success);
5987 }
5988
5989 #undef IS_A_TEMP
5990
5991 bind(L_fallthrough);
5992 }
5993
5994
5995 void MacroAssembler::cmov32(Condition cc, Register dst, Address src) {
5996 if (VM_Version::supports_cmov()) {
5997 cmovl(cc, dst, src);
5998 } else {
5999 Label L;
6000 jccb(negate_condition(cc), L);
6001 movl(dst, src);
6002 bind(L);
6003 }
6004 }
6005
6006 void MacroAssembler::cmov32(Condition cc, Register dst, Register src) {
6007 if (VM_Version::supports_cmov()) {
6008 cmovl(cc, dst, src);
6009 } else {
6010 Label L;
6011 jccb(negate_condition(cc), L);
6012 movl(dst, src);
6013 bind(L);
6014 }
6015 }
6016
6017 void MacroAssembler::verify_oop(Register reg, const char* s) {
6018 if (!VerifyOops) return;
6019
6020 // Pass register number to verify_oop_subroutine
6021 const char* b = NULL;
6022 {
6023 ResourceMark rm;
6024 stringStream ss;
6025 ss.print("verify_oop: %s: %s", reg->name(), s);
6026 b = code_string(ss.as_string());
6027 }
6028 BLOCK_COMMENT("verify_oop {");
6029 #ifdef _LP64
6030 push(rscratch1); // save r10, trashed by movptr()
6031 #endif
6032 push(rax); // save rax,
6033 push(reg); // pass register argument
6034 ExternalAddress buffer((address) b);
6035 // avoid using pushptr, as it modifies scratch registers
6036 // and our contract is not to modify anything
6037 movptr(rax, buffer.addr());
6038 push(rax);
6039 // call indirectly to solve generation ordering problem
6040 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
6041 call(rax);
6042 // Caller pops the arguments (oop, message) and restores rax, r10
6043 BLOCK_COMMENT("} verify_oop");
6044 }
6045
6046
6047 RegisterOrConstant MacroAssembler::delayed_value_impl(intptr_t* delayed_value_addr,
6048 Register tmp,
6049 int offset) {
6050 intptr_t value = *delayed_value_addr;
6051 if (value != 0)
6052 return RegisterOrConstant(value + offset);
6053
6054 // load indirectly to solve generation ordering problem
6055 movptr(tmp, ExternalAddress((address) delayed_value_addr));
6056
6057 #ifdef ASSERT
6058 { Label L;
6059 testptr(tmp, tmp);
6060 if (WizardMode) {
6061 const char* buf = NULL;
6062 {
6063 ResourceMark rm;
6064 stringStream ss;
6065 ss.print("DelayedValue=" INTPTR_FORMAT, delayed_value_addr[1]);
6066 buf = code_string(ss.as_string());
6067 }
6068 jcc(Assembler::notZero, L);
6069 STOP(buf);
6070 } else {
6071 jccb(Assembler::notZero, L);
6072 hlt();
6073 }
6074 bind(L);
6075 }
6076 #endif
6077
6078 if (offset != 0)
6079 addptr(tmp, offset);
6080
6081 return RegisterOrConstant(tmp);
6082 }
6083
6084
6085 Address MacroAssembler::argument_address(RegisterOrConstant arg_slot,
6086 int extra_slot_offset) {
6087 // cf. TemplateTable::prepare_invoke(), if (load_receiver).
6088 int stackElementSize = Interpreter::stackElementSize;
6089 int offset = Interpreter::expr_offset_in_bytes(extra_slot_offset+0);
6090 #ifdef ASSERT
6091 int offset1 = Interpreter::expr_offset_in_bytes(extra_slot_offset+1);
6092 assert(offset1 - offset == stackElementSize, "correct arithmetic");
6093 #endif
6094 Register scale_reg = noreg;
6095 Address::ScaleFactor scale_factor = Address::no_scale;
6096 if (arg_slot.is_constant()) {
6097 offset += arg_slot.as_constant() * stackElementSize;
6098 } else {
6099 scale_reg = arg_slot.as_register();
6100 scale_factor = Address::times(stackElementSize);
6101 }
6102 offset += wordSize; // return PC is on stack
6103 return Address(rsp, scale_reg, scale_factor, offset);
6104 }
6105
6106
6107 void MacroAssembler::verify_oop_addr(Address addr, const char* s) {
6108 if (!VerifyOops) return;
6109
6110 // Address adjust(addr.base(), addr.index(), addr.scale(), addr.disp() + BytesPerWord);
6111 // Pass register number to verify_oop_subroutine
6112 const char* b = NULL;
6113 {
6114 ResourceMark rm;
6115 stringStream ss;
6116 ss.print("verify_oop_addr: %s", s);
6117 b = code_string(ss.as_string());
6118 }
6119 #ifdef _LP64
6120 push(rscratch1); // save r10, trashed by movptr()
6121 #endif
6122 push(rax); // save rax,
6123 // addr may contain rsp so we will have to adjust it based on the push
6124 // we just did (and on 64 bit we do two pushes)
6125 // NOTE: 64bit seemed to have had a bug in that it did movq(addr, rax); which
6126 // stores rax into addr which is backwards of what was intended.
6127 if (addr.uses(rsp)) {
6128 lea(rax, addr);
6129 pushptr(Address(rax, LP64_ONLY(2 *) BytesPerWord));
6130 } else {
6131 pushptr(addr);
6132 }
6133
6134 ExternalAddress buffer((address) b);
6135 // pass msg argument
6136 // avoid using pushptr, as it modifies scratch registers
6137 // and our contract is not to modify anything
6138 movptr(rax, buffer.addr());
6139 push(rax);
6140
6141 // call indirectly to solve generation ordering problem
6142 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
6143 call(rax);
6144 // Caller pops the arguments (addr, message) and restores rax, r10.
6145 }
6146
6147 void MacroAssembler::verify_tlab() {
6148 #ifdef ASSERT
6149 if (UseTLAB && VerifyOops) {
6150 Label next, ok;
6151 Register t1 = rsi;
6152 Register thread_reg = NOT_LP64(rbx) LP64_ONLY(r15_thread);
6153
6154 push(t1);
6155 NOT_LP64(push(thread_reg));
6156 NOT_LP64(get_thread(thread_reg));
6157
6158 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())));
6159 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_start_offset())));
6160 jcc(Assembler::aboveEqual, next);
6161 STOP("assert(top >= start)");
6162 should_not_reach_here();
6163
6164 bind(next);
6165 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_end_offset())));
6166 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())));
6167 jcc(Assembler::aboveEqual, ok);
6168 STOP("assert(top <= end)");
6169 should_not_reach_here();
6170
6171 bind(ok);
6172 NOT_LP64(pop(thread_reg));
6173 pop(t1);
6174 }
6175 #endif
6176 }
6177
6178 class ControlWord {
6179 public:
6180 int32_t _value;
6181
6182 int rounding_control() const { return (_value >> 10) & 3 ; }
6183 int precision_control() const { return (_value >> 8) & 3 ; }
6184 bool precision() const { return ((_value >> 5) & 1) != 0; }
6185 bool underflow() const { return ((_value >> 4) & 1) != 0; }
6186 bool overflow() const { return ((_value >> 3) & 1) != 0; }
6187 bool zero_divide() const { return ((_value >> 2) & 1) != 0; }
6188 bool denormalized() const { return ((_value >> 1) & 1) != 0; }
6189 bool invalid() const { return ((_value >> 0) & 1) != 0; }
6190
6191 void print() const {
6192 // rounding control
6193 const char* rc;
6194 switch (rounding_control()) {
6195 case 0: rc = "round near"; break;
6196 case 1: rc = "round down"; break;
6197 case 2: rc = "round up "; break;
6198 case 3: rc = "chop "; break;
6199 };
6200 // precision control
6201 const char* pc;
6202 switch (precision_control()) {
6203 case 0: pc = "24 bits "; break;
6204 case 1: pc = "reserved"; break;
6205 case 2: pc = "53 bits "; break;
6206 case 3: pc = "64 bits "; break;
6207 };
6208 // flags
6209 char f[9];
6210 f[0] = ' ';
6211 f[1] = ' ';
6212 f[2] = (precision ()) ? 'P' : 'p';
6213 f[3] = (underflow ()) ? 'U' : 'u';
6214 f[4] = (overflow ()) ? 'O' : 'o';
6215 f[5] = (zero_divide ()) ? 'Z' : 'z';
6216 f[6] = (denormalized()) ? 'D' : 'd';
6217 f[7] = (invalid ()) ? 'I' : 'i';
6218 f[8] = '\x0';
6219 // output
6220 printf("%04x masks = %s, %s, %s", _value & 0xFFFF, f, rc, pc);
6221 }
6222
6223 };
6224
6225 class StatusWord {
6226 public:
6227 int32_t _value;
6228
6229 bool busy() const { return ((_value >> 15) & 1) != 0; }
6230 bool C3() const { return ((_value >> 14) & 1) != 0; }
6231 bool C2() const { return ((_value >> 10) & 1) != 0; }
6232 bool C1() const { return ((_value >> 9) & 1) != 0; }
6233 bool C0() const { return ((_value >> 8) & 1) != 0; }
6234 int top() const { return (_value >> 11) & 7 ; }
6235 bool error_status() const { return ((_value >> 7) & 1) != 0; }
6236 bool stack_fault() const { return ((_value >> 6) & 1) != 0; }
6237 bool precision() const { return ((_value >> 5) & 1) != 0; }
6238 bool underflow() const { return ((_value >> 4) & 1) != 0; }
6239 bool overflow() const { return ((_value >> 3) & 1) != 0; }
6240 bool zero_divide() const { return ((_value >> 2) & 1) != 0; }
6241 bool denormalized() const { return ((_value >> 1) & 1) != 0; }
6242 bool invalid() const { return ((_value >> 0) & 1) != 0; }
6243
6244 void print() const {
6245 // condition codes
6246 char c[5];
6247 c[0] = (C3()) ? '3' : '-';
6248 c[1] = (C2()) ? '2' : '-';
6249 c[2] = (C1()) ? '1' : '-';
6250 c[3] = (C0()) ? '0' : '-';
6251 c[4] = '\x0';
6252 // flags
6253 char f[9];
6254 f[0] = (error_status()) ? 'E' : '-';
6255 f[1] = (stack_fault ()) ? 'S' : '-';
6256 f[2] = (precision ()) ? 'P' : '-';
6257 f[3] = (underflow ()) ? 'U' : '-';
6258 f[4] = (overflow ()) ? 'O' : '-';
6259 f[5] = (zero_divide ()) ? 'Z' : '-';
6260 f[6] = (denormalized()) ? 'D' : '-';
6261 f[7] = (invalid ()) ? 'I' : '-';
6262 f[8] = '\x0';
6263 // output
6264 printf("%04x flags = %s, cc = %s, top = %d", _value & 0xFFFF, f, c, top());
6265 }
6266
6267 };
6268
6269 class TagWord {
6270 public:
6271 int32_t _value;
6272
6273 int tag_at(int i) const { return (_value >> (i*2)) & 3; }
6274
6275 void print() const {
6276 printf("%04x", _value & 0xFFFF);
6277 }
6278
6279 };
6280
6281 class FPU_Register {
6282 public:
6283 int32_t _m0;
6284 int32_t _m1;
6285 int16_t _ex;
6286
6287 bool is_indefinite() const {
6288 return _ex == -1 && _m1 == (int32_t)0xC0000000 && _m0 == 0;
6289 }
6290
6291 void print() const {
6292 char sign = (_ex < 0) ? '-' : '+';
6293 const char* kind = (_ex == 0x7FFF || _ex == (int16_t)-1) ? "NaN" : " ";
6294 printf("%c%04hx.%08x%08x %s", sign, _ex, _m1, _m0, kind);
6295 };
6296
6297 };
6298
6299 class FPU_State {
6300 public:
6301 enum {
6302 register_size = 10,
6303 number_of_registers = 8,
6304 register_mask = 7
6305 };
6306
6307 ControlWord _control_word;
6308 StatusWord _status_word;
6309 TagWord _tag_word;
6310 int32_t _error_offset;
6311 int32_t _error_selector;
6312 int32_t _data_offset;
6313 int32_t _data_selector;
6314 int8_t _register[register_size * number_of_registers];
6315
6316 int tag_for_st(int i) const { return _tag_word.tag_at((_status_word.top() + i) & register_mask); }
6317 FPU_Register* st(int i) const { return (FPU_Register*)&_register[register_size * i]; }
6318
6319 const char* tag_as_string(int tag) const {
6320 switch (tag) {
6321 case 0: return "valid";
6322 case 1: return "zero";
6323 case 2: return "special";
6324 case 3: return "empty";
6325 }
6326 ShouldNotReachHere();
6327 return NULL;
6328 }
6329
6330 void print() const {
6331 // print computation registers
6332 { int t = _status_word.top();
6333 for (int i = 0; i < number_of_registers; i++) {
6334 int j = (i - t) & register_mask;
6335 printf("%c r%d = ST%d = ", (j == 0 ? '*' : ' '), i, j);
6336 st(j)->print();
6337 printf(" %s\n", tag_as_string(_tag_word.tag_at(i)));
6338 }
6339 }
6340 printf("\n");
6341 // print control registers
6342 printf("ctrl = "); _control_word.print(); printf("\n");
6343 printf("stat = "); _status_word .print(); printf("\n");
6344 printf("tags = "); _tag_word .print(); printf("\n");
6345 }
6346
6347 };
6348
6349 class Flag_Register {
6350 public:
6351 int32_t _value;
6352
6353 bool overflow() const { return ((_value >> 11) & 1) != 0; }
6354 bool direction() const { return ((_value >> 10) & 1) != 0; }
6355 bool sign() const { return ((_value >> 7) & 1) != 0; }
6356 bool zero() const { return ((_value >> 6) & 1) != 0; }
6357 bool auxiliary_carry() const { return ((_value >> 4) & 1) != 0; }
6358 bool parity() const { return ((_value >> 2) & 1) != 0; }
6359 bool carry() const { return ((_value >> 0) & 1) != 0; }
6360
6361 void print() const {
6362 // flags
6363 char f[8];
6364 f[0] = (overflow ()) ? 'O' : '-';
6365 f[1] = (direction ()) ? 'D' : '-';
6366 f[2] = (sign ()) ? 'S' : '-';
6367 f[3] = (zero ()) ? 'Z' : '-';
6368 f[4] = (auxiliary_carry()) ? 'A' : '-';
6369 f[5] = (parity ()) ? 'P' : '-';
6370 f[6] = (carry ()) ? 'C' : '-';
6371 f[7] = '\x0';
6372 // output
6373 printf("%08x flags = %s", _value, f);
6374 }
6375
6376 };
6377
6378 class IU_Register {
6379 public:
6380 int32_t _value;
6381
6382 void print() const {
6383 printf("%08x %11d", _value, _value);
6384 }
6385
6386 };
6387
6388 class IU_State {
6389 public:
6390 Flag_Register _eflags;
6391 IU_Register _rdi;
6392 IU_Register _rsi;
6393 IU_Register _rbp;
6394 IU_Register _rsp;
6395 IU_Register _rbx;
6396 IU_Register _rdx;
6397 IU_Register _rcx;
6398 IU_Register _rax;
6399
6400 void print() const {
6401 // computation registers
6402 printf("rax, = "); _rax.print(); printf("\n");
6403 printf("rbx, = "); _rbx.print(); printf("\n");
6404 printf("rcx = "); _rcx.print(); printf("\n");
6405 printf("rdx = "); _rdx.print(); printf("\n");
6406 printf("rdi = "); _rdi.print(); printf("\n");
6407 printf("rsi = "); _rsi.print(); printf("\n");
6408 printf("rbp, = "); _rbp.print(); printf("\n");
6409 printf("rsp = "); _rsp.print(); printf("\n");
6410 printf("\n");
6411 // control registers
6412 printf("flgs = "); _eflags.print(); printf("\n");
6413 }
6414 };
6415
6416
6417 class CPU_State {
6418 public:
6419 FPU_State _fpu_state;
6420 IU_State _iu_state;
6421
6422 void print() const {
6423 printf("--------------------------------------------------\n");
6424 _iu_state .print();
6425 printf("\n");
6426 _fpu_state.print();
6427 printf("--------------------------------------------------\n");
6428 }
6429
6430 };
6431
6432
6433 static void _print_CPU_state(CPU_State* state) {
6434 state->print();
6435 };
6436
6437
6438 void MacroAssembler::print_CPU_state() {
6439 push_CPU_state();
6440 push(rsp); // pass CPU state
6441 call(RuntimeAddress(CAST_FROM_FN_PTR(address, _print_CPU_state)));
6442 addptr(rsp, wordSize); // discard argument
6443 pop_CPU_state();
6444 }
6445
6446
6447 static bool _verify_FPU(int stack_depth, char* s, CPU_State* state) {
6448 static int counter = 0;
6449 FPU_State* fs = &state->_fpu_state;
6450 counter++;
6451 // For leaf calls, only verify that the top few elements remain empty.
6452 // We only need 1 empty at the top for C2 code.
6453 if( stack_depth < 0 ) {
6454 if( fs->tag_for_st(7) != 3 ) {
6455 printf("FPR7 not empty\n");
6456 state->print();
6457 assert(false, "error");
6458 return false;
6459 }
6460 return true; // All other stack states do not matter
6461 }
6462
6463 assert((fs->_control_word._value & 0xffff) == StubRoutines::_fpu_cntrl_wrd_std,
6464 "bad FPU control word");
6465
6466 // compute stack depth
6467 int i = 0;
6468 while (i < FPU_State::number_of_registers && fs->tag_for_st(i) < 3) i++;
6469 int d = i;
6470 while (i < FPU_State::number_of_registers && fs->tag_for_st(i) == 3) i++;
6471 // verify findings
6472 if (i != FPU_State::number_of_registers) {
6473 // stack not contiguous
6474 printf("%s: stack not contiguous at ST%d\n", s, i);
6475 state->print();
6476 assert(false, "error");
6477 return false;
6478 }
6479 // check if computed stack depth corresponds to expected stack depth
6480 if (stack_depth < 0) {
6481 // expected stack depth is -stack_depth or less
6482 if (d > -stack_depth) {
6483 // too many elements on the stack
6484 printf("%s: <= %d stack elements expected but found %d\n", s, -stack_depth, d);
6485 state->print();
6486 assert(false, "error");
6487 return false;
6488 }
6489 } else {
6490 // expected stack depth is stack_depth
6491 if (d != stack_depth) {
6492 // wrong stack depth
6493 printf("%s: %d stack elements expected but found %d\n", s, stack_depth, d);
6494 state->print();
6495 assert(false, "error");
6496 return false;
6497 }
6498 }
6499 // everything is cool
6500 return true;
6501 }
6502
6503
6504 void MacroAssembler::verify_FPU(int stack_depth, const char* s) {
6505 if (!VerifyFPU) return;
6506 push_CPU_state();
6507 push(rsp); // pass CPU state
6508 ExternalAddress msg((address) s);
6509 // pass message string s
6510 pushptr(msg.addr());
6511 push(stack_depth); // pass stack depth
6512 call(RuntimeAddress(CAST_FROM_FN_PTR(address, _verify_FPU)));
6513 addptr(rsp, 3 * wordSize); // discard arguments
6514 // check for error
6515 { Label L;
6516 testl(rax, rax);
6517 jcc(Assembler::notZero, L);
6518 int3(); // break if error condition
6519 bind(L);
6520 }
6521 pop_CPU_state();
6522 }
6523
6524 void MacroAssembler::restore_cpu_control_state_after_jni() {
6525 // Either restore the MXCSR register after returning from the JNI Call
6526 // or verify that it wasn't changed (with -Xcheck:jni flag).
6527 if (VM_Version::supports_sse()) {
6528 if (RestoreMXCSROnJNICalls) {
6529 ldmxcsr(ExternalAddress(StubRoutines::addr_mxcsr_std()));
6530 } else if (CheckJNICalls) {
6531 call(RuntimeAddress(StubRoutines::x86::verify_mxcsr_entry()));
6532 }
6533 }
6534 // Clear upper bits of YMM registers to avoid SSE <-> AVX transition penalty.
6535 vzeroupper();
6536
6537 #ifndef _LP64
6538 // Either restore the x87 floating pointer control word after returning
6539 // from the JNI call or verify that it wasn't changed.
6540 if (CheckJNICalls) {
6541 call(RuntimeAddress(StubRoutines::x86::verify_fpu_cntrl_wrd_entry()));
6542 }
6543 #endif // _LP64
6544 }
6545
6546 void MacroAssembler::load_mirror(Register mirror, Register method) {
6547 // get mirror
6548 const int mirror_offset = in_bytes(Klass::java_mirror_offset());
6549 movptr(mirror, Address(method, Method::const_offset()));
6550 movptr(mirror, Address(mirror, ConstMethod::constants_offset()));
6551 movptr(mirror, Address(mirror, ConstantPool::pool_holder_offset_in_bytes()));
6552 movptr(mirror, Address(mirror, mirror_offset));
6553 }
6554
6555 void MacroAssembler::load_klass(Register dst, Register src) {
6556 #ifdef _LP64
6557 if (UseCompressedClassPointers) {
6558 movl(dst, Address(src, oopDesc::klass_offset_in_bytes()));
6559 decode_klass_not_null(dst);
6560 } else
6561 #endif
6562 movptr(dst, Address(src, oopDesc::klass_offset_in_bytes()));
6563 }
6564
6565 void MacroAssembler::load_prototype_header(Register dst, Register src) {
6566 load_klass(dst, src);
6567 movptr(dst, Address(dst, Klass::prototype_header_offset()));
6568 }
6569
6570 void MacroAssembler::store_klass(Register dst, Register src) {
6571 #ifdef _LP64
6572 if (UseCompressedClassPointers) {
6573 encode_klass_not_null(src);
6574 movl(Address(dst, oopDesc::klass_offset_in_bytes()), src);
6575 } else
6576 #endif
6577 movptr(Address(dst, oopDesc::klass_offset_in_bytes()), src);
6578 }
6579
6580 void MacroAssembler::load_heap_oop(Register dst, Address src) {
6581 #ifdef _LP64
6582 // FIXME: Must change all places where we try to load the klass.
6583 if (UseCompressedOops) {
6584 movl(dst, src);
6585 decode_heap_oop(dst);
6586 } else
6587 #endif
6588 movptr(dst, src);
6589 }
6590
6591 // Doesn't do verfication, generates fixed size code
6592 void MacroAssembler::load_heap_oop_not_null(Register dst, Address src) {
6593 #ifdef _LP64
6594 if (UseCompressedOops) {
6595 movl(dst, src);
6596 decode_heap_oop_not_null(dst);
6597 } else
6598 #endif
6599 movptr(dst, src);
6600 }
6601
6602 void MacroAssembler::store_heap_oop(Address dst, Register src) {
6603 #ifdef _LP64
6604 if (UseCompressedOops) {
6605 assert(!dst.uses(src), "not enough registers");
6606 encode_heap_oop(src);
6607 movl(dst, src);
6608 } else
6609 #endif
6610 movptr(dst, src);
6611 }
6612
6613 void MacroAssembler::cmp_heap_oop(Register src1, Address src2, Register tmp) {
6614 assert_different_registers(src1, tmp);
6615 #ifdef _LP64
6616 if (UseCompressedOops) {
6617 bool did_push = false;
6618 if (tmp == noreg) {
6619 tmp = rax;
6620 push(tmp);
6621 did_push = true;
6622 assert(!src2.uses(rsp), "can't push");
6623 }
6624 load_heap_oop(tmp, src2);
6625 cmpptr(src1, tmp);
6626 if (did_push) pop(tmp);
6627 } else
6628 #endif
6629 cmpptr(src1, src2);
6630 }
6631
6632 // Used for storing NULLs.
6633 void MacroAssembler::store_heap_oop_null(Address dst) {
6634 #ifdef _LP64
6635 if (UseCompressedOops) {
6636 movl(dst, (int32_t)NULL_WORD);
6637 } else {
6638 movslq(dst, (int32_t)NULL_WORD);
6639 }
6640 #else
6641 movl(dst, (int32_t)NULL_WORD);
6642 #endif
6643 }
6644
6645 #ifdef _LP64
6646 void MacroAssembler::store_klass_gap(Register dst, Register src) {
6647 if (UseCompressedClassPointers) {
6648 // Store to klass gap in destination
6649 movl(Address(dst, oopDesc::klass_gap_offset_in_bytes()), src);
6650 }
6651 }
6652
6653 #ifdef ASSERT
6654 void MacroAssembler::verify_heapbase(const char* msg) {
6655 assert (UseCompressedOops, "should be compressed");
6656 assert (Universe::heap() != NULL, "java heap should be initialized");
6657 if (CheckCompressedOops) {
6658 Label ok;
6659 push(rscratch1); // cmpptr trashes rscratch1
6660 cmpptr(r12_heapbase, ExternalAddress((address)Universe::narrow_ptrs_base_addr()));
6661 jcc(Assembler::equal, ok);
6662 STOP(msg);
6663 bind(ok);
6664 pop(rscratch1);
6665 }
6666 }
6667 #endif
6668
6669 // Algorithm must match oop.inline.hpp encode_heap_oop.
6670 void MacroAssembler::encode_heap_oop(Register r) {
6671 #ifdef ASSERT
6672 verify_heapbase("MacroAssembler::encode_heap_oop: heap base corrupted?");
6673 #endif
6674 verify_oop(r, "broken oop in encode_heap_oop");
6675 if (Universe::narrow_oop_base() == NULL) {
6676 if (Universe::narrow_oop_shift() != 0) {
6677 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
6678 shrq(r, LogMinObjAlignmentInBytes);
6679 }
6680 return;
6681 }
6682 testq(r, r);
6683 cmovq(Assembler::equal, r, r12_heapbase);
6684 subq(r, r12_heapbase);
6685 shrq(r, LogMinObjAlignmentInBytes);
6686 }
6687
6688 void MacroAssembler::encode_heap_oop_not_null(Register r) {
6689 #ifdef ASSERT
6690 verify_heapbase("MacroAssembler::encode_heap_oop_not_null: heap base corrupted?");
6691 if (CheckCompressedOops) {
6692 Label ok;
6693 testq(r, r);
6694 jcc(Assembler::notEqual, ok);
6695 STOP("null oop passed to encode_heap_oop_not_null");
6696 bind(ok);
6697 }
6698 #endif
6699 verify_oop(r, "broken oop in encode_heap_oop_not_null");
6700 if (Universe::narrow_oop_base() != NULL) {
6701 subq(r, r12_heapbase);
6702 }
6703 if (Universe::narrow_oop_shift() != 0) {
6704 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
6705 shrq(r, LogMinObjAlignmentInBytes);
6706 }
6707 }
6708
6709 void MacroAssembler::encode_heap_oop_not_null(Register dst, Register src) {
6710 #ifdef ASSERT
6711 verify_heapbase("MacroAssembler::encode_heap_oop_not_null2: heap base corrupted?");
6712 if (CheckCompressedOops) {
6713 Label ok;
6714 testq(src, src);
6715 jcc(Assembler::notEqual, ok);
6716 STOP("null oop passed to encode_heap_oop_not_null2");
6717 bind(ok);
6718 }
6719 #endif
6720 verify_oop(src, "broken oop in encode_heap_oop_not_null2");
6721 if (dst != src) {
6722 movq(dst, src);
6723 }
6724 if (Universe::narrow_oop_base() != NULL) {
6725 subq(dst, r12_heapbase);
6726 }
6727 if (Universe::narrow_oop_shift() != 0) {
6728 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
6729 shrq(dst, LogMinObjAlignmentInBytes);
6730 }
6731 }
6732
6733 void MacroAssembler::decode_heap_oop(Register r) {
6734 #ifdef ASSERT
6735 verify_heapbase("MacroAssembler::decode_heap_oop: heap base corrupted?");
6736 #endif
6737 if (Universe::narrow_oop_base() == NULL) {
6738 if (Universe::narrow_oop_shift() != 0) {
6739 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
6740 shlq(r, LogMinObjAlignmentInBytes);
6741 }
6742 } else {
6743 Label done;
6744 shlq(r, LogMinObjAlignmentInBytes);
6745 jccb(Assembler::equal, done);
6746 addq(r, r12_heapbase);
6747 bind(done);
6748 }
6749 verify_oop(r, "broken oop in decode_heap_oop");
6750 }
6751
6752 void MacroAssembler::decode_heap_oop_not_null(Register r) {
6753 // Note: it will change flags
6754 assert (UseCompressedOops, "should only be used for compressed headers");
6755 assert (Universe::heap() != NULL, "java heap should be initialized");
6756 // Cannot assert, unverified entry point counts instructions (see .ad file)
6757 // vtableStubs also counts instructions in pd_code_size_limit.
6758 // Also do not verify_oop as this is called by verify_oop.
6759 if (Universe::narrow_oop_shift() != 0) {
6760 assert(LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
6761 shlq(r, LogMinObjAlignmentInBytes);
6762 if (Universe::narrow_oop_base() != NULL) {
6763 addq(r, r12_heapbase);
6764 }
6765 } else {
6766 assert (Universe::narrow_oop_base() == NULL, "sanity");
6767 }
6768 }
6769
6770 void MacroAssembler::decode_heap_oop_not_null(Register dst, Register src) {
6771 // Note: it will change flags
6772 assert (UseCompressedOops, "should only be used for compressed headers");
6773 assert (Universe::heap() != NULL, "java heap should be initialized");
6774 // Cannot assert, unverified entry point counts instructions (see .ad file)
6775 // vtableStubs also counts instructions in pd_code_size_limit.
6776 // Also do not verify_oop as this is called by verify_oop.
6777 if (Universe::narrow_oop_shift() != 0) {
6778 assert(LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
6779 if (LogMinObjAlignmentInBytes == Address::times_8) {
6780 leaq(dst, Address(r12_heapbase, src, Address::times_8, 0));
6781 } else {
6782 if (dst != src) {
6783 movq(dst, src);
6784 }
6785 shlq(dst, LogMinObjAlignmentInBytes);
6786 if (Universe::narrow_oop_base() != NULL) {
6787 addq(dst, r12_heapbase);
6788 }
6789 }
6790 } else {
6791 assert (Universe::narrow_oop_base() == NULL, "sanity");
6792 if (dst != src) {
6793 movq(dst, src);
6794 }
6795 }
6796 }
6797
6798 void MacroAssembler::encode_klass_not_null(Register r) {
6799 if (Universe::narrow_klass_base() != NULL) {
6800 // Use r12 as a scratch register in which to temporarily load the narrow_klass_base.
6801 assert(r != r12_heapbase, "Encoding a klass in r12");
6802 mov64(r12_heapbase, (int64_t)Universe::narrow_klass_base());
6803 subq(r, r12_heapbase);
6804 }
6805 if (Universe::narrow_klass_shift() != 0) {
6806 assert (LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
6807 shrq(r, LogKlassAlignmentInBytes);
6808 }
6809 if (Universe::narrow_klass_base() != NULL) {
6810 reinit_heapbase();
6811 }
6812 }
6813
6814 void MacroAssembler::encode_klass_not_null(Register dst, Register src) {
6815 if (dst == src) {
6816 encode_klass_not_null(src);
6817 } else {
6818 if (Universe::narrow_klass_base() != NULL) {
6819 mov64(dst, (int64_t)Universe::narrow_klass_base());
6820 negq(dst);
6821 addq(dst, src);
6822 } else {
6823 movptr(dst, src);
6824 }
6825 if (Universe::narrow_klass_shift() != 0) {
6826 assert (LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
6827 shrq(dst, LogKlassAlignmentInBytes);
6828 }
6829 }
6830 }
6831
6832 // Function instr_size_for_decode_klass_not_null() counts the instructions
6833 // generated by decode_klass_not_null(register r) and reinit_heapbase(),
6834 // when (Universe::heap() != NULL). Hence, if the instructions they
6835 // generate change, then this method needs to be updated.
6836 int MacroAssembler::instr_size_for_decode_klass_not_null() {
6837 assert (UseCompressedClassPointers, "only for compressed klass ptrs");
6838 if (Universe::narrow_klass_base() != NULL) {
6839 // mov64 + addq + shlq? + mov64 (for reinit_heapbase()).
6840 return (Universe::narrow_klass_shift() == 0 ? 20 : 24);
6841 } else {
6842 // longest load decode klass function, mov64, leaq
6843 return 16;
6844 }
6845 }
6846
6847 // !!! If the instructions that get generated here change then function
6848 // instr_size_for_decode_klass_not_null() needs to get updated.
6849 void MacroAssembler::decode_klass_not_null(Register r) {
6850 // Note: it will change flags
6851 assert (UseCompressedClassPointers, "should only be used for compressed headers");
6852 assert(r != r12_heapbase, "Decoding a klass in r12");
6853 // Cannot assert, unverified entry point counts instructions (see .ad file)
6854 // vtableStubs also counts instructions in pd_code_size_limit.
6855 // Also do not verify_oop as this is called by verify_oop.
6856 if (Universe::narrow_klass_shift() != 0) {
6857 assert(LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
6858 shlq(r, LogKlassAlignmentInBytes);
6859 }
6860 // Use r12 as a scratch register in which to temporarily load the narrow_klass_base.
6861 if (Universe::narrow_klass_base() != NULL) {
6862 mov64(r12_heapbase, (int64_t)Universe::narrow_klass_base());
6863 addq(r, r12_heapbase);
6864 reinit_heapbase();
6865 }
6866 }
6867
6868 void MacroAssembler::decode_klass_not_null(Register dst, Register src) {
6869 // Note: it will change flags
6870 assert (UseCompressedClassPointers, "should only be used for compressed headers");
6871 if (dst == src) {
6872 decode_klass_not_null(dst);
6873 } else {
6874 // Cannot assert, unverified entry point counts instructions (see .ad file)
6875 // vtableStubs also counts instructions in pd_code_size_limit.
6876 // Also do not verify_oop as this is called by verify_oop.
6877 mov64(dst, (int64_t)Universe::narrow_klass_base());
6878 if (Universe::narrow_klass_shift() != 0) {
6879 assert(LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
6880 assert(LogKlassAlignmentInBytes == Address::times_8, "klass not aligned on 64bits?");
6881 leaq(dst, Address(dst, src, Address::times_8, 0));
6882 } else {
6883 addq(dst, src);
6884 }
6885 }
6886 }
6887
6888 void MacroAssembler::set_narrow_oop(Register dst, jobject obj) {
6889 assert (UseCompressedOops, "should only be used for compressed headers");
6890 assert (Universe::heap() != NULL, "java heap should be initialized");
6891 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
6892 int oop_index = oop_recorder()->find_index(obj);
6893 RelocationHolder rspec = oop_Relocation::spec(oop_index);
6894 mov_narrow_oop(dst, oop_index, rspec);
6895 }
6896
6897 void MacroAssembler::set_narrow_oop(Address dst, jobject obj) {
6898 assert (UseCompressedOops, "should only be used for compressed headers");
6899 assert (Universe::heap() != NULL, "java heap should be initialized");
6900 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
6901 int oop_index = oop_recorder()->find_index(obj);
6902 RelocationHolder rspec = oop_Relocation::spec(oop_index);
6903 mov_narrow_oop(dst, oop_index, rspec);
6904 }
6905
6906 void MacroAssembler::set_narrow_klass(Register dst, Klass* k) {
6907 assert (UseCompressedClassPointers, "should only be used for compressed headers");
6908 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
6909 int klass_index = oop_recorder()->find_index(k);
6910 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
6911 mov_narrow_oop(dst, Klass::encode_klass(k), rspec);
6912 }
6913
6914 void MacroAssembler::set_narrow_klass(Address dst, Klass* k) {
6915 assert (UseCompressedClassPointers, "should only be used for compressed headers");
6916 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
6917 int klass_index = oop_recorder()->find_index(k);
6918 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
6919 mov_narrow_oop(dst, Klass::encode_klass(k), rspec);
6920 }
6921
6922 void MacroAssembler::cmp_narrow_oop(Register dst, jobject obj) {
6923 assert (UseCompressedOops, "should only be used for compressed headers");
6924 assert (Universe::heap() != NULL, "java heap should be initialized");
6925 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
6926 int oop_index = oop_recorder()->find_index(obj);
6927 RelocationHolder rspec = oop_Relocation::spec(oop_index);
6928 Assembler::cmp_narrow_oop(dst, oop_index, rspec);
6929 }
6930
6931 void MacroAssembler::cmp_narrow_oop(Address dst, jobject obj) {
6932 assert (UseCompressedOops, "should only be used for compressed headers");
6933 assert (Universe::heap() != NULL, "java heap should be initialized");
6934 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
6935 int oop_index = oop_recorder()->find_index(obj);
6936 RelocationHolder rspec = oop_Relocation::spec(oop_index);
6937 Assembler::cmp_narrow_oop(dst, oop_index, rspec);
6938 }
6939
6940 void MacroAssembler::cmp_narrow_klass(Register dst, Klass* k) {
6941 assert (UseCompressedClassPointers, "should only be used for compressed headers");
6942 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
6943 int klass_index = oop_recorder()->find_index(k);
6944 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
6945 Assembler::cmp_narrow_oop(dst, Klass::encode_klass(k), rspec);
6946 }
6947
6948 void MacroAssembler::cmp_narrow_klass(Address dst, Klass* k) {
6949 assert (UseCompressedClassPointers, "should only be used for compressed headers");
6950 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
6951 int klass_index = oop_recorder()->find_index(k);
6952 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
6953 Assembler::cmp_narrow_oop(dst, Klass::encode_klass(k), rspec);
6954 }
6955
6956 void MacroAssembler::reinit_heapbase() {
6957 if (UseCompressedOops || UseCompressedClassPointers) {
6958 if (Universe::heap() != NULL) {
6959 if (Universe::narrow_oop_base() == NULL) {
6960 MacroAssembler::xorptr(r12_heapbase, r12_heapbase);
6961 } else {
6962 mov64(r12_heapbase, (int64_t)Universe::narrow_ptrs_base());
6963 }
6964 } else {
6965 movptr(r12_heapbase, ExternalAddress((address)Universe::narrow_ptrs_base_addr()));
6966 }
6967 }
6968 }
6969
6970 #endif // _LP64
6971
6972
6973 // C2 compiled method's prolog code.
6974 void MacroAssembler::verified_entry(int framesize, int stack_bang_size, bool fp_mode_24b) {
6975
6976 // WARNING: Initial instruction MUST be 5 bytes or longer so that
6977 // NativeJump::patch_verified_entry will be able to patch out the entry
6978 // code safely. The push to verify stack depth is ok at 5 bytes,
6979 // the frame allocation can be either 3 or 6 bytes. So if we don't do
6980 // stack bang then we must use the 6 byte frame allocation even if
6981 // we have no frame. :-(
6982 assert(stack_bang_size >= framesize || stack_bang_size <= 0, "stack bang size incorrect");
6983
6984 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
6985 // Remove word for return addr
6986 framesize -= wordSize;
6987 stack_bang_size -= wordSize;
6988
6989 // Calls to C2R adapters often do not accept exceptional returns.
6990 // We require that their callers must bang for them. But be careful, because
6991 // some VM calls (such as call site linkage) can use several kilobytes of
6992 // stack. But the stack safety zone should account for that.
6993 // See bugs 4446381, 4468289, 4497237.
6994 if (stack_bang_size > 0) {
6995 generate_stack_overflow_check(stack_bang_size);
6996
6997 // We always push rbp, so that on return to interpreter rbp, will be
6998 // restored correctly and we can correct the stack.
6999 push(rbp);
7000 // Save caller's stack pointer into RBP if the frame pointer is preserved.
7001 if (PreserveFramePointer) {
7002 mov(rbp, rsp);
7003 }
7004 // Remove word for ebp
7005 framesize -= wordSize;
7006
7007 // Create frame
7008 if (framesize) {
7009 subptr(rsp, framesize);
7010 }
7011 } else {
7012 // Create frame (force generation of a 4 byte immediate value)
7013 subptr_imm32(rsp, framesize);
7014
7015 // Save RBP register now.
7016 framesize -= wordSize;
7017 movptr(Address(rsp, framesize), rbp);
7018 // Save caller's stack pointer into RBP if the frame pointer is preserved.
7019 if (PreserveFramePointer) {
7020 movptr(rbp, rsp);
7021 if (framesize > 0) {
7022 addptr(rbp, framesize);
7023 }
7024 }
7025 }
7026
7027 if (VerifyStackAtCalls) { // Majik cookie to verify stack depth
7028 framesize -= wordSize;
7029 movptr(Address(rsp, framesize), (int32_t)0xbadb100d);
7030 }
7031
7032 #ifndef _LP64
7033 // If method sets FPU control word do it now
7034 if (fp_mode_24b) {
7035 fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
7036 }
7037 if (UseSSE >= 2 && VerifyFPU) {
7038 verify_FPU(0, "FPU stack must be clean on entry");
7039 }
7040 #endif
7041
7042 #ifdef ASSERT
7043 if (VerifyStackAtCalls) {
7044 Label L;
7045 push(rax);
7046 mov(rax, rsp);
7047 andptr(rax, StackAlignmentInBytes-1);
7048 cmpptr(rax, StackAlignmentInBytes-wordSize);
7049 pop(rax);
7050 jcc(Assembler::equal, L);
7051 STOP("Stack is not properly aligned!");
7052 bind(L);
7053 }
7054 #endif
7055
7056 }
7057
7058 void MacroAssembler::clear_mem(Register base, Register cnt, Register tmp, bool is_large) {
7059 // cnt - number of qwords (8-byte words).
7060 // base - start address, qword aligned.
7061 // is_large - if optimizers know cnt is larger than InitArrayShortSize
7062 assert(base==rdi, "base register must be edi for rep stos");
7063 assert(tmp==rax, "tmp register must be eax for rep stos");
7064 assert(cnt==rcx, "cnt register must be ecx for rep stos");
7065 assert(InitArrayShortSize % BytesPerLong == 0,
7066 "InitArrayShortSize should be the multiple of BytesPerLong");
7067
7068 Label DONE;
7069
7070 xorptr(tmp, tmp);
7071
7072 if (!is_large) {
7073 Label LOOP, LONG;
7074 cmpptr(cnt, InitArrayShortSize/BytesPerLong);
7075 jccb(Assembler::greater, LONG);
7076
7077 NOT_LP64(shlptr(cnt, 1);) // convert to number of 32-bit words for 32-bit VM
7078
7079 decrement(cnt);
7080 jccb(Assembler::negative, DONE); // Zero length
7081
7082 // Use individual pointer-sized stores for small counts:
7083 BIND(LOOP);
7084 movptr(Address(base, cnt, Address::times_ptr), tmp);
7085 decrement(cnt);
7086 jccb(Assembler::greaterEqual, LOOP);
7087 jmpb(DONE);
7088
7089 BIND(LONG);
7090 }
7091
7092 // Use longer rep-prefixed ops for non-small counts:
7093 if (UseFastStosb) {
7094 shlptr(cnt, 3); // convert to number of bytes
7095 rep_stosb();
7096 } else {
7097 NOT_LP64(shlptr(cnt, 1);) // convert to number of 32-bit words for 32-bit VM
7098 rep_stos();
7099 }
7100
7101 BIND(DONE);
7102 }
7103
7104 #ifdef COMPILER2
7105
7106 // IndexOf for constant substrings with size >= 8 chars
7107 // which don't need to be loaded through stack.
7108 void MacroAssembler::string_indexofC8(Register str1, Register str2,
7109 Register cnt1, Register cnt2,
7110 int int_cnt2, Register result,
7111 XMMRegister vec, Register tmp,
7112 int ae) {
7113 ShortBranchVerifier sbv(this);
7114 assert(UseSSE42Intrinsics, "SSE4.2 intrinsics are required");
7115 assert(ae != StrIntrinsicNode::LU, "Invalid encoding");
7116
7117 // This method uses the pcmpestri instruction with bound registers
7118 // inputs:
7119 // xmm - substring
7120 // rax - substring length (elements count)
7121 // mem - scanned string
7122 // rdx - string length (elements count)
7123 // 0xd - mode: 1100 (substring search) + 01 (unsigned shorts)
7124 // 0xc - mode: 1100 (substring search) + 00 (unsigned bytes)
7125 // outputs:
7126 // rcx - matched index in string
7127 assert(cnt1 == rdx && cnt2 == rax && tmp == rcx, "pcmpestri");
7128 int mode = (ae == StrIntrinsicNode::LL) ? 0x0c : 0x0d; // bytes or shorts
7129 int stride = (ae == StrIntrinsicNode::LL) ? 16 : 8; //UU, UL -> 8
7130 Address::ScaleFactor scale1 = (ae == StrIntrinsicNode::LL) ? Address::times_1 : Address::times_2;
7131 Address::ScaleFactor scale2 = (ae == StrIntrinsicNode::UL) ? Address::times_1 : scale1;
7132
7133 Label RELOAD_SUBSTR, SCAN_TO_SUBSTR, SCAN_SUBSTR,
7134 RET_FOUND, RET_NOT_FOUND, EXIT, FOUND_SUBSTR,
7135 MATCH_SUBSTR_HEAD, RELOAD_STR, FOUND_CANDIDATE;
7136
7137 // Note, inline_string_indexOf() generates checks:
7138 // if (substr.count > string.count) return -1;
7139 // if (substr.count == 0) return 0;
7140 assert(int_cnt2 >= stride, "this code is used only for cnt2 >= 8 chars");
7141
7142 // Load substring.
7143 if (ae == StrIntrinsicNode::UL) {
7144 pmovzxbw(vec, Address(str2, 0));
7145 } else {
7146 movdqu(vec, Address(str2, 0));
7147 }
7148 movl(cnt2, int_cnt2);
7149 movptr(result, str1); // string addr
7150
7151 if (int_cnt2 > stride) {
7152 jmpb(SCAN_TO_SUBSTR);
7153
7154 // Reload substr for rescan, this code
7155 // is executed only for large substrings (> 8 chars)
7156 bind(RELOAD_SUBSTR);
7157 if (ae == StrIntrinsicNode::UL) {
7158 pmovzxbw(vec, Address(str2, 0));
7159 } else {
7160 movdqu(vec, Address(str2, 0));
7161 }
7162 negptr(cnt2); // Jumped here with negative cnt2, convert to positive
7163
7164 bind(RELOAD_STR);
7165 // We came here after the beginning of the substring was
7166 // matched but the rest of it was not so we need to search
7167 // again. Start from the next element after the previous match.
7168
7169 // cnt2 is number of substring reminding elements and
7170 // cnt1 is number of string reminding elements when cmp failed.
7171 // Restored cnt1 = cnt1 - cnt2 + int_cnt2
7172 subl(cnt1, cnt2);
7173 addl(cnt1, int_cnt2);
7174 movl(cnt2, int_cnt2); // Now restore cnt2
7175
7176 decrementl(cnt1); // Shift to next element
7177 cmpl(cnt1, cnt2);
7178 jcc(Assembler::negative, RET_NOT_FOUND); // Left less then substring
7179
7180 addptr(result, (1<<scale1));
7181
7182 } // (int_cnt2 > 8)
7183
7184 // Scan string for start of substr in 16-byte vectors
7185 bind(SCAN_TO_SUBSTR);
7186 pcmpestri(vec, Address(result, 0), mode);
7187 jccb(Assembler::below, FOUND_CANDIDATE); // CF == 1
7188 subl(cnt1, stride);
7189 jccb(Assembler::lessEqual, RET_NOT_FOUND); // Scanned full string
7190 cmpl(cnt1, cnt2);
7191 jccb(Assembler::negative, RET_NOT_FOUND); // Left less then substring
7192 addptr(result, 16);
7193 jmpb(SCAN_TO_SUBSTR);
7194
7195 // Found a potential substr
7196 bind(FOUND_CANDIDATE);
7197 // Matched whole vector if first element matched (tmp(rcx) == 0).
7198 if (int_cnt2 == stride) {
7199 jccb(Assembler::overflow, RET_FOUND); // OF == 1
7200 } else { // int_cnt2 > 8
7201 jccb(Assembler::overflow, FOUND_SUBSTR);
7202 }
7203 // After pcmpestri tmp(rcx) contains matched element index
7204 // Compute start addr of substr
7205 lea(result, Address(result, tmp, scale1));
7206
7207 // Make sure string is still long enough
7208 subl(cnt1, tmp);
7209 cmpl(cnt1, cnt2);
7210 if (int_cnt2 == stride) {
7211 jccb(Assembler::greaterEqual, SCAN_TO_SUBSTR);
7212 } else { // int_cnt2 > 8
7213 jccb(Assembler::greaterEqual, MATCH_SUBSTR_HEAD);
7214 }
7215 // Left less then substring.
7216
7217 bind(RET_NOT_FOUND);
7218 movl(result, -1);
7219 jmp(EXIT);
7220
7221 if (int_cnt2 > stride) {
7222 // This code is optimized for the case when whole substring
7223 // is matched if its head is matched.
7224 bind(MATCH_SUBSTR_HEAD);
7225 pcmpestri(vec, Address(result, 0), mode);
7226 // Reload only string if does not match
7227 jcc(Assembler::noOverflow, RELOAD_STR); // OF == 0
7228
7229 Label CONT_SCAN_SUBSTR;
7230 // Compare the rest of substring (> 8 chars).
7231 bind(FOUND_SUBSTR);
7232 // First 8 chars are already matched.
7233 negptr(cnt2);
7234 addptr(cnt2, stride);
7235
7236 bind(SCAN_SUBSTR);
7237 subl(cnt1, stride);
7238 cmpl(cnt2, -stride); // Do not read beyond substring
7239 jccb(Assembler::lessEqual, CONT_SCAN_SUBSTR);
7240 // Back-up strings to avoid reading beyond substring:
7241 // cnt1 = cnt1 - cnt2 + 8
7242 addl(cnt1, cnt2); // cnt2 is negative
7243 addl(cnt1, stride);
7244 movl(cnt2, stride); negptr(cnt2);
7245 bind(CONT_SCAN_SUBSTR);
7246 if (int_cnt2 < (int)G) {
7247 int tail_off1 = int_cnt2<<scale1;
7248 int tail_off2 = int_cnt2<<scale2;
7249 if (ae == StrIntrinsicNode::UL) {
7250 pmovzxbw(vec, Address(str2, cnt2, scale2, tail_off2));
7251 } else {
7252 movdqu(vec, Address(str2, cnt2, scale2, tail_off2));
7253 }
7254 pcmpestri(vec, Address(result, cnt2, scale1, tail_off1), mode);
7255 } else {
7256 // calculate index in register to avoid integer overflow (int_cnt2*2)
7257 movl(tmp, int_cnt2);
7258 addptr(tmp, cnt2);
7259 if (ae == StrIntrinsicNode::UL) {
7260 pmovzxbw(vec, Address(str2, tmp, scale2, 0));
7261 } else {
7262 movdqu(vec, Address(str2, tmp, scale2, 0));
7263 }
7264 pcmpestri(vec, Address(result, tmp, scale1, 0), mode);
7265 }
7266 // Need to reload strings pointers if not matched whole vector
7267 jcc(Assembler::noOverflow, RELOAD_SUBSTR); // OF == 0
7268 addptr(cnt2, stride);
7269 jcc(Assembler::negative, SCAN_SUBSTR);
7270 // Fall through if found full substring
7271
7272 } // (int_cnt2 > 8)
7273
7274 bind(RET_FOUND);
7275 // Found result if we matched full small substring.
7276 // Compute substr offset
7277 subptr(result, str1);
7278 if (ae == StrIntrinsicNode::UU || ae == StrIntrinsicNode::UL) {
7279 shrl(result, 1); // index
7280 }
7281 bind(EXIT);
7282
7283 } // string_indexofC8
7284
7285 // Small strings are loaded through stack if they cross page boundary.
7286 void MacroAssembler::string_indexof(Register str1, Register str2,
7287 Register cnt1, Register cnt2,
7288 int int_cnt2, Register result,
7289 XMMRegister vec, Register tmp,
7290 int ae) {
7291 ShortBranchVerifier sbv(this);
7292 assert(UseSSE42Intrinsics, "SSE4.2 intrinsics are required");
7293 assert(ae != StrIntrinsicNode::LU, "Invalid encoding");
7294
7295 //
7296 // int_cnt2 is length of small (< 8 chars) constant substring
7297 // or (-1) for non constant substring in which case its length
7298 // is in cnt2 register.
7299 //
7300 // Note, inline_string_indexOf() generates checks:
7301 // if (substr.count > string.count) return -1;
7302 // if (substr.count == 0) return 0;
7303 //
7304 int stride = (ae == StrIntrinsicNode::LL) ? 16 : 8; //UU, UL -> 8
7305 assert(int_cnt2 == -1 || (0 < int_cnt2 && int_cnt2 < stride), "should be != 0");
7306 // This method uses the pcmpestri instruction with bound registers
7307 // inputs:
7308 // xmm - substring
7309 // rax - substring length (elements count)
7310 // mem - scanned string
7311 // rdx - string length (elements count)
7312 // 0xd - mode: 1100 (substring search) + 01 (unsigned shorts)
7313 // 0xc - mode: 1100 (substring search) + 00 (unsigned bytes)
7314 // outputs:
7315 // rcx - matched index in string
7316 assert(cnt1 == rdx && cnt2 == rax && tmp == rcx, "pcmpestri");
7317 int mode = (ae == StrIntrinsicNode::LL) ? 0x0c : 0x0d; // bytes or shorts
7318 Address::ScaleFactor scale1 = (ae == StrIntrinsicNode::LL) ? Address::times_1 : Address::times_2;
7319 Address::ScaleFactor scale2 = (ae == StrIntrinsicNode::UL) ? Address::times_1 : scale1;
7320
7321 Label RELOAD_SUBSTR, SCAN_TO_SUBSTR, SCAN_SUBSTR, ADJUST_STR,
7322 RET_FOUND, RET_NOT_FOUND, CLEANUP, FOUND_SUBSTR,
7323 FOUND_CANDIDATE;
7324
7325 { //========================================================
7326 // We don't know where these strings are located
7327 // and we can't read beyond them. Load them through stack.
7328 Label BIG_STRINGS, CHECK_STR, COPY_SUBSTR, COPY_STR;
7329
7330 movptr(tmp, rsp); // save old SP
7331
7332 if (int_cnt2 > 0) { // small (< 8 chars) constant substring
7333 if (int_cnt2 == (1>>scale2)) { // One byte
7334 assert((ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UL), "Only possible for latin1 encoding");
7335 load_unsigned_byte(result, Address(str2, 0));
7336 movdl(vec, result); // move 32 bits
7337 } else if (ae == StrIntrinsicNode::LL && int_cnt2 == 3) { // Three bytes
7338 // Not enough header space in 32-bit VM: 12+3 = 15.
7339 movl(result, Address(str2, -1));
7340 shrl(result, 8);
7341 movdl(vec, result); // move 32 bits
7342 } else if (ae != StrIntrinsicNode::UL && int_cnt2 == (2>>scale2)) { // One char
7343 load_unsigned_short(result, Address(str2, 0));
7344 movdl(vec, result); // move 32 bits
7345 } else if (ae != StrIntrinsicNode::UL && int_cnt2 == (4>>scale2)) { // Two chars
7346 movdl(vec, Address(str2, 0)); // move 32 bits
7347 } else if (ae != StrIntrinsicNode::UL && int_cnt2 == (8>>scale2)) { // Four chars
7348 movq(vec, Address(str2, 0)); // move 64 bits
7349 } else { // cnt2 = { 3, 5, 6, 7 } || (ae == StrIntrinsicNode::UL && cnt2 ={2, ..., 7})
7350 // Array header size is 12 bytes in 32-bit VM
7351 // + 6 bytes for 3 chars == 18 bytes,
7352 // enough space to load vec and shift.
7353 assert(HeapWordSize*TypeArrayKlass::header_size() >= 12,"sanity");
7354 if (ae == StrIntrinsicNode::UL) {
7355 int tail_off = int_cnt2-8;
7356 pmovzxbw(vec, Address(str2, tail_off));
7357 psrldq(vec, -2*tail_off);
7358 }
7359 else {
7360 int tail_off = int_cnt2*(1<<scale2);
7361 movdqu(vec, Address(str2, tail_off-16));
7362 psrldq(vec, 16-tail_off);
7363 }
7364 }
7365 } else { // not constant substring
7366 cmpl(cnt2, stride);
7367 jccb(Assembler::aboveEqual, BIG_STRINGS); // Both strings are big enough
7368
7369 // We can read beyond string if srt+16 does not cross page boundary
7370 // since heaps are aligned and mapped by pages.
7371 assert(os::vm_page_size() < (int)G, "default page should be small");
7372 movl(result, str2); // We need only low 32 bits
7373 andl(result, (os::vm_page_size()-1));
7374 cmpl(result, (os::vm_page_size()-16));
7375 jccb(Assembler::belowEqual, CHECK_STR);
7376
7377 // Move small strings to stack to allow load 16 bytes into vec.
7378 subptr(rsp, 16);
7379 int stk_offset = wordSize-(1<<scale2);
7380 push(cnt2);
7381
7382 bind(COPY_SUBSTR);
7383 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UL) {
7384 load_unsigned_byte(result, Address(str2, cnt2, scale2, -1));
7385 movb(Address(rsp, cnt2, scale2, stk_offset), result);
7386 } else if (ae == StrIntrinsicNode::UU) {
7387 load_unsigned_short(result, Address(str2, cnt2, scale2, -2));
7388 movw(Address(rsp, cnt2, scale2, stk_offset), result);
7389 }
7390 decrement(cnt2);
7391 jccb(Assembler::notZero, COPY_SUBSTR);
7392
7393 pop(cnt2);
7394 movptr(str2, rsp); // New substring address
7395 } // non constant
7396
7397 bind(CHECK_STR);
7398 cmpl(cnt1, stride);
7399 jccb(Assembler::aboveEqual, BIG_STRINGS);
7400
7401 // Check cross page boundary.
7402 movl(result, str1); // We need only low 32 bits
7403 andl(result, (os::vm_page_size()-1));
7404 cmpl(result, (os::vm_page_size()-16));
7405 jccb(Assembler::belowEqual, BIG_STRINGS);
7406
7407 subptr(rsp, 16);
7408 int stk_offset = -(1<<scale1);
7409 if (int_cnt2 < 0) { // not constant
7410 push(cnt2);
7411 stk_offset += wordSize;
7412 }
7413 movl(cnt2, cnt1);
7414
7415 bind(COPY_STR);
7416 if (ae == StrIntrinsicNode::LL) {
7417 load_unsigned_byte(result, Address(str1, cnt2, scale1, -1));
7418 movb(Address(rsp, cnt2, scale1, stk_offset), result);
7419 } else {
7420 load_unsigned_short(result, Address(str1, cnt2, scale1, -2));
7421 movw(Address(rsp, cnt2, scale1, stk_offset), result);
7422 }
7423 decrement(cnt2);
7424 jccb(Assembler::notZero, COPY_STR);
7425
7426 if (int_cnt2 < 0) { // not constant
7427 pop(cnt2);
7428 }
7429 movptr(str1, rsp); // New string address
7430
7431 bind(BIG_STRINGS);
7432 // Load substring.
7433 if (int_cnt2 < 0) { // -1
7434 if (ae == StrIntrinsicNode::UL) {
7435 pmovzxbw(vec, Address(str2, 0));
7436 } else {
7437 movdqu(vec, Address(str2, 0));
7438 }
7439 push(cnt2); // substr count
7440 push(str2); // substr addr
7441 push(str1); // string addr
7442 } else {
7443 // Small (< 8 chars) constant substrings are loaded already.
7444 movl(cnt2, int_cnt2);
7445 }
7446 push(tmp); // original SP
7447
7448 } // Finished loading
7449
7450 //========================================================
7451 // Start search
7452 //
7453
7454 movptr(result, str1); // string addr
7455
7456 if (int_cnt2 < 0) { // Only for non constant substring
7457 jmpb(SCAN_TO_SUBSTR);
7458
7459 // SP saved at sp+0
7460 // String saved at sp+1*wordSize
7461 // Substr saved at sp+2*wordSize
7462 // Substr count saved at sp+3*wordSize
7463
7464 // Reload substr for rescan, this code
7465 // is executed only for large substrings (> 8 chars)
7466 bind(RELOAD_SUBSTR);
7467 movptr(str2, Address(rsp, 2*wordSize));
7468 movl(cnt2, Address(rsp, 3*wordSize));
7469 if (ae == StrIntrinsicNode::UL) {
7470 pmovzxbw(vec, Address(str2, 0));
7471 } else {
7472 movdqu(vec, Address(str2, 0));
7473 }
7474 // We came here after the beginning of the substring was
7475 // matched but the rest of it was not so we need to search
7476 // again. Start from the next element after the previous match.
7477 subptr(str1, result); // Restore counter
7478 if (ae == StrIntrinsicNode::UU || ae == StrIntrinsicNode::UL) {
7479 shrl(str1, 1);
7480 }
7481 addl(cnt1, str1);
7482 decrementl(cnt1); // Shift to next element
7483 cmpl(cnt1, cnt2);
7484 jcc(Assembler::negative, RET_NOT_FOUND); // Left less then substring
7485
7486 addptr(result, (1<<scale1));
7487 } // non constant
7488
7489 // Scan string for start of substr in 16-byte vectors
7490 bind(SCAN_TO_SUBSTR);
7491 assert(cnt1 == rdx && cnt2 == rax && tmp == rcx, "pcmpestri");
7492 pcmpestri(vec, Address(result, 0), mode);
7493 jccb(Assembler::below, FOUND_CANDIDATE); // CF == 1
7494 subl(cnt1, stride);
7495 jccb(Assembler::lessEqual, RET_NOT_FOUND); // Scanned full string
7496 cmpl(cnt1, cnt2);
7497 jccb(Assembler::negative, RET_NOT_FOUND); // Left less then substring
7498 addptr(result, 16);
7499
7500 bind(ADJUST_STR);
7501 cmpl(cnt1, stride); // Do not read beyond string
7502 jccb(Assembler::greaterEqual, SCAN_TO_SUBSTR);
7503 // Back-up string to avoid reading beyond string.
7504 lea(result, Address(result, cnt1, scale1, -16));
7505 movl(cnt1, stride);
7506 jmpb(SCAN_TO_SUBSTR);
7507
7508 // Found a potential substr
7509 bind(FOUND_CANDIDATE);
7510 // After pcmpestri tmp(rcx) contains matched element index
7511
7512 // Make sure string is still long enough
7513 subl(cnt1, tmp);
7514 cmpl(cnt1, cnt2);
7515 jccb(Assembler::greaterEqual, FOUND_SUBSTR);
7516 // Left less then substring.
7517
7518 bind(RET_NOT_FOUND);
7519 movl(result, -1);
7520 jmpb(CLEANUP);
7521
7522 bind(FOUND_SUBSTR);
7523 // Compute start addr of substr
7524 lea(result, Address(result, tmp, scale1));
7525 if (int_cnt2 > 0) { // Constant substring
7526 // Repeat search for small substring (< 8 chars)
7527 // from new point without reloading substring.
7528 // Have to check that we don't read beyond string.
7529 cmpl(tmp, stride-int_cnt2);
7530 jccb(Assembler::greater, ADJUST_STR);
7531 // Fall through if matched whole substring.
7532 } else { // non constant
7533 assert(int_cnt2 == -1, "should be != 0");
7534
7535 addl(tmp, cnt2);
7536 // Found result if we matched whole substring.
7537 cmpl(tmp, stride);
7538 jccb(Assembler::lessEqual, RET_FOUND);
7539
7540 // Repeat search for small substring (<= 8 chars)
7541 // from new point 'str1' without reloading substring.
7542 cmpl(cnt2, stride);
7543 // Have to check that we don't read beyond string.
7544 jccb(Assembler::lessEqual, ADJUST_STR);
7545
7546 Label CHECK_NEXT, CONT_SCAN_SUBSTR, RET_FOUND_LONG;
7547 // Compare the rest of substring (> 8 chars).
7548 movptr(str1, result);
7549
7550 cmpl(tmp, cnt2);
7551 // First 8 chars are already matched.
7552 jccb(Assembler::equal, CHECK_NEXT);
7553
7554 bind(SCAN_SUBSTR);
7555 pcmpestri(vec, Address(str1, 0), mode);
7556 // Need to reload strings pointers if not matched whole vector
7557 jcc(Assembler::noOverflow, RELOAD_SUBSTR); // OF == 0
7558
7559 bind(CHECK_NEXT);
7560 subl(cnt2, stride);
7561 jccb(Assembler::lessEqual, RET_FOUND_LONG); // Found full substring
7562 addptr(str1, 16);
7563 if (ae == StrIntrinsicNode::UL) {
7564 addptr(str2, 8);
7565 } else {
7566 addptr(str2, 16);
7567 }
7568 subl(cnt1, stride);
7569 cmpl(cnt2, stride); // Do not read beyond substring
7570 jccb(Assembler::greaterEqual, CONT_SCAN_SUBSTR);
7571 // Back-up strings to avoid reading beyond substring.
7572
7573 if (ae == StrIntrinsicNode::UL) {
7574 lea(str2, Address(str2, cnt2, scale2, -8));
7575 lea(str1, Address(str1, cnt2, scale1, -16));
7576 } else {
7577 lea(str2, Address(str2, cnt2, scale2, -16));
7578 lea(str1, Address(str1, cnt2, scale1, -16));
7579 }
7580 subl(cnt1, cnt2);
7581 movl(cnt2, stride);
7582 addl(cnt1, stride);
7583 bind(CONT_SCAN_SUBSTR);
7584 if (ae == StrIntrinsicNode::UL) {
7585 pmovzxbw(vec, Address(str2, 0));
7586 } else {
7587 movdqu(vec, Address(str2, 0));
7588 }
7589 jmp(SCAN_SUBSTR);
7590
7591 bind(RET_FOUND_LONG);
7592 movptr(str1, Address(rsp, wordSize));
7593 } // non constant
7594
7595 bind(RET_FOUND);
7596 // Compute substr offset
7597 subptr(result, str1);
7598 if (ae == StrIntrinsicNode::UU || ae == StrIntrinsicNode::UL) {
7599 shrl(result, 1); // index
7600 }
7601 bind(CLEANUP);
7602 pop(rsp); // restore SP
7603
7604 } // string_indexof
7605
7606 void MacroAssembler::string_indexof_char(Register str1, Register cnt1, Register ch, Register result,
7607 XMMRegister vec1, XMMRegister vec2, XMMRegister vec3, Register tmp) {
7608 ShortBranchVerifier sbv(this);
7609 assert(UseSSE42Intrinsics, "SSE4.2 intrinsics are required");
7610
7611 int stride = 8;
7612
7613 Label FOUND_CHAR, SCAN_TO_CHAR, SCAN_TO_CHAR_LOOP,
7614 SCAN_TO_8_CHAR, SCAN_TO_8_CHAR_LOOP, SCAN_TO_16_CHAR_LOOP,
7615 RET_NOT_FOUND, SCAN_TO_8_CHAR_INIT,
7616 FOUND_SEQ_CHAR, DONE_LABEL;
7617
7618 movptr(result, str1);
7619 if (UseAVX >= 2) {
7620 cmpl(cnt1, stride);
7621 jcc(Assembler::less, SCAN_TO_CHAR_LOOP);
7622 cmpl(cnt1, 2*stride);
7623 jcc(Assembler::less, SCAN_TO_8_CHAR_INIT);
7624 movdl(vec1, ch);
7625 vpbroadcastw(vec1, vec1);
7626 vpxor(vec2, vec2);
7627 movl(tmp, cnt1);
7628 andl(tmp, 0xFFFFFFF0); //vector count (in chars)
7629 andl(cnt1,0x0000000F); //tail count (in chars)
7630
7631 bind(SCAN_TO_16_CHAR_LOOP);
7632 vmovdqu(vec3, Address(result, 0));
7633 vpcmpeqw(vec3, vec3, vec1, 1);
7634 vptest(vec2, vec3);
7635 jcc(Assembler::carryClear, FOUND_CHAR);
7636 addptr(result, 32);
7637 subl(tmp, 2*stride);
7638 jccb(Assembler::notZero, SCAN_TO_16_CHAR_LOOP);
7639 jmp(SCAN_TO_8_CHAR);
7640 bind(SCAN_TO_8_CHAR_INIT);
7641 movdl(vec1, ch);
7642 pshuflw(vec1, vec1, 0x00);
7643 pshufd(vec1, vec1, 0);
7644 pxor(vec2, vec2);
7645 }
7646 bind(SCAN_TO_8_CHAR);
7647 cmpl(cnt1, stride);
7648 if (UseAVX >= 2) {
7649 jcc(Assembler::less, SCAN_TO_CHAR);
7650 } else {
7651 jcc(Assembler::less, SCAN_TO_CHAR_LOOP);
7652 movdl(vec1, ch);
7653 pshuflw(vec1, vec1, 0x00);
7654 pshufd(vec1, vec1, 0);
7655 pxor(vec2, vec2);
7656 }
7657 movl(tmp, cnt1);
7658 andl(tmp, 0xFFFFFFF8); //vector count (in chars)
7659 andl(cnt1,0x00000007); //tail count (in chars)
7660
7661 bind(SCAN_TO_8_CHAR_LOOP);
7662 movdqu(vec3, Address(result, 0));
7663 pcmpeqw(vec3, vec1);
7664 ptest(vec2, vec3);
7665 jcc(Assembler::carryClear, FOUND_CHAR);
7666 addptr(result, 16);
7667 subl(tmp, stride);
7668 jccb(Assembler::notZero, SCAN_TO_8_CHAR_LOOP);
7669 bind(SCAN_TO_CHAR);
7670 testl(cnt1, cnt1);
7671 jcc(Assembler::zero, RET_NOT_FOUND);
7672 bind(SCAN_TO_CHAR_LOOP);
7673 load_unsigned_short(tmp, Address(result, 0));
7674 cmpl(ch, tmp);
7675 jccb(Assembler::equal, FOUND_SEQ_CHAR);
7676 addptr(result, 2);
7677 subl(cnt1, 1);
7678 jccb(Assembler::zero, RET_NOT_FOUND);
7679 jmp(SCAN_TO_CHAR_LOOP);
7680
7681 bind(RET_NOT_FOUND);
7682 movl(result, -1);
7683 jmpb(DONE_LABEL);
7684
7685 bind(FOUND_CHAR);
7686 if (UseAVX >= 2) {
7687 vpmovmskb(tmp, vec3);
7688 } else {
7689 pmovmskb(tmp, vec3);
7690 }
7691 bsfl(ch, tmp);
7692 addl(result, ch);
7693
7694 bind(FOUND_SEQ_CHAR);
7695 subptr(result, str1);
7696 shrl(result, 1);
7697
7698 bind(DONE_LABEL);
7699 } // string_indexof_char
7700
7701 // helper function for string_compare
7702 void MacroAssembler::load_next_elements(Register elem1, Register elem2, Register str1, Register str2,
7703 Address::ScaleFactor scale, Address::ScaleFactor scale1,
7704 Address::ScaleFactor scale2, Register index, int ae) {
7705 if (ae == StrIntrinsicNode::LL) {
7706 load_unsigned_byte(elem1, Address(str1, index, scale, 0));
7707 load_unsigned_byte(elem2, Address(str2, index, scale, 0));
7708 } else if (ae == StrIntrinsicNode::UU) {
7709 load_unsigned_short(elem1, Address(str1, index, scale, 0));
7710 load_unsigned_short(elem2, Address(str2, index, scale, 0));
7711 } else {
7712 load_unsigned_byte(elem1, Address(str1, index, scale1, 0));
7713 load_unsigned_short(elem2, Address(str2, index, scale2, 0));
7714 }
7715 }
7716
7717 // Compare strings, used for char[] and byte[].
7718 void MacroAssembler::string_compare(Register str1, Register str2,
7719 Register cnt1, Register cnt2, Register result,
7720 XMMRegister vec1, int ae) {
7721 ShortBranchVerifier sbv(this);
7722 Label LENGTH_DIFF_LABEL, POP_LABEL, DONE_LABEL, WHILE_HEAD_LABEL;
7723 Label COMPARE_WIDE_VECTORS_LOOP_FAILED; // used only _LP64 && AVX3
7724 int stride, stride2, adr_stride, adr_stride1, adr_stride2;
7725 int stride2x2 = 0x40;
7726 Address::ScaleFactor scale = Address::no_scale;
7727 Address::ScaleFactor scale1 = Address::no_scale;
7728 Address::ScaleFactor scale2 = Address::no_scale;
7729
7730 if (ae != StrIntrinsicNode::LL) {
7731 stride2x2 = 0x20;
7732 }
7733
7734 if (ae == StrIntrinsicNode::LU || ae == StrIntrinsicNode::UL) {
7735 shrl(cnt2, 1);
7736 }
7737 // Compute the minimum of the string lengths and the
7738 // difference of the string lengths (stack).
7739 // Do the conditional move stuff
7740 movl(result, cnt1);
7741 subl(cnt1, cnt2);
7742 push(cnt1);
7743 cmov32(Assembler::lessEqual, cnt2, result); // cnt2 = min(cnt1, cnt2)
7744
7745 // Is the minimum length zero?
7746 testl(cnt2, cnt2);
7747 jcc(Assembler::zero, LENGTH_DIFF_LABEL);
7748 if (ae == StrIntrinsicNode::LL) {
7749 // Load first bytes
7750 load_unsigned_byte(result, Address(str1, 0)); // result = str1[0]
7751 load_unsigned_byte(cnt1, Address(str2, 0)); // cnt1 = str2[0]
7752 } else if (ae == StrIntrinsicNode::UU) {
7753 // Load first characters
7754 load_unsigned_short(result, Address(str1, 0));
7755 load_unsigned_short(cnt1, Address(str2, 0));
7756 } else {
7757 load_unsigned_byte(result, Address(str1, 0));
7758 load_unsigned_short(cnt1, Address(str2, 0));
7759 }
7760 subl(result, cnt1);
7761 jcc(Assembler::notZero, POP_LABEL);
7762
7763 if (ae == StrIntrinsicNode::UU) {
7764 // Divide length by 2 to get number of chars
7765 shrl(cnt2, 1);
7766 }
7767 cmpl(cnt2, 1);
7768 jcc(Assembler::equal, LENGTH_DIFF_LABEL);
7769
7770 // Check if the strings start at the same location and setup scale and stride
7771 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
7772 cmpptr(str1, str2);
7773 jcc(Assembler::equal, LENGTH_DIFF_LABEL);
7774 if (ae == StrIntrinsicNode::LL) {
7775 scale = Address::times_1;
7776 stride = 16;
7777 } else {
7778 scale = Address::times_2;
7779 stride = 8;
7780 }
7781 } else {
7782 scale1 = Address::times_1;
7783 scale2 = Address::times_2;
7784 // scale not used
7785 stride = 8;
7786 }
7787
7788 if (UseAVX >= 2 && UseSSE42Intrinsics) {
7789 Label COMPARE_WIDE_VECTORS, VECTOR_NOT_EQUAL, COMPARE_WIDE_TAIL, COMPARE_SMALL_STR;
7790 Label COMPARE_WIDE_VECTORS_LOOP, COMPARE_16_CHARS, COMPARE_INDEX_CHAR;
7791 Label COMPARE_WIDE_VECTORS_LOOP_AVX2;
7792 Label COMPARE_TAIL_LONG;
7793 Label COMPARE_WIDE_VECTORS_LOOP_AVX3; // used only _LP64 && AVX3
7794
7795 int pcmpmask = 0x19;
7796 if (ae == StrIntrinsicNode::LL) {
7797 pcmpmask &= ~0x01;
7798 }
7799
7800 // Setup to compare 16-chars (32-bytes) vectors,
7801 // start from first character again because it has aligned address.
7802 if (ae == StrIntrinsicNode::LL) {
7803 stride2 = 32;
7804 } else {
7805 stride2 = 16;
7806 }
7807 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
7808 adr_stride = stride << scale;
7809 } else {
7810 adr_stride1 = 8; //stride << scale1;
7811 adr_stride2 = 16; //stride << scale2;
7812 }
7813
7814 assert(result == rax && cnt2 == rdx && cnt1 == rcx, "pcmpestri");
7815 // rax and rdx are used by pcmpestri as elements counters
7816 movl(result, cnt2);
7817 andl(cnt2, ~(stride2-1)); // cnt2 holds the vector count
7818 jcc(Assembler::zero, COMPARE_TAIL_LONG);
7819
7820 // fast path : compare first 2 8-char vectors.
7821 bind(COMPARE_16_CHARS);
7822 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
7823 movdqu(vec1, Address(str1, 0));
7824 } else {
7825 pmovzxbw(vec1, Address(str1, 0));
7826 }
7827 pcmpestri(vec1, Address(str2, 0), pcmpmask);
7828 jccb(Assembler::below, COMPARE_INDEX_CHAR);
7829
7830 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
7831 movdqu(vec1, Address(str1, adr_stride));
7832 pcmpestri(vec1, Address(str2, adr_stride), pcmpmask);
7833 } else {
7834 pmovzxbw(vec1, Address(str1, adr_stride1));
7835 pcmpestri(vec1, Address(str2, adr_stride2), pcmpmask);
7836 }
7837 jccb(Assembler::aboveEqual, COMPARE_WIDE_VECTORS);
7838 addl(cnt1, stride);
7839
7840 // Compare the characters at index in cnt1
7841 bind(COMPARE_INDEX_CHAR); // cnt1 has the offset of the mismatching character
7842 load_next_elements(result, cnt2, str1, str2, scale, scale1, scale2, cnt1, ae);
7843 subl(result, cnt2);
7844 jmp(POP_LABEL);
7845
7846 // Setup the registers to start vector comparison loop
7847 bind(COMPARE_WIDE_VECTORS);
7848 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
7849 lea(str1, Address(str1, result, scale));
7850 lea(str2, Address(str2, result, scale));
7851 } else {
7852 lea(str1, Address(str1, result, scale1));
7853 lea(str2, Address(str2, result, scale2));
7854 }
7855 subl(result, stride2);
7856 subl(cnt2, stride2);
7857 jcc(Assembler::zero, COMPARE_WIDE_TAIL);
7858 negptr(result);
7859
7860 // In a loop, compare 16-chars (32-bytes) at once using (vpxor+vptest)
7861 bind(COMPARE_WIDE_VECTORS_LOOP);
7862
7863 #ifdef _LP64
7864 if (VM_Version::supports_avx512vlbw()) { // trying 64 bytes fast loop
7865 cmpl(cnt2, stride2x2);
7866 jccb(Assembler::below, COMPARE_WIDE_VECTORS_LOOP_AVX2);
7867 testl(cnt2, stride2x2-1); // cnt2 holds the vector count
7868 jccb(Assembler::notZero, COMPARE_WIDE_VECTORS_LOOP_AVX2); // means we cannot subtract by 0x40
7869
7870 bind(COMPARE_WIDE_VECTORS_LOOP_AVX3); // the hottest loop
7871 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
7872 evmovdquq(vec1, Address(str1, result, scale), Assembler::AVX_512bit);
7873 evpcmpeqb(k7, vec1, Address(str2, result, scale), Assembler::AVX_512bit); // k7 == 11..11, if operands equal, otherwise k7 has some 0
7874 } else {
7875 vpmovzxbw(vec1, Address(str1, result, scale1), Assembler::AVX_512bit);
7876 evpcmpeqb(k7, vec1, Address(str2, result, scale2), Assembler::AVX_512bit); // k7 == 11..11, if operands equal, otherwise k7 has some 0
7877 }
7878 kortestql(k7, k7);
7879 jcc(Assembler::aboveEqual, COMPARE_WIDE_VECTORS_LOOP_FAILED); // miscompare
7880 addptr(result, stride2x2); // update since we already compared at this addr
7881 subl(cnt2, stride2x2); // and sub the size too
7882 jccb(Assembler::notZero, COMPARE_WIDE_VECTORS_LOOP_AVX3);
7883
7884 vpxor(vec1, vec1);
7885 jmpb(COMPARE_WIDE_TAIL);
7886 }//if (VM_Version::supports_avx512vlbw())
7887 #endif // _LP64
7888
7889
7890 bind(COMPARE_WIDE_VECTORS_LOOP_AVX2);
7891 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
7892 vmovdqu(vec1, Address(str1, result, scale));
7893 vpxor(vec1, Address(str2, result, scale));
7894 } else {
7895 vpmovzxbw(vec1, Address(str1, result, scale1), Assembler::AVX_256bit);
7896 vpxor(vec1, Address(str2, result, scale2));
7897 }
7898 vptest(vec1, vec1);
7899 jcc(Assembler::notZero, VECTOR_NOT_EQUAL);
7900 addptr(result, stride2);
7901 subl(cnt2, stride2);
7902 jcc(Assembler::notZero, COMPARE_WIDE_VECTORS_LOOP);
7903 // clean upper bits of YMM registers
7904 vpxor(vec1, vec1);
7905
7906 // compare wide vectors tail
7907 bind(COMPARE_WIDE_TAIL);
7908 testptr(result, result);
7909 jcc(Assembler::zero, LENGTH_DIFF_LABEL);
7910
7911 movl(result, stride2);
7912 movl(cnt2, result);
7913 negptr(result);
7914 jmp(COMPARE_WIDE_VECTORS_LOOP_AVX2);
7915
7916 // Identifies the mismatching (higher or lower)16-bytes in the 32-byte vectors.
7917 bind(VECTOR_NOT_EQUAL);
7918 // clean upper bits of YMM registers
7919 vpxor(vec1, vec1);
7920 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
7921 lea(str1, Address(str1, result, scale));
7922 lea(str2, Address(str2, result, scale));
7923 } else {
7924 lea(str1, Address(str1, result, scale1));
7925 lea(str2, Address(str2, result, scale2));
7926 }
7927 jmp(COMPARE_16_CHARS);
7928
7929 // Compare tail chars, length between 1 to 15 chars
7930 bind(COMPARE_TAIL_LONG);
7931 movl(cnt2, result);
7932 cmpl(cnt2, stride);
7933 jcc(Assembler::less, COMPARE_SMALL_STR);
7934
7935 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
7936 movdqu(vec1, Address(str1, 0));
7937 } else {
7938 pmovzxbw(vec1, Address(str1, 0));
7939 }
7940 pcmpestri(vec1, Address(str2, 0), pcmpmask);
7941 jcc(Assembler::below, COMPARE_INDEX_CHAR);
7942 subptr(cnt2, stride);
7943 jcc(Assembler::zero, LENGTH_DIFF_LABEL);
7944 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
7945 lea(str1, Address(str1, result, scale));
7946 lea(str2, Address(str2, result, scale));
7947 } else {
7948 lea(str1, Address(str1, result, scale1));
7949 lea(str2, Address(str2, result, scale2));
7950 }
7951 negptr(cnt2);
7952 jmpb(WHILE_HEAD_LABEL);
7953
7954 bind(COMPARE_SMALL_STR);
7955 } else if (UseSSE42Intrinsics) {
7956 Label COMPARE_WIDE_VECTORS, VECTOR_NOT_EQUAL, COMPARE_TAIL;
7957 int pcmpmask = 0x19;
7958 // Setup to compare 8-char (16-byte) vectors,
7959 // start from first character again because it has aligned address.
7960 movl(result, cnt2);
7961 andl(cnt2, ~(stride - 1)); // cnt2 holds the vector count
7962 if (ae == StrIntrinsicNode::LL) {
7963 pcmpmask &= ~0x01;
7964 }
7965 jcc(Assembler::zero, COMPARE_TAIL);
7966 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
7967 lea(str1, Address(str1, result, scale));
7968 lea(str2, Address(str2, result, scale));
7969 } else {
7970 lea(str1, Address(str1, result, scale1));
7971 lea(str2, Address(str2, result, scale2));
7972 }
7973 negptr(result);
7974
7975 // pcmpestri
7976 // inputs:
7977 // vec1- substring
7978 // rax - negative string length (elements count)
7979 // mem - scanned string
7980 // rdx - string length (elements count)
7981 // pcmpmask - cmp mode: 11000 (string compare with negated result)
7982 // + 00 (unsigned bytes) or + 01 (unsigned shorts)
7983 // outputs:
7984 // rcx - first mismatched element index
7985 assert(result == rax && cnt2 == rdx && cnt1 == rcx, "pcmpestri");
7986
7987 bind(COMPARE_WIDE_VECTORS);
7988 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
7989 movdqu(vec1, Address(str1, result, scale));
7990 pcmpestri(vec1, Address(str2, result, scale), pcmpmask);
7991 } else {
7992 pmovzxbw(vec1, Address(str1, result, scale1));
7993 pcmpestri(vec1, Address(str2, result, scale2), pcmpmask);
7994 }
7995 // After pcmpestri cnt1(rcx) contains mismatched element index
7996
7997 jccb(Assembler::below, VECTOR_NOT_EQUAL); // CF==1
7998 addptr(result, stride);
7999 subptr(cnt2, stride);
8000 jccb(Assembler::notZero, COMPARE_WIDE_VECTORS);
8001
8002 // compare wide vectors tail
8003 testptr(result, result);
8004 jcc(Assembler::zero, LENGTH_DIFF_LABEL);
8005
8006 movl(cnt2, stride);
8007 movl(result, stride);
8008 negptr(result);
8009 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
8010 movdqu(vec1, Address(str1, result, scale));
8011 pcmpestri(vec1, Address(str2, result, scale), pcmpmask);
8012 } else {
8013 pmovzxbw(vec1, Address(str1, result, scale1));
8014 pcmpestri(vec1, Address(str2, result, scale2), pcmpmask);
8015 }
8016 jccb(Assembler::aboveEqual, LENGTH_DIFF_LABEL);
8017
8018 // Mismatched characters in the vectors
8019 bind(VECTOR_NOT_EQUAL);
8020 addptr(cnt1, result);
8021 load_next_elements(result, cnt2, str1, str2, scale, scale1, scale2, cnt1, ae);
8022 subl(result, cnt2);
8023 jmpb(POP_LABEL);
8024
8025 bind(COMPARE_TAIL); // limit is zero
8026 movl(cnt2, result);
8027 // Fallthru to tail compare
8028 }
8029 // Shift str2 and str1 to the end of the arrays, negate min
8030 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
8031 lea(str1, Address(str1, cnt2, scale));
8032 lea(str2, Address(str2, cnt2, scale));
8033 } else {
8034 lea(str1, Address(str1, cnt2, scale1));
8035 lea(str2, Address(str2, cnt2, scale2));
8036 }
8037 decrementl(cnt2); // first character was compared already
8038 negptr(cnt2);
8039
8040 // Compare the rest of the elements
8041 bind(WHILE_HEAD_LABEL);
8042 load_next_elements(result, cnt1, str1, str2, scale, scale1, scale2, cnt2, ae);
8043 subl(result, cnt1);
8044 jccb(Assembler::notZero, POP_LABEL);
8045 increment(cnt2);
8046 jccb(Assembler::notZero, WHILE_HEAD_LABEL);
8047
8048 // Strings are equal up to min length. Return the length difference.
8049 bind(LENGTH_DIFF_LABEL);
8050 pop(result);
8051 if (ae == StrIntrinsicNode::UU) {
8052 // Divide diff by 2 to get number of chars
8053 sarl(result, 1);
8054 }
8055 jmpb(DONE_LABEL);
8056
8057 #ifdef _LP64
8058 if (VM_Version::supports_avx512vlbw()) {
8059
8060 bind(COMPARE_WIDE_VECTORS_LOOP_FAILED);
8061
8062 kmovql(cnt1, k7);
8063 notq(cnt1);
8064 bsfq(cnt2, cnt1);
8065 if (ae != StrIntrinsicNode::LL) {
8066 // Divide diff by 2 to get number of chars
8067 sarl(cnt2, 1);
8068 }
8069 addq(result, cnt2);
8070 if (ae == StrIntrinsicNode::LL) {
8071 load_unsigned_byte(cnt1, Address(str2, result));
8072 load_unsigned_byte(result, Address(str1, result));
8073 } else if (ae == StrIntrinsicNode::UU) {
8074 load_unsigned_short(cnt1, Address(str2, result, scale));
8075 load_unsigned_short(result, Address(str1, result, scale));
8076 } else {
8077 load_unsigned_short(cnt1, Address(str2, result, scale2));
8078 load_unsigned_byte(result, Address(str1, result, scale1));
8079 }
8080 subl(result, cnt1);
8081 jmpb(POP_LABEL);
8082 }//if (VM_Version::supports_avx512vlbw())
8083 #endif // _LP64
8084
8085 // Discard the stored length difference
8086 bind(POP_LABEL);
8087 pop(cnt1);
8088
8089 // That's it
8090 bind(DONE_LABEL);
8091 if(ae == StrIntrinsicNode::UL) {
8092 negl(result);
8093 }
8094
8095 }
8096
8097 // Search for Non-ASCII character (Negative byte value) in a byte array,
8098 // return true if it has any and false otherwise.
8099 // ..\jdk\src\java.base\share\classes\java\lang\StringCoding.java
8100 // @HotSpotIntrinsicCandidate
8101 // private static boolean hasNegatives(byte[] ba, int off, int len) {
8102 // for (int i = off; i < off + len; i++) {
8103 // if (ba[i] < 0) {
8104 // return true;
8105 // }
8106 // }
8107 // return false;
8108 // }
8109 void MacroAssembler::has_negatives(Register ary1, Register len,
8110 Register result, Register tmp1,
8111 XMMRegister vec1, XMMRegister vec2) {
8112 // rsi: byte array
8113 // rcx: len
8114 // rax: result
8115 ShortBranchVerifier sbv(this);
8116 assert_different_registers(ary1, len, result, tmp1);
8117 assert_different_registers(vec1, vec2);
8118 Label TRUE_LABEL, FALSE_LABEL, DONE, COMPARE_CHAR, COMPARE_VECTORS, COMPARE_BYTE;
8119
8120 // len == 0
8121 testl(len, len);
8122 jcc(Assembler::zero, FALSE_LABEL);
8123
8124 if ((UseAVX > 2) && // AVX512
8125 VM_Version::supports_avx512vlbw() &&
8126 VM_Version::supports_bmi2()) {
8127
8128 set_vector_masking(); // opening of the stub context for programming mask registers
8129
8130 Label test_64_loop, test_tail;
8131 Register tmp3_aliased = len;
8132
8133 movl(tmp1, len);
8134 vpxor(vec2, vec2, vec2, Assembler::AVX_512bit);
8135
8136 andl(tmp1, 64 - 1); // tail count (in chars) 0x3F
8137 andl(len, ~(64 - 1)); // vector count (in chars)
8138 jccb(Assembler::zero, test_tail);
8139
8140 lea(ary1, Address(ary1, len, Address::times_1));
8141 negptr(len);
8142
8143 bind(test_64_loop);
8144 // Check whether our 64 elements of size byte contain negatives
8145 evpcmpgtb(k2, vec2, Address(ary1, len, Address::times_1), Assembler::AVX_512bit);
8146 kortestql(k2, k2);
8147 jcc(Assembler::notZero, TRUE_LABEL);
8148
8149 addptr(len, 64);
8150 jccb(Assembler::notZero, test_64_loop);
8151
8152
8153 bind(test_tail);
8154 // bail out when there is nothing to be done
8155 testl(tmp1, -1);
8156 jcc(Assembler::zero, FALSE_LABEL);
8157
8158 // Save k1
8159 kmovql(k3, k1);
8160
8161 // ~(~0 << len) applied up to two times (for 32-bit scenario)
8162 #ifdef _LP64
8163 mov64(tmp3_aliased, 0xFFFFFFFFFFFFFFFF);
8164 shlxq(tmp3_aliased, tmp3_aliased, tmp1);
8165 notq(tmp3_aliased);
8166 kmovql(k1, tmp3_aliased);
8167 #else
8168 Label k_init;
8169 jmp(k_init);
8170
8171 // We could not read 64-bits from a general purpose register thus we move
8172 // data required to compose 64 1's to the instruction stream
8173 // We emit 64 byte wide series of elements from 0..63 which later on would
8174 // be used as a compare targets with tail count contained in tmp1 register.
8175 // Result would be a k1 register having tmp1 consecutive number or 1
8176 // counting from least significant bit.
8177 address tmp = pc();
8178 emit_int64(0x0706050403020100);
8179 emit_int64(0x0F0E0D0C0B0A0908);
8180 emit_int64(0x1716151413121110);
8181 emit_int64(0x1F1E1D1C1B1A1918);
8182 emit_int64(0x2726252423222120);
8183 emit_int64(0x2F2E2D2C2B2A2928);
8184 emit_int64(0x3736353433323130);
8185 emit_int64(0x3F3E3D3C3B3A3938);
8186
8187 bind(k_init);
8188 lea(len, InternalAddress(tmp));
8189 // create mask to test for negative byte inside a vector
8190 evpbroadcastb(vec1, tmp1, Assembler::AVX_512bit);
8191 evpcmpgtb(k1, vec1, Address(len, 0), Assembler::AVX_512bit);
8192
8193 #endif
8194 evpcmpgtb(k2, k1, vec2, Address(ary1, 0), Assembler::AVX_512bit);
8195 ktestq(k2, k1);
8196 // Restore k1
8197 kmovql(k1, k3);
8198 jcc(Assembler::notZero, TRUE_LABEL);
8199
8200 jmp(FALSE_LABEL);
8201
8202 clear_vector_masking(); // closing of the stub context for programming mask registers
8203 } else {
8204 movl(result, len); // copy
8205
8206 if (UseAVX == 2 && UseSSE >= 2) {
8207 // With AVX2, use 32-byte vector compare
8208 Label COMPARE_WIDE_VECTORS, COMPARE_TAIL;
8209
8210 // Compare 32-byte vectors
8211 andl(result, 0x0000001f); // tail count (in bytes)
8212 andl(len, 0xffffffe0); // vector count (in bytes)
8213 jccb(Assembler::zero, COMPARE_TAIL);
8214
8215 lea(ary1, Address(ary1, len, Address::times_1));
8216 negptr(len);
8217
8218 movl(tmp1, 0x80808080); // create mask to test for Unicode chars in vector
8219 movdl(vec2, tmp1);
8220 vpbroadcastd(vec2, vec2);
8221
8222 bind(COMPARE_WIDE_VECTORS);
8223 vmovdqu(vec1, Address(ary1, len, Address::times_1));
8224 vptest(vec1, vec2);
8225 jccb(Assembler::notZero, TRUE_LABEL);
8226 addptr(len, 32);
8227 jcc(Assembler::notZero, COMPARE_WIDE_VECTORS);
8228
8229 testl(result, result);
8230 jccb(Assembler::zero, FALSE_LABEL);
8231
8232 vmovdqu(vec1, Address(ary1, result, Address::times_1, -32));
8233 vptest(vec1, vec2);
8234 jccb(Assembler::notZero, TRUE_LABEL);
8235 jmpb(FALSE_LABEL);
8236
8237 bind(COMPARE_TAIL); // len is zero
8238 movl(len, result);
8239 // Fallthru to tail compare
8240 } else if (UseSSE42Intrinsics) {
8241 // With SSE4.2, use double quad vector compare
8242 Label COMPARE_WIDE_VECTORS, COMPARE_TAIL;
8243
8244 // Compare 16-byte vectors
8245 andl(result, 0x0000000f); // tail count (in bytes)
8246 andl(len, 0xfffffff0); // vector count (in bytes)
8247 jccb(Assembler::zero, COMPARE_TAIL);
8248
8249 lea(ary1, Address(ary1, len, Address::times_1));
8250 negptr(len);
8251
8252 movl(tmp1, 0x80808080);
8253 movdl(vec2, tmp1);
8254 pshufd(vec2, vec2, 0);
8255
8256 bind(COMPARE_WIDE_VECTORS);
8257 movdqu(vec1, Address(ary1, len, Address::times_1));
8258 ptest(vec1, vec2);
8259 jccb(Assembler::notZero, TRUE_LABEL);
8260 addptr(len, 16);
8261 jcc(Assembler::notZero, COMPARE_WIDE_VECTORS);
8262
8263 testl(result, result);
8264 jccb(Assembler::zero, FALSE_LABEL);
8265
8266 movdqu(vec1, Address(ary1, result, Address::times_1, -16));
8267 ptest(vec1, vec2);
8268 jccb(Assembler::notZero, TRUE_LABEL);
8269 jmpb(FALSE_LABEL);
8270
8271 bind(COMPARE_TAIL); // len is zero
8272 movl(len, result);
8273 // Fallthru to tail compare
8274 }
8275 }
8276 // Compare 4-byte vectors
8277 andl(len, 0xfffffffc); // vector count (in bytes)
8278 jccb(Assembler::zero, COMPARE_CHAR);
8279
8280 lea(ary1, Address(ary1, len, Address::times_1));
8281 negptr(len);
8282
8283 bind(COMPARE_VECTORS);
8284 movl(tmp1, Address(ary1, len, Address::times_1));
8285 andl(tmp1, 0x80808080);
8286 jccb(Assembler::notZero, TRUE_LABEL);
8287 addptr(len, 4);
8288 jcc(Assembler::notZero, COMPARE_VECTORS);
8289
8290 // Compare trailing char (final 2 bytes), if any
8291 bind(COMPARE_CHAR);
8292 testl(result, 0x2); // tail char
8293 jccb(Assembler::zero, COMPARE_BYTE);
8294 load_unsigned_short(tmp1, Address(ary1, 0));
8295 andl(tmp1, 0x00008080);
8296 jccb(Assembler::notZero, TRUE_LABEL);
8297 subptr(result, 2);
8298 lea(ary1, Address(ary1, 2));
8299
8300 bind(COMPARE_BYTE);
8301 testl(result, 0x1); // tail byte
8302 jccb(Assembler::zero, FALSE_LABEL);
8303 load_unsigned_byte(tmp1, Address(ary1, 0));
8304 andl(tmp1, 0x00000080);
8305 jccb(Assembler::notEqual, TRUE_LABEL);
8306 jmpb(FALSE_LABEL);
8307
8308 bind(TRUE_LABEL);
8309 movl(result, 1); // return true
8310 jmpb(DONE);
8311
8312 bind(FALSE_LABEL);
8313 xorl(result, result); // return false
8314
8315 // That's it
8316 bind(DONE);
8317 if (UseAVX >= 2 && UseSSE >= 2) {
8318 // clean upper bits of YMM registers
8319 vpxor(vec1, vec1);
8320 vpxor(vec2, vec2);
8321 }
8322 }
8323 // Compare char[] or byte[] arrays aligned to 4 bytes or substrings.
8324 void MacroAssembler::arrays_equals(bool is_array_equ, Register ary1, Register ary2,
8325 Register limit, Register result, Register chr,
8326 XMMRegister vec1, XMMRegister vec2, bool is_char) {
8327 ShortBranchVerifier sbv(this);
8328 Label TRUE_LABEL, FALSE_LABEL, DONE, COMPARE_VECTORS, COMPARE_CHAR, COMPARE_BYTE;
8329
8330 int length_offset = arrayOopDesc::length_offset_in_bytes();
8331 int base_offset = arrayOopDesc::base_offset_in_bytes(is_char ? T_CHAR : T_BYTE);
8332
8333 if (is_array_equ) {
8334 // Check the input args
8335 cmpptr(ary1, ary2);
8336 jcc(Assembler::equal, TRUE_LABEL);
8337
8338 // Need additional checks for arrays_equals.
8339 testptr(ary1, ary1);
8340 jcc(Assembler::zero, FALSE_LABEL);
8341 testptr(ary2, ary2);
8342 jcc(Assembler::zero, FALSE_LABEL);
8343
8344 // Check the lengths
8345 movl(limit, Address(ary1, length_offset));
8346 cmpl(limit, Address(ary2, length_offset));
8347 jcc(Assembler::notEqual, FALSE_LABEL);
8348 }
8349
8350 // count == 0
8351 testl(limit, limit);
8352 jcc(Assembler::zero, TRUE_LABEL);
8353
8354 if (is_array_equ) {
8355 // Load array address
8356 lea(ary1, Address(ary1, base_offset));
8357 lea(ary2, Address(ary2, base_offset));
8358 }
8359
8360 if (is_array_equ && is_char) {
8361 // arrays_equals when used for char[].
8362 shll(limit, 1); // byte count != 0
8363 }
8364 movl(result, limit); // copy
8365
8366 if (UseAVX >= 2) {
8367 // With AVX2, use 32-byte vector compare
8368 Label COMPARE_WIDE_VECTORS, COMPARE_TAIL;
8369
8370 // Compare 32-byte vectors
8371 andl(result, 0x0000001f); // tail count (in bytes)
8372 andl(limit, 0xffffffe0); // vector count (in bytes)
8373 jcc(Assembler::zero, COMPARE_TAIL);
8374
8375 lea(ary1, Address(ary1, limit, Address::times_1));
8376 lea(ary2, Address(ary2, limit, Address::times_1));
8377 negptr(limit);
8378
8379 bind(COMPARE_WIDE_VECTORS);
8380
8381 #ifdef _LP64
8382 if (VM_Version::supports_avx512vlbw()) { // trying 64 bytes fast loop
8383 Label COMPARE_WIDE_VECTORS_LOOP_AVX2, COMPARE_WIDE_VECTORS_LOOP_AVX3;
8384
8385 cmpl(limit, -64);
8386 jccb(Assembler::greater, COMPARE_WIDE_VECTORS_LOOP_AVX2);
8387
8388 bind(COMPARE_WIDE_VECTORS_LOOP_AVX3); // the hottest loop
8389
8390 evmovdquq(vec1, Address(ary1, limit, Address::times_1), Assembler::AVX_512bit);
8391 evpcmpeqb(k7, vec1, Address(ary2, limit, Address::times_1), Assembler::AVX_512bit);
8392 kortestql(k7, k7);
8393 jcc(Assembler::aboveEqual, FALSE_LABEL); // miscompare
8394 addptr(limit, 64); // update since we already compared at this addr
8395 cmpl(limit, -64);
8396 jccb(Assembler::lessEqual, COMPARE_WIDE_VECTORS_LOOP_AVX3);
8397
8398 // At this point we may still need to compare -limit+result bytes.
8399 // We could execute the next two instruction and just continue via non-wide path:
8400 // cmpl(limit, 0);
8401 // jcc(Assembler::equal, COMPARE_TAIL); // true
8402 // But since we stopped at the points ary{1,2}+limit which are
8403 // not farther than 64 bytes from the ends of arrays ary{1,2}+result
8404 // (|limit| <= 32 and result < 32),
8405 // we may just compare the last 64 bytes.
8406 //
8407 addptr(result, -64); // it is safe, bc we just came from this area
8408 evmovdquq(vec1, Address(ary1, result, Address::times_1), Assembler::AVX_512bit);
8409 evpcmpeqb(k7, vec1, Address(ary2, result, Address::times_1), Assembler::AVX_512bit);
8410 kortestql(k7, k7);
8411 jcc(Assembler::aboveEqual, FALSE_LABEL); // miscompare
8412
8413 jmp(TRUE_LABEL);
8414
8415 bind(COMPARE_WIDE_VECTORS_LOOP_AVX2);
8416
8417 }//if (VM_Version::supports_avx512vlbw())
8418 #endif //_LP64
8419
8420 vmovdqu(vec1, Address(ary1, limit, Address::times_1));
8421 vmovdqu(vec2, Address(ary2, limit, Address::times_1));
8422 vpxor(vec1, vec2);
8423
8424 vptest(vec1, vec1);
8425 jcc(Assembler::notZero, FALSE_LABEL);
8426 addptr(limit, 32);
8427 jcc(Assembler::notZero, COMPARE_WIDE_VECTORS);
8428
8429 testl(result, result);
8430 jcc(Assembler::zero, TRUE_LABEL);
8431
8432 vmovdqu(vec1, Address(ary1, result, Address::times_1, -32));
8433 vmovdqu(vec2, Address(ary2, result, Address::times_1, -32));
8434 vpxor(vec1, vec2);
8435
8436 vptest(vec1, vec1);
8437 jccb(Assembler::notZero, FALSE_LABEL);
8438 jmpb(TRUE_LABEL);
8439
8440 bind(COMPARE_TAIL); // limit is zero
8441 movl(limit, result);
8442 // Fallthru to tail compare
8443 } else if (UseSSE42Intrinsics) {
8444 // With SSE4.2, use double quad vector compare
8445 Label COMPARE_WIDE_VECTORS, COMPARE_TAIL;
8446
8447 // Compare 16-byte vectors
8448 andl(result, 0x0000000f); // tail count (in bytes)
8449 andl(limit, 0xfffffff0); // vector count (in bytes)
8450 jcc(Assembler::zero, COMPARE_TAIL);
8451
8452 lea(ary1, Address(ary1, limit, Address::times_1));
8453 lea(ary2, Address(ary2, limit, Address::times_1));
8454 negptr(limit);
8455
8456 bind(COMPARE_WIDE_VECTORS);
8457 movdqu(vec1, Address(ary1, limit, Address::times_1));
8458 movdqu(vec2, Address(ary2, limit, Address::times_1));
8459 pxor(vec1, vec2);
8460
8461 ptest(vec1, vec1);
8462 jcc(Assembler::notZero, FALSE_LABEL);
8463 addptr(limit, 16);
8464 jcc(Assembler::notZero, COMPARE_WIDE_VECTORS);
8465
8466 testl(result, result);
8467 jcc(Assembler::zero, TRUE_LABEL);
8468
8469 movdqu(vec1, Address(ary1, result, Address::times_1, -16));
8470 movdqu(vec2, Address(ary2, result, Address::times_1, -16));
8471 pxor(vec1, vec2);
8472
8473 ptest(vec1, vec1);
8474 jccb(Assembler::notZero, FALSE_LABEL);
8475 jmpb(TRUE_LABEL);
8476
8477 bind(COMPARE_TAIL); // limit is zero
8478 movl(limit, result);
8479 // Fallthru to tail compare
8480 }
8481
8482 // Compare 4-byte vectors
8483 andl(limit, 0xfffffffc); // vector count (in bytes)
8484 jccb(Assembler::zero, COMPARE_CHAR);
8485
8486 lea(ary1, Address(ary1, limit, Address::times_1));
8487 lea(ary2, Address(ary2, limit, Address::times_1));
8488 negptr(limit);
8489
8490 bind(COMPARE_VECTORS);
8491 movl(chr, Address(ary1, limit, Address::times_1));
8492 cmpl(chr, Address(ary2, limit, Address::times_1));
8493 jccb(Assembler::notEqual, FALSE_LABEL);
8494 addptr(limit, 4);
8495 jcc(Assembler::notZero, COMPARE_VECTORS);
8496
8497 // Compare trailing char (final 2 bytes), if any
8498 bind(COMPARE_CHAR);
8499 testl(result, 0x2); // tail char
8500 jccb(Assembler::zero, COMPARE_BYTE);
8501 load_unsigned_short(chr, Address(ary1, 0));
8502 load_unsigned_short(limit, Address(ary2, 0));
8503 cmpl(chr, limit);
8504 jccb(Assembler::notEqual, FALSE_LABEL);
8505
8506 if (is_array_equ && is_char) {
8507 bind(COMPARE_BYTE);
8508 } else {
8509 lea(ary1, Address(ary1, 2));
8510 lea(ary2, Address(ary2, 2));
8511
8512 bind(COMPARE_BYTE);
8513 testl(result, 0x1); // tail byte
8514 jccb(Assembler::zero, TRUE_LABEL);
8515 load_unsigned_byte(chr, Address(ary1, 0));
8516 load_unsigned_byte(limit, Address(ary2, 0));
8517 cmpl(chr, limit);
8518 jccb(Assembler::notEqual, FALSE_LABEL);
8519 }
8520 bind(TRUE_LABEL);
8521 movl(result, 1); // return true
8522 jmpb(DONE);
8523
8524 bind(FALSE_LABEL);
8525 xorl(result, result); // return false
8526
8527 // That's it
8528 bind(DONE);
8529 if (UseAVX >= 2) {
8530 // clean upper bits of YMM registers
8531 vpxor(vec1, vec1);
8532 vpxor(vec2, vec2);
8533 }
8534 }
8535
8536 #endif
8537
8538 void MacroAssembler::generate_fill(BasicType t, bool aligned,
8539 Register to, Register value, Register count,
8540 Register rtmp, XMMRegister xtmp) {
8541 ShortBranchVerifier sbv(this);
8542 assert_different_registers(to, value, count, rtmp);
8543 Label L_exit, L_skip_align1, L_skip_align2, L_fill_byte;
8544 Label L_fill_2_bytes, L_fill_4_bytes;
8545
8546 int shift = -1;
8547 switch (t) {
8548 case T_BYTE:
8549 shift = 2;
8550 break;
8551 case T_SHORT:
8552 shift = 1;
8553 break;
8554 case T_INT:
8555 shift = 0;
8556 break;
8557 default: ShouldNotReachHere();
8558 }
8559
8560 if (t == T_BYTE) {
8561 andl(value, 0xff);
8562 movl(rtmp, value);
8563 shll(rtmp, 8);
8564 orl(value, rtmp);
8565 }
8566 if (t == T_SHORT) {
8567 andl(value, 0xffff);
8568 }
8569 if (t == T_BYTE || t == T_SHORT) {
8570 movl(rtmp, value);
8571 shll(rtmp, 16);
8572 orl(value, rtmp);
8573 }
8574
8575 cmpl(count, 2<<shift); // Short arrays (< 8 bytes) fill by element
8576 jcc(Assembler::below, L_fill_4_bytes); // use unsigned cmp
8577 if (!UseUnalignedLoadStores && !aligned && (t == T_BYTE || t == T_SHORT)) {
8578 // align source address at 4 bytes address boundary
8579 if (t == T_BYTE) {
8580 // One byte misalignment happens only for byte arrays
8581 testptr(to, 1);
8582 jccb(Assembler::zero, L_skip_align1);
8583 movb(Address(to, 0), value);
8584 increment(to);
8585 decrement(count);
8586 BIND(L_skip_align1);
8587 }
8588 // Two bytes misalignment happens only for byte and short (char) arrays
8589 testptr(to, 2);
8590 jccb(Assembler::zero, L_skip_align2);
8591 movw(Address(to, 0), value);
8592 addptr(to, 2);
8593 subl(count, 1<<(shift-1));
8594 BIND(L_skip_align2);
8595 }
8596 if (UseSSE < 2) {
8597 Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes;
8598 // Fill 32-byte chunks
8599 subl(count, 8 << shift);
8600 jcc(Assembler::less, L_check_fill_8_bytes);
8601 align(16);
8602
8603 BIND(L_fill_32_bytes_loop);
8604
8605 for (int i = 0; i < 32; i += 4) {
8606 movl(Address(to, i), value);
8607 }
8608
8609 addptr(to, 32);
8610 subl(count, 8 << shift);
8611 jcc(Assembler::greaterEqual, L_fill_32_bytes_loop);
8612 BIND(L_check_fill_8_bytes);
8613 addl(count, 8 << shift);
8614 jccb(Assembler::zero, L_exit);
8615 jmpb(L_fill_8_bytes);
8616
8617 //
8618 // length is too short, just fill qwords
8619 //
8620 BIND(L_fill_8_bytes_loop);
8621 movl(Address(to, 0), value);
8622 movl(Address(to, 4), value);
8623 addptr(to, 8);
8624 BIND(L_fill_8_bytes);
8625 subl(count, 1 << (shift + 1));
8626 jcc(Assembler::greaterEqual, L_fill_8_bytes_loop);
8627 // fall through to fill 4 bytes
8628 } else {
8629 Label L_fill_32_bytes;
8630 if (!UseUnalignedLoadStores) {
8631 // align to 8 bytes, we know we are 4 byte aligned to start
8632 testptr(to, 4);
8633 jccb(Assembler::zero, L_fill_32_bytes);
8634 movl(Address(to, 0), value);
8635 addptr(to, 4);
8636 subl(count, 1<<shift);
8637 }
8638 BIND(L_fill_32_bytes);
8639 {
8640 assert( UseSSE >= 2, "supported cpu only" );
8641 Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes;
8642 if (UseAVX > 2) {
8643 movl(rtmp, 0xffff);
8644 kmovwl(k1, rtmp);
8645 }
8646 movdl(xtmp, value);
8647 if (UseAVX > 2 && UseUnalignedLoadStores) {
8648 // Fill 64-byte chunks
8649 Label L_fill_64_bytes_loop, L_check_fill_32_bytes;
8650 evpbroadcastd(xtmp, xtmp, Assembler::AVX_512bit);
8651
8652 subl(count, 16 << shift);
8653 jcc(Assembler::less, L_check_fill_32_bytes);
8654 align(16);
8655
8656 BIND(L_fill_64_bytes_loop);
8657 evmovdqul(Address(to, 0), xtmp, Assembler::AVX_512bit);
8658 addptr(to, 64);
8659 subl(count, 16 << shift);
8660 jcc(Assembler::greaterEqual, L_fill_64_bytes_loop);
8661
8662 BIND(L_check_fill_32_bytes);
8663 addl(count, 8 << shift);
8664 jccb(Assembler::less, L_check_fill_8_bytes);
8665 vmovdqu(Address(to, 0), xtmp);
8666 addptr(to, 32);
8667 subl(count, 8 << shift);
8668
8669 BIND(L_check_fill_8_bytes);
8670 } else if (UseAVX == 2 && UseUnalignedLoadStores) {
8671 // Fill 64-byte chunks
8672 Label L_fill_64_bytes_loop, L_check_fill_32_bytes;
8673 vpbroadcastd(xtmp, xtmp);
8674
8675 subl(count, 16 << shift);
8676 jcc(Assembler::less, L_check_fill_32_bytes);
8677 align(16);
8678
8679 BIND(L_fill_64_bytes_loop);
8680 vmovdqu(Address(to, 0), xtmp);
8681 vmovdqu(Address(to, 32), xtmp);
8682 addptr(to, 64);
8683 subl(count, 16 << shift);
8684 jcc(Assembler::greaterEqual, L_fill_64_bytes_loop);
8685
8686 BIND(L_check_fill_32_bytes);
8687 addl(count, 8 << shift);
8688 jccb(Assembler::less, L_check_fill_8_bytes);
8689 vmovdqu(Address(to, 0), xtmp);
8690 addptr(to, 32);
8691 subl(count, 8 << shift);
8692
8693 BIND(L_check_fill_8_bytes);
8694 // clean upper bits of YMM registers
8695 movdl(xtmp, value);
8696 pshufd(xtmp, xtmp, 0);
8697 } else {
8698 // Fill 32-byte chunks
8699 pshufd(xtmp, xtmp, 0);
8700
8701 subl(count, 8 << shift);
8702 jcc(Assembler::less, L_check_fill_8_bytes);
8703 align(16);
8704
8705 BIND(L_fill_32_bytes_loop);
8706
8707 if (UseUnalignedLoadStores) {
8708 movdqu(Address(to, 0), xtmp);
8709 movdqu(Address(to, 16), xtmp);
8710 } else {
8711 movq(Address(to, 0), xtmp);
8712 movq(Address(to, 8), xtmp);
8713 movq(Address(to, 16), xtmp);
8714 movq(Address(to, 24), xtmp);
8715 }
8716
8717 addptr(to, 32);
8718 subl(count, 8 << shift);
8719 jcc(Assembler::greaterEqual, L_fill_32_bytes_loop);
8720
8721 BIND(L_check_fill_8_bytes);
8722 }
8723 addl(count, 8 << shift);
8724 jccb(Assembler::zero, L_exit);
8725 jmpb(L_fill_8_bytes);
8726
8727 //
8728 // length is too short, just fill qwords
8729 //
8730 BIND(L_fill_8_bytes_loop);
8731 movq(Address(to, 0), xtmp);
8732 addptr(to, 8);
8733 BIND(L_fill_8_bytes);
8734 subl(count, 1 << (shift + 1));
8735 jcc(Assembler::greaterEqual, L_fill_8_bytes_loop);
8736 }
8737 }
8738 // fill trailing 4 bytes
8739 BIND(L_fill_4_bytes);
8740 testl(count, 1<<shift);
8741 jccb(Assembler::zero, L_fill_2_bytes);
8742 movl(Address(to, 0), value);
8743 if (t == T_BYTE || t == T_SHORT) {
8744 addptr(to, 4);
8745 BIND(L_fill_2_bytes);
8746 // fill trailing 2 bytes
8747 testl(count, 1<<(shift-1));
8748 jccb(Assembler::zero, L_fill_byte);
8749 movw(Address(to, 0), value);
8750 if (t == T_BYTE) {
8751 addptr(to, 2);
8752 BIND(L_fill_byte);
8753 // fill trailing byte
8754 testl(count, 1);
8755 jccb(Assembler::zero, L_exit);
8756 movb(Address(to, 0), value);
8757 } else {
8758 BIND(L_fill_byte);
8759 }
8760 } else {
8761 BIND(L_fill_2_bytes);
8762 }
8763 BIND(L_exit);
8764 }
8765
8766 // encode char[] to byte[] in ISO_8859_1
8767 //@HotSpotIntrinsicCandidate
8768 //private static int implEncodeISOArray(byte[] sa, int sp,
8769 //byte[] da, int dp, int len) {
8770 // int i = 0;
8771 // for (; i < len; i++) {
8772 // char c = StringUTF16.getChar(sa, sp++);
8773 // if (c > '\u00FF')
8774 // break;
8775 // da[dp++] = (byte)c;
8776 // }
8777 // return i;
8778 //}
8779 void MacroAssembler::encode_iso_array(Register src, Register dst, Register len,
8780 XMMRegister tmp1Reg, XMMRegister tmp2Reg,
8781 XMMRegister tmp3Reg, XMMRegister tmp4Reg,
8782 Register tmp5, Register result) {
8783
8784 // rsi: src
8785 // rdi: dst
8786 // rdx: len
8787 // rcx: tmp5
8788 // rax: result
8789 ShortBranchVerifier sbv(this);
8790 assert_different_registers(src, dst, len, tmp5, result);
8791 Label L_done, L_copy_1_char, L_copy_1_char_exit;
8792
8793 // set result
8794 xorl(result, result);
8795 // check for zero length
8796 testl(len, len);
8797 jcc(Assembler::zero, L_done);
8798
8799 movl(result, len);
8800
8801 // Setup pointers
8802 lea(src, Address(src, len, Address::times_2)); // char[]
8803 lea(dst, Address(dst, len, Address::times_1)); // byte[]
8804 negptr(len);
8805
8806 if (UseSSE42Intrinsics || UseAVX >= 2) {
8807 Label L_chars_8_check, L_copy_8_chars, L_copy_8_chars_exit;
8808 Label L_chars_16_check, L_copy_16_chars, L_copy_16_chars_exit;
8809
8810 if (UseAVX >= 2) {
8811 Label L_chars_32_check, L_copy_32_chars, L_copy_32_chars_exit;
8812 movl(tmp5, 0xff00ff00); // create mask to test for Unicode chars in vector
8813 movdl(tmp1Reg, tmp5);
8814 vpbroadcastd(tmp1Reg, tmp1Reg);
8815 jmp(L_chars_32_check);
8816
8817 bind(L_copy_32_chars);
8818 vmovdqu(tmp3Reg, Address(src, len, Address::times_2, -64));
8819 vmovdqu(tmp4Reg, Address(src, len, Address::times_2, -32));
8820 vpor(tmp2Reg, tmp3Reg, tmp4Reg, /* vector_len */ 1);
8821 vptest(tmp2Reg, tmp1Reg); // check for Unicode chars in vector
8822 jccb(Assembler::notZero, L_copy_32_chars_exit);
8823 vpackuswb(tmp3Reg, tmp3Reg, tmp4Reg, /* vector_len */ 1);
8824 vpermq(tmp4Reg, tmp3Reg, 0xD8, /* vector_len */ 1);
8825 vmovdqu(Address(dst, len, Address::times_1, -32), tmp4Reg);
8826
8827 bind(L_chars_32_check);
8828 addptr(len, 32);
8829 jcc(Assembler::lessEqual, L_copy_32_chars);
8830
8831 bind(L_copy_32_chars_exit);
8832 subptr(len, 16);
8833 jccb(Assembler::greater, L_copy_16_chars_exit);
8834
8835 } else if (UseSSE42Intrinsics) {
8836 movl(tmp5, 0xff00ff00); // create mask to test for Unicode chars in vector
8837 movdl(tmp1Reg, tmp5);
8838 pshufd(tmp1Reg, tmp1Reg, 0);
8839 jmpb(L_chars_16_check);
8840 }
8841
8842 bind(L_copy_16_chars);
8843 if (UseAVX >= 2) {
8844 vmovdqu(tmp2Reg, Address(src, len, Address::times_2, -32));
8845 vptest(tmp2Reg, tmp1Reg);
8846 jcc(Assembler::notZero, L_copy_16_chars_exit);
8847 vpackuswb(tmp2Reg, tmp2Reg, tmp1Reg, /* vector_len */ 1);
8848 vpermq(tmp3Reg, tmp2Reg, 0xD8, /* vector_len */ 1);
8849 } else {
8850 if (UseAVX > 0) {
8851 movdqu(tmp3Reg, Address(src, len, Address::times_2, -32));
8852 movdqu(tmp4Reg, Address(src, len, Address::times_2, -16));
8853 vpor(tmp2Reg, tmp3Reg, tmp4Reg, /* vector_len */ 0);
8854 } else {
8855 movdqu(tmp3Reg, Address(src, len, Address::times_2, -32));
8856 por(tmp2Reg, tmp3Reg);
8857 movdqu(tmp4Reg, Address(src, len, Address::times_2, -16));
8858 por(tmp2Reg, tmp4Reg);
8859 }
8860 ptest(tmp2Reg, tmp1Reg); // check for Unicode chars in vector
8861 jccb(Assembler::notZero, L_copy_16_chars_exit);
8862 packuswb(tmp3Reg, tmp4Reg);
8863 }
8864 movdqu(Address(dst, len, Address::times_1, -16), tmp3Reg);
8865
8866 bind(L_chars_16_check);
8867 addptr(len, 16);
8868 jcc(Assembler::lessEqual, L_copy_16_chars);
8869
8870 bind(L_copy_16_chars_exit);
8871 if (UseAVX >= 2) {
8872 // clean upper bits of YMM registers
8873 vpxor(tmp2Reg, tmp2Reg);
8874 vpxor(tmp3Reg, tmp3Reg);
8875 vpxor(tmp4Reg, tmp4Reg);
8876 movdl(tmp1Reg, tmp5);
8877 pshufd(tmp1Reg, tmp1Reg, 0);
8878 }
8879 subptr(len, 8);
8880 jccb(Assembler::greater, L_copy_8_chars_exit);
8881
8882 bind(L_copy_8_chars);
8883 movdqu(tmp3Reg, Address(src, len, Address::times_2, -16));
8884 ptest(tmp3Reg, tmp1Reg);
8885 jccb(Assembler::notZero, L_copy_8_chars_exit);
8886 packuswb(tmp3Reg, tmp1Reg);
8887 movq(Address(dst, len, Address::times_1, -8), tmp3Reg);
8888 addptr(len, 8);
8889 jccb(Assembler::lessEqual, L_copy_8_chars);
8890
8891 bind(L_copy_8_chars_exit);
8892 subptr(len, 8);
8893 jccb(Assembler::zero, L_done);
8894 }
8895
8896 bind(L_copy_1_char);
8897 load_unsigned_short(tmp5, Address(src, len, Address::times_2, 0));
8898 testl(tmp5, 0xff00); // check if Unicode char
8899 jccb(Assembler::notZero, L_copy_1_char_exit);
8900 movb(Address(dst, len, Address::times_1, 0), tmp5);
8901 addptr(len, 1);
8902 jccb(Assembler::less, L_copy_1_char);
8903
8904 bind(L_copy_1_char_exit);
8905 addptr(result, len); // len is negative count of not processed elements
8906
8907 bind(L_done);
8908 }
8909
8910 #ifdef _LP64
8911 /**
8912 * Helper for multiply_to_len().
8913 */
8914 void MacroAssembler::add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2) {
8915 addq(dest_lo, src1);
8916 adcq(dest_hi, 0);
8917 addq(dest_lo, src2);
8918 adcq(dest_hi, 0);
8919 }
8920
8921 /**
8922 * Multiply 64 bit by 64 bit first loop.
8923 */
8924 void MacroAssembler::multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
8925 Register y, Register y_idx, Register z,
8926 Register carry, Register product,
8927 Register idx, Register kdx) {
8928 //
8929 // jlong carry, x[], y[], z[];
8930 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) {
8931 // huge_128 product = y[idx] * x[xstart] + carry;
8932 // z[kdx] = (jlong)product;
8933 // carry = (jlong)(product >>> 64);
8934 // }
8935 // z[xstart] = carry;
8936 //
8937
8938 Label L_first_loop, L_first_loop_exit;
8939 Label L_one_x, L_one_y, L_multiply;
8940
8941 decrementl(xstart);
8942 jcc(Assembler::negative, L_one_x);
8943
8944 movq(x_xstart, Address(x, xstart, Address::times_4, 0));
8945 rorq(x_xstart, 32); // convert big-endian to little-endian
8946
8947 bind(L_first_loop);
8948 decrementl(idx);
8949 jcc(Assembler::negative, L_first_loop_exit);
8950 decrementl(idx);
8951 jcc(Assembler::negative, L_one_y);
8952 movq(y_idx, Address(y, idx, Address::times_4, 0));
8953 rorq(y_idx, 32); // convert big-endian to little-endian
8954 bind(L_multiply);
8955 movq(product, x_xstart);
8956 mulq(y_idx); // product(rax) * y_idx -> rdx:rax
8957 addq(product, carry);
8958 adcq(rdx, 0);
8959 subl(kdx, 2);
8960 movl(Address(z, kdx, Address::times_4, 4), product);
8961 shrq(product, 32);
8962 movl(Address(z, kdx, Address::times_4, 0), product);
8963 movq(carry, rdx);
8964 jmp(L_first_loop);
8965
8966 bind(L_one_y);
8967 movl(y_idx, Address(y, 0));
8968 jmp(L_multiply);
8969
8970 bind(L_one_x);
8971 movl(x_xstart, Address(x, 0));
8972 jmp(L_first_loop);
8973
8974 bind(L_first_loop_exit);
8975 }
8976
8977 /**
8978 * Multiply 64 bit by 64 bit and add 128 bit.
8979 */
8980 void MacroAssembler::multiply_add_128_x_128(Register x_xstart, Register y, Register z,
8981 Register yz_idx, Register idx,
8982 Register carry, Register product, int offset) {
8983 // huge_128 product = (y[idx] * x_xstart) + z[kdx] + carry;
8984 // z[kdx] = (jlong)product;
8985
8986 movq(yz_idx, Address(y, idx, Address::times_4, offset));
8987 rorq(yz_idx, 32); // convert big-endian to little-endian
8988 movq(product, x_xstart);
8989 mulq(yz_idx); // product(rax) * yz_idx -> rdx:product(rax)
8990 movq(yz_idx, Address(z, idx, Address::times_4, offset));
8991 rorq(yz_idx, 32); // convert big-endian to little-endian
8992
8993 add2_with_carry(rdx, product, carry, yz_idx);
8994
8995 movl(Address(z, idx, Address::times_4, offset+4), product);
8996 shrq(product, 32);
8997 movl(Address(z, idx, Address::times_4, offset), product);
8998
8999 }
9000
9001 /**
9002 * Multiply 128 bit by 128 bit. Unrolled inner loop.
9003 */
9004 void MacroAssembler::multiply_128_x_128_loop(Register x_xstart, Register y, Register z,
9005 Register yz_idx, Register idx, Register jdx,
9006 Register carry, Register product,
9007 Register carry2) {
9008 // jlong carry, x[], y[], z[];
9009 // int kdx = ystart+1;
9010 // for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop
9011 // huge_128 product = (y[idx+1] * x_xstart) + z[kdx+idx+1] + carry;
9012 // z[kdx+idx+1] = (jlong)product;
9013 // jlong carry2 = (jlong)(product >>> 64);
9014 // product = (y[idx] * x_xstart) + z[kdx+idx] + carry2;
9015 // z[kdx+idx] = (jlong)product;
9016 // carry = (jlong)(product >>> 64);
9017 // }
9018 // idx += 2;
9019 // if (idx > 0) {
9020 // product = (y[idx] * x_xstart) + z[kdx+idx] + carry;
9021 // z[kdx+idx] = (jlong)product;
9022 // carry = (jlong)(product >>> 64);
9023 // }
9024 //
9025
9026 Label L_third_loop, L_third_loop_exit, L_post_third_loop_done;
9027
9028 movl(jdx, idx);
9029 andl(jdx, 0xFFFFFFFC);
9030 shrl(jdx, 2);
9031
9032 bind(L_third_loop);
9033 subl(jdx, 1);
9034 jcc(Assembler::negative, L_third_loop_exit);
9035 subl(idx, 4);
9036
9037 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry, product, 8);
9038 movq(carry2, rdx);
9039
9040 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry2, product, 0);
9041 movq(carry, rdx);
9042 jmp(L_third_loop);
9043
9044 bind (L_third_loop_exit);
9045
9046 andl (idx, 0x3);
9047 jcc(Assembler::zero, L_post_third_loop_done);
9048
9049 Label L_check_1;
9050 subl(idx, 2);
9051 jcc(Assembler::negative, L_check_1);
9052
9053 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry, product, 0);
9054 movq(carry, rdx);
9055
9056 bind (L_check_1);
9057 addl (idx, 0x2);
9058 andl (idx, 0x1);
9059 subl(idx, 1);
9060 jcc(Assembler::negative, L_post_third_loop_done);
9061
9062 movl(yz_idx, Address(y, idx, Address::times_4, 0));
9063 movq(product, x_xstart);
9064 mulq(yz_idx); // product(rax) * yz_idx -> rdx:product(rax)
9065 movl(yz_idx, Address(z, idx, Address::times_4, 0));
9066
9067 add2_with_carry(rdx, product, yz_idx, carry);
9068
9069 movl(Address(z, idx, Address::times_4, 0), product);
9070 shrq(product, 32);
9071
9072 shlq(rdx, 32);
9073 orq(product, rdx);
9074 movq(carry, product);
9075
9076 bind(L_post_third_loop_done);
9077 }
9078
9079 /**
9080 * Multiply 128 bit by 128 bit using BMI2. Unrolled inner loop.
9081 *
9082 */
9083 void MacroAssembler::multiply_128_x_128_bmi2_loop(Register y, Register z,
9084 Register carry, Register carry2,
9085 Register idx, Register jdx,
9086 Register yz_idx1, Register yz_idx2,
9087 Register tmp, Register tmp3, Register tmp4) {
9088 assert(UseBMI2Instructions, "should be used only when BMI2 is available");
9089
9090 // jlong carry, x[], y[], z[];
9091 // int kdx = ystart+1;
9092 // for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop
9093 // huge_128 tmp3 = (y[idx+1] * rdx) + z[kdx+idx+1] + carry;
9094 // jlong carry2 = (jlong)(tmp3 >>> 64);
9095 // huge_128 tmp4 = (y[idx] * rdx) + z[kdx+idx] + carry2;
9096 // carry = (jlong)(tmp4 >>> 64);
9097 // z[kdx+idx+1] = (jlong)tmp3;
9098 // z[kdx+idx] = (jlong)tmp4;
9099 // }
9100 // idx += 2;
9101 // if (idx > 0) {
9102 // yz_idx1 = (y[idx] * rdx) + z[kdx+idx] + carry;
9103 // z[kdx+idx] = (jlong)yz_idx1;
9104 // carry = (jlong)(yz_idx1 >>> 64);
9105 // }
9106 //
9107
9108 Label L_third_loop, L_third_loop_exit, L_post_third_loop_done;
9109
9110 movl(jdx, idx);
9111 andl(jdx, 0xFFFFFFFC);
9112 shrl(jdx, 2);
9113
9114 bind(L_third_loop);
9115 subl(jdx, 1);
9116 jcc(Assembler::negative, L_third_loop_exit);
9117 subl(idx, 4);
9118
9119 movq(yz_idx1, Address(y, idx, Address::times_4, 8));
9120 rorxq(yz_idx1, yz_idx1, 32); // convert big-endian to little-endian
9121 movq(yz_idx2, Address(y, idx, Address::times_4, 0));
9122 rorxq(yz_idx2, yz_idx2, 32);
9123
9124 mulxq(tmp4, tmp3, yz_idx1); // yz_idx1 * rdx -> tmp4:tmp3
9125 mulxq(carry2, tmp, yz_idx2); // yz_idx2 * rdx -> carry2:tmp
9126
9127 movq(yz_idx1, Address(z, idx, Address::times_4, 8));
9128 rorxq(yz_idx1, yz_idx1, 32);
9129 movq(yz_idx2, Address(z, idx, Address::times_4, 0));
9130 rorxq(yz_idx2, yz_idx2, 32);
9131
9132 if (VM_Version::supports_adx()) {
9133 adcxq(tmp3, carry);
9134 adoxq(tmp3, yz_idx1);
9135
9136 adcxq(tmp4, tmp);
9137 adoxq(tmp4, yz_idx2);
9138
9139 movl(carry, 0); // does not affect flags
9140 adcxq(carry2, carry);
9141 adoxq(carry2, carry);
9142 } else {
9143 add2_with_carry(tmp4, tmp3, carry, yz_idx1);
9144 add2_with_carry(carry2, tmp4, tmp, yz_idx2);
9145 }
9146 movq(carry, carry2);
9147
9148 movl(Address(z, idx, Address::times_4, 12), tmp3);
9149 shrq(tmp3, 32);
9150 movl(Address(z, idx, Address::times_4, 8), tmp3);
9151
9152 movl(Address(z, idx, Address::times_4, 4), tmp4);
9153 shrq(tmp4, 32);
9154 movl(Address(z, idx, Address::times_4, 0), tmp4);
9155
9156 jmp(L_third_loop);
9157
9158 bind (L_third_loop_exit);
9159
9160 andl (idx, 0x3);
9161 jcc(Assembler::zero, L_post_third_loop_done);
9162
9163 Label L_check_1;
9164 subl(idx, 2);
9165 jcc(Assembler::negative, L_check_1);
9166
9167 movq(yz_idx1, Address(y, idx, Address::times_4, 0));
9168 rorxq(yz_idx1, yz_idx1, 32);
9169 mulxq(tmp4, tmp3, yz_idx1); // yz_idx1 * rdx -> tmp4:tmp3
9170 movq(yz_idx2, Address(z, idx, Address::times_4, 0));
9171 rorxq(yz_idx2, yz_idx2, 32);
9172
9173 add2_with_carry(tmp4, tmp3, carry, yz_idx2);
9174
9175 movl(Address(z, idx, Address::times_4, 4), tmp3);
9176 shrq(tmp3, 32);
9177 movl(Address(z, idx, Address::times_4, 0), tmp3);
9178 movq(carry, tmp4);
9179
9180 bind (L_check_1);
9181 addl (idx, 0x2);
9182 andl (idx, 0x1);
9183 subl(idx, 1);
9184 jcc(Assembler::negative, L_post_third_loop_done);
9185 movl(tmp4, Address(y, idx, Address::times_4, 0));
9186 mulxq(carry2, tmp3, tmp4); // tmp4 * rdx -> carry2:tmp3
9187 movl(tmp4, Address(z, idx, Address::times_4, 0));
9188
9189 add2_with_carry(carry2, tmp3, tmp4, carry);
9190
9191 movl(Address(z, idx, Address::times_4, 0), tmp3);
9192 shrq(tmp3, 32);
9193
9194 shlq(carry2, 32);
9195 orq(tmp3, carry2);
9196 movq(carry, tmp3);
9197
9198 bind(L_post_third_loop_done);
9199 }
9200
9201 /**
9202 * Code for BigInteger::multiplyToLen() instrinsic.
9203 *
9204 * rdi: x
9205 * rax: xlen
9206 * rsi: y
9207 * rcx: ylen
9208 * r8: z
9209 * r11: zlen
9210 * r12: tmp1
9211 * r13: tmp2
9212 * r14: tmp3
9213 * r15: tmp4
9214 * rbx: tmp5
9215 *
9216 */
9217 void MacroAssembler::multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z, Register zlen,
9218 Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5) {
9219 ShortBranchVerifier sbv(this);
9220 assert_different_registers(x, xlen, y, ylen, z, zlen, tmp1, tmp2, tmp3, tmp4, tmp5, rdx);
9221
9222 push(tmp1);
9223 push(tmp2);
9224 push(tmp3);
9225 push(tmp4);
9226 push(tmp5);
9227
9228 push(xlen);
9229 push(zlen);
9230
9231 const Register idx = tmp1;
9232 const Register kdx = tmp2;
9233 const Register xstart = tmp3;
9234
9235 const Register y_idx = tmp4;
9236 const Register carry = tmp5;
9237 const Register product = xlen;
9238 const Register x_xstart = zlen; // reuse register
9239
9240 // First Loop.
9241 //
9242 // final static long LONG_MASK = 0xffffffffL;
9243 // int xstart = xlen - 1;
9244 // int ystart = ylen - 1;
9245 // long carry = 0;
9246 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) {
9247 // long product = (y[idx] & LONG_MASK) * (x[xstart] & LONG_MASK) + carry;
9248 // z[kdx] = (int)product;
9249 // carry = product >>> 32;
9250 // }
9251 // z[xstart] = (int)carry;
9252 //
9253
9254 movl(idx, ylen); // idx = ylen;
9255 movl(kdx, zlen); // kdx = xlen+ylen;
9256 xorq(carry, carry); // carry = 0;
9257
9258 Label L_done;
9259
9260 movl(xstart, xlen);
9261 decrementl(xstart);
9262 jcc(Assembler::negative, L_done);
9263
9264 multiply_64_x_64_loop(x, xstart, x_xstart, y, y_idx, z, carry, product, idx, kdx);
9265
9266 Label L_second_loop;
9267 testl(kdx, kdx);
9268 jcc(Assembler::zero, L_second_loop);
9269
9270 Label L_carry;
9271 subl(kdx, 1);
9272 jcc(Assembler::zero, L_carry);
9273
9274 movl(Address(z, kdx, Address::times_4, 0), carry);
9275 shrq(carry, 32);
9276 subl(kdx, 1);
9277
9278 bind(L_carry);
9279 movl(Address(z, kdx, Address::times_4, 0), carry);
9280
9281 // Second and third (nested) loops.
9282 //
9283 // for (int i = xstart-1; i >= 0; i--) { // Second loop
9284 // carry = 0;
9285 // for (int jdx=ystart, k=ystart+1+i; jdx >= 0; jdx--, k--) { // Third loop
9286 // long product = (y[jdx] & LONG_MASK) * (x[i] & LONG_MASK) +
9287 // (z[k] & LONG_MASK) + carry;
9288 // z[k] = (int)product;
9289 // carry = product >>> 32;
9290 // }
9291 // z[i] = (int)carry;
9292 // }
9293 //
9294 // i = xlen, j = tmp1, k = tmp2, carry = tmp5, x[i] = rdx
9295
9296 const Register jdx = tmp1;
9297
9298 bind(L_second_loop);
9299 xorl(carry, carry); // carry = 0;
9300 movl(jdx, ylen); // j = ystart+1
9301
9302 subl(xstart, 1); // i = xstart-1;
9303 jcc(Assembler::negative, L_done);
9304
9305 push (z);
9306
9307 Label L_last_x;
9308 lea(z, Address(z, xstart, Address::times_4, 4)); // z = z + k - j
9309 subl(xstart, 1); // i = xstart-1;
9310 jcc(Assembler::negative, L_last_x);
9311
9312 if (UseBMI2Instructions) {
9313 movq(rdx, Address(x, xstart, Address::times_4, 0));
9314 rorxq(rdx, rdx, 32); // convert big-endian to little-endian
9315 } else {
9316 movq(x_xstart, Address(x, xstart, Address::times_4, 0));
9317 rorq(x_xstart, 32); // convert big-endian to little-endian
9318 }
9319
9320 Label L_third_loop_prologue;
9321 bind(L_third_loop_prologue);
9322
9323 push (x);
9324 push (xstart);
9325 push (ylen);
9326
9327
9328 if (UseBMI2Instructions) {
9329 multiply_128_x_128_bmi2_loop(y, z, carry, x, jdx, ylen, product, tmp2, x_xstart, tmp3, tmp4);
9330 } else { // !UseBMI2Instructions
9331 multiply_128_x_128_loop(x_xstart, y, z, y_idx, jdx, ylen, carry, product, x);
9332 }
9333
9334 pop(ylen);
9335 pop(xlen);
9336 pop(x);
9337 pop(z);
9338
9339 movl(tmp3, xlen);
9340 addl(tmp3, 1);
9341 movl(Address(z, tmp3, Address::times_4, 0), carry);
9342 subl(tmp3, 1);
9343 jccb(Assembler::negative, L_done);
9344
9345 shrq(carry, 32);
9346 movl(Address(z, tmp3, Address::times_4, 0), carry);
9347 jmp(L_second_loop);
9348
9349 // Next infrequent code is moved outside loops.
9350 bind(L_last_x);
9351 if (UseBMI2Instructions) {
9352 movl(rdx, Address(x, 0));
9353 } else {
9354 movl(x_xstart, Address(x, 0));
9355 }
9356 jmp(L_third_loop_prologue);
9357
9358 bind(L_done);
9359
9360 pop(zlen);
9361 pop(xlen);
9362
9363 pop(tmp5);
9364 pop(tmp4);
9365 pop(tmp3);
9366 pop(tmp2);
9367 pop(tmp1);
9368 }
9369
9370 void MacroAssembler::vectorized_mismatch(Register obja, Register objb, Register length, Register log2_array_indxscale,
9371 Register result, Register tmp1, Register tmp2, XMMRegister rymm0, XMMRegister rymm1, XMMRegister rymm2){
9372 assert(UseSSE42Intrinsics, "SSE4.2 must be enabled.");
9373 Label VECTOR64_LOOP, VECTOR64_TAIL, VECTOR64_NOT_EQUAL, VECTOR32_TAIL;
9374 Label VECTOR32_LOOP, VECTOR16_LOOP, VECTOR8_LOOP, VECTOR4_LOOP;
9375 Label VECTOR16_TAIL, VECTOR8_TAIL, VECTOR4_TAIL;
9376 Label VECTOR32_NOT_EQUAL, VECTOR16_NOT_EQUAL, VECTOR8_NOT_EQUAL, VECTOR4_NOT_EQUAL;
9377 Label SAME_TILL_END, DONE;
9378 Label BYTES_LOOP, BYTES_TAIL, BYTES_NOT_EQUAL;
9379
9380 //scale is in rcx in both Win64 and Unix
9381 ShortBranchVerifier sbv(this);
9382
9383 shlq(length);
9384 xorq(result, result);
9385
9386 if ((UseAVX > 2) &&
9387 VM_Version::supports_avx512vlbw()) {
9388 set_vector_masking(); // opening of the stub context for programming mask registers
9389 cmpq(length, 64);
9390 jcc(Assembler::less, VECTOR32_TAIL);
9391 movq(tmp1, length);
9392 andq(tmp1, 0x3F); // tail count
9393 andq(length, ~(0x3F)); //vector count
9394
9395 bind(VECTOR64_LOOP);
9396 // AVX512 code to compare 64 byte vectors.
9397 evmovdqub(rymm0, Address(obja, result), Assembler::AVX_512bit);
9398 evpcmpeqb(k7, rymm0, Address(objb, result), Assembler::AVX_512bit);
9399 kortestql(k7, k7);
9400 jcc(Assembler::aboveEqual, VECTOR64_NOT_EQUAL); // mismatch
9401 addq(result, 64);
9402 subq(length, 64);
9403 jccb(Assembler::notZero, VECTOR64_LOOP);
9404
9405 //bind(VECTOR64_TAIL);
9406 testq(tmp1, tmp1);
9407 jcc(Assembler::zero, SAME_TILL_END);
9408
9409 bind(VECTOR64_TAIL);
9410 // AVX512 code to compare upto 63 byte vectors.
9411 // Save k1
9412 kmovql(k3, k1);
9413 mov64(tmp2, 0xFFFFFFFFFFFFFFFF);
9414 shlxq(tmp2, tmp2, tmp1);
9415 notq(tmp2);
9416 kmovql(k1, tmp2);
9417
9418 evmovdqub(rymm0, k1, Address(obja, result), Assembler::AVX_512bit);
9419 evpcmpeqb(k7, k1, rymm0, Address(objb, result), Assembler::AVX_512bit);
9420
9421 ktestql(k7, k1);
9422 // Restore k1
9423 kmovql(k1, k3);
9424 jcc(Assembler::below, SAME_TILL_END); // not mismatch
9425
9426 bind(VECTOR64_NOT_EQUAL);
9427 kmovql(tmp1, k7);
9428 notq(tmp1);
9429 tzcntq(tmp1, tmp1);
9430 addq(result, tmp1);
9431 shrq(result);
9432 jmp(DONE);
9433 bind(VECTOR32_TAIL);
9434 clear_vector_masking(); // closing of the stub context for programming mask registers
9435 }
9436
9437 cmpq(length, 8);
9438 jcc(Assembler::equal, VECTOR8_LOOP);
9439 jcc(Assembler::less, VECTOR4_TAIL);
9440
9441 if (UseAVX >= 2) {
9442
9443 cmpq(length, 16);
9444 jcc(Assembler::equal, VECTOR16_LOOP);
9445 jcc(Assembler::less, VECTOR8_LOOP);
9446
9447 cmpq(length, 32);
9448 jccb(Assembler::less, VECTOR16_TAIL);
9449
9450 subq(length, 32);
9451 bind(VECTOR32_LOOP);
9452 vmovdqu(rymm0, Address(obja, result));
9453 vmovdqu(rymm1, Address(objb, result));
9454 vpxor(rymm2, rymm0, rymm1, Assembler::AVX_256bit);
9455 vptest(rymm2, rymm2);
9456 jcc(Assembler::notZero, VECTOR32_NOT_EQUAL);//mismatch found
9457 addq(result, 32);
9458 subq(length, 32);
9459 jccb(Assembler::greaterEqual, VECTOR32_LOOP);
9460 addq(length, 32);
9461 jcc(Assembler::equal, SAME_TILL_END);
9462 //falling through if less than 32 bytes left //close the branch here.
9463
9464 bind(VECTOR16_TAIL);
9465 cmpq(length, 16);
9466 jccb(Assembler::less, VECTOR8_TAIL);
9467 bind(VECTOR16_LOOP);
9468 movdqu(rymm0, Address(obja, result));
9469 movdqu(rymm1, Address(objb, result));
9470 vpxor(rymm2, rymm0, rymm1, Assembler::AVX_128bit);
9471 ptest(rymm2, rymm2);
9472 jcc(Assembler::notZero, VECTOR16_NOT_EQUAL);//mismatch found
9473 addq(result, 16);
9474 subq(length, 16);
9475 jcc(Assembler::equal, SAME_TILL_END);
9476 //falling through if less than 16 bytes left
9477 } else {//regular intrinsics
9478
9479 cmpq(length, 16);
9480 jccb(Assembler::less, VECTOR8_TAIL);
9481
9482 subq(length, 16);
9483 bind(VECTOR16_LOOP);
9484 movdqu(rymm0, Address(obja, result));
9485 movdqu(rymm1, Address(objb, result));
9486 pxor(rymm0, rymm1);
9487 ptest(rymm0, rymm0);
9488 jcc(Assembler::notZero, VECTOR16_NOT_EQUAL);//mismatch found
9489 addq(result, 16);
9490 subq(length, 16);
9491 jccb(Assembler::greaterEqual, VECTOR16_LOOP);
9492 addq(length, 16);
9493 jcc(Assembler::equal, SAME_TILL_END);
9494 //falling through if less than 16 bytes left
9495 }
9496
9497 bind(VECTOR8_TAIL);
9498 cmpq(length, 8);
9499 jccb(Assembler::less, VECTOR4_TAIL);
9500 bind(VECTOR8_LOOP);
9501 movq(tmp1, Address(obja, result));
9502 movq(tmp2, Address(objb, result));
9503 xorq(tmp1, tmp2);
9504 testq(tmp1, tmp1);
9505 jcc(Assembler::notZero, VECTOR8_NOT_EQUAL);//mismatch found
9506 addq(result, 8);
9507 subq(length, 8);
9508 jcc(Assembler::equal, SAME_TILL_END);
9509 //falling through if less than 8 bytes left
9510
9511 bind(VECTOR4_TAIL);
9512 cmpq(length, 4);
9513 jccb(Assembler::less, BYTES_TAIL);
9514 bind(VECTOR4_LOOP);
9515 movl(tmp1, Address(obja, result));
9516 xorl(tmp1, Address(objb, result));
9517 testl(tmp1, tmp1);
9518 jcc(Assembler::notZero, VECTOR4_NOT_EQUAL);//mismatch found
9519 addq(result, 4);
9520 subq(length, 4);
9521 jcc(Assembler::equal, SAME_TILL_END);
9522 //falling through if less than 4 bytes left
9523
9524 bind(BYTES_TAIL);
9525 bind(BYTES_LOOP);
9526 load_unsigned_byte(tmp1, Address(obja, result));
9527 load_unsigned_byte(tmp2, Address(objb, result));
9528 xorl(tmp1, tmp2);
9529 testl(tmp1, tmp1);
9530 jccb(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found
9531 decq(length);
9532 jccb(Assembler::zero, SAME_TILL_END);
9533 incq(result);
9534 load_unsigned_byte(tmp1, Address(obja, result));
9535 load_unsigned_byte(tmp2, Address(objb, result));
9536 xorl(tmp1, tmp2);
9537 testl(tmp1, tmp1);
9538 jccb(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found
9539 decq(length);
9540 jccb(Assembler::zero, SAME_TILL_END);
9541 incq(result);
9542 load_unsigned_byte(tmp1, Address(obja, result));
9543 load_unsigned_byte(tmp2, Address(objb, result));
9544 xorl(tmp1, tmp2);
9545 testl(tmp1, tmp1);
9546 jccb(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found
9547 jmpb(SAME_TILL_END);
9548
9549 if (UseAVX >= 2) {
9550 bind(VECTOR32_NOT_EQUAL);
9551 vpcmpeqb(rymm2, rymm2, rymm2, Assembler::AVX_256bit);
9552 vpcmpeqb(rymm0, rymm0, rymm1, Assembler::AVX_256bit);
9553 vpxor(rymm0, rymm0, rymm2, Assembler::AVX_256bit);
9554 vpmovmskb(tmp1, rymm0);
9555 bsfq(tmp1, tmp1);
9556 addq(result, tmp1);
9557 shrq(result);
9558 jmpb(DONE);
9559 }
9560
9561 bind(VECTOR16_NOT_EQUAL);
9562 if (UseAVX >= 2) {
9563 vpcmpeqb(rymm2, rymm2, rymm2, Assembler::AVX_128bit);
9564 vpcmpeqb(rymm0, rymm0, rymm1, Assembler::AVX_128bit);
9565 pxor(rymm0, rymm2);
9566 } else {
9567 pcmpeqb(rymm2, rymm2);
9568 pxor(rymm0, rymm1);
9569 pcmpeqb(rymm0, rymm1);
9570 pxor(rymm0, rymm2);
9571 }
9572 pmovmskb(tmp1, rymm0);
9573 bsfq(tmp1, tmp1);
9574 addq(result, tmp1);
9575 shrq(result);
9576 jmpb(DONE);
9577
9578 bind(VECTOR8_NOT_EQUAL);
9579 bind(VECTOR4_NOT_EQUAL);
9580 bsfq(tmp1, tmp1);
9581 shrq(tmp1, 3);
9582 addq(result, tmp1);
9583 bind(BYTES_NOT_EQUAL);
9584 shrq(result);
9585 jmpb(DONE);
9586
9587 bind(SAME_TILL_END);
9588 mov64(result, -1);
9589
9590 bind(DONE);
9591 }
9592
9593 //Helper functions for square_to_len()
9594
9595 /**
9596 * Store the squares of x[], right shifted one bit (divided by 2) into z[]
9597 * Preserves x and z and modifies rest of the registers.
9598 */
9599 void MacroAssembler::square_rshift(Register x, Register xlen, Register z, Register tmp1, Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
9600 // Perform square and right shift by 1
9601 // Handle odd xlen case first, then for even xlen do the following
9602 // jlong carry = 0;
9603 // for (int j=0, i=0; j < xlen; j+=2, i+=4) {
9604 // huge_128 product = x[j:j+1] * x[j:j+1];
9605 // z[i:i+1] = (carry << 63) | (jlong)(product >>> 65);
9606 // z[i+2:i+3] = (jlong)(product >>> 1);
9607 // carry = (jlong)product;
9608 // }
9609
9610 xorq(tmp5, tmp5); // carry
9611 xorq(rdxReg, rdxReg);
9612 xorl(tmp1, tmp1); // index for x
9613 xorl(tmp4, tmp4); // index for z
9614
9615 Label L_first_loop, L_first_loop_exit;
9616
9617 testl(xlen, 1);
9618 jccb(Assembler::zero, L_first_loop); //jump if xlen is even
9619
9620 // Square and right shift by 1 the odd element using 32 bit multiply
9621 movl(raxReg, Address(x, tmp1, Address::times_4, 0));
9622 imulq(raxReg, raxReg);
9623 shrq(raxReg, 1);
9624 adcq(tmp5, 0);
9625 movq(Address(z, tmp4, Address::times_4, 0), raxReg);
9626 incrementl(tmp1);
9627 addl(tmp4, 2);
9628
9629 // Square and right shift by 1 the rest using 64 bit multiply
9630 bind(L_first_loop);
9631 cmpptr(tmp1, xlen);
9632 jccb(Assembler::equal, L_first_loop_exit);
9633
9634 // Square
9635 movq(raxReg, Address(x, tmp1, Address::times_4, 0));
9636 rorq(raxReg, 32); // convert big-endian to little-endian
9637 mulq(raxReg); // 64-bit multiply rax * rax -> rdx:rax
9638
9639 // Right shift by 1 and save carry
9640 shrq(tmp5, 1); // rdx:rax:tmp5 = (tmp5:rdx:rax) >>> 1
9641 rcrq(rdxReg, 1);
9642 rcrq(raxReg, 1);
9643 adcq(tmp5, 0);
9644
9645 // Store result in z
9646 movq(Address(z, tmp4, Address::times_4, 0), rdxReg);
9647 movq(Address(z, tmp4, Address::times_4, 8), raxReg);
9648
9649 // Update indices for x and z
9650 addl(tmp1, 2);
9651 addl(tmp4, 4);
9652 jmp(L_first_loop);
9653
9654 bind(L_first_loop_exit);
9655 }
9656
9657
9658 /**
9659 * Perform the following multiply add operation using BMI2 instructions
9660 * carry:sum = sum + op1*op2 + carry
9661 * op2 should be in rdx
9662 * op2 is preserved, all other registers are modified
9663 */
9664 void MacroAssembler::multiply_add_64_bmi2(Register sum, Register op1, Register op2, Register carry, Register tmp2) {
9665 // assert op2 is rdx
9666 mulxq(tmp2, op1, op1); // op1 * op2 -> tmp2:op1
9667 addq(sum, carry);
9668 adcq(tmp2, 0);
9669 addq(sum, op1);
9670 adcq(tmp2, 0);
9671 movq(carry, tmp2);
9672 }
9673
9674 /**
9675 * Perform the following multiply add operation:
9676 * carry:sum = sum + op1*op2 + carry
9677 * Preserves op1, op2 and modifies rest of registers
9678 */
9679 void MacroAssembler::multiply_add_64(Register sum, Register op1, Register op2, Register carry, Register rdxReg, Register raxReg) {
9680 // rdx:rax = op1 * op2
9681 movq(raxReg, op2);
9682 mulq(op1);
9683
9684 // rdx:rax = sum + carry + rdx:rax
9685 addq(sum, carry);
9686 adcq(rdxReg, 0);
9687 addq(sum, raxReg);
9688 adcq(rdxReg, 0);
9689
9690 // carry:sum = rdx:sum
9691 movq(carry, rdxReg);
9692 }
9693
9694 /**
9695 * Add 64 bit long carry into z[] with carry propogation.
9696 * Preserves z and carry register values and modifies rest of registers.
9697 *
9698 */
9699 void MacroAssembler::add_one_64(Register z, Register zlen, Register carry, Register tmp1) {
9700 Label L_fourth_loop, L_fourth_loop_exit;
9701
9702 movl(tmp1, 1);
9703 subl(zlen, 2);
9704 addq(Address(z, zlen, Address::times_4, 0), carry);
9705
9706 bind(L_fourth_loop);
9707 jccb(Assembler::carryClear, L_fourth_loop_exit);
9708 subl(zlen, 2);
9709 jccb(Assembler::negative, L_fourth_loop_exit);
9710 addq(Address(z, zlen, Address::times_4, 0), tmp1);
9711 jmp(L_fourth_loop);
9712 bind(L_fourth_loop_exit);
9713 }
9714
9715 /**
9716 * Shift z[] left by 1 bit.
9717 * Preserves x, len, z and zlen registers and modifies rest of the registers.
9718 *
9719 */
9720 void MacroAssembler::lshift_by_1(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2, Register tmp3, Register tmp4) {
9721
9722 Label L_fifth_loop, L_fifth_loop_exit;
9723
9724 // Fifth loop
9725 // Perform primitiveLeftShift(z, zlen, 1)
9726
9727 const Register prev_carry = tmp1;
9728 const Register new_carry = tmp4;
9729 const Register value = tmp2;
9730 const Register zidx = tmp3;
9731
9732 // int zidx, carry;
9733 // long value;
9734 // carry = 0;
9735 // for (zidx = zlen-2; zidx >=0; zidx -= 2) {
9736 // (carry:value) = (z[i] << 1) | carry ;
9737 // z[i] = value;
9738 // }
9739
9740 movl(zidx, zlen);
9741 xorl(prev_carry, prev_carry); // clear carry flag and prev_carry register
9742
9743 bind(L_fifth_loop);
9744 decl(zidx); // Use decl to preserve carry flag
9745 decl(zidx);
9746 jccb(Assembler::negative, L_fifth_loop_exit);
9747
9748 if (UseBMI2Instructions) {
9749 movq(value, Address(z, zidx, Address::times_4, 0));
9750 rclq(value, 1);
9751 rorxq(value, value, 32);
9752 movq(Address(z, zidx, Address::times_4, 0), value); // Store back in big endian form
9753 }
9754 else {
9755 // clear new_carry
9756 xorl(new_carry, new_carry);
9757
9758 // Shift z[i] by 1, or in previous carry and save new carry
9759 movq(value, Address(z, zidx, Address::times_4, 0));
9760 shlq(value, 1);
9761 adcl(new_carry, 0);
9762
9763 orq(value, prev_carry);
9764 rorq(value, 0x20);
9765 movq(Address(z, zidx, Address::times_4, 0), value); // Store back in big endian form
9766
9767 // Set previous carry = new carry
9768 movl(prev_carry, new_carry);
9769 }
9770 jmp(L_fifth_loop);
9771
9772 bind(L_fifth_loop_exit);
9773 }
9774
9775
9776 /**
9777 * Code for BigInteger::squareToLen() intrinsic
9778 *
9779 * rdi: x
9780 * rsi: len
9781 * r8: z
9782 * rcx: zlen
9783 * r12: tmp1
9784 * r13: tmp2
9785 * r14: tmp3
9786 * r15: tmp4
9787 * rbx: tmp5
9788 *
9789 */
9790 void MacroAssembler::square_to_len(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
9791
9792 Label L_second_loop, L_second_loop_exit, L_third_loop, L_third_loop_exit, fifth_loop, fifth_loop_exit, L_last_x, L_multiply;
9793 push(tmp1);
9794 push(tmp2);
9795 push(tmp3);
9796 push(tmp4);
9797 push(tmp5);
9798
9799 // First loop
9800 // Store the squares, right shifted one bit (i.e., divided by 2).
9801 square_rshift(x, len, z, tmp1, tmp3, tmp4, tmp5, rdxReg, raxReg);
9802
9803 // Add in off-diagonal sums.
9804 //
9805 // Second, third (nested) and fourth loops.
9806 // zlen +=2;
9807 // for (int xidx=len-2,zidx=zlen-4; xidx > 0; xidx-=2,zidx-=4) {
9808 // carry = 0;
9809 // long op2 = x[xidx:xidx+1];
9810 // for (int j=xidx-2,k=zidx; j >= 0; j-=2) {
9811 // k -= 2;
9812 // long op1 = x[j:j+1];
9813 // long sum = z[k:k+1];
9814 // carry:sum = multiply_add_64(sum, op1, op2, carry, tmp_regs);
9815 // z[k:k+1] = sum;
9816 // }
9817 // add_one_64(z, k, carry, tmp_regs);
9818 // }
9819
9820 const Register carry = tmp5;
9821 const Register sum = tmp3;
9822 const Register op1 = tmp4;
9823 Register op2 = tmp2;
9824
9825 push(zlen);
9826 push(len);
9827 addl(zlen,2);
9828 bind(L_second_loop);
9829 xorq(carry, carry);
9830 subl(zlen, 4);
9831 subl(len, 2);
9832 push(zlen);
9833 push(len);
9834 cmpl(len, 0);
9835 jccb(Assembler::lessEqual, L_second_loop_exit);
9836
9837 // Multiply an array by one 64 bit long.
9838 if (UseBMI2Instructions) {
9839 op2 = rdxReg;
9840 movq(op2, Address(x, len, Address::times_4, 0));
9841 rorxq(op2, op2, 32);
9842 }
9843 else {
9844 movq(op2, Address(x, len, Address::times_4, 0));
9845 rorq(op2, 32);
9846 }
9847
9848 bind(L_third_loop);
9849 decrementl(len);
9850 jccb(Assembler::negative, L_third_loop_exit);
9851 decrementl(len);
9852 jccb(Assembler::negative, L_last_x);
9853
9854 movq(op1, Address(x, len, Address::times_4, 0));
9855 rorq(op1, 32);
9856
9857 bind(L_multiply);
9858 subl(zlen, 2);
9859 movq(sum, Address(z, zlen, Address::times_4, 0));
9860
9861 // Multiply 64 bit by 64 bit and add 64 bits lower half and upper 64 bits as carry.
9862 if (UseBMI2Instructions) {
9863 multiply_add_64_bmi2(sum, op1, op2, carry, tmp2);
9864 }
9865 else {
9866 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
9867 }
9868
9869 movq(Address(z, zlen, Address::times_4, 0), sum);
9870
9871 jmp(L_third_loop);
9872 bind(L_third_loop_exit);
9873
9874 // Fourth loop
9875 // Add 64 bit long carry into z with carry propogation.
9876 // Uses offsetted zlen.
9877 add_one_64(z, zlen, carry, tmp1);
9878
9879 pop(len);
9880 pop(zlen);
9881 jmp(L_second_loop);
9882
9883 // Next infrequent code is moved outside loops.
9884 bind(L_last_x);
9885 movl(op1, Address(x, 0));
9886 jmp(L_multiply);
9887
9888 bind(L_second_loop_exit);
9889 pop(len);
9890 pop(zlen);
9891 pop(len);
9892 pop(zlen);
9893
9894 // Fifth loop
9895 // Shift z left 1 bit.
9896 lshift_by_1(x, len, z, zlen, tmp1, tmp2, tmp3, tmp4);
9897
9898 // z[zlen-1] |= x[len-1] & 1;
9899 movl(tmp3, Address(x, len, Address::times_4, -4));
9900 andl(tmp3, 1);
9901 orl(Address(z, zlen, Address::times_4, -4), tmp3);
9902
9903 pop(tmp5);
9904 pop(tmp4);
9905 pop(tmp3);
9906 pop(tmp2);
9907 pop(tmp1);
9908 }
9909
9910 /**
9911 * Helper function for mul_add()
9912 * Multiply the in[] by int k and add to out[] starting at offset offs using
9913 * 128 bit by 32 bit multiply and return the carry in tmp5.
9914 * Only quad int aligned length of in[] is operated on in this function.
9915 * k is in rdxReg for BMI2Instructions, for others it is in tmp2.
9916 * This function preserves out, in and k registers.
9917 * len and offset point to the appropriate index in "in" & "out" correspondingly
9918 * tmp5 has the carry.
9919 * other registers are temporary and are modified.
9920 *
9921 */
9922 void MacroAssembler::mul_add_128_x_32_loop(Register out, Register in,
9923 Register offset, Register len, Register tmp1, Register tmp2, Register tmp3,
9924 Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
9925
9926 Label L_first_loop, L_first_loop_exit;
9927
9928 movl(tmp1, len);
9929 shrl(tmp1, 2);
9930
9931 bind(L_first_loop);
9932 subl(tmp1, 1);
9933 jccb(Assembler::negative, L_first_loop_exit);
9934
9935 subl(len, 4);
9936 subl(offset, 4);
9937
9938 Register op2 = tmp2;
9939 const Register sum = tmp3;
9940 const Register op1 = tmp4;
9941 const Register carry = tmp5;
9942
9943 if (UseBMI2Instructions) {
9944 op2 = rdxReg;
9945 }
9946
9947 movq(op1, Address(in, len, Address::times_4, 8));
9948 rorq(op1, 32);
9949 movq(sum, Address(out, offset, Address::times_4, 8));
9950 rorq(sum, 32);
9951 if (UseBMI2Instructions) {
9952 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
9953 }
9954 else {
9955 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
9956 }
9957 // Store back in big endian from little endian
9958 rorq(sum, 0x20);
9959 movq(Address(out, offset, Address::times_4, 8), sum);
9960
9961 movq(op1, Address(in, len, Address::times_4, 0));
9962 rorq(op1, 32);
9963 movq(sum, Address(out, offset, Address::times_4, 0));
9964 rorq(sum, 32);
9965 if (UseBMI2Instructions) {
9966 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
9967 }
9968 else {
9969 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
9970 }
9971 // Store back in big endian from little endian
9972 rorq(sum, 0x20);
9973 movq(Address(out, offset, Address::times_4, 0), sum);
9974
9975 jmp(L_first_loop);
9976 bind(L_first_loop_exit);
9977 }
9978
9979 /**
9980 * Code for BigInteger::mulAdd() intrinsic
9981 *
9982 * rdi: out
9983 * rsi: in
9984 * r11: offs (out.length - offset)
9985 * rcx: len
9986 * r8: k
9987 * r12: tmp1
9988 * r13: tmp2
9989 * r14: tmp3
9990 * r15: tmp4
9991 * rbx: tmp5
9992 * Multiply the in[] by word k and add to out[], return the carry in rax
9993 */
9994 void MacroAssembler::mul_add(Register out, Register in, Register offs,
9995 Register len, Register k, Register tmp1, Register tmp2, Register tmp3,
9996 Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
9997
9998 Label L_carry, L_last_in, L_done;
9999
10000 // carry = 0;
10001 // for (int j=len-1; j >= 0; j--) {
10002 // long product = (in[j] & LONG_MASK) * kLong +
10003 // (out[offs] & LONG_MASK) + carry;
10004 // out[offs--] = (int)product;
10005 // carry = product >>> 32;
10006 // }
10007 //
10008 push(tmp1);
10009 push(tmp2);
10010 push(tmp3);
10011 push(tmp4);
10012 push(tmp5);
10013
10014 Register op2 = tmp2;
10015 const Register sum = tmp3;
10016 const Register op1 = tmp4;
10017 const Register carry = tmp5;
10018
10019 if (UseBMI2Instructions) {
10020 op2 = rdxReg;
10021 movl(op2, k);
10022 }
10023 else {
10024 movl(op2, k);
10025 }
10026
10027 xorq(carry, carry);
10028
10029 //First loop
10030
10031 //Multiply in[] by k in a 4 way unrolled loop using 128 bit by 32 bit multiply
10032 //The carry is in tmp5
10033 mul_add_128_x_32_loop(out, in, offs, len, tmp1, tmp2, tmp3, tmp4, tmp5, rdxReg, raxReg);
10034
10035 //Multiply the trailing in[] entry using 64 bit by 32 bit, if any
10036 decrementl(len);
10037 jccb(Assembler::negative, L_carry);
10038 decrementl(len);
10039 jccb(Assembler::negative, L_last_in);
10040
10041 movq(op1, Address(in, len, Address::times_4, 0));
10042 rorq(op1, 32);
10043
10044 subl(offs, 2);
10045 movq(sum, Address(out, offs, Address::times_4, 0));
10046 rorq(sum, 32);
10047
10048 if (UseBMI2Instructions) {
10049 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
10050 }
10051 else {
10052 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
10053 }
10054
10055 // Store back in big endian from little endian
10056 rorq(sum, 0x20);
10057 movq(Address(out, offs, Address::times_4, 0), sum);
10058
10059 testl(len, len);
10060 jccb(Assembler::zero, L_carry);
10061
10062 //Multiply the last in[] entry, if any
10063 bind(L_last_in);
10064 movl(op1, Address(in, 0));
10065 movl(sum, Address(out, offs, Address::times_4, -4));
10066
10067 movl(raxReg, k);
10068 mull(op1); //tmp4 * eax -> edx:eax
10069 addl(sum, carry);
10070 adcl(rdxReg, 0);
10071 addl(sum, raxReg);
10072 adcl(rdxReg, 0);
10073 movl(carry, rdxReg);
10074
10075 movl(Address(out, offs, Address::times_4, -4), sum);
10076
10077 bind(L_carry);
10078 //return tmp5/carry as carry in rax
10079 movl(rax, carry);
10080
10081 bind(L_done);
10082 pop(tmp5);
10083 pop(tmp4);
10084 pop(tmp3);
10085 pop(tmp2);
10086 pop(tmp1);
10087 }
10088 #endif
10089
10090 /**
10091 * Emits code to update CRC-32 with a byte value according to constants in table
10092 *
10093 * @param [in,out]crc Register containing the crc.
10094 * @param [in]val Register containing the byte to fold into the CRC.
10095 * @param [in]table Register containing the table of crc constants.
10096 *
10097 * uint32_t crc;
10098 * val = crc_table[(val ^ crc) & 0xFF];
10099 * crc = val ^ (crc >> 8);
10100 *
10101 */
10102 void MacroAssembler::update_byte_crc32(Register crc, Register val, Register table) {
10103 xorl(val, crc);
10104 andl(val, 0xFF);
10105 shrl(crc, 8); // unsigned shift
10106 xorl(crc, Address(table, val, Address::times_4, 0));
10107 }
10108
10109 /**
10110 * Fold 128-bit data chunk
10111 */
10112 void MacroAssembler::fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, int offset) {
10113 if (UseAVX > 0) {
10114 vpclmulhdq(xtmp, xK, xcrc); // [123:64]
10115 vpclmulldq(xcrc, xK, xcrc); // [63:0]
10116 vpxor(xcrc, xcrc, Address(buf, offset), 0 /* vector_len */);
10117 pxor(xcrc, xtmp);
10118 } else {
10119 movdqa(xtmp, xcrc);
10120 pclmulhdq(xtmp, xK); // [123:64]
10121 pclmulldq(xcrc, xK); // [63:0]
10122 pxor(xcrc, xtmp);
10123 movdqu(xtmp, Address(buf, offset));
10124 pxor(xcrc, xtmp);
10125 }
10126 }
10127
10128 void MacroAssembler::fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, XMMRegister xbuf) {
10129 if (UseAVX > 0) {
10130 vpclmulhdq(xtmp, xK, xcrc);
10131 vpclmulldq(xcrc, xK, xcrc);
10132 pxor(xcrc, xbuf);
10133 pxor(xcrc, xtmp);
10134 } else {
10135 movdqa(xtmp, xcrc);
10136 pclmulhdq(xtmp, xK);
10137 pclmulldq(xcrc, xK);
10138 pxor(xcrc, xbuf);
10139 pxor(xcrc, xtmp);
10140 }
10141 }
10142
10143 /**
10144 * 8-bit folds to compute 32-bit CRC
10145 *
10146 * uint64_t xcrc;
10147 * timesXtoThe32[xcrc & 0xFF] ^ (xcrc >> 8);
10148 */
10149 void MacroAssembler::fold_8bit_crc32(XMMRegister xcrc, Register table, XMMRegister xtmp, Register tmp) {
10150 movdl(tmp, xcrc);
10151 andl(tmp, 0xFF);
10152 movdl(xtmp, Address(table, tmp, Address::times_4, 0));
10153 psrldq(xcrc, 1); // unsigned shift one byte
10154 pxor(xcrc, xtmp);
10155 }
10156
10157 /**
10158 * uint32_t crc;
10159 * timesXtoThe32[crc & 0xFF] ^ (crc >> 8);
10160 */
10161 void MacroAssembler::fold_8bit_crc32(Register crc, Register table, Register tmp) {
10162 movl(tmp, crc);
10163 andl(tmp, 0xFF);
10164 shrl(crc, 8);
10165 xorl(crc, Address(table, tmp, Address::times_4, 0));
10166 }
10167
10168 /**
10169 * @param crc register containing existing CRC (32-bit)
10170 * @param buf register pointing to input byte buffer (byte*)
10171 * @param len register containing number of bytes
10172 * @param table register that will contain address of CRC table
10173 * @param tmp scratch register
10174 */
10175 void MacroAssembler::kernel_crc32(Register crc, Register buf, Register len, Register table, Register tmp) {
10176 assert_different_registers(crc, buf, len, table, tmp, rax);
10177
10178 Label L_tail, L_tail_restore, L_tail_loop, L_exit, L_align_loop, L_aligned;
10179 Label L_fold_tail, L_fold_128b, L_fold_512b, L_fold_512b_loop, L_fold_tail_loop;
10180
10181 // For EVEX with VL and BW, provide a standard mask, VL = 128 will guide the merge
10182 // context for the registers used, where all instructions below are using 128-bit mode
10183 // On EVEX without VL and BW, these instructions will all be AVX.
10184 if (VM_Version::supports_avx512vlbw()) {
10185 movl(tmp, 0xffff);
10186 kmovwl(k1, tmp);
10187 }
10188
10189 lea(table, ExternalAddress(StubRoutines::crc_table_addr()));
10190 notl(crc); // ~crc
10191 cmpl(len, 16);
10192 jcc(Assembler::less, L_tail);
10193
10194 // Align buffer to 16 bytes
10195 movl(tmp, buf);
10196 andl(tmp, 0xF);
10197 jccb(Assembler::zero, L_aligned);
10198 subl(tmp, 16);
10199 addl(len, tmp);
10200
10201 align(4);
10202 BIND(L_align_loop);
10203 movsbl(rax, Address(buf, 0)); // load byte with sign extension
10204 update_byte_crc32(crc, rax, table);
10205 increment(buf);
10206 incrementl(tmp);
10207 jccb(Assembler::less, L_align_loop);
10208
10209 BIND(L_aligned);
10210 movl(tmp, len); // save
10211 shrl(len, 4);
10212 jcc(Assembler::zero, L_tail_restore);
10213
10214 // Fold crc into first bytes of vector
10215 movdqa(xmm1, Address(buf, 0));
10216 movdl(rax, xmm1);
10217 xorl(crc, rax);
10218 if (VM_Version::supports_sse4_1()) {
10219 pinsrd(xmm1, crc, 0);
10220 } else {
10221 pinsrw(xmm1, crc, 0);
10222 shrl(crc, 16);
10223 pinsrw(xmm1, crc, 1);
10224 }
10225 addptr(buf, 16);
10226 subl(len, 4); // len > 0
10227 jcc(Assembler::less, L_fold_tail);
10228
10229 movdqa(xmm2, Address(buf, 0));
10230 movdqa(xmm3, Address(buf, 16));
10231 movdqa(xmm4, Address(buf, 32));
10232 addptr(buf, 48);
10233 subl(len, 3);
10234 jcc(Assembler::lessEqual, L_fold_512b);
10235
10236 // Fold total 512 bits of polynomial on each iteration,
10237 // 128 bits per each of 4 parallel streams.
10238 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 32));
10239
10240 align(32);
10241 BIND(L_fold_512b_loop);
10242 fold_128bit_crc32(xmm1, xmm0, xmm5, buf, 0);
10243 fold_128bit_crc32(xmm2, xmm0, xmm5, buf, 16);
10244 fold_128bit_crc32(xmm3, xmm0, xmm5, buf, 32);
10245 fold_128bit_crc32(xmm4, xmm0, xmm5, buf, 48);
10246 addptr(buf, 64);
10247 subl(len, 4);
10248 jcc(Assembler::greater, L_fold_512b_loop);
10249
10250 // Fold 512 bits to 128 bits.
10251 BIND(L_fold_512b);
10252 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 16));
10253 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm2);
10254 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm3);
10255 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm4);
10256
10257 // Fold the rest of 128 bits data chunks
10258 BIND(L_fold_tail);
10259 addl(len, 3);
10260 jccb(Assembler::lessEqual, L_fold_128b);
10261 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 16));
10262
10263 BIND(L_fold_tail_loop);
10264 fold_128bit_crc32(xmm1, xmm0, xmm5, buf, 0);
10265 addptr(buf, 16);
10266 decrementl(len);
10267 jccb(Assembler::greater, L_fold_tail_loop);
10268
10269 // Fold 128 bits in xmm1 down into 32 bits in crc register.
10270 BIND(L_fold_128b);
10271 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr()));
10272 if (UseAVX > 0) {
10273 vpclmulqdq(xmm2, xmm0, xmm1, 0x1);
10274 vpand(xmm3, xmm0, xmm2, 0 /* vector_len */);
10275 vpclmulqdq(xmm0, xmm0, xmm3, 0x1);
10276 } else {
10277 movdqa(xmm2, xmm0);
10278 pclmulqdq(xmm2, xmm1, 0x1);
10279 movdqa(xmm3, xmm0);
10280 pand(xmm3, xmm2);
10281 pclmulqdq(xmm0, xmm3, 0x1);
10282 }
10283 psrldq(xmm1, 8);
10284 psrldq(xmm2, 4);
10285 pxor(xmm0, xmm1);
10286 pxor(xmm0, xmm2);
10287
10288 // 8 8-bit folds to compute 32-bit CRC.
10289 for (int j = 0; j < 4; j++) {
10290 fold_8bit_crc32(xmm0, table, xmm1, rax);
10291 }
10292 movdl(crc, xmm0); // mov 32 bits to general register
10293 for (int j = 0; j < 4; j++) {
10294 fold_8bit_crc32(crc, table, rax);
10295 }
10296
10297 BIND(L_tail_restore);
10298 movl(len, tmp); // restore
10299 BIND(L_tail);
10300 andl(len, 0xf);
10301 jccb(Assembler::zero, L_exit);
10302
10303 // Fold the rest of bytes
10304 align(4);
10305 BIND(L_tail_loop);
10306 movsbl(rax, Address(buf, 0)); // load byte with sign extension
10307 update_byte_crc32(crc, rax, table);
10308 increment(buf);
10309 decrementl(len);
10310 jccb(Assembler::greater, L_tail_loop);
10311
10312 BIND(L_exit);
10313 notl(crc); // ~c
10314 }
10315
10316 #ifdef _LP64
10317 // S. Gueron / Information Processing Letters 112 (2012) 184
10318 // Algorithm 4: Computing carry-less multiplication using a precomputed lookup table.
10319 // Input: A 32 bit value B = [byte3, byte2, byte1, byte0].
10320 // Output: the 64-bit carry-less product of B * CONST
10321 void MacroAssembler::crc32c_ipl_alg4(Register in, uint32_t n,
10322 Register tmp1, Register tmp2, Register tmp3) {
10323 lea(tmp3, ExternalAddress(StubRoutines::crc32c_table_addr()));
10324 if (n > 0) {
10325 addq(tmp3, n * 256 * 8);
10326 }
10327 // Q1 = TABLEExt[n][B & 0xFF];
10328 movl(tmp1, in);
10329 andl(tmp1, 0x000000FF);
10330 shll(tmp1, 3);
10331 addq(tmp1, tmp3);
10332 movq(tmp1, Address(tmp1, 0));
10333
10334 // Q2 = TABLEExt[n][B >> 8 & 0xFF];
10335 movl(tmp2, in);
10336 shrl(tmp2, 8);
10337 andl(tmp2, 0x000000FF);
10338 shll(tmp2, 3);
10339 addq(tmp2, tmp3);
10340 movq(tmp2, Address(tmp2, 0));
10341
10342 shlq(tmp2, 8);
10343 xorq(tmp1, tmp2);
10344
10345 // Q3 = TABLEExt[n][B >> 16 & 0xFF];
10346 movl(tmp2, in);
10347 shrl(tmp2, 16);
10348 andl(tmp2, 0x000000FF);
10349 shll(tmp2, 3);
10350 addq(tmp2, tmp3);
10351 movq(tmp2, Address(tmp2, 0));
10352
10353 shlq(tmp2, 16);
10354 xorq(tmp1, tmp2);
10355
10356 // Q4 = TABLEExt[n][B >> 24 & 0xFF];
10357 shrl(in, 24);
10358 andl(in, 0x000000FF);
10359 shll(in, 3);
10360 addq(in, tmp3);
10361 movq(in, Address(in, 0));
10362
10363 shlq(in, 24);
10364 xorq(in, tmp1);
10365 // return Q1 ^ Q2 << 8 ^ Q3 << 16 ^ Q4 << 24;
10366 }
10367
10368 void MacroAssembler::crc32c_pclmulqdq(XMMRegister w_xtmp1,
10369 Register in_out,
10370 uint32_t const_or_pre_comp_const_index, bool is_pclmulqdq_supported,
10371 XMMRegister w_xtmp2,
10372 Register tmp1,
10373 Register n_tmp2, Register n_tmp3) {
10374 if (is_pclmulqdq_supported) {
10375 movdl(w_xtmp1, in_out); // modified blindly
10376
10377 movl(tmp1, const_or_pre_comp_const_index);
10378 movdl(w_xtmp2, tmp1);
10379 pclmulqdq(w_xtmp1, w_xtmp2, 0);
10380
10381 movdq(in_out, w_xtmp1);
10382 } else {
10383 crc32c_ipl_alg4(in_out, const_or_pre_comp_const_index, tmp1, n_tmp2, n_tmp3);
10384 }
10385 }
10386
10387 // Recombination Alternative 2: No bit-reflections
10388 // T1 = (CRC_A * U1) << 1
10389 // T2 = (CRC_B * U2) << 1
10390 // C1 = T1 >> 32
10391 // C2 = T2 >> 32
10392 // T1 = T1 & 0xFFFFFFFF
10393 // T2 = T2 & 0xFFFFFFFF
10394 // T1 = CRC32(0, T1)
10395 // T2 = CRC32(0, T2)
10396 // C1 = C1 ^ T1
10397 // C2 = C2 ^ T2
10398 // CRC = C1 ^ C2 ^ CRC_C
10399 void MacroAssembler::crc32c_rec_alt2(uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, Register in_out, Register in1, Register in2,
10400 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
10401 Register tmp1, Register tmp2,
10402 Register n_tmp3) {
10403 crc32c_pclmulqdq(w_xtmp1, in_out, const_or_pre_comp_const_index_u1, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
10404 crc32c_pclmulqdq(w_xtmp2, in1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
10405 shlq(in_out, 1);
10406 movl(tmp1, in_out);
10407 shrq(in_out, 32);
10408 xorl(tmp2, tmp2);
10409 crc32(tmp2, tmp1, 4);
10410 xorl(in_out, tmp2); // we don't care about upper 32 bit contents here
10411 shlq(in1, 1);
10412 movl(tmp1, in1);
10413 shrq(in1, 32);
10414 xorl(tmp2, tmp2);
10415 crc32(tmp2, tmp1, 4);
10416 xorl(in1, tmp2);
10417 xorl(in_out, in1);
10418 xorl(in_out, in2);
10419 }
10420
10421 // Set N to predefined value
10422 // Subtract from a lenght of a buffer
10423 // execute in a loop:
10424 // CRC_A = 0xFFFFFFFF, CRC_B = 0, CRC_C = 0
10425 // for i = 1 to N do
10426 // CRC_A = CRC32(CRC_A, A[i])
10427 // CRC_B = CRC32(CRC_B, B[i])
10428 // CRC_C = CRC32(CRC_C, C[i])
10429 // end for
10430 // Recombine
10431 void MacroAssembler::crc32c_proc_chunk(uint32_t size, uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported,
10432 Register in_out1, Register in_out2, Register in_out3,
10433 Register tmp1, Register tmp2, Register tmp3,
10434 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
10435 Register tmp4, Register tmp5,
10436 Register n_tmp6) {
10437 Label L_processPartitions;
10438 Label L_processPartition;
10439 Label L_exit;
10440
10441 bind(L_processPartitions);
10442 cmpl(in_out1, 3 * size);
10443 jcc(Assembler::less, L_exit);
10444 xorl(tmp1, tmp1);
10445 xorl(tmp2, tmp2);
10446 movq(tmp3, in_out2);
10447 addq(tmp3, size);
10448
10449 bind(L_processPartition);
10450 crc32(in_out3, Address(in_out2, 0), 8);
10451 crc32(tmp1, Address(in_out2, size), 8);
10452 crc32(tmp2, Address(in_out2, size * 2), 8);
10453 addq(in_out2, 8);
10454 cmpq(in_out2, tmp3);
10455 jcc(Assembler::less, L_processPartition);
10456 crc32c_rec_alt2(const_or_pre_comp_const_index_u1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, in_out3, tmp1, tmp2,
10457 w_xtmp1, w_xtmp2, w_xtmp3,
10458 tmp4, tmp5,
10459 n_tmp6);
10460 addq(in_out2, 2 * size);
10461 subl(in_out1, 3 * size);
10462 jmp(L_processPartitions);
10463
10464 bind(L_exit);
10465 }
10466 #else
10467 void MacroAssembler::crc32c_ipl_alg4(Register in_out, uint32_t n,
10468 Register tmp1, Register tmp2, Register tmp3,
10469 XMMRegister xtmp1, XMMRegister xtmp2) {
10470 lea(tmp3, ExternalAddress(StubRoutines::crc32c_table_addr()));
10471 if (n > 0) {
10472 addl(tmp3, n * 256 * 8);
10473 }
10474 // Q1 = TABLEExt[n][B & 0xFF];
10475 movl(tmp1, in_out);
10476 andl(tmp1, 0x000000FF);
10477 shll(tmp1, 3);
10478 addl(tmp1, tmp3);
10479 movq(xtmp1, Address(tmp1, 0));
10480
10481 // Q2 = TABLEExt[n][B >> 8 & 0xFF];
10482 movl(tmp2, in_out);
10483 shrl(tmp2, 8);
10484 andl(tmp2, 0x000000FF);
10485 shll(tmp2, 3);
10486 addl(tmp2, tmp3);
10487 movq(xtmp2, Address(tmp2, 0));
10488
10489 psllq(xtmp2, 8);
10490 pxor(xtmp1, xtmp2);
10491
10492 // Q3 = TABLEExt[n][B >> 16 & 0xFF];
10493 movl(tmp2, in_out);
10494 shrl(tmp2, 16);
10495 andl(tmp2, 0x000000FF);
10496 shll(tmp2, 3);
10497 addl(tmp2, tmp3);
10498 movq(xtmp2, Address(tmp2, 0));
10499
10500 psllq(xtmp2, 16);
10501 pxor(xtmp1, xtmp2);
10502
10503 // Q4 = TABLEExt[n][B >> 24 & 0xFF];
10504 shrl(in_out, 24);
10505 andl(in_out, 0x000000FF);
10506 shll(in_out, 3);
10507 addl(in_out, tmp3);
10508 movq(xtmp2, Address(in_out, 0));
10509
10510 psllq(xtmp2, 24);
10511 pxor(xtmp1, xtmp2); // Result in CXMM
10512 // return Q1 ^ Q2 << 8 ^ Q3 << 16 ^ Q4 << 24;
10513 }
10514
10515 void MacroAssembler::crc32c_pclmulqdq(XMMRegister w_xtmp1,
10516 Register in_out,
10517 uint32_t const_or_pre_comp_const_index, bool is_pclmulqdq_supported,
10518 XMMRegister w_xtmp2,
10519 Register tmp1,
10520 Register n_tmp2, Register n_tmp3) {
10521 if (is_pclmulqdq_supported) {
10522 movdl(w_xtmp1, in_out);
10523
10524 movl(tmp1, const_or_pre_comp_const_index);
10525 movdl(w_xtmp2, tmp1);
10526 pclmulqdq(w_xtmp1, w_xtmp2, 0);
10527 // Keep result in XMM since GPR is 32 bit in length
10528 } else {
10529 crc32c_ipl_alg4(in_out, const_or_pre_comp_const_index, tmp1, n_tmp2, n_tmp3, w_xtmp1, w_xtmp2);
10530 }
10531 }
10532
10533 void MacroAssembler::crc32c_rec_alt2(uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, Register in_out, Register in1, Register in2,
10534 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
10535 Register tmp1, Register tmp2,
10536 Register n_tmp3) {
10537 crc32c_pclmulqdq(w_xtmp1, in_out, const_or_pre_comp_const_index_u1, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
10538 crc32c_pclmulqdq(w_xtmp2, in1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
10539
10540 psllq(w_xtmp1, 1);
10541 movdl(tmp1, w_xtmp1);
10542 psrlq(w_xtmp1, 32);
10543 movdl(in_out, w_xtmp1);
10544
10545 xorl(tmp2, tmp2);
10546 crc32(tmp2, tmp1, 4);
10547 xorl(in_out, tmp2);
10548
10549 psllq(w_xtmp2, 1);
10550 movdl(tmp1, w_xtmp2);
10551 psrlq(w_xtmp2, 32);
10552 movdl(in1, w_xtmp2);
10553
10554 xorl(tmp2, tmp2);
10555 crc32(tmp2, tmp1, 4);
10556 xorl(in1, tmp2);
10557 xorl(in_out, in1);
10558 xorl(in_out, in2);
10559 }
10560
10561 void MacroAssembler::crc32c_proc_chunk(uint32_t size, uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported,
10562 Register in_out1, Register in_out2, Register in_out3,
10563 Register tmp1, Register tmp2, Register tmp3,
10564 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
10565 Register tmp4, Register tmp5,
10566 Register n_tmp6) {
10567 Label L_processPartitions;
10568 Label L_processPartition;
10569 Label L_exit;
10570
10571 bind(L_processPartitions);
10572 cmpl(in_out1, 3 * size);
10573 jcc(Assembler::less, L_exit);
10574 xorl(tmp1, tmp1);
10575 xorl(tmp2, tmp2);
10576 movl(tmp3, in_out2);
10577 addl(tmp3, size);
10578
10579 bind(L_processPartition);
10580 crc32(in_out3, Address(in_out2, 0), 4);
10581 crc32(tmp1, Address(in_out2, size), 4);
10582 crc32(tmp2, Address(in_out2, size*2), 4);
10583 crc32(in_out3, Address(in_out2, 0+4), 4);
10584 crc32(tmp1, Address(in_out2, size+4), 4);
10585 crc32(tmp2, Address(in_out2, size*2+4), 4);
10586 addl(in_out2, 8);
10587 cmpl(in_out2, tmp3);
10588 jcc(Assembler::less, L_processPartition);
10589
10590 push(tmp3);
10591 push(in_out1);
10592 push(in_out2);
10593 tmp4 = tmp3;
10594 tmp5 = in_out1;
10595 n_tmp6 = in_out2;
10596
10597 crc32c_rec_alt2(const_or_pre_comp_const_index_u1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, in_out3, tmp1, tmp2,
10598 w_xtmp1, w_xtmp2, w_xtmp3,
10599 tmp4, tmp5,
10600 n_tmp6);
10601
10602 pop(in_out2);
10603 pop(in_out1);
10604 pop(tmp3);
10605
10606 addl(in_out2, 2 * size);
10607 subl(in_out1, 3 * size);
10608 jmp(L_processPartitions);
10609
10610 bind(L_exit);
10611 }
10612 #endif //LP64
10613
10614 #ifdef _LP64
10615 // Algorithm 2: Pipelined usage of the CRC32 instruction.
10616 // Input: A buffer I of L bytes.
10617 // Output: the CRC32C value of the buffer.
10618 // Notations:
10619 // Write L = 24N + r, with N = floor (L/24).
10620 // r = L mod 24 (0 <= r < 24).
10621 // Consider I as the concatenation of A|B|C|R, where A, B, C, each,
10622 // N quadwords, and R consists of r bytes.
10623 // A[j] = I [8j+7:8j], j= 0, 1, ..., N-1
10624 // B[j] = I [N + 8j+7:N + 8j], j= 0, 1, ..., N-1
10625 // C[j] = I [2N + 8j+7:2N + 8j], j= 0, 1, ..., N-1
10626 // if r > 0 R[j] = I [3N +j], j= 0, 1, ...,r-1
10627 void MacroAssembler::crc32c_ipl_alg2_alt2(Register in_out, Register in1, Register in2,
10628 Register tmp1, Register tmp2, Register tmp3,
10629 Register tmp4, Register tmp5, Register tmp6,
10630 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
10631 bool is_pclmulqdq_supported) {
10632 uint32_t const_or_pre_comp_const_index[CRC32C_NUM_PRECOMPUTED_CONSTANTS];
10633 Label L_wordByWord;
10634 Label L_byteByByteProlog;
10635 Label L_byteByByte;
10636 Label L_exit;
10637
10638 if (is_pclmulqdq_supported ) {
10639 const_or_pre_comp_const_index[1] = *(uint32_t *)StubRoutines::_crc32c_table_addr;
10640 const_or_pre_comp_const_index[0] = *((uint32_t *)StubRoutines::_crc32c_table_addr+1);
10641
10642 const_or_pre_comp_const_index[3] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 2);
10643 const_or_pre_comp_const_index[2] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 3);
10644
10645 const_or_pre_comp_const_index[5] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 4);
10646 const_or_pre_comp_const_index[4] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 5);
10647 assert((CRC32C_NUM_PRECOMPUTED_CONSTANTS - 1 ) == 5, "Checking whether you declared all of the constants based on the number of \"chunks\"");
10648 } else {
10649 const_or_pre_comp_const_index[0] = 1;
10650 const_or_pre_comp_const_index[1] = 0;
10651
10652 const_or_pre_comp_const_index[2] = 3;
10653 const_or_pre_comp_const_index[3] = 2;
10654
10655 const_or_pre_comp_const_index[4] = 5;
10656 const_or_pre_comp_const_index[5] = 4;
10657 }
10658 crc32c_proc_chunk(CRC32C_HIGH, const_or_pre_comp_const_index[0], const_or_pre_comp_const_index[1], is_pclmulqdq_supported,
10659 in2, in1, in_out,
10660 tmp1, tmp2, tmp3,
10661 w_xtmp1, w_xtmp2, w_xtmp3,
10662 tmp4, tmp5,
10663 tmp6);
10664 crc32c_proc_chunk(CRC32C_MIDDLE, const_or_pre_comp_const_index[2], const_or_pre_comp_const_index[3], is_pclmulqdq_supported,
10665 in2, in1, in_out,
10666 tmp1, tmp2, tmp3,
10667 w_xtmp1, w_xtmp2, w_xtmp3,
10668 tmp4, tmp5,
10669 tmp6);
10670 crc32c_proc_chunk(CRC32C_LOW, const_or_pre_comp_const_index[4], const_or_pre_comp_const_index[5], is_pclmulqdq_supported,
10671 in2, in1, in_out,
10672 tmp1, tmp2, tmp3,
10673 w_xtmp1, w_xtmp2, w_xtmp3,
10674 tmp4, tmp5,
10675 tmp6);
10676 movl(tmp1, in2);
10677 andl(tmp1, 0x00000007);
10678 negl(tmp1);
10679 addl(tmp1, in2);
10680 addq(tmp1, in1);
10681
10682 BIND(L_wordByWord);
10683 cmpq(in1, tmp1);
10684 jcc(Assembler::greaterEqual, L_byteByByteProlog);
10685 crc32(in_out, Address(in1, 0), 4);
10686 addq(in1, 4);
10687 jmp(L_wordByWord);
10688
10689 BIND(L_byteByByteProlog);
10690 andl(in2, 0x00000007);
10691 movl(tmp2, 1);
10692
10693 BIND(L_byteByByte);
10694 cmpl(tmp2, in2);
10695 jccb(Assembler::greater, L_exit);
10696 crc32(in_out, Address(in1, 0), 1);
10697 incq(in1);
10698 incl(tmp2);
10699 jmp(L_byteByByte);
10700
10701 BIND(L_exit);
10702 }
10703 #else
10704 void MacroAssembler::crc32c_ipl_alg2_alt2(Register in_out, Register in1, Register in2,
10705 Register tmp1, Register tmp2, Register tmp3,
10706 Register tmp4, Register tmp5, Register tmp6,
10707 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
10708 bool is_pclmulqdq_supported) {
10709 uint32_t const_or_pre_comp_const_index[CRC32C_NUM_PRECOMPUTED_CONSTANTS];
10710 Label L_wordByWord;
10711 Label L_byteByByteProlog;
10712 Label L_byteByByte;
10713 Label L_exit;
10714
10715 if (is_pclmulqdq_supported) {
10716 const_or_pre_comp_const_index[1] = *(uint32_t *)StubRoutines::_crc32c_table_addr;
10717 const_or_pre_comp_const_index[0] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 1);
10718
10719 const_or_pre_comp_const_index[3] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 2);
10720 const_or_pre_comp_const_index[2] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 3);
10721
10722 const_or_pre_comp_const_index[5] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 4);
10723 const_or_pre_comp_const_index[4] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 5);
10724 } else {
10725 const_or_pre_comp_const_index[0] = 1;
10726 const_or_pre_comp_const_index[1] = 0;
10727
10728 const_or_pre_comp_const_index[2] = 3;
10729 const_or_pre_comp_const_index[3] = 2;
10730
10731 const_or_pre_comp_const_index[4] = 5;
10732 const_or_pre_comp_const_index[5] = 4;
10733 }
10734 crc32c_proc_chunk(CRC32C_HIGH, const_or_pre_comp_const_index[0], const_or_pre_comp_const_index[1], is_pclmulqdq_supported,
10735 in2, in1, in_out,
10736 tmp1, tmp2, tmp3,
10737 w_xtmp1, w_xtmp2, w_xtmp3,
10738 tmp4, tmp5,
10739 tmp6);
10740 crc32c_proc_chunk(CRC32C_MIDDLE, const_or_pre_comp_const_index[2], const_or_pre_comp_const_index[3], is_pclmulqdq_supported,
10741 in2, in1, in_out,
10742 tmp1, tmp2, tmp3,
10743 w_xtmp1, w_xtmp2, w_xtmp3,
10744 tmp4, tmp5,
10745 tmp6);
10746 crc32c_proc_chunk(CRC32C_LOW, const_or_pre_comp_const_index[4], const_or_pre_comp_const_index[5], is_pclmulqdq_supported,
10747 in2, in1, in_out,
10748 tmp1, tmp2, tmp3,
10749 w_xtmp1, w_xtmp2, w_xtmp3,
10750 tmp4, tmp5,
10751 tmp6);
10752 movl(tmp1, in2);
10753 andl(tmp1, 0x00000007);
10754 negl(tmp1);
10755 addl(tmp1, in2);
10756 addl(tmp1, in1);
10757
10758 BIND(L_wordByWord);
10759 cmpl(in1, tmp1);
10760 jcc(Assembler::greaterEqual, L_byteByByteProlog);
10761 crc32(in_out, Address(in1,0), 4);
10762 addl(in1, 4);
10763 jmp(L_wordByWord);
10764
10765 BIND(L_byteByByteProlog);
10766 andl(in2, 0x00000007);
10767 movl(tmp2, 1);
10768
10769 BIND(L_byteByByte);
10770 cmpl(tmp2, in2);
10771 jccb(Assembler::greater, L_exit);
10772 movb(tmp1, Address(in1, 0));
10773 crc32(in_out, tmp1, 1);
10774 incl(in1);
10775 incl(tmp2);
10776 jmp(L_byteByByte);
10777
10778 BIND(L_exit);
10779 }
10780 #endif // LP64
10781 #undef BIND
10782 #undef BLOCK_COMMENT
10783
10784 // Compress char[] array to byte[].
10785 // ..\jdk\src\java.base\share\classes\java\lang\StringUTF16.java
10786 // @HotSpotIntrinsicCandidate
10787 // private static int compress(char[] src, int srcOff, byte[] dst, int dstOff, int len) {
10788 // for (int i = 0; i < len; i++) {
10789 // int c = src[srcOff++];
10790 // if (c >>> 8 != 0) {
10791 // return 0;
10792 // }
10793 // dst[dstOff++] = (byte)c;
10794 // }
10795 // return len;
10796 // }
10797 void MacroAssembler::char_array_compress(Register src, Register dst, Register len,
10798 XMMRegister tmp1Reg, XMMRegister tmp2Reg,
10799 XMMRegister tmp3Reg, XMMRegister tmp4Reg,
10800 Register tmp5, Register result) {
10801 Label copy_chars_loop, return_length, return_zero, done, below_threshold;
10802
10803 // rsi: src
10804 // rdi: dst
10805 // rdx: len
10806 // rcx: tmp5
10807 // rax: result
10808
10809 // rsi holds start addr of source char[] to be compressed
10810 // rdi holds start addr of destination byte[]
10811 // rdx holds length
10812
10813 assert(len != result, "");
10814
10815 // save length for return
10816 push(len);
10817
10818 if ((UseAVX > 2) && // AVX512
10819 VM_Version::supports_avx512vlbw() &&
10820 VM_Version::supports_bmi2()) {
10821
10822 set_vector_masking(); // opening of the stub context for programming mask registers
10823
10824 Label copy_32_loop, copy_loop_tail, restore_k1_return_zero;
10825
10826 // alignement
10827 Label post_alignement;
10828
10829 // if length of the string is less than 16, handle it in an old fashioned
10830 // way
10831 testl(len, -32);
10832 jcc(Assembler::zero, below_threshold);
10833
10834 // First check whether a character is compressable ( <= 0xFF).
10835 // Create mask to test for Unicode chars inside zmm vector
10836 movl(result, 0x00FF);
10837 evpbroadcastw(tmp2Reg, result, Assembler::AVX_512bit);
10838
10839 // Save k1
10840 kmovql(k3, k1);
10841
10842 testl(len, -64);
10843 jcc(Assembler::zero, post_alignement);
10844
10845 movl(tmp5, dst);
10846 andl(tmp5, (32 - 1));
10847 negl(tmp5);
10848 andl(tmp5, (32 - 1));
10849
10850 // bail out when there is nothing to be done
10851 testl(tmp5, 0xFFFFFFFF);
10852 jcc(Assembler::zero, post_alignement);
10853
10854 // ~(~0 << len), where len is the # of remaining elements to process
10855 movl(result, 0xFFFFFFFF);
10856 shlxl(result, result, tmp5);
10857 notl(result);
10858 kmovdl(k1, result);
10859
10860 evmovdquw(tmp1Reg, k1, Address(src, 0), Assembler::AVX_512bit);
10861 evpcmpuw(k2, k1, tmp1Reg, tmp2Reg, Assembler::le, Assembler::AVX_512bit);
10862 ktestd(k2, k1);
10863 jcc(Assembler::carryClear, restore_k1_return_zero);
10864
10865 evpmovwb(Address(dst, 0), k1, tmp1Reg, Assembler::AVX_512bit);
10866
10867 addptr(src, tmp5);
10868 addptr(src, tmp5);
10869 addptr(dst, tmp5);
10870 subl(len, tmp5);
10871
10872 bind(post_alignement);
10873 // end of alignement
10874
10875 movl(tmp5, len);
10876 andl(tmp5, (32 - 1)); // tail count (in chars)
10877 andl(len, ~(32 - 1)); // vector count (in chars)
10878 jcc(Assembler::zero, copy_loop_tail);
10879
10880 lea(src, Address(src, len, Address::times_2));
10881 lea(dst, Address(dst, len, Address::times_1));
10882 negptr(len);
10883
10884 bind(copy_32_loop);
10885 evmovdquw(tmp1Reg, Address(src, len, Address::times_2), Assembler::AVX_512bit);
10886 evpcmpuw(k2, tmp1Reg, tmp2Reg, Assembler::le, Assembler::AVX_512bit);
10887 kortestdl(k2, k2);
10888 jcc(Assembler::carryClear, restore_k1_return_zero);
10889
10890 // All elements in current processed chunk are valid candidates for
10891 // compression. Write a truncated byte elements to the memory.
10892 evpmovwb(Address(dst, len, Address::times_1), tmp1Reg, Assembler::AVX_512bit);
10893 addptr(len, 32);
10894 jcc(Assembler::notZero, copy_32_loop);
10895
10896 bind(copy_loop_tail);
10897 // bail out when there is nothing to be done
10898 testl(tmp5, 0xFFFFFFFF);
10899 // Restore k1
10900 kmovql(k1, k3);
10901 jcc(Assembler::zero, return_length);
10902
10903 movl(len, tmp5);
10904
10905 // ~(~0 << len), where len is the # of remaining elements to process
10906 movl(result, 0xFFFFFFFF);
10907 shlxl(result, result, len);
10908 notl(result);
10909
10910 kmovdl(k1, result);
10911
10912 evmovdquw(tmp1Reg, k1, Address(src, 0), Assembler::AVX_512bit);
10913 evpcmpuw(k2, k1, tmp1Reg, tmp2Reg, Assembler::le, Assembler::AVX_512bit);
10914 ktestd(k2, k1);
10915 jcc(Assembler::carryClear, restore_k1_return_zero);
10916
10917 evpmovwb(Address(dst, 0), k1, tmp1Reg, Assembler::AVX_512bit);
10918 // Restore k1
10919 kmovql(k1, k3);
10920 jmp(return_length);
10921
10922 bind(restore_k1_return_zero);
10923 // Restore k1
10924 kmovql(k1, k3);
10925 jmp(return_zero);
10926
10927 clear_vector_masking(); // closing of the stub context for programming mask registers
10928 }
10929 if (UseSSE42Intrinsics) {
10930 Label copy_32_loop, copy_16, copy_tail;
10931
10932 bind(below_threshold);
10933
10934 movl(result, len);
10935
10936 movl(tmp5, 0xff00ff00); // create mask to test for Unicode chars in vectors
10937
10938 // vectored compression
10939 andl(len, 0xfffffff0); // vector count (in chars)
10940 andl(result, 0x0000000f); // tail count (in chars)
10941 testl(len, len);
10942 jccb(Assembler::zero, copy_16);
10943
10944 // compress 16 chars per iter
10945 movdl(tmp1Reg, tmp5);
10946 pshufd(tmp1Reg, tmp1Reg, 0); // store Unicode mask in tmp1Reg
10947 pxor(tmp4Reg, tmp4Reg);
10948
10949 lea(src, Address(src, len, Address::times_2));
10950 lea(dst, Address(dst, len, Address::times_1));
10951 negptr(len);
10952
10953 bind(copy_32_loop);
10954 movdqu(tmp2Reg, Address(src, len, Address::times_2)); // load 1st 8 characters
10955 por(tmp4Reg, tmp2Reg);
10956 movdqu(tmp3Reg, Address(src, len, Address::times_2, 16)); // load next 8 characters
10957 por(tmp4Reg, tmp3Reg);
10958 ptest(tmp4Reg, tmp1Reg); // check for Unicode chars in next vector
10959 jcc(Assembler::notZero, return_zero);
10960 packuswb(tmp2Reg, tmp3Reg); // only ASCII chars; compress each to 1 byte
10961 movdqu(Address(dst, len, Address::times_1), tmp2Reg);
10962 addptr(len, 16);
10963 jcc(Assembler::notZero, copy_32_loop);
10964
10965 // compress next vector of 8 chars (if any)
10966 bind(copy_16);
10967 movl(len, result);
10968 andl(len, 0xfffffff8); // vector count (in chars)
10969 andl(result, 0x00000007); // tail count (in chars)
10970 testl(len, len);
10971 jccb(Assembler::zero, copy_tail);
10972
10973 movdl(tmp1Reg, tmp5);
10974 pshufd(tmp1Reg, tmp1Reg, 0); // store Unicode mask in tmp1Reg
10975 pxor(tmp3Reg, tmp3Reg);
10976
10977 movdqu(tmp2Reg, Address(src, 0));
10978 ptest(tmp2Reg, tmp1Reg); // check for Unicode chars in vector
10979 jccb(Assembler::notZero, return_zero);
10980 packuswb(tmp2Reg, tmp3Reg); // only LATIN1 chars; compress each to 1 byte
10981 movq(Address(dst, 0), tmp2Reg);
10982 addptr(src, 16);
10983 addptr(dst, 8);
10984
10985 bind(copy_tail);
10986 movl(len, result);
10987 }
10988 // compress 1 char per iter
10989 testl(len, len);
10990 jccb(Assembler::zero, return_length);
10991 lea(src, Address(src, len, Address::times_2));
10992 lea(dst, Address(dst, len, Address::times_1));
10993 negptr(len);
10994
10995 bind(copy_chars_loop);
10996 load_unsigned_short(result, Address(src, len, Address::times_2));
10997 testl(result, 0xff00); // check if Unicode char
10998 jccb(Assembler::notZero, return_zero);
10999 movb(Address(dst, len, Address::times_1), result); // ASCII char; compress to 1 byte
11000 increment(len);
11001 jcc(Assembler::notZero, copy_chars_loop);
11002
11003 // if compression succeeded, return length
11004 bind(return_length);
11005 pop(result);
11006 jmpb(done);
11007
11008 // if compression failed, return 0
11009 bind(return_zero);
11010 xorl(result, result);
11011 addptr(rsp, wordSize);
11012
11013 bind(done);
11014 }
11015
11016 // Inflate byte[] array to char[].
11017 // ..\jdk\src\java.base\share\classes\java\lang\StringLatin1.java
11018 // @HotSpotIntrinsicCandidate
11019 // private static void inflate(byte[] src, int srcOff, char[] dst, int dstOff, int len) {
11020 // for (int i = 0; i < len; i++) {
11021 // dst[dstOff++] = (char)(src[srcOff++] & 0xff);
11022 // }
11023 // }
11024 void MacroAssembler::byte_array_inflate(Register src, Register dst, Register len,
11025 XMMRegister tmp1, Register tmp2) {
11026 Label copy_chars_loop, done, below_threshold;
11027 // rsi: src
11028 // rdi: dst
11029 // rdx: len
11030 // rcx: tmp2
11031
11032 // rsi holds start addr of source byte[] to be inflated
11033 // rdi holds start addr of destination char[]
11034 // rdx holds length
11035 assert_different_registers(src, dst, len, tmp2);
11036
11037 if ((UseAVX > 2) && // AVX512
11038 VM_Version::supports_avx512vlbw() &&
11039 VM_Version::supports_bmi2()) {
11040
11041 set_vector_masking(); // opening of the stub context for programming mask registers
11042
11043 Label copy_32_loop, copy_tail;
11044 Register tmp3_aliased = len;
11045
11046 // if length of the string is less than 16, handle it in an old fashioned
11047 // way
11048 testl(len, -16);
11049 jcc(Assembler::zero, below_threshold);
11050
11051 // In order to use only one arithmetic operation for the main loop we use
11052 // this pre-calculation
11053 movl(tmp2, len);
11054 andl(tmp2, (32 - 1)); // tail count (in chars), 32 element wide loop
11055 andl(len, -32); // vector count
11056 jccb(Assembler::zero, copy_tail);
11057
11058 lea(src, Address(src, len, Address::times_1));
11059 lea(dst, Address(dst, len, Address::times_2));
11060 negptr(len);
11061
11062
11063 // inflate 32 chars per iter
11064 bind(copy_32_loop);
11065 vpmovzxbw(tmp1, Address(src, len, Address::times_1), Assembler::AVX_512bit);
11066 evmovdquw(Address(dst, len, Address::times_2), tmp1, Assembler::AVX_512bit);
11067 addptr(len, 32);
11068 jcc(Assembler::notZero, copy_32_loop);
11069
11070 bind(copy_tail);
11071 // bail out when there is nothing to be done
11072 testl(tmp2, -1); // we don't destroy the contents of tmp2 here
11073 jcc(Assembler::zero, done);
11074
11075 // Save k1
11076 kmovql(k2, k1);
11077
11078 // ~(~0 << length), where length is the # of remaining elements to process
11079 movl(tmp3_aliased, -1);
11080 shlxl(tmp3_aliased, tmp3_aliased, tmp2);
11081 notl(tmp3_aliased);
11082 kmovdl(k1, tmp3_aliased);
11083 evpmovzxbw(tmp1, k1, Address(src, 0), Assembler::AVX_512bit);
11084 evmovdquw(Address(dst, 0), k1, tmp1, Assembler::AVX_512bit);
11085
11086 // Restore k1
11087 kmovql(k1, k2);
11088 jmp(done);
11089
11090 clear_vector_masking(); // closing of the stub context for programming mask registers
11091 }
11092 if (UseSSE42Intrinsics) {
11093 Label copy_16_loop, copy_8_loop, copy_bytes, copy_new_tail, copy_tail;
11094
11095 movl(tmp2, len);
11096
11097 if (UseAVX > 1) {
11098 andl(tmp2, (16 - 1));
11099 andl(len, -16);
11100 jccb(Assembler::zero, copy_new_tail);
11101 } else {
11102 andl(tmp2, 0x00000007); // tail count (in chars)
11103 andl(len, 0xfffffff8); // vector count (in chars)
11104 jccb(Assembler::zero, copy_tail);
11105 }
11106
11107 // vectored inflation
11108 lea(src, Address(src, len, Address::times_1));
11109 lea(dst, Address(dst, len, Address::times_2));
11110 negptr(len);
11111
11112 if (UseAVX > 1) {
11113 bind(copy_16_loop);
11114 vpmovzxbw(tmp1, Address(src, len, Address::times_1), Assembler::AVX_256bit);
11115 vmovdqu(Address(dst, len, Address::times_2), tmp1);
11116 addptr(len, 16);
11117 jcc(Assembler::notZero, copy_16_loop);
11118
11119 bind(below_threshold);
11120 bind(copy_new_tail);
11121 if ((UseAVX > 2) &&
11122 VM_Version::supports_avx512vlbw() &&
11123 VM_Version::supports_bmi2()) {
11124 movl(tmp2, len);
11125 } else {
11126 movl(len, tmp2);
11127 }
11128 andl(tmp2, 0x00000007);
11129 andl(len, 0xFFFFFFF8);
11130 jccb(Assembler::zero, copy_tail);
11131
11132 pmovzxbw(tmp1, Address(src, 0));
11133 movdqu(Address(dst, 0), tmp1);
11134 addptr(src, 8);
11135 addptr(dst, 2 * 8);
11136
11137 jmp(copy_tail, true);
11138 }
11139
11140 // inflate 8 chars per iter
11141 bind(copy_8_loop);
11142 pmovzxbw(tmp1, Address(src, len, Address::times_1)); // unpack to 8 words
11143 movdqu(Address(dst, len, Address::times_2), tmp1);
11144 addptr(len, 8);
11145 jcc(Assembler::notZero, copy_8_loop);
11146
11147 bind(copy_tail);
11148 movl(len, tmp2);
11149
11150 cmpl(len, 4);
11151 jccb(Assembler::less, copy_bytes);
11152
11153 movdl(tmp1, Address(src, 0)); // load 4 byte chars
11154 pmovzxbw(tmp1, tmp1);
11155 movq(Address(dst, 0), tmp1);
11156 subptr(len, 4);
11157 addptr(src, 4);
11158 addptr(dst, 8);
11159
11160 bind(copy_bytes);
11161 }
11162 testl(len, len);
11163 jccb(Assembler::zero, done);
11164 lea(src, Address(src, len, Address::times_1));
11165 lea(dst, Address(dst, len, Address::times_2));
11166 negptr(len);
11167
11168 // inflate 1 char per iter
11169 bind(copy_chars_loop);
11170 load_unsigned_byte(tmp2, Address(src, len, Address::times_1)); // load byte char
11171 movw(Address(dst, len, Address::times_2), tmp2); // inflate byte char to word
11172 increment(len);
11173 jcc(Assembler::notZero, copy_chars_loop);
11174
11175 bind(done);
11176 }
11177
11178 Assembler::Condition MacroAssembler::negate_condition(Assembler::Condition cond) {
11179 switch (cond) {
11180 // Note some conditions are synonyms for others
11181 case Assembler::zero: return Assembler::notZero;
11182 case Assembler::notZero: return Assembler::zero;
11183 case Assembler::less: return Assembler::greaterEqual;
11184 case Assembler::lessEqual: return Assembler::greater;
11185 case Assembler::greater: return Assembler::lessEqual;
11186 case Assembler::greaterEqual: return Assembler::less;
11187 case Assembler::below: return Assembler::aboveEqual;
11188 case Assembler::belowEqual: return Assembler::above;
11189 case Assembler::above: return Assembler::belowEqual;
11190 case Assembler::aboveEqual: return Assembler::below;
11191 case Assembler::overflow: return Assembler::noOverflow;
11192 case Assembler::noOverflow: return Assembler::overflow;
11193 case Assembler::negative: return Assembler::positive;
11194 case Assembler::positive: return Assembler::negative;
11195 case Assembler::parity: return Assembler::noParity;
11196 case Assembler::noParity: return Assembler::parity;
11197 }
11198 ShouldNotReachHere(); return Assembler::overflow;
11199 }
11200
11201 SkipIfEqual::SkipIfEqual(
11202 MacroAssembler* masm, const bool* flag_addr, bool value) {
11203 _masm = masm;
11204 _masm->cmp8(ExternalAddress((address)flag_addr), value);
11205 _masm->jcc(Assembler::equal, _label);
11206 }
11207
11208 SkipIfEqual::~SkipIfEqual() {
11209 _masm->bind(_label);
11210 }
11211
11212 // 32-bit Windows has its own fast-path implementation
11213 // of get_thread
11214 #if !defined(WIN32) || defined(_LP64)
11215
11216 // This is simply a call to Thread::current()
11217 void MacroAssembler::get_thread(Register thread) {
11218 if (thread != rax) {
11219 push(rax);
11220 }
11221 LP64_ONLY(push(rdi);)
11222 LP64_ONLY(push(rsi);)
11223 push(rdx);
11224 push(rcx);
11225 #ifdef _LP64
11226 push(r8);
11227 push(r9);
11228 push(r10);
11229 push(r11);
11230 #endif
11231
11232 MacroAssembler::call_VM_leaf_base(CAST_FROM_FN_PTR(address, Thread::current), 0);
11233
11234 #ifdef _LP64
11235 pop(r11);
11236 pop(r10);
11237 pop(r9);
11238 pop(r8);
11239 #endif
11240 pop(rcx);
11241 pop(rdx);
11242 LP64_ONLY(pop(rsi);)
11243 LP64_ONLY(pop(rdi);)
11244 if (thread != rax) {
11245 mov(thread, rax);
11246 pop(rax);
11247 }
11248 }
11249
11250 #endif