1 /*
2 * Copyright (c) 1997, 2017, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "asm/macroAssembler.inline.hpp"
27 #include "logging/log.hpp"
28 #include "logging/logStream.hpp"
29 #include "memory/resourceArea.hpp"
30 #include "runtime/java.hpp"
31 #include "runtime/os.hpp"
32 #include "runtime/stubCodeGenerator.hpp"
33 #include "vm_version_sparc.hpp"
34
35 unsigned int VM_Version::_L2_data_cache_line_size = 0;
36
37 void VM_Version::initialize() {
38 assert(_features != 0, "System pre-initialization is not complete.");
39 guarantee(VM_Version::has_v9(), "only SPARC v9 is supported");
40
41 if (FLAG_IS_DEFAULT(PrefetchCopyIntervalInBytes)) {
42 FLAG_SET_DEFAULT(PrefetchCopyIntervalInBytes, prefetch_copy_interval_in_bytes());
43 }
44 if (FLAG_IS_DEFAULT(PrefetchScanIntervalInBytes)) {
45 FLAG_SET_DEFAULT(PrefetchScanIntervalInBytes, prefetch_scan_interval_in_bytes());
46 }
47 if (FLAG_IS_DEFAULT(PrefetchFieldsAhead)) {
48 FLAG_SET_DEFAULT(PrefetchFieldsAhead, prefetch_fields_ahead());
49 }
50
51 // Allocation prefetch settings
52 intx cache_line_size = prefetch_data_size();
53 if (FLAG_IS_DEFAULT(AllocatePrefetchStepSize) &&
54 (cache_line_size > AllocatePrefetchStepSize)) {
55 FLAG_SET_DEFAULT(AllocatePrefetchStepSize, cache_line_size);
56 }
57
58 if (FLAG_IS_DEFAULT(AllocatePrefetchDistance)) {
59 FLAG_SET_DEFAULT(AllocatePrefetchDistance, 512);
60 }
61
62 if ((AllocatePrefetchDistance == 0) && (AllocatePrefetchStyle != 0)) {
63 assert(!FLAG_IS_DEFAULT(AllocatePrefetchDistance), "default value should not be 0");
64 if (!FLAG_IS_DEFAULT(AllocatePrefetchStyle)) {
65 warning("AllocatePrefetchDistance is set to 0 which disable prefetching. Ignoring AllocatePrefetchStyle flag.");
66 }
67 FLAG_SET_DEFAULT(AllocatePrefetchStyle, 0);
68 }
69
70 if ((AllocatePrefetchInstr == 1) && (!has_blk_init() || cache_line_size <= 0)) {
71 if (!FLAG_IS_DEFAULT(AllocatePrefetchInstr)) {
72 warning("BIS instructions required for AllocatePrefetchInstr 1 unavailable");
73 }
74 FLAG_SET_DEFAULT(AllocatePrefetchInstr, 0);
75 }
76
77 UseSSE = 0; // Only on x86 and x64
78
79 _supports_cx8 = has_v9();
80 _supports_atomic_getset4 = true; // swap instruction
81
82 if (is_niagara()) {
83 // Indirect branch is the same cost as direct
84 if (FLAG_IS_DEFAULT(UseInlineCaches)) {
85 FLAG_SET_DEFAULT(UseInlineCaches, false);
86 }
87 // Align loops on a single instruction boundary.
88 if (FLAG_IS_DEFAULT(OptoLoopAlignment)) {
89 FLAG_SET_DEFAULT(OptoLoopAlignment, 4);
90 }
91 // 32-bit oops don't make sense for the 64-bit VM on sparc
92 // since the 32-bit VM has the same registers and smaller objects.
93 Universe::set_narrow_oop_shift(LogMinObjAlignmentInBytes);
94 Universe::set_narrow_klass_shift(LogKlassAlignmentInBytes);
95 #ifdef COMPILER2
96 // Indirect branch is the same cost as direct
97 if (FLAG_IS_DEFAULT(UseJumpTables)) {
98 FLAG_SET_DEFAULT(UseJumpTables, true);
99 }
100 // Single-issue, so entry and loop tops are
101 // aligned on a single instruction boundary
102 if (FLAG_IS_DEFAULT(InteriorEntryAlignment)) {
103 FLAG_SET_DEFAULT(InteriorEntryAlignment, 4);
104 }
105 if (is_niagara_plus()) {
106 if (has_blk_init() && (cache_line_size > 0) && UseTLAB &&
107 FLAG_IS_DEFAULT(AllocatePrefetchInstr)) {
108 if (!has_sparc5_instr()) {
109 // Use BIS instruction for TLAB allocation prefetch
110 // on Niagara plus processors other than those based on CoreS4
111 FLAG_SET_DEFAULT(AllocatePrefetchInstr, 1);
112 } else {
113 // On CoreS4 processors use prefetch instruction
114 // to avoid partial RAW issue, also use prefetch style 3
115 FLAG_SET_DEFAULT(AllocatePrefetchInstr, 0);
116 if (FLAG_IS_DEFAULT(AllocatePrefetchStyle)) {
117 FLAG_SET_DEFAULT(AllocatePrefetchStyle, 3);
118 }
119 }
120 }
121 if (FLAG_IS_DEFAULT(AllocatePrefetchDistance)) {
122 if (AllocatePrefetchInstr == 0) {
123 // Use different prefetch distance without BIS
124 FLAG_SET_DEFAULT(AllocatePrefetchDistance, 256);
125 } else {
126 // Use smaller prefetch distance with BIS
127 FLAG_SET_DEFAULT(AllocatePrefetchDistance, 64);
128 }
129 }
130 if (is_T4()) {
131 // Double number of prefetched cache lines on T4
132 // since L2 cache line size is smaller (32 bytes).
133 if (FLAG_IS_DEFAULT(AllocatePrefetchLines)) {
134 FLAG_SET_ERGO(intx, AllocatePrefetchLines, AllocatePrefetchLines*2);
135 }
136 if (FLAG_IS_DEFAULT(AllocateInstancePrefetchLines)) {
137 FLAG_SET_ERGO(intx, AllocateInstancePrefetchLines, AllocateInstancePrefetchLines*2);
138 }
139 }
140 }
141
142 if ((AllocatePrefetchInstr == 1) && (AllocatePrefetchStyle != 3)) {
143 if (!FLAG_IS_DEFAULT(AllocatePrefetchStyle)) {
144 warning("AllocatePrefetchStyle set to 3 because BIS instructions require aligned memory addresses");
145 }
146 FLAG_SET_DEFAULT(AllocatePrefetchStyle, 3);
147 }
148 #endif /* COMPILER2 */
149 }
150
151 // Use hardware population count instruction if available.
152 if (has_hardware_popc()) {
153 if (FLAG_IS_DEFAULT(UsePopCountInstruction)) {
154 FLAG_SET_DEFAULT(UsePopCountInstruction, true);
155 }
156 } else if (UsePopCountInstruction) {
157 warning("POPC instruction is not available on this CPU");
158 FLAG_SET_DEFAULT(UsePopCountInstruction, false);
159 }
160
161 // T4 and newer Sparc cpus have new compare and branch instruction.
162 if (has_cbcond()) {
163 if (FLAG_IS_DEFAULT(UseCBCond)) {
164 FLAG_SET_DEFAULT(UseCBCond, true);
165 }
166 } else if (UseCBCond) {
167 warning("CBCOND instruction is not available on this CPU");
168 FLAG_SET_DEFAULT(UseCBCond, false);
169 }
170
171 assert(BlockZeroingLowLimit > 0, "invalid value");
172 if (has_block_zeroing() && cache_line_size > 0) {
173 if (FLAG_IS_DEFAULT(UseBlockZeroing)) {
174 FLAG_SET_DEFAULT(UseBlockZeroing, true);
175 }
176 } else if (UseBlockZeroing) {
177 warning("BIS zeroing instructions are not available on this CPU");
178 FLAG_SET_DEFAULT(UseBlockZeroing, false);
179 }
180
181 assert(BlockCopyLowLimit > 0, "invalid value");
182 if (has_block_zeroing() && cache_line_size > 0) { // has_blk_init() && is_T4(): core's local L2 cache
183 if (FLAG_IS_DEFAULT(UseBlockCopy)) {
184 FLAG_SET_DEFAULT(UseBlockCopy, true);
185 }
186 } else if (UseBlockCopy) {
187 warning("BIS instructions are not available or expensive on this CPU");
188 FLAG_SET_DEFAULT(UseBlockCopy, false);
189 }
190
191 #ifdef COMPILER2
192 // T4 and newer Sparc cpus have fast RDPC.
193 if (has_fast_rdpc() && FLAG_IS_DEFAULT(UseRDPCForConstantTableBase)) {
194 FLAG_SET_DEFAULT(UseRDPCForConstantTableBase, true);
195 }
196
197 // Currently not supported anywhere.
198 FLAG_SET_DEFAULT(UseFPUForSpilling, false);
199
200 MaxVectorSize = 8;
201
202 assert((InteriorEntryAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size");
203 #endif
204
205 assert((CodeEntryAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size");
206 assert((OptoLoopAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size");
207
208 char buf[512];
209 jio_snprintf(buf, sizeof(buf), "%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s",
210 (has_v9() ? ", v9" : (has_v8() ? ", v8" : "")),
211 (has_hardware_popc() ? ", popc" : ""),
212 (has_vis1() ? ", vis1" : ""),
213 (has_vis2() ? ", vis2" : ""),
214 (has_vis3() ? ", vis3" : ""),
215 (has_blk_init() ? ", blk_init" : ""),
216 (has_cbcond() ? ", cbcond" : ""),
217 (has_aes() ? ", aes" : ""),
218 (has_sha1() ? ", sha1" : ""),
219 (has_sha256() ? ", sha256" : ""),
220 (has_sha512() ? ", sha512" : ""),
221 (has_crc32c() ? ", crc32c" : ""),
222 (is_ultra3() ? ", ultra3" : ""),
223 (has_sparc5_instr() ? ", sparc5" : ""),
224 (is_sun4v() ? ", sun4v" : ""),
225 (is_niagara_plus() ? ", niagara_plus" : (is_niagara() ? ", niagara" : "")),
226 (is_sparc64() ? ", sparc64" : ""),
227 (!has_hardware_mul32() ? ", no-mul32" : ""),
228 (!has_hardware_div32() ? ", no-div32" : ""),
229 (!has_hardware_fsmuld() ? ", no-fsmuld" : ""));
230
231 // buf is started with ", " or is empty
232 _features_string = os::strdup(strlen(buf) > 2 ? buf + 2 : buf);
233
234 // UseVIS is set to the smallest of what hardware supports and what
235 // the command line requires. I.e., you cannot set UseVIS to 3 on
236 // older UltraSparc which do not support it.
237 if (UseVIS > 3) UseVIS=3;
238 if (UseVIS < 0) UseVIS=0;
239 if (!has_vis3()) // Drop to 2 if no VIS3 support
240 UseVIS = MIN2((intx)2,UseVIS);
241 if (!has_vis2()) // Drop to 1 if no VIS2 support
242 UseVIS = MIN2((intx)1,UseVIS);
243 if (!has_vis1()) // Drop to 0 if no VIS1 support
244 UseVIS = 0;
245
246 // SPARC T4 and above should have support for AES instructions
247 if (has_aes()) {
248 if (FLAG_IS_DEFAULT(UseAES)) {
249 FLAG_SET_DEFAULT(UseAES, true);
250 }
251 if (!UseAES) {
252 if (UseAESIntrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) {
253 warning("AES intrinsics require UseAES flag to be enabled. Intrinsics will be disabled.");
254 }
255 FLAG_SET_DEFAULT(UseAESIntrinsics, false);
256 } else {
257 // The AES intrinsic stubs require AES instruction support (of course)
258 // but also require VIS3 mode or higher for instructions it use.
259 if (UseVIS > 2) {
260 if (FLAG_IS_DEFAULT(UseAESIntrinsics)) {
261 FLAG_SET_DEFAULT(UseAESIntrinsics, true);
262 }
263 } else {
264 if (UseAESIntrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) {
265 warning("SPARC AES intrinsics require VIS3 instructions. Intrinsics will be disabled.");
266 }
267 FLAG_SET_DEFAULT(UseAESIntrinsics, false);
268 }
269 }
270 } else if (UseAES || UseAESIntrinsics) {
271 if (UseAES && !FLAG_IS_DEFAULT(UseAES)) {
272 warning("AES instructions are not available on this CPU");
273 FLAG_SET_DEFAULT(UseAES, false);
274 }
275 if (UseAESIntrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) {
276 warning("AES intrinsics are not available on this CPU");
277 FLAG_SET_DEFAULT(UseAESIntrinsics, false);
278 }
279 }
280
281 if (UseAESCTRIntrinsics) {
282 warning("AES/CTR intrinsics are not available on this CPU");
283 FLAG_SET_DEFAULT(UseAESCTRIntrinsics, false);
284 }
285
286 // GHASH/GCM intrinsics
287 if (has_vis3() && (UseVIS > 2)) {
288 if (FLAG_IS_DEFAULT(UseGHASHIntrinsics)) {
289 UseGHASHIntrinsics = true;
290 }
291 } else if (UseGHASHIntrinsics) {
292 if (!FLAG_IS_DEFAULT(UseGHASHIntrinsics))
293 warning("GHASH intrinsics require VIS3 instruction support. Intrinsics will be disabled");
294 FLAG_SET_DEFAULT(UseGHASHIntrinsics, false);
295 }
296
297 if (UseFMA) {
298 warning("FMA instructions are not available on this CPU");
299 FLAG_SET_DEFAULT(UseFMA, false);
300 }
301
302 // SHA1, SHA256, and SHA512 instructions were added to SPARC T-series at different times
303 if (has_sha1() || has_sha256() || has_sha512()) {
304 if (UseVIS > 0) { // SHA intrinsics use VIS1 instructions
305 if (FLAG_IS_DEFAULT(UseSHA)) {
306 FLAG_SET_DEFAULT(UseSHA, true);
307 }
308 } else {
309 if (UseSHA) {
310 warning("SPARC SHA intrinsics require VIS1 instruction support. Intrinsics will be disabled.");
311 FLAG_SET_DEFAULT(UseSHA, false);
312 }
313 }
314 } else if (UseSHA) {
315 warning("SHA instructions are not available on this CPU");
316 FLAG_SET_DEFAULT(UseSHA, false);
317 }
318
319 if (UseSHA && has_sha1()) {
320 if (FLAG_IS_DEFAULT(UseSHA1Intrinsics)) {
321 FLAG_SET_DEFAULT(UseSHA1Intrinsics, true);
322 }
323 } else if (UseSHA1Intrinsics) {
324 warning("Intrinsics for SHA-1 crypto hash functions not available on this CPU.");
325 FLAG_SET_DEFAULT(UseSHA1Intrinsics, false);
326 }
327
328 if (UseSHA && has_sha256()) {
329 if (FLAG_IS_DEFAULT(UseSHA256Intrinsics)) {
330 FLAG_SET_DEFAULT(UseSHA256Intrinsics, true);
331 }
332 } else if (UseSHA256Intrinsics) {
333 warning("Intrinsics for SHA-224 and SHA-256 crypto hash functions not available on this CPU.");
334 FLAG_SET_DEFAULT(UseSHA256Intrinsics, false);
335 }
336
337 if (UseSHA && has_sha512()) {
338 if (FLAG_IS_DEFAULT(UseSHA512Intrinsics)) {
339 FLAG_SET_DEFAULT(UseSHA512Intrinsics, true);
340 }
341 } else if (UseSHA512Intrinsics) {
342 warning("Intrinsics for SHA-384 and SHA-512 crypto hash functions not available on this CPU.");
343 FLAG_SET_DEFAULT(UseSHA512Intrinsics, false);
344 }
345
346 if (!(UseSHA1Intrinsics || UseSHA256Intrinsics || UseSHA512Intrinsics)) {
347 FLAG_SET_DEFAULT(UseSHA, false);
348 }
349
350 // SPARC T4 and above should have support for CRC32C instruction
351 if (has_crc32c()) {
352 if (UseVIS > 2) { // CRC32C intrinsics use VIS3 instructions
353 if (FLAG_IS_DEFAULT(UseCRC32CIntrinsics)) {
354 FLAG_SET_DEFAULT(UseCRC32CIntrinsics, true);
355 }
356 } else {
357 if (UseCRC32CIntrinsics) {
358 warning("SPARC CRC32C intrinsics require VIS3 instruction support. Intrinsics will be disabled.");
359 FLAG_SET_DEFAULT(UseCRC32CIntrinsics, false);
360 }
361 }
362 } else if (UseCRC32CIntrinsics) {
363 warning("CRC32C instruction is not available on this CPU");
364 FLAG_SET_DEFAULT(UseCRC32CIntrinsics, false);
365 }
366
367 if (UseVIS > 2) {
368 if (FLAG_IS_DEFAULT(UseAdler32Intrinsics)) {
369 FLAG_SET_DEFAULT(UseAdler32Intrinsics, true);
370 }
371 } else if (UseAdler32Intrinsics) {
372 warning("SPARC Adler32 intrinsics require VIS3 instruction support. Intrinsics will be disabled.");
373 FLAG_SET_DEFAULT(UseAdler32Intrinsics, false);
374 }
375
376 if (UseVIS > 2) {
377 if (FLAG_IS_DEFAULT(UseCRC32Intrinsics)) {
378 FLAG_SET_DEFAULT(UseCRC32Intrinsics, true);
379 }
380 } else if (UseCRC32Intrinsics) {
381 warning("SPARC CRC32 intrinsics require VIS3 instructions support. Intrinsics will be disabled");
382 FLAG_SET_DEFAULT(UseCRC32Intrinsics, false);
383 }
384
385 if (UseVectorizedMismatchIntrinsic) {
386 warning("UseVectorizedMismatchIntrinsic specified, but not available on this CPU.");
387 FLAG_SET_DEFAULT(UseVectorizedMismatchIntrinsic, false);
388 }
389
390 if (FLAG_IS_DEFAULT(ContendedPaddingWidth) &&
391 (cache_line_size > ContendedPaddingWidth))
392 ContendedPaddingWidth = cache_line_size;
393
394 // This machine does not allow unaligned memory accesses
395 if (UseUnalignedAccesses) {
396 if (!FLAG_IS_DEFAULT(UseUnalignedAccesses))
397 warning("Unaligned memory access is not available on this CPU");
398 FLAG_SET_DEFAULT(UseUnalignedAccesses, false);
399 }
400
401 if (log_is_enabled(Info, os, cpu)) {
402 ResourceMark rm;
403 LogStream ls(Log(os, cpu)::info());
404 outputStream* log = &ls;
405 log->print_cr("L1 data cache line size: %u", L1_data_cache_line_size());
406 log->print_cr("L2 data cache line size: %u", L2_data_cache_line_size());
407 log->print("Allocation");
408 if (AllocatePrefetchStyle <= 0) {
409 log->print(": no prefetching");
410 } else {
411 log->print(" prefetching: ");
412 if (AllocatePrefetchInstr == 0) {
413 log->print("PREFETCH");
414 } else if (AllocatePrefetchInstr == 1) {
415 log->print("BIS");
416 }
417 if (AllocatePrefetchLines > 1) {
418 log->print_cr(" at distance %d, %d lines of %d bytes", (int) AllocatePrefetchDistance, (int) AllocatePrefetchLines, (int) AllocatePrefetchStepSize);
419 } else {
420 log->print_cr(" at distance %d, one line of %d bytes", (int) AllocatePrefetchDistance, (int) AllocatePrefetchStepSize);
421 }
422 }
423 if (PrefetchCopyIntervalInBytes > 0) {
424 log->print_cr("PrefetchCopyIntervalInBytes %d", (int) PrefetchCopyIntervalInBytes);
425 }
426 if (PrefetchScanIntervalInBytes > 0) {
427 log->print_cr("PrefetchScanIntervalInBytes %d", (int) PrefetchScanIntervalInBytes);
428 }
429 if (PrefetchFieldsAhead > 0) {
430 log->print_cr("PrefetchFieldsAhead %d", (int) PrefetchFieldsAhead);
431 }
432 if (ContendedPaddingWidth > 0) {
433 log->print_cr("ContendedPaddingWidth %d", (int) ContendedPaddingWidth);
434 }
435 }
436 }
437
438 void VM_Version::print_features() {
439 tty->print_cr("Version:%s", _features);
440 }
441
442 int VM_Version::determine_features() {
443 if (UseV8InstrsOnly) {
444 log_info(os, cpu)("Version is Forced-V8");
445 return generic_v8_m;
446 }
447
448 int features = platform_features(unknown_m); // platform_features() is os_arch specific
449
450 if (features == unknown_m) {
451 features = generic_v9_m;
452 log_info(os)("Cannot recognize SPARC version. Default to V9");
453 }
454
455 assert(is_T_family(features) == is_niagara(features), "Niagara should be T series");
456 if (UseNiagaraInstrs) { // Force code generation for Niagara
457 if (is_T_family(features)) {
458 // Happy to accomodate...
459 } else {
460 log_info(os, cpu)("Version is Forced-Niagara");
461 features |= T_family_m;
462 }
463 } else {
464 if (is_T_family(features) && !FLAG_IS_DEFAULT(UseNiagaraInstrs)) {
465 log_info(os, cpu)("Version is Forced-Not-Niagara");
466 features &= ~(T_family_m | T1_model_m);
467 } else {
468 // Happy to accomodate...
469 }
470 }
471
472 return features;
473 }
474
475 static uint64_t saved_features = 0;
476
477 void VM_Version::allow_all() {
478 saved_features = _features;
479 _features = all_features_m;
480 }
481
482 void VM_Version::revert() {
483 _features = saved_features;
484 }
485
486 unsigned int VM_Version::calc_parallel_worker_threads() {
487 unsigned int result;
488 if (is_M_series() || is_S_series()) {
489 // for now, use same gc thread calculation for M-series and S-series as for
490 // niagara-plus. In future, we may want to tweak parameters for
491 // nof_parallel_worker_thread
492 result = nof_parallel_worker_threads(5, 16, 8);
493 } else if (is_niagara_plus()) {
494 result = nof_parallel_worker_threads(5, 16, 8);
495 } else {
496 result = nof_parallel_worker_threads(5, 8, 8);
497 }
498 return result;
499 }
500
501
502 int VM_Version::parse_features(const char* implementation) {
503 int features = unknown_m;
504 // Convert to UPPER case before compare.
505 char* impl = os::strdup_check_oom(implementation);
506
507 for (int i = 0; impl[i] != 0; i++)
508 impl[i] = (char)toupper((uint)impl[i]);
509
510 if (strstr(impl, "SPARC64") != NULL) {
511 features |= sparc64_family_m;
512 } else if (strstr(impl, "SPARC-M") != NULL) {
513 // M-series SPARC is based on T-series.
514 features |= (M_family_m | T_family_m);
515 } else if (strstr(impl, "SPARC-S") != NULL) {
516 // S-series SPARC is based on T-series.
517 features |= (S_family_m | T_family_m);
518 } else if (strstr(impl, "SPARC-T") != NULL) {
519 features |= T_family_m;
520 if (strstr(impl, "SPARC-T1") != NULL) {
521 features |= T1_model_m;
522 }
523 } else if (strstr(impl, "SUN4V-CPU") != NULL) {
524 // Generic or migration class LDOM
525 features |= T_family_m;
526 } else {
527 log_info(os, cpu)("Failed to parse CPU implementation = '%s'", impl);
528 }
529 os::free((void*)impl);
530 return features;
531 }