201 };
202
203 union SefCpuid7Ebx {
204 uint32_t value;
205 struct {
206 uint32_t fsgsbase : 1,
207 : 2,
208 bmi1 : 1,
209 : 1,
210 avx2 : 1,
211 : 2,
212 bmi2 : 1,
213 erms : 1,
214 : 1,
215 rtm : 1,
216 : 4,
217 avx512f : 1,
218 avx512dq : 1,
219 : 1,
220 adx : 1,
221 : 6,
222 avx512pf : 1,
223 avx512er : 1,
224 avx512cd : 1,
225 sha : 1,
226 avx512bw : 1,
227 avx512vl : 1;
228 } bits;
229 };
230
231 union SefCpuid7Ecx {
232 uint32_t value;
233 struct {
234 uint32_t prefetchwt1 : 1,
235 avx512_vbmi : 1,
236 umip : 1,
237 pku : 1,
238 ospke : 1,
239 : 1,
240 avx512_vbmi2 : 1,
241 : 1,
320 CPU_BMI2 = (1 << 23),
321 CPU_RTM = (1 << 24), // Restricted Transactional Memory instructions
322 CPU_ADX = (1 << 25),
323 CPU_AVX512F = (1 << 26), // AVX 512bit foundation instructions
324 CPU_AVX512DQ = (1 << 27),
325 CPU_AVX512PF = (1 << 28),
326 CPU_AVX512ER = (1 << 29),
327 CPU_AVX512CD = (1 << 30)
328 // Keeping sign bit 31 unassigned.
329 };
330
331 #define CPU_AVX512BW ((uint64_t)UCONST64(0x100000000)) // enums are limited to 31 bit
332 #define CPU_AVX512VL ((uint64_t)UCONST64(0x200000000)) // EVEX instructions with smaller vector length
333 #define CPU_SHA ((uint64_t)UCONST64(0x400000000)) // SHA instructions
334 #define CPU_FMA ((uint64_t)UCONST64(0x800000000)) // FMA instructions
335 #define CPU_VZEROUPPER ((uint64_t)UCONST64(0x1000000000)) // Vzeroupper instruction
336 #define CPU_AVX512_VPOPCNTDQ ((uint64_t)UCONST64(0x2000000000)) // Vector popcount
337 #define CPU_VPCLMULQDQ ((uint64_t)UCONST64(0x4000000000)) //Vector carryless multiplication
338 #define CPU_VAES ((uint64_t)UCONST64(0x8000000000)) // Vector AES instructions
339
340 enum Extended_Family {
341 // AMD
342 CPU_FAMILY_AMD_11H = 0x11,
343 // ZX
344 CPU_FAMILY_ZX_CORE_F6 = 6,
345 CPU_FAMILY_ZX_CORE_F7 = 7,
346 // Intel
347 CPU_FAMILY_INTEL_CORE = 6,
348 CPU_MODEL_NEHALEM = 0x1e,
349 CPU_MODEL_NEHALEM_EP = 0x1a,
350 CPU_MODEL_NEHALEM_EX = 0x2e,
351 CPU_MODEL_WESTMERE = 0x25,
352 CPU_MODEL_WESTMERE_EP = 0x2c,
353 CPU_MODEL_WESTMERE_EX = 0x2f,
354 CPU_MODEL_SANDYBRIDGE = 0x2a,
355 CPU_MODEL_SANDYBRIDGE_EP = 0x2d,
356 CPU_MODEL_IVYBRIDGE_EP = 0x3a,
357 CPU_MODEL_HASWELL_E3 = 0x3c,
358 CPU_MODEL_HASWELL_E7 = 0x3f,
359 CPU_MODEL_BROADWELL = 0x3d,
360 CPU_MODEL_SKYLAKE = CPU_MODEL_HASWELL_E3
555 if (_cpuid_info.std_cpuid1_edx.bits.tsc != 0)
556 result |= CPU_TSC;
557 if (_cpuid_info.ext_cpuid7_edx.bits.tsc_invariance != 0)
558 result |= CPU_TSCINV;
559 if (_cpuid_info.std_cpuid1_ecx.bits.aes != 0)
560 result |= CPU_AES;
561 if (_cpuid_info.sef_cpuid7_ebx.bits.erms != 0)
562 result |= CPU_ERMS;
563 if (_cpuid_info.std_cpuid1_ecx.bits.clmul != 0)
564 result |= CPU_CLMUL;
565 if (_cpuid_info.sef_cpuid7_ebx.bits.rtm != 0)
566 result |= CPU_RTM;
567 if(_cpuid_info.sef_cpuid7_ebx.bits.adx != 0)
568 result |= CPU_ADX;
569 if(_cpuid_info.sef_cpuid7_ebx.bits.bmi2 != 0)
570 result |= CPU_BMI2;
571 if (_cpuid_info.sef_cpuid7_ebx.bits.sha != 0)
572 result |= CPU_SHA;
573 if (_cpuid_info.std_cpuid1_ecx.bits.fma != 0)
574 result |= CPU_FMA;
575
576 // AMD features.
577 if (is_amd()) {
578 if ((_cpuid_info.ext_cpuid1_edx.bits.tdnow != 0) ||
579 (_cpuid_info.ext_cpuid1_ecx.bits.prefetchw != 0))
580 result |= CPU_3DNOW_PREFETCH;
581 if (_cpuid_info.ext_cpuid1_ecx.bits.lzcnt != 0)
582 result |= CPU_LZCNT;
583 if (_cpuid_info.ext_cpuid1_ecx.bits.sse4a != 0)
584 result |= CPU_SSE4A;
585 }
586 // Intel features.
587 if(is_intel()) {
588 if(_cpuid_info.ext_cpuid1_ecx.bits.lzcnt_intel != 0)
589 result |= CPU_LZCNT;
590 // for Intel, ecx.bits.misalignsse bit (bit 8) indicates support for prefetchw
591 if (_cpuid_info.ext_cpuid1_ecx.bits.misalignsse != 0) {
592 result |= CPU_3DNOW_PREFETCH;
593 }
594 }
595
596 // ZX features.
597 if (is_zx()) {
598 if (_cpuid_info.ext_cpuid1_ecx.bits.lzcnt_intel != 0)
599 result |= CPU_LZCNT;
600 // for ZX, ecx.bits.misalignsse bit (bit 8) indicates support for prefetchw
601 if (_cpuid_info.ext_cpuid1_ecx.bits.misalignsse != 0) {
602 result |= CPU_3DNOW_PREFETCH;
603 }
604 }
605
606 return result;
607 }
608
609 static bool os_supports_avx_vectors() {
610 bool retVal = false;
611 if (supports_evex()) {
612 // Verify that OS save/restore all bits of EVEX registers
613 // during signal processing.
908 return 320;
909 #endif
910 }
911 }
912 if (supports_sse2()) {
913 if (cpu_family() == 6) {
914 return 256; // Pentium M, Core, Core2
915 } else {
916 return 512; // Pentium 4
917 }
918 } else {
919 return 128; // Pentium 3 (and all other old CPUs)
920 }
921 }
922 }
923
924 // SSE2 and later processors implement a 'pause' instruction
925 // that can be used for efficient implementation of
926 // the intrinsic for java.lang.Thread.onSpinWait()
927 static bool supports_on_spin_wait() { return supports_sse2(); }
928 };
929
930 #endif // CPU_X86_VM_VM_VERSION_X86_HPP
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201 };
202
203 union SefCpuid7Ebx {
204 uint32_t value;
205 struct {
206 uint32_t fsgsbase : 1,
207 : 2,
208 bmi1 : 1,
209 : 1,
210 avx2 : 1,
211 : 2,
212 bmi2 : 1,
213 erms : 1,
214 : 1,
215 rtm : 1,
216 : 4,
217 avx512f : 1,
218 avx512dq : 1,
219 : 1,
220 adx : 1,
221 : 3,
222 clflushopt : 1,
223 clwb : 1,
224 : 1,
225 avx512pf : 1,
226 avx512er : 1,
227 avx512cd : 1,
228 sha : 1,
229 avx512bw : 1,
230 avx512vl : 1;
231 } bits;
232 };
233
234 union SefCpuid7Ecx {
235 uint32_t value;
236 struct {
237 uint32_t prefetchwt1 : 1,
238 avx512_vbmi : 1,
239 umip : 1,
240 pku : 1,
241 ospke : 1,
242 : 1,
243 avx512_vbmi2 : 1,
244 : 1,
323 CPU_BMI2 = (1 << 23),
324 CPU_RTM = (1 << 24), // Restricted Transactional Memory instructions
325 CPU_ADX = (1 << 25),
326 CPU_AVX512F = (1 << 26), // AVX 512bit foundation instructions
327 CPU_AVX512DQ = (1 << 27),
328 CPU_AVX512PF = (1 << 28),
329 CPU_AVX512ER = (1 << 29),
330 CPU_AVX512CD = (1 << 30)
331 // Keeping sign bit 31 unassigned.
332 };
333
334 #define CPU_AVX512BW ((uint64_t)UCONST64(0x100000000)) // enums are limited to 31 bit
335 #define CPU_AVX512VL ((uint64_t)UCONST64(0x200000000)) // EVEX instructions with smaller vector length
336 #define CPU_SHA ((uint64_t)UCONST64(0x400000000)) // SHA instructions
337 #define CPU_FMA ((uint64_t)UCONST64(0x800000000)) // FMA instructions
338 #define CPU_VZEROUPPER ((uint64_t)UCONST64(0x1000000000)) // Vzeroupper instruction
339 #define CPU_AVX512_VPOPCNTDQ ((uint64_t)UCONST64(0x2000000000)) // Vector popcount
340 #define CPU_VPCLMULQDQ ((uint64_t)UCONST64(0x4000000000)) //Vector carryless multiplication
341 #define CPU_VAES ((uint64_t)UCONST64(0x8000000000)) // Vector AES instructions
342
343 #define CPU_FLUSHOPT ((uint64_t)UCONST64(0x1000000000)) // flushopt instruction
344 #define CPU_CLWB ((uint64_t)UCONST64(0x2000000000)) // clwb instruction
345
346 enum Extended_Family {
347 // AMD
348 CPU_FAMILY_AMD_11H = 0x11,
349 // ZX
350 CPU_FAMILY_ZX_CORE_F6 = 6,
351 CPU_FAMILY_ZX_CORE_F7 = 7,
352 // Intel
353 CPU_FAMILY_INTEL_CORE = 6,
354 CPU_MODEL_NEHALEM = 0x1e,
355 CPU_MODEL_NEHALEM_EP = 0x1a,
356 CPU_MODEL_NEHALEM_EX = 0x2e,
357 CPU_MODEL_WESTMERE = 0x25,
358 CPU_MODEL_WESTMERE_EP = 0x2c,
359 CPU_MODEL_WESTMERE_EX = 0x2f,
360 CPU_MODEL_SANDYBRIDGE = 0x2a,
361 CPU_MODEL_SANDYBRIDGE_EP = 0x2d,
362 CPU_MODEL_IVYBRIDGE_EP = 0x3a,
363 CPU_MODEL_HASWELL_E3 = 0x3c,
364 CPU_MODEL_HASWELL_E7 = 0x3f,
365 CPU_MODEL_BROADWELL = 0x3d,
366 CPU_MODEL_SKYLAKE = CPU_MODEL_HASWELL_E3
561 if (_cpuid_info.std_cpuid1_edx.bits.tsc != 0)
562 result |= CPU_TSC;
563 if (_cpuid_info.ext_cpuid7_edx.bits.tsc_invariance != 0)
564 result |= CPU_TSCINV;
565 if (_cpuid_info.std_cpuid1_ecx.bits.aes != 0)
566 result |= CPU_AES;
567 if (_cpuid_info.sef_cpuid7_ebx.bits.erms != 0)
568 result |= CPU_ERMS;
569 if (_cpuid_info.std_cpuid1_ecx.bits.clmul != 0)
570 result |= CPU_CLMUL;
571 if (_cpuid_info.sef_cpuid7_ebx.bits.rtm != 0)
572 result |= CPU_RTM;
573 if(_cpuid_info.sef_cpuid7_ebx.bits.adx != 0)
574 result |= CPU_ADX;
575 if(_cpuid_info.sef_cpuid7_ebx.bits.bmi2 != 0)
576 result |= CPU_BMI2;
577 if (_cpuid_info.sef_cpuid7_ebx.bits.sha != 0)
578 result |= CPU_SHA;
579 if (_cpuid_info.std_cpuid1_ecx.bits.fma != 0)
580 result |= CPU_FMA;
581 if (_cpuid_info.sef_cpuid7_ebx.bits.clflushopt != 0)
582 result |= CPU_FLUSHOPT;
583
584 // AMD features.
585 if (is_amd()) {
586 if ((_cpuid_info.ext_cpuid1_edx.bits.tdnow != 0) ||
587 (_cpuid_info.ext_cpuid1_ecx.bits.prefetchw != 0))
588 result |= CPU_3DNOW_PREFETCH;
589 if (_cpuid_info.ext_cpuid1_ecx.bits.lzcnt != 0)
590 result |= CPU_LZCNT;
591 if (_cpuid_info.ext_cpuid1_ecx.bits.sse4a != 0)
592 result |= CPU_SSE4A;
593 }
594 // Intel features.
595 if(is_intel()) {
596 if(_cpuid_info.ext_cpuid1_ecx.bits.lzcnt_intel != 0)
597 result |= CPU_LZCNT;
598 // for Intel, ecx.bits.misalignsse bit (bit 8) indicates support for prefetchw
599 if (_cpuid_info.ext_cpuid1_ecx.bits.misalignsse != 0) {
600 result |= CPU_3DNOW_PREFETCH;
601 }
602 if (_cpuid_info.sef_cpuid7_ebx.bits.clwb != 0) {
603 result |= CPU_CLWB;
604 }
605 }
606
607 // ZX features.
608 if (is_zx()) {
609 if (_cpuid_info.ext_cpuid1_ecx.bits.lzcnt_intel != 0)
610 result |= CPU_LZCNT;
611 // for ZX, ecx.bits.misalignsse bit (bit 8) indicates support for prefetchw
612 if (_cpuid_info.ext_cpuid1_ecx.bits.misalignsse != 0) {
613 result |= CPU_3DNOW_PREFETCH;
614 }
615 }
616
617 return result;
618 }
619
620 static bool os_supports_avx_vectors() {
621 bool retVal = false;
622 if (supports_evex()) {
623 // Verify that OS save/restore all bits of EVEX registers
624 // during signal processing.
919 return 320;
920 #endif
921 }
922 }
923 if (supports_sse2()) {
924 if (cpu_family() == 6) {
925 return 256; // Pentium M, Core, Core2
926 } else {
927 return 512; // Pentium 4
928 }
929 } else {
930 return 128; // Pentium 3 (and all other old CPUs)
931 }
932 }
933 }
934
935 // SSE2 and later processors implement a 'pause' instruction
936 // that can be used for efficient implementation of
937 // the intrinsic for java.lang.Thread.onSpinWait()
938 static bool supports_on_spin_wait() { return supports_sse2(); }
939
940 // there are several insns to force cache line sync to memory which
941 // we can use to ensure mapped persistent memory is up to date with
942 // pending in-cache changes.
943 //
944 // 64 bit cpus always support clflush which writes back and evicts
945 //
946 // clflushopt is optional and acts like clflush except it does
947 // not synchronize with other memory ops. it needs a preceding
948 // and trailing StoreStore fence
949 //
950 // clwb is an optional, intel-specific instruction optional which
951 // writes back without evicting the line. it also does not
952 // synchronize with other memory ops. so, it also needs a preceding
953 // and trailing StoreStore fence.
954
955 #ifdef _LP64
956 static bool supports_clflush() { return true; }
957 static bool supports_clflushopt() { return (_features & CPU_FLUSHOPT == 0); }
958 static bool supports_clwb() { return (_features & CPU_CLWB == 0); }
959 #else
960 static bool supports_clflush() { return true; }
961 static bool supports_clflushopt() { return false; }
962 static bool supports_clwb() { return false; }
963 #endif // _LP64
964
965 };
966
967 #endif // CPU_X86_VM_VM_VERSION_X86_HPP
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