--- old/src/hotspot/cpu/aarch64/macroAssembler_aarch64.cpp	2018-07-25 11:31:17.568888166 +0100
+++ new/src/hotspot/cpu/aarch64/macroAssembler_aarch64.cpp	2018-07-25 11:31:17.290887336 +0100
@@ -5803,3 +5803,21 @@
 
   pop(saved_regs, sp);
 }
+
+void MacroAssembler::cache_wb(Address line)
+{
+  assert(line.getMode() == Address::base_plus_offset, "mode should be base_plus_offset");
+  assert(line.index() == noreg, "index should be noreg");
+  assert(line.offset() == 0, "offset should be 0");
+  // would like to assert this
+  // assert(line._ext.shift == 0, "shift should be zero");
+  dc(Assembler::CVAC, line.base());
+}
+
+void MacroAssembler::cache_wbsync(bool is_pre)
+{
+  // we only need a barrier post sync
+  if (!is_pre) {
+    membar(Assembler::AnyAny);
+  }
+}