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src/hotspot/cpu/x86/vm_version_x86.hpp
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@@ -216,11 +216,14 @@
: 4,
avx512f : 1,
avx512dq : 1,
: 1,
adx : 1,
- : 6,
+ : 3,
+ clflushopt : 1,
+ clwb : 1,
+ : 1,
avx512pf : 1,
avx512er : 1,
avx512cd : 1,
sha : 1,
avx512bw : 1,
@@ -335,11 +338,14 @@
#define CPU_VZEROUPPER ((uint64_t)UCONST64(0x1000000000)) // Vzeroupper instruction
#define CPU_AVX512_VPOPCNTDQ ((uint64_t)UCONST64(0x2000000000)) // Vector popcount
#define CPU_VPCLMULQDQ ((uint64_t)UCONST64(0x4000000000)) //Vector carryless multiplication
#define CPU_VAES ((uint64_t)UCONST64(0x8000000000)) // Vector AES instructions
- enum Extended_Family {
+#define CPU_FLUSHOPT ((uint64_t)UCONST64(0x1000000000)) // flushopt instruction
+#define CPU_CLWB ((uint64_t)UCONST64(0x2000000000)) // clwb instruction
+
+enum Extended_Family {
// AMD
CPU_FAMILY_AMD_11H = 0x11,
// ZX
CPU_FAMILY_ZX_CORE_F6 = 6,
CPU_FAMILY_ZX_CORE_F7 = 7,
@@ -570,10 +576,12 @@
result |= CPU_BMI2;
if (_cpuid_info.sef_cpuid7_ebx.bits.sha != 0)
result |= CPU_SHA;
if (_cpuid_info.std_cpuid1_ecx.bits.fma != 0)
result |= CPU_FMA;
+ if (_cpuid_info.sef_cpuid7_ebx.bits.clflushopt != 0)
+ result |= CPU_FLUSHOPT;
// AMD features.
if (is_amd()) {
if ((_cpuid_info.ext_cpuid1_edx.bits.tdnow != 0) ||
(_cpuid_info.ext_cpuid1_ecx.bits.prefetchw != 0))
@@ -589,10 +597,13 @@
result |= CPU_LZCNT;
// for Intel, ecx.bits.misalignsse bit (bit 8) indicates support for prefetchw
if (_cpuid_info.ext_cpuid1_ecx.bits.misalignsse != 0) {
result |= CPU_3DNOW_PREFETCH;
}
+ if (_cpuid_info.sef_cpuid7_ebx.bits.clwb != 0) {
+ result |= CPU_CLWB;
+ }
}
// ZX features.
if (is_zx()) {
if (_cpuid_info.ext_cpuid1_ecx.bits.lzcnt_intel != 0)
@@ -923,8 +934,34 @@
// SSE2 and later processors implement a 'pause' instruction
// that can be used for efficient implementation of
// the intrinsic for java.lang.Thread.onSpinWait()
static bool supports_on_spin_wait() { return supports_sse2(); }
+
+ // there are several insns to force cache line sync to memory which
+ // we can use to ensure mapped persistent memory is up to date with
+ // pending in-cache changes.
+ //
+ // 64 bit cpus always support clflush which writes back and evicts
+ //
+ // clflushopt is optional and acts like clflush except it does
+ // not synchronize with other memory ops. it needs a preceding
+ // and trailing StoreStore fence
+ //
+ // clwb is an optional, intel-specific instruction optional which
+ // writes back without evicting the line. it also does not
+ // synchronize with other memory ops. so, it also needs a preceding
+ // and trailing StoreStore fence.
+
+#ifdef _LP64
+ static bool supports_clflush() { return true; }
+ static bool supports_clflushopt() { return (_features & CPU_FLUSHOPT == 0); }
+ static bool supports_clwb() { return (_features & CPU_CLWB == 0); }
+#else
+ static bool supports_clflush() { return true; }
+ static bool supports_clflushopt() { return false; }
+ static bool supports_clwb() { return false; }
+#endif // _LP64
+
};
#endif // CPU_X86_VM_VM_VERSION_X86_HPP
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