src/hotspot/cpu/aarch64/aarch64.ad

*** 8923,8932 ****
--- 8923,8970 ----
    ins_pipe(pipe_class_memory);
  %}
  
  //  ---------------- end of volatile loads and stores ----------------
  
+ instruct cacheWB(indirect addr)
+ %{
+   match(CacheWB addr);
+ 
+   ins_cost(100);
+   format %{"cache wb $addr" %}
+   ins_encode %{
+     assert($addr->index_position() < 0, "should be");
+     assert($addr$$disp == 0, "should be");
+     __ cache_wb(Address($addr$$base$$Register, 0));
+   %}
+   ins_pipe(pipe_slow); // XXX
+ %}
+ 
+ instruct cacheWBPreSync()
+ %{
+   match(CacheWBPreSync);
+ 
+   ins_cost(100);
+   format %{"cache wb presync" %}
+   ins_encode %{
+     __ cache_wbsync(true);
+   %}
+   ins_pipe(pipe_slow); // XXX
+ %}
+ 
+ instruct cacheWBPostSync()
+ %{
+   match(CacheWBPostSync);
+ 
+   ins_cost(100);
+   format %{"cache wb postsync" %}
+   ins_encode %{
+     __ cache_wbsync(false);
+   %}
+   ins_pipe(pipe_slow); // XXX
+ %}
+ 
  // ============================================================================
  // BSWAP Instructions
  
  instruct bytes_reverse_int(iRegINoSp dst, iRegIorL2I src) %{
    match(Set dst (ReverseBytesI src));