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src/hotspot/cpu/aarch64/aarch64.ad

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8908 %}
8909 
8910 // TODO
8911 // implement storeImmF0 and storeFImmPacked
8912 
8913 // Store Double
8914 instruct storeD_volatile(vRegD src, /* sync_memory*/indirect mem)
8915 %{
8916   match(Set mem (StoreD mem src));
8917 
8918   ins_cost(VOLATILE_REF_COST);
8919   format %{ "stlrd  $src, $mem\t# double" %}
8920 
8921   ins_encode( aarch64_enc_fstlrd(src, mem) );
8922 
8923   ins_pipe(pipe_class_memory);
8924 %}
8925 
8926 //  ---------------- end of volatile loads and stores ----------------
8927 






































8928 // ============================================================================
8929 // BSWAP Instructions
8930 
8931 instruct bytes_reverse_int(iRegINoSp dst, iRegIorL2I src) %{
8932   match(Set dst (ReverseBytesI src));
8933 
8934   ins_cost(INSN_COST);
8935   format %{ "revw  $dst, $src" %}
8936 
8937   ins_encode %{
8938     __ revw(as_Register($dst$$reg), as_Register($src$$reg));
8939   %}
8940 
8941   ins_pipe(ialu_reg);
8942 %}
8943 
8944 instruct bytes_reverse_long(iRegLNoSp dst, iRegL src) %{
8945   match(Set dst (ReverseBytesL src));
8946 
8947   ins_cost(INSN_COST);




8908 %}
8909 
8910 // TODO
8911 // implement storeImmF0 and storeFImmPacked
8912 
8913 // Store Double
8914 instruct storeD_volatile(vRegD src, /* sync_memory*/indirect mem)
8915 %{
8916   match(Set mem (StoreD mem src));
8917 
8918   ins_cost(VOLATILE_REF_COST);
8919   format %{ "stlrd  $src, $mem\t# double" %}
8920 
8921   ins_encode( aarch64_enc_fstlrd(src, mem) );
8922 
8923   ins_pipe(pipe_class_memory);
8924 %}
8925 
8926 //  ---------------- end of volatile loads and stores ----------------
8927 
8928 instruct cacheWB(indirect addr)
8929 %{
8930   match(CacheWB addr);
8931 
8932   ins_cost(100);
8933   format %{"cache wb $addr" %}
8934   ins_encode %{
8935     assert($addr->index_position() < 0, "should be");
8936     assert($addr$$disp == 0, "should be");
8937     __ cache_wb(Address($addr$$base$$Register, 0));
8938   %}
8939   ins_pipe(pipe_slow); // XXX
8940 %}
8941 
8942 instruct cacheWBPreSync()
8943 %{
8944   match(CacheWBPreSync);
8945 
8946   ins_cost(100);
8947   format %{"cache wb presync" %}
8948   ins_encode %{
8949     __ cache_wbsync(true);
8950   %}
8951   ins_pipe(pipe_slow); // XXX
8952 %}
8953 
8954 instruct cacheWBPostSync()
8955 %{
8956   match(CacheWBPostSync);
8957 
8958   ins_cost(100);
8959   format %{"cache wb postsync" %}
8960   ins_encode %{
8961     __ cache_wbsync(false);
8962   %}
8963   ins_pipe(pipe_slow); // XXX
8964 %}
8965 
8966 // ============================================================================
8967 // BSWAP Instructions
8968 
8969 instruct bytes_reverse_int(iRegINoSp dst, iRegIorL2I src) %{
8970   match(Set dst (ReverseBytesI src));
8971 
8972   ins_cost(INSN_COST);
8973   format %{ "revw  $dst, $src" %}
8974 
8975   ins_encode %{
8976     __ revw(as_Register($dst$$reg), as_Register($src$$reg));
8977   %}
8978 
8979   ins_pipe(ialu_reg);
8980 %}
8981 
8982 instruct bytes_reverse_long(iRegLNoSp dst, iRegL src) %{
8983   match(Set dst (ReverseBytesL src));
8984 
8985   ins_cost(INSN_COST);


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