1 /*
   2  * Copyright (c) 1997, 2018, Oracle and/or its affiliates. All rights reserved.
   3  * Copyright (c) 2014, 2015, Red Hat Inc. All rights reserved.
   4  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   5  *
   6  * This code is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License version 2 only, as
   8  * published by the Free Software Foundation.
   9  *
  10  * This code is distributed in the hope that it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  13  * version 2 for more details (a copy is included in the LICENSE file that
  14  * accompanied this code).
  15  *
  16  * You should have received a copy of the GNU General Public License version
  17  * 2 along with this work; if not, write to the Free Software Foundation,
  18  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  19  *
  20  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  21  * or visit www.oracle.com if you need additional information or have any
  22  * questions.
  23  *
  24  */
  25 
  26 #ifndef CPU_AARCH64_VM_MACROASSEMBLER_AARCH64_HPP
  27 #define CPU_AARCH64_VM_MACROASSEMBLER_AARCH64_HPP
  28 
  29 #include "asm/assembler.hpp"
  30 
  31 // MacroAssembler extends Assembler by frequently used macros.
  32 //
  33 // Instructions for which a 'better' code sequence exists depending
  34 // on arguments should also go in here.
  35 
  36 class MacroAssembler: public Assembler {
  37   friend class LIR_Assembler;
  38 
  39  public:
  40   using Assembler::mov;
  41   using Assembler::movi;
  42 
  43  protected:
  44 
  45   // Support for VM calls
  46   //
  47   // This is the base routine called by the different versions of call_VM_leaf. The interpreter
  48   // may customize this version by overriding it for its purposes (e.g., to save/restore
  49   // additional registers when doing a VM call).
  50   virtual void call_VM_leaf_base(
  51     address entry_point,               // the entry point
  52     int     number_of_arguments,        // the number of arguments to pop after the call
  53     Label *retaddr = NULL
  54   );
  55 
  56   virtual void call_VM_leaf_base(
  57     address entry_point,               // the entry point
  58     int     number_of_arguments,        // the number of arguments to pop after the call
  59     Label &retaddr) {
  60     call_VM_leaf_base(entry_point, number_of_arguments, &retaddr);
  61   }
  62 
  63   // This is the base routine called by the different versions of call_VM. The interpreter
  64   // may customize this version by overriding it for its purposes (e.g., to save/restore
  65   // additional registers when doing a VM call).
  66   //
  67   // If no java_thread register is specified (noreg) than rthread will be used instead. call_VM_base
  68   // returns the register which contains the thread upon return. If a thread register has been
  69   // specified, the return value will correspond to that register. If no last_java_sp is specified
  70   // (noreg) than rsp will be used instead.
  71   virtual void call_VM_base(           // returns the register containing the thread upon return
  72     Register oop_result,               // where an oop-result ends up if any; use noreg otherwise
  73     Register java_thread,              // the thread if computed before     ; use noreg otherwise
  74     Register last_java_sp,             // to set up last_Java_frame in stubs; use noreg otherwise
  75     address  entry_point,              // the entry point
  76     int      number_of_arguments,      // the number of arguments (w/o thread) to pop after the call
  77     bool     check_exceptions          // whether to check for pending exceptions after return
  78   );
  79 
  80   void call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions = true);
  81 
  82   // True if an XOR can be used to expand narrow klass references.
  83   bool use_XOR_for_compressed_class_base;
  84 
  85  public:
  86   MacroAssembler(CodeBuffer* code) : Assembler(code) {
  87     use_XOR_for_compressed_class_base
  88       = (operand_valid_for_logical_immediate(false /*is32*/,
  89                                              (uint64_t)Universe::narrow_klass_base())
  90          && ((uint64_t)Universe::narrow_klass_base()
  91              > (1UL << log2_intptr(Universe::narrow_klass_range()))));
  92   }
  93 
  94  // These routines should emit JVMTI PopFrame and ForceEarlyReturn handling code.
  95  // The implementation is only non-empty for the InterpreterMacroAssembler,
  96  // as only the interpreter handles PopFrame and ForceEarlyReturn requests.
  97  virtual void check_and_handle_popframe(Register java_thread);
  98  virtual void check_and_handle_earlyret(Register java_thread);
  99 
 100   void safepoint_poll(Label& slow_path);
 101   void safepoint_poll_acquire(Label& slow_path);
 102 
 103   // Biased locking support
 104   // lock_reg and obj_reg must be loaded up with the appropriate values.
 105   // swap_reg is killed.
 106   // tmp_reg must be supplied and must not be rscratch1 or rscratch2
 107   // Optional slow case is for implementations (interpreter and C1) which branch to
 108   // slow case directly. Leaves condition codes set for C2's Fast_Lock node.
 109   // Returns offset of first potentially-faulting instruction for null
 110   // check info (currently consumed only by C1). If
 111   // swap_reg_contains_mark is true then returns -1 as it is assumed
 112   // the calling code has already passed any potential faults.
 113   int biased_locking_enter(Register lock_reg, Register obj_reg,
 114                            Register swap_reg, Register tmp_reg,
 115                            bool swap_reg_contains_mark,
 116                            Label& done, Label* slow_case = NULL,
 117                            BiasedLockingCounters* counters = NULL);
 118   void biased_locking_exit (Register obj_reg, Register temp_reg, Label& done);
 119 
 120 
 121   // Helper functions for statistics gathering.
 122   // Unconditional atomic increment.
 123   void atomic_incw(Register counter_addr, Register tmp, Register tmp2);
 124   void atomic_incw(Address counter_addr, Register tmp1, Register tmp2, Register tmp3) {
 125     lea(tmp1, counter_addr);
 126     atomic_incw(tmp1, tmp2, tmp3);
 127   }
 128   // Load Effective Address
 129   void lea(Register r, const Address &a) {
 130     InstructionMark im(this);
 131     code_section()->relocate(inst_mark(), a.rspec());
 132     a.lea(this, r);
 133   }
 134 
 135   void addmw(Address a, Register incr, Register scratch) {
 136     ldrw(scratch, a);
 137     addw(scratch, scratch, incr);
 138     strw(scratch, a);
 139   }
 140 
 141   // Add constant to memory word
 142   void addmw(Address a, int imm, Register scratch) {
 143     ldrw(scratch, a);
 144     if (imm > 0)
 145       addw(scratch, scratch, (unsigned)imm);
 146     else
 147       subw(scratch, scratch, (unsigned)-imm);
 148     strw(scratch, a);
 149   }
 150 
 151   void bind(Label& L) {
 152     Assembler::bind(L);
 153     code()->clear_last_insn();
 154   }
 155 
 156   void membar(Membar_mask_bits order_constraint);
 157 
 158   using Assembler::ldr;
 159   using Assembler::str;
 160 
 161   void ldr(Register Rx, const Address &adr);
 162   void ldrw(Register Rw, const Address &adr);
 163   void str(Register Rx, const Address &adr);
 164   void strw(Register Rx, const Address &adr);
 165 
 166   // Frame creation and destruction shared between JITs.
 167   void build_frame(int framesize);
 168   void remove_frame(int framesize);
 169 
 170   virtual void _call_Unimplemented(address call_site) {
 171     mov(rscratch2, call_site);
 172     haltsim();
 173   }
 174 
 175 #define call_Unimplemented() _call_Unimplemented((address)__PRETTY_FUNCTION__)
 176 
 177   virtual void notify(int type);
 178 
 179   // aliases defined in AARCH64 spec
 180 
 181   template<class T>
 182   inline void cmpw(Register Rd, T imm)  { subsw(zr, Rd, imm); }
 183 
 184   inline void cmp(Register Rd, unsigned char imm8)  { subs(zr, Rd, imm8); }
 185   inline void cmp(Register Rd, unsigned imm) __attribute__ ((deprecated));
 186 
 187   inline void cmnw(Register Rd, unsigned imm) { addsw(zr, Rd, imm); }
 188   inline void cmn(Register Rd, unsigned imm) { adds(zr, Rd, imm); }
 189 
 190   void cset(Register Rd, Assembler::Condition cond) {
 191     csinc(Rd, zr, zr, ~cond);
 192   }
 193   void csetw(Register Rd, Assembler::Condition cond) {
 194     csincw(Rd, zr, zr, ~cond);
 195   }
 196 
 197   void cneg(Register Rd, Register Rn, Assembler::Condition cond) {
 198     csneg(Rd, Rn, Rn, ~cond);
 199   }
 200   void cnegw(Register Rd, Register Rn, Assembler::Condition cond) {
 201     csnegw(Rd, Rn, Rn, ~cond);
 202   }
 203 
 204   inline void movw(Register Rd, Register Rn) {
 205     if (Rd == sp || Rn == sp) {
 206       addw(Rd, Rn, 0U);
 207     } else {
 208       orrw(Rd, zr, Rn);
 209     }
 210   }
 211   inline void mov(Register Rd, Register Rn) {
 212     assert(Rd != r31_sp && Rn != r31_sp, "should be");
 213     if (Rd == Rn) {
 214     } else if (Rd == sp || Rn == sp) {
 215       add(Rd, Rn, 0U);
 216     } else {
 217       orr(Rd, zr, Rn);
 218     }
 219   }
 220 
 221   inline void moviw(Register Rd, unsigned imm) { orrw(Rd, zr, imm); }
 222   inline void movi(Register Rd, unsigned imm) { orr(Rd, zr, imm); }
 223 
 224   inline void tstw(Register Rd, Register Rn) { andsw(zr, Rd, Rn); }
 225   inline void tst(Register Rd, Register Rn) { ands(zr, Rd, Rn); }
 226 
 227   inline void tstw(Register Rd, uint64_t imm) { andsw(zr, Rd, imm); }
 228   inline void tst(Register Rd, uint64_t imm) { ands(zr, Rd, imm); }
 229 
 230   inline void bfiw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 231     bfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1));
 232   }
 233   inline void bfi(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 234     bfm(Rd, Rn, ((64 - lsb) & 63), (width - 1));
 235   }
 236 
 237   inline void bfxilw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 238     bfmw(Rd, Rn, lsb, (lsb + width - 1));
 239   }
 240   inline void bfxil(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 241     bfm(Rd, Rn, lsb , (lsb + width - 1));
 242   }
 243 
 244   inline void sbfizw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 245     sbfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1));
 246   }
 247   inline void sbfiz(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 248     sbfm(Rd, Rn, ((64 - lsb) & 63), (width - 1));
 249   }
 250 
 251   inline void sbfxw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 252     sbfmw(Rd, Rn, lsb, (lsb + width - 1));
 253   }
 254   inline void sbfx(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 255     sbfm(Rd, Rn, lsb , (lsb + width - 1));
 256   }
 257 
 258   inline void ubfizw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 259     ubfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1));
 260   }
 261   inline void ubfiz(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 262     ubfm(Rd, Rn, ((64 - lsb) & 63), (width - 1));
 263   }
 264 
 265   inline void ubfxw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 266     ubfmw(Rd, Rn, lsb, (lsb + width - 1));
 267   }
 268   inline void ubfx(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 269     ubfm(Rd, Rn, lsb , (lsb + width - 1));
 270   }
 271 
 272   inline void asrw(Register Rd, Register Rn, unsigned imm) {
 273     sbfmw(Rd, Rn, imm, 31);
 274   }
 275 
 276   inline void asr(Register Rd, Register Rn, unsigned imm) {
 277     sbfm(Rd, Rn, imm, 63);
 278   }
 279 
 280   inline void lslw(Register Rd, Register Rn, unsigned imm) {
 281     ubfmw(Rd, Rn, ((32 - imm) & 31), (31 - imm));
 282   }
 283 
 284   inline void lsl(Register Rd, Register Rn, unsigned imm) {
 285     ubfm(Rd, Rn, ((64 - imm) & 63), (63 - imm));
 286   }
 287 
 288   inline void lsrw(Register Rd, Register Rn, unsigned imm) {
 289     ubfmw(Rd, Rn, imm, 31);
 290   }
 291 
 292   inline void lsr(Register Rd, Register Rn, unsigned imm) {
 293     ubfm(Rd, Rn, imm, 63);
 294   }
 295 
 296   inline void rorw(Register Rd, Register Rn, unsigned imm) {
 297     extrw(Rd, Rn, Rn, imm);
 298   }
 299 
 300   inline void ror(Register Rd, Register Rn, unsigned imm) {
 301     extr(Rd, Rn, Rn, imm);
 302   }
 303 
 304   inline void sxtbw(Register Rd, Register Rn) {
 305     sbfmw(Rd, Rn, 0, 7);
 306   }
 307   inline void sxthw(Register Rd, Register Rn) {
 308     sbfmw(Rd, Rn, 0, 15);
 309   }
 310   inline void sxtb(Register Rd, Register Rn) {
 311     sbfm(Rd, Rn, 0, 7);
 312   }
 313   inline void sxth(Register Rd, Register Rn) {
 314     sbfm(Rd, Rn, 0, 15);
 315   }
 316   inline void sxtw(Register Rd, Register Rn) {
 317     sbfm(Rd, Rn, 0, 31);
 318   }
 319 
 320   inline void uxtbw(Register Rd, Register Rn) {
 321     ubfmw(Rd, Rn, 0, 7);
 322   }
 323   inline void uxthw(Register Rd, Register Rn) {
 324     ubfmw(Rd, Rn, 0, 15);
 325   }
 326   inline void uxtb(Register Rd, Register Rn) {
 327     ubfm(Rd, Rn, 0, 7);
 328   }
 329   inline void uxth(Register Rd, Register Rn) {
 330     ubfm(Rd, Rn, 0, 15);
 331   }
 332   inline void uxtw(Register Rd, Register Rn) {
 333     ubfm(Rd, Rn, 0, 31);
 334   }
 335 
 336   inline void cmnw(Register Rn, Register Rm) {
 337     addsw(zr, Rn, Rm);
 338   }
 339   inline void cmn(Register Rn, Register Rm) {
 340     adds(zr, Rn, Rm);
 341   }
 342 
 343   inline void cmpw(Register Rn, Register Rm) {
 344     subsw(zr, Rn, Rm);
 345   }
 346   inline void cmp(Register Rn, Register Rm) {
 347     subs(zr, Rn, Rm);
 348   }
 349 
 350   inline void negw(Register Rd, Register Rn) {
 351     subw(Rd, zr, Rn);
 352   }
 353 
 354   inline void neg(Register Rd, Register Rn) {
 355     sub(Rd, zr, Rn);
 356   }
 357 
 358   inline void negsw(Register Rd, Register Rn) {
 359     subsw(Rd, zr, Rn);
 360   }
 361 
 362   inline void negs(Register Rd, Register Rn) {
 363     subs(Rd, zr, Rn);
 364   }
 365 
 366   inline void cmnw(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
 367     addsw(zr, Rn, Rm, kind, shift);
 368   }
 369   inline void cmn(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
 370     adds(zr, Rn, Rm, kind, shift);
 371   }
 372 
 373   inline void cmpw(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
 374     subsw(zr, Rn, Rm, kind, shift);
 375   }
 376   inline void cmp(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
 377     subs(zr, Rn, Rm, kind, shift);
 378   }
 379 
 380   inline void negw(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
 381     subw(Rd, zr, Rn, kind, shift);
 382   }
 383 
 384   inline void neg(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
 385     sub(Rd, zr, Rn, kind, shift);
 386   }
 387 
 388   inline void negsw(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
 389     subsw(Rd, zr, Rn, kind, shift);
 390   }
 391 
 392   inline void negs(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
 393     subs(Rd, zr, Rn, kind, shift);
 394   }
 395 
 396   inline void mnegw(Register Rd, Register Rn, Register Rm) {
 397     msubw(Rd, Rn, Rm, zr);
 398   }
 399   inline void mneg(Register Rd, Register Rn, Register Rm) {
 400     msub(Rd, Rn, Rm, zr);
 401   }
 402 
 403   inline void mulw(Register Rd, Register Rn, Register Rm) {
 404     maddw(Rd, Rn, Rm, zr);
 405   }
 406   inline void mul(Register Rd, Register Rn, Register Rm) {
 407     madd(Rd, Rn, Rm, zr);
 408   }
 409 
 410   inline void smnegl(Register Rd, Register Rn, Register Rm) {
 411     smsubl(Rd, Rn, Rm, zr);
 412   }
 413   inline void smull(Register Rd, Register Rn, Register Rm) {
 414     smaddl(Rd, Rn, Rm, zr);
 415   }
 416 
 417   inline void umnegl(Register Rd, Register Rn, Register Rm) {
 418     umsubl(Rd, Rn, Rm, zr);
 419   }
 420   inline void umull(Register Rd, Register Rn, Register Rm) {
 421     umaddl(Rd, Rn, Rm, zr);
 422   }
 423 
 424 #define WRAP(INSN)                                                            \
 425   void INSN(Register Rd, Register Rn, Register Rm, Register Ra) {             \
 426     if ((VM_Version::features() & VM_Version::CPU_A53MAC) && Ra != zr)        \
 427       nop();                                                                  \
 428     Assembler::INSN(Rd, Rn, Rm, Ra);                                          \
 429   }
 430 
 431   WRAP(madd) WRAP(msub) WRAP(maddw) WRAP(msubw)
 432   WRAP(smaddl) WRAP(smsubl) WRAP(umaddl) WRAP(umsubl)
 433 #undef WRAP
 434 
 435 
 436   // macro assembly operations needed for aarch64
 437 
 438   // first two private routines for loading 32 bit or 64 bit constants
 439 private:
 440 
 441   void mov_immediate64(Register dst, u_int64_t imm64);
 442   void mov_immediate32(Register dst, u_int32_t imm32);
 443 
 444   int push(unsigned int bitset, Register stack);
 445   int pop(unsigned int bitset, Register stack);
 446 
 447   void mov(Register dst, Address a);
 448 
 449 public:
 450   void push(RegSet regs, Register stack) { if (regs.bits()) push(regs.bits(), stack); }
 451   void pop(RegSet regs, Register stack) { if (regs.bits()) pop(regs.bits(), stack); }
 452 
 453   // Push and pop everything that might be clobbered by a native
 454   // runtime call except rscratch1 and rscratch2.  (They are always
 455   // scratch, so we don't have to protect them.)  Only save the lower
 456   // 64 bits of each vector register.
 457   void push_call_clobbered_registers();
 458   void pop_call_clobbered_registers();
 459 
 460   // now mov instructions for loading absolute addresses and 32 or
 461   // 64 bit integers
 462 
 463   inline void mov(Register dst, address addr)
 464   {
 465     mov_immediate64(dst, (u_int64_t)addr);
 466   }
 467 
 468   inline void mov(Register dst, u_int64_t imm64)
 469   {
 470     mov_immediate64(dst, imm64);
 471   }
 472 
 473   inline void movw(Register dst, u_int32_t imm32)
 474   {
 475     mov_immediate32(dst, imm32);
 476   }
 477 
 478   inline void mov(Register dst, long l)
 479   {
 480     mov(dst, (u_int64_t)l);
 481   }
 482 
 483   inline void mov(Register dst, int i)
 484   {
 485     mov(dst, (long)i);
 486   }
 487 
 488   void mov(Register dst, RegisterOrConstant src) {
 489     if (src.is_register())
 490       mov(dst, src.as_register());
 491     else
 492       mov(dst, src.as_constant());
 493   }
 494 
 495   void movptr(Register r, uintptr_t imm64);
 496 
 497   void mov(FloatRegister Vd, SIMD_Arrangement T, u_int32_t imm32);
 498 
 499   void mov(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn) {
 500     orr(Vd, T, Vn, Vn);
 501   }
 502 
 503 public:
 504 
 505   // Generalized Test Bit And Branch, including a "far" variety which
 506   // spans more than 32KiB.
 507   void tbr(Condition cond, Register Rt, int bitpos, Label &dest, bool far = false) {
 508     assert(cond == EQ || cond == NE, "must be");
 509 
 510     if (far)
 511       cond = ~cond;
 512 
 513     void (Assembler::* branch)(Register Rt, int bitpos, Label &L);
 514     if (cond == Assembler::EQ)
 515       branch = &Assembler::tbz;
 516     else
 517       branch = &Assembler::tbnz;
 518 
 519     if (far) {
 520       Label L;
 521       (this->*branch)(Rt, bitpos, L);
 522       b(dest);
 523       bind(L);
 524     } else {
 525       (this->*branch)(Rt, bitpos, dest);
 526     }
 527   }
 528 
 529   // macro instructions for accessing and updating floating point
 530   // status register
 531   //
 532   // FPSR : op1 == 011
 533   //        CRn == 0100
 534   //        CRm == 0100
 535   //        op2 == 001
 536 
 537   inline void get_fpsr(Register reg)
 538   {
 539     mrs(0b11, 0b0100, 0b0100, 0b001, reg);
 540   }
 541 
 542   inline void set_fpsr(Register reg)
 543   {
 544     msr(0b011, 0b0100, 0b0100, 0b001, reg);
 545   }
 546 
 547   inline void clear_fpsr()
 548   {
 549     msr(0b011, 0b0100, 0b0100, 0b001, zr);
 550   }
 551 
 552   // DCZID_EL0: op1 == 011
 553   //            CRn == 0000
 554   //            CRm == 0000
 555   //            op2 == 111
 556   inline void get_dczid_el0(Register reg)
 557   {
 558     mrs(0b011, 0b0000, 0b0000, 0b111, reg);
 559   }
 560 
 561   // CTR_EL0:   op1 == 011
 562   //            CRn == 0000
 563   //            CRm == 0000
 564   //            op2 == 001
 565   inline void get_ctr_el0(Register reg)
 566   {
 567     mrs(0b011, 0b0000, 0b0000, 0b001, reg);
 568   }
 569 
 570   // idiv variant which deals with MINLONG as dividend and -1 as divisor
 571   int corrected_idivl(Register result, Register ra, Register rb,
 572                       bool want_remainder, Register tmp = rscratch1);
 573   int corrected_idivq(Register result, Register ra, Register rb,
 574                       bool want_remainder, Register tmp = rscratch1);
 575 
 576   // Support for NULL-checks
 577   //
 578   // Generates code that causes a NULL OS exception if the content of reg is NULL.
 579   // If the accessed location is M[reg + offset] and the offset is known, provide the
 580   // offset. No explicit code generation is needed if the offset is within a certain
 581   // range (0 <= offset <= page_size).
 582 
 583   virtual void null_check(Register reg, int offset = -1);
 584   static bool needs_explicit_null_check(intptr_t offset);
 585 
 586   static address target_addr_for_insn(address insn_addr, unsigned insn);
 587   static address target_addr_for_insn(address insn_addr) {
 588     unsigned insn = *(unsigned*)insn_addr;
 589     return target_addr_for_insn(insn_addr, insn);
 590   }
 591 
 592   // Required platform-specific helpers for Label::patch_instructions.
 593   // They _shadow_ the declarations in AbstractAssembler, which are undefined.
 594   static int pd_patch_instruction_size(address branch, address target);
 595   static void pd_patch_instruction(address branch, address target) {
 596     pd_patch_instruction_size(branch, target);
 597   }
 598   static address pd_call_destination(address branch) {
 599     return target_addr_for_insn(branch);
 600   }
 601 #ifndef PRODUCT
 602   static void pd_print_patched_instruction(address branch);
 603 #endif
 604 
 605   static int patch_oop(address insn_addr, address o);
 606   static int patch_narrow_klass(address insn_addr, narrowKlass n);
 607 
 608   address emit_trampoline_stub(int insts_call_instruction_offset, address target);
 609 
 610   // The following 4 methods return the offset of the appropriate move instruction
 611 
 612   // Support for fast byte/short loading with zero extension (depending on particular CPU)
 613   int load_unsigned_byte(Register dst, Address src);
 614   int load_unsigned_short(Register dst, Address src);
 615 
 616   // Support for fast byte/short loading with sign extension (depending on particular CPU)
 617   int load_signed_byte(Register dst, Address src);
 618   int load_signed_short(Register dst, Address src);
 619 
 620   int load_signed_byte32(Register dst, Address src);
 621   int load_signed_short32(Register dst, Address src);
 622 
 623   // Support for sign-extension (hi:lo = extend_sign(lo))
 624   void extend_sign(Register hi, Register lo);
 625 
 626   // Load and store values by size and signed-ness
 627   void load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2 = noreg);
 628   void store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2 = noreg);
 629 
 630   // Support for inc/dec with optimal instruction selection depending on value
 631 
 632   // x86_64 aliases an unqualified register/address increment and
 633   // decrement to call incrementq and decrementq but also supports
 634   // explicitly sized calls to incrementq/decrementq or
 635   // incrementl/decrementl
 636 
 637   // for aarch64 the proper convention would be to use
 638   // increment/decrement for 64 bit operatons and
 639   // incrementw/decrementw for 32 bit operations. so when porting
 640   // x86_64 code we can leave calls to increment/decrement as is,
 641   // replace incrementq/decrementq with increment/decrement and
 642   // replace incrementl/decrementl with incrementw/decrementw.
 643 
 644   // n.b. increment/decrement calls with an Address destination will
 645   // need to use a scratch register to load the value to be
 646   // incremented. increment/decrement calls which add or subtract a
 647   // constant value greater than 2^12 will need to use a 2nd scratch
 648   // register to hold the constant. so, a register increment/decrement
 649   // may trash rscratch2 and an address increment/decrement trash
 650   // rscratch and rscratch2
 651 
 652   void decrementw(Address dst, int value = 1);
 653   void decrementw(Register reg, int value = 1);
 654 
 655   void decrement(Register reg, int value = 1);
 656   void decrement(Address dst, int value = 1);
 657 
 658   void incrementw(Address dst, int value = 1);
 659   void incrementw(Register reg, int value = 1);
 660 
 661   void increment(Register reg, int value = 1);
 662   void increment(Address dst, int value = 1);
 663 
 664 
 665   // Alignment
 666   void align(int modulus);
 667 
 668   // Stack frame creation/removal
 669   void enter()
 670   {
 671     stp(rfp, lr, Address(pre(sp, -2 * wordSize)));
 672     mov(rfp, sp);
 673   }
 674   void leave()
 675   {
 676     mov(sp, rfp);
 677     ldp(rfp, lr, Address(post(sp, 2 * wordSize)));
 678   }
 679 
 680   // Support for getting the JavaThread pointer (i.e.; a reference to thread-local information)
 681   // The pointer will be loaded into the thread register.
 682   void get_thread(Register thread);
 683 
 684 
 685   // Support for VM calls
 686   //
 687   // It is imperative that all calls into the VM are handled via the call_VM macros.
 688   // They make sure that the stack linkage is setup correctly. call_VM's correspond
 689   // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points.
 690 
 691 
 692   void call_VM(Register oop_result,
 693                address entry_point,
 694                bool check_exceptions = true);
 695   void call_VM(Register oop_result,
 696                address entry_point,
 697                Register arg_1,
 698                bool check_exceptions = true);
 699   void call_VM(Register oop_result,
 700                address entry_point,
 701                Register arg_1, Register arg_2,
 702                bool check_exceptions = true);
 703   void call_VM(Register oop_result,
 704                address entry_point,
 705                Register arg_1, Register arg_2, Register arg_3,
 706                bool check_exceptions = true);
 707 
 708   // Overloadings with last_Java_sp
 709   void call_VM(Register oop_result,
 710                Register last_java_sp,
 711                address entry_point,
 712                int number_of_arguments = 0,
 713                bool check_exceptions = true);
 714   void call_VM(Register oop_result,
 715                Register last_java_sp,
 716                address entry_point,
 717                Register arg_1, bool
 718                check_exceptions = true);
 719   void call_VM(Register oop_result,
 720                Register last_java_sp,
 721                address entry_point,
 722                Register arg_1, Register arg_2,
 723                bool check_exceptions = true);
 724   void call_VM(Register oop_result,
 725                Register last_java_sp,
 726                address entry_point,
 727                Register arg_1, Register arg_2, Register arg_3,
 728                bool check_exceptions = true);
 729 
 730   void get_vm_result  (Register oop_result, Register thread);
 731   void get_vm_result_2(Register metadata_result, Register thread);
 732 
 733   // These always tightly bind to MacroAssembler::call_VM_base
 734   // bypassing the virtual implementation
 735   void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments = 0, bool check_exceptions = true);
 736   void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions = true);
 737   void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true);
 738   void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true);
 739   void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4, bool check_exceptions = true);
 740 
 741   void call_VM_leaf(address entry_point,
 742                     int number_of_arguments = 0);
 743   void call_VM_leaf(address entry_point,
 744                     Register arg_1);
 745   void call_VM_leaf(address entry_point,
 746                     Register arg_1, Register arg_2);
 747   void call_VM_leaf(address entry_point,
 748                     Register arg_1, Register arg_2, Register arg_3);
 749 
 750   // These always tightly bind to MacroAssembler::call_VM_leaf_base
 751   // bypassing the virtual implementation
 752   void super_call_VM_leaf(address entry_point);
 753   void super_call_VM_leaf(address entry_point, Register arg_1);
 754   void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2);
 755   void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3);
 756   void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4);
 757 
 758   // last Java Frame (fills frame anchor)
 759   void set_last_Java_frame(Register last_java_sp,
 760                            Register last_java_fp,
 761                            address last_java_pc,
 762                            Register scratch);
 763 
 764   void set_last_Java_frame(Register last_java_sp,
 765                            Register last_java_fp,
 766                            Label &last_java_pc,
 767                            Register scratch);
 768 
 769   void set_last_Java_frame(Register last_java_sp,
 770                            Register last_java_fp,
 771                            Register last_java_pc,
 772                            Register scratch);
 773 
 774   void reset_last_Java_frame(Register thread);
 775 
 776   // thread in the default location (rthread)
 777   void reset_last_Java_frame(bool clear_fp);
 778 
 779   // Stores
 780   void store_check(Register obj);                // store check for obj - register is destroyed afterwards
 781   void store_check(Register obj, Address dst);   // same as above, dst is exact store location (reg. is destroyed)
 782 
 783   void resolve_jobject(Register value, Register thread, Register tmp);
 784 
 785   // oop manipulations
 786   void load_klass(Register dst, Register src);
 787   void store_klass(Register dst, Register src);
 788   void cmp_klass(Register oop, Register trial_klass, Register tmp);
 789 
 790   void resolve_oop_handle(Register result, Register tmp = r5);
 791   void load_mirror(Register dst, Register method, Register tmp = r5);
 792 
 793   void access_load_at(BasicType type, DecoratorSet decorators, Register dst, Address src,
 794                       Register tmp1, Register tmp_thread);
 795 
 796   void access_store_at(BasicType type, DecoratorSet decorators, Address dst, Register src,
 797                        Register tmp1, Register tmp_thread);
 798 
 799   // Resolves obj for access. Result is placed in the same register.
 800   // All other registers are preserved.
 801   void resolve(DecoratorSet decorators, Register obj);
 802 
 803   void load_heap_oop(Register dst, Address src, Register tmp1 = noreg,
 804                      Register thread_tmp = noreg, DecoratorSet decorators = 0);
 805 
 806   void load_heap_oop_not_null(Register dst, Address src, Register tmp1 = noreg,
 807                               Register thread_tmp = noreg, DecoratorSet decorators = 0);
 808   void store_heap_oop(Address dst, Register src, Register tmp1 = noreg,
 809                       Register tmp_thread = noreg, DecoratorSet decorators = 0);
 810 
 811   // currently unimplemented
 812   // Used for storing NULL. All other oop constants should be
 813   // stored using routines that take a jobject.
 814   void store_heap_oop_null(Address dst);
 815 
 816   void load_prototype_header(Register dst, Register src);
 817 
 818   void store_klass_gap(Register dst, Register src);
 819 
 820   // This dummy is to prevent a call to store_heap_oop from
 821   // converting a zero (like NULL) into a Register by giving
 822   // the compiler two choices it can't resolve
 823 
 824   void store_heap_oop(Address dst, void* dummy);
 825 
 826   void encode_heap_oop(Register d, Register s);
 827   void encode_heap_oop(Register r) { encode_heap_oop(r, r); }
 828   void decode_heap_oop(Register d, Register s);
 829   void decode_heap_oop(Register r) { decode_heap_oop(r, r); }
 830   void encode_heap_oop_not_null(Register r);
 831   void decode_heap_oop_not_null(Register r);
 832   void encode_heap_oop_not_null(Register dst, Register src);
 833   void decode_heap_oop_not_null(Register dst, Register src);
 834 
 835   void set_narrow_oop(Register dst, jobject obj);
 836 
 837   void encode_klass_not_null(Register r);
 838   void decode_klass_not_null(Register r);
 839   void encode_klass_not_null(Register dst, Register src);
 840   void decode_klass_not_null(Register dst, Register src);
 841 
 842   void set_narrow_klass(Register dst, Klass* k);
 843 
 844   // if heap base register is used - reinit it with the correct value
 845   void reinit_heapbase();
 846 
 847   DEBUG_ONLY(void verify_heapbase(const char* msg);)
 848 
 849   void push_CPU_state(bool save_vectors = false);
 850   void pop_CPU_state(bool restore_vectors = false) ;
 851 
 852   // Round up to a power of two
 853   void round_to(Register reg, int modulus);
 854 
 855   // allocation
 856   void eden_allocate(
 857     Register obj,                      // result: pointer to object after successful allocation
 858     Register var_size_in_bytes,        // object size in bytes if unknown at compile time; invalid otherwise
 859     int      con_size_in_bytes,        // object size in bytes if   known at compile time
 860     Register t1,                       // temp register
 861     Label&   slow_case                 // continuation point if fast allocation fails
 862   );
 863   void tlab_allocate(
 864     Register obj,                      // result: pointer to object after successful allocation
 865     Register var_size_in_bytes,        // object size in bytes if unknown at compile time; invalid otherwise
 866     int      con_size_in_bytes,        // object size in bytes if   known at compile time
 867     Register t1,                       // temp register
 868     Register t2,                       // temp register
 869     Label&   slow_case                 // continuation point if fast allocation fails
 870   );
 871   void zero_memory(Register addr, Register len, Register t1);
 872   void verify_tlab();
 873 
 874   // interface method calling
 875   void lookup_interface_method(Register recv_klass,
 876                                Register intf_klass,
 877                                RegisterOrConstant itable_index,
 878                                Register method_result,
 879                                Register scan_temp,
 880                                Label& no_such_interface,
 881                    bool return_method = true);
 882 
 883   // virtual method calling
 884   // n.b. x86 allows RegisterOrConstant for vtable_index
 885   void lookup_virtual_method(Register recv_klass,
 886                              RegisterOrConstant vtable_index,
 887                              Register method_result);
 888 
 889   // Test sub_klass against super_klass, with fast and slow paths.
 890 
 891   // The fast path produces a tri-state answer: yes / no / maybe-slow.
 892   // One of the three labels can be NULL, meaning take the fall-through.
 893   // If super_check_offset is -1, the value is loaded up from super_klass.
 894   // No registers are killed, except temp_reg.
 895   void check_klass_subtype_fast_path(Register sub_klass,
 896                                      Register super_klass,
 897                                      Register temp_reg,
 898                                      Label* L_success,
 899                                      Label* L_failure,
 900                                      Label* L_slow_path,
 901                 RegisterOrConstant super_check_offset = RegisterOrConstant(-1));
 902 
 903   // The rest of the type check; must be wired to a corresponding fast path.
 904   // It does not repeat the fast path logic, so don't use it standalone.
 905   // The temp_reg and temp2_reg can be noreg, if no temps are available.
 906   // Updates the sub's secondary super cache as necessary.
 907   // If set_cond_codes, condition codes will be Z on success, NZ on failure.
 908   void check_klass_subtype_slow_path(Register sub_klass,
 909                                      Register super_klass,
 910                                      Register temp_reg,
 911                                      Register temp2_reg,
 912                                      Label* L_success,
 913                                      Label* L_failure,
 914                                      bool set_cond_codes = false);
 915 
 916   // Simplified, combined version, good for typical uses.
 917   // Falls through on failure.
 918   void check_klass_subtype(Register sub_klass,
 919                            Register super_klass,
 920                            Register temp_reg,
 921                            Label& L_success);
 922 
 923   Address argument_address(RegisterOrConstant arg_slot, int extra_slot_offset = 0);
 924 
 925 
 926   // Debugging
 927 
 928   // only if +VerifyOops
 929   void verify_oop(Register reg, const char* s = "broken oop");
 930   void verify_oop_addr(Address addr, const char * s = "broken oop addr");
 931 
 932 // TODO: verify method and klass metadata (compare against vptr?)
 933   void _verify_method_ptr(Register reg, const char * msg, const char * file, int line) {}
 934   void _verify_klass_ptr(Register reg, const char * msg, const char * file, int line){}
 935 
 936 #define verify_method_ptr(reg) _verify_method_ptr(reg, "broken method " #reg, __FILE__, __LINE__)
 937 #define verify_klass_ptr(reg) _verify_klass_ptr(reg, "broken klass " #reg, __FILE__, __LINE__)
 938 
 939   // only if +VerifyFPU
 940   void verify_FPU(int stack_depth, const char* s = "illegal FPU state");
 941 
 942   // prints msg, dumps registers and stops execution
 943   void stop(const char* msg);
 944 
 945   // prints msg and continues
 946   void warn(const char* msg);
 947 
 948   static void debug64(char* msg, int64_t pc, int64_t regs[]);
 949 
 950   void untested()                                { stop("untested"); }
 951 
 952   void unimplemented(const char* what = "");
 953 
 954   void should_not_reach_here()                   { stop("should not reach here"); }
 955 
 956   // Stack overflow checking
 957   void bang_stack_with_offset(int offset) {
 958     // stack grows down, caller passes positive offset
 959     assert(offset > 0, "must bang with negative offset");
 960     sub(rscratch2, sp, offset);
 961     str(zr, Address(rscratch2));
 962   }
 963 
 964   // Writes to stack successive pages until offset reached to check for
 965   // stack overflow + shadow pages.  Also, clobbers tmp
 966   void bang_stack_size(Register size, Register tmp);
 967 
 968   // Check for reserved stack access in method being exited (for JIT)
 969   void reserved_stack_check();
 970 
 971   virtual RegisterOrConstant delayed_value_impl(intptr_t* delayed_value_addr,
 972                                                 Register tmp,
 973                                                 int offset);
 974 
 975   // Support for serializing memory accesses between threads
 976   void serialize_memory(Register thread, Register tmp);
 977 
 978   // Arithmetics
 979 
 980   void addptr(const Address &dst, int32_t src);
 981   void cmpptr(Register src1, Address src2);
 982 
 983   void cmpoop(Register obj1, Register obj2);
 984 
 985   // Various forms of CAS
 986 
 987   void cmpxchg_obj_header(Register oldv, Register newv, Register obj, Register tmp,
 988                           Label &suceed, Label *fail);
 989   void cmpxchgptr(Register oldv, Register newv, Register addr, Register tmp,
 990                   Label &suceed, Label *fail);
 991 
 992   void cmpxchgw(Register oldv, Register newv, Register addr, Register tmp,
 993                   Label &suceed, Label *fail);
 994 
 995   void atomic_add(Register prev, RegisterOrConstant incr, Register addr);
 996   void atomic_addw(Register prev, RegisterOrConstant incr, Register addr);
 997   void atomic_addal(Register prev, RegisterOrConstant incr, Register addr);
 998   void atomic_addalw(Register prev, RegisterOrConstant incr, Register addr);
 999 
1000   void atomic_xchg(Register prev, Register newv, Register addr);
1001   void atomic_xchgw(Register prev, Register newv, Register addr);
1002   void atomic_xchgal(Register prev, Register newv, Register addr);
1003   void atomic_xchgalw(Register prev, Register newv, Register addr);
1004 
1005   void orptr(Address adr, RegisterOrConstant src) {
1006     ldr(rscratch1, adr);
1007     if (src.is_register())
1008       orr(rscratch1, rscratch1, src.as_register());
1009     else
1010       orr(rscratch1, rscratch1, src.as_constant());
1011     str(rscratch1, adr);
1012   }
1013 
1014   // A generic CAS; success or failure is in the EQ flag.
1015   // Clobbers rscratch1
1016   void cmpxchg(Register addr, Register expected, Register new_val,
1017                enum operand_size size,
1018                bool acquire, bool release, bool weak,
1019                Register result);
1020 
1021   // Calls
1022 
1023   address trampoline_call(Address entry, CodeBuffer *cbuf = NULL);
1024 
1025   static bool far_branches() {
1026     return ReservedCodeCacheSize > branch_range || UseAOT;
1027   }
1028 
1029   // Jumps that can reach anywhere in the code cache.
1030   // Trashes tmp.
1031   void far_call(Address entry, CodeBuffer *cbuf = NULL, Register tmp = rscratch1);
1032   void far_jump(Address entry, CodeBuffer *cbuf = NULL, Register tmp = rscratch1);
1033 
1034   static int far_branch_size() {
1035     if (far_branches()) {
1036       return 3 * 4;  // adrp, add, br
1037     } else {
1038       return 4;
1039     }
1040   }
1041 
1042   // Emit the CompiledIC call idiom
1043   address ic_call(address entry, jint method_index = 0);
1044 
1045 public:
1046 
1047   // Data
1048 
1049   void mov_metadata(Register dst, Metadata* obj);
1050   Address allocate_metadata_address(Metadata* obj);
1051   Address constant_oop_address(jobject obj);
1052 
1053   void movoop(Register dst, jobject obj, bool immediate = false);
1054 
1055   // CRC32 code for java.util.zip.CRC32::updateBytes() instrinsic.
1056   void kernel_crc32(Register crc, Register buf, Register len,
1057         Register table0, Register table1, Register table2, Register table3,
1058         Register tmp, Register tmp2, Register tmp3);
1059   // CRC32 code for java.util.zip.CRC32C::updateBytes() instrinsic.
1060   void kernel_crc32c(Register crc, Register buf, Register len,
1061         Register table0, Register table1, Register table2, Register table3,
1062         Register tmp, Register tmp2, Register tmp3);
1063 
1064   // Stack push and pop individual 64 bit registers
1065   void push(Register src);
1066   void pop(Register dst);
1067 
1068   // push all registers onto the stack
1069   void pusha();
1070   void popa();
1071 
1072   void repne_scan(Register addr, Register value, Register count,
1073                   Register scratch);
1074   void repne_scanw(Register addr, Register value, Register count,
1075                    Register scratch);
1076 
1077   typedef void (MacroAssembler::* add_sub_imm_insn)(Register Rd, Register Rn, unsigned imm);
1078   typedef void (MacroAssembler::* add_sub_reg_insn)(Register Rd, Register Rn, Register Rm, enum shift_kind kind, unsigned shift);
1079 
1080   // If a constant does not fit in an immediate field, generate some
1081   // number of MOV instructions and then perform the operation
1082   void wrap_add_sub_imm_insn(Register Rd, Register Rn, unsigned imm,
1083                              add_sub_imm_insn insn1,
1084                              add_sub_reg_insn insn2);
1085   // Seperate vsn which sets the flags
1086   void wrap_adds_subs_imm_insn(Register Rd, Register Rn, unsigned imm,
1087                              add_sub_imm_insn insn1,
1088                              add_sub_reg_insn insn2);
1089 
1090 #define WRAP(INSN)                                                      \
1091   void INSN(Register Rd, Register Rn, unsigned imm) {                   \
1092     wrap_add_sub_imm_insn(Rd, Rn, imm, &Assembler::INSN, &Assembler::INSN); \
1093   }                                                                     \
1094                                                                         \
1095   void INSN(Register Rd, Register Rn, Register Rm,                      \
1096              enum shift_kind kind, unsigned shift = 0) {                \
1097     Assembler::INSN(Rd, Rn, Rm, kind, shift);                           \
1098   }                                                                     \
1099                                                                         \
1100   void INSN(Register Rd, Register Rn, Register Rm) {                    \
1101     Assembler::INSN(Rd, Rn, Rm);                                        \
1102   }                                                                     \
1103                                                                         \
1104   void INSN(Register Rd, Register Rn, Register Rm,                      \
1105            ext::operation option, int amount = 0) {                     \
1106     Assembler::INSN(Rd, Rn, Rm, option, amount);                        \
1107   }
1108 
1109   WRAP(add) WRAP(addw) WRAP(sub) WRAP(subw)
1110 
1111 #undef WRAP
1112 #define WRAP(INSN)                                                      \
1113   void INSN(Register Rd, Register Rn, unsigned imm) {                   \
1114     wrap_adds_subs_imm_insn(Rd, Rn, imm, &Assembler::INSN, &Assembler::INSN); \
1115   }                                                                     \
1116                                                                         \
1117   void INSN(Register Rd, Register Rn, Register Rm,                      \
1118              enum shift_kind kind, unsigned shift = 0) {                \
1119     Assembler::INSN(Rd, Rn, Rm, kind, shift);                           \
1120   }                                                                     \
1121                                                                         \
1122   void INSN(Register Rd, Register Rn, Register Rm) {                    \
1123     Assembler::INSN(Rd, Rn, Rm);                                        \
1124   }                                                                     \
1125                                                                         \
1126   void INSN(Register Rd, Register Rn, Register Rm,                      \
1127            ext::operation option, int amount = 0) {                     \
1128     Assembler::INSN(Rd, Rn, Rm, option, amount);                        \
1129   }
1130 
1131   WRAP(adds) WRAP(addsw) WRAP(subs) WRAP(subsw)
1132 
1133   void add(Register Rd, Register Rn, RegisterOrConstant increment);
1134   void addw(Register Rd, Register Rn, RegisterOrConstant increment);
1135   void sub(Register Rd, Register Rn, RegisterOrConstant decrement);
1136   void subw(Register Rd, Register Rn, RegisterOrConstant decrement);
1137 
1138   void adrp(Register reg1, const Address &dest, unsigned long &byte_offset);
1139 
1140   void tableswitch(Register index, jint lowbound, jint highbound,
1141                    Label &jumptable, Label &jumptable_end, int stride = 1) {
1142     adr(rscratch1, jumptable);
1143     subsw(rscratch2, index, lowbound);
1144     subsw(zr, rscratch2, highbound - lowbound);
1145     br(Assembler::HS, jumptable_end);
1146     add(rscratch1, rscratch1, rscratch2,
1147         ext::sxtw, exact_log2(stride * Assembler::instruction_size));
1148     br(rscratch1);
1149   }
1150 
1151   // Form an address from base + offset in Rd.  Rd may or may not
1152   // actually be used: you must use the Address that is returned.  It
1153   // is up to you to ensure that the shift provided matches the size
1154   // of your data.
1155   Address form_address(Register Rd, Register base, long byte_offset, int shift);
1156 
1157   // Return true iff an address is within the 48-bit AArch64 address
1158   // space.
1159   bool is_valid_AArch64_address(address a) {
1160     return ((uint64_t)a >> 48) == 0;
1161   }
1162 
1163   // Load the base of the cardtable byte map into reg.
1164   void load_byte_map_base(Register reg);
1165 
1166   // Prolog generator routines to support switch between x86 code and
1167   // generated ARM code
1168 
1169   // routine to generate an x86 prolog for a stub function which
1170   // bootstraps into the generated ARM code which directly follows the
1171   // stub
1172   //
1173 
1174   public:
1175   // enum used for aarch64--x86 linkage to define return type of x86 function
1176   enum ret_type { ret_type_void, ret_type_integral, ret_type_float, ret_type_double};
1177 
1178 #ifdef BUILTIN_SIM
1179   void c_stub_prolog(int gp_arg_count, int fp_arg_count, int ret_type, address *prolog_ptr = NULL);
1180 #else
1181   void c_stub_prolog(int gp_arg_count, int fp_arg_count, int ret_type) { }
1182 #endif
1183 
1184   // special version of call_VM_leaf_base needed for aarch64 simulator
1185   // where we need to specify both the gp and fp arg counts and the
1186   // return type so that the linkage routine from aarch64 to x86 and
1187   // back knows which aarch64 registers to copy to x86 registers and
1188   // which x86 result register to copy back to an aarch64 register
1189 
1190   void call_VM_leaf_base1(
1191     address  entry_point,             // the entry point
1192     int      number_of_gp_arguments,  // the number of gp reg arguments to pass
1193     int      number_of_fp_arguments,  // the number of fp reg arguments to pass
1194     ret_type type,                    // the return type for the call
1195     Label*   retaddr = NULL
1196   );
1197 
1198   void ldr_constant(Register dest, const Address &const_addr) {
1199     if (NearCpool) {
1200       ldr(dest, const_addr);
1201     } else {
1202       unsigned long offset;
1203       adrp(dest, InternalAddress(const_addr.target()), offset);
1204       ldr(dest, Address(dest, offset));
1205     }
1206   }
1207 
1208   address read_polling_page(Register r, address page, relocInfo::relocType rtype);
1209   address read_polling_page(Register r, relocInfo::relocType rtype);
1210   void get_polling_page(Register dest, address page, relocInfo::relocType rtype);
1211 
1212   // CRC32 code for java.util.zip.CRC32::updateBytes() instrinsic.
1213   void update_byte_crc32(Register crc, Register val, Register table);
1214   void update_word_crc32(Register crc, Register v, Register tmp,
1215         Register table0, Register table1, Register table2, Register table3,
1216         bool upper = false);
1217 
1218   void string_compare(Register str1, Register str2,
1219                       Register cnt1, Register cnt2, Register result,
1220                       Register tmp1, Register tmp2, FloatRegister vtmp1,
1221                       FloatRegister vtmp2, FloatRegister vtmp3, int ae);
1222 
1223   void has_negatives(Register ary1, Register len, Register result);
1224 
1225   void arrays_equals(Register a1, Register a2, Register result, Register cnt1,
1226                      Register tmp1, Register tmp2, Register tmp3, int elem_size);
1227 
1228   void string_equals(Register a1, Register a2, Register result, Register cnt1,
1229                      int elem_size);
1230 
1231   void fill_words(Register base, Register cnt, Register value);
1232   void zero_words(Register base, u_int64_t cnt);
1233   void zero_words(Register ptr, Register cnt);
1234   void zero_dcache_blocks(Register base, Register cnt);
1235 
1236   static const int zero_words_block_size;
1237 
1238   void byte_array_inflate(Register src, Register dst, Register len,
1239                           FloatRegister vtmp1, FloatRegister vtmp2,
1240                           FloatRegister vtmp3, Register tmp4);
1241 
1242   void char_array_compress(Register src, Register dst, Register len,
1243                            FloatRegister tmp1Reg, FloatRegister tmp2Reg,
1244                            FloatRegister tmp3Reg, FloatRegister tmp4Reg,
1245                            Register result);
1246 
1247   void encode_iso_array(Register src, Register dst,
1248                         Register len, Register result,
1249                         FloatRegister Vtmp1, FloatRegister Vtmp2,
1250                         FloatRegister Vtmp3, FloatRegister Vtmp4);
1251   void string_indexof(Register str1, Register str2,
1252                       Register cnt1, Register cnt2,
1253                       Register tmp1, Register tmp2,
1254                       Register tmp3, Register tmp4,
1255                       Register tmp5, Register tmp6,
1256                       int int_cnt1, Register result, int ae);
1257   void string_indexof_char(Register str1, Register cnt1,
1258                            Register ch, Register result,
1259                            Register tmp1, Register tmp2, Register tmp3);
1260   void fast_log(FloatRegister vtmp0, FloatRegister vtmp1, FloatRegister vtmp2,
1261                 FloatRegister vtmp3, FloatRegister vtmp4, FloatRegister vtmp5,
1262                 FloatRegister tmpC1, FloatRegister tmpC2, FloatRegister tmpC3,
1263                 FloatRegister tmpC4, Register tmp1, Register tmp2,
1264                 Register tmp3, Register tmp4, Register tmp5);
1265   void generate_dsin_dcos(bool isCos, address npio2_hw, address two_over_pi,
1266       address pio2, address dsin_coef, address dcos_coef);
1267  private:
1268   // begin trigonometric functions support block
1269   void generate__ieee754_rem_pio2(address npio2_hw, address two_over_pi, address pio2);
1270   void generate__kernel_rem_pio2(address two_over_pi, address pio2);
1271   void generate_kernel_sin(FloatRegister x, bool iyIsOne, address dsin_coef);
1272   void generate_kernel_cos(FloatRegister x, address dcos_coef);
1273   // end trigonometric functions support block
1274   void add2_with_carry(Register final_dest_hi, Register dest_hi, Register dest_lo,
1275                        Register src1, Register src2);
1276   void add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2) {
1277     add2_with_carry(dest_hi, dest_hi, dest_lo, src1, src2);
1278   }
1279   void multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
1280                              Register y, Register y_idx, Register z,
1281                              Register carry, Register product,
1282                              Register idx, Register kdx);
1283   void multiply_128_x_128_loop(Register y, Register z,
1284                                Register carry, Register carry2,
1285                                Register idx, Register jdx,
1286                                Register yz_idx1, Register yz_idx2,
1287                                Register tmp, Register tmp3, Register tmp4,
1288                                Register tmp7, Register product_hi);
1289   void kernel_crc32_using_crc32(Register crc, Register buf,
1290         Register len, Register tmp0, Register tmp1, Register tmp2,
1291         Register tmp3);
1292   void kernel_crc32c_using_crc32c(Register crc, Register buf,
1293         Register len, Register tmp0, Register tmp1, Register tmp2,
1294         Register tmp3);
1295 public:
1296   void multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z,
1297                        Register zlen, Register tmp1, Register tmp2, Register tmp3,
1298                        Register tmp4, Register tmp5, Register tmp6, Register tmp7);
1299   void mul_add(Register out, Register in, Register offs, Register len, Register k);
1300   // ISB may be needed because of a safepoint
1301   void maybe_isb() { isb(); }
1302 
1303 private:
1304   // Return the effective address r + (r1 << ext) + offset.
1305   // Uses rscratch2.
1306   Address offsetted_address(Register r, Register r1, Address::extend ext,
1307                             int offset, int size);
1308 
1309 private:
1310   // Returns an address on the stack which is reachable with a ldr/str of size
1311   // Uses rscratch2 if the address is not directly reachable
1312   Address spill_address(int size, int offset, Register tmp=rscratch2);
1313 
1314   bool merge_alignment_check(Register base, size_t size, long cur_offset, long prev_offset) const;
1315 
1316   // Check whether two loads/stores can be merged into ldp/stp.
1317   bool ldst_can_merge(Register rx, const Address &adr, size_t cur_size_in_bytes, bool is_store) const;
1318 
1319   // Merge current load/store with previous load/store into ldp/stp.
1320   void merge_ldst(Register rx, const Address &adr, size_t cur_size_in_bytes, bool is_store);
1321 
1322   // Try to merge two loads/stores into ldp/stp. If success, returns true else false.
1323   bool try_merge_ldst(Register rt, const Address &adr, size_t cur_size_in_bytes, bool is_store);
1324 
1325 public:
1326   void spill(Register Rx, bool is64, int offset) {
1327     if (is64) {
1328       str(Rx, spill_address(8, offset));
1329     } else {
1330       strw(Rx, spill_address(4, offset));
1331     }
1332   }
1333   void spill(FloatRegister Vx, SIMD_RegVariant T, int offset) {
1334     str(Vx, T, spill_address(1 << (int)T, offset));
1335   }
1336   void unspill(Register Rx, bool is64, int offset) {
1337     if (is64) {
1338       ldr(Rx, spill_address(8, offset));
1339     } else {
1340       ldrw(Rx, spill_address(4, offset));
1341     }
1342   }
1343   void unspill(FloatRegister Vx, SIMD_RegVariant T, int offset) {
1344     ldr(Vx, T, spill_address(1 << (int)T, offset));
1345   }
1346   void spill_copy128(int src_offset, int dst_offset,
1347                      Register tmp1=rscratch1, Register tmp2=rscratch2) {
1348     if (src_offset < 512 && (src_offset & 7) == 0 &&
1349         dst_offset < 512 && (dst_offset & 7) == 0) {
1350       ldp(tmp1, tmp2, Address(sp, src_offset));
1351       stp(tmp1, tmp2, Address(sp, dst_offset));
1352     } else {
1353       unspill(tmp1, true, src_offset);
1354       spill(tmp1, true, dst_offset);
1355       unspill(tmp1, true, src_offset+8);
1356       spill(tmp1, true, dst_offset+8);
1357     }
1358   }
1359 
1360   void cache_wb(Address line);
1361   void cache_wbsync(bool is_pre);
1362 };
1363 
1364 #ifdef ASSERT
1365 inline bool AbstractAssembler::pd_check_instruction_mark() { return false; }
1366 #endif
1367 
1368 /**
1369  * class SkipIfEqual:
1370  *
1371  * Instantiating this class will result in assembly code being output that will
1372  * jump around any code emitted between the creation of the instance and it's
1373  * automatic destruction at the end of a scope block, depending on the value of
1374  * the flag passed to the constructor, which will be checked at run-time.
1375  */
1376 class SkipIfEqual {
1377  private:
1378   MacroAssembler* _masm;
1379   Label _label;
1380 
1381  public:
1382    SkipIfEqual(MacroAssembler*, const bool* flag_addr, bool value);
1383    ~SkipIfEqual();
1384 };
1385 
1386 struct tableswitch {
1387   Register _reg;
1388   int _insn_index; jint _first_key; jint _last_key;
1389   Label _after;
1390   Label _branches;
1391 };
1392 
1393 #endif // CPU_AARCH64_VM_MACROASSEMBLER_AARCH64_HPP