1 /* 2 * Copyright (c) 1997, 2016, Oracle and/or its affiliates. All rights reserved. 3 * Copyright (c) 2015, Red Hat Inc. All rights reserved. 4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 5 * 6 * This code is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License version 2 only, as 8 * published by the Free Software Foundation. 9 * 10 * This code is distributed in the hope that it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 13 * version 2 for more details (a copy is included in the LICENSE file that 14 * accompanied this code). 15 * 16 * You should have received a copy of the GNU General Public License version 17 * 2 along with this work; if not, write to the Free Software Foundation, 18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 19 * 20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 21 * or visit www.oracle.com if you need additional information or have any 22 * questions. 23 * 24 */ 25 26 #include "precompiled.hpp" 27 #include "asm/macroAssembler.hpp" 28 #include "asm/macroAssembler.inline.hpp" 29 #include "memory/resourceArea.hpp" 30 #include "runtime/java.hpp" 31 #include "runtime/stubCodeGenerator.hpp" 32 #include "utilities/macros.hpp" 33 #include "vm_version_aarch64.hpp" 34 35 #include OS_HEADER_INLINE(os) 36 37 #ifndef BUILTIN_SIM 38 #include <sys/auxv.h> 39 #include <asm/hwcap.h> 40 #else 41 #define getauxval(hwcap) 0 42 #endif 43 44 #ifndef HWCAP_AES 45 #define HWCAP_AES (1<<3) 46 #endif 47 48 #ifndef HWCAP_PMULL 49 #define HWCAP_PMULL (1<<4) 50 #endif 51 52 #ifndef HWCAP_SHA1 53 #define HWCAP_SHA1 (1<<5) 54 #endif 55 56 #ifndef HWCAP_SHA2 57 #define HWCAP_SHA2 (1<<6) 58 #endif 59 60 #ifndef HWCAP_CRC32 61 #define HWCAP_CRC32 (1<<7) 62 #endif 63 64 #ifndef HWCAP_ATOMICS 65 #define HWCAP_ATOMICS (1<<8) 66 #endif 67 68 int VM_Version::_cpu; 69 int VM_Version::_model; 70 int VM_Version::_model2; 71 int VM_Version::_variant; 72 int VM_Version::_revision; 73 int VM_Version::_stepping; 74 VM_Version::PsrInfo VM_Version::_psr_info = { 0, }; 75 76 static BufferBlob* stub_blob; 77 static const int stub_size = 550; 78 79 extern "C" { 80 typedef void (*getPsrInfo_stub_t)(void*); 81 } 82 static getPsrInfo_stub_t getPsrInfo_stub = NULL; 83 84 85 class VM_Version_StubGenerator: public StubCodeGenerator { 86 public: 87 88 VM_Version_StubGenerator(CodeBuffer *c) : StubCodeGenerator(c) {} 89 90 address generate_getPsrInfo() { 91 StubCodeMark mark(this, "VM_Version", "getPsrInfo_stub"); 92 # define __ _masm-> 93 address start = __ pc(); 94 95 #ifdef BUILTIN_SIM 96 __ c_stub_prolog(1, 0, MacroAssembler::ret_type_void); 97 #endif 98 99 // void getPsrInfo(VM_Version::PsrInfo* psr_info); 100 101 address entry = __ pc(); 102 103 __ enter(); 104 105 __ get_dczid_el0(rscratch1); 106 __ strw(rscratch1, Address(c_rarg0, in_bytes(VM_Version::dczid_el0_offset()))); 107 108 __ get_ctr_el0(rscratch1); 109 __ strw(rscratch1, Address(c_rarg0, in_bytes(VM_Version::ctr_el0_offset()))); 110 111 __ leave(); 112 __ ret(lr); 113 114 # undef __ 115 116 return start; 117 } 118 }; 119 120 121 void VM_Version::get_processor_features() { 122 _supports_cx8 = true; 123 _supports_atomic_getset4 = true; 124 _supports_atomic_getadd4 = true; 125 _supports_atomic_getset8 = true; 126 _supports_atomic_getadd8 = true; 127 128 getPsrInfo_stub(&_psr_info); 129 130 int dcache_line = VM_Version::dcache_line_size(); 131 132 if (FLAG_IS_DEFAULT(AllocatePrefetchDistance)) 133 FLAG_SET_DEFAULT(AllocatePrefetchDistance, 3*dcache_line); 134 if (FLAG_IS_DEFAULT(AllocatePrefetchStepSize)) 135 FLAG_SET_DEFAULT(AllocatePrefetchStepSize, dcache_line); 136 if (FLAG_IS_DEFAULT(PrefetchScanIntervalInBytes)) 137 FLAG_SET_DEFAULT(PrefetchScanIntervalInBytes, 3*dcache_line); 138 if (FLAG_IS_DEFAULT(PrefetchCopyIntervalInBytes)) 139 FLAG_SET_DEFAULT(PrefetchCopyIntervalInBytes, 3*dcache_line); 140 if (FLAG_IS_DEFAULT(SoftwarePrefetchHintDistance)) 141 FLAG_SET_DEFAULT(SoftwarePrefetchHintDistance, 3*dcache_line); 142 143 if (PrefetchCopyIntervalInBytes != -1 && 144 ((PrefetchCopyIntervalInBytes & 7) || (PrefetchCopyIntervalInBytes >= 32768))) { 145 warning("PrefetchCopyIntervalInBytes must be -1, or a multiple of 8 and < 32768"); 146 PrefetchCopyIntervalInBytes &= ~7; 147 if (PrefetchCopyIntervalInBytes >= 32768) 148 PrefetchCopyIntervalInBytes = 32760; 149 } 150 151 if (AllocatePrefetchDistance !=-1 && (AllocatePrefetchDistance & 7)) { 152 warning("AllocatePrefetchDistance must be multiple of 8"); 153 AllocatePrefetchDistance &= ~7; 154 } 155 156 if (AllocatePrefetchStepSize & 7) { 157 warning("AllocatePrefetchStepSize must be multiple of 8"); 158 AllocatePrefetchStepSize &= ~7; 159 } 160 161 if (SoftwarePrefetchHintDistance != -1 && 162 (SoftwarePrefetchHintDistance & 7)) { 163 warning("SoftwarePrefetchHintDistance must be -1, or a multiple of 8"); 164 SoftwarePrefetchHintDistance &= ~7; 165 } 166 167 unsigned long auxv = getauxval(AT_HWCAP); 168 169 char buf[512]; 170 171 _features = auxv; 172 173 int cpu_lines = 0; 174 if (FILE *f = fopen("/proc/cpuinfo", "r")) { 175 char buf[128], *p; 176 while (fgets(buf, sizeof (buf), f) != NULL) { 177 if (p = strchr(buf, ':')) { 178 long v = strtol(p+1, NULL, 0); 179 if (strncmp(buf, "CPU implementer", sizeof "CPU implementer" - 1) == 0) { 180 _cpu = v; 181 cpu_lines++; 182 } else if (strncmp(buf, "CPU variant", sizeof "CPU variant" - 1) == 0) { 183 _variant = v; 184 } else if (strncmp(buf, "CPU part", sizeof "CPU part" - 1) == 0) { 185 if (_model != v) _model2 = _model; 186 _model = v; 187 } else if (strncmp(buf, "CPU revision", sizeof "CPU revision" - 1) == 0) { 188 _revision = v; 189 } 190 } 191 } 192 fclose(f); 193 } 194 195 // Enable vendor specific features 196 197 // ThunderX 198 if (_cpu == CPU_CAVIUM && (_model == 0xA1)) { 199 if (_variant == 0) _features |= CPU_DMB_ATOMICS; 200 if (FLAG_IS_DEFAULT(AvoidUnalignedAccesses)) { 201 FLAG_SET_DEFAULT(AvoidUnalignedAccesses, true); 202 } 203 if (FLAG_IS_DEFAULT(UseSIMDForMemoryOps)) { 204 FLAG_SET_DEFAULT(UseSIMDForMemoryOps, (_variant > 0)); 205 } 206 if (FLAG_IS_DEFAULT(UseSIMDForArrayEquals)) { 207 FLAG_SET_DEFAULT(UseSIMDForArrayEquals, false); 208 } 209 } 210 211 // ThunderX2 212 if ((_cpu == CPU_CAVIUM && (_model == 0xAF)) || 213 (_cpu == CPU_BROADCOM && (_model == 0x516))) { 214 if (FLAG_IS_DEFAULT(AvoidUnalignedAccesses)) { 215 FLAG_SET_DEFAULT(AvoidUnalignedAccesses, true); 216 } 217 if (FLAG_IS_DEFAULT(UseSIMDForMemoryOps)) { 218 FLAG_SET_DEFAULT(UseSIMDForMemoryOps, true); 219 } 220 if (FLAG_IS_DEFAULT(UseFPUForSpilling)) { 221 FLAG_SET_DEFAULT(UseFPUForSpilling, true); 222 } 223 } 224 225 // Cortex A53 226 if (_cpu == CPU_ARM && (_model == 0xd03 || _model2 == 0xd03)) { 227 _features |= CPU_A53MAC; 228 if (FLAG_IS_DEFAULT(UseSIMDForArrayEquals)) { 229 FLAG_SET_DEFAULT(UseSIMDForArrayEquals, false); 230 } 231 } 232 233 // Cortex A73 234 if (_cpu == CPU_ARM && (_model == 0xd09 || _model2 == 0xd09)) { 235 if (FLAG_IS_DEFAULT(SoftwarePrefetchHintDistance)) { 236 FLAG_SET_DEFAULT(SoftwarePrefetchHintDistance, -1); 237 } 238 // A73 is faster with short-and-easy-for-speculative-execution-loop 239 if (FLAG_IS_DEFAULT(UseSimpleArrayEquals)) { 240 FLAG_SET_DEFAULT(UseSimpleArrayEquals, true); 241 } 242 } 243 244 if (_cpu == CPU_ARM && (_model == 0xd07 || _model2 == 0xd07)) _features |= CPU_STXR_PREFETCH; 245 // If an olde style /proc/cpuinfo (cpu_lines == 1) then if _model is an A57 (0xd07) 246 // we assume the worst and assume we could be on a big little system and have 247 // undisclosed A53 cores which we could be swapped to at any stage 248 if (_cpu == CPU_ARM && cpu_lines == 1 && _model == 0xd07) _features |= CPU_A53MAC; 249 250 sprintf(buf, "0x%02x:0x%x:0x%03x:%d", _cpu, _variant, _model, _revision); 251 if (_model2) sprintf(buf+strlen(buf), "(0x%03x)", _model2); 252 if (auxv & HWCAP_ASIMD) strcat(buf, ", simd"); 253 if (auxv & HWCAP_CRC32) strcat(buf, ", crc"); 254 if (auxv & HWCAP_AES) strcat(buf, ", aes"); 255 if (auxv & HWCAP_SHA1) strcat(buf, ", sha1"); 256 if (auxv & HWCAP_SHA2) strcat(buf, ", sha256"); 257 if (auxv & HWCAP_ATOMICS) strcat(buf, ", lse"); 258 259 _features_string = os::strdup(buf); 260 261 if (FLAG_IS_DEFAULT(UseCRC32)) { 262 UseCRC32 = (auxv & HWCAP_CRC32) != 0; 263 } 264 if (UseCRC32 && (auxv & HWCAP_CRC32) == 0) { 265 warning("UseCRC32 specified, but not supported on this CPU"); 266 } 267 268 if (FLAG_IS_DEFAULT(UseAdler32Intrinsics)) { 269 FLAG_SET_DEFAULT(UseAdler32Intrinsics, true); 270 } 271 272 if (UseVectorizedMismatchIntrinsic) { 273 warning("UseVectorizedMismatchIntrinsic specified, but not available on this CPU."); 274 FLAG_SET_DEFAULT(UseVectorizedMismatchIntrinsic, false); 275 } 276 277 if (auxv & HWCAP_ATOMICS) { 278 if (FLAG_IS_DEFAULT(UseLSE)) 279 FLAG_SET_DEFAULT(UseLSE, true); 280 } else { 281 if (UseLSE) { 282 warning("UseLSE specified, but not supported on this CPU"); 283 } 284 } 285 286 if (auxv & HWCAP_AES) { 287 UseAES = UseAES || FLAG_IS_DEFAULT(UseAES); 288 UseAESIntrinsics = 289 UseAESIntrinsics || (UseAES && FLAG_IS_DEFAULT(UseAESIntrinsics)); 290 if (UseAESIntrinsics && !UseAES) { 291 warning("UseAESIntrinsics enabled, but UseAES not, enabling"); 292 UseAES = true; 293 } 294 } else { 295 if (UseAES) { 296 warning("UseAES specified, but not supported on this CPU"); 297 } 298 if (UseAESIntrinsics) { 299 warning("UseAESIntrinsics specified, but not supported on this CPU"); 300 } 301 } 302 303 if (UseAESCTRIntrinsics) { 304 warning("AES/CTR intrinsics are not available on this CPU"); 305 FLAG_SET_DEFAULT(UseAESCTRIntrinsics, false); 306 } 307 308 if (FLAG_IS_DEFAULT(UseCRC32Intrinsics)) { 309 UseCRC32Intrinsics = true; 310 } 311 312 if (auxv & HWCAP_CRC32) { 313 if (FLAG_IS_DEFAULT(UseCRC32CIntrinsics)) { 314 FLAG_SET_DEFAULT(UseCRC32CIntrinsics, true); 315 } 316 } else if (UseCRC32CIntrinsics) { 317 warning("CRC32C is not available on the CPU"); 318 FLAG_SET_DEFAULT(UseCRC32CIntrinsics, false); 319 } 320 321 if (FLAG_IS_DEFAULT(UseFMA)) { 322 FLAG_SET_DEFAULT(UseFMA, true); 323 } 324 325 if (auxv & (HWCAP_SHA1 | HWCAP_SHA2)) { 326 if (FLAG_IS_DEFAULT(UseSHA)) { 327 FLAG_SET_DEFAULT(UseSHA, true); 328 } 329 } else if (UseSHA) { 330 warning("SHA instructions are not available on this CPU"); 331 FLAG_SET_DEFAULT(UseSHA, false); 332 } 333 334 if (UseSHA && (auxv & HWCAP_SHA1)) { 335 if (FLAG_IS_DEFAULT(UseSHA1Intrinsics)) { 336 FLAG_SET_DEFAULT(UseSHA1Intrinsics, true); 337 } 338 } else if (UseSHA1Intrinsics) { 339 warning("Intrinsics for SHA-1 crypto hash functions not available on this CPU."); 340 FLAG_SET_DEFAULT(UseSHA1Intrinsics, false); 341 } 342 343 if (UseSHA && (auxv & HWCAP_SHA2)) { 344 if (FLAG_IS_DEFAULT(UseSHA256Intrinsics)) { 345 FLAG_SET_DEFAULT(UseSHA256Intrinsics, true); 346 } 347 } else if (UseSHA256Intrinsics) { 348 warning("Intrinsics for SHA-224 and SHA-256 crypto hash functions not available on this CPU."); 349 FLAG_SET_DEFAULT(UseSHA256Intrinsics, false); 350 } 351 352 if (UseSHA512Intrinsics) { 353 warning("Intrinsics for SHA-384 and SHA-512 crypto hash functions not available on this CPU."); 354 FLAG_SET_DEFAULT(UseSHA512Intrinsics, false); 355 } 356 357 if (!(UseSHA1Intrinsics || UseSHA256Intrinsics || UseSHA512Intrinsics)) { 358 FLAG_SET_DEFAULT(UseSHA, false); 359 } 360 361 if (auxv & HWCAP_PMULL) { 362 if (FLAG_IS_DEFAULT(UseGHASHIntrinsics)) { 363 FLAG_SET_DEFAULT(UseGHASHIntrinsics, true); 364 } 365 } else if (UseGHASHIntrinsics) { 366 warning("GHASH intrinsics are not available on this CPU"); 367 FLAG_SET_DEFAULT(UseGHASHIntrinsics, false); 368 } 369 370 if (is_zva_enabled()) { 371 if (FLAG_IS_DEFAULT(UseBlockZeroing)) { 372 FLAG_SET_DEFAULT(UseBlockZeroing, true); 373 } 374 if (FLAG_IS_DEFAULT(BlockZeroingLowLimit)) { 375 FLAG_SET_DEFAULT(BlockZeroingLowLimit, 4 * VM_Version::zva_length()); 376 } 377 } else if (UseBlockZeroing) { 378 warning("DC ZVA is not available on this CPU"); 379 FLAG_SET_DEFAULT(UseBlockZeroing, false); 380 } 381 382 // This machine allows unaligned memory accesses 383 if (FLAG_IS_DEFAULT(UseUnalignedAccesses)) { 384 FLAG_SET_DEFAULT(UseUnalignedAccesses, true); 385 } 386 387 if (FLAG_IS_DEFAULT(UseMultiplyToLenIntrinsic)) { 388 UseMultiplyToLenIntrinsic = true; 389 } 390 391 if (FLAG_IS_DEFAULT(UseSquareToLenIntrinsic)) { 392 UseSquareToLenIntrinsic = true; 393 } 394 395 if (FLAG_IS_DEFAULT(UseMulAddIntrinsic)) { 396 UseMulAddIntrinsic = true; 397 } 398 399 if (FLAG_IS_DEFAULT(UseBarriersForVolatile)) { 400 UseBarriersForVolatile = (_features & CPU_DMB_ATOMICS) != 0; 401 } 402 403 if (FLAG_IS_DEFAULT(UsePopCountInstruction)) { 404 UsePopCountInstruction = true; 405 } 406 407 if (FLAG_IS_DEFAULT(UseMontgomeryMultiplyIntrinsic)) { 408 UseMontgomeryMultiplyIntrinsic = true; 409 } 410 if (FLAG_IS_DEFAULT(UseMontgomerySquareIntrinsic)) { 411 UseMontgomerySquareIntrinsic = true; 412 } 413 414 #ifdef COMPILER2 415 if (FLAG_IS_DEFAULT(OptoScheduling)) { 416 OptoScheduling = true; 417 } 418 #endif 419 } 420 421 void VM_Version::initialize() { 422 ResourceMark rm; 423 424 stub_blob = BufferBlob::create("getPsrInfo_stub", stub_size); 425 if (stub_blob == NULL) { 426 vm_exit_during_initialization("Unable to allocate getPsrInfo_stub"); 427 } 428 429 CodeBuffer c(stub_blob); 430 VM_Version_StubGenerator g(&c); 431 getPsrInfo_stub = CAST_TO_FN_PTR(getPsrInfo_stub_t, 432 g.generate_getPsrInfo()); 433 434 get_processor_features(); 435 436 UNSUPPORTED_OPTION(CriticalJNINatives); 437 }