1 /*
2 * Copyright (c) 1997, 2016, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2015, Red Hat Inc. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #include "precompiled.hpp"
27 #include "asm/macroAssembler.hpp"
28 #include "asm/macroAssembler.inline.hpp"
29 #include "memory/resourceArea.hpp"
30 #include "runtime/java.hpp"
31 #include "runtime/stubCodeGenerator.hpp"
32 #include "utilities/macros.hpp"
33 #include "vm_version_aarch64.hpp"
34
35 #include OS_HEADER_INLINE(os)
36
37 #ifndef BUILTIN_SIM
38 #include <sys/auxv.h>
39 #include <asm/hwcap.h>
40 #else
41 #define getauxval(hwcap) 0
42 #endif
43
44 #ifndef HWCAP_AES
45 #define HWCAP_AES (1<<3)
46 #endif
47
48 #ifndef HWCAP_PMULL
49 #define HWCAP_PMULL (1<<4)
50 #endif
51
52 #ifndef HWCAP_SHA1
53 #define HWCAP_SHA1 (1<<5)
54 #endif
55
56 #ifndef HWCAP_SHA2
57 #define HWCAP_SHA2 (1<<6)
58 #endif
59
60 #ifndef HWCAP_CRC32
61 #define HWCAP_CRC32 (1<<7)
62 #endif
63
64 #ifndef HWCAP_ATOMICS
65 #define HWCAP_ATOMICS (1<<8)
66 #endif
67
68 int VM_Version::_cpu;
69 int VM_Version::_model;
70 int VM_Version::_model2;
71 int VM_Version::_variant;
72 int VM_Version::_revision;
73 int VM_Version::_stepping;
74 VM_Version::PsrInfo VM_Version::_psr_info = { 0, };
75
76 static BufferBlob* stub_blob;
77 static const int stub_size = 550;
78
79 extern "C" {
80 typedef void (*getPsrInfo_stub_t)(void*);
81 }
82 static getPsrInfo_stub_t getPsrInfo_stub = NULL;
83
84
85 class VM_Version_StubGenerator: public StubCodeGenerator {
86 public:
87
88 VM_Version_StubGenerator(CodeBuffer *c) : StubCodeGenerator(c) {}
89
90 address generate_getPsrInfo() {
91 StubCodeMark mark(this, "VM_Version", "getPsrInfo_stub");
92 # define __ _masm->
93 address start = __ pc();
94
95 #ifdef BUILTIN_SIM
96 __ c_stub_prolog(1, 0, MacroAssembler::ret_type_void);
97 #endif
98
99 // void getPsrInfo(VM_Version::PsrInfo* psr_info);
100
101 address entry = __ pc();
102
103 __ enter();
104
105 __ get_dczid_el0(rscratch1);
106 __ strw(rscratch1, Address(c_rarg0, in_bytes(VM_Version::dczid_el0_offset())));
107
108 __ get_ctr_el0(rscratch1);
109 __ strw(rscratch1, Address(c_rarg0, in_bytes(VM_Version::ctr_el0_offset())));
110
111 __ leave();
112 __ ret(lr);
113
114 # undef __
115
116 return start;
117 }
118 };
119
120
121 void VM_Version::get_processor_features() {
122 _supports_cx8 = true;
123 _supports_atomic_getset4 = true;
124 _supports_atomic_getadd4 = true;
125 _supports_atomic_getset8 = true;
126 _supports_atomic_getadd8 = true;
127
128 getPsrInfo_stub(&_psr_info);
129
130 int dcache_line = VM_Version::dcache_line_size();
131
132 // publish data cache line flush size via generic field
133 _data_cache_line_flush_size = dcache_line;
134
135 if (FLAG_IS_DEFAULT(AllocatePrefetchDistance))
136 FLAG_SET_DEFAULT(AllocatePrefetchDistance, 3*dcache_line);
137 if (FLAG_IS_DEFAULT(AllocatePrefetchStepSize))
138 FLAG_SET_DEFAULT(AllocatePrefetchStepSize, dcache_line);
139 if (FLAG_IS_DEFAULT(PrefetchScanIntervalInBytes))
140 FLAG_SET_DEFAULT(PrefetchScanIntervalInBytes, 3*dcache_line);
141 if (FLAG_IS_DEFAULT(PrefetchCopyIntervalInBytes))
142 FLAG_SET_DEFAULT(PrefetchCopyIntervalInBytes, 3*dcache_line);
143 if (FLAG_IS_DEFAULT(SoftwarePrefetchHintDistance))
144 FLAG_SET_DEFAULT(SoftwarePrefetchHintDistance, 3*dcache_line);
145
146 if (PrefetchCopyIntervalInBytes != -1 &&
147 ((PrefetchCopyIntervalInBytes & 7) || (PrefetchCopyIntervalInBytes >= 32768))) {
148 warning("PrefetchCopyIntervalInBytes must be -1, or a multiple of 8 and < 32768");
149 PrefetchCopyIntervalInBytes &= ~7;
150 if (PrefetchCopyIntervalInBytes >= 32768)
151 PrefetchCopyIntervalInBytes = 32760;
152 }
153
154 if (AllocatePrefetchDistance !=-1 && (AllocatePrefetchDistance & 7)) {
155 warning("AllocatePrefetchDistance must be multiple of 8");
156 AllocatePrefetchDistance &= ~7;
157 }
158
159 if (AllocatePrefetchStepSize & 7) {
160 warning("AllocatePrefetchStepSize must be multiple of 8");
161 AllocatePrefetchStepSize &= ~7;
162 }
163
164 if (SoftwarePrefetchHintDistance != -1 &&
165 (SoftwarePrefetchHintDistance & 7)) {
166 warning("SoftwarePrefetchHintDistance must be -1, or a multiple of 8");
167 SoftwarePrefetchHintDistance &= ~7;
168 }
169
170 unsigned long auxv = getauxval(AT_HWCAP);
171
172 char buf[512];
173
174 _features = auxv;
175
176 int cpu_lines = 0;
177 if (FILE *f = fopen("/proc/cpuinfo", "r")) {
178 char buf[128], *p;
179 while (fgets(buf, sizeof (buf), f) != NULL) {
180 if (p = strchr(buf, ':')) {
181 long v = strtol(p+1, NULL, 0);
182 if (strncmp(buf, "CPU implementer", sizeof "CPU implementer" - 1) == 0) {
183 _cpu = v;
184 cpu_lines++;
185 } else if (strncmp(buf, "CPU variant", sizeof "CPU variant" - 1) == 0) {
186 _variant = v;
187 } else if (strncmp(buf, "CPU part", sizeof "CPU part" - 1) == 0) {
188 if (_model != v) _model2 = _model;
189 _model = v;
190 } else if (strncmp(buf, "CPU revision", sizeof "CPU revision" - 1) == 0) {
191 _revision = v;
192 }
193 }
194 }
195 fclose(f);
196 }
197
198 // Enable vendor specific features
199
200 // ThunderX
201 if (_cpu == CPU_CAVIUM && (_model == 0xA1)) {
202 if (_variant == 0) _features |= CPU_DMB_ATOMICS;
203 if (FLAG_IS_DEFAULT(AvoidUnalignedAccesses)) {
204 FLAG_SET_DEFAULT(AvoidUnalignedAccesses, true);
205 }
206 if (FLAG_IS_DEFAULT(UseSIMDForMemoryOps)) {
207 FLAG_SET_DEFAULT(UseSIMDForMemoryOps, (_variant > 0));
208 }
209 if (FLAG_IS_DEFAULT(UseSIMDForArrayEquals)) {
210 FLAG_SET_DEFAULT(UseSIMDForArrayEquals, false);
211 }
212 }
213
214 // ThunderX2
215 if ((_cpu == CPU_CAVIUM && (_model == 0xAF)) ||
216 (_cpu == CPU_BROADCOM && (_model == 0x516))) {
217 if (FLAG_IS_DEFAULT(AvoidUnalignedAccesses)) {
218 FLAG_SET_DEFAULT(AvoidUnalignedAccesses, true);
219 }
220 if (FLAG_IS_DEFAULT(UseSIMDForMemoryOps)) {
221 FLAG_SET_DEFAULT(UseSIMDForMemoryOps, true);
222 }
223 if (FLAG_IS_DEFAULT(UseFPUForSpilling)) {
224 FLAG_SET_DEFAULT(UseFPUForSpilling, true);
225 }
226 }
227
228 // Cortex A53
229 if (_cpu == CPU_ARM && (_model == 0xd03 || _model2 == 0xd03)) {
230 _features |= CPU_A53MAC;
231 if (FLAG_IS_DEFAULT(UseSIMDForArrayEquals)) {
232 FLAG_SET_DEFAULT(UseSIMDForArrayEquals, false);
233 }
234 }
235
236 // Cortex A73
237 if (_cpu == CPU_ARM && (_model == 0xd09 || _model2 == 0xd09)) {
238 if (FLAG_IS_DEFAULT(SoftwarePrefetchHintDistance)) {
239 FLAG_SET_DEFAULT(SoftwarePrefetchHintDistance, -1);
240 }
241 // A73 is faster with short-and-easy-for-speculative-execution-loop
242 if (FLAG_IS_DEFAULT(UseSimpleArrayEquals)) {
243 FLAG_SET_DEFAULT(UseSimpleArrayEquals, true);
244 }
245 }
246
247 if (_cpu == CPU_ARM && (_model == 0xd07 || _model2 == 0xd07)) _features |= CPU_STXR_PREFETCH;
248 // If an olde style /proc/cpuinfo (cpu_lines == 1) then if _model is an A57 (0xd07)
249 // we assume the worst and assume we could be on a big little system and have
250 // undisclosed A53 cores which we could be swapped to at any stage
251 if (_cpu == CPU_ARM && cpu_lines == 1 && _model == 0xd07) _features |= CPU_A53MAC;
252
253 sprintf(buf, "0x%02x:0x%x:0x%03x:%d", _cpu, _variant, _model, _revision);
254 if (_model2) sprintf(buf+strlen(buf), "(0x%03x)", _model2);
255 if (auxv & HWCAP_ASIMD) strcat(buf, ", simd");
256 if (auxv & HWCAP_CRC32) strcat(buf, ", crc");
257 if (auxv & HWCAP_AES) strcat(buf, ", aes");
258 if (auxv & HWCAP_SHA1) strcat(buf, ", sha1");
259 if (auxv & HWCAP_SHA2) strcat(buf, ", sha256");
260 if (auxv & HWCAP_ATOMICS) strcat(buf, ", lse");
261
262 _features_string = os::strdup(buf);
263
264 if (FLAG_IS_DEFAULT(UseCRC32)) {
265 UseCRC32 = (auxv & HWCAP_CRC32) != 0;
266 }
267 if (UseCRC32 && (auxv & HWCAP_CRC32) == 0) {
268 warning("UseCRC32 specified, but not supported on this CPU");
269 }
270
271 if (FLAG_IS_DEFAULT(UseAdler32Intrinsics)) {
272 FLAG_SET_DEFAULT(UseAdler32Intrinsics, true);
273 }
274
275 if (UseVectorizedMismatchIntrinsic) {
276 warning("UseVectorizedMismatchIntrinsic specified, but not available on this CPU.");
277 FLAG_SET_DEFAULT(UseVectorizedMismatchIntrinsic, false);
278 }
279
280 if (auxv & HWCAP_ATOMICS) {
281 if (FLAG_IS_DEFAULT(UseLSE))
282 FLAG_SET_DEFAULT(UseLSE, true);
283 } else {
284 if (UseLSE) {
285 warning("UseLSE specified, but not supported on this CPU");
286 }
287 }
288
289 if (auxv & HWCAP_AES) {
290 UseAES = UseAES || FLAG_IS_DEFAULT(UseAES);
291 UseAESIntrinsics =
292 UseAESIntrinsics || (UseAES && FLAG_IS_DEFAULT(UseAESIntrinsics));
293 if (UseAESIntrinsics && !UseAES) {
294 warning("UseAESIntrinsics enabled, but UseAES not, enabling");
295 UseAES = true;
296 }
297 } else {
298 if (UseAES) {
299 warning("UseAES specified, but not supported on this CPU");
300 }
301 if (UseAESIntrinsics) {
302 warning("UseAESIntrinsics specified, but not supported on this CPU");
303 }
304 }
305
306 if (UseAESCTRIntrinsics) {
307 warning("AES/CTR intrinsics are not available on this CPU");
308 FLAG_SET_DEFAULT(UseAESCTRIntrinsics, false);
309 }
310
311 if (FLAG_IS_DEFAULT(UseCRC32Intrinsics)) {
312 UseCRC32Intrinsics = true;
313 }
314
315 if (auxv & HWCAP_CRC32) {
316 if (FLAG_IS_DEFAULT(UseCRC32CIntrinsics)) {
317 FLAG_SET_DEFAULT(UseCRC32CIntrinsics, true);
318 }
319 } else if (UseCRC32CIntrinsics) {
320 warning("CRC32C is not available on the CPU");
321 FLAG_SET_DEFAULT(UseCRC32CIntrinsics, false);
322 }
323
324 if (FLAG_IS_DEFAULT(UseFMA)) {
325 FLAG_SET_DEFAULT(UseFMA, true);
326 }
327
328 if (auxv & (HWCAP_SHA1 | HWCAP_SHA2)) {
329 if (FLAG_IS_DEFAULT(UseSHA)) {
330 FLAG_SET_DEFAULT(UseSHA, true);
331 }
332 } else if (UseSHA) {
333 warning("SHA instructions are not available on this CPU");
334 FLAG_SET_DEFAULT(UseSHA, false);
335 }
336
337 if (UseSHA && (auxv & HWCAP_SHA1)) {
338 if (FLAG_IS_DEFAULT(UseSHA1Intrinsics)) {
339 FLAG_SET_DEFAULT(UseSHA1Intrinsics, true);
340 }
341 } else if (UseSHA1Intrinsics) {
342 warning("Intrinsics for SHA-1 crypto hash functions not available on this CPU.");
343 FLAG_SET_DEFAULT(UseSHA1Intrinsics, false);
344 }
345
346 if (UseSHA && (auxv & HWCAP_SHA2)) {
347 if (FLAG_IS_DEFAULT(UseSHA256Intrinsics)) {
348 FLAG_SET_DEFAULT(UseSHA256Intrinsics, true);
349 }
350 } else if (UseSHA256Intrinsics) {
351 warning("Intrinsics for SHA-224 and SHA-256 crypto hash functions not available on this CPU.");
352 FLAG_SET_DEFAULT(UseSHA256Intrinsics, false);
353 }
354
355 if (UseSHA512Intrinsics) {
356 warning("Intrinsics for SHA-384 and SHA-512 crypto hash functions not available on this CPU.");
357 FLAG_SET_DEFAULT(UseSHA512Intrinsics, false);
358 }
359
360 if (!(UseSHA1Intrinsics || UseSHA256Intrinsics || UseSHA512Intrinsics)) {
361 FLAG_SET_DEFAULT(UseSHA, false);
362 }
363
364 if (auxv & HWCAP_PMULL) {
365 if (FLAG_IS_DEFAULT(UseGHASHIntrinsics)) {
366 FLAG_SET_DEFAULT(UseGHASHIntrinsics, true);
367 }
368 } else if (UseGHASHIntrinsics) {
369 warning("GHASH intrinsics are not available on this CPU");
370 FLAG_SET_DEFAULT(UseGHASHIntrinsics, false);
371 }
372
373 if (is_zva_enabled()) {
374 if (FLAG_IS_DEFAULT(UseBlockZeroing)) {
375 FLAG_SET_DEFAULT(UseBlockZeroing, true);
376 }
377 if (FLAG_IS_DEFAULT(BlockZeroingLowLimit)) {
378 FLAG_SET_DEFAULT(BlockZeroingLowLimit, 4 * VM_Version::zva_length());
379 }
380 } else if (UseBlockZeroing) {
381 warning("DC ZVA is not available on this CPU");
382 FLAG_SET_DEFAULT(UseBlockZeroing, false);
383 }
384
385 // This machine allows unaligned memory accesses
386 if (FLAG_IS_DEFAULT(UseUnalignedAccesses)) {
387 FLAG_SET_DEFAULT(UseUnalignedAccesses, true);
388 }
389
390 if (FLAG_IS_DEFAULT(UseMultiplyToLenIntrinsic)) {
391 UseMultiplyToLenIntrinsic = true;
392 }
393
394 if (FLAG_IS_DEFAULT(UseSquareToLenIntrinsic)) {
395 UseSquareToLenIntrinsic = true;
396 }
397
398 if (FLAG_IS_DEFAULT(UseMulAddIntrinsic)) {
399 UseMulAddIntrinsic = true;
400 }
401
402 if (FLAG_IS_DEFAULT(UseBarriersForVolatile)) {
403 UseBarriersForVolatile = (_features & CPU_DMB_ATOMICS) != 0;
404 }
405
406 if (FLAG_IS_DEFAULT(UsePopCountInstruction)) {
407 UsePopCountInstruction = true;
408 }
409
410 if (FLAG_IS_DEFAULT(UseMontgomeryMultiplyIntrinsic)) {
411 UseMontgomeryMultiplyIntrinsic = true;
412 }
413 if (FLAG_IS_DEFAULT(UseMontgomerySquareIntrinsic)) {
414 UseMontgomerySquareIntrinsic = true;
415 }
416
417 #ifdef COMPILER2
418 if (FLAG_IS_DEFAULT(OptoScheduling)) {
419 OptoScheduling = true;
420 }
421 #endif
422 }
423
424 void VM_Version::initialize() {
425 ResourceMark rm;
426
427 stub_blob = BufferBlob::create("getPsrInfo_stub", stub_size);
428 if (stub_blob == NULL) {
429 vm_exit_during_initialization("Unable to allocate getPsrInfo_stub");
430 }
431
432 CodeBuffer c(stub_blob);
433 VM_Version_StubGenerator g(&c);
434 getPsrInfo_stub = CAST_TO_FN_PTR(getPsrInfo_stub_t,
435 g.generate_getPsrInfo());
436
437 get_processor_features();
438
439 UNSUPPORTED_OPTION(CriticalJNINatives);
440 }