1 /*
2 * Copyright (c) 1997, 2018, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "asm/assembler.hpp"
27 #include "asm/assembler.inline.hpp"
28 #include "gc/shared/cardTableBarrierSet.hpp"
29 #include "gc/shared/collectedHeap.inline.hpp"
30 #include "interpreter/interpreter.hpp"
31 #include "memory/resourceArea.hpp"
32 #include "prims/methodHandles.hpp"
33 #include "runtime/biasedLocking.hpp"
34 #include "runtime/objectMonitor.hpp"
35 #include "runtime/os.hpp"
36 #include "runtime/sharedRuntime.hpp"
37 #include "runtime/stubRoutines.hpp"
38 #include "utilities/macros.hpp"
39
40 #ifdef PRODUCT
41 #define BLOCK_COMMENT(str) /* nothing */
42 #define STOP(error) stop(error)
43 #else
44 #define BLOCK_COMMENT(str) block_comment(str)
45 #define STOP(error) block_comment(error); stop(error)
46 #endif
47
48 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":")
49 // Implementation of AddressLiteral
50
51 // A 2-D table for managing compressed displacement(disp8) on EVEX enabled platforms.
52 unsigned char tuple_table[Assembler::EVEX_ETUP + 1][Assembler::AVX_512bit + 1] = {
53 // -----------------Table 4.5 -------------------- //
54 16, 32, 64, // EVEX_FV(0)
55 4, 4, 4, // EVEX_FV(1) - with Evex.b
56 16, 32, 64, // EVEX_FV(2) - with Evex.w
57 8, 8, 8, // EVEX_FV(3) - with Evex.w and Evex.b
58 8, 16, 32, // EVEX_HV(0)
59 4, 4, 4, // EVEX_HV(1) - with Evex.b
60 // -----------------Table 4.6 -------------------- //
61 16, 32, 64, // EVEX_FVM(0)
62 1, 1, 1, // EVEX_T1S(0)
63 2, 2, 2, // EVEX_T1S(1)
64 4, 4, 4, // EVEX_T1S(2)
65 8, 8, 8, // EVEX_T1S(3)
66 4, 4, 4, // EVEX_T1F(0)
67 8, 8, 8, // EVEX_T1F(1)
68 8, 8, 8, // EVEX_T2(0)
69 0, 16, 16, // EVEX_T2(1)
70 0, 16, 16, // EVEX_T4(0)
71 0, 0, 32, // EVEX_T4(1)
72 0, 0, 32, // EVEX_T8(0)
73 8, 16, 32, // EVEX_HVM(0)
74 4, 8, 16, // EVEX_QVM(0)
75 2, 4, 8, // EVEX_OVM(0)
76 16, 16, 16, // EVEX_M128(0)
77 8, 32, 64, // EVEX_DUP(0)
78 0, 0, 0 // EVEX_NTUP
79 };
80
81 AddressLiteral::AddressLiteral(address target, relocInfo::relocType rtype) {
82 _is_lval = false;
83 _target = target;
84 switch (rtype) {
85 case relocInfo::oop_type:
86 case relocInfo::metadata_type:
87 // Oops are a special case. Normally they would be their own section
88 // but in cases like icBuffer they are literals in the code stream that
89 // we don't have a section for. We use none so that we get a literal address
90 // which is always patchable.
91 break;
92 case relocInfo::external_word_type:
93 _rspec = external_word_Relocation::spec(target);
94 break;
95 case relocInfo::internal_word_type:
96 _rspec = internal_word_Relocation::spec(target);
97 break;
98 case relocInfo::opt_virtual_call_type:
99 _rspec = opt_virtual_call_Relocation::spec();
100 break;
101 case relocInfo::static_call_type:
102 _rspec = static_call_Relocation::spec();
103 break;
104 case relocInfo::runtime_call_type:
105 _rspec = runtime_call_Relocation::spec();
106 break;
107 case relocInfo::poll_type:
108 case relocInfo::poll_return_type:
109 _rspec = Relocation::spec_simple(rtype);
110 break;
111 case relocInfo::none:
112 break;
113 default:
114 ShouldNotReachHere();
115 break;
116 }
117 }
118
119 // Implementation of Address
120
121 #ifdef _LP64
122
123 Address Address::make_array(ArrayAddress adr) {
124 // Not implementable on 64bit machines
125 // Should have been handled higher up the call chain.
126 ShouldNotReachHere();
127 return Address();
128 }
129
130 // exceedingly dangerous constructor
131 Address::Address(int disp, address loc, relocInfo::relocType rtype) {
132 _base = noreg;
133 _index = noreg;
134 _scale = no_scale;
135 _disp = disp;
136 _xmmindex = xnoreg;
137 _isxmmindex = false;
138 switch (rtype) {
139 case relocInfo::external_word_type:
140 _rspec = external_word_Relocation::spec(loc);
141 break;
142 case relocInfo::internal_word_type:
143 _rspec = internal_word_Relocation::spec(loc);
144 break;
145 case relocInfo::runtime_call_type:
146 // HMM
147 _rspec = runtime_call_Relocation::spec();
148 break;
149 case relocInfo::poll_type:
150 case relocInfo::poll_return_type:
151 _rspec = Relocation::spec_simple(rtype);
152 break;
153 case relocInfo::none:
154 break;
155 default:
156 ShouldNotReachHere();
157 }
158 }
159 #else // LP64
160
161 Address Address::make_array(ArrayAddress adr) {
162 AddressLiteral base = adr.base();
163 Address index = adr.index();
164 assert(index._disp == 0, "must not have disp"); // maybe it can?
165 Address array(index._base, index._index, index._scale, (intptr_t) base.target());
166 array._rspec = base._rspec;
167 return array;
168 }
169
170 // exceedingly dangerous constructor
171 Address::Address(address loc, RelocationHolder spec) {
172 _base = noreg;
173 _index = noreg;
174 _scale = no_scale;
175 _disp = (intptr_t) loc;
176 _rspec = spec;
177 _xmmindex = xnoreg;
178 _isxmmindex = false;
179 }
180
181 #endif // _LP64
182
183
184
185 // Convert the raw encoding form into the form expected by the constructor for
186 // Address. An index of 4 (rsp) corresponds to having no index, so convert
187 // that to noreg for the Address constructor.
188 Address Address::make_raw(int base, int index, int scale, int disp, relocInfo::relocType disp_reloc) {
189 RelocationHolder rspec;
190 if (disp_reloc != relocInfo::none) {
191 rspec = Relocation::spec_simple(disp_reloc);
192 }
193 bool valid_index = index != rsp->encoding();
194 if (valid_index) {
195 Address madr(as_Register(base), as_Register(index), (Address::ScaleFactor)scale, in_ByteSize(disp));
196 madr._rspec = rspec;
197 return madr;
198 } else {
199 Address madr(as_Register(base), noreg, Address::no_scale, in_ByteSize(disp));
200 madr._rspec = rspec;
201 return madr;
202 }
203 }
204
205 // Implementation of Assembler
206
207 int AbstractAssembler::code_fill_byte() {
208 return (u_char)'\xF4'; // hlt
209 }
210
211 // make this go away someday
212 void Assembler::emit_data(jint data, relocInfo::relocType rtype, int format) {
213 if (rtype == relocInfo::none)
214 emit_int32(data);
215 else
216 emit_data(data, Relocation::spec_simple(rtype), format);
217 }
218
219 void Assembler::emit_data(jint data, RelocationHolder const& rspec, int format) {
220 assert(imm_operand == 0, "default format must be immediate in this file");
221 assert(inst_mark() != NULL, "must be inside InstructionMark");
222 if (rspec.type() != relocInfo::none) {
223 #ifdef ASSERT
224 check_relocation(rspec, format);
225 #endif
226 // Do not use AbstractAssembler::relocate, which is not intended for
227 // embedded words. Instead, relocate to the enclosing instruction.
228
229 // hack. call32 is too wide for mask so use disp32
230 if (format == call32_operand)
231 code_section()->relocate(inst_mark(), rspec, disp32_operand);
232 else
233 code_section()->relocate(inst_mark(), rspec, format);
234 }
235 emit_int32(data);
236 }
237
238 static int encode(Register r) {
239 int enc = r->encoding();
240 if (enc >= 8) {
241 enc -= 8;
242 }
243 return enc;
244 }
245
246 void Assembler::emit_arith_b(int op1, int op2, Register dst, int imm8) {
247 assert(dst->has_byte_register(), "must have byte register");
248 assert(isByte(op1) && isByte(op2), "wrong opcode");
249 assert(isByte(imm8), "not a byte");
250 assert((op1 & 0x01) == 0, "should be 8bit operation");
251 emit_int8(op1);
252 emit_int8(op2 | encode(dst));
253 emit_int8(imm8);
254 }
255
256
257 void Assembler::emit_arith(int op1, int op2, Register dst, int32_t imm32) {
258 assert(isByte(op1) && isByte(op2), "wrong opcode");
259 assert((op1 & 0x01) == 1, "should be 32bit operation");
260 assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
261 if (is8bit(imm32)) {
262 emit_int8(op1 | 0x02); // set sign bit
263 emit_int8(op2 | encode(dst));
264 emit_int8(imm32 & 0xFF);
265 } else {
266 emit_int8(op1);
267 emit_int8(op2 | encode(dst));
268 emit_int32(imm32);
269 }
270 }
271
272 // Force generation of a 4 byte immediate value even if it fits into 8bit
273 void Assembler::emit_arith_imm32(int op1, int op2, Register dst, int32_t imm32) {
274 assert(isByte(op1) && isByte(op2), "wrong opcode");
275 assert((op1 & 0x01) == 1, "should be 32bit operation");
276 assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
277 emit_int8(op1);
278 emit_int8(op2 | encode(dst));
279 emit_int32(imm32);
280 }
281
282 // immediate-to-memory forms
283 void Assembler::emit_arith_operand(int op1, Register rm, Address adr, int32_t imm32) {
284 assert((op1 & 0x01) == 1, "should be 32bit operation");
285 assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
286 if (is8bit(imm32)) {
287 emit_int8(op1 | 0x02); // set sign bit
288 emit_operand(rm, adr, 1);
289 emit_int8(imm32 & 0xFF);
290 } else {
291 emit_int8(op1);
292 emit_operand(rm, adr, 4);
293 emit_int32(imm32);
294 }
295 }
296
297
298 void Assembler::emit_arith(int op1, int op2, Register dst, Register src) {
299 assert(isByte(op1) && isByte(op2), "wrong opcode");
300 emit_int8(op1);
301 emit_int8(op2 | encode(dst) << 3 | encode(src));
302 }
303
304
305 bool Assembler::query_compressed_disp_byte(int disp, bool is_evex_inst, int vector_len,
306 int cur_tuple_type, int in_size_in_bits, int cur_encoding) {
307 int mod_idx = 0;
308 // We will test if the displacement fits the compressed format and if so
309 // apply the compression to the displacment iff the result is8bit.
310 if (VM_Version::supports_evex() && is_evex_inst) {
311 switch (cur_tuple_type) {
312 case EVEX_FV:
313 if ((cur_encoding & VEX_W) == VEX_W) {
314 mod_idx = ((cur_encoding & EVEX_Rb) == EVEX_Rb) ? 3 : 2;
315 } else {
316 mod_idx = ((cur_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0;
317 }
318 break;
319
320 case EVEX_HV:
321 mod_idx = ((cur_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0;
322 break;
323
324 case EVEX_FVM:
325 break;
326
327 case EVEX_T1S:
328 switch (in_size_in_bits) {
329 case EVEX_8bit:
330 break;
331
332 case EVEX_16bit:
333 mod_idx = 1;
334 break;
335
336 case EVEX_32bit:
337 mod_idx = 2;
338 break;
339
340 case EVEX_64bit:
341 mod_idx = 3;
342 break;
343 }
344 break;
345
346 case EVEX_T1F:
347 case EVEX_T2:
348 case EVEX_T4:
349 mod_idx = (in_size_in_bits == EVEX_64bit) ? 1 : 0;
350 break;
351
352 case EVEX_T8:
353 break;
354
355 case EVEX_HVM:
356 break;
357
358 case EVEX_QVM:
359 break;
360
361 case EVEX_OVM:
362 break;
363
364 case EVEX_M128:
365 break;
366
367 case EVEX_DUP:
368 break;
369
370 default:
371 assert(0, "no valid evex tuple_table entry");
372 break;
373 }
374
375 if (vector_len >= AVX_128bit && vector_len <= AVX_512bit) {
376 int disp_factor = tuple_table[cur_tuple_type + mod_idx][vector_len];
377 if ((disp % disp_factor) == 0) {
378 int new_disp = disp / disp_factor;
379 if ((-0x80 <= new_disp && new_disp < 0x80)) {
380 disp = new_disp;
381 }
382 } else {
383 return false;
384 }
385 }
386 }
387 return (-0x80 <= disp && disp < 0x80);
388 }
389
390
391 bool Assembler::emit_compressed_disp_byte(int &disp) {
392 int mod_idx = 0;
393 // We will test if the displacement fits the compressed format and if so
394 // apply the compression to the displacment iff the result is8bit.
395 if (VM_Version::supports_evex() && _attributes && _attributes->is_evex_instruction()) {
396 int evex_encoding = _attributes->get_evex_encoding();
397 int tuple_type = _attributes->get_tuple_type();
398 switch (tuple_type) {
399 case EVEX_FV:
400 if ((evex_encoding & VEX_W) == VEX_W) {
401 mod_idx = ((evex_encoding & EVEX_Rb) == EVEX_Rb) ? 3 : 2;
402 } else {
403 mod_idx = ((evex_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0;
404 }
405 break;
406
407 case EVEX_HV:
408 mod_idx = ((evex_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0;
409 break;
410
411 case EVEX_FVM:
412 break;
413
414 case EVEX_T1S:
415 switch (_attributes->get_input_size()) {
416 case EVEX_8bit:
417 break;
418
419 case EVEX_16bit:
420 mod_idx = 1;
421 break;
422
423 case EVEX_32bit:
424 mod_idx = 2;
425 break;
426
427 case EVEX_64bit:
428 mod_idx = 3;
429 break;
430 }
431 break;
432
433 case EVEX_T1F:
434 case EVEX_T2:
435 case EVEX_T4:
436 mod_idx = (_attributes->get_input_size() == EVEX_64bit) ? 1 : 0;
437 break;
438
439 case EVEX_T8:
440 break;
441
442 case EVEX_HVM:
443 break;
444
445 case EVEX_QVM:
446 break;
447
448 case EVEX_OVM:
449 break;
450
451 case EVEX_M128:
452 break;
453
454 case EVEX_DUP:
455 break;
456
457 default:
458 assert(0, "no valid evex tuple_table entry");
459 break;
460 }
461
462 int vector_len = _attributes->get_vector_len();
463 if (vector_len >= AVX_128bit && vector_len <= AVX_512bit) {
464 int disp_factor = tuple_table[tuple_type + mod_idx][vector_len];
465 if ((disp % disp_factor) == 0) {
466 int new_disp = disp / disp_factor;
467 if (is8bit(new_disp)) {
468 disp = new_disp;
469 }
470 } else {
471 return false;
472 }
473 }
474 }
475 return is8bit(disp);
476 }
477
478
479 void Assembler::emit_operand(Register reg, Register base, Register index,
480 Address::ScaleFactor scale, int disp,
481 RelocationHolder const& rspec,
482 int rip_relative_correction) {
483 relocInfo::relocType rtype = (relocInfo::relocType) rspec.type();
484
485 // Encode the registers as needed in the fields they are used in
486
487 int regenc = encode(reg) << 3;
488 int indexenc = index->is_valid() ? encode(index) << 3 : 0;
489 int baseenc = base->is_valid() ? encode(base) : 0;
490
491 if (base->is_valid()) {
492 if (index->is_valid()) {
493 assert(scale != Address::no_scale, "inconsistent address");
494 // [base + index*scale + disp]
495 if (disp == 0 && rtype == relocInfo::none &&
496 base != rbp LP64_ONLY(&& base != r13)) {
497 // [base + index*scale]
498 // [00 reg 100][ss index base]
499 assert(index != rsp, "illegal addressing mode");
500 emit_int8(0x04 | regenc);
501 emit_int8(scale << 6 | indexenc | baseenc);
502 } else if (emit_compressed_disp_byte(disp) && rtype == relocInfo::none) {
503 // [base + index*scale + imm8]
504 // [01 reg 100][ss index base] imm8
505 assert(index != rsp, "illegal addressing mode");
506 emit_int8(0x44 | regenc);
507 emit_int8(scale << 6 | indexenc | baseenc);
508 emit_int8(disp & 0xFF);
509 } else {
510 // [base + index*scale + disp32]
511 // [10 reg 100][ss index base] disp32
512 assert(index != rsp, "illegal addressing mode");
513 emit_int8(0x84 | regenc);
514 emit_int8(scale << 6 | indexenc | baseenc);
515 emit_data(disp, rspec, disp32_operand);
516 }
517 } else if (base == rsp LP64_ONLY(|| base == r12)) {
518 // [rsp + disp]
519 if (disp == 0 && rtype == relocInfo::none) {
520 // [rsp]
521 // [00 reg 100][00 100 100]
522 emit_int8(0x04 | regenc);
523 emit_int8(0x24);
524 } else if (emit_compressed_disp_byte(disp) && rtype == relocInfo::none) {
525 // [rsp + imm8]
526 // [01 reg 100][00 100 100] disp8
527 emit_int8(0x44 | regenc);
528 emit_int8(0x24);
529 emit_int8(disp & 0xFF);
530 } else {
531 // [rsp + imm32]
532 // [10 reg 100][00 100 100] disp32
533 emit_int8(0x84 | regenc);
534 emit_int8(0x24);
535 emit_data(disp, rspec, disp32_operand);
536 }
537 } else {
538 // [base + disp]
539 assert(base != rsp LP64_ONLY(&& base != r12), "illegal addressing mode");
540 if (disp == 0 && rtype == relocInfo::none &&
541 base != rbp LP64_ONLY(&& base != r13)) {
542 // [base]
543 // [00 reg base]
544 emit_int8(0x00 | regenc | baseenc);
545 } else if (emit_compressed_disp_byte(disp) && rtype == relocInfo::none) {
546 // [base + disp8]
547 // [01 reg base] disp8
548 emit_int8(0x40 | regenc | baseenc);
549 emit_int8(disp & 0xFF);
550 } else {
551 // [base + disp32]
552 // [10 reg base] disp32
553 emit_int8(0x80 | regenc | baseenc);
554 emit_data(disp, rspec, disp32_operand);
555 }
556 }
557 } else {
558 if (index->is_valid()) {
559 assert(scale != Address::no_scale, "inconsistent address");
560 // [index*scale + disp]
561 // [00 reg 100][ss index 101] disp32
562 assert(index != rsp, "illegal addressing mode");
563 emit_int8(0x04 | regenc);
564 emit_int8(scale << 6 | indexenc | 0x05);
565 emit_data(disp, rspec, disp32_operand);
566 } else if (rtype != relocInfo::none ) {
567 // [disp] (64bit) RIP-RELATIVE (32bit) abs
568 // [00 000 101] disp32
569
570 emit_int8(0x05 | regenc);
571 // Note that the RIP-rel. correction applies to the generated
572 // disp field, but _not_ to the target address in the rspec.
573
574 // disp was created by converting the target address minus the pc
575 // at the start of the instruction. That needs more correction here.
576 // intptr_t disp = target - next_ip;
577 assert(inst_mark() != NULL, "must be inside InstructionMark");
578 address next_ip = pc() + sizeof(int32_t) + rip_relative_correction;
579 int64_t adjusted = disp;
580 // Do rip-rel adjustment for 64bit
581 LP64_ONLY(adjusted -= (next_ip - inst_mark()));
582 assert(is_simm32(adjusted),
583 "must be 32bit offset (RIP relative address)");
584 emit_data((int32_t) adjusted, rspec, disp32_operand);
585
586 } else {
587 // 32bit never did this, did everything as the rip-rel/disp code above
588 // [disp] ABSOLUTE
589 // [00 reg 100][00 100 101] disp32
590 emit_int8(0x04 | regenc);
591 emit_int8(0x25);
592 emit_data(disp, rspec, disp32_operand);
593 }
594 }
595 }
596
597 void Assembler::emit_operand(XMMRegister reg, Register base, Register index,
598 Address::ScaleFactor scale, int disp,
599 RelocationHolder const& rspec) {
600 if (UseAVX > 2) {
601 int xreg_enc = reg->encoding();
602 if (xreg_enc > 15) {
603 XMMRegister new_reg = as_XMMRegister(xreg_enc & 0xf);
604 emit_operand((Register)new_reg, base, index, scale, disp, rspec);
605 return;
606 }
607 }
608 emit_operand((Register)reg, base, index, scale, disp, rspec);
609 }
610
611 void Assembler::emit_operand(XMMRegister reg, Register base, XMMRegister index,
612 Address::ScaleFactor scale, int disp,
613 RelocationHolder const& rspec) {
614 if (UseAVX > 2) {
615 int xreg_enc = reg->encoding();
616 int xmmindex_enc = index->encoding();
617 XMMRegister new_reg = as_XMMRegister(xreg_enc & 0xf);
618 XMMRegister new_index = as_XMMRegister(xmmindex_enc & 0xf);
619 emit_operand((Register)new_reg, base, (Register)new_index, scale, disp, rspec);
620 } else {
621 emit_operand((Register)reg, base, (Register)index, scale, disp, rspec);
622 }
623 }
624
625
626 // Secret local extension to Assembler::WhichOperand:
627 #define end_pc_operand (_WhichOperand_limit)
628
629 address Assembler::locate_operand(address inst, WhichOperand which) {
630 // Decode the given instruction, and return the address of
631 // an embedded 32-bit operand word.
632
633 // If "which" is disp32_operand, selects the displacement portion
634 // of an effective address specifier.
635 // If "which" is imm64_operand, selects the trailing immediate constant.
636 // If "which" is call32_operand, selects the displacement of a call or jump.
637 // Caller is responsible for ensuring that there is such an operand,
638 // and that it is 32/64 bits wide.
639
640 // If "which" is end_pc_operand, find the end of the instruction.
641
642 address ip = inst;
643 bool is_64bit = false;
644
645 debug_only(bool has_disp32 = false);
646 int tail_size = 0; // other random bytes (#32, #16, etc.) at end of insn
647
648 again_after_prefix:
649 switch (0xFF & *ip++) {
650
651 // These convenience macros generate groups of "case" labels for the switch.
652 #define REP4(x) (x)+0: case (x)+1: case (x)+2: case (x)+3
653 #define REP8(x) (x)+0: case (x)+1: case (x)+2: case (x)+3: \
654 case (x)+4: case (x)+5: case (x)+6: case (x)+7
655 #define REP16(x) REP8((x)+0): \
656 case REP8((x)+8)
657
658 case CS_segment:
659 case SS_segment:
660 case DS_segment:
661 case ES_segment:
662 case FS_segment:
663 case GS_segment:
664 // Seems dubious
665 LP64_ONLY(assert(false, "shouldn't have that prefix"));
666 assert(ip == inst+1, "only one prefix allowed");
667 goto again_after_prefix;
668
669 case 0x67:
670 case REX:
671 case REX_B:
672 case REX_X:
673 case REX_XB:
674 case REX_R:
675 case REX_RB:
676 case REX_RX:
677 case REX_RXB:
678 NOT_LP64(assert(false, "64bit prefixes"));
679 goto again_after_prefix;
680
681 case REX_W:
682 case REX_WB:
683 case REX_WX:
684 case REX_WXB:
685 case REX_WR:
686 case REX_WRB:
687 case REX_WRX:
688 case REX_WRXB:
689 NOT_LP64(assert(false, "64bit prefixes"));
690 is_64bit = true;
691 goto again_after_prefix;
692
693 case 0xFF: // pushq a; decl a; incl a; call a; jmp a
694 case 0x88: // movb a, r
695 case 0x89: // movl a, r
696 case 0x8A: // movb r, a
697 case 0x8B: // movl r, a
698 case 0x8F: // popl a
699 debug_only(has_disp32 = true);
700 break;
701
702 case 0x68: // pushq #32
703 if (which == end_pc_operand) {
704 return ip + 4;
705 }
706 assert(which == imm_operand && !is_64bit, "pushl has no disp32 or 64bit immediate");
707 return ip; // not produced by emit_operand
708
709 case 0x66: // movw ... (size prefix)
710 again_after_size_prefix2:
711 switch (0xFF & *ip++) {
712 case REX:
713 case REX_B:
714 case REX_X:
715 case REX_XB:
716 case REX_R:
717 case REX_RB:
718 case REX_RX:
719 case REX_RXB:
720 case REX_W:
721 case REX_WB:
722 case REX_WX:
723 case REX_WXB:
724 case REX_WR:
725 case REX_WRB:
726 case REX_WRX:
727 case REX_WRXB:
728 NOT_LP64(assert(false, "64bit prefix found"));
729 goto again_after_size_prefix2;
730 case 0x8B: // movw r, a
731 case 0x89: // movw a, r
732 debug_only(has_disp32 = true);
733 break;
734 case 0xC7: // movw a, #16
735 debug_only(has_disp32 = true);
736 tail_size = 2; // the imm16
737 break;
738 case 0x0F: // several SSE/SSE2 variants
739 ip--; // reparse the 0x0F
740 goto again_after_prefix;
741 default:
742 ShouldNotReachHere();
743 }
744 break;
745
746 case REP8(0xB8): // movl/q r, #32/#64(oop?)
747 if (which == end_pc_operand) return ip + (is_64bit ? 8 : 4);
748 // these asserts are somewhat nonsensical
749 #ifndef _LP64
750 assert(which == imm_operand || which == disp32_operand,
751 "which %d is_64_bit %d ip " INTPTR_FORMAT, which, is_64bit, p2i(ip));
752 #else
753 assert((which == call32_operand || which == imm_operand) && is_64bit ||
754 which == narrow_oop_operand && !is_64bit,
755 "which %d is_64_bit %d ip " INTPTR_FORMAT, which, is_64bit, p2i(ip));
756 #endif // _LP64
757 return ip;
758
759 case 0x69: // imul r, a, #32
760 case 0xC7: // movl a, #32(oop?)
761 tail_size = 4;
762 debug_only(has_disp32 = true); // has both kinds of operands!
763 break;
764
765 case 0x0F: // movx..., etc.
766 switch (0xFF & *ip++) {
767 case 0x3A: // pcmpestri
768 tail_size = 1;
769 case 0x38: // ptest, pmovzxbw
770 ip++; // skip opcode
771 debug_only(has_disp32 = true); // has both kinds of operands!
772 break;
773
774 case 0x70: // pshufd r, r/a, #8
775 debug_only(has_disp32 = true); // has both kinds of operands!
776 case 0x73: // psrldq r, #8
777 tail_size = 1;
778 break;
779
780 case 0x12: // movlps
781 case 0x28: // movaps
782 case 0x2E: // ucomiss
783 case 0x2F: // comiss
784 case 0x54: // andps
785 case 0x55: // andnps
786 case 0x56: // orps
787 case 0x57: // xorps
788 case 0x58: // addpd
789 case 0x59: // mulpd
790 case 0x6E: // movd
791 case 0x7E: // movd
792 case 0xAE: // ldmxcsr, stmxcsr, fxrstor, fxsave, clflush
793 case 0xFE: // paddd
794 debug_only(has_disp32 = true);
795 break;
796
797 case 0xAD: // shrd r, a, %cl
798 case 0xAF: // imul r, a
799 case 0xBE: // movsbl r, a (movsxb)
800 case 0xBF: // movswl r, a (movsxw)
801 case 0xB6: // movzbl r, a (movzxb)
802 case 0xB7: // movzwl r, a (movzxw)
803 case REP16(0x40): // cmovl cc, r, a
804 case 0xB0: // cmpxchgb
805 case 0xB1: // cmpxchg
806 case 0xC1: // xaddl
807 case 0xC7: // cmpxchg8
808 case REP16(0x90): // setcc a
809 debug_only(has_disp32 = true);
810 // fall out of the switch to decode the address
811 break;
812
813 case 0xC4: // pinsrw r, a, #8
814 debug_only(has_disp32 = true);
815 case 0xC5: // pextrw r, r, #8
816 tail_size = 1; // the imm8
817 break;
818
819 case 0xAC: // shrd r, a, #8
820 debug_only(has_disp32 = true);
821 tail_size = 1; // the imm8
822 break;
823
824 case REP16(0x80): // jcc rdisp32
825 if (which == end_pc_operand) return ip + 4;
826 assert(which == call32_operand, "jcc has no disp32 or imm");
827 return ip;
828 default:
829 ShouldNotReachHere();
830 }
831 break;
832
833 case 0x81: // addl a, #32; addl r, #32
834 // also: orl, adcl, sbbl, andl, subl, xorl, cmpl
835 // on 32bit in the case of cmpl, the imm might be an oop
836 tail_size = 4;
837 debug_only(has_disp32 = true); // has both kinds of operands!
838 break;
839
840 case 0x83: // addl a, #8; addl r, #8
841 // also: orl, adcl, sbbl, andl, subl, xorl, cmpl
842 debug_only(has_disp32 = true); // has both kinds of operands!
843 tail_size = 1;
844 break;
845
846 case 0x9B:
847 switch (0xFF & *ip++) {
848 case 0xD9: // fnstcw a
849 debug_only(has_disp32 = true);
850 break;
851 default:
852 ShouldNotReachHere();
853 }
854 break;
855
856 case REP4(0x00): // addb a, r; addl a, r; addb r, a; addl r, a
857 case REP4(0x10): // adc...
858 case REP4(0x20): // and...
859 case REP4(0x30): // xor...
860 case REP4(0x08): // or...
861 case REP4(0x18): // sbb...
862 case REP4(0x28): // sub...
863 case 0xF7: // mull a
864 case 0x8D: // lea r, a
865 case 0x87: // xchg r, a
866 case REP4(0x38): // cmp...
867 case 0x85: // test r, a
868 debug_only(has_disp32 = true); // has both kinds of operands!
869 break;
870
871 case 0xC1: // sal a, #8; sar a, #8; shl a, #8; shr a, #8
872 case 0xC6: // movb a, #8
873 case 0x80: // cmpb a, #8
874 case 0x6B: // imul r, a, #8
875 debug_only(has_disp32 = true); // has both kinds of operands!
876 tail_size = 1; // the imm8
877 break;
878
879 case 0xC4: // VEX_3bytes
880 case 0xC5: // VEX_2bytes
881 assert((UseAVX > 0), "shouldn't have VEX prefix");
882 assert(ip == inst+1, "no prefixes allowed");
883 // C4 and C5 are also used as opcodes for PINSRW and PEXTRW instructions
884 // but they have prefix 0x0F and processed when 0x0F processed above.
885 //
886 // In 32-bit mode the VEX first byte C4 and C5 alias onto LDS and LES
887 // instructions (these instructions are not supported in 64-bit mode).
888 // To distinguish them bits [7:6] are set in the VEX second byte since
889 // ModRM byte can not be of the form 11xxxxxx in 32-bit mode. To set
890 // those VEX bits REX and vvvv bits are inverted.
891 //
892 // Fortunately C2 doesn't generate these instructions so we don't need
893 // to check for them in product version.
894
895 // Check second byte
896 NOT_LP64(assert((0xC0 & *ip) == 0xC0, "shouldn't have LDS and LES instructions"));
897
898 int vex_opcode;
899 // First byte
900 if ((0xFF & *inst) == VEX_3bytes) {
901 vex_opcode = VEX_OPCODE_MASK & *ip;
902 ip++; // third byte
903 is_64bit = ((VEX_W & *ip) == VEX_W);
904 } else {
905 vex_opcode = VEX_OPCODE_0F;
906 }
907 ip++; // opcode
908 // To find the end of instruction (which == end_pc_operand).
909 switch (vex_opcode) {
910 case VEX_OPCODE_0F:
911 switch (0xFF & *ip) {
912 case 0x70: // pshufd r, r/a, #8
913 case 0x71: // ps[rl|ra|ll]w r, #8
914 case 0x72: // ps[rl|ra|ll]d r, #8
915 case 0x73: // ps[rl|ra|ll]q r, #8
916 case 0xC2: // cmp[ps|pd|ss|sd] r, r, r/a, #8
917 case 0xC4: // pinsrw r, r, r/a, #8
918 case 0xC5: // pextrw r/a, r, #8
919 case 0xC6: // shufp[s|d] r, r, r/a, #8
920 tail_size = 1; // the imm8
921 break;
922 }
923 break;
924 case VEX_OPCODE_0F_3A:
925 tail_size = 1;
926 break;
927 }
928 ip++; // skip opcode
929 debug_only(has_disp32 = true); // has both kinds of operands!
930 break;
931
932 case 0x62: // EVEX_4bytes
933 assert(VM_Version::supports_evex(), "shouldn't have EVEX prefix");
934 assert(ip == inst+1, "no prefixes allowed");
935 // no EVEX collisions, all instructions that have 0x62 opcodes
936 // have EVEX versions and are subopcodes of 0x66
937 ip++; // skip P0 and exmaine W in P1
938 is_64bit = ((VEX_W & *ip) == VEX_W);
939 ip++; // move to P2
940 ip++; // skip P2, move to opcode
941 // To find the end of instruction (which == end_pc_operand).
942 switch (0xFF & *ip) {
943 case 0x22: // pinsrd r, r/a, #8
944 case 0x61: // pcmpestri r, r/a, #8
945 case 0x70: // pshufd r, r/a, #8
946 case 0x73: // psrldq r, #8
947 tail_size = 1; // the imm8
948 break;
949 default:
950 break;
951 }
952 ip++; // skip opcode
953 debug_only(has_disp32 = true); // has both kinds of operands!
954 break;
955
956 case 0xD1: // sal a, 1; sar a, 1; shl a, 1; shr a, 1
957 case 0xD3: // sal a, %cl; sar a, %cl; shl a, %cl; shr a, %cl
958 case 0xD9: // fld_s a; fst_s a; fstp_s a; fldcw a
959 case 0xDD: // fld_d a; fst_d a; fstp_d a
960 case 0xDB: // fild_s a; fistp_s a; fld_x a; fstp_x a
961 case 0xDF: // fild_d a; fistp_d a
962 case 0xD8: // fadd_s a; fsubr_s a; fmul_s a; fdivr_s a; fcomp_s a
963 case 0xDC: // fadd_d a; fsubr_d a; fmul_d a; fdivr_d a; fcomp_d a
964 case 0xDE: // faddp_d a; fsubrp_d a; fmulp_d a; fdivrp_d a; fcompp_d a
965 debug_only(has_disp32 = true);
966 break;
967
968 case 0xE8: // call rdisp32
969 case 0xE9: // jmp rdisp32
970 if (which == end_pc_operand) return ip + 4;
971 assert(which == call32_operand, "call has no disp32 or imm");
972 return ip;
973
974 case 0xF0: // Lock
975 assert(os::is_MP(), "only on MP");
976 goto again_after_prefix;
977
978 case 0xF3: // For SSE
979 case 0xF2: // For SSE2
980 switch (0xFF & *ip++) {
981 case REX:
982 case REX_B:
983 case REX_X:
984 case REX_XB:
985 case REX_R:
986 case REX_RB:
987 case REX_RX:
988 case REX_RXB:
989 case REX_W:
990 case REX_WB:
991 case REX_WX:
992 case REX_WXB:
993 case REX_WR:
994 case REX_WRB:
995 case REX_WRX:
996 case REX_WRXB:
997 NOT_LP64(assert(false, "found 64bit prefix"));
998 ip++;
999 default:
1000 ip++;
1001 }
1002 debug_only(has_disp32 = true); // has both kinds of operands!
1003 break;
1004
1005 default:
1006 ShouldNotReachHere();
1007
1008 #undef REP8
1009 #undef REP16
1010 }
1011
1012 assert(which != call32_operand, "instruction is not a call, jmp, or jcc");
1013 #ifdef _LP64
1014 assert(which != imm_operand, "instruction is not a movq reg, imm64");
1015 #else
1016 // assert(which != imm_operand || has_imm32, "instruction has no imm32 field");
1017 assert(which != imm_operand || has_disp32, "instruction has no imm32 field");
1018 #endif // LP64
1019 assert(which != disp32_operand || has_disp32, "instruction has no disp32 field");
1020
1021 // parse the output of emit_operand
1022 int op2 = 0xFF & *ip++;
1023 int base = op2 & 0x07;
1024 int op3 = -1;
1025 const int b100 = 4;
1026 const int b101 = 5;
1027 if (base == b100 && (op2 >> 6) != 3) {
1028 op3 = 0xFF & *ip++;
1029 base = op3 & 0x07; // refetch the base
1030 }
1031 // now ip points at the disp (if any)
1032
1033 switch (op2 >> 6) {
1034 case 0:
1035 // [00 reg 100][ss index base]
1036 // [00 reg 100][00 100 esp]
1037 // [00 reg base]
1038 // [00 reg 100][ss index 101][disp32]
1039 // [00 reg 101] [disp32]
1040
1041 if (base == b101) {
1042 if (which == disp32_operand)
1043 return ip; // caller wants the disp32
1044 ip += 4; // skip the disp32
1045 }
1046 break;
1047
1048 case 1:
1049 // [01 reg 100][ss index base][disp8]
1050 // [01 reg 100][00 100 esp][disp8]
1051 // [01 reg base] [disp8]
1052 ip += 1; // skip the disp8
1053 break;
1054
1055 case 2:
1056 // [10 reg 100][ss index base][disp32]
1057 // [10 reg 100][00 100 esp][disp32]
1058 // [10 reg base] [disp32]
1059 if (which == disp32_operand)
1060 return ip; // caller wants the disp32
1061 ip += 4; // skip the disp32
1062 break;
1063
1064 case 3:
1065 // [11 reg base] (not a memory addressing mode)
1066 break;
1067 }
1068
1069 if (which == end_pc_operand) {
1070 return ip + tail_size;
1071 }
1072
1073 #ifdef _LP64
1074 assert(which == narrow_oop_operand && !is_64bit, "instruction is not a movl adr, imm32");
1075 #else
1076 assert(which == imm_operand, "instruction has only an imm field");
1077 #endif // LP64
1078 return ip;
1079 }
1080
1081 address Assembler::locate_next_instruction(address inst) {
1082 // Secretly share code with locate_operand:
1083 return locate_operand(inst, end_pc_operand);
1084 }
1085
1086
1087 #ifdef ASSERT
1088 void Assembler::check_relocation(RelocationHolder const& rspec, int format) {
1089 address inst = inst_mark();
1090 assert(inst != NULL && inst < pc(), "must point to beginning of instruction");
1091 address opnd;
1092
1093 Relocation* r = rspec.reloc();
1094 if (r->type() == relocInfo::none) {
1095 return;
1096 } else if (r->is_call() || format == call32_operand) {
1097 // assert(format == imm32_operand, "cannot specify a nonzero format");
1098 opnd = locate_operand(inst, call32_operand);
1099 } else if (r->is_data()) {
1100 assert(format == imm_operand || format == disp32_operand
1101 LP64_ONLY(|| format == narrow_oop_operand), "format ok");
1102 opnd = locate_operand(inst, (WhichOperand)format);
1103 } else {
1104 assert(format == imm_operand, "cannot specify a format");
1105 return;
1106 }
1107 assert(opnd == pc(), "must put operand where relocs can find it");
1108 }
1109 #endif // ASSERT
1110
1111 void Assembler::emit_operand32(Register reg, Address adr) {
1112 assert(reg->encoding() < 8, "no extended registers");
1113 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers");
1114 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp,
1115 adr._rspec);
1116 }
1117
1118 void Assembler::emit_operand(Register reg, Address adr,
1119 int rip_relative_correction) {
1120 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp,
1121 adr._rspec,
1122 rip_relative_correction);
1123 }
1124
1125 void Assembler::emit_operand(XMMRegister reg, Address adr) {
1126 if (adr.isxmmindex()) {
1127 emit_operand(reg, adr._base, adr._xmmindex, adr._scale, adr._disp, adr._rspec);
1128 } else {
1129 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp,
1130 adr._rspec);
1131 }
1132 }
1133
1134 // MMX operations
1135 void Assembler::emit_operand(MMXRegister reg, Address adr) {
1136 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers");
1137 emit_operand((Register)reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec);
1138 }
1139
1140 // work around gcc (3.2.1-7a) bug
1141 void Assembler::emit_operand(Address adr, MMXRegister reg) {
1142 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers");
1143 emit_operand((Register)reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec);
1144 }
1145
1146
1147 void Assembler::emit_farith(int b1, int b2, int i) {
1148 assert(isByte(b1) && isByte(b2), "wrong opcode");
1149 assert(0 <= i && i < 8, "illegal stack offset");
1150 emit_int8(b1);
1151 emit_int8(b2 + i);
1152 }
1153
1154
1155 // Now the Assembler instructions (identical for 32/64 bits)
1156
1157 void Assembler::adcl(Address dst, int32_t imm32) {
1158 InstructionMark im(this);
1159 prefix(dst);
1160 emit_arith_operand(0x81, rdx, dst, imm32);
1161 }
1162
1163 void Assembler::adcl(Address dst, Register src) {
1164 InstructionMark im(this);
1165 prefix(dst, src);
1166 emit_int8(0x11);
1167 emit_operand(src, dst);
1168 }
1169
1170 void Assembler::adcl(Register dst, int32_t imm32) {
1171 prefix(dst);
1172 emit_arith(0x81, 0xD0, dst, imm32);
1173 }
1174
1175 void Assembler::adcl(Register dst, Address src) {
1176 InstructionMark im(this);
1177 prefix(src, dst);
1178 emit_int8(0x13);
1179 emit_operand(dst, src);
1180 }
1181
1182 void Assembler::adcl(Register dst, Register src) {
1183 (void) prefix_and_encode(dst->encoding(), src->encoding());
1184 emit_arith(0x13, 0xC0, dst, src);
1185 }
1186
1187 void Assembler::addl(Address dst, int32_t imm32) {
1188 InstructionMark im(this);
1189 prefix(dst);
1190 emit_arith_operand(0x81, rax, dst, imm32);
1191 }
1192
1193 void Assembler::addb(Address dst, int imm8) {
1194 InstructionMark im(this);
1195 prefix(dst);
1196 emit_int8((unsigned char)0x80);
1197 emit_operand(rax, dst, 1);
1198 emit_int8(imm8);
1199 }
1200
1201 void Assembler::addw(Address dst, int imm16) {
1202 InstructionMark im(this);
1203 emit_int8(0x66);
1204 prefix(dst);
1205 emit_int8((unsigned char)0x81);
1206 emit_operand(rax, dst, 2);
1207 emit_int16(imm16);
1208 }
1209
1210 void Assembler::addl(Address dst, Register src) {
1211 InstructionMark im(this);
1212 prefix(dst, src);
1213 emit_int8(0x01);
1214 emit_operand(src, dst);
1215 }
1216
1217 void Assembler::addl(Register dst, int32_t imm32) {
1218 prefix(dst);
1219 emit_arith(0x81, 0xC0, dst, imm32);
1220 }
1221
1222 void Assembler::addl(Register dst, Address src) {
1223 InstructionMark im(this);
1224 prefix(src, dst);
1225 emit_int8(0x03);
1226 emit_operand(dst, src);
1227 }
1228
1229 void Assembler::addl(Register dst, Register src) {
1230 (void) prefix_and_encode(dst->encoding(), src->encoding());
1231 emit_arith(0x03, 0xC0, dst, src);
1232 }
1233
1234 void Assembler::addr_nop_4() {
1235 assert(UseAddressNop, "no CPU support");
1236 // 4 bytes: NOP DWORD PTR [EAX+0]
1237 emit_int8(0x0F);
1238 emit_int8(0x1F);
1239 emit_int8(0x40); // emit_rm(cbuf, 0x1, EAX_enc, EAX_enc);
1240 emit_int8(0); // 8-bits offset (1 byte)
1241 }
1242
1243 void Assembler::addr_nop_5() {
1244 assert(UseAddressNop, "no CPU support");
1245 // 5 bytes: NOP DWORD PTR [EAX+EAX*0+0] 8-bits offset
1246 emit_int8(0x0F);
1247 emit_int8(0x1F);
1248 emit_int8(0x44); // emit_rm(cbuf, 0x1, EAX_enc, 0x4);
1249 emit_int8(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc);
1250 emit_int8(0); // 8-bits offset (1 byte)
1251 }
1252
1253 void Assembler::addr_nop_7() {
1254 assert(UseAddressNop, "no CPU support");
1255 // 7 bytes: NOP DWORD PTR [EAX+0] 32-bits offset
1256 emit_int8(0x0F);
1257 emit_int8(0x1F);
1258 emit_int8((unsigned char)0x80);
1259 // emit_rm(cbuf, 0x2, EAX_enc, EAX_enc);
1260 emit_int32(0); // 32-bits offset (4 bytes)
1261 }
1262
1263 void Assembler::addr_nop_8() {
1264 assert(UseAddressNop, "no CPU support");
1265 // 8 bytes: NOP DWORD PTR [EAX+EAX*0+0] 32-bits offset
1266 emit_int8(0x0F);
1267 emit_int8(0x1F);
1268 emit_int8((unsigned char)0x84);
1269 // emit_rm(cbuf, 0x2, EAX_enc, 0x4);
1270 emit_int8(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc);
1271 emit_int32(0); // 32-bits offset (4 bytes)
1272 }
1273
1274 void Assembler::addsd(XMMRegister dst, XMMRegister src) {
1275 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1276 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1277 attributes.set_rex_vex_w_reverted();
1278 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1279 emit_int8(0x58);
1280 emit_int8((unsigned char)(0xC0 | encode));
1281 }
1282
1283 void Assembler::addsd(XMMRegister dst, Address src) {
1284 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1285 InstructionMark im(this);
1286 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1287 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
1288 attributes.set_rex_vex_w_reverted();
1289 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1290 emit_int8(0x58);
1291 emit_operand(dst, src);
1292 }
1293
1294 void Assembler::addss(XMMRegister dst, XMMRegister src) {
1295 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1296 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1297 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1298 emit_int8(0x58);
1299 emit_int8((unsigned char)(0xC0 | encode));
1300 }
1301
1302 void Assembler::addss(XMMRegister dst, Address src) {
1303 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1304 InstructionMark im(this);
1305 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1306 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
1307 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1308 emit_int8(0x58);
1309 emit_operand(dst, src);
1310 }
1311
1312 void Assembler::aesdec(XMMRegister dst, Address src) {
1313 assert(VM_Version::supports_aes(), "");
1314 InstructionMark im(this);
1315 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1316 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1317 emit_int8((unsigned char)0xDE);
1318 emit_operand(dst, src);
1319 }
1320
1321 void Assembler::aesdec(XMMRegister dst, XMMRegister src) {
1322 assert(VM_Version::supports_aes(), "");
1323 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1324 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1325 emit_int8((unsigned char)0xDE);
1326 emit_int8(0xC0 | encode);
1327 }
1328
1329 void Assembler::vaesdec(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
1330 assert(VM_Version::supports_vaes(), "");
1331 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
1332 attributes.set_is_evex_instruction();
1333 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1334 emit_int8((unsigned char)0xDE);
1335 emit_int8((unsigned char)(0xC0 | encode));
1336 }
1337
1338
1339 void Assembler::aesdeclast(XMMRegister dst, Address src) {
1340 assert(VM_Version::supports_aes(), "");
1341 InstructionMark im(this);
1342 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1343 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1344 emit_int8((unsigned char)0xDF);
1345 emit_operand(dst, src);
1346 }
1347
1348 void Assembler::aesdeclast(XMMRegister dst, XMMRegister src) {
1349 assert(VM_Version::supports_aes(), "");
1350 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1351 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1352 emit_int8((unsigned char)0xDF);
1353 emit_int8((unsigned char)(0xC0 | encode));
1354 }
1355
1356 void Assembler::vaesdeclast(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
1357 assert(VM_Version::supports_vaes(), "");
1358 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
1359 attributes.set_is_evex_instruction();
1360 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1361 emit_int8((unsigned char)0xDF);
1362 emit_int8((unsigned char)(0xC0 | encode));
1363 }
1364
1365 void Assembler::aesenc(XMMRegister dst, Address src) {
1366 assert(VM_Version::supports_aes(), "");
1367 InstructionMark im(this);
1368 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1369 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1370 emit_int8((unsigned char)0xDC);
1371 emit_operand(dst, src);
1372 }
1373
1374 void Assembler::aesenc(XMMRegister dst, XMMRegister src) {
1375 assert(VM_Version::supports_aes(), "");
1376 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1377 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1378 emit_int8((unsigned char)0xDC);
1379 emit_int8(0xC0 | encode);
1380 }
1381
1382 void Assembler::aesenclast(XMMRegister dst, Address src) {
1383 assert(VM_Version::supports_aes(), "");
1384 InstructionMark im(this);
1385 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1386 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1387 emit_int8((unsigned char)0xDD);
1388 emit_operand(dst, src);
1389 }
1390
1391 void Assembler::aesenclast(XMMRegister dst, XMMRegister src) {
1392 assert(VM_Version::supports_aes(), "");
1393 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1394 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1395 emit_int8((unsigned char)0xDD);
1396 emit_int8((unsigned char)(0xC0 | encode));
1397 }
1398
1399 void Assembler::andl(Address dst, int32_t imm32) {
1400 InstructionMark im(this);
1401 prefix(dst);
1402 emit_int8((unsigned char)0x81);
1403 emit_operand(rsp, dst, 4);
1404 emit_int32(imm32);
1405 }
1406
1407 void Assembler::andl(Register dst, int32_t imm32) {
1408 prefix(dst);
1409 emit_arith(0x81, 0xE0, dst, imm32);
1410 }
1411
1412 void Assembler::andl(Register dst, Address src) {
1413 InstructionMark im(this);
1414 prefix(src, dst);
1415 emit_int8(0x23);
1416 emit_operand(dst, src);
1417 }
1418
1419 void Assembler::andl(Register dst, Register src) {
1420 (void) prefix_and_encode(dst->encoding(), src->encoding());
1421 emit_arith(0x23, 0xC0, dst, src);
1422 }
1423
1424 void Assembler::andnl(Register dst, Register src1, Register src2) {
1425 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1426 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1427 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1428 emit_int8((unsigned char)0xF2);
1429 emit_int8((unsigned char)(0xC0 | encode));
1430 }
1431
1432 void Assembler::andnl(Register dst, Register src1, Address src2) {
1433 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1434 InstructionMark im(this);
1435 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1436 vex_prefix(src2, src1->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1437 emit_int8((unsigned char)0xF2);
1438 emit_operand(dst, src2);
1439 }
1440
1441 void Assembler::bsfl(Register dst, Register src) {
1442 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1443 emit_int8(0x0F);
1444 emit_int8((unsigned char)0xBC);
1445 emit_int8((unsigned char)(0xC0 | encode));
1446 }
1447
1448 void Assembler::bsrl(Register dst, Register src) {
1449 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1450 emit_int8(0x0F);
1451 emit_int8((unsigned char)0xBD);
1452 emit_int8((unsigned char)(0xC0 | encode));
1453 }
1454
1455 void Assembler::bswapl(Register reg) { // bswap
1456 int encode = prefix_and_encode(reg->encoding());
1457 emit_int8(0x0F);
1458 emit_int8((unsigned char)(0xC8 | encode));
1459 }
1460
1461 void Assembler::blsil(Register dst, Register src) {
1462 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1463 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1464 int encode = vex_prefix_and_encode(rbx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1465 emit_int8((unsigned char)0xF3);
1466 emit_int8((unsigned char)(0xC0 | encode));
1467 }
1468
1469 void Assembler::blsil(Register dst, Address src) {
1470 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1471 InstructionMark im(this);
1472 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1473 vex_prefix(src, dst->encoding(), rbx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1474 emit_int8((unsigned char)0xF3);
1475 emit_operand(rbx, src);
1476 }
1477
1478 void Assembler::blsmskl(Register dst, Register src) {
1479 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1480 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1481 int encode = vex_prefix_and_encode(rdx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1482 emit_int8((unsigned char)0xF3);
1483 emit_int8((unsigned char)(0xC0 | encode));
1484 }
1485
1486 void Assembler::blsmskl(Register dst, Address src) {
1487 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1488 InstructionMark im(this);
1489 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1490 vex_prefix(src, dst->encoding(), rdx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1491 emit_int8((unsigned char)0xF3);
1492 emit_operand(rdx, src);
1493 }
1494
1495 void Assembler::blsrl(Register dst, Register src) {
1496 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1497 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1498 int encode = vex_prefix_and_encode(rcx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1499 emit_int8((unsigned char)0xF3);
1500 emit_int8((unsigned char)(0xC0 | encode));
1501 }
1502
1503 void Assembler::blsrl(Register dst, Address src) {
1504 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1505 InstructionMark im(this);
1506 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1507 vex_prefix(src, dst->encoding(), rcx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1508 emit_int8((unsigned char)0xF3);
1509 emit_operand(rcx, src);
1510 }
1511
1512 void Assembler::call(Label& L, relocInfo::relocType rtype) {
1513 // suspect disp32 is always good
1514 int operand = LP64_ONLY(disp32_operand) NOT_LP64(imm_operand);
1515
1516 if (L.is_bound()) {
1517 const int long_size = 5;
1518 int offs = (int)( target(L) - pc() );
1519 assert(offs <= 0, "assembler error");
1520 InstructionMark im(this);
1521 // 1110 1000 #32-bit disp
1522 emit_int8((unsigned char)0xE8);
1523 emit_data(offs - long_size, rtype, operand);
1524 } else {
1525 InstructionMark im(this);
1526 // 1110 1000 #32-bit disp
1527 L.add_patch_at(code(), locator());
1528
1529 emit_int8((unsigned char)0xE8);
1530 emit_data(int(0), rtype, operand);
1531 }
1532 }
1533
1534 void Assembler::call(Register dst) {
1535 int encode = prefix_and_encode(dst->encoding());
1536 emit_int8((unsigned char)0xFF);
1537 emit_int8((unsigned char)(0xD0 | encode));
1538 }
1539
1540
1541 void Assembler::call(Address adr) {
1542 InstructionMark im(this);
1543 prefix(adr);
1544 emit_int8((unsigned char)0xFF);
1545 emit_operand(rdx, adr);
1546 }
1547
1548 void Assembler::call_literal(address entry, RelocationHolder const& rspec) {
1549 InstructionMark im(this);
1550 emit_int8((unsigned char)0xE8);
1551 intptr_t disp = entry - (pc() + sizeof(int32_t));
1552 // Entry is NULL in case of a scratch emit.
1553 assert(entry == NULL || is_simm32(disp), "disp=" INTPTR_FORMAT " must be 32bit offset (call2)", disp);
1554 // Technically, should use call32_operand, but this format is
1555 // implied by the fact that we're emitting a call instruction.
1556
1557 int operand = LP64_ONLY(disp32_operand) NOT_LP64(call32_operand);
1558 emit_data((int) disp, rspec, operand);
1559 }
1560
1561 void Assembler::cdql() {
1562 emit_int8((unsigned char)0x99);
1563 }
1564
1565 void Assembler::cld() {
1566 emit_int8((unsigned char)0xFC);
1567 }
1568
1569 void Assembler::cmovl(Condition cc, Register dst, Register src) {
1570 NOT_LP64(guarantee(VM_Version::supports_cmov(), "illegal instruction"));
1571 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1572 emit_int8(0x0F);
1573 emit_int8(0x40 | cc);
1574 emit_int8((unsigned char)(0xC0 | encode));
1575 }
1576
1577
1578 void Assembler::cmovl(Condition cc, Register dst, Address src) {
1579 NOT_LP64(guarantee(VM_Version::supports_cmov(), "illegal instruction"));
1580 prefix(src, dst);
1581 emit_int8(0x0F);
1582 emit_int8(0x40 | cc);
1583 emit_operand(dst, src);
1584 }
1585
1586 void Assembler::cmpb(Address dst, int imm8) {
1587 InstructionMark im(this);
1588 prefix(dst);
1589 emit_int8((unsigned char)0x80);
1590 emit_operand(rdi, dst, 1);
1591 emit_int8(imm8);
1592 }
1593
1594 void Assembler::cmpl(Address dst, int32_t imm32) {
1595 InstructionMark im(this);
1596 prefix(dst);
1597 emit_int8((unsigned char)0x81);
1598 emit_operand(rdi, dst, 4);
1599 emit_int32(imm32);
1600 }
1601
1602 void Assembler::cmpl(Register dst, int32_t imm32) {
1603 prefix(dst);
1604 emit_arith(0x81, 0xF8, dst, imm32);
1605 }
1606
1607 void Assembler::cmpl(Register dst, Register src) {
1608 (void) prefix_and_encode(dst->encoding(), src->encoding());
1609 emit_arith(0x3B, 0xC0, dst, src);
1610 }
1611
1612 void Assembler::cmpl(Register dst, Address src) {
1613 InstructionMark im(this);
1614 prefix(src, dst);
1615 emit_int8((unsigned char)0x3B);
1616 emit_operand(dst, src);
1617 }
1618
1619 void Assembler::cmpw(Address dst, int imm16) {
1620 InstructionMark im(this);
1621 assert(!dst.base_needs_rex() && !dst.index_needs_rex(), "no extended registers");
1622 emit_int8(0x66);
1623 emit_int8((unsigned char)0x81);
1624 emit_operand(rdi, dst, 2);
1625 emit_int16(imm16);
1626 }
1627
1628 // The 32-bit cmpxchg compares the value at adr with the contents of rax,
1629 // and stores reg into adr if so; otherwise, the value at adr is loaded into rax,.
1630 // The ZF is set if the compared values were equal, and cleared otherwise.
1631 void Assembler::cmpxchgl(Register reg, Address adr) { // cmpxchg
1632 InstructionMark im(this);
1633 prefix(adr, reg);
1634 emit_int8(0x0F);
1635 emit_int8((unsigned char)0xB1);
1636 emit_operand(reg, adr);
1637 }
1638
1639 // The 8-bit cmpxchg compares the value at adr with the contents of rax,
1640 // and stores reg into adr if so; otherwise, the value at adr is loaded into rax,.
1641 // The ZF is set if the compared values were equal, and cleared otherwise.
1642 void Assembler::cmpxchgb(Register reg, Address adr) { // cmpxchg
1643 InstructionMark im(this);
1644 prefix(adr, reg, true);
1645 emit_int8(0x0F);
1646 emit_int8((unsigned char)0xB0);
1647 emit_operand(reg, adr);
1648 }
1649
1650 void Assembler::comisd(XMMRegister dst, Address src) {
1651 // NOTE: dbx seems to decode this as comiss even though the
1652 // 0x66 is there. Strangly ucomisd comes out correct
1653 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1654 InstructionMark im(this);
1655 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);;
1656 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
1657 attributes.set_rex_vex_w_reverted();
1658 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
1659 emit_int8(0x2F);
1660 emit_operand(dst, src);
1661 }
1662
1663 void Assembler::comisd(XMMRegister dst, XMMRegister src) {
1664 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1665 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1666 attributes.set_rex_vex_w_reverted();
1667 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
1668 emit_int8(0x2F);
1669 emit_int8((unsigned char)(0xC0 | encode));
1670 }
1671
1672 void Assembler::comiss(XMMRegister dst, Address src) {
1673 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1674 InstructionMark im(this);
1675 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1676 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
1677 simd_prefix(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
1678 emit_int8(0x2F);
1679 emit_operand(dst, src);
1680 }
1681
1682 void Assembler::comiss(XMMRegister dst, XMMRegister src) {
1683 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1684 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1685 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
1686 emit_int8(0x2F);
1687 emit_int8((unsigned char)(0xC0 | encode));
1688 }
1689
1690 void Assembler::cpuid() {
1691 emit_int8(0x0F);
1692 emit_int8((unsigned char)0xA2);
1693 }
1694
1695 // Opcode / Instruction Op / En 64 - Bit Mode Compat / Leg Mode Description Implemented
1696 // F2 0F 38 F0 / r CRC32 r32, r / m8 RM Valid Valid Accumulate CRC32 on r / m8. v
1697 // F2 REX 0F 38 F0 / r CRC32 r32, r / m8* RM Valid N.E. Accumulate CRC32 on r / m8. -
1698 // F2 REX.W 0F 38 F0 / r CRC32 r64, r / m8 RM Valid N.E. Accumulate CRC32 on r / m8. -
1699 //
1700 // F2 0F 38 F1 / r CRC32 r32, r / m16 RM Valid Valid Accumulate CRC32 on r / m16. v
1701 //
1702 // F2 0F 38 F1 / r CRC32 r32, r / m32 RM Valid Valid Accumulate CRC32 on r / m32. v
1703 //
1704 // F2 REX.W 0F 38 F1 / r CRC32 r64, r / m64 RM Valid N.E. Accumulate CRC32 on r / m64. v
1705 void Assembler::crc32(Register crc, Register v, int8_t sizeInBytes) {
1706 assert(VM_Version::supports_sse4_2(), "");
1707 int8_t w = 0x01;
1708 Prefix p = Prefix_EMPTY;
1709
1710 emit_int8((int8_t)0xF2);
1711 switch (sizeInBytes) {
1712 case 1:
1713 w = 0;
1714 break;
1715 case 2:
1716 case 4:
1717 break;
1718 LP64_ONLY(case 8:)
1719 // This instruction is not valid in 32 bits
1720 // Note:
1721 // http://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-instruction-set-reference-manual-325383.pdf
1722 //
1723 // Page B - 72 Vol. 2C says
1724 // qwreg2 to qwreg 1111 0010 : 0100 1R0B : 0000 1111 : 0011 1000 : 1111 0000 : 11 qwreg1 qwreg2
1725 // mem64 to qwreg 1111 0010 : 0100 1R0B : 0000 1111 : 0011 1000 : 1111 0000 : mod qwreg r / m
1726 // F0!!!
1727 // while 3 - 208 Vol. 2A
1728 // F2 REX.W 0F 38 F1 / r CRC32 r64, r / m64 RM Valid N.E.Accumulate CRC32 on r / m64.
1729 //
1730 // the 0 on a last bit is reserved for a different flavor of this instruction :
1731 // F2 REX.W 0F 38 F0 / r CRC32 r64, r / m8 RM Valid N.E.Accumulate CRC32 on r / m8.
1732 p = REX_W;
1733 break;
1734 default:
1735 assert(0, "Unsupported value for a sizeInBytes argument");
1736 break;
1737 }
1738 LP64_ONLY(prefix(crc, v, p);)
1739 emit_int8((int8_t)0x0F);
1740 emit_int8(0x38);
1741 emit_int8((int8_t)(0xF0 | w));
1742 emit_int8(0xC0 | ((crc->encoding() & 0x7) << 3) | (v->encoding() & 7));
1743 }
1744
1745 void Assembler::crc32(Register crc, Address adr, int8_t sizeInBytes) {
1746 assert(VM_Version::supports_sse4_2(), "");
1747 InstructionMark im(this);
1748 int8_t w = 0x01;
1749 Prefix p = Prefix_EMPTY;
1750
1751 emit_int8((int8_t)0xF2);
1752 switch (sizeInBytes) {
1753 case 1:
1754 w = 0;
1755 break;
1756 case 2:
1757 case 4:
1758 break;
1759 LP64_ONLY(case 8:)
1760 // This instruction is not valid in 32 bits
1761 p = REX_W;
1762 break;
1763 default:
1764 assert(0, "Unsupported value for a sizeInBytes argument");
1765 break;
1766 }
1767 LP64_ONLY(prefix(crc, adr, p);)
1768 emit_int8((int8_t)0x0F);
1769 emit_int8(0x38);
1770 emit_int8((int8_t)(0xF0 | w));
1771 emit_operand(crc, adr);
1772 }
1773
1774 void Assembler::cvtdq2pd(XMMRegister dst, XMMRegister src) {
1775 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1776 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
1777 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1778 emit_int8((unsigned char)0xE6);
1779 emit_int8((unsigned char)(0xC0 | encode));
1780 }
1781
1782 void Assembler::cvtdq2ps(XMMRegister dst, XMMRegister src) {
1783 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1784 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
1785 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
1786 emit_int8(0x5B);
1787 emit_int8((unsigned char)(0xC0 | encode));
1788 }
1789
1790 void Assembler::cvtsd2ss(XMMRegister dst, XMMRegister src) {
1791 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1792 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1793 attributes.set_rex_vex_w_reverted();
1794 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1795 emit_int8(0x5A);
1796 emit_int8((unsigned char)(0xC0 | encode));
1797 }
1798
1799 void Assembler::cvtsd2ss(XMMRegister dst, Address src) {
1800 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1801 InstructionMark im(this);
1802 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1803 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
1804 attributes.set_rex_vex_w_reverted();
1805 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1806 emit_int8(0x5A);
1807 emit_operand(dst, src);
1808 }
1809
1810 void Assembler::cvtsi2sdl(XMMRegister dst, Register src) {
1811 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1812 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1813 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1814 emit_int8(0x2A);
1815 emit_int8((unsigned char)(0xC0 | encode));
1816 }
1817
1818 void Assembler::cvtsi2sdl(XMMRegister dst, Address src) {
1819 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1820 InstructionMark im(this);
1821 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1822 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
1823 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1824 emit_int8(0x2A);
1825 emit_operand(dst, src);
1826 }
1827
1828 void Assembler::cvtsi2ssl(XMMRegister dst, Register src) {
1829 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1830 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1831 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1832 emit_int8(0x2A);
1833 emit_int8((unsigned char)(0xC0 | encode));
1834 }
1835
1836 void Assembler::cvtsi2ssl(XMMRegister dst, Address src) {
1837 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1838 InstructionMark im(this);
1839 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1840 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
1841 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1842 emit_int8(0x2A);
1843 emit_operand(dst, src);
1844 }
1845
1846 void Assembler::cvtsi2ssq(XMMRegister dst, Register src) {
1847 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1848 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1849 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1850 emit_int8(0x2A);
1851 emit_int8((unsigned char)(0xC0 | encode));
1852 }
1853
1854 void Assembler::cvtss2sd(XMMRegister dst, XMMRegister src) {
1855 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1856 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1857 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1858 emit_int8(0x5A);
1859 emit_int8((unsigned char)(0xC0 | encode));
1860 }
1861
1862 void Assembler::cvtss2sd(XMMRegister dst, Address src) {
1863 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1864 InstructionMark im(this);
1865 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1866 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
1867 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1868 emit_int8(0x5A);
1869 emit_operand(dst, src);
1870 }
1871
1872
1873 void Assembler::cvttsd2sil(Register dst, XMMRegister src) {
1874 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1875 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1876 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1877 emit_int8(0x2C);
1878 emit_int8((unsigned char)(0xC0 | encode));
1879 }
1880
1881 void Assembler::cvttss2sil(Register dst, XMMRegister src) {
1882 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1883 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1884 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1885 emit_int8(0x2C);
1886 emit_int8((unsigned char)(0xC0 | encode));
1887 }
1888
1889 void Assembler::cvttpd2dq(XMMRegister dst, XMMRegister src) {
1890 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1891 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit;
1892 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
1893 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
1894 emit_int8((unsigned char)0xE6);
1895 emit_int8((unsigned char)(0xC0 | encode));
1896 }
1897
1898 void Assembler::decl(Address dst) {
1899 // Don't use it directly. Use MacroAssembler::decrement() instead.
1900 InstructionMark im(this);
1901 prefix(dst);
1902 emit_int8((unsigned char)0xFF);
1903 emit_operand(rcx, dst);
1904 }
1905
1906 void Assembler::divsd(XMMRegister dst, Address src) {
1907 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1908 InstructionMark im(this);
1909 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1910 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
1911 attributes.set_rex_vex_w_reverted();
1912 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1913 emit_int8(0x5E);
1914 emit_operand(dst, src);
1915 }
1916
1917 void Assembler::divsd(XMMRegister dst, XMMRegister src) {
1918 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1919 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1920 attributes.set_rex_vex_w_reverted();
1921 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1922 emit_int8(0x5E);
1923 emit_int8((unsigned char)(0xC0 | encode));
1924 }
1925
1926 void Assembler::divss(XMMRegister dst, Address src) {
1927 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1928 InstructionMark im(this);
1929 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1930 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
1931 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1932 emit_int8(0x5E);
1933 emit_operand(dst, src);
1934 }
1935
1936 void Assembler::divss(XMMRegister dst, XMMRegister src) {
1937 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1938 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1939 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1940 emit_int8(0x5E);
1941 emit_int8((unsigned char)(0xC0 | encode));
1942 }
1943
1944 void Assembler::emms() {
1945 NOT_LP64(assert(VM_Version::supports_mmx(), ""));
1946 emit_int8(0x0F);
1947 emit_int8(0x77);
1948 }
1949
1950 void Assembler::hlt() {
1951 emit_int8((unsigned char)0xF4);
1952 }
1953
1954 void Assembler::idivl(Register src) {
1955 int encode = prefix_and_encode(src->encoding());
1956 emit_int8((unsigned char)0xF7);
1957 emit_int8((unsigned char)(0xF8 | encode));
1958 }
1959
1960 void Assembler::divl(Register src) { // Unsigned
1961 int encode = prefix_and_encode(src->encoding());
1962 emit_int8((unsigned char)0xF7);
1963 emit_int8((unsigned char)(0xF0 | encode));
1964 }
1965
1966 void Assembler::imull(Register src) {
1967 int encode = prefix_and_encode(src->encoding());
1968 emit_int8((unsigned char)0xF7);
1969 emit_int8((unsigned char)(0xE8 | encode));
1970 }
1971
1972 void Assembler::imull(Register dst, Register src) {
1973 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1974 emit_int8(0x0F);
1975 emit_int8((unsigned char)0xAF);
1976 emit_int8((unsigned char)(0xC0 | encode));
1977 }
1978
1979
1980 void Assembler::imull(Register dst, Register src, int value) {
1981 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1982 if (is8bit(value)) {
1983 emit_int8(0x6B);
1984 emit_int8((unsigned char)(0xC0 | encode));
1985 emit_int8(value & 0xFF);
1986 } else {
1987 emit_int8(0x69);
1988 emit_int8((unsigned char)(0xC0 | encode));
1989 emit_int32(value);
1990 }
1991 }
1992
1993 void Assembler::imull(Register dst, Address src) {
1994 InstructionMark im(this);
1995 prefix(src, dst);
1996 emit_int8(0x0F);
1997 emit_int8((unsigned char) 0xAF);
1998 emit_operand(dst, src);
1999 }
2000
2001
2002 void Assembler::incl(Address dst) {
2003 // Don't use it directly. Use MacroAssembler::increment() instead.
2004 InstructionMark im(this);
2005 prefix(dst);
2006 emit_int8((unsigned char)0xFF);
2007 emit_operand(rax, dst);
2008 }
2009
2010 void Assembler::jcc(Condition cc, Label& L, bool maybe_short) {
2011 InstructionMark im(this);
2012 assert((0 <= cc) && (cc < 16), "illegal cc");
2013 if (L.is_bound()) {
2014 address dst = target(L);
2015 assert(dst != NULL, "jcc most probably wrong");
2016
2017 const int short_size = 2;
2018 const int long_size = 6;
2019 intptr_t offs = (intptr_t)dst - (intptr_t)pc();
2020 if (maybe_short && is8bit(offs - short_size)) {
2021 // 0111 tttn #8-bit disp
2022 emit_int8(0x70 | cc);
2023 emit_int8((offs - short_size) & 0xFF);
2024 } else {
2025 // 0000 1111 1000 tttn #32-bit disp
2026 assert(is_simm32(offs - long_size),
2027 "must be 32bit offset (call4)");
2028 emit_int8(0x0F);
2029 emit_int8((unsigned char)(0x80 | cc));
2030 emit_int32(offs - long_size);
2031 }
2032 } else {
2033 // Note: could eliminate cond. jumps to this jump if condition
2034 // is the same however, seems to be rather unlikely case.
2035 // Note: use jccb() if label to be bound is very close to get
2036 // an 8-bit displacement
2037 L.add_patch_at(code(), locator());
2038 emit_int8(0x0F);
2039 emit_int8((unsigned char)(0x80 | cc));
2040 emit_int32(0);
2041 }
2042 }
2043
2044 void Assembler::jccb(Condition cc, Label& L) {
2045 if (L.is_bound()) {
2046 const int short_size = 2;
2047 address entry = target(L);
2048 #ifdef ASSERT
2049 intptr_t dist = (intptr_t)entry - ((intptr_t)pc() + short_size);
2050 intptr_t delta = short_branch_delta();
2051 if (delta != 0) {
2052 dist += (dist < 0 ? (-delta) :delta);
2053 }
2054 assert(is8bit(dist), "Dispacement too large for a short jmp");
2055 #endif
2056 intptr_t offs = (intptr_t)entry - (intptr_t)pc();
2057 // 0111 tttn #8-bit disp
2058 emit_int8(0x70 | cc);
2059 emit_int8((offs - short_size) & 0xFF);
2060 } else {
2061 InstructionMark im(this);
2062 L.add_patch_at(code(), locator());
2063 emit_int8(0x70 | cc);
2064 emit_int8(0);
2065 }
2066 }
2067
2068 void Assembler::jmp(Address adr) {
2069 InstructionMark im(this);
2070 prefix(adr);
2071 emit_int8((unsigned char)0xFF);
2072 emit_operand(rsp, adr);
2073 }
2074
2075 void Assembler::jmp(Label& L, bool maybe_short) {
2076 if (L.is_bound()) {
2077 address entry = target(L);
2078 assert(entry != NULL, "jmp most probably wrong");
2079 InstructionMark im(this);
2080 const int short_size = 2;
2081 const int long_size = 5;
2082 intptr_t offs = entry - pc();
2083 if (maybe_short && is8bit(offs - short_size)) {
2084 emit_int8((unsigned char)0xEB);
2085 emit_int8((offs - short_size) & 0xFF);
2086 } else {
2087 emit_int8((unsigned char)0xE9);
2088 emit_int32(offs - long_size);
2089 }
2090 } else {
2091 // By default, forward jumps are always 32-bit displacements, since
2092 // we can't yet know where the label will be bound. If you're sure that
2093 // the forward jump will not run beyond 256 bytes, use jmpb to
2094 // force an 8-bit displacement.
2095 InstructionMark im(this);
2096 L.add_patch_at(code(), locator());
2097 emit_int8((unsigned char)0xE9);
2098 emit_int32(0);
2099 }
2100 }
2101
2102 void Assembler::jmp(Register entry) {
2103 int encode = prefix_and_encode(entry->encoding());
2104 emit_int8((unsigned char)0xFF);
2105 emit_int8((unsigned char)(0xE0 | encode));
2106 }
2107
2108 void Assembler::jmp_literal(address dest, RelocationHolder const& rspec) {
2109 InstructionMark im(this);
2110 emit_int8((unsigned char)0xE9);
2111 assert(dest != NULL, "must have a target");
2112 intptr_t disp = dest - (pc() + sizeof(int32_t));
2113 assert(is_simm32(disp), "must be 32bit offset (jmp)");
2114 emit_data(disp, rspec.reloc(), call32_operand);
2115 }
2116
2117 void Assembler::jmpb(Label& L) {
2118 if (L.is_bound()) {
2119 const int short_size = 2;
2120 address entry = target(L);
2121 assert(entry != NULL, "jmp most probably wrong");
2122 #ifdef ASSERT
2123 intptr_t dist = (intptr_t)entry - ((intptr_t)pc() + short_size);
2124 intptr_t delta = short_branch_delta();
2125 if (delta != 0) {
2126 dist += (dist < 0 ? (-delta) :delta);
2127 }
2128 assert(is8bit(dist), "Dispacement too large for a short jmp");
2129 #endif
2130 intptr_t offs = entry - pc();
2131 emit_int8((unsigned char)0xEB);
2132 emit_int8((offs - short_size) & 0xFF);
2133 } else {
2134 InstructionMark im(this);
2135 L.add_patch_at(code(), locator());
2136 emit_int8((unsigned char)0xEB);
2137 emit_int8(0);
2138 }
2139 }
2140
2141 void Assembler::ldmxcsr( Address src) {
2142 if (UseAVX > 0 ) {
2143 InstructionMark im(this);
2144 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2145 vex_prefix(src, 0, 0, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2146 emit_int8((unsigned char)0xAE);
2147 emit_operand(as_Register(2), src);
2148 } else {
2149 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2150 InstructionMark im(this);
2151 prefix(src);
2152 emit_int8(0x0F);
2153 emit_int8((unsigned char)0xAE);
2154 emit_operand(as_Register(2), src);
2155 }
2156 }
2157
2158 void Assembler::leal(Register dst, Address src) {
2159 InstructionMark im(this);
2160 #ifdef _LP64
2161 emit_int8(0x67); // addr32
2162 prefix(src, dst);
2163 #endif // LP64
2164 emit_int8((unsigned char)0x8D);
2165 emit_operand(dst, src);
2166 }
2167
2168 void Assembler::lfence() {
2169 emit_int8(0x0F);
2170 emit_int8((unsigned char)0xAE);
2171 emit_int8((unsigned char)0xE8);
2172 }
2173
2174 void Assembler::lock() {
2175 emit_int8((unsigned char)0xF0);
2176 }
2177
2178 void Assembler::lzcntl(Register dst, Register src) {
2179 assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR");
2180 emit_int8((unsigned char)0xF3);
2181 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2182 emit_int8(0x0F);
2183 emit_int8((unsigned char)0xBD);
2184 emit_int8((unsigned char)(0xC0 | encode));
2185 }
2186
2187 // Emit mfence instruction
2188 void Assembler::mfence() {
2189 NOT_LP64(assert(VM_Version::supports_sse2(), "unsupported");)
2190 emit_int8(0x0F);
2191 emit_int8((unsigned char)0xAE);
2192 emit_int8((unsigned char)0xF0);
2193 }
2194
2195 void Assembler::mov(Register dst, Register src) {
2196 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
2197 }
2198
2199 void Assembler::movapd(XMMRegister dst, XMMRegister src) {
2200 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2201 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit;
2202 InstructionAttr attributes(vector_len, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
2203 attributes.set_rex_vex_w_reverted();
2204 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2205 emit_int8(0x28);
2206 emit_int8((unsigned char)(0xC0 | encode));
2207 }
2208
2209 void Assembler::movaps(XMMRegister dst, XMMRegister src) {
2210 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2211 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit;
2212 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
2213 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2214 emit_int8(0x28);
2215 emit_int8((unsigned char)(0xC0 | encode));
2216 }
2217
2218 void Assembler::movlhps(XMMRegister dst, XMMRegister src) {
2219 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2220 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2221 int encode = simd_prefix_and_encode(dst, src, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2222 emit_int8(0x16);
2223 emit_int8((unsigned char)(0xC0 | encode));
2224 }
2225
2226 void Assembler::movb(Register dst, Address src) {
2227 NOT_LP64(assert(dst->has_byte_register(), "must have byte register"));
2228 InstructionMark im(this);
2229 prefix(src, dst, true);
2230 emit_int8((unsigned char)0x8A);
2231 emit_operand(dst, src);
2232 }
2233
2234 void Assembler::movddup(XMMRegister dst, XMMRegister src) {
2235 NOT_LP64(assert(VM_Version::supports_sse3(), ""));
2236 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit;
2237 InstructionAttr attributes(vector_len, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2238 attributes.set_rex_vex_w_reverted();
2239 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2240 emit_int8(0x12);
2241 emit_int8(0xC0 | encode);
2242 }
2243
2244 void Assembler::kmovbl(KRegister dst, Register src) {
2245 assert(VM_Version::supports_avx512dq(), "");
2246 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2247 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2248 emit_int8((unsigned char)0x92);
2249 emit_int8((unsigned char)(0xC0 | encode));
2250 }
2251
2252 void Assembler::kmovbl(Register dst, KRegister src) {
2253 assert(VM_Version::supports_avx512dq(), "");
2254 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2255 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2256 emit_int8((unsigned char)0x93);
2257 emit_int8((unsigned char)(0xC0 | encode));
2258 }
2259
2260 void Assembler::kmovwl(KRegister dst, Register src) {
2261 assert(VM_Version::supports_evex(), "");
2262 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2263 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2264 emit_int8((unsigned char)0x92);
2265 emit_int8((unsigned char)(0xC0 | encode));
2266 }
2267
2268 void Assembler::kmovwl(Register dst, KRegister src) {
2269 assert(VM_Version::supports_evex(), "");
2270 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2271 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2272 emit_int8((unsigned char)0x93);
2273 emit_int8((unsigned char)(0xC0 | encode));
2274 }
2275
2276 void Assembler::kmovwl(KRegister dst, Address src) {
2277 assert(VM_Version::supports_evex(), "");
2278 InstructionMark im(this);
2279 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2280 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2281 emit_int8((unsigned char)0x90);
2282 emit_operand((Register)dst, src);
2283 }
2284
2285 void Assembler::kmovdl(KRegister dst, Register src) {
2286 assert(VM_Version::supports_avx512bw(), "");
2287 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2288 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2289 emit_int8((unsigned char)0x92);
2290 emit_int8((unsigned char)(0xC0 | encode));
2291 }
2292
2293 void Assembler::kmovdl(Register dst, KRegister src) {
2294 assert(VM_Version::supports_avx512bw(), "");
2295 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2296 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2297 emit_int8((unsigned char)0x93);
2298 emit_int8((unsigned char)(0xC0 | encode));
2299 }
2300
2301 void Assembler::kmovql(KRegister dst, KRegister src) {
2302 assert(VM_Version::supports_avx512bw(), "");
2303 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2304 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2305 emit_int8((unsigned char)0x90);
2306 emit_int8((unsigned char)(0xC0 | encode));
2307 }
2308
2309 void Assembler::kmovql(KRegister dst, Address src) {
2310 assert(VM_Version::supports_avx512bw(), "");
2311 InstructionMark im(this);
2312 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2313 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2314 emit_int8((unsigned char)0x90);
2315 emit_operand((Register)dst, src);
2316 }
2317
2318 void Assembler::kmovql(Address dst, KRegister src) {
2319 assert(VM_Version::supports_avx512bw(), "");
2320 InstructionMark im(this);
2321 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2322 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2323 emit_int8((unsigned char)0x90);
2324 emit_operand((Register)src, dst);
2325 }
2326
2327 void Assembler::kmovql(KRegister dst, Register src) {
2328 assert(VM_Version::supports_avx512bw(), "");
2329 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2330 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2331 emit_int8((unsigned char)0x92);
2332 emit_int8((unsigned char)(0xC0 | encode));
2333 }
2334
2335 void Assembler::kmovql(Register dst, KRegister src) {
2336 assert(VM_Version::supports_avx512bw(), "");
2337 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2338 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2339 emit_int8((unsigned char)0x93);
2340 emit_int8((unsigned char)(0xC0 | encode));
2341 }
2342
2343 void Assembler::knotwl(KRegister dst, KRegister src) {
2344 assert(VM_Version::supports_evex(), "");
2345 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2346 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2347 emit_int8((unsigned char)0x44);
2348 emit_int8((unsigned char)(0xC0 | encode));
2349 }
2350
2351 // This instruction produces ZF or CF flags
2352 void Assembler::kortestbl(KRegister src1, KRegister src2) {
2353 assert(VM_Version::supports_avx512dq(), "");
2354 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2355 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2356 emit_int8((unsigned char)0x98);
2357 emit_int8((unsigned char)(0xC0 | encode));
2358 }
2359
2360 // This instruction produces ZF or CF flags
2361 void Assembler::kortestwl(KRegister src1, KRegister src2) {
2362 assert(VM_Version::supports_evex(), "");
2363 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2364 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2365 emit_int8((unsigned char)0x98);
2366 emit_int8((unsigned char)(0xC0 | encode));
2367 }
2368
2369 // This instruction produces ZF or CF flags
2370 void Assembler::kortestdl(KRegister src1, KRegister src2) {
2371 assert(VM_Version::supports_avx512bw(), "");
2372 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2373 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2374 emit_int8((unsigned char)0x98);
2375 emit_int8((unsigned char)(0xC0 | encode));
2376 }
2377
2378 // This instruction produces ZF or CF flags
2379 void Assembler::kortestql(KRegister src1, KRegister src2) {
2380 assert(VM_Version::supports_avx512bw(), "");
2381 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2382 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2383 emit_int8((unsigned char)0x98);
2384 emit_int8((unsigned char)(0xC0 | encode));
2385 }
2386
2387 // This instruction produces ZF or CF flags
2388 void Assembler::ktestql(KRegister src1, KRegister src2) {
2389 assert(VM_Version::supports_avx512bw(), "");
2390 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2391 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2392 emit_int8((unsigned char)0x99);
2393 emit_int8((unsigned char)(0xC0 | encode));
2394 }
2395
2396 void Assembler::ktestq(KRegister src1, KRegister src2) {
2397 assert(VM_Version::supports_avx512bw(), "");
2398 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2399 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2400 emit_int8((unsigned char)0x99);
2401 emit_int8((unsigned char)(0xC0 | encode));
2402 }
2403
2404 void Assembler::ktestd(KRegister src1, KRegister src2) {
2405 assert(VM_Version::supports_avx512bw(), "");
2406 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2407 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2408 emit_int8((unsigned char)0x99);
2409 emit_int8((unsigned char)(0xC0 | encode));
2410 }
2411
2412 void Assembler::movb(Address dst, int imm8) {
2413 InstructionMark im(this);
2414 prefix(dst);
2415 emit_int8((unsigned char)0xC6);
2416 emit_operand(rax, dst, 1);
2417 emit_int8(imm8);
2418 }
2419
2420
2421 void Assembler::movb(Address dst, Register src) {
2422 assert(src->has_byte_register(), "must have byte register");
2423 InstructionMark im(this);
2424 prefix(dst, src, true);
2425 emit_int8((unsigned char)0x88);
2426 emit_operand(src, dst);
2427 }
2428
2429 void Assembler::movdl(XMMRegister dst, Register src) {
2430 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2431 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2432 int encode = simd_prefix_and_encode(dst, xnoreg, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2433 emit_int8(0x6E);
2434 emit_int8((unsigned char)(0xC0 | encode));
2435 }
2436
2437 void Assembler::movdl(Register dst, XMMRegister src) {
2438 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2439 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2440 // swap src/dst to get correct prefix
2441 int encode = simd_prefix_and_encode(src, xnoreg, as_XMMRegister(dst->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2442 emit_int8(0x7E);
2443 emit_int8((unsigned char)(0xC0 | encode));
2444 }
2445
2446 void Assembler::movdl(XMMRegister dst, Address src) {
2447 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2448 InstructionMark im(this);
2449 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2450 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
2451 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2452 emit_int8(0x6E);
2453 emit_operand(dst, src);
2454 }
2455
2456 void Assembler::movdl(Address dst, XMMRegister src) {
2457 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2458 InstructionMark im(this);
2459 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2460 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
2461 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2462 emit_int8(0x7E);
2463 emit_operand(src, dst);
2464 }
2465
2466 void Assembler::movdqa(XMMRegister dst, XMMRegister src) {
2467 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2468 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit;
2469 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2470 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2471 emit_int8(0x6F);
2472 emit_int8((unsigned char)(0xC0 | encode));
2473 }
2474
2475 void Assembler::movdqa(XMMRegister dst, Address src) {
2476 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2477 InstructionMark im(this);
2478 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2479 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2480 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2481 emit_int8(0x6F);
2482 emit_operand(dst, src);
2483 }
2484
2485 void Assembler::movdqu(XMMRegister dst, Address src) {
2486 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2487 InstructionMark im(this);
2488 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2489 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2490 simd_prefix(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2491 emit_int8(0x6F);
2492 emit_operand(dst, src);
2493 }
2494
2495 void Assembler::movdqu(XMMRegister dst, XMMRegister src) {
2496 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2497 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2498 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2499 emit_int8(0x6F);
2500 emit_int8((unsigned char)(0xC0 | encode));
2501 }
2502
2503 void Assembler::movdqu(Address dst, XMMRegister src) {
2504 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2505 InstructionMark im(this);
2506 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2507 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2508 attributes.reset_is_clear_context();
2509 simd_prefix(src, xnoreg, dst, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2510 emit_int8(0x7F);
2511 emit_operand(src, dst);
2512 }
2513
2514 // Move Unaligned 256bit Vector
2515 void Assembler::vmovdqu(XMMRegister dst, XMMRegister src) {
2516 assert(UseAVX > 0, "");
2517 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2518 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2519 emit_int8(0x6F);
2520 emit_int8((unsigned char)(0xC0 | encode));
2521 }
2522
2523 void Assembler::vmovdqu(XMMRegister dst, Address src) {
2524 assert(UseAVX > 0, "");
2525 InstructionMark im(this);
2526 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2527 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2528 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2529 emit_int8(0x6F);
2530 emit_operand(dst, src);
2531 }
2532
2533 void Assembler::vmovdqu(Address dst, XMMRegister src) {
2534 assert(UseAVX > 0, "");
2535 InstructionMark im(this);
2536 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2537 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2538 attributes.reset_is_clear_context();
2539 // swap src<->dst for encoding
2540 assert(src != xnoreg, "sanity");
2541 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2542 emit_int8(0x7F);
2543 emit_operand(src, dst);
2544 }
2545
2546 // Move Unaligned EVEX enabled Vector (programmable : 8,16,32,64)
2547 void Assembler::evmovdqub(XMMRegister dst, XMMRegister src, int vector_len) {
2548 assert(VM_Version::supports_evex(), "");
2549 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
2550 attributes.set_is_evex_instruction();
2551 int prefix = (_legacy_mode_bw) ? VEX_SIMD_F2 : VEX_SIMD_F3;
2552 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), (Assembler::VexSimdPrefix)prefix, VEX_OPCODE_0F, &attributes);
2553 emit_int8(0x6F);
2554 emit_int8((unsigned char)(0xC0 | encode));
2555 }
2556
2557 void Assembler::evmovdqub(XMMRegister dst, Address src, int vector_len) {
2558 assert(VM_Version::supports_evex(), "");
2559 InstructionMark im(this);
2560 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
2561 int prefix = (_legacy_mode_bw) ? VEX_SIMD_F2 : VEX_SIMD_F3;
2562 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2563 attributes.set_is_evex_instruction();
2564 vex_prefix(src, 0, dst->encoding(), (Assembler::VexSimdPrefix)prefix, VEX_OPCODE_0F, &attributes);
2565 emit_int8(0x6F);
2566 emit_operand(dst, src);
2567 }
2568
2569 void Assembler::evmovdqub(Address dst, XMMRegister src, int vector_len) {
2570 assert(VM_Version::supports_evex(), "");
2571 assert(src != xnoreg, "sanity");
2572 InstructionMark im(this);
2573 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
2574 int prefix = (_legacy_mode_bw) ? VEX_SIMD_F2 : VEX_SIMD_F3;
2575 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2576 attributes.set_is_evex_instruction();
2577 vex_prefix(dst, 0, src->encoding(), (Assembler::VexSimdPrefix)prefix, VEX_OPCODE_0F, &attributes);
2578 emit_int8(0x7F);
2579 emit_operand(src, dst);
2580 }
2581
2582 void Assembler::evmovdqub(XMMRegister dst, KRegister mask, Address src, int vector_len) {
2583 assert(VM_Version::supports_avx512vlbw(), "");
2584 assert(is_vector_masking(), ""); // For stub code use only
2585 InstructionMark im(this);
2586 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
2587 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2588 attributes.set_embedded_opmask_register_specifier(mask);
2589 attributes.set_is_evex_instruction();
2590 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2591 emit_int8(0x6F);
2592 emit_operand(dst, src);
2593 }
2594
2595 void Assembler::evmovdquw(XMMRegister dst, Address src, int vector_len) {
2596 assert(VM_Version::supports_evex(), "");
2597 InstructionMark im(this);
2598 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
2599 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2600 attributes.set_is_evex_instruction();
2601 int prefix = (_legacy_mode_bw) ? VEX_SIMD_F2 : VEX_SIMD_F3;
2602 vex_prefix(src, 0, dst->encoding(), (Assembler::VexSimdPrefix)prefix, VEX_OPCODE_0F, &attributes);
2603 emit_int8(0x6F);
2604 emit_operand(dst, src);
2605 }
2606
2607 void Assembler::evmovdquw(XMMRegister dst, KRegister mask, Address src, int vector_len) {
2608 assert(is_vector_masking(), "");
2609 assert(VM_Version::supports_avx512vlbw(), "");
2610 InstructionMark im(this);
2611 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
2612 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2613 attributes.set_embedded_opmask_register_specifier(mask);
2614 attributes.set_is_evex_instruction();
2615 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2616 emit_int8(0x6F);
2617 emit_operand(dst, src);
2618 }
2619
2620 void Assembler::evmovdquw(Address dst, XMMRegister src, int vector_len) {
2621 assert(VM_Version::supports_evex(), "");
2622 assert(src != xnoreg, "sanity");
2623 InstructionMark im(this);
2624 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
2625 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2626 attributes.set_is_evex_instruction();
2627 int prefix = (_legacy_mode_bw) ? VEX_SIMD_F2 : VEX_SIMD_F3;
2628 vex_prefix(dst, 0, src->encoding(), (Assembler::VexSimdPrefix)prefix, VEX_OPCODE_0F, &attributes);
2629 emit_int8(0x7F);
2630 emit_operand(src, dst);
2631 }
2632
2633 void Assembler::evmovdquw(Address dst, KRegister mask, XMMRegister src, int vector_len) {
2634 assert(VM_Version::supports_avx512vlbw(), "");
2635 assert(src != xnoreg, "sanity");
2636 InstructionMark im(this);
2637 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2638 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2639 attributes.reset_is_clear_context();
2640 attributes.set_embedded_opmask_register_specifier(mask);
2641 attributes.set_is_evex_instruction();
2642 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2643 emit_int8(0x7F);
2644 emit_operand(src, dst);
2645 }
2646
2647 void Assembler::evmovdqul(XMMRegister dst, XMMRegister src, int vector_len) {
2648 assert(VM_Version::supports_evex(), "");
2649 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2650 attributes.set_is_evex_instruction();
2651 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2652 emit_int8(0x6F);
2653 emit_int8((unsigned char)(0xC0 | encode));
2654 }
2655
2656 void Assembler::evmovdqul(XMMRegister dst, Address src, int vector_len) {
2657 assert(VM_Version::supports_evex(), "");
2658 InstructionMark im(this);
2659 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false , /* uses_vl */ true);
2660 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2661 attributes.set_is_evex_instruction();
2662 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2663 emit_int8(0x6F);
2664 emit_operand(dst, src);
2665 }
2666
2667 void Assembler::evmovdqul(Address dst, XMMRegister src, int vector_len) {
2668 assert(VM_Version::supports_evex(), "");
2669 assert(src != xnoreg, "sanity");
2670 InstructionMark im(this);
2671 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2672 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2673 attributes.reset_is_clear_context();
2674 attributes.set_is_evex_instruction();
2675 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2676 emit_int8(0x7F);
2677 emit_operand(src, dst);
2678 }
2679
2680 void Assembler::evmovdquq(XMMRegister dst, XMMRegister src, int vector_len) {
2681 assert(VM_Version::supports_evex(), "");
2682 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2683 attributes.set_is_evex_instruction();
2684 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2685 emit_int8(0x6F);
2686 emit_int8((unsigned char)(0xC0 | encode));
2687 }
2688
2689 void Assembler::evmovdquq(XMMRegister dst, Address src, int vector_len) {
2690 assert(VM_Version::supports_evex(), "");
2691 InstructionMark im(this);
2692 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2693 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2694 attributes.set_is_evex_instruction();
2695 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2696 emit_int8(0x6F);
2697 emit_operand(dst, src);
2698 }
2699
2700 void Assembler::evmovdquq(Address dst, XMMRegister src, int vector_len) {
2701 assert(VM_Version::supports_evex(), "");
2702 assert(src != xnoreg, "sanity");
2703 InstructionMark im(this);
2704 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2705 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2706 attributes.reset_is_clear_context();
2707 attributes.set_is_evex_instruction();
2708 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2709 emit_int8(0x7F);
2710 emit_operand(src, dst);
2711 }
2712
2713 // Uses zero extension on 64bit
2714
2715 void Assembler::movl(Register dst, int32_t imm32) {
2716 int encode = prefix_and_encode(dst->encoding());
2717 emit_int8((unsigned char)(0xB8 | encode));
2718 emit_int32(imm32);
2719 }
2720
2721 void Assembler::movl(Register dst, Register src) {
2722 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2723 emit_int8((unsigned char)0x8B);
2724 emit_int8((unsigned char)(0xC0 | encode));
2725 }
2726
2727 void Assembler::movl(Register dst, Address src) {
2728 InstructionMark im(this);
2729 prefix(src, dst);
2730 emit_int8((unsigned char)0x8B);
2731 emit_operand(dst, src);
2732 }
2733
2734 void Assembler::movl(Address dst, int32_t imm32) {
2735 InstructionMark im(this);
2736 prefix(dst);
2737 emit_int8((unsigned char)0xC7);
2738 emit_operand(rax, dst, 4);
2739 emit_int32(imm32);
2740 }
2741
2742 void Assembler::movl(Address dst, Register src) {
2743 InstructionMark im(this);
2744 prefix(dst, src);
2745 emit_int8((unsigned char)0x89);
2746 emit_operand(src, dst);
2747 }
2748
2749 // New cpus require to use movsd and movss to avoid partial register stall
2750 // when loading from memory. But for old Opteron use movlpd instead of movsd.
2751 // The selection is done in MacroAssembler::movdbl() and movflt().
2752 void Assembler::movlpd(XMMRegister dst, Address src) {
2753 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2754 InstructionMark im(this);
2755 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2756 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
2757 attributes.set_rex_vex_w_reverted();
2758 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2759 emit_int8(0x12);
2760 emit_operand(dst, src);
2761 }
2762
2763 void Assembler::movq( MMXRegister dst, Address src ) {
2764 assert( VM_Version::supports_mmx(), "" );
2765 emit_int8(0x0F);
2766 emit_int8(0x6F);
2767 emit_operand(dst, src);
2768 }
2769
2770 void Assembler::movq( Address dst, MMXRegister src ) {
2771 assert( VM_Version::supports_mmx(), "" );
2772 emit_int8(0x0F);
2773 emit_int8(0x7F);
2774 // workaround gcc (3.2.1-7a) bug
2775 // In that version of gcc with only an emit_operand(MMX, Address)
2776 // gcc will tail jump and try and reverse the parameters completely
2777 // obliterating dst in the process. By having a version available
2778 // that doesn't need to swap the args at the tail jump the bug is
2779 // avoided.
2780 emit_operand(dst, src);
2781 }
2782
2783 void Assembler::movq(XMMRegister dst, Address src) {
2784 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2785 InstructionMark im(this);
2786 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2787 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
2788 attributes.set_rex_vex_w_reverted();
2789 simd_prefix(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2790 emit_int8(0x7E);
2791 emit_operand(dst, src);
2792 }
2793
2794 void Assembler::movq(Address dst, XMMRegister src) {
2795 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2796 InstructionMark im(this);
2797 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2798 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
2799 attributes.set_rex_vex_w_reverted();
2800 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2801 emit_int8((unsigned char)0xD6);
2802 emit_operand(src, dst);
2803 }
2804
2805 void Assembler::movsbl(Register dst, Address src) { // movsxb
2806 InstructionMark im(this);
2807 prefix(src, dst);
2808 emit_int8(0x0F);
2809 emit_int8((unsigned char)0xBE);
2810 emit_operand(dst, src);
2811 }
2812
2813 void Assembler::movsbl(Register dst, Register src) { // movsxb
2814 NOT_LP64(assert(src->has_byte_register(), "must have byte register"));
2815 int encode = prefix_and_encode(dst->encoding(), false, src->encoding(), true);
2816 emit_int8(0x0F);
2817 emit_int8((unsigned char)0xBE);
2818 emit_int8((unsigned char)(0xC0 | encode));
2819 }
2820
2821 void Assembler::movsd(XMMRegister dst, XMMRegister src) {
2822 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2823 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2824 attributes.set_rex_vex_w_reverted();
2825 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2826 emit_int8(0x10);
2827 emit_int8((unsigned char)(0xC0 | encode));
2828 }
2829
2830 void Assembler::movsd(XMMRegister dst, Address src) {
2831 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2832 InstructionMark im(this);
2833 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2834 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
2835 attributes.set_rex_vex_w_reverted();
2836 simd_prefix(dst, xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2837 emit_int8(0x10);
2838 emit_operand(dst, src);
2839 }
2840
2841 void Assembler::movsd(Address dst, XMMRegister src) {
2842 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2843 InstructionMark im(this);
2844 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2845 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
2846 attributes.reset_is_clear_context();
2847 attributes.set_rex_vex_w_reverted();
2848 simd_prefix(src, xnoreg, dst, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2849 emit_int8(0x11);
2850 emit_operand(src, dst);
2851 }
2852
2853 void Assembler::movss(XMMRegister dst, XMMRegister src) {
2854 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2855 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2856 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2857 emit_int8(0x10);
2858 emit_int8((unsigned char)(0xC0 | encode));
2859 }
2860
2861 void Assembler::movss(XMMRegister dst, Address src) {
2862 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2863 InstructionMark im(this);
2864 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2865 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
2866 simd_prefix(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2867 emit_int8(0x10);
2868 emit_operand(dst, src);
2869 }
2870
2871 void Assembler::movss(Address dst, XMMRegister src) {
2872 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2873 InstructionMark im(this);
2874 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2875 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
2876 attributes.reset_is_clear_context();
2877 simd_prefix(src, xnoreg, dst, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2878 emit_int8(0x11);
2879 emit_operand(src, dst);
2880 }
2881
2882 void Assembler::movswl(Register dst, Address src) { // movsxw
2883 InstructionMark im(this);
2884 prefix(src, dst);
2885 emit_int8(0x0F);
2886 emit_int8((unsigned char)0xBF);
2887 emit_operand(dst, src);
2888 }
2889
2890 void Assembler::movswl(Register dst, Register src) { // movsxw
2891 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2892 emit_int8(0x0F);
2893 emit_int8((unsigned char)0xBF);
2894 emit_int8((unsigned char)(0xC0 | encode));
2895 }
2896
2897 void Assembler::movw(Address dst, int imm16) {
2898 InstructionMark im(this);
2899
2900 emit_int8(0x66); // switch to 16-bit mode
2901 prefix(dst);
2902 emit_int8((unsigned char)0xC7);
2903 emit_operand(rax, dst, 2);
2904 emit_int16(imm16);
2905 }
2906
2907 void Assembler::movw(Register dst, Address src) {
2908 InstructionMark im(this);
2909 emit_int8(0x66);
2910 prefix(src, dst);
2911 emit_int8((unsigned char)0x8B);
2912 emit_operand(dst, src);
2913 }
2914
2915 void Assembler::movw(Address dst, Register src) {
2916 InstructionMark im(this);
2917 emit_int8(0x66);
2918 prefix(dst, src);
2919 emit_int8((unsigned char)0x89);
2920 emit_operand(src, dst);
2921 }
2922
2923 void Assembler::movzbl(Register dst, Address src) { // movzxb
2924 InstructionMark im(this);
2925 prefix(src, dst);
2926 emit_int8(0x0F);
2927 emit_int8((unsigned char)0xB6);
2928 emit_operand(dst, src);
2929 }
2930
2931 void Assembler::movzbl(Register dst, Register src) { // movzxb
2932 NOT_LP64(assert(src->has_byte_register(), "must have byte register"));
2933 int encode = prefix_and_encode(dst->encoding(), false, src->encoding(), true);
2934 emit_int8(0x0F);
2935 emit_int8((unsigned char)0xB6);
2936 emit_int8(0xC0 | encode);
2937 }
2938
2939 void Assembler::movzwl(Register dst, Address src) { // movzxw
2940 InstructionMark im(this);
2941 prefix(src, dst);
2942 emit_int8(0x0F);
2943 emit_int8((unsigned char)0xB7);
2944 emit_operand(dst, src);
2945 }
2946
2947 void Assembler::movzwl(Register dst, Register src) { // movzxw
2948 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2949 emit_int8(0x0F);
2950 emit_int8((unsigned char)0xB7);
2951 emit_int8(0xC0 | encode);
2952 }
2953
2954 void Assembler::mull(Address src) {
2955 InstructionMark im(this);
2956 prefix(src);
2957 emit_int8((unsigned char)0xF7);
2958 emit_operand(rsp, src);
2959 }
2960
2961 void Assembler::mull(Register src) {
2962 int encode = prefix_and_encode(src->encoding());
2963 emit_int8((unsigned char)0xF7);
2964 emit_int8((unsigned char)(0xE0 | encode));
2965 }
2966
2967 void Assembler::mulsd(XMMRegister dst, Address src) {
2968 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2969 InstructionMark im(this);
2970 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2971 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
2972 attributes.set_rex_vex_w_reverted();
2973 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2974 emit_int8(0x59);
2975 emit_operand(dst, src);
2976 }
2977
2978 void Assembler::mulsd(XMMRegister dst, XMMRegister src) {
2979 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2980 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2981 attributes.set_rex_vex_w_reverted();
2982 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2983 emit_int8(0x59);
2984 emit_int8((unsigned char)(0xC0 | encode));
2985 }
2986
2987 void Assembler::mulss(XMMRegister dst, Address src) {
2988 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2989 InstructionMark im(this);
2990 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2991 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
2992 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2993 emit_int8(0x59);
2994 emit_operand(dst, src);
2995 }
2996
2997 void Assembler::mulss(XMMRegister dst, XMMRegister src) {
2998 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2999 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3000 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
3001 emit_int8(0x59);
3002 emit_int8((unsigned char)(0xC0 | encode));
3003 }
3004
3005 void Assembler::negl(Register dst) {
3006 int encode = prefix_and_encode(dst->encoding());
3007 emit_int8((unsigned char)0xF7);
3008 emit_int8((unsigned char)(0xD8 | encode));
3009 }
3010
3011 void Assembler::nop(int i) {
3012 #ifdef ASSERT
3013 assert(i > 0, " ");
3014 // The fancy nops aren't currently recognized by debuggers making it a
3015 // pain to disassemble code while debugging. If asserts are on clearly
3016 // speed is not an issue so simply use the single byte traditional nop
3017 // to do alignment.
3018
3019 for (; i > 0 ; i--) emit_int8((unsigned char)0x90);
3020 return;
3021
3022 #endif // ASSERT
3023
3024 if (UseAddressNop && VM_Version::is_intel()) {
3025 //
3026 // Using multi-bytes nops "0x0F 0x1F [address]" for Intel
3027 // 1: 0x90
3028 // 2: 0x66 0x90
3029 // 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding)
3030 // 4: 0x0F 0x1F 0x40 0x00
3031 // 5: 0x0F 0x1F 0x44 0x00 0x00
3032 // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00
3033 // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
3034 // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3035 // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3036 // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3037 // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3038
3039 // The rest coding is Intel specific - don't use consecutive address nops
3040
3041 // 12: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
3042 // 13: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
3043 // 14: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
3044 // 15: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
3045
3046 while(i >= 15) {
3047 // For Intel don't generate consecutive addess nops (mix with regular nops)
3048 i -= 15;
3049 emit_int8(0x66); // size prefix
3050 emit_int8(0x66); // size prefix
3051 emit_int8(0x66); // size prefix
3052 addr_nop_8();
3053 emit_int8(0x66); // size prefix
3054 emit_int8(0x66); // size prefix
3055 emit_int8(0x66); // size prefix
3056 emit_int8((unsigned char)0x90);
3057 // nop
3058 }
3059 switch (i) {
3060 case 14:
3061 emit_int8(0x66); // size prefix
3062 case 13:
3063 emit_int8(0x66); // size prefix
3064 case 12:
3065 addr_nop_8();
3066 emit_int8(0x66); // size prefix
3067 emit_int8(0x66); // size prefix
3068 emit_int8(0x66); // size prefix
3069 emit_int8((unsigned char)0x90);
3070 // nop
3071 break;
3072 case 11:
3073 emit_int8(0x66); // size prefix
3074 case 10:
3075 emit_int8(0x66); // size prefix
3076 case 9:
3077 emit_int8(0x66); // size prefix
3078 case 8:
3079 addr_nop_8();
3080 break;
3081 case 7:
3082 addr_nop_7();
3083 break;
3084 case 6:
3085 emit_int8(0x66); // size prefix
3086 case 5:
3087 addr_nop_5();
3088 break;
3089 case 4:
3090 addr_nop_4();
3091 break;
3092 case 3:
3093 // Don't use "0x0F 0x1F 0x00" - need patching safe padding
3094 emit_int8(0x66); // size prefix
3095 case 2:
3096 emit_int8(0x66); // size prefix
3097 case 1:
3098 emit_int8((unsigned char)0x90);
3099 // nop
3100 break;
3101 default:
3102 assert(i == 0, " ");
3103 }
3104 return;
3105 }
3106 if (UseAddressNop && VM_Version::is_amd()) {
3107 //
3108 // Using multi-bytes nops "0x0F 0x1F [address]" for AMD.
3109 // 1: 0x90
3110 // 2: 0x66 0x90
3111 // 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding)
3112 // 4: 0x0F 0x1F 0x40 0x00
3113 // 5: 0x0F 0x1F 0x44 0x00 0x00
3114 // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00
3115 // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
3116 // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3117 // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3118 // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3119 // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3120
3121 // The rest coding is AMD specific - use consecutive address nops
3122
3123 // 12: 0x66 0x0F 0x1F 0x44 0x00 0x00 0x66 0x0F 0x1F 0x44 0x00 0x00
3124 // 13: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 0x66 0x0F 0x1F 0x44 0x00 0x00
3125 // 14: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
3126 // 15: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
3127 // 16: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3128 // Size prefixes (0x66) are added for larger sizes
3129
3130 while(i >= 22) {
3131 i -= 11;
3132 emit_int8(0x66); // size prefix
3133 emit_int8(0x66); // size prefix
3134 emit_int8(0x66); // size prefix
3135 addr_nop_8();
3136 }
3137 // Generate first nop for size between 21-12
3138 switch (i) {
3139 case 21:
3140 i -= 1;
3141 emit_int8(0x66); // size prefix
3142 case 20:
3143 case 19:
3144 i -= 1;
3145 emit_int8(0x66); // size prefix
3146 case 18:
3147 case 17:
3148 i -= 1;
3149 emit_int8(0x66); // size prefix
3150 case 16:
3151 case 15:
3152 i -= 8;
3153 addr_nop_8();
3154 break;
3155 case 14:
3156 case 13:
3157 i -= 7;
3158 addr_nop_7();
3159 break;
3160 case 12:
3161 i -= 6;
3162 emit_int8(0x66); // size prefix
3163 addr_nop_5();
3164 break;
3165 default:
3166 assert(i < 12, " ");
3167 }
3168
3169 // Generate second nop for size between 11-1
3170 switch (i) {
3171 case 11:
3172 emit_int8(0x66); // size prefix
3173 case 10:
3174 emit_int8(0x66); // size prefix
3175 case 9:
3176 emit_int8(0x66); // size prefix
3177 case 8:
3178 addr_nop_8();
3179 break;
3180 case 7:
3181 addr_nop_7();
3182 break;
3183 case 6:
3184 emit_int8(0x66); // size prefix
3185 case 5:
3186 addr_nop_5();
3187 break;
3188 case 4:
3189 addr_nop_4();
3190 break;
3191 case 3:
3192 // Don't use "0x0F 0x1F 0x00" - need patching safe padding
3193 emit_int8(0x66); // size prefix
3194 case 2:
3195 emit_int8(0x66); // size prefix
3196 case 1:
3197 emit_int8((unsigned char)0x90);
3198 // nop
3199 break;
3200 default:
3201 assert(i == 0, " ");
3202 }
3203 return;
3204 }
3205
3206 if (UseAddressNop && VM_Version::is_zx()) {
3207 //
3208 // Using multi-bytes nops "0x0F 0x1F [address]" for ZX
3209 // 1: 0x90
3210 // 2: 0x66 0x90
3211 // 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding)
3212 // 4: 0x0F 0x1F 0x40 0x00
3213 // 5: 0x0F 0x1F 0x44 0x00 0x00
3214 // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00
3215 // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
3216 // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3217 // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3218 // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3219 // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3220
3221 // The rest coding is ZX specific - don't use consecutive address nops
3222
3223 // 12: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
3224 // 13: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
3225 // 14: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
3226 // 15: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
3227
3228 while (i >= 15) {
3229 // For ZX don't generate consecutive addess nops (mix with regular nops)
3230 i -= 15;
3231 emit_int8(0x66); // size prefix
3232 emit_int8(0x66); // size prefix
3233 emit_int8(0x66); // size prefix
3234 addr_nop_8();
3235 emit_int8(0x66); // size prefix
3236 emit_int8(0x66); // size prefix
3237 emit_int8(0x66); // size prefix
3238 emit_int8((unsigned char)0x90);
3239 // nop
3240 }
3241 switch (i) {
3242 case 14:
3243 emit_int8(0x66); // size prefix
3244 case 13:
3245 emit_int8(0x66); // size prefix
3246 case 12:
3247 addr_nop_8();
3248 emit_int8(0x66); // size prefix
3249 emit_int8(0x66); // size prefix
3250 emit_int8(0x66); // size prefix
3251 emit_int8((unsigned char)0x90);
3252 // nop
3253 break;
3254 case 11:
3255 emit_int8(0x66); // size prefix
3256 case 10:
3257 emit_int8(0x66); // size prefix
3258 case 9:
3259 emit_int8(0x66); // size prefix
3260 case 8:
3261 addr_nop_8();
3262 break;
3263 case 7:
3264 addr_nop_7();
3265 break;
3266 case 6:
3267 emit_int8(0x66); // size prefix
3268 case 5:
3269 addr_nop_5();
3270 break;
3271 case 4:
3272 addr_nop_4();
3273 break;
3274 case 3:
3275 // Don't use "0x0F 0x1F 0x00" - need patching safe padding
3276 emit_int8(0x66); // size prefix
3277 case 2:
3278 emit_int8(0x66); // size prefix
3279 case 1:
3280 emit_int8((unsigned char)0x90);
3281 // nop
3282 break;
3283 default:
3284 assert(i == 0, " ");
3285 }
3286 return;
3287 }
3288
3289 // Using nops with size prefixes "0x66 0x90".
3290 // From AMD Optimization Guide:
3291 // 1: 0x90
3292 // 2: 0x66 0x90
3293 // 3: 0x66 0x66 0x90
3294 // 4: 0x66 0x66 0x66 0x90
3295 // 5: 0x66 0x66 0x90 0x66 0x90
3296 // 6: 0x66 0x66 0x90 0x66 0x66 0x90
3297 // 7: 0x66 0x66 0x66 0x90 0x66 0x66 0x90
3298 // 8: 0x66 0x66 0x66 0x90 0x66 0x66 0x66 0x90
3299 // 9: 0x66 0x66 0x90 0x66 0x66 0x90 0x66 0x66 0x90
3300 // 10: 0x66 0x66 0x66 0x90 0x66 0x66 0x90 0x66 0x66 0x90
3301 //
3302 while(i > 12) {
3303 i -= 4;
3304 emit_int8(0x66); // size prefix
3305 emit_int8(0x66);
3306 emit_int8(0x66);
3307 emit_int8((unsigned char)0x90);
3308 // nop
3309 }
3310 // 1 - 12 nops
3311 if(i > 8) {
3312 if(i > 9) {
3313 i -= 1;
3314 emit_int8(0x66);
3315 }
3316 i -= 3;
3317 emit_int8(0x66);
3318 emit_int8(0x66);
3319 emit_int8((unsigned char)0x90);
3320 }
3321 // 1 - 8 nops
3322 if(i > 4) {
3323 if(i > 6) {
3324 i -= 1;
3325 emit_int8(0x66);
3326 }
3327 i -= 3;
3328 emit_int8(0x66);
3329 emit_int8(0x66);
3330 emit_int8((unsigned char)0x90);
3331 }
3332 switch (i) {
3333 case 4:
3334 emit_int8(0x66);
3335 case 3:
3336 emit_int8(0x66);
3337 case 2:
3338 emit_int8(0x66);
3339 case 1:
3340 emit_int8((unsigned char)0x90);
3341 break;
3342 default:
3343 assert(i == 0, " ");
3344 }
3345 }
3346
3347 void Assembler::notl(Register dst) {
3348 int encode = prefix_and_encode(dst->encoding());
3349 emit_int8((unsigned char)0xF7);
3350 emit_int8((unsigned char)(0xD0 | encode));
3351 }
3352
3353 void Assembler::orl(Address dst, int32_t imm32) {
3354 InstructionMark im(this);
3355 prefix(dst);
3356 emit_arith_operand(0x81, rcx, dst, imm32);
3357 }
3358
3359 void Assembler::orl(Register dst, int32_t imm32) {
3360 prefix(dst);
3361 emit_arith(0x81, 0xC8, dst, imm32);
3362 }
3363
3364 void Assembler::orl(Register dst, Address src) {
3365 InstructionMark im(this);
3366 prefix(src, dst);
3367 emit_int8(0x0B);
3368 emit_operand(dst, src);
3369 }
3370
3371 void Assembler::orl(Register dst, Register src) {
3372 (void) prefix_and_encode(dst->encoding(), src->encoding());
3373 emit_arith(0x0B, 0xC0, dst, src);
3374 }
3375
3376 void Assembler::orl(Address dst, Register src) {
3377 InstructionMark im(this);
3378 prefix(dst, src);
3379 emit_int8(0x09);
3380 emit_operand(src, dst);
3381 }
3382
3383 void Assembler::orb(Address dst, int imm8) {
3384 InstructionMark im(this);
3385 prefix(dst);
3386 emit_int8((unsigned char)0x80);
3387 emit_operand(rcx, dst, 1);
3388 emit_int8(imm8);
3389 }
3390
3391 void Assembler::packuswb(XMMRegister dst, Address src) {
3392 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3393 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
3394 InstructionMark im(this);
3395 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
3396 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
3397 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3398 emit_int8(0x67);
3399 emit_operand(dst, src);
3400 }
3401
3402 void Assembler::packuswb(XMMRegister dst, XMMRegister src) {
3403 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3404 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
3405 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3406 emit_int8(0x67);
3407 emit_int8((unsigned char)(0xC0 | encode));
3408 }
3409
3410 void Assembler::vpackuswb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3411 assert(UseAVX > 0, "some form of AVX must be enabled");
3412 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
3413 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3414 emit_int8(0x67);
3415 emit_int8((unsigned char)(0xC0 | encode));
3416 }
3417
3418 void Assembler::vpermq(XMMRegister dst, XMMRegister src, int imm8, int vector_len) {
3419 assert(VM_Version::supports_avx2(), "");
3420 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3421 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3422 emit_int8(0x00);
3423 emit_int8(0xC0 | encode);
3424 emit_int8(imm8);
3425 }
3426
3427 void Assembler::vperm2i128(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8) {
3428 assert(VM_Version::supports_avx2(), "");
3429 InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3430 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3431 emit_int8(0x46);
3432 emit_int8(0xC0 | encode);
3433 emit_int8(imm8);
3434 }
3435
3436 void Assembler::vperm2f128(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8) {
3437 assert(VM_Version::supports_avx(), "");
3438 InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3439 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3440 emit_int8(0x06);
3441 emit_int8(0xC0 | encode);
3442 emit_int8(imm8);
3443 }
3444
3445 void Assembler::evpermi2q(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3446 assert(VM_Version::supports_evex(), "");
3447 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3448 attributes.set_is_evex_instruction();
3449 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3450 emit_int8(0x76);
3451 emit_int8((unsigned char)(0xC0 | encode));
3452 }
3453
3454
3455 void Assembler::pause() {
3456 emit_int8((unsigned char)0xF3);
3457 emit_int8((unsigned char)0x90);
3458 }
3459
3460 void Assembler::ud2() {
3461 emit_int8(0x0F);
3462 emit_int8(0x0B);
3463 }
3464
3465 void Assembler::pcmpestri(XMMRegister dst, Address src, int imm8) {
3466 assert(VM_Version::supports_sse4_2(), "");
3467 InstructionMark im(this);
3468 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3469 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3470 emit_int8(0x61);
3471 emit_operand(dst, src);
3472 emit_int8(imm8);
3473 }
3474
3475 void Assembler::pcmpestri(XMMRegister dst, XMMRegister src, int imm8) {
3476 assert(VM_Version::supports_sse4_2(), "");
3477 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3478 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3479 emit_int8(0x61);
3480 emit_int8((unsigned char)(0xC0 | encode));
3481 emit_int8(imm8);
3482 }
3483
3484 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3485 void Assembler::pcmpeqb(XMMRegister dst, XMMRegister src) {
3486 assert(VM_Version::supports_sse2(), "");
3487 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3488 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3489 emit_int8(0x74);
3490 emit_int8((unsigned char)(0xC0 | encode));
3491 }
3492
3493 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3494 void Assembler::vpcmpeqb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3495 assert(VM_Version::supports_avx(), "");
3496 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3497 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3498 emit_int8(0x74);
3499 emit_int8((unsigned char)(0xC0 | encode));
3500 }
3501
3502 // In this context, kdst is written the mask used to process the equal components
3503 void Assembler::evpcmpeqb(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len) {
3504 assert(VM_Version::supports_avx512bw(), "");
3505 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3506 attributes.set_is_evex_instruction();
3507 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3508 emit_int8(0x74);
3509 emit_int8((unsigned char)(0xC0 | encode));
3510 }
3511
3512 void Assembler::evpcmpgtb(KRegister kdst, XMMRegister nds, Address src, int vector_len) {
3513 assert(VM_Version::supports_avx512vlbw(), "");
3514 InstructionMark im(this);
3515 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3516 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3517 attributes.set_is_evex_instruction();
3518 int dst_enc = kdst->encoding();
3519 vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3520 emit_int8(0x64);
3521 emit_operand(as_Register(dst_enc), src);
3522 }
3523
3524 void Assembler::evpcmpgtb(KRegister kdst, KRegister mask, XMMRegister nds, Address src, int vector_len) {
3525 assert(is_vector_masking(), "");
3526 assert(VM_Version::supports_avx512vlbw(), "");
3527 InstructionMark im(this);
3528 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
3529 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3530 attributes.reset_is_clear_context();
3531 attributes.set_embedded_opmask_register_specifier(mask);
3532 attributes.set_is_evex_instruction();
3533 int dst_enc = kdst->encoding();
3534 vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3535 emit_int8(0x64);
3536 emit_operand(as_Register(dst_enc), src);
3537 }
3538
3539 void Assembler::evpcmpuw(KRegister kdst, XMMRegister nds, XMMRegister src, ComparisonPredicate vcc, int vector_len) {
3540 assert(VM_Version::supports_avx512vlbw(), "");
3541 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3542 attributes.set_is_evex_instruction();
3543 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3544 emit_int8(0x3E);
3545 emit_int8((unsigned char)(0xC0 | encode));
3546 emit_int8(vcc);
3547 }
3548
3549 void Assembler::evpcmpuw(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src, ComparisonPredicate vcc, int vector_len) {
3550 assert(is_vector_masking(), "");
3551 assert(VM_Version::supports_avx512vlbw(), "");
3552 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
3553 attributes.reset_is_clear_context();
3554 attributes.set_embedded_opmask_register_specifier(mask);
3555 attributes.set_is_evex_instruction();
3556 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3557 emit_int8(0x3E);
3558 emit_int8((unsigned char)(0xC0 | encode));
3559 emit_int8(vcc);
3560 }
3561
3562 void Assembler::evpcmpuw(KRegister kdst, XMMRegister nds, Address src, ComparisonPredicate vcc, int vector_len) {
3563 assert(VM_Version::supports_avx512vlbw(), "");
3564 InstructionMark im(this);
3565 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3566 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3567 attributes.set_is_evex_instruction();
3568 int dst_enc = kdst->encoding();
3569 vex_prefix(src, nds->encoding(), kdst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3570 emit_int8(0x3E);
3571 emit_operand(as_Register(dst_enc), src);
3572 emit_int8(vcc);
3573 }
3574
3575 void Assembler::evpcmpeqb(KRegister kdst, XMMRegister nds, Address src, int vector_len) {
3576 assert(VM_Version::supports_avx512bw(), "");
3577 InstructionMark im(this);
3578 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3579 attributes.set_is_evex_instruction();
3580 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3581 int dst_enc = kdst->encoding();
3582 vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3583 emit_int8(0x74);
3584 emit_operand(as_Register(dst_enc), src);
3585 }
3586
3587 void Assembler::evpcmpeqb(KRegister kdst, KRegister mask, XMMRegister nds, Address src, int vector_len) {
3588 assert(VM_Version::supports_avx512vlbw(), "");
3589 assert(is_vector_masking(), ""); // For stub code use only
3590 InstructionMark im(this);
3591 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_reg_mask */ false, /* uses_vl */ false);
3592 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3593 attributes.reset_is_clear_context();
3594 attributes.set_embedded_opmask_register_specifier(mask);
3595 attributes.set_is_evex_instruction();
3596 vex_prefix(src, nds->encoding(), kdst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3597 emit_int8(0x74);
3598 emit_operand(as_Register(kdst->encoding()), src);
3599 }
3600
3601 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3602 void Assembler::pcmpeqw(XMMRegister dst, XMMRegister src) {
3603 assert(VM_Version::supports_sse2(), "");
3604 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3605 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3606 emit_int8(0x75);
3607 emit_int8((unsigned char)(0xC0 | encode));
3608 }
3609
3610 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3611 void Assembler::vpcmpeqw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3612 assert(VM_Version::supports_avx(), "");
3613 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3614 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3615 emit_int8(0x75);
3616 emit_int8((unsigned char)(0xC0 | encode));
3617 }
3618
3619 // In this context, kdst is written the mask used to process the equal components
3620 void Assembler::evpcmpeqw(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len) {
3621 assert(VM_Version::supports_avx512bw(), "");
3622 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3623 attributes.set_is_evex_instruction();
3624 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3625 emit_int8(0x75);
3626 emit_int8((unsigned char)(0xC0 | encode));
3627 }
3628
3629 void Assembler::evpcmpeqw(KRegister kdst, XMMRegister nds, Address src, int vector_len) {
3630 assert(VM_Version::supports_avx512bw(), "");
3631 InstructionMark im(this);
3632 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3633 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3634 attributes.set_is_evex_instruction();
3635 int dst_enc = kdst->encoding();
3636 vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3637 emit_int8(0x75);
3638 emit_operand(as_Register(dst_enc), src);
3639 }
3640
3641 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3642 void Assembler::pcmpeqd(XMMRegister dst, XMMRegister src) {
3643 assert(VM_Version::supports_sse2(), "");
3644 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3645 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3646 emit_int8(0x76);
3647 emit_int8((unsigned char)(0xC0 | encode));
3648 }
3649
3650 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3651 void Assembler::vpcmpeqd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3652 assert(VM_Version::supports_avx(), "");
3653 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3654 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3655 emit_int8(0x76);
3656 emit_int8((unsigned char)(0xC0 | encode));
3657 }
3658
3659 // In this context, kdst is written the mask used to process the equal components
3660 void Assembler::evpcmpeqd(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len) {
3661 assert(VM_Version::supports_evex(), "");
3662 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3663 attributes.set_is_evex_instruction();
3664 attributes.reset_is_clear_context();
3665 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3666 emit_int8(0x76);
3667 emit_int8((unsigned char)(0xC0 | encode));
3668 }
3669
3670 void Assembler::evpcmpeqd(KRegister kdst, XMMRegister nds, Address src, int vector_len) {
3671 assert(VM_Version::supports_evex(), "");
3672 InstructionMark im(this);
3673 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3674 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
3675 attributes.reset_is_clear_context();
3676 attributes.set_is_evex_instruction();
3677 int dst_enc = kdst->encoding();
3678 vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3679 emit_int8(0x76);
3680 emit_operand(as_Register(dst_enc), src);
3681 }
3682
3683 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3684 void Assembler::pcmpeqq(XMMRegister dst, XMMRegister src) {
3685 assert(VM_Version::supports_sse4_1(), "");
3686 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3687 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3688 emit_int8(0x29);
3689 emit_int8((unsigned char)(0xC0 | encode));
3690 }
3691
3692 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3693 void Assembler::vpcmpeqq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3694 assert(VM_Version::supports_avx(), "");
3695 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3696 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3697 emit_int8(0x29);
3698 emit_int8((unsigned char)(0xC0 | encode));
3699 }
3700
3701 // In this context, kdst is written the mask used to process the equal components
3702 void Assembler::evpcmpeqq(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len) {
3703 assert(VM_Version::supports_evex(), "");
3704 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3705 attributes.reset_is_clear_context();
3706 attributes.set_is_evex_instruction();
3707 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3708 emit_int8(0x29);
3709 emit_int8((unsigned char)(0xC0 | encode));
3710 }
3711
3712 // In this context, kdst is written the mask used to process the equal components
3713 void Assembler::evpcmpeqq(KRegister kdst, XMMRegister nds, Address src, int vector_len) {
3714 assert(VM_Version::supports_evex(), "");
3715 InstructionMark im(this);
3716 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3717 attributes.reset_is_clear_context();
3718 attributes.set_is_evex_instruction();
3719 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
3720 int dst_enc = kdst->encoding();
3721 vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3722 emit_int8(0x29);
3723 emit_operand(as_Register(dst_enc), src);
3724 }
3725
3726 void Assembler::pmovmskb(Register dst, XMMRegister src) {
3727 assert(VM_Version::supports_sse2(), "");
3728 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3729 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3730 emit_int8((unsigned char)0xD7);
3731 emit_int8((unsigned char)(0xC0 | encode));
3732 }
3733
3734 void Assembler::vpmovmskb(Register dst, XMMRegister src) {
3735 assert(VM_Version::supports_avx2(), "");
3736 InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3737 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3738 emit_int8((unsigned char)0xD7);
3739 emit_int8((unsigned char)(0xC0 | encode));
3740 }
3741
3742 void Assembler::pextrd(Register dst, XMMRegister src, int imm8) {
3743 assert(VM_Version::supports_sse4_1(), "");
3744 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
3745 int encode = simd_prefix_and_encode(src, xnoreg, as_XMMRegister(dst->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3746 emit_int8(0x16);
3747 emit_int8((unsigned char)(0xC0 | encode));
3748 emit_int8(imm8);
3749 }
3750
3751 void Assembler::pextrd(Address dst, XMMRegister src, int imm8) {
3752 assert(VM_Version::supports_sse4_1(), "");
3753 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
3754 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
3755 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3756 emit_int8(0x16);
3757 emit_operand(src, dst);
3758 emit_int8(imm8);
3759 }
3760
3761 void Assembler::pextrq(Register dst, XMMRegister src, int imm8) {
3762 assert(VM_Version::supports_sse4_1(), "");
3763 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
3764 int encode = simd_prefix_and_encode(src, xnoreg, as_XMMRegister(dst->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3765 emit_int8(0x16);
3766 emit_int8((unsigned char)(0xC0 | encode));
3767 emit_int8(imm8);
3768 }
3769
3770 void Assembler::pextrq(Address dst, XMMRegister src, int imm8) {
3771 assert(VM_Version::supports_sse4_1(), "");
3772 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
3773 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
3774 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3775 emit_int8(0x16);
3776 emit_operand(src, dst);
3777 emit_int8(imm8);
3778 }
3779
3780 void Assembler::pextrw(Register dst, XMMRegister src, int imm8) {
3781 assert(VM_Version::supports_sse2(), "");
3782 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3783 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3784 emit_int8((unsigned char)0xC5);
3785 emit_int8((unsigned char)(0xC0 | encode));
3786 emit_int8(imm8);
3787 }
3788
3789 void Assembler::pextrw(Address dst, XMMRegister src, int imm8) {
3790 assert(VM_Version::supports_sse4_1(), "");
3791 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3792 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_16bit);
3793 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3794 emit_int8((unsigned char)0x15);
3795 emit_operand(src, dst);
3796 emit_int8(imm8);
3797 }
3798
3799 void Assembler::pextrb(Address dst, XMMRegister src, int imm8) {
3800 assert(VM_Version::supports_sse4_1(), "");
3801 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3802 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_8bit);
3803 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3804 emit_int8(0x14);
3805 emit_operand(src, dst);
3806 emit_int8(imm8);
3807 }
3808
3809 void Assembler::pinsrd(XMMRegister dst, Register src, int imm8) {
3810 assert(VM_Version::supports_sse4_1(), "");
3811 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
3812 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3813 emit_int8(0x22);
3814 emit_int8((unsigned char)(0xC0 | encode));
3815 emit_int8(imm8);
3816 }
3817
3818 void Assembler::pinsrd(XMMRegister dst, Address src, int imm8) {
3819 assert(VM_Version::supports_sse4_1(), "");
3820 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
3821 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
3822 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3823 emit_int8(0x22);
3824 emit_operand(dst,src);
3825 emit_int8(imm8);
3826 }
3827
3828 void Assembler::pinsrq(XMMRegister dst, Register src, int imm8) {
3829 assert(VM_Version::supports_sse4_1(), "");
3830 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
3831 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3832 emit_int8(0x22);
3833 emit_int8((unsigned char)(0xC0 | encode));
3834 emit_int8(imm8);
3835 }
3836
3837 void Assembler::pinsrq(XMMRegister dst, Address src, int imm8) {
3838 assert(VM_Version::supports_sse4_1(), "");
3839 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
3840 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
3841 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3842 emit_int8(0x22);
3843 emit_operand(dst, src);
3844 emit_int8(imm8);
3845 }
3846
3847 void Assembler::pinsrw(XMMRegister dst, Register src, int imm8) {
3848 assert(VM_Version::supports_sse2(), "");
3849 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3850 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3851 emit_int8((unsigned char)0xC4);
3852 emit_int8((unsigned char)(0xC0 | encode));
3853 emit_int8(imm8);
3854 }
3855
3856 void Assembler::pinsrw(XMMRegister dst, Address src, int imm8) {
3857 assert(VM_Version::supports_sse2(), "");
3858 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3859 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_16bit);
3860 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3861 emit_int8((unsigned char)0xC4);
3862 emit_operand(dst, src);
3863 emit_int8(imm8);
3864 }
3865
3866 void Assembler::pinsrb(XMMRegister dst, Address src, int imm8) {
3867 assert(VM_Version::supports_sse4_1(), "");
3868 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3869 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_8bit);
3870 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3871 emit_int8(0x20);
3872 emit_operand(dst, src);
3873 emit_int8(imm8);
3874 }
3875
3876 void Assembler::pmovzxbw(XMMRegister dst, Address src) {
3877 assert(VM_Version::supports_sse4_1(), "");
3878 InstructionMark im(this);
3879 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3880 attributes.set_address_attributes(/* tuple_type */ EVEX_HVM, /* input_size_in_bits */ EVEX_NObit);
3881 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3882 emit_int8(0x30);
3883 emit_operand(dst, src);
3884 }
3885
3886 void Assembler::pmovzxbw(XMMRegister dst, XMMRegister src) {
3887 assert(VM_Version::supports_sse4_1(), "");
3888 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3889 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3890 emit_int8(0x30);
3891 emit_int8((unsigned char)(0xC0 | encode));
3892 }
3893
3894 void Assembler::vpmovzxbw(XMMRegister dst, Address src, int vector_len) {
3895 assert(VM_Version::supports_avx(), "");
3896 InstructionMark im(this);
3897 assert(dst != xnoreg, "sanity");
3898 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3899 attributes.set_address_attributes(/* tuple_type */ EVEX_HVM, /* input_size_in_bits */ EVEX_NObit);
3900 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3901 emit_int8(0x30);
3902 emit_operand(dst, src);
3903 }
3904
3905 void Assembler::vpmovzxbw(XMMRegister dst, XMMRegister src, int vector_len) {
3906 assert(vector_len == AVX_128bit? VM_Version::supports_avx() :
3907 vector_len == AVX_256bit? VM_Version::supports_avx2() :
3908 vector_len == AVX_512bit? VM_Version::supports_avx512bw() : 0, "");
3909 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3910 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3911 emit_int8(0x30);
3912 emit_int8((unsigned char) (0xC0 | encode));
3913 }
3914
3915
3916 void Assembler::evpmovzxbw(XMMRegister dst, KRegister mask, Address src, int vector_len) {
3917 assert(is_vector_masking(), "");
3918 assert(VM_Version::supports_avx512vlbw(), "");
3919 assert(dst != xnoreg, "sanity");
3920 InstructionMark im(this);
3921 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
3922 attributes.set_address_attributes(/* tuple_type */ EVEX_HVM, /* input_size_in_bits */ EVEX_NObit);
3923 attributes.set_embedded_opmask_register_specifier(mask);
3924 attributes.set_is_evex_instruction();
3925 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3926 emit_int8(0x30);
3927 emit_operand(dst, src);
3928 }
3929 void Assembler::evpmovwb(Address dst, XMMRegister src, int vector_len) {
3930 assert(VM_Version::supports_avx512vlbw(), "");
3931 assert(src != xnoreg, "sanity");
3932 InstructionMark im(this);
3933 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3934 attributes.set_address_attributes(/* tuple_type */ EVEX_HVM, /* input_size_in_bits */ EVEX_NObit);
3935 attributes.set_is_evex_instruction();
3936 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes);
3937 emit_int8(0x30);
3938 emit_operand(src, dst);
3939 }
3940
3941 void Assembler::evpmovwb(Address dst, KRegister mask, XMMRegister src, int vector_len) {
3942 assert(is_vector_masking(), "");
3943 assert(VM_Version::supports_avx512vlbw(), "");
3944 assert(src != xnoreg, "sanity");
3945 InstructionMark im(this);
3946 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
3947 attributes.set_address_attributes(/* tuple_type */ EVEX_HVM, /* input_size_in_bits */ EVEX_NObit);
3948 attributes.reset_is_clear_context();
3949 attributes.set_embedded_opmask_register_specifier(mask);
3950 attributes.set_is_evex_instruction();
3951 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes);
3952 emit_int8(0x30);
3953 emit_operand(src, dst);
3954 }
3955
3956 void Assembler::evpmovdb(Address dst, XMMRegister src, int vector_len) {
3957 assert(VM_Version::supports_evex(), "");
3958 assert(src != xnoreg, "sanity");
3959 InstructionMark im(this);
3960 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3961 attributes.set_address_attributes(/* tuple_type */ EVEX_QVM, /* input_size_in_bits */ EVEX_NObit);
3962 attributes.set_is_evex_instruction();
3963 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes);
3964 emit_int8(0x31);
3965 emit_operand(src, dst);
3966 }
3967
3968 void Assembler::vpmovzxwd(XMMRegister dst, XMMRegister src, int vector_len) {
3969 assert(vector_len == AVX_128bit? VM_Version::supports_avx() :
3970 vector_len == AVX_256bit? VM_Version::supports_avx2() :
3971 vector_len == AVX_512bit? VM_Version::supports_evex() : 0, " ");
3972 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3973 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3974 emit_int8(0x33);
3975 emit_int8((unsigned char)(0xC0 | encode));
3976 }
3977
3978 // generic
3979 void Assembler::pop(Register dst) {
3980 int encode = prefix_and_encode(dst->encoding());
3981 emit_int8(0x58 | encode);
3982 }
3983
3984 void Assembler::popcntl(Register dst, Address src) {
3985 assert(VM_Version::supports_popcnt(), "must support");
3986 InstructionMark im(this);
3987 emit_int8((unsigned char)0xF3);
3988 prefix(src, dst);
3989 emit_int8(0x0F);
3990 emit_int8((unsigned char)0xB8);
3991 emit_operand(dst, src);
3992 }
3993
3994 void Assembler::popcntl(Register dst, Register src) {
3995 assert(VM_Version::supports_popcnt(), "must support");
3996 emit_int8((unsigned char)0xF3);
3997 int encode = prefix_and_encode(dst->encoding(), src->encoding());
3998 emit_int8(0x0F);
3999 emit_int8((unsigned char)0xB8);
4000 emit_int8((unsigned char)(0xC0 | encode));
4001 }
4002
4003 void Assembler::vpopcntd(XMMRegister dst, XMMRegister src, int vector_len) {
4004 assert(VM_Version::supports_vpopcntdq(), "must support vpopcntdq feature");
4005 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4006 attributes.set_is_evex_instruction();
4007 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4008 emit_int8(0x55);
4009 emit_int8((unsigned char)(0xC0 | encode));
4010 }
4011
4012 void Assembler::popf() {
4013 emit_int8((unsigned char)0x9D);
4014 }
4015
4016 #ifndef _LP64 // no 32bit push/pop on amd64
4017 void Assembler::popl(Address dst) {
4018 // NOTE: this will adjust stack by 8byte on 64bits
4019 InstructionMark im(this);
4020 prefix(dst);
4021 emit_int8((unsigned char)0x8F);
4022 emit_operand(rax, dst);
4023 }
4024 #endif
4025
4026 void Assembler::prefetch_prefix(Address src) {
4027 prefix(src);
4028 emit_int8(0x0F);
4029 }
4030
4031 void Assembler::prefetchnta(Address src) {
4032 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
4033 InstructionMark im(this);
4034 prefetch_prefix(src);
4035 emit_int8(0x18);
4036 emit_operand(rax, src); // 0, src
4037 }
4038
4039 void Assembler::prefetchr(Address src) {
4040 assert(VM_Version::supports_3dnow_prefetch(), "must support");
4041 InstructionMark im(this);
4042 prefetch_prefix(src);
4043 emit_int8(0x0D);
4044 emit_operand(rax, src); // 0, src
4045 }
4046
4047 void Assembler::prefetcht0(Address src) {
4048 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
4049 InstructionMark im(this);
4050 prefetch_prefix(src);
4051 emit_int8(0x18);
4052 emit_operand(rcx, src); // 1, src
4053 }
4054
4055 void Assembler::prefetcht1(Address src) {
4056 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
4057 InstructionMark im(this);
4058 prefetch_prefix(src);
4059 emit_int8(0x18);
4060 emit_operand(rdx, src); // 2, src
4061 }
4062
4063 void Assembler::prefetcht2(Address src) {
4064 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
4065 InstructionMark im(this);
4066 prefetch_prefix(src);
4067 emit_int8(0x18);
4068 emit_operand(rbx, src); // 3, src
4069 }
4070
4071 void Assembler::prefetchw(Address src) {
4072 assert(VM_Version::supports_3dnow_prefetch(), "must support");
4073 InstructionMark im(this);
4074 prefetch_prefix(src);
4075 emit_int8(0x0D);
4076 emit_operand(rcx, src); // 1, src
4077 }
4078
4079 void Assembler::prefix(Prefix p) {
4080 emit_int8(p);
4081 }
4082
4083 void Assembler::pshufb(XMMRegister dst, XMMRegister src) {
4084 assert(VM_Version::supports_ssse3(), "");
4085 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
4086 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4087 emit_int8(0x00);
4088 emit_int8((unsigned char)(0xC0 | encode));
4089 }
4090
4091 void Assembler::vpshufb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4092 assert(vector_len == AVX_128bit? VM_Version::supports_avx() :
4093 vector_len == AVX_256bit? VM_Version::supports_avx2() :
4094 0, "");
4095 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
4096 int encode = simd_prefix_and_encode(dst, nds, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4097 emit_int8(0x00);
4098 emit_int8((unsigned char)(0xC0 | encode));
4099 }
4100
4101 void Assembler::pshufb(XMMRegister dst, Address src) {
4102 assert(VM_Version::supports_ssse3(), "");
4103 InstructionMark im(this);
4104 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
4105 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
4106 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4107 emit_int8(0x00);
4108 emit_operand(dst, src);
4109 }
4110
4111 void Assembler::pshufd(XMMRegister dst, XMMRegister src, int mode) {
4112 assert(isByte(mode), "invalid value");
4113 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4114 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit;
4115 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4116 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4117 emit_int8(0x70);
4118 emit_int8((unsigned char)(0xC0 | encode));
4119 emit_int8(mode & 0xFF);
4120 }
4121
4122 void Assembler::vpshufd(XMMRegister dst, XMMRegister src, int mode, int vector_len) {
4123 assert(vector_len == AVX_128bit? VM_Version::supports_avx() :
4124 vector_len == AVX_256bit? VM_Version::supports_avx2() :
4125 0, "");
4126 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4127 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4128 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4129 emit_int8(0x70);
4130 emit_int8((unsigned char)(0xC0 | encode));
4131 emit_int8(mode & 0xFF);
4132 }
4133
4134 void Assembler::pshufd(XMMRegister dst, Address src, int mode) {
4135 assert(isByte(mode), "invalid value");
4136 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4137 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
4138 InstructionMark im(this);
4139 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4140 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
4141 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4142 emit_int8(0x70);
4143 emit_operand(dst, src);
4144 emit_int8(mode & 0xFF);
4145 }
4146
4147 void Assembler::pshuflw(XMMRegister dst, XMMRegister src, int mode) {
4148 assert(isByte(mode), "invalid value");
4149 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4150 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
4151 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4152 emit_int8(0x70);
4153 emit_int8((unsigned char)(0xC0 | encode));
4154 emit_int8(mode & 0xFF);
4155 }
4156
4157 void Assembler::pshuflw(XMMRegister dst, Address src, int mode) {
4158 assert(isByte(mode), "invalid value");
4159 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4160 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
4161 InstructionMark im(this);
4162 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
4163 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
4164 simd_prefix(dst, xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4165 emit_int8(0x70);
4166 emit_operand(dst, src);
4167 emit_int8(mode & 0xFF);
4168 }
4169 void Assembler::evshufi64x2(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8, int vector_len) {
4170 assert(VM_Version::supports_evex(), "requires EVEX support");
4171 assert(vector_len == Assembler::AVX_256bit || vector_len == Assembler::AVX_512bit, "");
4172 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
4173 attributes.set_is_evex_instruction();
4174 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4175 emit_int8(0x43);
4176 emit_int8((unsigned char)(0xC0 | encode));
4177 emit_int8(imm8 & 0xFF);
4178 }
4179
4180 void Assembler::psrldq(XMMRegister dst, int shift) {
4181 // Shift left 128 bit value in dst XMMRegister by shift number of bytes.
4182 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4183 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
4184 int encode = simd_prefix_and_encode(xmm3, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4185 emit_int8(0x73);
4186 emit_int8((unsigned char)(0xC0 | encode));
4187 emit_int8(shift);
4188 }
4189
4190 void Assembler::pslldq(XMMRegister dst, int shift) {
4191 // Shift left 128 bit value in dst XMMRegister by shift number of bytes.
4192 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4193 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
4194 // XMM7 is for /7 encoding: 66 0F 73 /7 ib
4195 int encode = simd_prefix_and_encode(xmm7, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4196 emit_int8(0x73);
4197 emit_int8((unsigned char)(0xC0 | encode));
4198 emit_int8(shift);
4199 }
4200
4201 void Assembler::ptest(XMMRegister dst, Address src) {
4202 assert(VM_Version::supports_sse4_1(), "");
4203 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
4204 InstructionMark im(this);
4205 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
4206 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4207 emit_int8(0x17);
4208 emit_operand(dst, src);
4209 }
4210
4211 void Assembler::ptest(XMMRegister dst, XMMRegister src) {
4212 assert(VM_Version::supports_sse4_1(), "");
4213 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
4214 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4215 emit_int8(0x17);
4216 emit_int8((unsigned char)(0xC0 | encode));
4217 }
4218
4219 void Assembler::vptest(XMMRegister dst, Address src) {
4220 assert(VM_Version::supports_avx(), "");
4221 InstructionMark im(this);
4222 InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
4223 assert(dst != xnoreg, "sanity");
4224 // swap src<->dst for encoding
4225 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4226 emit_int8(0x17);
4227 emit_operand(dst, src);
4228 }
4229
4230 void Assembler::vptest(XMMRegister dst, XMMRegister src) {
4231 assert(VM_Version::supports_avx(), "");
4232 InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
4233 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4234 emit_int8(0x17);
4235 emit_int8((unsigned char)(0xC0 | encode));
4236 }
4237
4238 void Assembler::punpcklbw(XMMRegister dst, Address src) {
4239 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4240 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
4241 InstructionMark im(this);
4242 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_vlbw, /* no_mask_reg */ false, /* uses_vl */ true);
4243 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
4244 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4245 emit_int8(0x60);
4246 emit_operand(dst, src);
4247 }
4248
4249 void Assembler::punpcklbw(XMMRegister dst, XMMRegister src) {
4250 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4251 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_vlbw, /* no_mask_reg */ false, /* uses_vl */ true);
4252 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4253 emit_int8(0x60);
4254 emit_int8((unsigned char)(0xC0 | encode));
4255 }
4256
4257 void Assembler::punpckldq(XMMRegister dst, Address src) {
4258 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4259 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
4260 InstructionMark im(this);
4261 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4262 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
4263 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4264 emit_int8(0x62);
4265 emit_operand(dst, src);
4266 }
4267
4268 void Assembler::punpckldq(XMMRegister dst, XMMRegister src) {
4269 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4270 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4271 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4272 emit_int8(0x62);
4273 emit_int8((unsigned char)(0xC0 | encode));
4274 }
4275
4276 void Assembler::punpcklqdq(XMMRegister dst, XMMRegister src) {
4277 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4278 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4279 attributes.set_rex_vex_w_reverted();
4280 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4281 emit_int8(0x6C);
4282 emit_int8((unsigned char)(0xC0 | encode));
4283 }
4284
4285 void Assembler::push(int32_t imm32) {
4286 // in 64bits we push 64bits onto the stack but only
4287 // take a 32bit immediate
4288 emit_int8(0x68);
4289 emit_int32(imm32);
4290 }
4291
4292 void Assembler::push(Register src) {
4293 int encode = prefix_and_encode(src->encoding());
4294
4295 emit_int8(0x50 | encode);
4296 }
4297
4298 void Assembler::pushf() {
4299 emit_int8((unsigned char)0x9C);
4300 }
4301
4302 #ifndef _LP64 // no 32bit push/pop on amd64
4303 void Assembler::pushl(Address src) {
4304 // Note this will push 64bit on 64bit
4305 InstructionMark im(this);
4306 prefix(src);
4307 emit_int8((unsigned char)0xFF);
4308 emit_operand(rsi, src);
4309 }
4310 #endif
4311
4312 void Assembler::rcll(Register dst, int imm8) {
4313 assert(isShiftCount(imm8), "illegal shift count");
4314 int encode = prefix_and_encode(dst->encoding());
4315 if (imm8 == 1) {
4316 emit_int8((unsigned char)0xD1);
4317 emit_int8((unsigned char)(0xD0 | encode));
4318 } else {
4319 emit_int8((unsigned char)0xC1);
4320 emit_int8((unsigned char)0xD0 | encode);
4321 emit_int8(imm8);
4322 }
4323 }
4324
4325 void Assembler::rcpps(XMMRegister dst, XMMRegister src) {
4326 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4327 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
4328 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4329 emit_int8(0x53);
4330 emit_int8((unsigned char)(0xC0 | encode));
4331 }
4332
4333 void Assembler::rcpss(XMMRegister dst, XMMRegister src) {
4334 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4335 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
4336 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4337 emit_int8(0x53);
4338 emit_int8((unsigned char)(0xC0 | encode));
4339 }
4340
4341 void Assembler::rdtsc() {
4342 emit_int8((unsigned char)0x0F);
4343 emit_int8((unsigned char)0x31);
4344 }
4345
4346 // copies data from [esi] to [edi] using rcx pointer sized words
4347 // generic
4348 void Assembler::rep_mov() {
4349 emit_int8((unsigned char)0xF3);
4350 // MOVSQ
4351 LP64_ONLY(prefix(REX_W));
4352 emit_int8((unsigned char)0xA5);
4353 }
4354
4355 // sets rcx bytes with rax, value at [edi]
4356 void Assembler::rep_stosb() {
4357 emit_int8((unsigned char)0xF3); // REP
4358 LP64_ONLY(prefix(REX_W));
4359 emit_int8((unsigned char)0xAA); // STOSB
4360 }
4361
4362 // sets rcx pointer sized words with rax, value at [edi]
4363 // generic
4364 void Assembler::rep_stos() {
4365 emit_int8((unsigned char)0xF3); // REP
4366 LP64_ONLY(prefix(REX_W)); // LP64:STOSQ, LP32:STOSD
4367 emit_int8((unsigned char)0xAB);
4368 }
4369
4370 // scans rcx pointer sized words at [edi] for occurance of rax,
4371 // generic
4372 void Assembler::repne_scan() { // repne_scan
4373 emit_int8((unsigned char)0xF2);
4374 // SCASQ
4375 LP64_ONLY(prefix(REX_W));
4376 emit_int8((unsigned char)0xAF);
4377 }
4378
4379 #ifdef _LP64
4380 // scans rcx 4 byte words at [edi] for occurance of rax,
4381 // generic
4382 void Assembler::repne_scanl() { // repne_scan
4383 emit_int8((unsigned char)0xF2);
4384 // SCASL
4385 emit_int8((unsigned char)0xAF);
4386 }
4387 #endif
4388
4389 void Assembler::ret(int imm16) {
4390 if (imm16 == 0) {
4391 emit_int8((unsigned char)0xC3);
4392 } else {
4393 emit_int8((unsigned char)0xC2);
4394 emit_int16(imm16);
4395 }
4396 }
4397
4398 void Assembler::sahf() {
4399 #ifdef _LP64
4400 // Not supported in 64bit mode
4401 ShouldNotReachHere();
4402 #endif
4403 emit_int8((unsigned char)0x9E);
4404 }
4405
4406 void Assembler::sarl(Register dst, int imm8) {
4407 int encode = prefix_and_encode(dst->encoding());
4408 assert(isShiftCount(imm8), "illegal shift count");
4409 if (imm8 == 1) {
4410 emit_int8((unsigned char)0xD1);
4411 emit_int8((unsigned char)(0xF8 | encode));
4412 } else {
4413 emit_int8((unsigned char)0xC1);
4414 emit_int8((unsigned char)(0xF8 | encode));
4415 emit_int8(imm8);
4416 }
4417 }
4418
4419 void Assembler::sarl(Register dst) {
4420 int encode = prefix_and_encode(dst->encoding());
4421 emit_int8((unsigned char)0xD3);
4422 emit_int8((unsigned char)(0xF8 | encode));
4423 }
4424
4425 void Assembler::sbbl(Address dst, int32_t imm32) {
4426 InstructionMark im(this);
4427 prefix(dst);
4428 emit_arith_operand(0x81, rbx, dst, imm32);
4429 }
4430
4431 void Assembler::sbbl(Register dst, int32_t imm32) {
4432 prefix(dst);
4433 emit_arith(0x81, 0xD8, dst, imm32);
4434 }
4435
4436
4437 void Assembler::sbbl(Register dst, Address src) {
4438 InstructionMark im(this);
4439 prefix(src, dst);
4440 emit_int8(0x1B);
4441 emit_operand(dst, src);
4442 }
4443
4444 void Assembler::sbbl(Register dst, Register src) {
4445 (void) prefix_and_encode(dst->encoding(), src->encoding());
4446 emit_arith(0x1B, 0xC0, dst, src);
4447 }
4448
4449 void Assembler::setb(Condition cc, Register dst) {
4450 assert(0 <= cc && cc < 16, "illegal cc");
4451 int encode = prefix_and_encode(dst->encoding(), true);
4452 emit_int8(0x0F);
4453 emit_int8((unsigned char)0x90 | cc);
4454 emit_int8((unsigned char)(0xC0 | encode));
4455 }
4456
4457 void Assembler::palignr(XMMRegister dst, XMMRegister src, int imm8) {
4458 assert(VM_Version::supports_ssse3(), "");
4459 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ false);
4460 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4461 emit_int8((unsigned char)0x0F);
4462 emit_int8((unsigned char)(0xC0 | encode));
4463 emit_int8(imm8);
4464 }
4465
4466 void Assembler::vpalignr(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8, int vector_len) {
4467 assert(vector_len == AVX_128bit? VM_Version::supports_avx() :
4468 vector_len == AVX_256bit? VM_Version::supports_avx2() :
4469 0, "");
4470 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
4471 int encode = simd_prefix_and_encode(dst, nds, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4472 emit_int8((unsigned char)0x0F);
4473 emit_int8((unsigned char)(0xC0 | encode));
4474 emit_int8(imm8);
4475 }
4476
4477 void Assembler::evalignq(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
4478 assert(VM_Version::supports_evex(), "");
4479 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4480 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4481 emit_int8(0x3);
4482 emit_int8((unsigned char)(0xC0 | encode));
4483 emit_int8(imm8);
4484 }
4485
4486 void Assembler::pblendw(XMMRegister dst, XMMRegister src, int imm8) {
4487 assert(VM_Version::supports_sse4_1(), "");
4488 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
4489 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4490 emit_int8((unsigned char)0x0E);
4491 emit_int8((unsigned char)(0xC0 | encode));
4492 emit_int8(imm8);
4493 }
4494
4495 void Assembler::sha1rnds4(XMMRegister dst, XMMRegister src, int imm8) {
4496 assert(VM_Version::supports_sha(), "");
4497 int encode = rex_prefix_and_encode(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3A, /* rex_w */ false);
4498 emit_int8((unsigned char)0xCC);
4499 emit_int8((unsigned char)(0xC0 | encode));
4500 emit_int8((unsigned char)imm8);
4501 }
4502
4503 void Assembler::sha1nexte(XMMRegister dst, XMMRegister src) {
4504 assert(VM_Version::supports_sha(), "");
4505 int encode = rex_prefix_and_encode(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, /* rex_w */ false);
4506 emit_int8((unsigned char)0xC8);
4507 emit_int8((unsigned char)(0xC0 | encode));
4508 }
4509
4510 void Assembler::sha1msg1(XMMRegister dst, XMMRegister src) {
4511 assert(VM_Version::supports_sha(), "");
4512 int encode = rex_prefix_and_encode(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, /* rex_w */ false);
4513 emit_int8((unsigned char)0xC9);
4514 emit_int8((unsigned char)(0xC0 | encode));
4515 }
4516
4517 void Assembler::sha1msg2(XMMRegister dst, XMMRegister src) {
4518 assert(VM_Version::supports_sha(), "");
4519 int encode = rex_prefix_and_encode(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, /* rex_w */ false);
4520 emit_int8((unsigned char)0xCA);
4521 emit_int8((unsigned char)(0xC0 | encode));
4522 }
4523
4524 // xmm0 is implicit additional source to this instruction.
4525 void Assembler::sha256rnds2(XMMRegister dst, XMMRegister src) {
4526 assert(VM_Version::supports_sha(), "");
4527 int encode = rex_prefix_and_encode(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, /* rex_w */ false);
4528 emit_int8((unsigned char)0xCB);
4529 emit_int8((unsigned char)(0xC0 | encode));
4530 }
4531
4532 void Assembler::sha256msg1(XMMRegister dst, XMMRegister src) {
4533 assert(VM_Version::supports_sha(), "");
4534 int encode = rex_prefix_and_encode(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, /* rex_w */ false);
4535 emit_int8((unsigned char)0xCC);
4536 emit_int8((unsigned char)(0xC0 | encode));
4537 }
4538
4539 void Assembler::sha256msg2(XMMRegister dst, XMMRegister src) {
4540 assert(VM_Version::supports_sha(), "");
4541 int encode = rex_prefix_and_encode(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, /* rex_w */ false);
4542 emit_int8((unsigned char)0xCD);
4543 emit_int8((unsigned char)(0xC0 | encode));
4544 }
4545
4546
4547 void Assembler::shll(Register dst, int imm8) {
4548 assert(isShiftCount(imm8), "illegal shift count");
4549 int encode = prefix_and_encode(dst->encoding());
4550 if (imm8 == 1 ) {
4551 emit_int8((unsigned char)0xD1);
4552 emit_int8((unsigned char)(0xE0 | encode));
4553 } else {
4554 emit_int8((unsigned char)0xC1);
4555 emit_int8((unsigned char)(0xE0 | encode));
4556 emit_int8(imm8);
4557 }
4558 }
4559
4560 void Assembler::shll(Register dst) {
4561 int encode = prefix_and_encode(dst->encoding());
4562 emit_int8((unsigned char)0xD3);
4563 emit_int8((unsigned char)(0xE0 | encode));
4564 }
4565
4566 void Assembler::shrl(Register dst, int imm8) {
4567 assert(isShiftCount(imm8), "illegal shift count");
4568 int encode = prefix_and_encode(dst->encoding());
4569 emit_int8((unsigned char)0xC1);
4570 emit_int8((unsigned char)(0xE8 | encode));
4571 emit_int8(imm8);
4572 }
4573
4574 void Assembler::shrl(Register dst) {
4575 int encode = prefix_and_encode(dst->encoding());
4576 emit_int8((unsigned char)0xD3);
4577 emit_int8((unsigned char)(0xE8 | encode));
4578 }
4579
4580 // copies a single word from [esi] to [edi]
4581 void Assembler::smovl() {
4582 emit_int8((unsigned char)0xA5);
4583 }
4584
4585 void Assembler::sqrtsd(XMMRegister dst, XMMRegister src) {
4586 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4587 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4588 attributes.set_rex_vex_w_reverted();
4589 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4590 emit_int8(0x51);
4591 emit_int8((unsigned char)(0xC0 | encode));
4592 }
4593
4594 void Assembler::sqrtsd(XMMRegister dst, Address src) {
4595 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4596 InstructionMark im(this);
4597 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4598 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
4599 attributes.set_rex_vex_w_reverted();
4600 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4601 emit_int8(0x51);
4602 emit_operand(dst, src);
4603 }
4604
4605 void Assembler::sqrtss(XMMRegister dst, XMMRegister src) {
4606 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4607 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4608 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4609 emit_int8(0x51);
4610 emit_int8((unsigned char)(0xC0 | encode));
4611 }
4612
4613 void Assembler::std() {
4614 emit_int8((unsigned char)0xFD);
4615 }
4616
4617 void Assembler::sqrtss(XMMRegister dst, Address src) {
4618 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4619 InstructionMark im(this);
4620 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4621 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
4622 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4623 emit_int8(0x51);
4624 emit_operand(dst, src);
4625 }
4626
4627 void Assembler::stmxcsr( Address dst) {
4628 if (UseAVX > 0 ) {
4629 assert(VM_Version::supports_avx(), "");
4630 InstructionMark im(this);
4631 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
4632 vex_prefix(dst, 0, 0, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4633 emit_int8((unsigned char)0xAE);
4634 emit_operand(as_Register(3), dst);
4635 } else {
4636 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4637 InstructionMark im(this);
4638 prefix(dst);
4639 emit_int8(0x0F);
4640 emit_int8((unsigned char)0xAE);
4641 emit_operand(as_Register(3), dst);
4642 }
4643 }
4644
4645 void Assembler::subl(Address dst, int32_t imm32) {
4646 InstructionMark im(this);
4647 prefix(dst);
4648 emit_arith_operand(0x81, rbp, dst, imm32);
4649 }
4650
4651 void Assembler::subl(Address dst, Register src) {
4652 InstructionMark im(this);
4653 prefix(dst, src);
4654 emit_int8(0x29);
4655 emit_operand(src, dst);
4656 }
4657
4658 void Assembler::subl(Register dst, int32_t imm32) {
4659 prefix(dst);
4660 emit_arith(0x81, 0xE8, dst, imm32);
4661 }
4662
4663 // Force generation of a 4 byte immediate value even if it fits into 8bit
4664 void Assembler::subl_imm32(Register dst, int32_t imm32) {
4665 prefix(dst);
4666 emit_arith_imm32(0x81, 0xE8, dst, imm32);
4667 }
4668
4669 void Assembler::subl(Register dst, Address src) {
4670 InstructionMark im(this);
4671 prefix(src, dst);
4672 emit_int8(0x2B);
4673 emit_operand(dst, src);
4674 }
4675
4676 void Assembler::subl(Register dst, Register src) {
4677 (void) prefix_and_encode(dst->encoding(), src->encoding());
4678 emit_arith(0x2B, 0xC0, dst, src);
4679 }
4680
4681 void Assembler::subsd(XMMRegister dst, XMMRegister src) {
4682 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4683 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4684 attributes.set_rex_vex_w_reverted();
4685 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4686 emit_int8(0x5C);
4687 emit_int8((unsigned char)(0xC0 | encode));
4688 }
4689
4690 void Assembler::subsd(XMMRegister dst, Address src) {
4691 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4692 InstructionMark im(this);
4693 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4694 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
4695 attributes.set_rex_vex_w_reverted();
4696 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4697 emit_int8(0x5C);
4698 emit_operand(dst, src);
4699 }
4700
4701 void Assembler::subss(XMMRegister dst, XMMRegister src) {
4702 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4703 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true , /* uses_vl */ false);
4704 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4705 emit_int8(0x5C);
4706 emit_int8((unsigned char)(0xC0 | encode));
4707 }
4708
4709 void Assembler::subss(XMMRegister dst, Address src) {
4710 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4711 InstructionMark im(this);
4712 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4713 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
4714 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4715 emit_int8(0x5C);
4716 emit_operand(dst, src);
4717 }
4718
4719 void Assembler::testb(Register dst, int imm8) {
4720 NOT_LP64(assert(dst->has_byte_register(), "must have byte register"));
4721 (void) prefix_and_encode(dst->encoding(), true);
4722 emit_arith_b(0xF6, 0xC0, dst, imm8);
4723 }
4724
4725 void Assembler::testb(Address dst, int imm8) {
4726 InstructionMark im(this);
4727 prefix(dst);
4728 emit_int8((unsigned char)0xF6);
4729 emit_operand(rax, dst, 1);
4730 emit_int8(imm8);
4731 }
4732
4733 void Assembler::testl(Register dst, int32_t imm32) {
4734 // not using emit_arith because test
4735 // doesn't support sign-extension of
4736 // 8bit operands
4737 int encode = dst->encoding();
4738 if (encode == 0) {
4739 emit_int8((unsigned char)0xA9);
4740 } else {
4741 encode = prefix_and_encode(encode);
4742 emit_int8((unsigned char)0xF7);
4743 emit_int8((unsigned char)(0xC0 | encode));
4744 }
4745 emit_int32(imm32);
4746 }
4747
4748 void Assembler::testl(Register dst, Register src) {
4749 (void) prefix_and_encode(dst->encoding(), src->encoding());
4750 emit_arith(0x85, 0xC0, dst, src);
4751 }
4752
4753 void Assembler::testl(Register dst, Address src) {
4754 InstructionMark im(this);
4755 prefix(src, dst);
4756 emit_int8((unsigned char)0x85);
4757 emit_operand(dst, src);
4758 }
4759
4760 void Assembler::tzcntl(Register dst, Register src) {
4761 assert(VM_Version::supports_bmi1(), "tzcnt instruction not supported");
4762 emit_int8((unsigned char)0xF3);
4763 int encode = prefix_and_encode(dst->encoding(), src->encoding());
4764 emit_int8(0x0F);
4765 emit_int8((unsigned char)0xBC);
4766 emit_int8((unsigned char)0xC0 | encode);
4767 }
4768
4769 void Assembler::tzcntq(Register dst, Register src) {
4770 assert(VM_Version::supports_bmi1(), "tzcnt instruction not supported");
4771 emit_int8((unsigned char)0xF3);
4772 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
4773 emit_int8(0x0F);
4774 emit_int8((unsigned char)0xBC);
4775 emit_int8((unsigned char)(0xC0 | encode));
4776 }
4777
4778 void Assembler::ucomisd(XMMRegister dst, Address src) {
4779 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4780 InstructionMark im(this);
4781 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4782 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
4783 attributes.set_rex_vex_w_reverted();
4784 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4785 emit_int8(0x2E);
4786 emit_operand(dst, src);
4787 }
4788
4789 void Assembler::ucomisd(XMMRegister dst, XMMRegister src) {
4790 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4791 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4792 attributes.set_rex_vex_w_reverted();
4793 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4794 emit_int8(0x2E);
4795 emit_int8((unsigned char)(0xC0 | encode));
4796 }
4797
4798 void Assembler::ucomiss(XMMRegister dst, Address src) {
4799 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4800 InstructionMark im(this);
4801 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4802 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
4803 simd_prefix(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4804 emit_int8(0x2E);
4805 emit_operand(dst, src);
4806 }
4807
4808 void Assembler::ucomiss(XMMRegister dst, XMMRegister src) {
4809 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4810 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4811 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4812 emit_int8(0x2E);
4813 emit_int8((unsigned char)(0xC0 | encode));
4814 }
4815
4816 void Assembler::xabort(int8_t imm8) {
4817 emit_int8((unsigned char)0xC6);
4818 emit_int8((unsigned char)0xF8);
4819 emit_int8((unsigned char)(imm8 & 0xFF));
4820 }
4821
4822 void Assembler::xaddb(Address dst, Register src) {
4823 InstructionMark im(this);
4824 prefix(dst, src, true);
4825 emit_int8(0x0F);
4826 emit_int8((unsigned char)0xC0);
4827 emit_operand(src, dst);
4828 }
4829
4830 void Assembler::xaddw(Address dst, Register src) {
4831 InstructionMark im(this);
4832 emit_int8(0x66);
4833 prefix(dst, src);
4834 emit_int8(0x0F);
4835 emit_int8((unsigned char)0xC1);
4836 emit_operand(src, dst);
4837 }
4838
4839 void Assembler::xaddl(Address dst, Register src) {
4840 InstructionMark im(this);
4841 prefix(dst, src);
4842 emit_int8(0x0F);
4843 emit_int8((unsigned char)0xC1);
4844 emit_operand(src, dst);
4845 }
4846
4847 void Assembler::xbegin(Label& abort, relocInfo::relocType rtype) {
4848 InstructionMark im(this);
4849 relocate(rtype);
4850 if (abort.is_bound()) {
4851 address entry = target(abort);
4852 assert(entry != NULL, "abort entry NULL");
4853 intptr_t offset = entry - pc();
4854 emit_int8((unsigned char)0xC7);
4855 emit_int8((unsigned char)0xF8);
4856 emit_int32(offset - 6); // 2 opcode + 4 address
4857 } else {
4858 abort.add_patch_at(code(), locator());
4859 emit_int8((unsigned char)0xC7);
4860 emit_int8((unsigned char)0xF8);
4861 emit_int32(0);
4862 }
4863 }
4864
4865 void Assembler::xchgb(Register dst, Address src) { // xchg
4866 InstructionMark im(this);
4867 prefix(src, dst, true);
4868 emit_int8((unsigned char)0x86);
4869 emit_operand(dst, src);
4870 }
4871
4872 void Assembler::xchgw(Register dst, Address src) { // xchg
4873 InstructionMark im(this);
4874 emit_int8(0x66);
4875 prefix(src, dst);
4876 emit_int8((unsigned char)0x87);
4877 emit_operand(dst, src);
4878 }
4879
4880 void Assembler::xchgl(Register dst, Address src) { // xchg
4881 InstructionMark im(this);
4882 prefix(src, dst);
4883 emit_int8((unsigned char)0x87);
4884 emit_operand(dst, src);
4885 }
4886
4887 void Assembler::xchgl(Register dst, Register src) {
4888 int encode = prefix_and_encode(dst->encoding(), src->encoding());
4889 emit_int8((unsigned char)0x87);
4890 emit_int8((unsigned char)(0xC0 | encode));
4891 }
4892
4893 void Assembler::xend() {
4894 emit_int8((unsigned char)0x0F);
4895 emit_int8((unsigned char)0x01);
4896 emit_int8((unsigned char)0xD5);
4897 }
4898
4899 void Assembler::xgetbv() {
4900 emit_int8(0x0F);
4901 emit_int8(0x01);
4902 emit_int8((unsigned char)0xD0);
4903 }
4904
4905 void Assembler::xorl(Register dst, int32_t imm32) {
4906 prefix(dst);
4907 emit_arith(0x81, 0xF0, dst, imm32);
4908 }
4909
4910 void Assembler::xorl(Register dst, Address src) {
4911 InstructionMark im(this);
4912 prefix(src, dst);
4913 emit_int8(0x33);
4914 emit_operand(dst, src);
4915 }
4916
4917 void Assembler::xorl(Register dst, Register src) {
4918 (void) prefix_and_encode(dst->encoding(), src->encoding());
4919 emit_arith(0x33, 0xC0, dst, src);
4920 }
4921
4922 void Assembler::xorb(Register dst, Address src) {
4923 InstructionMark im(this);
4924 prefix(src, dst);
4925 emit_int8(0x32);
4926 emit_operand(dst, src);
4927 }
4928
4929 // AVX 3-operands scalar float-point arithmetic instructions
4930
4931 void Assembler::vaddsd(XMMRegister dst, XMMRegister nds, Address src) {
4932 assert(VM_Version::supports_avx(), "");
4933 InstructionMark im(this);
4934 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4935 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
4936 attributes.set_rex_vex_w_reverted();
4937 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4938 emit_int8(0x58);
4939 emit_operand(dst, src);
4940 }
4941
4942 void Assembler::vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4943 assert(VM_Version::supports_avx(), "");
4944 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4945 attributes.set_rex_vex_w_reverted();
4946 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4947 emit_int8(0x58);
4948 emit_int8((unsigned char)(0xC0 | encode));
4949 }
4950
4951 void Assembler::vaddss(XMMRegister dst, XMMRegister nds, Address src) {
4952 assert(VM_Version::supports_avx(), "");
4953 InstructionMark im(this);
4954 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4955 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
4956 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4957 emit_int8(0x58);
4958 emit_operand(dst, src);
4959 }
4960
4961 void Assembler::vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4962 assert(VM_Version::supports_avx(), "");
4963 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4964 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4965 emit_int8(0x58);
4966 emit_int8((unsigned char)(0xC0 | encode));
4967 }
4968
4969 void Assembler::vdivsd(XMMRegister dst, XMMRegister nds, Address src) {
4970 assert(VM_Version::supports_avx(), "");
4971 InstructionMark im(this);
4972 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4973 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
4974 attributes.set_rex_vex_w_reverted();
4975 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4976 emit_int8(0x5E);
4977 emit_operand(dst, src);
4978 }
4979
4980 void Assembler::vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4981 assert(VM_Version::supports_avx(), "");
4982 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4983 attributes.set_rex_vex_w_reverted();
4984 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4985 emit_int8(0x5E);
4986 emit_int8((unsigned char)(0xC0 | encode));
4987 }
4988
4989 void Assembler::vdivss(XMMRegister dst, XMMRegister nds, Address src) {
4990 assert(VM_Version::supports_avx(), "");
4991 InstructionMark im(this);
4992 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4993 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
4994 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4995 emit_int8(0x5E);
4996 emit_operand(dst, src);
4997 }
4998
4999 void Assembler::vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
5000 assert(VM_Version::supports_avx(), "");
5001 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
5002 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
5003 emit_int8(0x5E);
5004 emit_int8((unsigned char)(0xC0 | encode));
5005 }
5006
5007 void Assembler::vfmadd231sd(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
5008 assert(VM_Version::supports_fma(), "");
5009 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
5010 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5011 emit_int8((unsigned char)0xB9);
5012 emit_int8((unsigned char)(0xC0 | encode));
5013 }
5014
5015 void Assembler::vfmadd231ss(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
5016 assert(VM_Version::supports_fma(), "");
5017 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
5018 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5019 emit_int8((unsigned char)0xB9);
5020 emit_int8((unsigned char)(0xC0 | encode));
5021 }
5022
5023 void Assembler::vmulsd(XMMRegister dst, XMMRegister nds, Address src) {
5024 assert(VM_Version::supports_avx(), "");
5025 InstructionMark im(this);
5026 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
5027 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
5028 attributes.set_rex_vex_w_reverted();
5029 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
5030 emit_int8(0x59);
5031 emit_operand(dst, src);
5032 }
5033
5034 void Assembler::vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
5035 assert(VM_Version::supports_avx(), "");
5036 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
5037 attributes.set_rex_vex_w_reverted();
5038 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
5039 emit_int8(0x59);
5040 emit_int8((unsigned char)(0xC0 | encode));
5041 }
5042
5043 void Assembler::vmulss(XMMRegister dst, XMMRegister nds, Address src) {
5044 assert(VM_Version::supports_avx(), "");
5045 InstructionMark im(this);
5046 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
5047 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
5048 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
5049 emit_int8(0x59);
5050 emit_operand(dst, src);
5051 }
5052
5053 void Assembler::vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
5054 assert(VM_Version::supports_avx(), "");
5055 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
5056 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
5057 emit_int8(0x59);
5058 emit_int8((unsigned char)(0xC0 | encode));
5059 }
5060
5061 void Assembler::vsubsd(XMMRegister dst, XMMRegister nds, Address src) {
5062 assert(VM_Version::supports_avx(), "");
5063 InstructionMark im(this);
5064 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
5065 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
5066 attributes.set_rex_vex_w_reverted();
5067 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
5068 emit_int8(0x5C);
5069 emit_operand(dst, src);
5070 }
5071
5072 void Assembler::vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
5073 assert(VM_Version::supports_avx(), "");
5074 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
5075 attributes.set_rex_vex_w_reverted();
5076 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
5077 emit_int8(0x5C);
5078 emit_int8((unsigned char)(0xC0 | encode));
5079 }
5080
5081 void Assembler::vsubss(XMMRegister dst, XMMRegister nds, Address src) {
5082 assert(VM_Version::supports_avx(), "");
5083 InstructionMark im(this);
5084 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
5085 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
5086 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
5087 emit_int8(0x5C);
5088 emit_operand(dst, src);
5089 }
5090
5091 void Assembler::vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
5092 assert(VM_Version::supports_avx(), "");
5093 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
5094 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
5095 emit_int8(0x5C);
5096 emit_int8((unsigned char)(0xC0 | encode));
5097 }
5098
5099 //====================VECTOR ARITHMETIC=====================================
5100
5101 // Float-point vector arithmetic
5102
5103 void Assembler::addpd(XMMRegister dst, XMMRegister src) {
5104 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5105 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5106 attributes.set_rex_vex_w_reverted();
5107 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5108 emit_int8(0x58);
5109 emit_int8((unsigned char)(0xC0 | encode));
5110 }
5111
5112 void Assembler::addpd(XMMRegister dst, Address src) {
5113 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5114 InstructionMark im(this);
5115 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5116 attributes.set_rex_vex_w_reverted();
5117 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5118 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5119 emit_int8(0x58);
5120 emit_operand(dst, src);
5121 }
5122
5123
5124 void Assembler::addps(XMMRegister dst, XMMRegister src) {
5125 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5126 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5127 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5128 emit_int8(0x58);
5129 emit_int8((unsigned char)(0xC0 | encode));
5130 }
5131
5132 void Assembler::vaddpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5133 assert(VM_Version::supports_avx(), "");
5134 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5135 attributes.set_rex_vex_w_reverted();
5136 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5137 emit_int8(0x58);
5138 emit_int8((unsigned char)(0xC0 | encode));
5139 }
5140
5141 void Assembler::vaddps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5142 assert(VM_Version::supports_avx(), "");
5143 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5144 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5145 emit_int8(0x58);
5146 emit_int8((unsigned char)(0xC0 | encode));
5147 }
5148
5149 void Assembler::vaddpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5150 assert(VM_Version::supports_avx(), "");
5151 InstructionMark im(this);
5152 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5153 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5154 attributes.set_rex_vex_w_reverted();
5155 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5156 emit_int8(0x58);
5157 emit_operand(dst, src);
5158 }
5159
5160 void Assembler::vaddps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5161 assert(VM_Version::supports_avx(), "");
5162 InstructionMark im(this);
5163 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5164 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5165 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5166 emit_int8(0x58);
5167 emit_operand(dst, src);
5168 }
5169
5170 void Assembler::subpd(XMMRegister dst, XMMRegister src) {
5171 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5172 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5173 attributes.set_rex_vex_w_reverted();
5174 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5175 emit_int8(0x5C);
5176 emit_int8((unsigned char)(0xC0 | encode));
5177 }
5178
5179 void Assembler::subps(XMMRegister dst, XMMRegister src) {
5180 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5181 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5182 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5183 emit_int8(0x5C);
5184 emit_int8((unsigned char)(0xC0 | encode));
5185 }
5186
5187 void Assembler::vsubpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5188 assert(VM_Version::supports_avx(), "");
5189 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5190 attributes.set_rex_vex_w_reverted();
5191 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5192 emit_int8(0x5C);
5193 emit_int8((unsigned char)(0xC0 | encode));
5194 }
5195
5196 void Assembler::vsubps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5197 assert(VM_Version::supports_avx(), "");
5198 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5199 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5200 emit_int8(0x5C);
5201 emit_int8((unsigned char)(0xC0 | encode));
5202 }
5203
5204 void Assembler::vsubpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5205 assert(VM_Version::supports_avx(), "");
5206 InstructionMark im(this);
5207 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5208 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5209 attributes.set_rex_vex_w_reverted();
5210 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5211 emit_int8(0x5C);
5212 emit_operand(dst, src);
5213 }
5214
5215 void Assembler::vsubps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5216 assert(VM_Version::supports_avx(), "");
5217 InstructionMark im(this);
5218 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5219 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5220 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5221 emit_int8(0x5C);
5222 emit_operand(dst, src);
5223 }
5224
5225 void Assembler::mulpd(XMMRegister dst, XMMRegister src) {
5226 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5227 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5228 attributes.set_rex_vex_w_reverted();
5229 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5230 emit_int8(0x59);
5231 emit_int8((unsigned char)(0xC0 | encode));
5232 }
5233
5234 void Assembler::mulpd(XMMRegister dst, Address src) {
5235 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5236 InstructionMark im(this);
5237 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5238 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5239 attributes.set_rex_vex_w_reverted();
5240 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5241 emit_int8(0x59);
5242 emit_operand(dst, src);
5243 }
5244
5245 void Assembler::mulps(XMMRegister dst, XMMRegister src) {
5246 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5247 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5248 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5249 emit_int8(0x59);
5250 emit_int8((unsigned char)(0xC0 | encode));
5251 }
5252
5253 void Assembler::vmulpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5254 assert(VM_Version::supports_avx(), "");
5255 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5256 attributes.set_rex_vex_w_reverted();
5257 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5258 emit_int8(0x59);
5259 emit_int8((unsigned char)(0xC0 | encode));
5260 }
5261
5262 void Assembler::vmulps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5263 assert(VM_Version::supports_avx(), "");
5264 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5265 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5266 emit_int8(0x59);
5267 emit_int8((unsigned char)(0xC0 | encode));
5268 }
5269
5270 void Assembler::vmulpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5271 assert(VM_Version::supports_avx(), "");
5272 InstructionMark im(this);
5273 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5274 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5275 attributes.set_rex_vex_w_reverted();
5276 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5277 emit_int8(0x59);
5278 emit_operand(dst, src);
5279 }
5280
5281 void Assembler::vmulps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5282 assert(VM_Version::supports_avx(), "");
5283 InstructionMark im(this);
5284 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5285 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5286 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5287 emit_int8(0x59);
5288 emit_operand(dst, src);
5289 }
5290
5291 void Assembler::vfmadd231pd(XMMRegister dst, XMMRegister src1, XMMRegister src2, int vector_len) {
5292 assert(VM_Version::supports_fma(), "");
5293 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5294 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5295 emit_int8((unsigned char)0xB8);
5296 emit_int8((unsigned char)(0xC0 | encode));
5297 }
5298
5299 void Assembler::vfmadd231ps(XMMRegister dst, XMMRegister src1, XMMRegister src2, int vector_len) {
5300 assert(VM_Version::supports_fma(), "");
5301 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5302 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5303 emit_int8((unsigned char)0xB8);
5304 emit_int8((unsigned char)(0xC0 | encode));
5305 }
5306
5307 void Assembler::vfmadd231pd(XMMRegister dst, XMMRegister src1, Address src2, int vector_len) {
5308 assert(VM_Version::supports_fma(), "");
5309 InstructionMark im(this);
5310 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5311 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5312 vex_prefix(src2, src1->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5313 emit_int8((unsigned char)0xB8);
5314 emit_operand(dst, src2);
5315 }
5316
5317 void Assembler::vfmadd231ps(XMMRegister dst, XMMRegister src1, Address src2, int vector_len) {
5318 assert(VM_Version::supports_fma(), "");
5319 InstructionMark im(this);
5320 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5321 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5322 vex_prefix(src2, src1->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5323 emit_int8((unsigned char)0xB8);
5324 emit_operand(dst, src2);
5325 }
5326
5327 void Assembler::divpd(XMMRegister dst, XMMRegister src) {
5328 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5329 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5330 attributes.set_rex_vex_w_reverted();
5331 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5332 emit_int8(0x5E);
5333 emit_int8((unsigned char)(0xC0 | encode));
5334 }
5335
5336 void Assembler::divps(XMMRegister dst, XMMRegister src) {
5337 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5338 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5339 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5340 emit_int8(0x5E);
5341 emit_int8((unsigned char)(0xC0 | encode));
5342 }
5343
5344 void Assembler::vdivpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5345 assert(VM_Version::supports_avx(), "");
5346 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5347 attributes.set_rex_vex_w_reverted();
5348 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5349 emit_int8(0x5E);
5350 emit_int8((unsigned char)(0xC0 | encode));
5351 }
5352
5353 void Assembler::vdivps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5354 assert(VM_Version::supports_avx(), "");
5355 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5356 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5357 emit_int8(0x5E);
5358 emit_int8((unsigned char)(0xC0 | encode));
5359 }
5360
5361 void Assembler::vdivpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5362 assert(VM_Version::supports_avx(), "");
5363 InstructionMark im(this);
5364 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5365 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5366 attributes.set_rex_vex_w_reverted();
5367 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5368 emit_int8(0x5E);
5369 emit_operand(dst, src);
5370 }
5371
5372 void Assembler::vdivps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5373 assert(VM_Version::supports_avx(), "");
5374 InstructionMark im(this);
5375 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5376 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5377 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5378 emit_int8(0x5E);
5379 emit_operand(dst, src);
5380 }
5381
5382 void Assembler::vsqrtpd(XMMRegister dst, XMMRegister src, int vector_len) {
5383 assert(VM_Version::supports_avx(), "");
5384 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5385 attributes.set_rex_vex_w_reverted();
5386 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5387 emit_int8(0x51);
5388 emit_int8((unsigned char)(0xC0 | encode));
5389 }
5390
5391 void Assembler::vsqrtpd(XMMRegister dst, Address src, int vector_len) {
5392 assert(VM_Version::supports_avx(), "");
5393 InstructionMark im(this);
5394 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5395 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5396 attributes.set_rex_vex_w_reverted();
5397 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5398 emit_int8(0x51);
5399 emit_operand(dst, src);
5400 }
5401
5402 void Assembler::vsqrtps(XMMRegister dst, XMMRegister src, int vector_len) {
5403 assert(VM_Version::supports_avx(), "");
5404 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5405 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5406 emit_int8(0x51);
5407 emit_int8((unsigned char)(0xC0 | encode));
5408 }
5409
5410 void Assembler::vsqrtps(XMMRegister dst, Address src, int vector_len) {
5411 assert(VM_Version::supports_avx(), "");
5412 InstructionMark im(this);
5413 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5414 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5415 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5416 emit_int8(0x51);
5417 emit_operand(dst, src);
5418 }
5419
5420 void Assembler::andpd(XMMRegister dst, XMMRegister src) {
5421 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5422 InstructionAttr attributes(AVX_128bit, /* rex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
5423 attributes.set_rex_vex_w_reverted();
5424 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5425 emit_int8(0x54);
5426 emit_int8((unsigned char)(0xC0 | encode));
5427 }
5428
5429 void Assembler::andps(XMMRegister dst, XMMRegister src) {
5430 NOT_LP64(assert(VM_Version::supports_sse(), ""));
5431 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
5432 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5433 emit_int8(0x54);
5434 emit_int8((unsigned char)(0xC0 | encode));
5435 }
5436
5437 void Assembler::andps(XMMRegister dst, Address src) {
5438 NOT_LP64(assert(VM_Version::supports_sse(), ""));
5439 InstructionMark im(this);
5440 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
5441 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5442 simd_prefix(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5443 emit_int8(0x54);
5444 emit_operand(dst, src);
5445 }
5446
5447 void Assembler::andpd(XMMRegister dst, Address src) {
5448 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5449 InstructionMark im(this);
5450 InstructionAttr attributes(AVX_128bit, /* rex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
5451 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5452 attributes.set_rex_vex_w_reverted();
5453 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5454 emit_int8(0x54);
5455 emit_operand(dst, src);
5456 }
5457
5458 void Assembler::vandpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5459 assert(VM_Version::supports_avx(), "");
5460 InstructionAttr attributes(vector_len, /* vex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
5461 attributes.set_rex_vex_w_reverted();
5462 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5463 emit_int8(0x54);
5464 emit_int8((unsigned char)(0xC0 | encode));
5465 }
5466
5467 void Assembler::vandps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5468 assert(VM_Version::supports_avx(), "");
5469 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
5470 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5471 emit_int8(0x54);
5472 emit_int8((unsigned char)(0xC0 | encode));
5473 }
5474
5475 void Assembler::vandpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5476 assert(VM_Version::supports_avx(), "");
5477 InstructionMark im(this);
5478 InstructionAttr attributes(vector_len, /* vex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
5479 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5480 attributes.set_rex_vex_w_reverted();
5481 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5482 emit_int8(0x54);
5483 emit_operand(dst, src);
5484 }
5485
5486 void Assembler::vandps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5487 assert(VM_Version::supports_avx(), "");
5488 InstructionMark im(this);
5489 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
5490 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5491 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5492 emit_int8(0x54);
5493 emit_operand(dst, src);
5494 }
5495
5496 void Assembler::unpckhpd(XMMRegister dst, XMMRegister src) {
5497 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5498 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5499 attributes.set_rex_vex_w_reverted();
5500 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5501 emit_int8(0x15);
5502 emit_int8((unsigned char)(0xC0 | encode));
5503 }
5504
5505 void Assembler::unpcklpd(XMMRegister dst, XMMRegister src) {
5506 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5507 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5508 attributes.set_rex_vex_w_reverted();
5509 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5510 emit_int8(0x14);
5511 emit_int8((unsigned char)(0xC0 | encode));
5512 }
5513
5514 void Assembler::xorpd(XMMRegister dst, XMMRegister src) {
5515 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5516 InstructionAttr attributes(AVX_128bit, /* rex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
5517 attributes.set_rex_vex_w_reverted();
5518 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5519 emit_int8(0x57);
5520 emit_int8((unsigned char)(0xC0 | encode));
5521 }
5522
5523 void Assembler::xorps(XMMRegister dst, XMMRegister src) {
5524 NOT_LP64(assert(VM_Version::supports_sse(), ""));
5525 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
5526 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5527 emit_int8(0x57);
5528 emit_int8((unsigned char)(0xC0 | encode));
5529 }
5530
5531 void Assembler::xorpd(XMMRegister dst, Address src) {
5532 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5533 InstructionMark im(this);
5534 InstructionAttr attributes(AVX_128bit, /* rex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
5535 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5536 attributes.set_rex_vex_w_reverted();
5537 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5538 emit_int8(0x57);
5539 emit_operand(dst, src);
5540 }
5541
5542 void Assembler::xorps(XMMRegister dst, Address src) {
5543 NOT_LP64(assert(VM_Version::supports_sse(), ""));
5544 InstructionMark im(this);
5545 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
5546 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5547 simd_prefix(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5548 emit_int8(0x57);
5549 emit_operand(dst, src);
5550 }
5551
5552 void Assembler::vxorpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5553 assert(VM_Version::supports_avx(), "");
5554 InstructionAttr attributes(vector_len, /* vex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
5555 attributes.set_rex_vex_w_reverted();
5556 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5557 emit_int8(0x57);
5558 emit_int8((unsigned char)(0xC0 | encode));
5559 }
5560
5561 void Assembler::vxorps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5562 assert(VM_Version::supports_avx(), "");
5563 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
5564 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5565 emit_int8(0x57);
5566 emit_int8((unsigned char)(0xC0 | encode));
5567 }
5568
5569 void Assembler::vxorpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5570 assert(VM_Version::supports_avx(), "");
5571 InstructionMark im(this);
5572 InstructionAttr attributes(vector_len, /* vex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
5573 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5574 attributes.set_rex_vex_w_reverted();
5575 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5576 emit_int8(0x57);
5577 emit_operand(dst, src);
5578 }
5579
5580 void Assembler::vxorps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5581 assert(VM_Version::supports_avx(), "");
5582 InstructionMark im(this);
5583 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
5584 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5585 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5586 emit_int8(0x57);
5587 emit_operand(dst, src);
5588 }
5589
5590 // Integer vector arithmetic
5591 void Assembler::vphaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5592 assert(VM_Version::supports_avx() && (vector_len == 0) ||
5593 VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
5594 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
5595 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5596 emit_int8(0x01);
5597 emit_int8((unsigned char)(0xC0 | encode));
5598 }
5599
5600 void Assembler::vphaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5601 assert(VM_Version::supports_avx() && (vector_len == 0) ||
5602 VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
5603 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
5604 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5605 emit_int8(0x02);
5606 emit_int8((unsigned char)(0xC0 | encode));
5607 }
5608
5609 void Assembler::paddb(XMMRegister dst, XMMRegister src) {
5610 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5611 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5612 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5613 emit_int8((unsigned char)0xFC);
5614 emit_int8((unsigned char)(0xC0 | encode));
5615 }
5616
5617 void Assembler::paddw(XMMRegister dst, XMMRegister src) {
5618 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5619 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5620 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5621 emit_int8((unsigned char)0xFD);
5622 emit_int8((unsigned char)(0xC0 | encode));
5623 }
5624
5625 void Assembler::paddd(XMMRegister dst, XMMRegister src) {
5626 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5627 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5628 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5629 emit_int8((unsigned char)0xFE);
5630 emit_int8((unsigned char)(0xC0 | encode));
5631 }
5632
5633 void Assembler::paddd(XMMRegister dst, Address src) {
5634 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5635 InstructionMark im(this);
5636 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5637 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5638 emit_int8((unsigned char)0xFE);
5639 emit_operand(dst, src);
5640 }
5641
5642 void Assembler::paddq(XMMRegister dst, XMMRegister src) {
5643 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5644 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5645 attributes.set_rex_vex_w_reverted();
5646 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5647 emit_int8((unsigned char)0xD4);
5648 emit_int8((unsigned char)(0xC0 | encode));
5649 }
5650
5651 void Assembler::phaddw(XMMRegister dst, XMMRegister src) {
5652 assert(VM_Version::supports_sse3(), "");
5653 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
5654 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5655 emit_int8(0x01);
5656 emit_int8((unsigned char)(0xC0 | encode));
5657 }
5658
5659 void Assembler::phaddd(XMMRegister dst, XMMRegister src) {
5660 assert(VM_Version::supports_sse3(), "");
5661 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
5662 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5663 emit_int8(0x02);
5664 emit_int8((unsigned char)(0xC0 | encode));
5665 }
5666
5667 void Assembler::vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5668 assert(UseAVX > 0, "requires some form of AVX");
5669 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5670 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5671 emit_int8((unsigned char)0xFC);
5672 emit_int8((unsigned char)(0xC0 | encode));
5673 }
5674
5675 void Assembler::vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5676 assert(UseAVX > 0, "requires some form of AVX");
5677 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5678 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5679 emit_int8((unsigned char)0xFD);
5680 emit_int8((unsigned char)(0xC0 | encode));
5681 }
5682
5683 void Assembler::vpaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5684 assert(UseAVX > 0, "requires some form of AVX");
5685 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5686 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5687 emit_int8((unsigned char)0xFE);
5688 emit_int8((unsigned char)(0xC0 | encode));
5689 }
5690
5691 void Assembler::vpaddq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5692 assert(UseAVX > 0, "requires some form of AVX");
5693 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5694 attributes.set_rex_vex_w_reverted();
5695 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5696 emit_int8((unsigned char)0xD4);
5697 emit_int8((unsigned char)(0xC0 | encode));
5698 }
5699
5700 void Assembler::vpaddb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5701 assert(UseAVX > 0, "requires some form of AVX");
5702 InstructionMark im(this);
5703 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5704 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
5705 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5706 emit_int8((unsigned char)0xFC);
5707 emit_operand(dst, src);
5708 }
5709
5710 void Assembler::vpaddw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5711 assert(UseAVX > 0, "requires some form of AVX");
5712 InstructionMark im(this);
5713 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5714 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
5715 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5716 emit_int8((unsigned char)0xFD);
5717 emit_operand(dst, src);
5718 }
5719
5720 void Assembler::vpaddd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5721 assert(UseAVX > 0, "requires some form of AVX");
5722 InstructionMark im(this);
5723 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5724 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5725 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5726 emit_int8((unsigned char)0xFE);
5727 emit_operand(dst, src);
5728 }
5729
5730 void Assembler::vpaddq(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5731 assert(UseAVX > 0, "requires some form of AVX");
5732 InstructionMark im(this);
5733 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5734 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5735 attributes.set_rex_vex_w_reverted();
5736 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5737 emit_int8((unsigned char)0xD4);
5738 emit_operand(dst, src);
5739 }
5740
5741 void Assembler::psubb(XMMRegister dst, XMMRegister src) {
5742 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5743 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5744 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5745 emit_int8((unsigned char)0xF8);
5746 emit_int8((unsigned char)(0xC0 | encode));
5747 }
5748
5749 void Assembler::psubw(XMMRegister dst, XMMRegister src) {
5750 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5751 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5752 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5753 emit_int8((unsigned char)0xF9);
5754 emit_int8((unsigned char)(0xC0 | encode));
5755 }
5756
5757 void Assembler::psubd(XMMRegister dst, XMMRegister src) {
5758 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5759 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5760 emit_int8((unsigned char)0xFA);
5761 emit_int8((unsigned char)(0xC0 | encode));
5762 }
5763
5764 void Assembler::psubq(XMMRegister dst, XMMRegister src) {
5765 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5766 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5767 attributes.set_rex_vex_w_reverted();
5768 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5769 emit_int8((unsigned char)0xFB);
5770 emit_int8((unsigned char)(0xC0 | encode));
5771 }
5772
5773 void Assembler::vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5774 assert(UseAVX > 0, "requires some form of AVX");
5775 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5776 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5777 emit_int8((unsigned char)0xF8);
5778 emit_int8((unsigned char)(0xC0 | encode));
5779 }
5780
5781 void Assembler::vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5782 assert(UseAVX > 0, "requires some form of AVX");
5783 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5784 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5785 emit_int8((unsigned char)0xF9);
5786 emit_int8((unsigned char)(0xC0 | encode));
5787 }
5788
5789 void Assembler::vpsubd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5790 assert(UseAVX > 0, "requires some form of AVX");
5791 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5792 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5793 emit_int8((unsigned char)0xFA);
5794 emit_int8((unsigned char)(0xC0 | encode));
5795 }
5796
5797 void Assembler::vpsubq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5798 assert(UseAVX > 0, "requires some form of AVX");
5799 InstructionAttr attributes(vector_len, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5800 attributes.set_rex_vex_w_reverted();
5801 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5802 emit_int8((unsigned char)0xFB);
5803 emit_int8((unsigned char)(0xC0 | encode));
5804 }
5805
5806 void Assembler::vpsubb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5807 assert(UseAVX > 0, "requires some form of AVX");
5808 InstructionMark im(this);
5809 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5810 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
5811 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5812 emit_int8((unsigned char)0xF8);
5813 emit_operand(dst, src);
5814 }
5815
5816 void Assembler::vpsubw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5817 assert(UseAVX > 0, "requires some form of AVX");
5818 InstructionMark im(this);
5819 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5820 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
5821 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5822 emit_int8((unsigned char)0xF9);
5823 emit_operand(dst, src);
5824 }
5825
5826 void Assembler::vpsubd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5827 assert(UseAVX > 0, "requires some form of AVX");
5828 InstructionMark im(this);
5829 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5830 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5831 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5832 emit_int8((unsigned char)0xFA);
5833 emit_operand(dst, src);
5834 }
5835
5836 void Assembler::vpsubq(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5837 assert(UseAVX > 0, "requires some form of AVX");
5838 InstructionMark im(this);
5839 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5840 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5841 attributes.set_rex_vex_w_reverted();
5842 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5843 emit_int8((unsigned char)0xFB);
5844 emit_operand(dst, src);
5845 }
5846
5847 void Assembler::pmullw(XMMRegister dst, XMMRegister src) {
5848 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5849 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5850 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5851 emit_int8((unsigned char)0xD5);
5852 emit_int8((unsigned char)(0xC0 | encode));
5853 }
5854
5855 void Assembler::pmulld(XMMRegister dst, XMMRegister src) {
5856 assert(VM_Version::supports_sse4_1(), "");
5857 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5858 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5859 emit_int8(0x40);
5860 emit_int8((unsigned char)(0xC0 | encode));
5861 }
5862
5863 void Assembler::vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5864 assert(UseAVX > 0, "requires some form of AVX");
5865 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5866 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5867 emit_int8((unsigned char)0xD5);
5868 emit_int8((unsigned char)(0xC0 | encode));
5869 }
5870
5871 void Assembler::vpmulld(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5872 assert(UseAVX > 0, "requires some form of AVX");
5873 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5874 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5875 emit_int8(0x40);
5876 emit_int8((unsigned char)(0xC0 | encode));
5877 }
5878
5879 void Assembler::vpmullq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5880 assert(UseAVX > 2, "requires some form of EVEX");
5881 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
5882 attributes.set_is_evex_instruction();
5883 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5884 emit_int8(0x40);
5885 emit_int8((unsigned char)(0xC0 | encode));
5886 }
5887
5888 void Assembler::vpmullw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5889 assert(UseAVX > 0, "requires some form of AVX");
5890 InstructionMark im(this);
5891 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5892 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
5893 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5894 emit_int8((unsigned char)0xD5);
5895 emit_operand(dst, src);
5896 }
5897
5898 void Assembler::vpmulld(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5899 assert(UseAVX > 0, "requires some form of AVX");
5900 InstructionMark im(this);
5901 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5902 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5903 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5904 emit_int8(0x40);
5905 emit_operand(dst, src);
5906 }
5907
5908 void Assembler::vpmullq(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5909 assert(UseAVX > 2, "requires some form of EVEX");
5910 InstructionMark im(this);
5911 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
5912 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5913 attributes.set_is_evex_instruction();
5914 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5915 emit_int8(0x40);
5916 emit_operand(dst, src);
5917 }
5918
5919 // Shift packed integers left by specified number of bits.
5920 void Assembler::psllw(XMMRegister dst, int shift) {
5921 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5922 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5923 // XMM6 is for /6 encoding: 66 0F 71 /6 ib
5924 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5925 emit_int8(0x71);
5926 emit_int8((unsigned char)(0xC0 | encode));
5927 emit_int8(shift & 0xFF);
5928 }
5929
5930 void Assembler::pslld(XMMRegister dst, int shift) {
5931 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5932 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5933 // XMM6 is for /6 encoding: 66 0F 72 /6 ib
5934 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5935 emit_int8(0x72);
5936 emit_int8((unsigned char)(0xC0 | encode));
5937 emit_int8(shift & 0xFF);
5938 }
5939
5940 void Assembler::psllq(XMMRegister dst, int shift) {
5941 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5942 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5943 // XMM6 is for /6 encoding: 66 0F 73 /6 ib
5944 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5945 emit_int8(0x73);
5946 emit_int8((unsigned char)(0xC0 | encode));
5947 emit_int8(shift & 0xFF);
5948 }
5949
5950 void Assembler::psllw(XMMRegister dst, XMMRegister shift) {
5951 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5952 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5953 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5954 emit_int8((unsigned char)0xF1);
5955 emit_int8((unsigned char)(0xC0 | encode));
5956 }
5957
5958 void Assembler::pslld(XMMRegister dst, XMMRegister shift) {
5959 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5960 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5961 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5962 emit_int8((unsigned char)0xF2);
5963 emit_int8((unsigned char)(0xC0 | encode));
5964 }
5965
5966 void Assembler::psllq(XMMRegister dst, XMMRegister shift) {
5967 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5968 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5969 attributes.set_rex_vex_w_reverted();
5970 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5971 emit_int8((unsigned char)0xF3);
5972 emit_int8((unsigned char)(0xC0 | encode));
5973 }
5974
5975 void Assembler::vpsllw(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
5976 assert(UseAVX > 0, "requires some form of AVX");
5977 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5978 // XMM6 is for /6 encoding: 66 0F 71 /6 ib
5979 int encode = vex_prefix_and_encode(xmm6->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5980 emit_int8(0x71);
5981 emit_int8((unsigned char)(0xC0 | encode));
5982 emit_int8(shift & 0xFF);
5983 }
5984
5985 void Assembler::vpslld(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
5986 assert(UseAVX > 0, "requires some form of AVX");
5987 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5988 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5989 // XMM6 is for /6 encoding: 66 0F 72 /6 ib
5990 int encode = vex_prefix_and_encode(xmm6->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5991 emit_int8(0x72);
5992 emit_int8((unsigned char)(0xC0 | encode));
5993 emit_int8(shift & 0xFF);
5994 }
5995
5996 void Assembler::vpsllq(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
5997 assert(UseAVX > 0, "requires some form of AVX");
5998 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5999 attributes.set_rex_vex_w_reverted();
6000 // XMM6 is for /6 encoding: 66 0F 73 /6 ib
6001 int encode = vex_prefix_and_encode(xmm6->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6002 emit_int8(0x73);
6003 emit_int8((unsigned char)(0xC0 | encode));
6004 emit_int8(shift & 0xFF);
6005 }
6006
6007 void Assembler::vpsllw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
6008 assert(UseAVX > 0, "requires some form of AVX");
6009 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6010 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6011 emit_int8((unsigned char)0xF1);
6012 emit_int8((unsigned char)(0xC0 | encode));
6013 }
6014
6015 void Assembler::vpslld(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
6016 assert(UseAVX > 0, "requires some form of AVX");
6017 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6018 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6019 emit_int8((unsigned char)0xF2);
6020 emit_int8((unsigned char)(0xC0 | encode));
6021 }
6022
6023 void Assembler::vpsllq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
6024 assert(UseAVX > 0, "requires some form of AVX");
6025 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6026 attributes.set_rex_vex_w_reverted();
6027 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6028 emit_int8((unsigned char)0xF3);
6029 emit_int8((unsigned char)(0xC0 | encode));
6030 }
6031
6032 // Shift packed integers logically right by specified number of bits.
6033 void Assembler::psrlw(XMMRegister dst, int shift) {
6034 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6035 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6036 // XMM2 is for /2 encoding: 66 0F 71 /2 ib
6037 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6038 emit_int8(0x71);
6039 emit_int8((unsigned char)(0xC0 | encode));
6040 emit_int8(shift & 0xFF);
6041 }
6042
6043 void Assembler::psrld(XMMRegister dst, int shift) {
6044 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6045 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6046 // XMM2 is for /2 encoding: 66 0F 72 /2 ib
6047 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6048 emit_int8(0x72);
6049 emit_int8((unsigned char)(0xC0 | encode));
6050 emit_int8(shift & 0xFF);
6051 }
6052
6053 void Assembler::psrlq(XMMRegister dst, int shift) {
6054 // Do not confuse it with psrldq SSE2 instruction which
6055 // shifts 128 bit value in xmm register by number of bytes.
6056 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6057 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6058 attributes.set_rex_vex_w_reverted();
6059 // XMM2 is for /2 encoding: 66 0F 73 /2 ib
6060 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6061 emit_int8(0x73);
6062 emit_int8((unsigned char)(0xC0 | encode));
6063 emit_int8(shift & 0xFF);
6064 }
6065
6066 void Assembler::psrlw(XMMRegister dst, XMMRegister shift) {
6067 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6068 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6069 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6070 emit_int8((unsigned char)0xD1);
6071 emit_int8((unsigned char)(0xC0 | encode));
6072 }
6073
6074 void Assembler::psrld(XMMRegister dst, XMMRegister shift) {
6075 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6076 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6077 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6078 emit_int8((unsigned char)0xD2);
6079 emit_int8((unsigned char)(0xC0 | encode));
6080 }
6081
6082 void Assembler::psrlq(XMMRegister dst, XMMRegister shift) {
6083 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6084 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6085 attributes.set_rex_vex_w_reverted();
6086 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6087 emit_int8((unsigned char)0xD3);
6088 emit_int8((unsigned char)(0xC0 | encode));
6089 }
6090
6091 void Assembler::vpsrlw(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
6092 assert(UseAVX > 0, "requires some form of AVX");
6093 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6094 // XMM2 is for /2 encoding: 66 0F 71 /2 ib
6095 int encode = vex_prefix_and_encode(xmm2->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6096 emit_int8(0x71);
6097 emit_int8((unsigned char)(0xC0 | encode));
6098 emit_int8(shift & 0xFF);
6099 }
6100
6101 void Assembler::vpsrld(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
6102 assert(UseAVX > 0, "requires some form of AVX");
6103 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6104 // XMM2 is for /2 encoding: 66 0F 72 /2 ib
6105 int encode = vex_prefix_and_encode(xmm2->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6106 emit_int8(0x72);
6107 emit_int8((unsigned char)(0xC0 | encode));
6108 emit_int8(shift & 0xFF);
6109 }
6110
6111 void Assembler::vpsrlq(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
6112 assert(UseAVX > 0, "requires some form of AVX");
6113 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6114 attributes.set_rex_vex_w_reverted();
6115 // XMM2 is for /2 encoding: 66 0F 73 /2 ib
6116 int encode = vex_prefix_and_encode(xmm2->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6117 emit_int8(0x73);
6118 emit_int8((unsigned char)(0xC0 | encode));
6119 emit_int8(shift & 0xFF);
6120 }
6121
6122 void Assembler::vpsrlw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
6123 assert(UseAVX > 0, "requires some form of AVX");
6124 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6125 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6126 emit_int8((unsigned char)0xD1);
6127 emit_int8((unsigned char)(0xC0 | encode));
6128 }
6129
6130 void Assembler::vpsrld(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
6131 assert(UseAVX > 0, "requires some form of AVX");
6132 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6133 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6134 emit_int8((unsigned char)0xD2);
6135 emit_int8((unsigned char)(0xC0 | encode));
6136 }
6137
6138 void Assembler::vpsrlq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
6139 assert(UseAVX > 0, "requires some form of AVX");
6140 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6141 attributes.set_rex_vex_w_reverted();
6142 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6143 emit_int8((unsigned char)0xD3);
6144 emit_int8((unsigned char)(0xC0 | encode));
6145 }
6146
6147 void Assembler::evpsrlvw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
6148 assert(VM_Version::supports_avx512bw(), "");
6149 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6150 attributes.set_is_evex_instruction();
6151 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6152 emit_int8(0x10);
6153 emit_int8((unsigned char)(0xC0 | encode));
6154 }
6155
6156 void Assembler::evpsllvw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
6157 assert(VM_Version::supports_avx512bw(), "");
6158 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6159 attributes.set_is_evex_instruction();
6160 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6161 emit_int8(0x12);
6162 emit_int8((unsigned char)(0xC0 | encode));
6163 }
6164
6165 // Shift packed integers arithmetically right by specified number of bits.
6166 void Assembler::psraw(XMMRegister dst, int shift) {
6167 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6168 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6169 // XMM4 is for /4 encoding: 66 0F 71 /4 ib
6170 int encode = simd_prefix_and_encode(xmm4, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6171 emit_int8(0x71);
6172 emit_int8((unsigned char)(0xC0 | encode));
6173 emit_int8(shift & 0xFF);
6174 }
6175
6176 void Assembler::psrad(XMMRegister dst, int shift) {
6177 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6178 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6179 // XMM4 is for /4 encoding: 66 0F 72 /4 ib
6180 int encode = simd_prefix_and_encode(xmm4, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6181 emit_int8(0x72);
6182 emit_int8((unsigned char)(0xC0 | encode));
6183 emit_int8(shift & 0xFF);
6184 }
6185
6186 void Assembler::psraw(XMMRegister dst, XMMRegister shift) {
6187 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6188 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6189 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6190 emit_int8((unsigned char)0xE1);
6191 emit_int8((unsigned char)(0xC0 | encode));
6192 }
6193
6194 void Assembler::psrad(XMMRegister dst, XMMRegister shift) {
6195 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6196 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6197 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6198 emit_int8((unsigned char)0xE2);
6199 emit_int8((unsigned char)(0xC0 | encode));
6200 }
6201
6202 void Assembler::vpsraw(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
6203 assert(UseAVX > 0, "requires some form of AVX");
6204 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6205 // XMM4 is for /4 encoding: 66 0F 71 /4 ib
6206 int encode = vex_prefix_and_encode(xmm4->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6207 emit_int8(0x71);
6208 emit_int8((unsigned char)(0xC0 | encode));
6209 emit_int8(shift & 0xFF);
6210 }
6211
6212 void Assembler::vpsrad(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
6213 assert(UseAVX > 0, "requires some form of AVX");
6214 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6215 // XMM4 is for /4 encoding: 66 0F 71 /4 ib
6216 int encode = vex_prefix_and_encode(xmm4->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6217 emit_int8(0x72);
6218 emit_int8((unsigned char)(0xC0 | encode));
6219 emit_int8(shift & 0xFF);
6220 }
6221
6222 void Assembler::vpsraw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
6223 assert(UseAVX > 0, "requires some form of AVX");
6224 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6225 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6226 emit_int8((unsigned char)0xE1);
6227 emit_int8((unsigned char)(0xC0 | encode));
6228 }
6229
6230 void Assembler::vpsrad(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
6231 assert(UseAVX > 0, "requires some form of AVX");
6232 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6233 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6234 emit_int8((unsigned char)0xE2);
6235 emit_int8((unsigned char)(0xC0 | encode));
6236 }
6237
6238
6239 // logical operations packed integers
6240 void Assembler::pand(XMMRegister dst, XMMRegister src) {
6241 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6242 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6243 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6244 emit_int8((unsigned char)0xDB);
6245 emit_int8((unsigned char)(0xC0 | encode));
6246 }
6247
6248 void Assembler::vpand(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
6249 assert(UseAVX > 0, "requires some form of AVX");
6250 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6251 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6252 emit_int8((unsigned char)0xDB);
6253 emit_int8((unsigned char)(0xC0 | encode));
6254 }
6255
6256 void Assembler::vpand(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
6257 assert(UseAVX > 0, "requires some form of AVX");
6258 InstructionMark im(this);
6259 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6260 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
6261 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6262 emit_int8((unsigned char)0xDB);
6263 emit_operand(dst, src);
6264 }
6265
6266 void Assembler::vpandq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
6267 assert(VM_Version::supports_evex(), "");
6268 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6269 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6270 emit_int8((unsigned char)0xDB);
6271 emit_int8((unsigned char)(0xC0 | encode));
6272 }
6273
6274
6275 void Assembler::pandn(XMMRegister dst, XMMRegister src) {
6276 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6277 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6278 attributes.set_rex_vex_w_reverted();
6279 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6280 emit_int8((unsigned char)0xDF);
6281 emit_int8((unsigned char)(0xC0 | encode));
6282 }
6283
6284 void Assembler::por(XMMRegister dst, XMMRegister src) {
6285 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6286 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6287 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6288 emit_int8((unsigned char)0xEB);
6289 emit_int8((unsigned char)(0xC0 | encode));
6290 }
6291
6292 void Assembler::vpor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
6293 assert(UseAVX > 0, "requires some form of AVX");
6294 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6295 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6296 emit_int8((unsigned char)0xEB);
6297 emit_int8((unsigned char)(0xC0 | encode));
6298 }
6299
6300 void Assembler::vpor(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
6301 assert(UseAVX > 0, "requires some form of AVX");
6302 InstructionMark im(this);
6303 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6304 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
6305 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6306 emit_int8((unsigned char)0xEB);
6307 emit_operand(dst, src);
6308 }
6309
6310 void Assembler::vporq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
6311 assert(VM_Version::supports_evex(), "");
6312 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6313 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6314 emit_int8((unsigned char)0xEB);
6315 emit_int8((unsigned char)(0xC0 | encode));
6316 }
6317
6318
6319 void Assembler::pxor(XMMRegister dst, XMMRegister src) {
6320 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6321 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6322 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6323 emit_int8((unsigned char)0xEF);
6324 emit_int8((unsigned char)(0xC0 | encode));
6325 }
6326
6327 void Assembler::vpxor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
6328 assert(UseAVX > 0, "requires some form of AVX");
6329 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6330 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6331 emit_int8((unsigned char)0xEF);
6332 emit_int8((unsigned char)(0xC0 | encode));
6333 }
6334
6335 void Assembler::vpxor(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
6336 assert(UseAVX > 0, "requires some form of AVX");
6337 InstructionMark im(this);
6338 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6339 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
6340 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6341 emit_int8((unsigned char)0xEF);
6342 emit_operand(dst, src);
6343 }
6344
6345 void Assembler::evpxorq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
6346 assert(VM_Version::supports_evex(), "requires EVEX support");
6347 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6348 attributes.set_is_evex_instruction();
6349 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6350 emit_int8((unsigned char)0xEF);
6351 emit_int8((unsigned char)(0xC0 | encode));
6352 }
6353
6354 void Assembler::evpxorq(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
6355 assert(VM_Version::supports_evex(), "requires EVEX support");
6356 assert(dst != xnoreg, "sanity");
6357 InstructionMark im(this);
6358 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6359 attributes.set_is_evex_instruction();
6360 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
6361 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6362 emit_int8((unsigned char)0xEF);
6363 emit_operand(dst, src);
6364 }
6365
6366
6367 // vinserti forms
6368
6369 void Assembler::vinserti128(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
6370 assert(VM_Version::supports_avx2(), "");
6371 assert(imm8 <= 0x01, "imm8: %u", imm8);
6372 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_256bit;
6373 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6374 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6375 emit_int8(0x38);
6376 emit_int8((unsigned char)(0xC0 | encode));
6377 // 0x00 - insert into lower 128 bits
6378 // 0x01 - insert into upper 128 bits
6379 emit_int8(imm8 & 0x01);
6380 }
6381
6382 void Assembler::vinserti128(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) {
6383 assert(VM_Version::supports_avx2(), "");
6384 assert(dst != xnoreg, "sanity");
6385 assert(imm8 <= 0x01, "imm8: %u", imm8);
6386 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_256bit;
6387 InstructionMark im(this);
6388 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6389 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
6390 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6391 emit_int8(0x38);
6392 emit_operand(dst, src);
6393 // 0x00 - insert into lower 128 bits
6394 // 0x01 - insert into upper 128 bits
6395 emit_int8(imm8 & 0x01);
6396 }
6397
6398 void Assembler::vinserti32x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
6399 assert(VM_Version::supports_evex(), "");
6400 assert(imm8 <= 0x03, "imm8: %u", imm8);
6401 InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6402 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6403 emit_int8(0x38);
6404 emit_int8((unsigned char)(0xC0 | encode));
6405 // 0x00 - insert into q0 128 bits (0..127)
6406 // 0x01 - insert into q1 128 bits (128..255)
6407 // 0x02 - insert into q2 128 bits (256..383)
6408 // 0x03 - insert into q3 128 bits (384..511)
6409 emit_int8(imm8 & 0x03);
6410 }
6411
6412 void Assembler::vinserti32x4(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) {
6413 assert(VM_Version::supports_avx(), "");
6414 assert(dst != xnoreg, "sanity");
6415 assert(imm8 <= 0x03, "imm8: %u", imm8);
6416 int vector_len = VM_Version::supports_evex() ? AVX_512bit : AVX_256bit;
6417 InstructionMark im(this);
6418 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6419 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
6420 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6421 emit_int8(0x18);
6422 emit_operand(dst, src);
6423 // 0x00 - insert into q0 128 bits (0..127)
6424 // 0x01 - insert into q1 128 bits (128..255)
6425 // 0x02 - insert into q2 128 bits (256..383)
6426 // 0x03 - insert into q3 128 bits (384..511)
6427 emit_int8(imm8 & 0x03);
6428 }
6429
6430 void Assembler::vinserti64x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
6431 assert(VM_Version::supports_evex(), "");
6432 assert(imm8 <= 0x01, "imm8: %u", imm8);
6433 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6434 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6435 emit_int8(0x38);
6436 emit_int8((unsigned char)(0xC0 | encode));
6437 // 0x00 - insert into lower 256 bits
6438 // 0x01 - insert into upper 256 bits
6439 emit_int8(imm8 & 0x01);
6440 }
6441
6442
6443 // vinsertf forms
6444
6445 void Assembler::vinsertf128(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
6446 assert(VM_Version::supports_avx(), "");
6447 assert(imm8 <= 0x01, "imm8: %u", imm8);
6448 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_256bit;
6449 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6450 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6451 emit_int8(0x18);
6452 emit_int8((unsigned char)(0xC0 | encode));
6453 // 0x00 - insert into lower 128 bits
6454 // 0x01 - insert into upper 128 bits
6455 emit_int8(imm8 & 0x01);
6456 }
6457
6458 void Assembler::vinsertf128(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) {
6459 assert(VM_Version::supports_avx(), "");
6460 assert(dst != xnoreg, "sanity");
6461 assert(imm8 <= 0x01, "imm8: %u", imm8);
6462 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_256bit;
6463 InstructionMark im(this);
6464 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6465 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
6466 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6467 emit_int8(0x18);
6468 emit_operand(dst, src);
6469 // 0x00 - insert into lower 128 bits
6470 // 0x01 - insert into upper 128 bits
6471 emit_int8(imm8 & 0x01);
6472 }
6473
6474 void Assembler::vinsertf32x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
6475 assert(VM_Version::supports_evex(), "");
6476 assert(imm8 <= 0x03, "imm8: %u", imm8);
6477 InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6478 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6479 emit_int8(0x18);
6480 emit_int8((unsigned char)(0xC0 | encode));
6481 // 0x00 - insert into q0 128 bits (0..127)
6482 // 0x01 - insert into q1 128 bits (128..255)
6483 // 0x02 - insert into q2 128 bits (256..383)
6484 // 0x03 - insert into q3 128 bits (384..511)
6485 emit_int8(imm8 & 0x03);
6486 }
6487
6488 void Assembler::vinsertf32x4(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) {
6489 assert(VM_Version::supports_avx(), "");
6490 assert(dst != xnoreg, "sanity");
6491 assert(imm8 <= 0x03, "imm8: %u", imm8);
6492 int vector_len = VM_Version::supports_evex() ? AVX_512bit : AVX_256bit;
6493 InstructionMark im(this);
6494 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6495 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
6496 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6497 emit_int8(0x18);
6498 emit_operand(dst, src);
6499 // 0x00 - insert into q0 128 bits (0..127)
6500 // 0x01 - insert into q1 128 bits (128..255)
6501 // 0x02 - insert into q2 128 bits (256..383)
6502 // 0x03 - insert into q3 128 bits (384..511)
6503 emit_int8(imm8 & 0x03);
6504 }
6505
6506 void Assembler::vinsertf64x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
6507 assert(VM_Version::supports_evex(), "");
6508 assert(imm8 <= 0x01, "imm8: %u", imm8);
6509 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6510 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6511 emit_int8(0x1A);
6512 emit_int8((unsigned char)(0xC0 | encode));
6513 // 0x00 - insert into lower 256 bits
6514 // 0x01 - insert into upper 256 bits
6515 emit_int8(imm8 & 0x01);
6516 }
6517
6518 void Assembler::vinsertf64x4(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) {
6519 assert(VM_Version::supports_evex(), "");
6520 assert(dst != xnoreg, "sanity");
6521 assert(imm8 <= 0x01, "imm8: %u", imm8);
6522 InstructionMark im(this);
6523 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6524 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_64bit);
6525 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6526 emit_int8(0x1A);
6527 emit_operand(dst, src);
6528 // 0x00 - insert into lower 256 bits
6529 // 0x01 - insert into upper 256 bits
6530 emit_int8(imm8 & 0x01);
6531 }
6532
6533
6534 // vextracti forms
6535
6536 void Assembler::vextracti128(XMMRegister dst, XMMRegister src, uint8_t imm8) {
6537 assert(VM_Version::supports_avx(), "");
6538 assert(imm8 <= 0x01, "imm8: %u", imm8);
6539 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_256bit;
6540 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6541 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6542 emit_int8(0x39);
6543 emit_int8((unsigned char)(0xC0 | encode));
6544 // 0x00 - extract from lower 128 bits
6545 // 0x01 - extract from upper 128 bits
6546 emit_int8(imm8 & 0x01);
6547 }
6548
6549 void Assembler::vextracti128(Address dst, XMMRegister src, uint8_t imm8) {
6550 assert(VM_Version::supports_avx2(), "");
6551 assert(src != xnoreg, "sanity");
6552 assert(imm8 <= 0x01, "imm8: %u", imm8);
6553 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_256bit;
6554 InstructionMark im(this);
6555 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6556 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
6557 attributes.reset_is_clear_context();
6558 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6559 emit_int8(0x39);
6560 emit_operand(src, dst);
6561 // 0x00 - extract from lower 128 bits
6562 // 0x01 - extract from upper 128 bits
6563 emit_int8(imm8 & 0x01);
6564 }
6565
6566 void Assembler::vextracti32x4(XMMRegister dst, XMMRegister src, uint8_t imm8) {
6567 assert(VM_Version::supports_avx(), "");
6568 assert(imm8 <= 0x03, "imm8: %u", imm8);
6569 int vector_len = VM_Version::supports_evex() ? AVX_512bit : AVX_256bit;
6570 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6571 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6572 emit_int8(0x39);
6573 emit_int8((unsigned char)(0xC0 | encode));
6574 // 0x00 - extract from bits 127:0
6575 // 0x01 - extract from bits 255:128
6576 // 0x02 - extract from bits 383:256
6577 // 0x03 - extract from bits 511:384
6578 emit_int8(imm8 & 0x03);
6579 }
6580
6581 void Assembler::vextracti32x4(Address dst, XMMRegister src, uint8_t imm8) {
6582 assert(VM_Version::supports_evex(), "");
6583 assert(src != xnoreg, "sanity");
6584 assert(imm8 <= 0x03, "imm8: %u", imm8);
6585 InstructionMark im(this);
6586 InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6587 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
6588 attributes.reset_is_clear_context();
6589 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6590 emit_int8(0x39);
6591 emit_operand(src, dst);
6592 // 0x00 - extract from bits 127:0
6593 // 0x01 - extract from bits 255:128
6594 // 0x02 - extract from bits 383:256
6595 // 0x03 - extract from bits 511:384
6596 emit_int8(imm8 & 0x03);
6597 }
6598
6599 void Assembler::vextracti64x2(XMMRegister dst, XMMRegister src, uint8_t imm8) {
6600 assert(VM_Version::supports_avx512dq(), "");
6601 assert(imm8 <= 0x03, "imm8: %u", imm8);
6602 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6603 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6604 emit_int8(0x39);
6605 emit_int8((unsigned char)(0xC0 | encode));
6606 // 0x00 - extract from bits 127:0
6607 // 0x01 - extract from bits 255:128
6608 // 0x02 - extract from bits 383:256
6609 // 0x03 - extract from bits 511:384
6610 emit_int8(imm8 & 0x03);
6611 }
6612
6613 void Assembler::vextracti64x4(XMMRegister dst, XMMRegister src, uint8_t imm8) {
6614 assert(VM_Version::supports_evex(), "");
6615 assert(imm8 <= 0x01, "imm8: %u", imm8);
6616 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6617 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6618 emit_int8(0x3B);
6619 emit_int8((unsigned char)(0xC0 | encode));
6620 // 0x00 - extract from lower 256 bits
6621 // 0x01 - extract from upper 256 bits
6622 emit_int8(imm8 & 0x01);
6623 }
6624
6625
6626 // vextractf forms
6627
6628 void Assembler::vextractf128(XMMRegister dst, XMMRegister src, uint8_t imm8) {
6629 assert(VM_Version::supports_avx(), "");
6630 assert(imm8 <= 0x01, "imm8: %u", imm8);
6631 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_256bit;
6632 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6633 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6634 emit_int8(0x19);
6635 emit_int8((unsigned char)(0xC0 | encode));
6636 // 0x00 - extract from lower 128 bits
6637 // 0x01 - extract from upper 128 bits
6638 emit_int8(imm8 & 0x01);
6639 }
6640
6641 void Assembler::vextractf128(Address dst, XMMRegister src, uint8_t imm8) {
6642 assert(VM_Version::supports_avx(), "");
6643 assert(src != xnoreg, "sanity");
6644 assert(imm8 <= 0x01, "imm8: %u", imm8);
6645 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_256bit;
6646 InstructionMark im(this);
6647 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6648 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
6649 attributes.reset_is_clear_context();
6650 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6651 emit_int8(0x19);
6652 emit_operand(src, dst);
6653 // 0x00 - extract from lower 128 bits
6654 // 0x01 - extract from upper 128 bits
6655 emit_int8(imm8 & 0x01);
6656 }
6657
6658 void Assembler::vextractf32x4(XMMRegister dst, XMMRegister src, uint8_t imm8) {
6659 assert(VM_Version::supports_avx(), "");
6660 assert(imm8 <= 0x03, "imm8: %u", imm8);
6661 int vector_len = VM_Version::supports_evex() ? AVX_512bit : AVX_256bit;
6662 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6663 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6664 emit_int8(0x19);
6665 emit_int8((unsigned char)(0xC0 | encode));
6666 // 0x00 - extract from bits 127:0
6667 // 0x01 - extract from bits 255:128
6668 // 0x02 - extract from bits 383:256
6669 // 0x03 - extract from bits 511:384
6670 emit_int8(imm8 & 0x03);
6671 }
6672
6673 void Assembler::vextractf32x4(Address dst, XMMRegister src, uint8_t imm8) {
6674 assert(VM_Version::supports_evex(), "");
6675 assert(src != xnoreg, "sanity");
6676 assert(imm8 <= 0x03, "imm8: %u", imm8);
6677 InstructionMark im(this);
6678 InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6679 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
6680 attributes.reset_is_clear_context();
6681 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6682 emit_int8(0x19);
6683 emit_operand(src, dst);
6684 // 0x00 - extract from bits 127:0
6685 // 0x01 - extract from bits 255:128
6686 // 0x02 - extract from bits 383:256
6687 // 0x03 - extract from bits 511:384
6688 emit_int8(imm8 & 0x03);
6689 }
6690
6691 void Assembler::vextractf64x2(XMMRegister dst, XMMRegister src, uint8_t imm8) {
6692 assert(VM_Version::supports_avx512dq(), "");
6693 assert(imm8 <= 0x03, "imm8: %u", imm8);
6694 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6695 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6696 emit_int8(0x19);
6697 emit_int8((unsigned char)(0xC0 | encode));
6698 // 0x00 - extract from bits 127:0
6699 // 0x01 - extract from bits 255:128
6700 // 0x02 - extract from bits 383:256
6701 // 0x03 - extract from bits 511:384
6702 emit_int8(imm8 & 0x03);
6703 }
6704
6705 void Assembler::vextractf64x4(XMMRegister dst, XMMRegister src, uint8_t imm8) {
6706 assert(VM_Version::supports_evex(), "");
6707 assert(imm8 <= 0x01, "imm8: %u", imm8);
6708 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6709 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6710 emit_int8(0x1B);
6711 emit_int8((unsigned char)(0xC0 | encode));
6712 // 0x00 - extract from lower 256 bits
6713 // 0x01 - extract from upper 256 bits
6714 emit_int8(imm8 & 0x01);
6715 }
6716
6717 void Assembler::vextractf64x4(Address dst, XMMRegister src, uint8_t imm8) {
6718 assert(VM_Version::supports_evex(), "");
6719 assert(src != xnoreg, "sanity");
6720 assert(imm8 <= 0x01, "imm8: %u", imm8);
6721 InstructionMark im(this);
6722 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6723 attributes.set_address_attributes(/* tuple_type */ EVEX_T4,/* input_size_in_bits */ EVEX_64bit);
6724 attributes.reset_is_clear_context();
6725 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6726 emit_int8(0x1B);
6727 emit_operand(src, dst);
6728 // 0x00 - extract from lower 256 bits
6729 // 0x01 - extract from upper 256 bits
6730 emit_int8(imm8 & 0x01);
6731 }
6732
6733
6734 // legacy word/dword replicate
6735 void Assembler::vpbroadcastw(XMMRegister dst, XMMRegister src) {
6736 assert(VM_Version::supports_avx2(), "");
6737 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6738 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6739 emit_int8(0x79);
6740 emit_int8((unsigned char)(0xC0 | encode));
6741 }
6742
6743 void Assembler::vpbroadcastd(XMMRegister dst, XMMRegister src) {
6744 assert(VM_Version::supports_avx2(), "");
6745 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6746 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6747 emit_int8(0x58);
6748 emit_int8((unsigned char)(0xC0 | encode));
6749 }
6750
6751
6752 // xmm/mem sourced byte/word/dword/qword replicate
6753
6754 // duplicate 1-byte integer data from src into programmed locations in dest : requires AVX512BW and AVX512VL
6755 void Assembler::evpbroadcastb(XMMRegister dst, XMMRegister src, int vector_len) {
6756 assert(VM_Version::supports_evex(), "");
6757 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6758 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6759 emit_int8(0x78);
6760 emit_int8((unsigned char)(0xC0 | encode));
6761 }
6762
6763 void Assembler::evpbroadcastb(XMMRegister dst, Address src, int vector_len) {
6764 assert(VM_Version::supports_evex(), "");
6765 assert(dst != xnoreg, "sanity");
6766 InstructionMark im(this);
6767 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6768 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_8bit);
6769 // swap src<->dst for encoding
6770 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6771 emit_int8(0x78);
6772 emit_operand(dst, src);
6773 }
6774
6775 // duplicate 2-byte integer data from src into programmed locations in dest : requires AVX512BW and AVX512VL
6776 void Assembler::evpbroadcastw(XMMRegister dst, XMMRegister src, int vector_len) {
6777 assert(VM_Version::supports_evex(), "");
6778 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6779 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6780 emit_int8(0x79);
6781 emit_int8((unsigned char)(0xC0 | encode));
6782 }
6783
6784 void Assembler::evpbroadcastw(XMMRegister dst, Address src, int vector_len) {
6785 assert(VM_Version::supports_evex(), "");
6786 assert(dst != xnoreg, "sanity");
6787 InstructionMark im(this);
6788 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6789 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_16bit);
6790 // swap src<->dst for encoding
6791 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6792 emit_int8(0x79);
6793 emit_operand(dst, src);
6794 }
6795
6796 // duplicate 4-byte integer data from src into programmed locations in dest : requires AVX512VL
6797 void Assembler::evpbroadcastd(XMMRegister dst, XMMRegister src, int vector_len) {
6798 assert(VM_Version::supports_evex(), "");
6799 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6800 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6801 emit_int8(0x58);
6802 emit_int8((unsigned char)(0xC0 | encode));
6803 }
6804
6805 void Assembler::evpbroadcastd(XMMRegister dst, Address src, int vector_len) {
6806 assert(VM_Version::supports_evex(), "");
6807 assert(dst != xnoreg, "sanity");
6808 InstructionMark im(this);
6809 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6810 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
6811 // swap src<->dst for encoding
6812 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6813 emit_int8(0x58);
6814 emit_operand(dst, src);
6815 }
6816
6817 // duplicate 8-byte integer data from src into programmed locations in dest : requires AVX512VL
6818 void Assembler::evpbroadcastq(XMMRegister dst, XMMRegister src, int vector_len) {
6819 assert(VM_Version::supports_evex(), "");
6820 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6821 attributes.set_rex_vex_w_reverted();
6822 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6823 emit_int8(0x59);
6824 emit_int8((unsigned char)(0xC0 | encode));
6825 }
6826
6827 void Assembler::evpbroadcastq(XMMRegister dst, Address src, int vector_len) {
6828 assert(VM_Version::supports_evex(), "");
6829 assert(dst != xnoreg, "sanity");
6830 InstructionMark im(this);
6831 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6832 attributes.set_rex_vex_w_reverted();
6833 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
6834 // swap src<->dst for encoding
6835 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6836 emit_int8(0x59);
6837 emit_operand(dst, src);
6838 }
6839 void Assembler::evbroadcasti64x2(XMMRegister dst, XMMRegister src, int vector_len) {
6840 assert(vector_len != Assembler::AVX_128bit, "");
6841 assert(VM_Version::supports_avx512dq(), "");
6842 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6843 attributes.set_rex_vex_w_reverted();
6844 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6845 emit_int8(0x5A);
6846 emit_int8((unsigned char)(0xC0 | encode));
6847 }
6848
6849 void Assembler::evbroadcasti64x2(XMMRegister dst, Address src, int vector_len) {
6850 assert(vector_len != Assembler::AVX_128bit, "");
6851 assert(VM_Version::supports_avx512dq(), "");
6852 assert(dst != xnoreg, "sanity");
6853 InstructionMark im(this);
6854 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6855 attributes.set_rex_vex_w_reverted();
6856 attributes.set_address_attributes(/* tuple_type */ EVEX_T2, /* input_size_in_bits */ EVEX_64bit);
6857 // swap src<->dst for encoding
6858 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6859 emit_int8(0x5A);
6860 emit_operand(dst, src);
6861 }
6862
6863 // scalar single/double precision replicate
6864
6865 // duplicate single precision data from src into programmed locations in dest : requires AVX512VL
6866 void Assembler::evpbroadcastss(XMMRegister dst, XMMRegister src, int vector_len) {
6867 assert(VM_Version::supports_evex(), "");
6868 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6869 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6870 emit_int8(0x18);
6871 emit_int8((unsigned char)(0xC0 | encode));
6872 }
6873
6874 void Assembler::evpbroadcastss(XMMRegister dst, Address src, int vector_len) {
6875 assert(VM_Version::supports_evex(), "");
6876 assert(dst != xnoreg, "sanity");
6877 InstructionMark im(this);
6878 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6879 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
6880 // swap src<->dst for encoding
6881 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6882 emit_int8(0x18);
6883 emit_operand(dst, src);
6884 }
6885
6886 // duplicate double precision data from src into programmed locations in dest : requires AVX512VL
6887 void Assembler::evpbroadcastsd(XMMRegister dst, XMMRegister src, int vector_len) {
6888 assert(VM_Version::supports_evex(), "");
6889 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6890 attributes.set_rex_vex_w_reverted();
6891 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6892 emit_int8(0x19);
6893 emit_int8((unsigned char)(0xC0 | encode));
6894 }
6895
6896 void Assembler::evpbroadcastsd(XMMRegister dst, Address src, int vector_len) {
6897 assert(VM_Version::supports_evex(), "");
6898 assert(dst != xnoreg, "sanity");
6899 InstructionMark im(this);
6900 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6901 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
6902 attributes.set_rex_vex_w_reverted();
6903 // swap src<->dst for encoding
6904 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6905 emit_int8(0x19);
6906 emit_operand(dst, src);
6907 }
6908
6909
6910 // gpr source broadcast forms
6911
6912 // duplicate 1-byte integer data from src into programmed locations in dest : requires AVX512BW and AVX512VL
6913 void Assembler::evpbroadcastb(XMMRegister dst, Register src, int vector_len) {
6914 assert(VM_Version::supports_evex(), "");
6915 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6916 attributes.set_is_evex_instruction();
6917 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6918 emit_int8(0x7A);
6919 emit_int8((unsigned char)(0xC0 | encode));
6920 }
6921
6922 // duplicate 2-byte integer data from src into programmed locations in dest : requires AVX512BW and AVX512VL
6923 void Assembler::evpbroadcastw(XMMRegister dst, Register src, int vector_len) {
6924 assert(VM_Version::supports_evex(), "");
6925 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6926 attributes.set_is_evex_instruction();
6927 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6928 emit_int8(0x7B);
6929 emit_int8((unsigned char)(0xC0 | encode));
6930 }
6931
6932 // duplicate 4-byte integer data from src into programmed locations in dest : requires AVX512VL
6933 void Assembler::evpbroadcastd(XMMRegister dst, Register src, int vector_len) {
6934 assert(VM_Version::supports_evex(), "");
6935 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6936 attributes.set_is_evex_instruction();
6937 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6938 emit_int8(0x7C);
6939 emit_int8((unsigned char)(0xC0 | encode));
6940 }
6941
6942 // duplicate 8-byte integer data from src into programmed locations in dest : requires AVX512VL
6943 void Assembler::evpbroadcastq(XMMRegister dst, Register src, int vector_len) {
6944 assert(VM_Version::supports_evex(), "");
6945 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6946 attributes.set_is_evex_instruction();
6947 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6948 emit_int8(0x7C);
6949 emit_int8((unsigned char)(0xC0 | encode));
6950 }
6951
6952 void Assembler::evpgatherdd(XMMRegister dst, KRegister mask, Address src, int vector_len) {
6953 assert(VM_Version::supports_evex(), "");
6954 assert(dst != xnoreg, "sanity");
6955 InstructionMark im(this);
6956 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6957 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
6958 attributes.reset_is_clear_context();
6959 attributes.set_embedded_opmask_register_specifier(mask);
6960 attributes.set_is_evex_instruction();
6961 // swap src<->dst for encoding
6962 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6963 emit_int8((unsigned char)0x90);
6964 emit_operand(dst, src);
6965 }
6966
6967 // Carry-Less Multiplication Quadword
6968 void Assembler::pclmulqdq(XMMRegister dst, XMMRegister src, int mask) {
6969 assert(VM_Version::supports_clmul(), "");
6970 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
6971 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6972 emit_int8(0x44);
6973 emit_int8((unsigned char)(0xC0 | encode));
6974 emit_int8((unsigned char)mask);
6975 }
6976
6977 // Carry-Less Multiplication Quadword
6978 void Assembler::vpclmulqdq(XMMRegister dst, XMMRegister nds, XMMRegister src, int mask) {
6979 assert(VM_Version::supports_avx() && VM_Version::supports_clmul(), "");
6980 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
6981 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6982 emit_int8(0x44);
6983 emit_int8((unsigned char)(0xC0 | encode));
6984 emit_int8((unsigned char)mask);
6985 }
6986
6987 void Assembler::evpclmulqdq(XMMRegister dst, XMMRegister nds, XMMRegister src, int mask, int vector_len) {
6988 assert(VM_Version::supports_vpclmulqdq(), "Requires vector carryless multiplication support");
6989 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6990 attributes.set_is_evex_instruction();
6991 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6992 emit_int8(0x44);
6993 emit_int8((unsigned char)(0xC0 | encode));
6994 emit_int8((unsigned char)mask);
6995 }
6996
6997 void Assembler::vzeroupper() {
6998 if (VM_Version::supports_vzeroupper()) {
6999 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
7000 (void)vex_prefix_and_encode(0, 0, 0, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
7001 emit_int8(0x77);
7002 }
7003 }
7004
7005 #ifndef _LP64
7006 // 32bit only pieces of the assembler
7007
7008 void Assembler::cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec) {
7009 // NO PREFIX AS NEVER 64BIT
7010 InstructionMark im(this);
7011 emit_int8((unsigned char)0x81);
7012 emit_int8((unsigned char)(0xF8 | src1->encoding()));
7013 emit_data(imm32, rspec, 0);
7014 }
7015
7016 void Assembler::cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec) {
7017 // NO PREFIX AS NEVER 64BIT (not even 32bit versions of 64bit regs
7018 InstructionMark im(this);
7019 emit_int8((unsigned char)0x81);
7020 emit_operand(rdi, src1);
7021 emit_data(imm32, rspec, 0);
7022 }
7023
7024 // The 64-bit (32bit platform) cmpxchg compares the value at adr with the contents of rdx:rax,
7025 // and stores rcx:rbx into adr if so; otherwise, the value at adr is loaded
7026 // into rdx:rax. The ZF is set if the compared values were equal, and cleared otherwise.
7027 void Assembler::cmpxchg8(Address adr) {
7028 InstructionMark im(this);
7029 emit_int8(0x0F);
7030 emit_int8((unsigned char)0xC7);
7031 emit_operand(rcx, adr);
7032 }
7033
7034 void Assembler::decl(Register dst) {
7035 // Don't use it directly. Use MacroAssembler::decrementl() instead.
7036 emit_int8(0x48 | dst->encoding());
7037 }
7038
7039 #endif // _LP64
7040
7041 // 64bit typically doesn't use the x87 but needs to for the trig funcs
7042
7043 void Assembler::fabs() {
7044 emit_int8((unsigned char)0xD9);
7045 emit_int8((unsigned char)0xE1);
7046 }
7047
7048 void Assembler::fadd(int i) {
7049 emit_farith(0xD8, 0xC0, i);
7050 }
7051
7052 void Assembler::fadd_d(Address src) {
7053 InstructionMark im(this);
7054 emit_int8((unsigned char)0xDC);
7055 emit_operand32(rax, src);
7056 }
7057
7058 void Assembler::fadd_s(Address src) {
7059 InstructionMark im(this);
7060 emit_int8((unsigned char)0xD8);
7061 emit_operand32(rax, src);
7062 }
7063
7064 void Assembler::fadda(int i) {
7065 emit_farith(0xDC, 0xC0, i);
7066 }
7067
7068 void Assembler::faddp(int i) {
7069 emit_farith(0xDE, 0xC0, i);
7070 }
7071
7072 void Assembler::fchs() {
7073 emit_int8((unsigned char)0xD9);
7074 emit_int8((unsigned char)0xE0);
7075 }
7076
7077 void Assembler::fcom(int i) {
7078 emit_farith(0xD8, 0xD0, i);
7079 }
7080
7081 void Assembler::fcomp(int i) {
7082 emit_farith(0xD8, 0xD8, i);
7083 }
7084
7085 void Assembler::fcomp_d(Address src) {
7086 InstructionMark im(this);
7087 emit_int8((unsigned char)0xDC);
7088 emit_operand32(rbx, src);
7089 }
7090
7091 void Assembler::fcomp_s(Address src) {
7092 InstructionMark im(this);
7093 emit_int8((unsigned char)0xD8);
7094 emit_operand32(rbx, src);
7095 }
7096
7097 void Assembler::fcompp() {
7098 emit_int8((unsigned char)0xDE);
7099 emit_int8((unsigned char)0xD9);
7100 }
7101
7102 void Assembler::fcos() {
7103 emit_int8((unsigned char)0xD9);
7104 emit_int8((unsigned char)0xFF);
7105 }
7106
7107 void Assembler::fdecstp() {
7108 emit_int8((unsigned char)0xD9);
7109 emit_int8((unsigned char)0xF6);
7110 }
7111
7112 void Assembler::fdiv(int i) {
7113 emit_farith(0xD8, 0xF0, i);
7114 }
7115
7116 void Assembler::fdiv_d(Address src) {
7117 InstructionMark im(this);
7118 emit_int8((unsigned char)0xDC);
7119 emit_operand32(rsi, src);
7120 }
7121
7122 void Assembler::fdiv_s(Address src) {
7123 InstructionMark im(this);
7124 emit_int8((unsigned char)0xD8);
7125 emit_operand32(rsi, src);
7126 }
7127
7128 void Assembler::fdiva(int i) {
7129 emit_farith(0xDC, 0xF8, i);
7130 }
7131
7132 // Note: The Intel manual (Pentium Processor User's Manual, Vol.3, 1994)
7133 // is erroneous for some of the floating-point instructions below.
7134
7135 void Assembler::fdivp(int i) {
7136 emit_farith(0xDE, 0xF8, i); // ST(0) <- ST(0) / ST(1) and pop (Intel manual wrong)
7137 }
7138
7139 void Assembler::fdivr(int i) {
7140 emit_farith(0xD8, 0xF8, i);
7141 }
7142
7143 void Assembler::fdivr_d(Address src) {
7144 InstructionMark im(this);
7145 emit_int8((unsigned char)0xDC);
7146 emit_operand32(rdi, src);
7147 }
7148
7149 void Assembler::fdivr_s(Address src) {
7150 InstructionMark im(this);
7151 emit_int8((unsigned char)0xD8);
7152 emit_operand32(rdi, src);
7153 }
7154
7155 void Assembler::fdivra(int i) {
7156 emit_farith(0xDC, 0xF0, i);
7157 }
7158
7159 void Assembler::fdivrp(int i) {
7160 emit_farith(0xDE, 0xF0, i); // ST(0) <- ST(1) / ST(0) and pop (Intel manual wrong)
7161 }
7162
7163 void Assembler::ffree(int i) {
7164 emit_farith(0xDD, 0xC0, i);
7165 }
7166
7167 void Assembler::fild_d(Address adr) {
7168 InstructionMark im(this);
7169 emit_int8((unsigned char)0xDF);
7170 emit_operand32(rbp, adr);
7171 }
7172
7173 void Assembler::fild_s(Address adr) {
7174 InstructionMark im(this);
7175 emit_int8((unsigned char)0xDB);
7176 emit_operand32(rax, adr);
7177 }
7178
7179 void Assembler::fincstp() {
7180 emit_int8((unsigned char)0xD9);
7181 emit_int8((unsigned char)0xF7);
7182 }
7183
7184 void Assembler::finit() {
7185 emit_int8((unsigned char)0x9B);
7186 emit_int8((unsigned char)0xDB);
7187 emit_int8((unsigned char)0xE3);
7188 }
7189
7190 void Assembler::fist_s(Address adr) {
7191 InstructionMark im(this);
7192 emit_int8((unsigned char)0xDB);
7193 emit_operand32(rdx, adr);
7194 }
7195
7196 void Assembler::fistp_d(Address adr) {
7197 InstructionMark im(this);
7198 emit_int8((unsigned char)0xDF);
7199 emit_operand32(rdi, adr);
7200 }
7201
7202 void Assembler::fistp_s(Address adr) {
7203 InstructionMark im(this);
7204 emit_int8((unsigned char)0xDB);
7205 emit_operand32(rbx, adr);
7206 }
7207
7208 void Assembler::fld1() {
7209 emit_int8((unsigned char)0xD9);
7210 emit_int8((unsigned char)0xE8);
7211 }
7212
7213 void Assembler::fld_d(Address adr) {
7214 InstructionMark im(this);
7215 emit_int8((unsigned char)0xDD);
7216 emit_operand32(rax, adr);
7217 }
7218
7219 void Assembler::fld_s(Address adr) {
7220 InstructionMark im(this);
7221 emit_int8((unsigned char)0xD9);
7222 emit_operand32(rax, adr);
7223 }
7224
7225
7226 void Assembler::fld_s(int index) {
7227 emit_farith(0xD9, 0xC0, index);
7228 }
7229
7230 void Assembler::fld_x(Address adr) {
7231 InstructionMark im(this);
7232 emit_int8((unsigned char)0xDB);
7233 emit_operand32(rbp, adr);
7234 }
7235
7236 void Assembler::fldcw(Address src) {
7237 InstructionMark im(this);
7238 emit_int8((unsigned char)0xD9);
7239 emit_operand32(rbp, src);
7240 }
7241
7242 void Assembler::fldenv(Address src) {
7243 InstructionMark im(this);
7244 emit_int8((unsigned char)0xD9);
7245 emit_operand32(rsp, src);
7246 }
7247
7248 void Assembler::fldlg2() {
7249 emit_int8((unsigned char)0xD9);
7250 emit_int8((unsigned char)0xEC);
7251 }
7252
7253 void Assembler::fldln2() {
7254 emit_int8((unsigned char)0xD9);
7255 emit_int8((unsigned char)0xED);
7256 }
7257
7258 void Assembler::fldz() {
7259 emit_int8((unsigned char)0xD9);
7260 emit_int8((unsigned char)0xEE);
7261 }
7262
7263 void Assembler::flog() {
7264 fldln2();
7265 fxch();
7266 fyl2x();
7267 }
7268
7269 void Assembler::flog10() {
7270 fldlg2();
7271 fxch();
7272 fyl2x();
7273 }
7274
7275 void Assembler::fmul(int i) {
7276 emit_farith(0xD8, 0xC8, i);
7277 }
7278
7279 void Assembler::fmul_d(Address src) {
7280 InstructionMark im(this);
7281 emit_int8((unsigned char)0xDC);
7282 emit_operand32(rcx, src);
7283 }
7284
7285 void Assembler::fmul_s(Address src) {
7286 InstructionMark im(this);
7287 emit_int8((unsigned char)0xD8);
7288 emit_operand32(rcx, src);
7289 }
7290
7291 void Assembler::fmula(int i) {
7292 emit_farith(0xDC, 0xC8, i);
7293 }
7294
7295 void Assembler::fmulp(int i) {
7296 emit_farith(0xDE, 0xC8, i);
7297 }
7298
7299 void Assembler::fnsave(Address dst) {
7300 InstructionMark im(this);
7301 emit_int8((unsigned char)0xDD);
7302 emit_operand32(rsi, dst);
7303 }
7304
7305 void Assembler::fnstcw(Address src) {
7306 InstructionMark im(this);
7307 emit_int8((unsigned char)0x9B);
7308 emit_int8((unsigned char)0xD9);
7309 emit_operand32(rdi, src);
7310 }
7311
7312 void Assembler::fnstsw_ax() {
7313 emit_int8((unsigned char)0xDF);
7314 emit_int8((unsigned char)0xE0);
7315 }
7316
7317 void Assembler::fprem() {
7318 emit_int8((unsigned char)0xD9);
7319 emit_int8((unsigned char)0xF8);
7320 }
7321
7322 void Assembler::fprem1() {
7323 emit_int8((unsigned char)0xD9);
7324 emit_int8((unsigned char)0xF5);
7325 }
7326
7327 void Assembler::frstor(Address src) {
7328 InstructionMark im(this);
7329 emit_int8((unsigned char)0xDD);
7330 emit_operand32(rsp, src);
7331 }
7332
7333 void Assembler::fsin() {
7334 emit_int8((unsigned char)0xD9);
7335 emit_int8((unsigned char)0xFE);
7336 }
7337
7338 void Assembler::fsqrt() {
7339 emit_int8((unsigned char)0xD9);
7340 emit_int8((unsigned char)0xFA);
7341 }
7342
7343 void Assembler::fst_d(Address adr) {
7344 InstructionMark im(this);
7345 emit_int8((unsigned char)0xDD);
7346 emit_operand32(rdx, adr);
7347 }
7348
7349 void Assembler::fst_s(Address adr) {
7350 InstructionMark im(this);
7351 emit_int8((unsigned char)0xD9);
7352 emit_operand32(rdx, adr);
7353 }
7354
7355 void Assembler::fstp_d(Address adr) {
7356 InstructionMark im(this);
7357 emit_int8((unsigned char)0xDD);
7358 emit_operand32(rbx, adr);
7359 }
7360
7361 void Assembler::fstp_d(int index) {
7362 emit_farith(0xDD, 0xD8, index);
7363 }
7364
7365 void Assembler::fstp_s(Address adr) {
7366 InstructionMark im(this);
7367 emit_int8((unsigned char)0xD9);
7368 emit_operand32(rbx, adr);
7369 }
7370
7371 void Assembler::fstp_x(Address adr) {
7372 InstructionMark im(this);
7373 emit_int8((unsigned char)0xDB);
7374 emit_operand32(rdi, adr);
7375 }
7376
7377 void Assembler::fsub(int i) {
7378 emit_farith(0xD8, 0xE0, i);
7379 }
7380
7381 void Assembler::fsub_d(Address src) {
7382 InstructionMark im(this);
7383 emit_int8((unsigned char)0xDC);
7384 emit_operand32(rsp, src);
7385 }
7386
7387 void Assembler::fsub_s(Address src) {
7388 InstructionMark im(this);
7389 emit_int8((unsigned char)0xD8);
7390 emit_operand32(rsp, src);
7391 }
7392
7393 void Assembler::fsuba(int i) {
7394 emit_farith(0xDC, 0xE8, i);
7395 }
7396
7397 void Assembler::fsubp(int i) {
7398 emit_farith(0xDE, 0xE8, i); // ST(0) <- ST(0) - ST(1) and pop (Intel manual wrong)
7399 }
7400
7401 void Assembler::fsubr(int i) {
7402 emit_farith(0xD8, 0xE8, i);
7403 }
7404
7405 void Assembler::fsubr_d(Address src) {
7406 InstructionMark im(this);
7407 emit_int8((unsigned char)0xDC);
7408 emit_operand32(rbp, src);
7409 }
7410
7411 void Assembler::fsubr_s(Address src) {
7412 InstructionMark im(this);
7413 emit_int8((unsigned char)0xD8);
7414 emit_operand32(rbp, src);
7415 }
7416
7417 void Assembler::fsubra(int i) {
7418 emit_farith(0xDC, 0xE0, i);
7419 }
7420
7421 void Assembler::fsubrp(int i) {
7422 emit_farith(0xDE, 0xE0, i); // ST(0) <- ST(1) - ST(0) and pop (Intel manual wrong)
7423 }
7424
7425 void Assembler::ftan() {
7426 emit_int8((unsigned char)0xD9);
7427 emit_int8((unsigned char)0xF2);
7428 emit_int8((unsigned char)0xDD);
7429 emit_int8((unsigned char)0xD8);
7430 }
7431
7432 void Assembler::ftst() {
7433 emit_int8((unsigned char)0xD9);
7434 emit_int8((unsigned char)0xE4);
7435 }
7436
7437 void Assembler::fucomi(int i) {
7438 // make sure the instruction is supported (introduced for P6, together with cmov)
7439 guarantee(VM_Version::supports_cmov(), "illegal instruction");
7440 emit_farith(0xDB, 0xE8, i);
7441 }
7442
7443 void Assembler::fucomip(int i) {
7444 // make sure the instruction is supported (introduced for P6, together with cmov)
7445 guarantee(VM_Version::supports_cmov(), "illegal instruction");
7446 emit_farith(0xDF, 0xE8, i);
7447 }
7448
7449 void Assembler::fwait() {
7450 emit_int8((unsigned char)0x9B);
7451 }
7452
7453 void Assembler::fxch(int i) {
7454 emit_farith(0xD9, 0xC8, i);
7455 }
7456
7457 void Assembler::fyl2x() {
7458 emit_int8((unsigned char)0xD9);
7459 emit_int8((unsigned char)0xF1);
7460 }
7461
7462 void Assembler::frndint() {
7463 emit_int8((unsigned char)0xD9);
7464 emit_int8((unsigned char)0xFC);
7465 }
7466
7467 void Assembler::f2xm1() {
7468 emit_int8((unsigned char)0xD9);
7469 emit_int8((unsigned char)0xF0);
7470 }
7471
7472 void Assembler::fldl2e() {
7473 emit_int8((unsigned char)0xD9);
7474 emit_int8((unsigned char)0xEA);
7475 }
7476
7477 // SSE SIMD prefix byte values corresponding to VexSimdPrefix encoding.
7478 static int simd_pre[4] = { 0, 0x66, 0xF3, 0xF2 };
7479 // SSE opcode second byte values (first is 0x0F) corresponding to VexOpcode encoding.
7480 static int simd_opc[4] = { 0, 0, 0x38, 0x3A };
7481
7482 // Generate SSE legacy REX prefix and SIMD opcode based on VEX encoding.
7483 void Assembler::rex_prefix(Address adr, XMMRegister xreg, VexSimdPrefix pre, VexOpcode opc, bool rex_w) {
7484 if (pre > 0) {
7485 emit_int8(simd_pre[pre]);
7486 }
7487 if (rex_w) {
7488 prefixq(adr, xreg);
7489 } else {
7490 prefix(adr, xreg);
7491 }
7492 if (opc > 0) {
7493 emit_int8(0x0F);
7494 int opc2 = simd_opc[opc];
7495 if (opc2 > 0) {
7496 emit_int8(opc2);
7497 }
7498 }
7499 }
7500
7501 int Assembler::rex_prefix_and_encode(int dst_enc, int src_enc, VexSimdPrefix pre, VexOpcode opc, bool rex_w) {
7502 if (pre > 0) {
7503 emit_int8(simd_pre[pre]);
7504 }
7505 int encode = (rex_w) ? prefixq_and_encode(dst_enc, src_enc) : prefix_and_encode(dst_enc, src_enc);
7506 if (opc > 0) {
7507 emit_int8(0x0F);
7508 int opc2 = simd_opc[opc];
7509 if (opc2 > 0) {
7510 emit_int8(opc2);
7511 }
7512 }
7513 return encode;
7514 }
7515
7516
7517 void Assembler::vex_prefix(bool vex_r, bool vex_b, bool vex_x, int nds_enc, VexSimdPrefix pre, VexOpcode opc) {
7518 int vector_len = _attributes->get_vector_len();
7519 bool vex_w = _attributes->is_rex_vex_w();
7520 if (vex_b || vex_x || vex_w || (opc == VEX_OPCODE_0F_38) || (opc == VEX_OPCODE_0F_3A)) {
7521 prefix(VEX_3bytes);
7522
7523 int byte1 = (vex_r ? VEX_R : 0) | (vex_x ? VEX_X : 0) | (vex_b ? VEX_B : 0);
7524 byte1 = (~byte1) & 0xE0;
7525 byte1 |= opc;
7526 emit_int8(byte1);
7527
7528 int byte2 = ((~nds_enc) & 0xf) << 3;
7529 byte2 |= (vex_w ? VEX_W : 0) | ((vector_len > 0) ? 4 : 0) | pre;
7530 emit_int8(byte2);
7531 } else {
7532 prefix(VEX_2bytes);
7533
7534 int byte1 = vex_r ? VEX_R : 0;
7535 byte1 = (~byte1) & 0x80;
7536 byte1 |= ((~nds_enc) & 0xf) << 3;
7537 byte1 |= ((vector_len > 0 ) ? 4 : 0) | pre;
7538 emit_int8(byte1);
7539 }
7540 }
7541
7542 // This is a 4 byte encoding
7543 void Assembler::evex_prefix(bool vex_r, bool vex_b, bool vex_x, bool evex_r, bool evex_v, int nds_enc, VexSimdPrefix pre, VexOpcode opc){
7544 // EVEX 0x62 prefix
7545 prefix(EVEX_4bytes);
7546 bool vex_w = _attributes->is_rex_vex_w();
7547 int evex_encoding = (vex_w ? VEX_W : 0);
7548 // EVEX.b is not currently used for broadcast of single element or data rounding modes
7549 _attributes->set_evex_encoding(evex_encoding);
7550
7551 // P0: byte 2, initialized to RXBR`00mm
7552 // instead of not'd
7553 int byte2 = (vex_r ? VEX_R : 0) | (vex_x ? VEX_X : 0) | (vex_b ? VEX_B : 0) | (evex_r ? EVEX_Rb : 0);
7554 byte2 = (~byte2) & 0xF0;
7555 // confine opc opcode extensions in mm bits to lower two bits
7556 // of form {0F, 0F_38, 0F_3A}
7557 byte2 |= opc;
7558 emit_int8(byte2);
7559
7560 // P1: byte 3 as Wvvvv1pp
7561 int byte3 = ((~nds_enc) & 0xf) << 3;
7562 // p[10] is always 1
7563 byte3 |= EVEX_F;
7564 byte3 |= (vex_w & 1) << 7;
7565 // confine pre opcode extensions in pp bits to lower two bits
7566 // of form {66, F3, F2}
7567 byte3 |= pre;
7568 emit_int8(byte3);
7569
7570 // P2: byte 4 as zL'Lbv'aaa
7571 // kregs are implemented in the low 3 bits as aaa (hard code k1, it will be initialized for now)
7572 int byte4 = (_attributes->is_no_reg_mask()) ?
7573 0 :
7574 _attributes->get_embedded_opmask_register_specifier();
7575 // EVEX.v` for extending EVEX.vvvv or VIDX
7576 byte4 |= (evex_v ? 0: EVEX_V);
7577 // third EXEC.b for broadcast actions
7578 byte4 |= (_attributes->is_extended_context() ? EVEX_Rb : 0);
7579 // fourth EVEX.L'L for vector length : 0 is 128, 1 is 256, 2 is 512, currently we do not support 1024
7580 byte4 |= ((_attributes->get_vector_len())& 0x3) << 5;
7581 // last is EVEX.z for zero/merge actions
7582 if (_attributes->is_no_reg_mask() == false) {
7583 byte4 |= (_attributes->is_clear_context() ? EVEX_Z : 0);
7584 }
7585 emit_int8(byte4);
7586 }
7587
7588 void Assembler::vex_prefix(Address adr, int nds_enc, int xreg_enc, VexSimdPrefix pre, VexOpcode opc, InstructionAttr *attributes) {
7589 bool vex_r = ((xreg_enc & 8) == 8) ? 1 : 0;
7590 bool vex_b = adr.base_needs_rex();
7591 bool vex_x;
7592 if (adr.isxmmindex()) {
7593 vex_x = adr.xmmindex_needs_rex();
7594 } else {
7595 vex_x = adr.index_needs_rex();
7596 }
7597 set_attributes(attributes);
7598 attributes->set_current_assembler(this);
7599
7600 // if vector length is turned off, revert to AVX for vectors smaller than 512-bit
7601 if (UseAVX > 2 && _legacy_mode_vl && attributes->uses_vl()) {
7602 switch (attributes->get_vector_len()) {
7603 case AVX_128bit:
7604 case AVX_256bit:
7605 attributes->set_is_legacy_mode();
7606 break;
7607 }
7608 }
7609
7610 // For pure EVEX check and see if this instruction
7611 // is allowed in legacy mode and has resources which will
7612 // fit in it. Pure EVEX instructions will use set_is_evex_instruction in their definition,
7613 // else that field is set when we encode to EVEX
7614 if (UseAVX > 2 && !attributes->is_legacy_mode() &&
7615 !_is_managed && !attributes->is_evex_instruction()) {
7616 if (!_legacy_mode_vl && attributes->get_vector_len() != AVX_512bit) {
7617 bool check_register_bank = NOT_IA32(true) IA32_ONLY(false);
7618 if (check_register_bank) {
7619 // check nds_enc and xreg_enc for upper bank usage
7620 if (nds_enc < 16 && xreg_enc < 16) {
7621 attributes->set_is_legacy_mode();
7622 }
7623 } else {
7624 attributes->set_is_legacy_mode();
7625 }
7626 }
7627 }
7628
7629 _is_managed = false;
7630 if (UseAVX > 2 && !attributes->is_legacy_mode())
7631 {
7632 bool evex_r = (xreg_enc >= 16);
7633 bool evex_v;
7634 // EVEX.V' is set to true when VSIB is used as we may need to use higher order XMM registers (16-31)
7635 if (adr.isxmmindex()) {
7636 evex_v = ((adr._xmmindex->encoding() > 15) ? true : false);
7637 } else {
7638 evex_v = (nds_enc >= 16);
7639 }
7640 attributes->set_is_evex_instruction();
7641 evex_prefix(vex_r, vex_b, vex_x, evex_r, evex_v, nds_enc, pre, opc);
7642 } else {
7643 if (UseAVX > 2 && attributes->is_rex_vex_w_reverted()) {
7644 attributes->set_rex_vex_w(false);
7645 }
7646 vex_prefix(vex_r, vex_b, vex_x, nds_enc, pre, opc);
7647 }
7648 }
7649
7650 int Assembler::vex_prefix_and_encode(int dst_enc, int nds_enc, int src_enc, VexSimdPrefix pre, VexOpcode opc, InstructionAttr *attributes) {
7651 bool vex_r = ((dst_enc & 8) == 8) ? 1 : 0;
7652 bool vex_b = ((src_enc & 8) == 8) ? 1 : 0;
7653 bool vex_x = false;
7654 set_attributes(attributes);
7655 attributes->set_current_assembler(this);
7656 bool check_register_bank = NOT_IA32(true) IA32_ONLY(false);
7657
7658 // if vector length is turned off, revert to AVX for vectors smaller than 512-bit
7659 if (UseAVX > 2 && _legacy_mode_vl && attributes->uses_vl()) {
7660 switch (attributes->get_vector_len()) {
7661 case AVX_128bit:
7662 case AVX_256bit:
7663 if (check_register_bank) {
7664 if (dst_enc >= 16 || nds_enc >= 16 || src_enc >= 16) {
7665 // up propagate arithmetic instructions to meet RA requirements
7666 attributes->set_vector_len(AVX_512bit);
7667 } else {
7668 attributes->set_is_legacy_mode();
7669 }
7670 } else {
7671 attributes->set_is_legacy_mode();
7672 }
7673 break;
7674 }
7675 }
7676
7677 // For pure EVEX check and see if this instruction
7678 // is allowed in legacy mode and has resources which will
7679 // fit in it. Pure EVEX instructions will use set_is_evex_instruction in their definition,
7680 // else that field is set when we encode to EVEX
7681 if (UseAVX > 2 && !attributes->is_legacy_mode() &&
7682 !_is_managed && !attributes->is_evex_instruction()) {
7683 if (!_legacy_mode_vl && attributes->get_vector_len() != AVX_512bit) {
7684 if (check_register_bank) {
7685 // check dst_enc, nds_enc and src_enc for upper bank usage
7686 if (dst_enc < 16 && nds_enc < 16 && src_enc < 16) {
7687 attributes->set_is_legacy_mode();
7688 }
7689 } else {
7690 attributes->set_is_legacy_mode();
7691 }
7692 }
7693 }
7694
7695 _is_managed = false;
7696 if (UseAVX > 2 && !attributes->is_legacy_mode())
7697 {
7698 bool evex_r = (dst_enc >= 16);
7699 bool evex_v = (nds_enc >= 16);
7700 // can use vex_x as bank extender on rm encoding
7701 vex_x = (src_enc >= 16);
7702 attributes->set_is_evex_instruction();
7703 evex_prefix(vex_r, vex_b, vex_x, evex_r, evex_v, nds_enc, pre, opc);
7704 } else {
7705 if (UseAVX > 2 && attributes->is_rex_vex_w_reverted()) {
7706 attributes->set_rex_vex_w(false);
7707 }
7708 vex_prefix(vex_r, vex_b, vex_x, nds_enc, pre, opc);
7709 }
7710
7711 // return modrm byte components for operands
7712 return (((dst_enc & 7) << 3) | (src_enc & 7));
7713 }
7714
7715
7716 void Assembler::simd_prefix(XMMRegister xreg, XMMRegister nds, Address adr, VexSimdPrefix pre,
7717 VexOpcode opc, InstructionAttr *attributes) {
7718 if (UseAVX > 0) {
7719 int xreg_enc = xreg->encoding();
7720 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
7721 vex_prefix(adr, nds_enc, xreg_enc, pre, opc, attributes);
7722 } else {
7723 assert((nds == xreg) || (nds == xnoreg), "wrong sse encoding");
7724 rex_prefix(adr, xreg, pre, opc, attributes->is_rex_vex_w());
7725 }
7726 }
7727
7728 int Assembler::simd_prefix_and_encode(XMMRegister dst, XMMRegister nds, XMMRegister src, VexSimdPrefix pre,
7729 VexOpcode opc, InstructionAttr *attributes) {
7730 int dst_enc = dst->encoding();
7731 int src_enc = src->encoding();
7732 if (UseAVX > 0) {
7733 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
7734 return vex_prefix_and_encode(dst_enc, nds_enc, src_enc, pre, opc, attributes);
7735 } else {
7736 assert((nds == dst) || (nds == src) || (nds == xnoreg), "wrong sse encoding");
7737 return rex_prefix_and_encode(dst_enc, src_enc, pre, opc, attributes->is_rex_vex_w());
7738 }
7739 }
7740
7741 void Assembler::cmppd(XMMRegister dst, XMMRegister nds, XMMRegister src, int cop, int vector_len) {
7742 assert(VM_Version::supports_avx(), "");
7743 assert(!VM_Version::supports_evex(), "");
7744 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
7745 int encode = simd_prefix_and_encode(dst, nds, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7746 emit_int8((unsigned char)0xC2);
7747 emit_int8((unsigned char)(0xC0 | encode));
7748 emit_int8((unsigned char)(0xF & cop));
7749 }
7750
7751 void Assembler::blendvpd(XMMRegister dst, XMMRegister nds, XMMRegister src1, XMMRegister src2, int vector_len) {
7752 assert(VM_Version::supports_avx(), "");
7753 assert(!VM_Version::supports_evex(), "");
7754 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
7755 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src1->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
7756 emit_int8((unsigned char)0x4B);
7757 emit_int8((unsigned char)(0xC0 | encode));
7758 int src2_enc = src2->encoding();
7759 emit_int8((unsigned char)(0xF0 & src2_enc<<4));
7760 }
7761
7762 void Assembler::cmpps(XMMRegister dst, XMMRegister nds, XMMRegister src, int cop, int vector_len) {
7763 assert(VM_Version::supports_avx(), "");
7764 assert(!VM_Version::supports_evex(), "");
7765 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
7766 int encode = simd_prefix_and_encode(dst, nds, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
7767 emit_int8((unsigned char)0xC2);
7768 emit_int8((unsigned char)(0xC0 | encode));
7769 emit_int8((unsigned char)(0xF & cop));
7770 }
7771
7772 void Assembler::blendvps(XMMRegister dst, XMMRegister nds, XMMRegister src1, XMMRegister src2, int vector_len) {
7773 assert(VM_Version::supports_avx(), "");
7774 assert(!VM_Version::supports_evex(), "");
7775 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
7776 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src1->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
7777 emit_int8((unsigned char)0x4A);
7778 emit_int8((unsigned char)(0xC0 | encode));
7779 int src2_enc = src2->encoding();
7780 emit_int8((unsigned char)(0xF0 & src2_enc<<4));
7781 }
7782
7783 void Assembler::vpblendd(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8, int vector_len) {
7784 assert(VM_Version::supports_avx2(), "");
7785 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
7786 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
7787 emit_int8((unsigned char)0x02);
7788 emit_int8((unsigned char)(0xC0 | encode));
7789 emit_int8((unsigned char)imm8);
7790 }
7791
7792 void Assembler::shlxl(Register dst, Register src1, Register src2) {
7793 assert(VM_Version::supports_bmi2(), "");
7794 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
7795 int encode = vex_prefix_and_encode(dst->encoding(), src2->encoding(), src1->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
7796 emit_int8((unsigned char)0xF7);
7797 emit_int8((unsigned char)(0xC0 | encode));
7798 }
7799
7800 void Assembler::shlxq(Register dst, Register src1, Register src2) {
7801 assert(VM_Version::supports_bmi2(), "");
7802 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
7803 int encode = vex_prefix_and_encode(dst->encoding(), src2->encoding(), src1->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
7804 emit_int8((unsigned char)0xF7);
7805 emit_int8((unsigned char)(0xC0 | encode));
7806 }
7807
7808 #ifndef _LP64
7809
7810 void Assembler::incl(Register dst) {
7811 // Don't use it directly. Use MacroAssembler::incrementl() instead.
7812 emit_int8(0x40 | dst->encoding());
7813 }
7814
7815 void Assembler::lea(Register dst, Address src) {
7816 leal(dst, src);
7817 }
7818
7819 void Assembler::mov_literal32(Address dst, int32_t imm32, RelocationHolder const& rspec) {
7820 InstructionMark im(this);
7821 emit_int8((unsigned char)0xC7);
7822 emit_operand(rax, dst);
7823 emit_data((int)imm32, rspec, 0);
7824 }
7825
7826 void Assembler::mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec) {
7827 InstructionMark im(this);
7828 int encode = prefix_and_encode(dst->encoding());
7829 emit_int8((unsigned char)(0xB8 | encode));
7830 emit_data((int)imm32, rspec, 0);
7831 }
7832
7833 void Assembler::popa() { // 32bit
7834 emit_int8(0x61);
7835 }
7836
7837 void Assembler::push_literal32(int32_t imm32, RelocationHolder const& rspec) {
7838 InstructionMark im(this);
7839 emit_int8(0x68);
7840 emit_data(imm32, rspec, 0);
7841 }
7842
7843 void Assembler::pusha() { // 32bit
7844 emit_int8(0x60);
7845 }
7846
7847 void Assembler::set_byte_if_not_zero(Register dst) {
7848 emit_int8(0x0F);
7849 emit_int8((unsigned char)0x95);
7850 emit_int8((unsigned char)(0xE0 | dst->encoding()));
7851 }
7852
7853 void Assembler::shldl(Register dst, Register src) {
7854 emit_int8(0x0F);
7855 emit_int8((unsigned char)0xA5);
7856 emit_int8((unsigned char)(0xC0 | src->encoding() << 3 | dst->encoding()));
7857 }
7858
7859 // 0F A4 / r ib
7860 void Assembler::shldl(Register dst, Register src, int8_t imm8) {
7861 emit_int8(0x0F);
7862 emit_int8((unsigned char)0xA4);
7863 emit_int8((unsigned char)(0xC0 | src->encoding() << 3 | dst->encoding()));
7864 emit_int8(imm8);
7865 }
7866
7867 void Assembler::shrdl(Register dst, Register src) {
7868 emit_int8(0x0F);
7869 emit_int8((unsigned char)0xAD);
7870 emit_int8((unsigned char)(0xC0 | src->encoding() << 3 | dst->encoding()));
7871 }
7872
7873 #else // LP64
7874
7875 void Assembler::set_byte_if_not_zero(Register dst) {
7876 int enc = prefix_and_encode(dst->encoding(), true);
7877 emit_int8(0x0F);
7878 emit_int8((unsigned char)0x95);
7879 emit_int8((unsigned char)(0xE0 | enc));
7880 }
7881
7882 // 64bit only pieces of the assembler
7883 // This should only be used by 64bit instructions that can use rip-relative
7884 // it cannot be used by instructions that want an immediate value.
7885
7886 bool Assembler::reachable(AddressLiteral adr) {
7887 int64_t disp;
7888 // None will force a 64bit literal to the code stream. Likely a placeholder
7889 // for something that will be patched later and we need to certain it will
7890 // always be reachable.
7891 if (adr.reloc() == relocInfo::none) {
7892 return false;
7893 }
7894 if (adr.reloc() == relocInfo::internal_word_type) {
7895 // This should be rip relative and easily reachable.
7896 return true;
7897 }
7898 if (adr.reloc() == relocInfo::virtual_call_type ||
7899 adr.reloc() == relocInfo::opt_virtual_call_type ||
7900 adr.reloc() == relocInfo::static_call_type ||
7901 adr.reloc() == relocInfo::static_stub_type ) {
7902 // This should be rip relative within the code cache and easily
7903 // reachable until we get huge code caches. (At which point
7904 // ic code is going to have issues).
7905 return true;
7906 }
7907 if (adr.reloc() != relocInfo::external_word_type &&
7908 adr.reloc() != relocInfo::poll_return_type && // these are really external_word but need special
7909 adr.reloc() != relocInfo::poll_type && // relocs to identify them
7910 adr.reloc() != relocInfo::runtime_call_type ) {
7911 return false;
7912 }
7913
7914 // Stress the correction code
7915 if (ForceUnreachable) {
7916 // Must be runtimecall reloc, see if it is in the codecache
7917 // Flipping stuff in the codecache to be unreachable causes issues
7918 // with things like inline caches where the additional instructions
7919 // are not handled.
7920 if (CodeCache::find_blob(adr._target) == NULL) {
7921 return false;
7922 }
7923 }
7924 // For external_word_type/runtime_call_type if it is reachable from where we
7925 // are now (possibly a temp buffer) and where we might end up
7926 // anywhere in the codeCache then we are always reachable.
7927 // This would have to change if we ever save/restore shared code
7928 // to be more pessimistic.
7929 disp = (int64_t)adr._target - ((int64_t)CodeCache::low_bound() + sizeof(int));
7930 if (!is_simm32(disp)) return false;
7931 disp = (int64_t)adr._target - ((int64_t)CodeCache::high_bound() + sizeof(int));
7932 if (!is_simm32(disp)) return false;
7933
7934 disp = (int64_t)adr._target - ((int64_t)pc() + sizeof(int));
7935
7936 // Because rip relative is a disp + address_of_next_instruction and we
7937 // don't know the value of address_of_next_instruction we apply a fudge factor
7938 // to make sure we will be ok no matter the size of the instruction we get placed into.
7939 // We don't have to fudge the checks above here because they are already worst case.
7940
7941 // 12 == override/rex byte, opcode byte, rm byte, sib byte, a 4-byte disp , 4-byte literal
7942 // + 4 because better safe than sorry.
7943 const int fudge = 12 + 4;
7944 if (disp < 0) {
7945 disp -= fudge;
7946 } else {
7947 disp += fudge;
7948 }
7949 return is_simm32(disp);
7950 }
7951
7952 // Check if the polling page is not reachable from the code cache using rip-relative
7953 // addressing.
7954 bool Assembler::is_polling_page_far() {
7955 intptr_t addr = (intptr_t)os::get_polling_page();
7956 return ForceUnreachable ||
7957 !is_simm32(addr - (intptr_t)CodeCache::low_bound()) ||
7958 !is_simm32(addr - (intptr_t)CodeCache::high_bound());
7959 }
7960
7961 void Assembler::emit_data64(jlong data,
7962 relocInfo::relocType rtype,
7963 int format) {
7964 if (rtype == relocInfo::none) {
7965 emit_int64(data);
7966 } else {
7967 emit_data64(data, Relocation::spec_simple(rtype), format);
7968 }
7969 }
7970
7971 void Assembler::emit_data64(jlong data,
7972 RelocationHolder const& rspec,
7973 int format) {
7974 assert(imm_operand == 0, "default format must be immediate in this file");
7975 assert(imm_operand == format, "must be immediate");
7976 assert(inst_mark() != NULL, "must be inside InstructionMark");
7977 // Do not use AbstractAssembler::relocate, which is not intended for
7978 // embedded words. Instead, relocate to the enclosing instruction.
7979 code_section()->relocate(inst_mark(), rspec, format);
7980 #ifdef ASSERT
7981 check_relocation(rspec, format);
7982 #endif
7983 emit_int64(data);
7984 }
7985
7986 int Assembler::prefix_and_encode(int reg_enc, bool byteinst) {
7987 if (reg_enc >= 8) {
7988 prefix(REX_B);
7989 reg_enc -= 8;
7990 } else if (byteinst && reg_enc >= 4) {
7991 prefix(REX);
7992 }
7993 return reg_enc;
7994 }
7995
7996 int Assembler::prefixq_and_encode(int reg_enc) {
7997 if (reg_enc < 8) {
7998 prefix(REX_W);
7999 } else {
8000 prefix(REX_WB);
8001 reg_enc -= 8;
8002 }
8003 return reg_enc;
8004 }
8005
8006 int Assembler::prefix_and_encode(int dst_enc, bool dst_is_byte, int src_enc, bool src_is_byte) {
8007 if (dst_enc < 8) {
8008 if (src_enc >= 8) {
8009 prefix(REX_B);
8010 src_enc -= 8;
8011 } else if ((src_is_byte && src_enc >= 4) || (dst_is_byte && dst_enc >= 4)) {
8012 prefix(REX);
8013 }
8014 } else {
8015 if (src_enc < 8) {
8016 prefix(REX_R);
8017 } else {
8018 prefix(REX_RB);
8019 src_enc -= 8;
8020 }
8021 dst_enc -= 8;
8022 }
8023 return dst_enc << 3 | src_enc;
8024 }
8025
8026 int Assembler::prefixq_and_encode(int dst_enc, int src_enc) {
8027 if (dst_enc < 8) {
8028 if (src_enc < 8) {
8029 prefix(REX_W);
8030 } else {
8031 prefix(REX_WB);
8032 src_enc -= 8;
8033 }
8034 } else {
8035 if (src_enc < 8) {
8036 prefix(REX_WR);
8037 } else {
8038 prefix(REX_WRB);
8039 src_enc -= 8;
8040 }
8041 dst_enc -= 8;
8042 }
8043 return dst_enc << 3 | src_enc;
8044 }
8045
8046 void Assembler::prefix(Register reg) {
8047 if (reg->encoding() >= 8) {
8048 prefix(REX_B);
8049 }
8050 }
8051
8052 void Assembler::prefix(Register dst, Register src, Prefix p) {
8053 if (src->encoding() >= 8) {
8054 p = (Prefix)(p | REX_B);
8055 }
8056 if (dst->encoding() >= 8) {
8057 p = (Prefix)( p | REX_R);
8058 }
8059 if (p != Prefix_EMPTY) {
8060 // do not generate an empty prefix
8061 prefix(p);
8062 }
8063 }
8064
8065 void Assembler::prefix(Register dst, Address adr, Prefix p) {
8066 if (adr.base_needs_rex()) {
8067 if (adr.index_needs_rex()) {
8068 assert(false, "prefix(Register dst, Address adr, Prefix p) does not support handling of an X");
8069 } else {
8070 prefix(REX_B);
8071 }
8072 } else {
8073 if (adr.index_needs_rex()) {
8074 assert(false, "prefix(Register dst, Address adr, Prefix p) does not support handling of an X");
8075 }
8076 }
8077 if (dst->encoding() >= 8) {
8078 p = (Prefix)(p | REX_R);
8079 }
8080 if (p != Prefix_EMPTY) {
8081 // do not generate an empty prefix
8082 prefix(p);
8083 }
8084 }
8085
8086 void Assembler::prefix(Address adr) {
8087 if (adr.base_needs_rex()) {
8088 if (adr.index_needs_rex()) {
8089 prefix(REX_XB);
8090 } else {
8091 prefix(REX_B);
8092 }
8093 } else {
8094 if (adr.index_needs_rex()) {
8095 prefix(REX_X);
8096 }
8097 }
8098 }
8099
8100 void Assembler::prefixq(Address adr) {
8101 if (adr.base_needs_rex()) {
8102 if (adr.index_needs_rex()) {
8103 prefix(REX_WXB);
8104 } else {
8105 prefix(REX_WB);
8106 }
8107 } else {
8108 if (adr.index_needs_rex()) {
8109 prefix(REX_WX);
8110 } else {
8111 prefix(REX_W);
8112 }
8113 }
8114 }
8115
8116
8117 void Assembler::prefix(Address adr, Register reg, bool byteinst) {
8118 if (reg->encoding() < 8) {
8119 if (adr.base_needs_rex()) {
8120 if (adr.index_needs_rex()) {
8121 prefix(REX_XB);
8122 } else {
8123 prefix(REX_B);
8124 }
8125 } else {
8126 if (adr.index_needs_rex()) {
8127 prefix(REX_X);
8128 } else if (byteinst && reg->encoding() >= 4 ) {
8129 prefix(REX);
8130 }
8131 }
8132 } else {
8133 if (adr.base_needs_rex()) {
8134 if (adr.index_needs_rex()) {
8135 prefix(REX_RXB);
8136 } else {
8137 prefix(REX_RB);
8138 }
8139 } else {
8140 if (adr.index_needs_rex()) {
8141 prefix(REX_RX);
8142 } else {
8143 prefix(REX_R);
8144 }
8145 }
8146 }
8147 }
8148
8149 void Assembler::prefixq(Address adr, Register src) {
8150 if (src->encoding() < 8) {
8151 if (adr.base_needs_rex()) {
8152 if (adr.index_needs_rex()) {
8153 prefix(REX_WXB);
8154 } else {
8155 prefix(REX_WB);
8156 }
8157 } else {
8158 if (adr.index_needs_rex()) {
8159 prefix(REX_WX);
8160 } else {
8161 prefix(REX_W);
8162 }
8163 }
8164 } else {
8165 if (adr.base_needs_rex()) {
8166 if (adr.index_needs_rex()) {
8167 prefix(REX_WRXB);
8168 } else {
8169 prefix(REX_WRB);
8170 }
8171 } else {
8172 if (adr.index_needs_rex()) {
8173 prefix(REX_WRX);
8174 } else {
8175 prefix(REX_WR);
8176 }
8177 }
8178 }
8179 }
8180
8181 void Assembler::prefix(Address adr, XMMRegister reg) {
8182 if (reg->encoding() < 8) {
8183 if (adr.base_needs_rex()) {
8184 if (adr.index_needs_rex()) {
8185 prefix(REX_XB);
8186 } else {
8187 prefix(REX_B);
8188 }
8189 } else {
8190 if (adr.index_needs_rex()) {
8191 prefix(REX_X);
8192 }
8193 }
8194 } else {
8195 if (adr.base_needs_rex()) {
8196 if (adr.index_needs_rex()) {
8197 prefix(REX_RXB);
8198 } else {
8199 prefix(REX_RB);
8200 }
8201 } else {
8202 if (adr.index_needs_rex()) {
8203 prefix(REX_RX);
8204 } else {
8205 prefix(REX_R);
8206 }
8207 }
8208 }
8209 }
8210
8211 void Assembler::prefixq(Address adr, XMMRegister src) {
8212 if (src->encoding() < 8) {
8213 if (adr.base_needs_rex()) {
8214 if (adr.index_needs_rex()) {
8215 prefix(REX_WXB);
8216 } else {
8217 prefix(REX_WB);
8218 }
8219 } else {
8220 if (adr.index_needs_rex()) {
8221 prefix(REX_WX);
8222 } else {
8223 prefix(REX_W);
8224 }
8225 }
8226 } else {
8227 if (adr.base_needs_rex()) {
8228 if (adr.index_needs_rex()) {
8229 prefix(REX_WRXB);
8230 } else {
8231 prefix(REX_WRB);
8232 }
8233 } else {
8234 if (adr.index_needs_rex()) {
8235 prefix(REX_WRX);
8236 } else {
8237 prefix(REX_WR);
8238 }
8239 }
8240 }
8241 }
8242
8243 void Assembler::adcq(Register dst, int32_t imm32) {
8244 (void) prefixq_and_encode(dst->encoding());
8245 emit_arith(0x81, 0xD0, dst, imm32);
8246 }
8247
8248 void Assembler::adcq(Register dst, Address src) {
8249 InstructionMark im(this);
8250 prefixq(src, dst);
8251 emit_int8(0x13);
8252 emit_operand(dst, src);
8253 }
8254
8255 void Assembler::adcq(Register dst, Register src) {
8256 (void) prefixq_and_encode(dst->encoding(), src->encoding());
8257 emit_arith(0x13, 0xC0, dst, src);
8258 }
8259
8260 void Assembler::addq(Address dst, int32_t imm32) {
8261 InstructionMark im(this);
8262 prefixq(dst);
8263 emit_arith_operand(0x81, rax, dst,imm32);
8264 }
8265
8266 void Assembler::addq(Address dst, Register src) {
8267 InstructionMark im(this);
8268 prefixq(dst, src);
8269 emit_int8(0x01);
8270 emit_operand(src, dst);
8271 }
8272
8273 void Assembler::addq(Register dst, int32_t imm32) {
8274 (void) prefixq_and_encode(dst->encoding());
8275 emit_arith(0x81, 0xC0, dst, imm32);
8276 }
8277
8278 void Assembler::addq(Register dst, Address src) {
8279 InstructionMark im(this);
8280 prefixq(src, dst);
8281 emit_int8(0x03);
8282 emit_operand(dst, src);
8283 }
8284
8285 void Assembler::addq(Register dst, Register src) {
8286 (void) prefixq_and_encode(dst->encoding(), src->encoding());
8287 emit_arith(0x03, 0xC0, dst, src);
8288 }
8289
8290 void Assembler::adcxq(Register dst, Register src) {
8291 //assert(VM_Version::supports_adx(), "adx instructions not supported");
8292 emit_int8((unsigned char)0x66);
8293 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8294 emit_int8(0x0F);
8295 emit_int8(0x38);
8296 emit_int8((unsigned char)0xF6);
8297 emit_int8((unsigned char)(0xC0 | encode));
8298 }
8299
8300 void Assembler::adoxq(Register dst, Register src) {
8301 //assert(VM_Version::supports_adx(), "adx instructions not supported");
8302 emit_int8((unsigned char)0xF3);
8303 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8304 emit_int8(0x0F);
8305 emit_int8(0x38);
8306 emit_int8((unsigned char)0xF6);
8307 emit_int8((unsigned char)(0xC0 | encode));
8308 }
8309
8310 void Assembler::andq(Address dst, int32_t imm32) {
8311 InstructionMark im(this);
8312 prefixq(dst);
8313 emit_int8((unsigned char)0x81);
8314 emit_operand(rsp, dst, 4);
8315 emit_int32(imm32);
8316 }
8317
8318 void Assembler::andq(Register dst, int32_t imm32) {
8319 (void) prefixq_and_encode(dst->encoding());
8320 emit_arith(0x81, 0xE0, dst, imm32);
8321 }
8322
8323 void Assembler::andq(Register dst, Address src) {
8324 InstructionMark im(this);
8325 prefixq(src, dst);
8326 emit_int8(0x23);
8327 emit_operand(dst, src);
8328 }
8329
8330 void Assembler::andq(Register dst, Register src) {
8331 (void) prefixq_and_encode(dst->encoding(), src->encoding());
8332 emit_arith(0x23, 0xC0, dst, src);
8333 }
8334
8335 void Assembler::andnq(Register dst, Register src1, Register src2) {
8336 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
8337 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
8338 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
8339 emit_int8((unsigned char)0xF2);
8340 emit_int8((unsigned char)(0xC0 | encode));
8341 }
8342
8343 void Assembler::andnq(Register dst, Register src1, Address src2) {
8344 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
8345 InstructionMark im(this);
8346 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
8347 vex_prefix(src2, src1->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
8348 emit_int8((unsigned char)0xF2);
8349 emit_operand(dst, src2);
8350 }
8351
8352 void Assembler::bsfq(Register dst, Register src) {
8353 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8354 emit_int8(0x0F);
8355 emit_int8((unsigned char)0xBC);
8356 emit_int8((unsigned char)(0xC0 | encode));
8357 }
8358
8359 void Assembler::bsrq(Register dst, Register src) {
8360 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8361 emit_int8(0x0F);
8362 emit_int8((unsigned char)0xBD);
8363 emit_int8((unsigned char)(0xC0 | encode));
8364 }
8365
8366 void Assembler::bswapq(Register reg) {
8367 int encode = prefixq_and_encode(reg->encoding());
8368 emit_int8(0x0F);
8369 emit_int8((unsigned char)(0xC8 | encode));
8370 }
8371
8372 void Assembler::blsiq(Register dst, Register src) {
8373 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
8374 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
8375 int encode = vex_prefix_and_encode(rbx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
8376 emit_int8((unsigned char)0xF3);
8377 emit_int8((unsigned char)(0xC0 | encode));
8378 }
8379
8380 void Assembler::blsiq(Register dst, Address src) {
8381 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
8382 InstructionMark im(this);
8383 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
8384 vex_prefix(src, dst->encoding(), rbx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
8385 emit_int8((unsigned char)0xF3);
8386 emit_operand(rbx, src);
8387 }
8388
8389 void Assembler::blsmskq(Register dst, Register src) {
8390 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
8391 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
8392 int encode = vex_prefix_and_encode(rdx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
8393 emit_int8((unsigned char)0xF3);
8394 emit_int8((unsigned char)(0xC0 | encode));
8395 }
8396
8397 void Assembler::blsmskq(Register dst, Address src) {
8398 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
8399 InstructionMark im(this);
8400 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
8401 vex_prefix(src, dst->encoding(), rdx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
8402 emit_int8((unsigned char)0xF3);
8403 emit_operand(rdx, src);
8404 }
8405
8406 void Assembler::blsrq(Register dst, Register src) {
8407 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
8408 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
8409 int encode = vex_prefix_and_encode(rcx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
8410 emit_int8((unsigned char)0xF3);
8411 emit_int8((unsigned char)(0xC0 | encode));
8412 }
8413
8414 void Assembler::blsrq(Register dst, Address src) {
8415 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
8416 InstructionMark im(this);
8417 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
8418 vex_prefix(src, dst->encoding(), rcx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
8419 emit_int8((unsigned char)0xF3);
8420 emit_operand(rcx, src);
8421 }
8422
8423 void Assembler::cdqq() {
8424 prefix(REX_W);
8425 emit_int8((unsigned char)0x99);
8426 }
8427
8428 void Assembler::clflush(Address adr) {
8429 prefix(adr);
8430 emit_int8(0x0F);
8431 emit_int8((unsigned char)0xAE);
8432 emit_operand(rdi, adr);
8433 }
8434
8435 void Assembler::cmovq(Condition cc, Register dst, Register src) {
8436 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8437 emit_int8(0x0F);
8438 emit_int8(0x40 | cc);
8439 emit_int8((unsigned char)(0xC0 | encode));
8440 }
8441
8442 void Assembler::cmovq(Condition cc, Register dst, Address src) {
8443 InstructionMark im(this);
8444 prefixq(src, dst);
8445 emit_int8(0x0F);
8446 emit_int8(0x40 | cc);
8447 emit_operand(dst, src);
8448 }
8449
8450 void Assembler::cmpq(Address dst, int32_t imm32) {
8451 InstructionMark im(this);
8452 prefixq(dst);
8453 emit_int8((unsigned char)0x81);
8454 emit_operand(rdi, dst, 4);
8455 emit_int32(imm32);
8456 }
8457
8458 void Assembler::cmpq(Register dst, int32_t imm32) {
8459 (void) prefixq_and_encode(dst->encoding());
8460 emit_arith(0x81, 0xF8, dst, imm32);
8461 }
8462
8463 void Assembler::cmpq(Address dst, Register src) {
8464 InstructionMark im(this);
8465 prefixq(dst, src);
8466 emit_int8(0x3B);
8467 emit_operand(src, dst);
8468 }
8469
8470 void Assembler::cmpq(Register dst, Register src) {
8471 (void) prefixq_and_encode(dst->encoding(), src->encoding());
8472 emit_arith(0x3B, 0xC0, dst, src);
8473 }
8474
8475 void Assembler::cmpq(Register dst, Address src) {
8476 InstructionMark im(this);
8477 prefixq(src, dst);
8478 emit_int8(0x3B);
8479 emit_operand(dst, src);
8480 }
8481
8482 void Assembler::cmpxchgq(Register reg, Address adr) {
8483 InstructionMark im(this);
8484 prefixq(adr, reg);
8485 emit_int8(0x0F);
8486 emit_int8((unsigned char)0xB1);
8487 emit_operand(reg, adr);
8488 }
8489
8490 void Assembler::cvtsi2sdq(XMMRegister dst, Register src) {
8491 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
8492 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
8493 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
8494 emit_int8(0x2A);
8495 emit_int8((unsigned char)(0xC0 | encode));
8496 }
8497
8498 void Assembler::cvtsi2sdq(XMMRegister dst, Address src) {
8499 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
8500 InstructionMark im(this);
8501 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
8502 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
8503 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
8504 emit_int8(0x2A);
8505 emit_operand(dst, src);
8506 }
8507
8508 void Assembler::cvtsi2ssq(XMMRegister dst, Address src) {
8509 NOT_LP64(assert(VM_Version::supports_sse(), ""));
8510 InstructionMark im(this);
8511 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
8512 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
8513 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
8514 emit_int8(0x2A);
8515 emit_operand(dst, src);
8516 }
8517
8518 void Assembler::cvttsd2siq(Register dst, XMMRegister src) {
8519 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
8520 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
8521 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
8522 emit_int8(0x2C);
8523 emit_int8((unsigned char)(0xC0 | encode));
8524 }
8525
8526 void Assembler::cvttss2siq(Register dst, XMMRegister src) {
8527 NOT_LP64(assert(VM_Version::supports_sse(), ""));
8528 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
8529 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
8530 emit_int8(0x2C);
8531 emit_int8((unsigned char)(0xC0 | encode));
8532 }
8533
8534 void Assembler::decl(Register dst) {
8535 // Don't use it directly. Use MacroAssembler::decrementl() instead.
8536 // Use two-byte form (one-byte form is a REX prefix in 64-bit mode)
8537 int encode = prefix_and_encode(dst->encoding());
8538 emit_int8((unsigned char)0xFF);
8539 emit_int8((unsigned char)(0xC8 | encode));
8540 }
8541
8542 void Assembler::decq(Register dst) {
8543 // Don't use it directly. Use MacroAssembler::decrementq() instead.
8544 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
8545 int encode = prefixq_and_encode(dst->encoding());
8546 emit_int8((unsigned char)0xFF);
8547 emit_int8(0xC8 | encode);
8548 }
8549
8550 void Assembler::decq(Address dst) {
8551 // Don't use it directly. Use MacroAssembler::decrementq() instead.
8552 InstructionMark im(this);
8553 prefixq(dst);
8554 emit_int8((unsigned char)0xFF);
8555 emit_operand(rcx, dst);
8556 }
8557
8558 void Assembler::fxrstor(Address src) {
8559 prefixq(src);
8560 emit_int8(0x0F);
8561 emit_int8((unsigned char)0xAE);
8562 emit_operand(as_Register(1), src);
8563 }
8564
8565 void Assembler::xrstor(Address src) {
8566 prefixq(src);
8567 emit_int8(0x0F);
8568 emit_int8((unsigned char)0xAE);
8569 emit_operand(as_Register(5), src);
8570 }
8571
8572 void Assembler::fxsave(Address dst) {
8573 prefixq(dst);
8574 emit_int8(0x0F);
8575 emit_int8((unsigned char)0xAE);
8576 emit_operand(as_Register(0), dst);
8577 }
8578
8579 void Assembler::xsave(Address dst) {
8580 prefixq(dst);
8581 emit_int8(0x0F);
8582 emit_int8((unsigned char)0xAE);
8583 emit_operand(as_Register(4), dst);
8584 }
8585
8586 void Assembler::idivq(Register src) {
8587 int encode = prefixq_and_encode(src->encoding());
8588 emit_int8((unsigned char)0xF7);
8589 emit_int8((unsigned char)(0xF8 | encode));
8590 }
8591
8592 void Assembler::imulq(Register dst, Register src) {
8593 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8594 emit_int8(0x0F);
8595 emit_int8((unsigned char)0xAF);
8596 emit_int8((unsigned char)(0xC0 | encode));
8597 }
8598
8599 void Assembler::imulq(Register dst, Register src, int value) {
8600 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8601 if (is8bit(value)) {
8602 emit_int8(0x6B);
8603 emit_int8((unsigned char)(0xC0 | encode));
8604 emit_int8(value & 0xFF);
8605 } else {
8606 emit_int8(0x69);
8607 emit_int8((unsigned char)(0xC0 | encode));
8608 emit_int32(value);
8609 }
8610 }
8611
8612 void Assembler::imulq(Register dst, Address src) {
8613 InstructionMark im(this);
8614 prefixq(src, dst);
8615 emit_int8(0x0F);
8616 emit_int8((unsigned char) 0xAF);
8617 emit_operand(dst, src);
8618 }
8619
8620 void Assembler::incl(Register dst) {
8621 // Don't use it directly. Use MacroAssembler::incrementl() instead.
8622 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
8623 int encode = prefix_and_encode(dst->encoding());
8624 emit_int8((unsigned char)0xFF);
8625 emit_int8((unsigned char)(0xC0 | encode));
8626 }
8627
8628 void Assembler::incq(Register dst) {
8629 // Don't use it directly. Use MacroAssembler::incrementq() instead.
8630 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
8631 int encode = prefixq_and_encode(dst->encoding());
8632 emit_int8((unsigned char)0xFF);
8633 emit_int8((unsigned char)(0xC0 | encode));
8634 }
8635
8636 void Assembler::incq(Address dst) {
8637 // Don't use it directly. Use MacroAssembler::incrementq() instead.
8638 InstructionMark im(this);
8639 prefixq(dst);
8640 emit_int8((unsigned char)0xFF);
8641 emit_operand(rax, dst);
8642 }
8643
8644 void Assembler::lea(Register dst, Address src) {
8645 leaq(dst, src);
8646 }
8647
8648 void Assembler::leaq(Register dst, Address src) {
8649 InstructionMark im(this);
8650 prefixq(src, dst);
8651 emit_int8((unsigned char)0x8D);
8652 emit_operand(dst, src);
8653 }
8654
8655 void Assembler::mov64(Register dst, int64_t imm64) {
8656 InstructionMark im(this);
8657 int encode = prefixq_and_encode(dst->encoding());
8658 emit_int8((unsigned char)(0xB8 | encode));
8659 emit_int64(imm64);
8660 }
8661
8662 void Assembler::mov_literal64(Register dst, intptr_t imm64, RelocationHolder const& rspec) {
8663 InstructionMark im(this);
8664 int encode = prefixq_and_encode(dst->encoding());
8665 emit_int8(0xB8 | encode);
8666 emit_data64(imm64, rspec);
8667 }
8668
8669 void Assembler::mov_narrow_oop(Register dst, int32_t imm32, RelocationHolder const& rspec) {
8670 InstructionMark im(this);
8671 int encode = prefix_and_encode(dst->encoding());
8672 emit_int8((unsigned char)(0xB8 | encode));
8673 emit_data((int)imm32, rspec, narrow_oop_operand);
8674 }
8675
8676 void Assembler::mov_narrow_oop(Address dst, int32_t imm32, RelocationHolder const& rspec) {
8677 InstructionMark im(this);
8678 prefix(dst);
8679 emit_int8((unsigned char)0xC7);
8680 emit_operand(rax, dst, 4);
8681 emit_data((int)imm32, rspec, narrow_oop_operand);
8682 }
8683
8684 void Assembler::cmp_narrow_oop(Register src1, int32_t imm32, RelocationHolder const& rspec) {
8685 InstructionMark im(this);
8686 int encode = prefix_and_encode(src1->encoding());
8687 emit_int8((unsigned char)0x81);
8688 emit_int8((unsigned char)(0xF8 | encode));
8689 emit_data((int)imm32, rspec, narrow_oop_operand);
8690 }
8691
8692 void Assembler::cmp_narrow_oop(Address src1, int32_t imm32, RelocationHolder const& rspec) {
8693 InstructionMark im(this);
8694 prefix(src1);
8695 emit_int8((unsigned char)0x81);
8696 emit_operand(rax, src1, 4);
8697 emit_data((int)imm32, rspec, narrow_oop_operand);
8698 }
8699
8700 void Assembler::lzcntq(Register dst, Register src) {
8701 assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR");
8702 emit_int8((unsigned char)0xF3);
8703 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8704 emit_int8(0x0F);
8705 emit_int8((unsigned char)0xBD);
8706 emit_int8((unsigned char)(0xC0 | encode));
8707 }
8708
8709 void Assembler::movdq(XMMRegister dst, Register src) {
8710 // table D-1 says MMX/SSE2
8711 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
8712 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
8713 int encode = simd_prefix_and_encode(dst, xnoreg, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
8714 emit_int8(0x6E);
8715 emit_int8((unsigned char)(0xC0 | encode));
8716 }
8717
8718 void Assembler::movdq(Register dst, XMMRegister src) {
8719 // table D-1 says MMX/SSE2
8720 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
8721 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
8722 // swap src/dst to get correct prefix
8723 int encode = simd_prefix_and_encode(src, xnoreg, as_XMMRegister(dst->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
8724 emit_int8(0x7E);
8725 emit_int8((unsigned char)(0xC0 | encode));
8726 }
8727
8728 void Assembler::movq(Register dst, Register src) {
8729 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8730 emit_int8((unsigned char)0x8B);
8731 emit_int8((unsigned char)(0xC0 | encode));
8732 }
8733
8734 void Assembler::movq(Register dst, Address src) {
8735 InstructionMark im(this);
8736 prefixq(src, dst);
8737 emit_int8((unsigned char)0x8B);
8738 emit_operand(dst, src);
8739 }
8740
8741 void Assembler::movq(Address dst, Register src) {
8742 InstructionMark im(this);
8743 prefixq(dst, src);
8744 emit_int8((unsigned char)0x89);
8745 emit_operand(src, dst);
8746 }
8747
8748 void Assembler::movsbq(Register dst, Address src) {
8749 InstructionMark im(this);
8750 prefixq(src, dst);
8751 emit_int8(0x0F);
8752 emit_int8((unsigned char)0xBE);
8753 emit_operand(dst, src);
8754 }
8755
8756 void Assembler::movsbq(Register dst, Register src) {
8757 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8758 emit_int8(0x0F);
8759 emit_int8((unsigned char)0xBE);
8760 emit_int8((unsigned char)(0xC0 | encode));
8761 }
8762
8763 void Assembler::movslq(Register dst, int32_t imm32) {
8764 // dbx shows movslq(rcx, 3) as movq $0x0000000049000000,(%rbx)
8765 // and movslq(r8, 3); as movl $0x0000000048000000,(%rbx)
8766 // as a result we shouldn't use until tested at runtime...
8767 ShouldNotReachHere();
8768 InstructionMark im(this);
8769 int encode = prefixq_and_encode(dst->encoding());
8770 emit_int8((unsigned char)(0xC7 | encode));
8771 emit_int32(imm32);
8772 }
8773
8774 void Assembler::movslq(Address dst, int32_t imm32) {
8775 assert(is_simm32(imm32), "lost bits");
8776 InstructionMark im(this);
8777 prefixq(dst);
8778 emit_int8((unsigned char)0xC7);
8779 emit_operand(rax, dst, 4);
8780 emit_int32(imm32);
8781 }
8782
8783 void Assembler::movslq(Register dst, Address src) {
8784 InstructionMark im(this);
8785 prefixq(src, dst);
8786 emit_int8(0x63);
8787 emit_operand(dst, src);
8788 }
8789
8790 void Assembler::movslq(Register dst, Register src) {
8791 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8792 emit_int8(0x63);
8793 emit_int8((unsigned char)(0xC0 | encode));
8794 }
8795
8796 void Assembler::movswq(Register dst, Address src) {
8797 InstructionMark im(this);
8798 prefixq(src, dst);
8799 emit_int8(0x0F);
8800 emit_int8((unsigned char)0xBF);
8801 emit_operand(dst, src);
8802 }
8803
8804 void Assembler::movswq(Register dst, Register src) {
8805 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8806 emit_int8((unsigned char)0x0F);
8807 emit_int8((unsigned char)0xBF);
8808 emit_int8((unsigned char)(0xC0 | encode));
8809 }
8810
8811 void Assembler::movzbq(Register dst, Address src) {
8812 InstructionMark im(this);
8813 prefixq(src, dst);
8814 emit_int8((unsigned char)0x0F);
8815 emit_int8((unsigned char)0xB6);
8816 emit_operand(dst, src);
8817 }
8818
8819 void Assembler::movzbq(Register dst, Register src) {
8820 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8821 emit_int8(0x0F);
8822 emit_int8((unsigned char)0xB6);
8823 emit_int8(0xC0 | encode);
8824 }
8825
8826 void Assembler::movzwq(Register dst, Address src) {
8827 InstructionMark im(this);
8828 prefixq(src, dst);
8829 emit_int8((unsigned char)0x0F);
8830 emit_int8((unsigned char)0xB7);
8831 emit_operand(dst, src);
8832 }
8833
8834 void Assembler::movzwq(Register dst, Register src) {
8835 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8836 emit_int8((unsigned char)0x0F);
8837 emit_int8((unsigned char)0xB7);
8838 emit_int8((unsigned char)(0xC0 | encode));
8839 }
8840
8841 void Assembler::mulq(Address src) {
8842 InstructionMark im(this);
8843 prefixq(src);
8844 emit_int8((unsigned char)0xF7);
8845 emit_operand(rsp, src);
8846 }
8847
8848 void Assembler::mulq(Register src) {
8849 int encode = prefixq_and_encode(src->encoding());
8850 emit_int8((unsigned char)0xF7);
8851 emit_int8((unsigned char)(0xE0 | encode));
8852 }
8853
8854 void Assembler::mulxq(Register dst1, Register dst2, Register src) {
8855 assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported");
8856 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
8857 int encode = vex_prefix_and_encode(dst1->encoding(), dst2->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F_38, &attributes);
8858 emit_int8((unsigned char)0xF6);
8859 emit_int8((unsigned char)(0xC0 | encode));
8860 }
8861
8862 void Assembler::negq(Register dst) {
8863 int encode = prefixq_and_encode(dst->encoding());
8864 emit_int8((unsigned char)0xF7);
8865 emit_int8((unsigned char)(0xD8 | encode));
8866 }
8867
8868 void Assembler::notq(Register dst) {
8869 int encode = prefixq_and_encode(dst->encoding());
8870 emit_int8((unsigned char)0xF7);
8871 emit_int8((unsigned char)(0xD0 | encode));
8872 }
8873
8874 void Assembler::orq(Address dst, int32_t imm32) {
8875 InstructionMark im(this);
8876 prefixq(dst);
8877 emit_int8((unsigned char)0x81);
8878 emit_operand(rcx, dst, 4);
8879 emit_int32(imm32);
8880 }
8881
8882 void Assembler::orq(Register dst, int32_t imm32) {
8883 (void) prefixq_and_encode(dst->encoding());
8884 emit_arith(0x81, 0xC8, dst, imm32);
8885 }
8886
8887 void Assembler::orq(Register dst, Address src) {
8888 InstructionMark im(this);
8889 prefixq(src, dst);
8890 emit_int8(0x0B);
8891 emit_operand(dst, src);
8892 }
8893
8894 void Assembler::orq(Register dst, Register src) {
8895 (void) prefixq_and_encode(dst->encoding(), src->encoding());
8896 emit_arith(0x0B, 0xC0, dst, src);
8897 }
8898
8899 void Assembler::popa() { // 64bit
8900 movq(r15, Address(rsp, 0));
8901 movq(r14, Address(rsp, wordSize));
8902 movq(r13, Address(rsp, 2 * wordSize));
8903 movq(r12, Address(rsp, 3 * wordSize));
8904 movq(r11, Address(rsp, 4 * wordSize));
8905 movq(r10, Address(rsp, 5 * wordSize));
8906 movq(r9, Address(rsp, 6 * wordSize));
8907 movq(r8, Address(rsp, 7 * wordSize));
8908 movq(rdi, Address(rsp, 8 * wordSize));
8909 movq(rsi, Address(rsp, 9 * wordSize));
8910 movq(rbp, Address(rsp, 10 * wordSize));
8911 // skip rsp
8912 movq(rbx, Address(rsp, 12 * wordSize));
8913 movq(rdx, Address(rsp, 13 * wordSize));
8914 movq(rcx, Address(rsp, 14 * wordSize));
8915 movq(rax, Address(rsp, 15 * wordSize));
8916
8917 addq(rsp, 16 * wordSize);
8918 }
8919
8920 void Assembler::popcntq(Register dst, Address src) {
8921 assert(VM_Version::supports_popcnt(), "must support");
8922 InstructionMark im(this);
8923 emit_int8((unsigned char)0xF3);
8924 prefixq(src, dst);
8925 emit_int8((unsigned char)0x0F);
8926 emit_int8((unsigned char)0xB8);
8927 emit_operand(dst, src);
8928 }
8929
8930 void Assembler::popcntq(Register dst, Register src) {
8931 assert(VM_Version::supports_popcnt(), "must support");
8932 emit_int8((unsigned char)0xF3);
8933 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8934 emit_int8((unsigned char)0x0F);
8935 emit_int8((unsigned char)0xB8);
8936 emit_int8((unsigned char)(0xC0 | encode));
8937 }
8938
8939 void Assembler::popq(Address dst) {
8940 InstructionMark im(this);
8941 prefixq(dst);
8942 emit_int8((unsigned char)0x8F);
8943 emit_operand(rax, dst);
8944 }
8945
8946 void Assembler::pusha() { // 64bit
8947 // we have to store original rsp. ABI says that 128 bytes
8948 // below rsp are local scratch.
8949 movq(Address(rsp, -5 * wordSize), rsp);
8950
8951 subq(rsp, 16 * wordSize);
8952
8953 movq(Address(rsp, 15 * wordSize), rax);
8954 movq(Address(rsp, 14 * wordSize), rcx);
8955 movq(Address(rsp, 13 * wordSize), rdx);
8956 movq(Address(rsp, 12 * wordSize), rbx);
8957 // skip rsp
8958 movq(Address(rsp, 10 * wordSize), rbp);
8959 movq(Address(rsp, 9 * wordSize), rsi);
8960 movq(Address(rsp, 8 * wordSize), rdi);
8961 movq(Address(rsp, 7 * wordSize), r8);
8962 movq(Address(rsp, 6 * wordSize), r9);
8963 movq(Address(rsp, 5 * wordSize), r10);
8964 movq(Address(rsp, 4 * wordSize), r11);
8965 movq(Address(rsp, 3 * wordSize), r12);
8966 movq(Address(rsp, 2 * wordSize), r13);
8967 movq(Address(rsp, wordSize), r14);
8968 movq(Address(rsp, 0), r15);
8969 }
8970
8971 void Assembler::pushq(Address src) {
8972 InstructionMark im(this);
8973 prefixq(src);
8974 emit_int8((unsigned char)0xFF);
8975 emit_operand(rsi, src);
8976 }
8977
8978 void Assembler::rclq(Register dst, int imm8) {
8979 assert(isShiftCount(imm8 >> 1), "illegal shift count");
8980 int encode = prefixq_and_encode(dst->encoding());
8981 if (imm8 == 1) {
8982 emit_int8((unsigned char)0xD1);
8983 emit_int8((unsigned char)(0xD0 | encode));
8984 } else {
8985 emit_int8((unsigned char)0xC1);
8986 emit_int8((unsigned char)(0xD0 | encode));
8987 emit_int8(imm8);
8988 }
8989 }
8990
8991 void Assembler::rcrq(Register dst, int imm8) {
8992 assert(isShiftCount(imm8 >> 1), "illegal shift count");
8993 int encode = prefixq_and_encode(dst->encoding());
8994 if (imm8 == 1) {
8995 emit_int8((unsigned char)0xD1);
8996 emit_int8((unsigned char)(0xD8 | encode));
8997 } else {
8998 emit_int8((unsigned char)0xC1);
8999 emit_int8((unsigned char)(0xD8 | encode));
9000 emit_int8(imm8);
9001 }
9002 }
9003
9004 void Assembler::rorq(Register dst, int imm8) {
9005 assert(isShiftCount(imm8 >> 1), "illegal shift count");
9006 int encode = prefixq_and_encode(dst->encoding());
9007 if (imm8 == 1) {
9008 emit_int8((unsigned char)0xD1);
9009 emit_int8((unsigned char)(0xC8 | encode));
9010 } else {
9011 emit_int8((unsigned char)0xC1);
9012 emit_int8((unsigned char)(0xc8 | encode));
9013 emit_int8(imm8);
9014 }
9015 }
9016
9017 void Assembler::rorxq(Register dst, Register src, int imm8) {
9018 assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported");
9019 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
9020 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F_3A, &attributes);
9021 emit_int8((unsigned char)0xF0);
9022 emit_int8((unsigned char)(0xC0 | encode));
9023 emit_int8(imm8);
9024 }
9025
9026 void Assembler::rorxd(Register dst, Register src, int imm8) {
9027 assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported");
9028 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
9029 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F_3A, &attributes);
9030 emit_int8((unsigned char)0xF0);
9031 emit_int8((unsigned char)(0xC0 | encode));
9032 emit_int8(imm8);
9033 }
9034
9035 void Assembler::sarq(Register dst, int imm8) {
9036 assert(isShiftCount(imm8 >> 1), "illegal shift count");
9037 int encode = prefixq_and_encode(dst->encoding());
9038 if (imm8 == 1) {
9039 emit_int8((unsigned char)0xD1);
9040 emit_int8((unsigned char)(0xF8 | encode));
9041 } else {
9042 emit_int8((unsigned char)0xC1);
9043 emit_int8((unsigned char)(0xF8 | encode));
9044 emit_int8(imm8);
9045 }
9046 }
9047
9048 void Assembler::sarq(Register dst) {
9049 int encode = prefixq_and_encode(dst->encoding());
9050 emit_int8((unsigned char)0xD3);
9051 emit_int8((unsigned char)(0xF8 | encode));
9052 }
9053
9054 void Assembler::sbbq(Address dst, int32_t imm32) {
9055 InstructionMark im(this);
9056 prefixq(dst);
9057 emit_arith_operand(0x81, rbx, dst, imm32);
9058 }
9059
9060 void Assembler::sbbq(Register dst, int32_t imm32) {
9061 (void) prefixq_and_encode(dst->encoding());
9062 emit_arith(0x81, 0xD8, dst, imm32);
9063 }
9064
9065 void Assembler::sbbq(Register dst, Address src) {
9066 InstructionMark im(this);
9067 prefixq(src, dst);
9068 emit_int8(0x1B);
9069 emit_operand(dst, src);
9070 }
9071
9072 void Assembler::sbbq(Register dst, Register src) {
9073 (void) prefixq_and_encode(dst->encoding(), src->encoding());
9074 emit_arith(0x1B, 0xC0, dst, src);
9075 }
9076
9077 void Assembler::shlq(Register dst, int imm8) {
9078 assert(isShiftCount(imm8 >> 1), "illegal shift count");
9079 int encode = prefixq_and_encode(dst->encoding());
9080 if (imm8 == 1) {
9081 emit_int8((unsigned char)0xD1);
9082 emit_int8((unsigned char)(0xE0 | encode));
9083 } else {
9084 emit_int8((unsigned char)0xC1);
9085 emit_int8((unsigned char)(0xE0 | encode));
9086 emit_int8(imm8);
9087 }
9088 }
9089
9090 void Assembler::shlq(Register dst) {
9091 int encode = prefixq_and_encode(dst->encoding());
9092 emit_int8((unsigned char)0xD3);
9093 emit_int8((unsigned char)(0xE0 | encode));
9094 }
9095
9096 void Assembler::shrq(Register dst, int imm8) {
9097 assert(isShiftCount(imm8 >> 1), "illegal shift count");
9098 int encode = prefixq_and_encode(dst->encoding());
9099 emit_int8((unsigned char)0xC1);
9100 emit_int8((unsigned char)(0xE8 | encode));
9101 emit_int8(imm8);
9102 }
9103
9104 void Assembler::shrq(Register dst) {
9105 int encode = prefixq_and_encode(dst->encoding());
9106 emit_int8((unsigned char)0xD3);
9107 emit_int8(0xE8 | encode);
9108 }
9109
9110 void Assembler::subq(Address dst, int32_t imm32) {
9111 InstructionMark im(this);
9112 prefixq(dst);
9113 emit_arith_operand(0x81, rbp, dst, imm32);
9114 }
9115
9116 void Assembler::subq(Address dst, Register src) {
9117 InstructionMark im(this);
9118 prefixq(dst, src);
9119 emit_int8(0x29);
9120 emit_operand(src, dst);
9121 }
9122
9123 void Assembler::subq(Register dst, int32_t imm32) {
9124 (void) prefixq_and_encode(dst->encoding());
9125 emit_arith(0x81, 0xE8, dst, imm32);
9126 }
9127
9128 // Force generation of a 4 byte immediate value even if it fits into 8bit
9129 void Assembler::subq_imm32(Register dst, int32_t imm32) {
9130 (void) prefixq_and_encode(dst->encoding());
9131 emit_arith_imm32(0x81, 0xE8, dst, imm32);
9132 }
9133
9134 void Assembler::subq(Register dst, Address src) {
9135 InstructionMark im(this);
9136 prefixq(src, dst);
9137 emit_int8(0x2B);
9138 emit_operand(dst, src);
9139 }
9140
9141 void Assembler::subq(Register dst, Register src) {
9142 (void) prefixq_and_encode(dst->encoding(), src->encoding());
9143 emit_arith(0x2B, 0xC0, dst, src);
9144 }
9145
9146 void Assembler::testq(Register dst, int32_t imm32) {
9147 // not using emit_arith because test
9148 // doesn't support sign-extension of
9149 // 8bit operands
9150 int encode = dst->encoding();
9151 if (encode == 0) {
9152 prefix(REX_W);
9153 emit_int8((unsigned char)0xA9);
9154 } else {
9155 encode = prefixq_and_encode(encode);
9156 emit_int8((unsigned char)0xF7);
9157 emit_int8((unsigned char)(0xC0 | encode));
9158 }
9159 emit_int32(imm32);
9160 }
9161
9162 void Assembler::testq(Register dst, Register src) {
9163 (void) prefixq_and_encode(dst->encoding(), src->encoding());
9164 emit_arith(0x85, 0xC0, dst, src);
9165 }
9166
9167 void Assembler::testq(Register dst, Address src) {
9168 InstructionMark im(this);
9169 prefixq(src, dst);
9170 emit_int8((unsigned char)0x85);
9171 emit_operand(dst, src);
9172 }
9173
9174 void Assembler::xaddq(Address dst, Register src) {
9175 InstructionMark im(this);
9176 prefixq(dst, src);
9177 emit_int8(0x0F);
9178 emit_int8((unsigned char)0xC1);
9179 emit_operand(src, dst);
9180 }
9181
9182 void Assembler::xchgq(Register dst, Address src) {
9183 InstructionMark im(this);
9184 prefixq(src, dst);
9185 emit_int8((unsigned char)0x87);
9186 emit_operand(dst, src);
9187 }
9188
9189 void Assembler::xchgq(Register dst, Register src) {
9190 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
9191 emit_int8((unsigned char)0x87);
9192 emit_int8((unsigned char)(0xc0 | encode));
9193 }
9194
9195 void Assembler::xorq(Register dst, Register src) {
9196 (void) prefixq_and_encode(dst->encoding(), src->encoding());
9197 emit_arith(0x33, 0xC0, dst, src);
9198 }
9199
9200 void Assembler::xorq(Register dst, Address src) {
9201 InstructionMark im(this);
9202 prefixq(src, dst);
9203 emit_int8(0x33);
9204 emit_operand(dst, src);
9205 }
9206
9207 #endif // !LP64