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src/hotspot/cpu/x86/assembler_x86.cpp

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2175   emit_int8((unsigned char)0xF0);
2176 }
2177 
2178 void Assembler::lzcntl(Register dst, Register src) {
2179   assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR");
2180   emit_int8((unsigned char)0xF3);
2181   int encode = prefix_and_encode(dst->encoding(), src->encoding());
2182   emit_int8(0x0F);
2183   emit_int8((unsigned char)0xBD);
2184   emit_int8((unsigned char)(0xC0 | encode));
2185 }
2186 
2187 // Emit mfence instruction
2188 void Assembler::mfence() {
2189   NOT_LP64(assert(VM_Version::supports_sse2(), "unsupported");)
2190   emit_int8(0x0F);
2191   emit_int8((unsigned char)0xAE);
2192   emit_int8((unsigned char)0xF0);
2193 }
2194 








2195 void Assembler::mov(Register dst, Register src) {
2196   LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
2197 }
2198 
2199 void Assembler::movapd(XMMRegister dst, XMMRegister src) {
2200   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2201   int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit;
2202   InstructionAttr attributes(vector_len, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
2203   attributes.set_rex_vex_w_reverted();
2204   int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2205   emit_int8(0x28);
2206   emit_int8((unsigned char)(0xC0 | encode));
2207 }
2208 
2209 void Assembler::movaps(XMMRegister dst, XMMRegister src) {
2210   NOT_LP64(assert(VM_Version::supports_sse(), ""));
2211   int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit;
2212   InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
2213   int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2214   emit_int8(0x28);


8409   int encode = vex_prefix_and_encode(rcx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
8410   emit_int8((unsigned char)0xF3);
8411   emit_int8((unsigned char)(0xC0 | encode));
8412 }
8413 
8414 void Assembler::blsrq(Register dst, Address src) {
8415   assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
8416   InstructionMark im(this);
8417   InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
8418   vex_prefix(src, dst->encoding(), rcx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
8419   emit_int8((unsigned char)0xF3);
8420   emit_operand(rcx, src);
8421 }
8422 
8423 void Assembler::cdqq() {
8424   prefix(REX_W);
8425   emit_int8((unsigned char)0x99);
8426 }
8427 
8428 void Assembler::clflush(Address adr) {
















8429   prefix(adr);

8430   emit_int8(0x0F);
8431   emit_int8((unsigned char)0xAE);

8432   emit_operand(rdi, adr);
8433 }

















8434 
8435 void Assembler::cmovq(Condition cc, Register dst, Register src) {
8436   int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8437   emit_int8(0x0F);
8438   emit_int8(0x40 | cc);
8439   emit_int8((unsigned char)(0xC0 | encode));
8440 }
8441 
8442 void Assembler::cmovq(Condition cc, Register dst, Address src) {
8443   InstructionMark im(this);
8444   prefixq(src, dst);
8445   emit_int8(0x0F);
8446   emit_int8(0x40 | cc);
8447   emit_operand(dst, src);
8448 }
8449 
8450 void Assembler::cmpq(Address dst, int32_t imm32) {
8451   InstructionMark im(this);
8452   prefixq(dst);
8453   emit_int8((unsigned char)0x81);




2175   emit_int8((unsigned char)0xF0);
2176 }
2177 
2178 void Assembler::lzcntl(Register dst, Register src) {
2179   assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR");
2180   emit_int8((unsigned char)0xF3);
2181   int encode = prefix_and_encode(dst->encoding(), src->encoding());
2182   emit_int8(0x0F);
2183   emit_int8((unsigned char)0xBD);
2184   emit_int8((unsigned char)(0xC0 | encode));
2185 }
2186 
2187 // Emit mfence instruction
2188 void Assembler::mfence() {
2189   NOT_LP64(assert(VM_Version::supports_sse2(), "unsupported");)
2190   emit_int8(0x0F);
2191   emit_int8((unsigned char)0xAE);
2192   emit_int8((unsigned char)0xF0);
2193 }
2194 
2195 // Emit sfence instruction
2196 void Assembler::sfence() {
2197   NOT_LP64(assert(VM_Version::supports_sse2(), "unsupported");)
2198   emit_int8(0x0F);
2199   emit_int8((unsigned char)0xAE);
2200   emit_int8((unsigned char)0xF8);
2201 }
2202 
2203 void Assembler::mov(Register dst, Register src) {
2204   LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
2205 }
2206 
2207 void Assembler::movapd(XMMRegister dst, XMMRegister src) {
2208   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2209   int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit;
2210   InstructionAttr attributes(vector_len, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
2211   attributes.set_rex_vex_w_reverted();
2212   int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2213   emit_int8(0x28);
2214   emit_int8((unsigned char)(0xC0 | encode));
2215 }
2216 
2217 void Assembler::movaps(XMMRegister dst, XMMRegister src) {
2218   NOT_LP64(assert(VM_Version::supports_sse(), ""));
2219   int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit;
2220   InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
2221   int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2222   emit_int8(0x28);


8417   int encode = vex_prefix_and_encode(rcx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
8418   emit_int8((unsigned char)0xF3);
8419   emit_int8((unsigned char)(0xC0 | encode));
8420 }
8421 
8422 void Assembler::blsrq(Register dst, Address src) {
8423   assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
8424   InstructionMark im(this);
8425   InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
8426   vex_prefix(src, dst->encoding(), rcx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
8427   emit_int8((unsigned char)0xF3);
8428   emit_operand(rcx, src);
8429 }
8430 
8431 void Assembler::cdqq() {
8432   prefix(REX_W);
8433   emit_int8((unsigned char)0x99);
8434 }
8435 
8436 void Assembler::clflush(Address adr) {
8437   assert(VM_Version::supports_clflush(), "should do");
8438   prefix(adr);
8439   emit_int8(0x0F);
8440   emit_int8((unsigned char)0xAE);
8441   emit_operand(rdi, adr);
8442 }
8443 
8444 #ifdef _LP64
8445 void Assembler::clflushopt(Address adr) {
8446   assert(VM_Version::supports_clflushopt(), "should do!");
8447   // adr should be base reg only with no index or offset
8448   assert(adr.index() == noreg, "index should be noreg");
8449   assert(adr.scale() == Address::no_scale, "scale should be no_scale");
8450   assert(adr.disp() == 0, "displacement should be 0");
8451   // instruction prefix is 0x66
8452   emit_int8(0x66);
8453   prefix(adr);
8454   // opcode family is 0x0f 0xAE
8455   emit_int8(0x0F);
8456   emit_int8((unsigned char)0xAE);
8457   // extended opcode byte is 7 == rdi
8458   emit_operand(rdi, adr);
8459 }
8460 
8461 void Assembler::clwb(Address adr) {
8462   assert(VM_Version::supports_clwb(), "should do!");
8463   // adr should be base reg only with no index or offset
8464   assert(adr.index() == noreg, "index should be noreg");
8465   assert(adr.scale() == Address::no_scale, "scale should be no_scale");
8466   assert(adr.disp() == 0, "displacement should be 0");
8467   // instruction prefix is 0x66
8468   emit_int8(0x66);
8469   prefix(adr);
8470   // opcode family is 0x0f 0xAE
8471   emit_int8(0x0F);
8472   emit_int8((unsigned char)0xAE);
8473   // extended opcode byte is 6 == rsi
8474   emit_operand(rsi, adr);
8475 }
8476 #endif
8477 
8478 void Assembler::cmovq(Condition cc, Register dst, Register src) {
8479   int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8480   emit_int8(0x0F);
8481   emit_int8(0x40 | cc);
8482   emit_int8((unsigned char)(0xC0 | encode));
8483 }
8484 
8485 void Assembler::cmovq(Condition cc, Register dst, Address src) {
8486   InstructionMark im(this);
8487   prefixq(src, dst);
8488   emit_int8(0x0F);
8489   emit_int8(0x40 | cc);
8490   emit_operand(dst, src);
8491 }
8492 
8493 void Assembler::cmpq(Address dst, int32_t imm32) {
8494   InstructionMark im(this);
8495   prefixq(dst);
8496   emit_int8((unsigned char)0x81);


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