1 /*
2 * Copyright (c) 1997, 2018, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
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23 */
24
25 #ifndef CPU_X86_VM_MACROASSEMBLER_X86_HPP
26 #define CPU_X86_VM_MACROASSEMBLER_X86_HPP
27
28 #include "asm/assembler.hpp"
29 #include "utilities/macros.hpp"
30 #include "runtime/rtmLocking.hpp"
31
32 // MacroAssembler extends Assembler by frequently used macros.
33 //
34 // Instructions for which a 'better' code sequence exists depending
35 // on arguments should also go in here.
36
37 class MacroAssembler: public Assembler {
38 friend class LIR_Assembler;
39 friend class Runtime1; // as_Address()
40
41 public:
42 // Support for VM calls
43 //
44 // This is the base routine called by the different versions of call_VM_leaf. The interpreter
45 // may customize this version by overriding it for its purposes (e.g., to save/restore
46 // additional registers when doing a VM call).
47
48 virtual void call_VM_leaf_base(
49 address entry_point, // the entry point
50 int number_of_arguments // the number of arguments to pop after the call
51 );
52
53 protected:
54 // This is the base routine called by the different versions of call_VM. The interpreter
55 // may customize this version by overriding it for its purposes (e.g., to save/restore
56 // additional registers when doing a VM call).
57 //
58 // If no java_thread register is specified (noreg) than rdi will be used instead. call_VM_base
59 // returns the register which contains the thread upon return. If a thread register has been
60 // specified, the return value will correspond to that register. If no last_java_sp is specified
61 // (noreg) than rsp will be used instead.
62 virtual void call_VM_base( // returns the register containing the thread upon return
63 Register oop_result, // where an oop-result ends up if any; use noreg otherwise
64 Register java_thread, // the thread if computed before ; use noreg otherwise
65 Register last_java_sp, // to set up last_Java_frame in stubs; use noreg otherwise
66 address entry_point, // the entry point
67 int number_of_arguments, // the number of arguments (w/o thread) to pop after the call
68 bool check_exceptions // whether to check for pending exceptions after return
69 );
70
71 void call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions = true);
72
73 // helpers for FPU flag access
74 // tmp is a temporary register, if none is available use noreg
75 void save_rax (Register tmp);
76 void restore_rax(Register tmp);
77
78 public:
79 MacroAssembler(CodeBuffer* code) : Assembler(code) {}
80
81 // These routines should emit JVMTI PopFrame and ForceEarlyReturn handling code.
82 // The implementation is only non-empty for the InterpreterMacroAssembler,
83 // as only the interpreter handles PopFrame and ForceEarlyReturn requests.
84 virtual void check_and_handle_popframe(Register java_thread);
85 virtual void check_and_handle_earlyret(Register java_thread);
86
87 Address as_Address(AddressLiteral adr);
88 Address as_Address(ArrayAddress adr);
89
90 // Support for NULL-checks
91 //
92 // Generates code that causes a NULL OS exception if the content of reg is NULL.
93 // If the accessed location is M[reg + offset] and the offset is known, provide the
94 // offset. No explicit code generation is needed if the offset is within a certain
95 // range (0 <= offset <= page_size).
96
97 void null_check(Register reg, int offset = -1);
98 static bool needs_explicit_null_check(intptr_t offset);
99
100 // Required platform-specific helpers for Label::patch_instructions.
101 // They _shadow_ the declarations in AbstractAssembler, which are undefined.
102 void pd_patch_instruction(address branch, address target) {
103 unsigned char op = branch[0];
104 assert(op == 0xE8 /* call */ ||
105 op == 0xE9 /* jmp */ ||
106 op == 0xEB /* short jmp */ ||
107 (op & 0xF0) == 0x70 /* short jcc */ ||
108 op == 0x0F && (branch[1] & 0xF0) == 0x80 /* jcc */ ||
109 op == 0xC7 && branch[1] == 0xF8 /* xbegin */,
110 "Invalid opcode at patch point");
111
112 if (op == 0xEB || (op & 0xF0) == 0x70) {
113 // short offset operators (jmp and jcc)
114 char* disp = (char*) &branch[1];
115 int imm8 = target - (address) &disp[1];
116 guarantee(this->is8bit(imm8), "Short forward jump exceeds 8-bit offset");
117 *disp = imm8;
118 } else {
119 int* disp = (int*) &branch[(op == 0x0F || op == 0xC7)? 2: 1];
120 int imm32 = target - (address) &disp[1];
121 *disp = imm32;
122 }
123 }
124
125 // The following 4 methods return the offset of the appropriate move instruction
126
127 // Support for fast byte/short loading with zero extension (depending on particular CPU)
128 int load_unsigned_byte(Register dst, Address src);
129 int load_unsigned_short(Register dst, Address src);
130
131 // Support for fast byte/short loading with sign extension (depending on particular CPU)
132 int load_signed_byte(Register dst, Address src);
133 int load_signed_short(Register dst, Address src);
134
135 // Support for sign-extension (hi:lo = extend_sign(lo))
136 void extend_sign(Register hi, Register lo);
137
138 // Load and store values by size and signed-ness
139 void load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2 = noreg);
140 void store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2 = noreg);
141
142 // Support for inc/dec with optimal instruction selection depending on value
143
144 void increment(Register reg, int value = 1) { LP64_ONLY(incrementq(reg, value)) NOT_LP64(incrementl(reg, value)) ; }
145 void decrement(Register reg, int value = 1) { LP64_ONLY(decrementq(reg, value)) NOT_LP64(decrementl(reg, value)) ; }
146
147 void decrementl(Address dst, int value = 1);
148 void decrementl(Register reg, int value = 1);
149
150 void decrementq(Register reg, int value = 1);
151 void decrementq(Address dst, int value = 1);
152
153 void incrementl(Address dst, int value = 1);
154 void incrementl(Register reg, int value = 1);
155
156 void incrementq(Register reg, int value = 1);
157 void incrementq(Address dst, int value = 1);
158
159 // special instructions for EVEX
160 void setvectmask(Register dst, Register src);
161 void restorevectmask();
162
163 // Support optimal SSE move instructions.
164 void movflt(XMMRegister dst, XMMRegister src) {
165 if (UseXmmRegToRegMoveAll) { movaps(dst, src); return; }
166 else { movss (dst, src); return; }
167 }
168 void movflt(XMMRegister dst, Address src) { movss(dst, src); }
169 void movflt(XMMRegister dst, AddressLiteral src);
170 void movflt(Address dst, XMMRegister src) { movss(dst, src); }
171
172 void movdbl(XMMRegister dst, XMMRegister src) {
173 if (UseXmmRegToRegMoveAll) { movapd(dst, src); return; }
174 else { movsd (dst, src); return; }
175 }
176
177 void movdbl(XMMRegister dst, AddressLiteral src);
178
179 void movdbl(XMMRegister dst, Address src) {
180 if (UseXmmLoadAndClearUpper) { movsd (dst, src); return; }
181 else { movlpd(dst, src); return; }
182 }
183 void movdbl(Address dst, XMMRegister src) { movsd(dst, src); }
184
185 void incrementl(AddressLiteral dst);
186 void incrementl(ArrayAddress dst);
187
188 void incrementq(AddressLiteral dst);
189
190 // Alignment
191 void align(int modulus);
192 void align(int modulus, int target);
193
194 // A 5 byte nop that is safe for patching (see patch_verified_entry)
195 void fat_nop();
196
197 // Stack frame creation/removal
198 void enter();
199 void leave();
200
201 // Support for getting the JavaThread pointer (i.e.; a reference to thread-local information)
202 // The pointer will be loaded into the thread register.
203 void get_thread(Register thread);
204
205
206 // Support for VM calls
207 //
208 // It is imperative that all calls into the VM are handled via the call_VM macros.
209 // They make sure that the stack linkage is setup correctly. call_VM's correspond
210 // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points.
211
212
213 void call_VM(Register oop_result,
214 address entry_point,
215 bool check_exceptions = true);
216 void call_VM(Register oop_result,
217 address entry_point,
218 Register arg_1,
219 bool check_exceptions = true);
220 void call_VM(Register oop_result,
221 address entry_point,
222 Register arg_1, Register arg_2,
223 bool check_exceptions = true);
224 void call_VM(Register oop_result,
225 address entry_point,
226 Register arg_1, Register arg_2, Register arg_3,
227 bool check_exceptions = true);
228
229 // Overloadings with last_Java_sp
230 void call_VM(Register oop_result,
231 Register last_java_sp,
232 address entry_point,
233 int number_of_arguments = 0,
234 bool check_exceptions = true);
235 void call_VM(Register oop_result,
236 Register last_java_sp,
237 address entry_point,
238 Register arg_1, bool
239 check_exceptions = true);
240 void call_VM(Register oop_result,
241 Register last_java_sp,
242 address entry_point,
243 Register arg_1, Register arg_2,
244 bool check_exceptions = true);
245 void call_VM(Register oop_result,
246 Register last_java_sp,
247 address entry_point,
248 Register arg_1, Register arg_2, Register arg_3,
249 bool check_exceptions = true);
250
251 void get_vm_result (Register oop_result, Register thread);
252 void get_vm_result_2(Register metadata_result, Register thread);
253
254 // These always tightly bind to MacroAssembler::call_VM_base
255 // bypassing the virtual implementation
256 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments = 0, bool check_exceptions = true);
257 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions = true);
258 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true);
259 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true);
260 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4, bool check_exceptions = true);
261
262 void call_VM_leaf0(address entry_point);
263 void call_VM_leaf(address entry_point,
264 int number_of_arguments = 0);
265 void call_VM_leaf(address entry_point,
266 Register arg_1);
267 void call_VM_leaf(address entry_point,
268 Register arg_1, Register arg_2);
269 void call_VM_leaf(address entry_point,
270 Register arg_1, Register arg_2, Register arg_3);
271
272 // These always tightly bind to MacroAssembler::call_VM_leaf_base
273 // bypassing the virtual implementation
274 void super_call_VM_leaf(address entry_point);
275 void super_call_VM_leaf(address entry_point, Register arg_1);
276 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2);
277 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3);
278 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4);
279
280 // last Java Frame (fills frame anchor)
281 void set_last_Java_frame(Register thread,
282 Register last_java_sp,
283 Register last_java_fp,
284 address last_java_pc);
285
286 // thread in the default location (r15_thread on 64bit)
287 void set_last_Java_frame(Register last_java_sp,
288 Register last_java_fp,
289 address last_java_pc);
290
291 void reset_last_Java_frame(Register thread, bool clear_fp);
292
293 // thread in the default location (r15_thread on 64bit)
294 void reset_last_Java_frame(bool clear_fp);
295
296 // jobjects
297 void clear_jweak_tag(Register possibly_jweak);
298 void resolve_jobject(Register value, Register thread, Register tmp);
299
300 // C 'boolean' to Java boolean: x == 0 ? 0 : 1
301 void c2bool(Register x);
302
303 // C++ bool manipulation
304
305 void movbool(Register dst, Address src);
306 void movbool(Address dst, bool boolconst);
307 void movbool(Address dst, Register src);
308 void testbool(Register dst);
309
310 void resolve_oop_handle(Register result, Register tmp = rscratch2);
311 void load_mirror(Register mirror, Register method, Register tmp = rscratch2);
312
313 // oop manipulations
314 void load_klass(Register dst, Register src);
315 void store_klass(Register dst, Register src);
316
317 void access_load_at(BasicType type, DecoratorSet decorators, Register dst, Address src,
318 Register tmp1, Register thread_tmp);
319 void access_store_at(BasicType type, DecoratorSet decorators, Address dst, Register src,
320 Register tmp1, Register tmp2);
321
322 // Resolves obj access. Result is placed in the same register.
323 // All other registers are preserved.
324 void resolve(DecoratorSet decorators, Register obj);
325
326 void load_heap_oop(Register dst, Address src, Register tmp1 = noreg,
327 Register thread_tmp = noreg, DecoratorSet decorators = 0);
328 void load_heap_oop_not_null(Register dst, Address src, Register tmp1 = noreg,
329 Register thread_tmp = noreg, DecoratorSet decorators = 0);
330 void store_heap_oop(Address dst, Register src, Register tmp1 = noreg,
331 Register tmp2 = noreg, DecoratorSet decorators = 0);
332
333 // Used for storing NULL. All other oop constants should be
334 // stored using routines that take a jobject.
335 void store_heap_oop_null(Address dst);
336
337 void load_prototype_header(Register dst, Register src);
338
339 #ifdef _LP64
340 void store_klass_gap(Register dst, Register src);
341
342 // This dummy is to prevent a call to store_heap_oop from
343 // converting a zero (like NULL) into a Register by giving
344 // the compiler two choices it can't resolve
345
346 void store_heap_oop(Address dst, void* dummy);
347
348 void encode_heap_oop(Register r);
349 void decode_heap_oop(Register r);
350 void encode_heap_oop_not_null(Register r);
351 void decode_heap_oop_not_null(Register r);
352 void encode_heap_oop_not_null(Register dst, Register src);
353 void decode_heap_oop_not_null(Register dst, Register src);
354
355 void set_narrow_oop(Register dst, jobject obj);
356 void set_narrow_oop(Address dst, jobject obj);
357 void cmp_narrow_oop(Register dst, jobject obj);
358 void cmp_narrow_oop(Address dst, jobject obj);
359
360 void encode_klass_not_null(Register r);
361 void decode_klass_not_null(Register r);
362 void encode_klass_not_null(Register dst, Register src);
363 void decode_klass_not_null(Register dst, Register src);
364 void set_narrow_klass(Register dst, Klass* k);
365 void set_narrow_klass(Address dst, Klass* k);
366 void cmp_narrow_klass(Register dst, Klass* k);
367 void cmp_narrow_klass(Address dst, Klass* k);
368
369 // Returns the byte size of the instructions generated by decode_klass_not_null()
370 // when compressed klass pointers are being used.
371 static int instr_size_for_decode_klass_not_null();
372
373 // if heap base register is used - reinit it with the correct value
374 void reinit_heapbase();
375
376 DEBUG_ONLY(void verify_heapbase(const char* msg);)
377
378 #endif // _LP64
379
380 // Int division/remainder for Java
381 // (as idivl, but checks for special case as described in JVM spec.)
382 // returns idivl instruction offset for implicit exception handling
383 int corrected_idivl(Register reg);
384
385 // Long division/remainder for Java
386 // (as idivq, but checks for special case as described in JVM spec.)
387 // returns idivq instruction offset for implicit exception handling
388 int corrected_idivq(Register reg);
389
390 void int3();
391
392 // Long operation macros for a 32bit cpu
393 // Long negation for Java
394 void lneg(Register hi, Register lo);
395
396 // Long multiplication for Java
397 // (destroys contents of eax, ebx, ecx and edx)
398 void lmul(int x_rsp_offset, int y_rsp_offset); // rdx:rax = x * y
399
400 // Long shifts for Java
401 // (semantics as described in JVM spec.)
402 void lshl(Register hi, Register lo); // hi:lo << (rcx & 0x3f)
403 void lshr(Register hi, Register lo, bool sign_extension = false); // hi:lo >> (rcx & 0x3f)
404
405 // Long compare for Java
406 // (semantics as described in JVM spec.)
407 void lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo); // x_hi = lcmp(x, y)
408
409
410 // misc
411
412 // Sign extension
413 void sign_extend_short(Register reg);
414 void sign_extend_byte(Register reg);
415
416 // Division by power of 2, rounding towards 0
417 void division_with_shift(Register reg, int shift_value);
418
419 // Compares the top-most stack entries on the FPU stack and sets the eflags as follows:
420 //
421 // CF (corresponds to C0) if x < y
422 // PF (corresponds to C2) if unordered
423 // ZF (corresponds to C3) if x = y
424 //
425 // The arguments are in reversed order on the stack (i.e., top of stack is first argument).
426 // tmp is a temporary register, if none is available use noreg (only matters for non-P6 code)
427 void fcmp(Register tmp);
428 // Variant of the above which allows y to be further down the stack
429 // and which only pops x and y if specified. If pop_right is
430 // specified then pop_left must also be specified.
431 void fcmp(Register tmp, int index, bool pop_left, bool pop_right);
432
433 // Floating-point comparison for Java
434 // Compares the top-most stack entries on the FPU stack and stores the result in dst.
435 // The arguments are in reversed order on the stack (i.e., top of stack is first argument).
436 // (semantics as described in JVM spec.)
437 void fcmp2int(Register dst, bool unordered_is_less);
438 // Variant of the above which allows y to be further down the stack
439 // and which only pops x and y if specified. If pop_right is
440 // specified then pop_left must also be specified.
441 void fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right);
442
443 // Floating-point remainder for Java (ST0 = ST0 fremr ST1, ST1 is empty afterwards)
444 // tmp is a temporary register, if none is available use noreg
445 void fremr(Register tmp);
446
447 // dst = c = a * b + c
448 void fmad(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c);
449 void fmaf(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c);
450
451 void vfmad(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c, int vector_len);
452 void vfmaf(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c, int vector_len);
453 void vfmad(XMMRegister dst, XMMRegister a, Address b, XMMRegister c, int vector_len);
454 void vfmaf(XMMRegister dst, XMMRegister a, Address b, XMMRegister c, int vector_len);
455
456
457 // same as fcmp2int, but using SSE2
458 void cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less);
459 void cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less);
460
461 // branch to L if FPU flag C2 is set/not set
462 // tmp is a temporary register, if none is available use noreg
463 void jC2 (Register tmp, Label& L);
464 void jnC2(Register tmp, Label& L);
465
466 // Pop ST (ffree & fincstp combined)
467 void fpop();
468
469 // Load float value from 'address'. If UseSSE >= 1, the value is loaded into
470 // register xmm0. Otherwise, the value is loaded onto the FPU stack.
471 void load_float(Address src);
472
473 // Store float value to 'address'. If UseSSE >= 1, the value is stored
474 // from register xmm0. Otherwise, the value is stored from the FPU stack.
475 void store_float(Address dst);
476
477 // Load double value from 'address'. If UseSSE >= 2, the value is loaded into
478 // register xmm0. Otherwise, the value is loaded onto the FPU stack.
479 void load_double(Address src);
480
481 // Store double value to 'address'. If UseSSE >= 2, the value is stored
482 // from register xmm0. Otherwise, the value is stored from the FPU stack.
483 void store_double(Address dst);
484
485 // pushes double TOS element of FPU stack on CPU stack; pops from FPU stack
486 void push_fTOS();
487
488 // pops double TOS element from CPU stack and pushes on FPU stack
489 void pop_fTOS();
490
491 void empty_FPU_stack();
492
493 void push_IU_state();
494 void pop_IU_state();
495
496 void push_FPU_state();
497 void pop_FPU_state();
498
499 void push_CPU_state();
500 void pop_CPU_state();
501
502 // Round up to a power of two
503 void round_to(Register reg, int modulus);
504
505 // Callee saved registers handling
506 void push_callee_saved_registers();
507 void pop_callee_saved_registers();
508
509 // allocation
510 void eden_allocate(
511 Register thread, // Current thread
512 Register obj, // result: pointer to object after successful allocation
513 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
514 int con_size_in_bytes, // object size in bytes if known at compile time
515 Register t1, // temp register
516 Label& slow_case // continuation point if fast allocation fails
517 );
518 void tlab_allocate(
519 Register thread, // Current thread
520 Register obj, // result: pointer to object after successful allocation
521 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
522 int con_size_in_bytes, // object size in bytes if known at compile time
523 Register t1, // temp register
524 Register t2, // temp register
525 Label& slow_case // continuation point if fast allocation fails
526 );
527 void zero_memory(Register address, Register length_in_bytes, int offset_in_bytes, Register temp);
528
529 // interface method calling
530 void lookup_interface_method(Register recv_klass,
531 Register intf_klass,
532 RegisterOrConstant itable_index,
533 Register method_result,
534 Register scan_temp,
535 Label& no_such_interface,
536 bool return_method = true);
537
538 // virtual method calling
539 void lookup_virtual_method(Register recv_klass,
540 RegisterOrConstant vtable_index,
541 Register method_result);
542
543 // Test sub_klass against super_klass, with fast and slow paths.
544
545 // The fast path produces a tri-state answer: yes / no / maybe-slow.
546 // One of the three labels can be NULL, meaning take the fall-through.
547 // If super_check_offset is -1, the value is loaded up from super_klass.
548 // No registers are killed, except temp_reg.
549 void check_klass_subtype_fast_path(Register sub_klass,
550 Register super_klass,
551 Register temp_reg,
552 Label* L_success,
553 Label* L_failure,
554 Label* L_slow_path,
555 RegisterOrConstant super_check_offset = RegisterOrConstant(-1));
556
557 // The rest of the type check; must be wired to a corresponding fast path.
558 // It does not repeat the fast path logic, so don't use it standalone.
559 // The temp_reg and temp2_reg can be noreg, if no temps are available.
560 // Updates the sub's secondary super cache as necessary.
561 // If set_cond_codes, condition codes will be Z on success, NZ on failure.
562 void check_klass_subtype_slow_path(Register sub_klass,
563 Register super_klass,
564 Register temp_reg,
565 Register temp2_reg,
566 Label* L_success,
567 Label* L_failure,
568 bool set_cond_codes = false);
569
570 // Simplified, combined version, good for typical uses.
571 // Falls through on failure.
572 void check_klass_subtype(Register sub_klass,
573 Register super_klass,
574 Register temp_reg,
575 Label& L_success);
576
577 // method handles (JSR 292)
578 Address argument_address(RegisterOrConstant arg_slot, int extra_slot_offset = 0);
579
580 //----
581 void set_word_if_not_zero(Register reg); // sets reg to 1 if not zero, otherwise 0
582
583 // Debugging
584
585 // only if +VerifyOops
586 // TODO: Make these macros with file and line like sparc version!
587 void verify_oop(Register reg, const char* s = "broken oop");
588 void verify_oop_addr(Address addr, const char * s = "broken oop addr");
589
590 // TODO: verify method and klass metadata (compare against vptr?)
591 void _verify_method_ptr(Register reg, const char * msg, const char * file, int line) {}
592 void _verify_klass_ptr(Register reg, const char * msg, const char * file, int line){}
593
594 #define verify_method_ptr(reg) _verify_method_ptr(reg, "broken method " #reg, __FILE__, __LINE__)
595 #define verify_klass_ptr(reg) _verify_klass_ptr(reg, "broken klass " #reg, __FILE__, __LINE__)
596
597 // only if +VerifyFPU
598 void verify_FPU(int stack_depth, const char* s = "illegal FPU state");
599
600 // Verify or restore cpu control state after JNI call
601 void restore_cpu_control_state_after_jni();
602
603 // prints msg, dumps registers and stops execution
604 void stop(const char* msg);
605
606 // prints msg and continues
607 void warn(const char* msg);
608
609 // dumps registers and other state
610 void print_state();
611
612 static void debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg);
613 static void debug64(char* msg, int64_t pc, int64_t regs[]);
614 static void print_state32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip);
615 static void print_state64(int64_t pc, int64_t regs[]);
616
617 void os_breakpoint();
618
619 void untested() { stop("untested"); }
620
621 void unimplemented(const char* what = "");
622
623 void should_not_reach_here() { stop("should not reach here"); }
624
625 void print_CPU_state();
626
627 // Stack overflow checking
628 void bang_stack_with_offset(int offset) {
629 // stack grows down, caller passes positive offset
630 assert(offset > 0, "must bang with negative offset");
631 movl(Address(rsp, (-offset)), rax);
632 }
633
634 // Writes to stack successive pages until offset reached to check for
635 // stack overflow + shadow pages. Also, clobbers tmp
636 void bang_stack_size(Register size, Register tmp);
637
638 // Check for reserved stack access in method being exited (for JIT)
639 void reserved_stack_check();
640
641 virtual RegisterOrConstant delayed_value_impl(intptr_t* delayed_value_addr,
642 Register tmp,
643 int offset);
644
645 // Support for serializing memory accesses between threads
646 void serialize_memory(Register thread, Register tmp);
647
648 // If thread_reg is != noreg the code assumes the register passed contains
649 // the thread (required on 64 bit).
650 void safepoint_poll(Label& slow_path, Register thread_reg, Register temp_reg);
651
652 void verify_tlab();
653
654 // Biased locking support
655 // lock_reg and obj_reg must be loaded up with the appropriate values.
656 // swap_reg must be rax, and is killed.
657 // tmp_reg is optional. If it is supplied (i.e., != noreg) it will
658 // be killed; if not supplied, push/pop will be used internally to
659 // allocate a temporary (inefficient, avoid if possible).
660 // Optional slow case is for implementations (interpreter and C1) which branch to
661 // slow case directly. Leaves condition codes set for C2's Fast_Lock node.
662 // Returns offset of first potentially-faulting instruction for null
663 // check info (currently consumed only by C1). If
664 // swap_reg_contains_mark is true then returns -1 as it is assumed
665 // the calling code has already passed any potential faults.
666 int biased_locking_enter(Register lock_reg, Register obj_reg,
667 Register swap_reg, Register tmp_reg,
668 bool swap_reg_contains_mark,
669 Label& done, Label* slow_case = NULL,
670 BiasedLockingCounters* counters = NULL);
671 void biased_locking_exit (Register obj_reg, Register temp_reg, Label& done);
672 #ifdef COMPILER2
673 // Code used by cmpFastLock and cmpFastUnlock mach instructions in .ad file.
674 // See full desription in macroAssembler_x86.cpp.
675 void fast_lock(Register obj, Register box, Register tmp,
676 Register scr, Register cx1, Register cx2,
677 BiasedLockingCounters* counters,
678 RTMLockingCounters* rtm_counters,
679 RTMLockingCounters* stack_rtm_counters,
680 Metadata* method_data,
681 bool use_rtm, bool profile_rtm);
682 void fast_unlock(Register obj, Register box, Register tmp, bool use_rtm);
683 #if INCLUDE_RTM_OPT
684 void rtm_counters_update(Register abort_status, Register rtm_counters);
685 void branch_on_random_using_rdtsc(Register tmp, Register scr, int count, Label& brLabel);
686 void rtm_abort_ratio_calculation(Register tmp, Register rtm_counters_reg,
687 RTMLockingCounters* rtm_counters,
688 Metadata* method_data);
689 void rtm_profiling(Register abort_status_Reg, Register rtm_counters_Reg,
690 RTMLockingCounters* rtm_counters, Metadata* method_data, bool profile_rtm);
691 void rtm_retry_lock_on_abort(Register retry_count, Register abort_status, Label& retryLabel);
692 void rtm_retry_lock_on_busy(Register retry_count, Register box, Register tmp, Register scr, Label& retryLabel);
693 void rtm_stack_locking(Register obj, Register tmp, Register scr,
694 Register retry_on_abort_count,
695 RTMLockingCounters* stack_rtm_counters,
696 Metadata* method_data, bool profile_rtm,
697 Label& DONE_LABEL, Label& IsInflated);
698 void rtm_inflated_locking(Register obj, Register box, Register tmp,
699 Register scr, Register retry_on_busy_count,
700 Register retry_on_abort_count,
701 RTMLockingCounters* rtm_counters,
702 Metadata* method_data, bool profile_rtm,
703 Label& DONE_LABEL);
704 #endif
705 #endif
706
707 Condition negate_condition(Condition cond);
708
709 // Instructions that use AddressLiteral operands. These instruction can handle 32bit/64bit
710 // operands. In general the names are modified to avoid hiding the instruction in Assembler
711 // so that we don't need to implement all the varieties in the Assembler with trivial wrappers
712 // here in MacroAssembler. The major exception to this rule is call
713
714 // Arithmetics
715
716
717 void addptr(Address dst, int32_t src) { LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)) ; }
718 void addptr(Address dst, Register src);
719
720 void addptr(Register dst, Address src) { LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)); }
721 void addptr(Register dst, int32_t src);
722 void addptr(Register dst, Register src);
723 void addptr(Register dst, RegisterOrConstant src) {
724 if (src.is_constant()) addptr(dst, (int) src.as_constant());
725 else addptr(dst, src.as_register());
726 }
727
728 void andptr(Register dst, int32_t src);
729 void andptr(Register src1, Register src2) { LP64_ONLY(andq(src1, src2)) NOT_LP64(andl(src1, src2)) ; }
730
731 void cmp8(AddressLiteral src1, int imm);
732
733 // renamed to drag out the casting of address to int32_t/intptr_t
734 void cmp32(Register src1, int32_t imm);
735
736 void cmp32(AddressLiteral src1, int32_t imm);
737 // compare reg - mem, or reg - &mem
738 void cmp32(Register src1, AddressLiteral src2);
739
740 void cmp32(Register src1, Address src2);
741
742 #ifndef _LP64
743 void cmpklass(Address dst, Metadata* obj);
744 void cmpklass(Register dst, Metadata* obj);
745 void cmpoop(Address dst, jobject obj);
746 void cmpoop_raw(Address dst, jobject obj);
747 #endif // _LP64
748
749 void cmpoop(Register src1, Register src2);
750 void cmpoop(Register src1, Address src2);
751 void cmpoop(Register dst, jobject obj);
752 void cmpoop_raw(Register dst, jobject obj);
753
754 // NOTE src2 must be the lval. This is NOT an mem-mem compare
755 void cmpptr(Address src1, AddressLiteral src2);
756
757 void cmpptr(Register src1, AddressLiteral src2);
758
759 void cmpptr(Register src1, Register src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
760 void cmpptr(Register src1, Address src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
761 // void cmpptr(Address src1, Register src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
762
763 void cmpptr(Register src1, int32_t src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
764 void cmpptr(Address src1, int32_t src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
765
766 // cmp64 to avoild hiding cmpq
767 void cmp64(Register src1, AddressLiteral src);
768
769 void cmpxchgptr(Register reg, Address adr);
770
771 void locked_cmpxchgptr(Register reg, AddressLiteral adr);
772
773
774 void imulptr(Register dst, Register src) { LP64_ONLY(imulq(dst, src)) NOT_LP64(imull(dst, src)); }
775 void imulptr(Register dst, Register src, int imm32) { LP64_ONLY(imulq(dst, src, imm32)) NOT_LP64(imull(dst, src, imm32)); }
776
777
778 void negptr(Register dst) { LP64_ONLY(negq(dst)) NOT_LP64(negl(dst)); }
779
780 void notptr(Register dst) { LP64_ONLY(notq(dst)) NOT_LP64(notl(dst)); }
781
782 void shlptr(Register dst, int32_t shift);
783 void shlptr(Register dst) { LP64_ONLY(shlq(dst)) NOT_LP64(shll(dst)); }
784
785 void shrptr(Register dst, int32_t shift);
786 void shrptr(Register dst) { LP64_ONLY(shrq(dst)) NOT_LP64(shrl(dst)); }
787
788 void sarptr(Register dst) { LP64_ONLY(sarq(dst)) NOT_LP64(sarl(dst)); }
789 void sarptr(Register dst, int32_t src) { LP64_ONLY(sarq(dst, src)) NOT_LP64(sarl(dst, src)); }
790
791 void subptr(Address dst, int32_t src) { LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); }
792
793 void subptr(Register dst, Address src) { LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); }
794 void subptr(Register dst, int32_t src);
795 // Force generation of a 4 byte immediate value even if it fits into 8bit
796 void subptr_imm32(Register dst, int32_t src);
797 void subptr(Register dst, Register src);
798 void subptr(Register dst, RegisterOrConstant src) {
799 if (src.is_constant()) subptr(dst, (int) src.as_constant());
800 else subptr(dst, src.as_register());
801 }
802
803 void sbbptr(Address dst, int32_t src) { LP64_ONLY(sbbq(dst, src)) NOT_LP64(sbbl(dst, src)); }
804 void sbbptr(Register dst, int32_t src) { LP64_ONLY(sbbq(dst, src)) NOT_LP64(sbbl(dst, src)); }
805
806 void xchgptr(Register src1, Register src2) { LP64_ONLY(xchgq(src1, src2)) NOT_LP64(xchgl(src1, src2)) ; }
807 void xchgptr(Register src1, Address src2) { LP64_ONLY(xchgq(src1, src2)) NOT_LP64(xchgl(src1, src2)) ; }
808
809 void xaddptr(Address src1, Register src2) { LP64_ONLY(xaddq(src1, src2)) NOT_LP64(xaddl(src1, src2)) ; }
810
811
812
813 // Helper functions for statistics gathering.
814 // Conditionally (atomically, on MPs) increments passed counter address, preserving condition codes.
815 void cond_inc32(Condition cond, AddressLiteral counter_addr);
816 // Unconditional atomic increment.
817 void atomic_incl(Address counter_addr);
818 void atomic_incl(AddressLiteral counter_addr, Register scr = rscratch1);
819 #ifdef _LP64
820 void atomic_incq(Address counter_addr);
821 void atomic_incq(AddressLiteral counter_addr, Register scr = rscratch1);
822 #endif
823 void atomic_incptr(AddressLiteral counter_addr, Register scr = rscratch1) { LP64_ONLY(atomic_incq(counter_addr, scr)) NOT_LP64(atomic_incl(counter_addr, scr)) ; }
824 void atomic_incptr(Address counter_addr) { LP64_ONLY(atomic_incq(counter_addr)) NOT_LP64(atomic_incl(counter_addr)) ; }
825
826 void lea(Register dst, AddressLiteral adr);
827 void lea(Address dst, AddressLiteral adr);
828 void lea(Register dst, Address adr) { Assembler::lea(dst, adr); }
829
830 void leal32(Register dst, Address src) { leal(dst, src); }
831
832 // Import other testl() methods from the parent class or else
833 // they will be hidden by the following overriding declaration.
834 using Assembler::testl;
835 void testl(Register dst, AddressLiteral src);
836
837 void orptr(Register dst, Address src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
838 void orptr(Register dst, Register src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
839 void orptr(Register dst, int32_t src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
840 void orptr(Address dst, int32_t imm32) { LP64_ONLY(orq(dst, imm32)) NOT_LP64(orl(dst, imm32)); }
841
842 void testptr(Register src, int32_t imm32) { LP64_ONLY(testq(src, imm32)) NOT_LP64(testl(src, imm32)); }
843 void testptr(Register src1, Address src2) { LP64_ONLY(testq(src1, src2)) NOT_LP64(testl(src1, src2)); }
844 void testptr(Register src1, Register src2);
845
846 void xorptr(Register dst, Register src) { LP64_ONLY(xorq(dst, src)) NOT_LP64(xorl(dst, src)); }
847 void xorptr(Register dst, Address src) { LP64_ONLY(xorq(dst, src)) NOT_LP64(xorl(dst, src)); }
848
849 // Calls
850
851 void call(Label& L, relocInfo::relocType rtype);
852 void call(Register entry);
853
854 // NOTE: this call transfers to the effective address of entry NOT
855 // the address contained by entry. This is because this is more natural
856 // for jumps/calls.
857 void call(AddressLiteral entry);
858
859 // Emit the CompiledIC call idiom
860 void ic_call(address entry, jint method_index = 0);
861
862 // Jumps
863
864 // NOTE: these jumps tranfer to the effective address of dst NOT
865 // the address contained by dst. This is because this is more natural
866 // for jumps/calls.
867 void jump(AddressLiteral dst);
868 void jump_cc(Condition cc, AddressLiteral dst);
869
870 // 32bit can do a case table jump in one instruction but we no longer allow the base
871 // to be installed in the Address class. This jump will tranfers to the address
872 // contained in the location described by entry (not the address of entry)
873 void jump(ArrayAddress entry);
874
875 // Floating
876
877 void andpd(XMMRegister dst, Address src) { Assembler::andpd(dst, src); }
878 void andpd(XMMRegister dst, AddressLiteral src);
879 void andpd(XMMRegister dst, XMMRegister src) { Assembler::andpd(dst, src); }
880
881 void andps(XMMRegister dst, XMMRegister src) { Assembler::andps(dst, src); }
882 void andps(XMMRegister dst, Address src) { Assembler::andps(dst, src); }
883 void andps(XMMRegister dst, AddressLiteral src);
884
885 void comiss(XMMRegister dst, XMMRegister src) { Assembler::comiss(dst, src); }
886 void comiss(XMMRegister dst, Address src) { Assembler::comiss(dst, src); }
887 void comiss(XMMRegister dst, AddressLiteral src);
888
889 void comisd(XMMRegister dst, XMMRegister src) { Assembler::comisd(dst, src); }
890 void comisd(XMMRegister dst, Address src) { Assembler::comisd(dst, src); }
891 void comisd(XMMRegister dst, AddressLiteral src);
892
893 void fadd_s(Address src) { Assembler::fadd_s(src); }
894 void fadd_s(AddressLiteral src) { Assembler::fadd_s(as_Address(src)); }
895
896 void fldcw(Address src) { Assembler::fldcw(src); }
897 void fldcw(AddressLiteral src);
898
899 void fld_s(int index) { Assembler::fld_s(index); }
900 void fld_s(Address src) { Assembler::fld_s(src); }
901 void fld_s(AddressLiteral src);
902
903 void fld_d(Address src) { Assembler::fld_d(src); }
904 void fld_d(AddressLiteral src);
905
906 void fld_x(Address src) { Assembler::fld_x(src); }
907 void fld_x(AddressLiteral src);
908
909 void fmul_s(Address src) { Assembler::fmul_s(src); }
910 void fmul_s(AddressLiteral src) { Assembler::fmul_s(as_Address(src)); }
911
912 void ldmxcsr(Address src) { Assembler::ldmxcsr(src); }
913 void ldmxcsr(AddressLiteral src);
914
915 #ifdef _LP64
916 private:
917 void sha256_AVX2_one_round_compute(
918 Register reg_old_h,
919 Register reg_a,
920 Register reg_b,
921 Register reg_c,
922 Register reg_d,
923 Register reg_e,
924 Register reg_f,
925 Register reg_g,
926 Register reg_h,
927 int iter);
928 void sha256_AVX2_four_rounds_compute_first(int start);
929 void sha256_AVX2_four_rounds_compute_last(int start);
930 void sha256_AVX2_one_round_and_sched(
931 XMMRegister xmm_0, /* == ymm4 on 0, 1, 2, 3 iterations, then rotate 4 registers left on 4, 8, 12 iterations */
932 XMMRegister xmm_1, /* ymm5 */ /* full cycle is 16 iterations */
933 XMMRegister xmm_2, /* ymm6 */
934 XMMRegister xmm_3, /* ymm7 */
935 Register reg_a, /* == eax on 0 iteration, then rotate 8 register right on each next iteration */
936 Register reg_b, /* ebx */ /* full cycle is 8 iterations */
937 Register reg_c, /* edi */
938 Register reg_d, /* esi */
939 Register reg_e, /* r8d */
940 Register reg_f, /* r9d */
941 Register reg_g, /* r10d */
942 Register reg_h, /* r11d */
943 int iter);
944
945 void addm(int disp, Register r1, Register r2);
946
947 public:
948 void sha256_AVX2(XMMRegister msg, XMMRegister state0, XMMRegister state1, XMMRegister msgtmp0,
949 XMMRegister msgtmp1, XMMRegister msgtmp2, XMMRegister msgtmp3, XMMRegister msgtmp4,
950 Register buf, Register state, Register ofs, Register limit, Register rsp,
951 bool multi_block, XMMRegister shuf_mask);
952 #endif
953
954 #ifdef _LP64
955 private:
956 void sha512_AVX2_one_round_compute(Register old_h, Register a, Register b, Register c, Register d,
957 Register e, Register f, Register g, Register h, int iteration);
958
959 void sha512_AVX2_one_round_and_schedule(XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
960 Register a, Register b, Register c, Register d, Register e, Register f,
961 Register g, Register h, int iteration);
962
963 void addmq(int disp, Register r1, Register r2);
964 public:
965 void sha512_AVX2(XMMRegister msg, XMMRegister state0, XMMRegister state1, XMMRegister msgtmp0,
966 XMMRegister msgtmp1, XMMRegister msgtmp2, XMMRegister msgtmp3, XMMRegister msgtmp4,
967 Register buf, Register state, Register ofs, Register limit, Register rsp, bool multi_block,
968 XMMRegister shuf_mask);
969 #endif
970
971 void fast_sha1(XMMRegister abcd, XMMRegister e0, XMMRegister e1, XMMRegister msg0,
972 XMMRegister msg1, XMMRegister msg2, XMMRegister msg3, XMMRegister shuf_mask,
973 Register buf, Register state, Register ofs, Register limit, Register rsp,
974 bool multi_block);
975
976 #ifdef _LP64
977 void fast_sha256(XMMRegister msg, XMMRegister state0, XMMRegister state1, XMMRegister msgtmp0,
978 XMMRegister msgtmp1, XMMRegister msgtmp2, XMMRegister msgtmp3, XMMRegister msgtmp4,
979 Register buf, Register state, Register ofs, Register limit, Register rsp,
980 bool multi_block, XMMRegister shuf_mask);
981 #else
982 void fast_sha256(XMMRegister msg, XMMRegister state0, XMMRegister state1, XMMRegister msgtmp0,
983 XMMRegister msgtmp1, XMMRegister msgtmp2, XMMRegister msgtmp3, XMMRegister msgtmp4,
984 Register buf, Register state, Register ofs, Register limit, Register rsp,
985 bool multi_block);
986 #endif
987
988 void fast_exp(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
989 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
990 Register rax, Register rcx, Register rdx, Register tmp);
991
992 #ifdef _LP64
993 void fast_log(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
994 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
995 Register rax, Register rcx, Register rdx, Register tmp1, Register tmp2);
996
997 void fast_log10(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
998 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
999 Register rax, Register rcx, Register rdx, Register r11);
1000
1001 void fast_pow(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3, XMMRegister xmm4,
1002 XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7, Register rax, Register rcx,
1003 Register rdx, Register tmp1, Register tmp2, Register tmp3, Register tmp4);
1004
1005 void fast_sin(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1006 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1007 Register rax, Register rbx, Register rcx, Register rdx, Register tmp1, Register tmp2,
1008 Register tmp3, Register tmp4);
1009
1010 void fast_cos(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1011 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1012 Register rax, Register rcx, Register rdx, Register tmp1,
1013 Register tmp2, Register tmp3, Register tmp4);
1014 void fast_tan(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1015 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1016 Register rax, Register rcx, Register rdx, Register tmp1,
1017 Register tmp2, Register tmp3, Register tmp4);
1018 #else
1019 void fast_log(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1020 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1021 Register rax, Register rcx, Register rdx, Register tmp1);
1022
1023 void fast_log10(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1024 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1025 Register rax, Register rcx, Register rdx, Register tmp);
1026
1027 void fast_pow(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3, XMMRegister xmm4,
1028 XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7, Register rax, Register rcx,
1029 Register rdx, Register tmp);
1030
1031 void fast_sin(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1032 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1033 Register rax, Register rbx, Register rdx);
1034
1035 void fast_cos(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1036 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1037 Register rax, Register rcx, Register rdx, Register tmp);
1038
1039 void libm_sincos_huge(XMMRegister xmm0, XMMRegister xmm1, Register eax, Register ecx,
1040 Register edx, Register ebx, Register esi, Register edi,
1041 Register ebp, Register esp);
1042
1043 void libm_reduce_pi04l(Register eax, Register ecx, Register edx, Register ebx,
1044 Register esi, Register edi, Register ebp, Register esp);
1045
1046 void libm_tancot_huge(XMMRegister xmm0, XMMRegister xmm1, Register eax, Register ecx,
1047 Register edx, Register ebx, Register esi, Register edi,
1048 Register ebp, Register esp);
1049
1050 void fast_tan(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1051 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1052 Register rax, Register rcx, Register rdx, Register tmp);
1053 #endif
1054
1055 void increase_precision();
1056 void restore_precision();
1057
1058 private:
1059
1060 // these are private because users should be doing movflt/movdbl
1061
1062 void movss(Address dst, XMMRegister src) { Assembler::movss(dst, src); }
1063 void movss(XMMRegister dst, XMMRegister src) { Assembler::movss(dst, src); }
1064 void movss(XMMRegister dst, Address src) { Assembler::movss(dst, src); }
1065 void movss(XMMRegister dst, AddressLiteral src);
1066
1067 void movlpd(XMMRegister dst, Address src) {Assembler::movlpd(dst, src); }
1068 void movlpd(XMMRegister dst, AddressLiteral src);
1069
1070 public:
1071
1072 void addsd(XMMRegister dst, XMMRegister src) { Assembler::addsd(dst, src); }
1073 void addsd(XMMRegister dst, Address src) { Assembler::addsd(dst, src); }
1074 void addsd(XMMRegister dst, AddressLiteral src);
1075
1076 void addss(XMMRegister dst, XMMRegister src) { Assembler::addss(dst, src); }
1077 void addss(XMMRegister dst, Address src) { Assembler::addss(dst, src); }
1078 void addss(XMMRegister dst, AddressLiteral src);
1079
1080 void addpd(XMMRegister dst, XMMRegister src) { Assembler::addpd(dst, src); }
1081 void addpd(XMMRegister dst, Address src) { Assembler::addpd(dst, src); }
1082 void addpd(XMMRegister dst, AddressLiteral src);
1083
1084 void divsd(XMMRegister dst, XMMRegister src) { Assembler::divsd(dst, src); }
1085 void divsd(XMMRegister dst, Address src) { Assembler::divsd(dst, src); }
1086 void divsd(XMMRegister dst, AddressLiteral src);
1087
1088 void divss(XMMRegister dst, XMMRegister src) { Assembler::divss(dst, src); }
1089 void divss(XMMRegister dst, Address src) { Assembler::divss(dst, src); }
1090 void divss(XMMRegister dst, AddressLiteral src);
1091
1092 // Move Unaligned Double Quadword
1093 void movdqu(Address dst, XMMRegister src);
1094 void movdqu(XMMRegister dst, Address src);
1095 void movdqu(XMMRegister dst, XMMRegister src);
1096 void movdqu(XMMRegister dst, AddressLiteral src, Register scratchReg = rscratch1);
1097 // AVX Unaligned forms
1098 void vmovdqu(Address dst, XMMRegister src);
1099 void vmovdqu(XMMRegister dst, Address src);
1100 void vmovdqu(XMMRegister dst, XMMRegister src);
1101 void vmovdqu(XMMRegister dst, AddressLiteral src);
1102 void evmovdquq(XMMRegister dst, Address src, int vector_len) { Assembler::evmovdquq(dst, src, vector_len); }
1103 void evmovdquq(XMMRegister dst, XMMRegister src, int vector_len) { Assembler::evmovdquq(dst, src, vector_len); }
1104 void evmovdquq(Address dst, XMMRegister src, int vector_len) { Assembler::evmovdquq(dst, src, vector_len); }
1105 void evmovdquq(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch);
1106
1107 // Move Aligned Double Quadword
1108 void movdqa(XMMRegister dst, Address src) { Assembler::movdqa(dst, src); }
1109 void movdqa(XMMRegister dst, XMMRegister src) { Assembler::movdqa(dst, src); }
1110 void movdqa(XMMRegister dst, AddressLiteral src);
1111
1112 void movsd(XMMRegister dst, XMMRegister src) { Assembler::movsd(dst, src); }
1113 void movsd(Address dst, XMMRegister src) { Assembler::movsd(dst, src); }
1114 void movsd(XMMRegister dst, Address src) { Assembler::movsd(dst, src); }
1115 void movsd(XMMRegister dst, AddressLiteral src);
1116
1117 void mulpd(XMMRegister dst, XMMRegister src) { Assembler::mulpd(dst, src); }
1118 void mulpd(XMMRegister dst, Address src) { Assembler::mulpd(dst, src); }
1119 void mulpd(XMMRegister dst, AddressLiteral src);
1120
1121 void mulsd(XMMRegister dst, XMMRegister src) { Assembler::mulsd(dst, src); }
1122 void mulsd(XMMRegister dst, Address src) { Assembler::mulsd(dst, src); }
1123 void mulsd(XMMRegister dst, AddressLiteral src);
1124
1125 void mulss(XMMRegister dst, XMMRegister src) { Assembler::mulss(dst, src); }
1126 void mulss(XMMRegister dst, Address src) { Assembler::mulss(dst, src); }
1127 void mulss(XMMRegister dst, AddressLiteral src);
1128
1129 // Carry-Less Multiplication Quadword
1130 void pclmulldq(XMMRegister dst, XMMRegister src) {
1131 // 0x00 - multiply lower 64 bits [0:63]
1132 Assembler::pclmulqdq(dst, src, 0x00);
1133 }
1134 void pclmulhdq(XMMRegister dst, XMMRegister src) {
1135 // 0x11 - multiply upper 64 bits [64:127]
1136 Assembler::pclmulqdq(dst, src, 0x11);
1137 }
1138
1139 void pcmpeqb(XMMRegister dst, XMMRegister src);
1140 void pcmpeqw(XMMRegister dst, XMMRegister src);
1141
1142 void pcmpestri(XMMRegister dst, Address src, int imm8);
1143 void pcmpestri(XMMRegister dst, XMMRegister src, int imm8);
1144
1145 void pmovzxbw(XMMRegister dst, XMMRegister src);
1146 void pmovzxbw(XMMRegister dst, Address src);
1147
1148 void pmovmskb(Register dst, XMMRegister src);
1149
1150 void ptest(XMMRegister dst, XMMRegister src);
1151
1152 void sqrtsd(XMMRegister dst, XMMRegister src) { Assembler::sqrtsd(dst, src); }
1153 void sqrtsd(XMMRegister dst, Address src) { Assembler::sqrtsd(dst, src); }
1154 void sqrtsd(XMMRegister dst, AddressLiteral src);
1155
1156 void sqrtss(XMMRegister dst, XMMRegister src) { Assembler::sqrtss(dst, src); }
1157 void sqrtss(XMMRegister dst, Address src) { Assembler::sqrtss(dst, src); }
1158 void sqrtss(XMMRegister dst, AddressLiteral src);
1159
1160 void subsd(XMMRegister dst, XMMRegister src) { Assembler::subsd(dst, src); }
1161 void subsd(XMMRegister dst, Address src) { Assembler::subsd(dst, src); }
1162 void subsd(XMMRegister dst, AddressLiteral src);
1163
1164 void subss(XMMRegister dst, XMMRegister src) { Assembler::subss(dst, src); }
1165 void subss(XMMRegister dst, Address src) { Assembler::subss(dst, src); }
1166 void subss(XMMRegister dst, AddressLiteral src);
1167
1168 void ucomiss(XMMRegister dst, XMMRegister src) { Assembler::ucomiss(dst, src); }
1169 void ucomiss(XMMRegister dst, Address src) { Assembler::ucomiss(dst, src); }
1170 void ucomiss(XMMRegister dst, AddressLiteral src);
1171
1172 void ucomisd(XMMRegister dst, XMMRegister src) { Assembler::ucomisd(dst, src); }
1173 void ucomisd(XMMRegister dst, Address src) { Assembler::ucomisd(dst, src); }
1174 void ucomisd(XMMRegister dst, AddressLiteral src);
1175
1176 // Bitwise Logical XOR of Packed Double-Precision Floating-Point Values
1177 void xorpd(XMMRegister dst, XMMRegister src);
1178 void xorpd(XMMRegister dst, Address src) { Assembler::xorpd(dst, src); }
1179 void xorpd(XMMRegister dst, AddressLiteral src);
1180
1181 // Bitwise Logical XOR of Packed Single-Precision Floating-Point Values
1182 void xorps(XMMRegister dst, XMMRegister src);
1183 void xorps(XMMRegister dst, Address src) { Assembler::xorps(dst, src); }
1184 void xorps(XMMRegister dst, AddressLiteral src);
1185
1186 // Shuffle Bytes
1187 void pshufb(XMMRegister dst, XMMRegister src) { Assembler::pshufb(dst, src); }
1188 void pshufb(XMMRegister dst, Address src) { Assembler::pshufb(dst, src); }
1189 void pshufb(XMMRegister dst, AddressLiteral src);
1190 // AVX 3-operands instructions
1191
1192 void vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vaddsd(dst, nds, src); }
1193 void vaddsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vaddsd(dst, nds, src); }
1194 void vaddsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1195
1196 void vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vaddss(dst, nds, src); }
1197 void vaddss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vaddss(dst, nds, src); }
1198 void vaddss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1199
1200 void vabsss(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len);
1201 void vabssd(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len);
1202
1203 void vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1204 void vpaddb(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1205
1206 void vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1207 void vpaddw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1208
1209 void vpand(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vpand(dst, nds, src, vector_len); }
1210 void vpand(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vpand(dst, nds, src, vector_len); }
1211 void vpand(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len);
1212
1213 void vpbroadcastw(XMMRegister dst, XMMRegister src);
1214
1215 void vpcmpeqb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1216 void vpcmpeqw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1217
1218 void vpmovzxbw(XMMRegister dst, Address src, int vector_len);
1219 void vpmovzxbw(XMMRegister dst, XMMRegister src, int vector_len) { Assembler::vpmovzxbw(dst, src, vector_len); }
1220
1221 void vpmovmskb(Register dst, XMMRegister src);
1222
1223 void vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1224 void vpmullw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1225
1226 void vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1227 void vpsubb(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1228
1229 void vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1230 void vpsubw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1231
1232 void vpsraw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len);
1233 void vpsraw(XMMRegister dst, XMMRegister nds, int shift, int vector_len);
1234
1235 void vpsrlw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len);
1236 void vpsrlw(XMMRegister dst, XMMRegister nds, int shift, int vector_len);
1237
1238 void vpsllw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len);
1239 void vpsllw(XMMRegister dst, XMMRegister nds, int shift, int vector_len);
1240
1241 void vptest(XMMRegister dst, XMMRegister src);
1242
1243 void punpcklbw(XMMRegister dst, XMMRegister src);
1244 void punpcklbw(XMMRegister dst, Address src) { Assembler::punpcklbw(dst, src); }
1245
1246 void pshufd(XMMRegister dst, Address src, int mode);
1247 void pshufd(XMMRegister dst, XMMRegister src, int mode) { Assembler::pshufd(dst, src, mode); }
1248
1249 void pshuflw(XMMRegister dst, XMMRegister src, int mode);
1250 void pshuflw(XMMRegister dst, Address src, int mode) { Assembler::pshuflw(dst, src, mode); }
1251
1252 void vandpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vandpd(dst, nds, src, vector_len); }
1253 void vandpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vandpd(dst, nds, src, vector_len); }
1254 void vandpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len);
1255
1256 void vandps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vandps(dst, nds, src, vector_len); }
1257 void vandps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vandps(dst, nds, src, vector_len); }
1258 void vandps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len);
1259
1260 void vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vdivsd(dst, nds, src); }
1261 void vdivsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vdivsd(dst, nds, src); }
1262 void vdivsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1263
1264 void vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vdivss(dst, nds, src); }
1265 void vdivss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vdivss(dst, nds, src); }
1266 void vdivss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1267
1268 void vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vmulsd(dst, nds, src); }
1269 void vmulsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vmulsd(dst, nds, src); }
1270 void vmulsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1271
1272 void vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vmulss(dst, nds, src); }
1273 void vmulss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vmulss(dst, nds, src); }
1274 void vmulss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1275
1276 void vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vsubsd(dst, nds, src); }
1277 void vsubsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vsubsd(dst, nds, src); }
1278 void vsubsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1279
1280 void vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vsubss(dst, nds, src); }
1281 void vsubss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vsubss(dst, nds, src); }
1282 void vsubss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1283
1284 void vnegatess(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1285 void vnegatesd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1286
1287 // AVX Vector instructions
1288
1289 void vxorpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vxorpd(dst, nds, src, vector_len); }
1290 void vxorpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vxorpd(dst, nds, src, vector_len); }
1291 void vxorpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len);
1292
1293 void vxorps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vxorps(dst, nds, src, vector_len); }
1294 void vxorps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vxorps(dst, nds, src, vector_len); }
1295 void vxorps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len);
1296
1297 void vpxor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
1298 if (UseAVX > 1 || (vector_len < 1)) // vpxor 256 bit is available only in AVX2
1299 Assembler::vpxor(dst, nds, src, vector_len);
1300 else
1301 Assembler::vxorpd(dst, nds, src, vector_len);
1302 }
1303 void vpxor(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
1304 if (UseAVX > 1 || (vector_len < 1)) // vpxor 256 bit is available only in AVX2
1305 Assembler::vpxor(dst, nds, src, vector_len);
1306 else
1307 Assembler::vxorpd(dst, nds, src, vector_len);
1308 }
1309
1310 // Simple version for AVX2 256bit vectors
1311 void vpxor(XMMRegister dst, XMMRegister src) { Assembler::vpxor(dst, dst, src, true); }
1312 void vpxor(XMMRegister dst, Address src) { Assembler::vpxor(dst, dst, src, true); }
1313
1314 void vinserti128(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
1315 if (UseAVX > 2) {
1316 Assembler::vinserti32x4(dst, dst, src, imm8);
1317 } else if (UseAVX > 1) {
1318 // vinserti128 is available only in AVX2
1319 Assembler::vinserti128(dst, nds, src, imm8);
1320 } else {
1321 Assembler::vinsertf128(dst, nds, src, imm8);
1322 }
1323 }
1324
1325 void vinserti128(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) {
1326 if (UseAVX > 2) {
1327 Assembler::vinserti32x4(dst, dst, src, imm8);
1328 } else if (UseAVX > 1) {
1329 // vinserti128 is available only in AVX2
1330 Assembler::vinserti128(dst, nds, src, imm8);
1331 } else {
1332 Assembler::vinsertf128(dst, nds, src, imm8);
1333 }
1334 }
1335
1336 void vextracti128(XMMRegister dst, XMMRegister src, uint8_t imm8) {
1337 if (UseAVX > 2) {
1338 Assembler::vextracti32x4(dst, src, imm8);
1339 } else if (UseAVX > 1) {
1340 // vextracti128 is available only in AVX2
1341 Assembler::vextracti128(dst, src, imm8);
1342 } else {
1343 Assembler::vextractf128(dst, src, imm8);
1344 }
1345 }
1346
1347 void vextracti128(Address dst, XMMRegister src, uint8_t imm8) {
1348 if (UseAVX > 2) {
1349 Assembler::vextracti32x4(dst, src, imm8);
1350 } else if (UseAVX > 1) {
1351 // vextracti128 is available only in AVX2
1352 Assembler::vextracti128(dst, src, imm8);
1353 } else {
1354 Assembler::vextractf128(dst, src, imm8);
1355 }
1356 }
1357
1358 // 128bit copy to/from high 128 bits of 256bit (YMM) vector registers
1359 void vinserti128_high(XMMRegister dst, XMMRegister src) {
1360 vinserti128(dst, dst, src, 1);
1361 }
1362 void vinserti128_high(XMMRegister dst, Address src) {
1363 vinserti128(dst, dst, src, 1);
1364 }
1365 void vextracti128_high(XMMRegister dst, XMMRegister src) {
1366 vextracti128(dst, src, 1);
1367 }
1368 void vextracti128_high(Address dst, XMMRegister src) {
1369 vextracti128(dst, src, 1);
1370 }
1371
1372 void vinsertf128_high(XMMRegister dst, XMMRegister src) {
1373 if (UseAVX > 2) {
1374 Assembler::vinsertf32x4(dst, dst, src, 1);
1375 } else {
1376 Assembler::vinsertf128(dst, dst, src, 1);
1377 }
1378 }
1379
1380 void vinsertf128_high(XMMRegister dst, Address src) {
1381 if (UseAVX > 2) {
1382 Assembler::vinsertf32x4(dst, dst, src, 1);
1383 } else {
1384 Assembler::vinsertf128(dst, dst, src, 1);
1385 }
1386 }
1387
1388 void vextractf128_high(XMMRegister dst, XMMRegister src) {
1389 if (UseAVX > 2) {
1390 Assembler::vextractf32x4(dst, src, 1);
1391 } else {
1392 Assembler::vextractf128(dst, src, 1);
1393 }
1394 }
1395
1396 void vextractf128_high(Address dst, XMMRegister src) {
1397 if (UseAVX > 2) {
1398 Assembler::vextractf32x4(dst, src, 1);
1399 } else {
1400 Assembler::vextractf128(dst, src, 1);
1401 }
1402 }
1403
1404 // 256bit copy to/from high 256 bits of 512bit (ZMM) vector registers
1405 void vinserti64x4_high(XMMRegister dst, XMMRegister src) {
1406 Assembler::vinserti64x4(dst, dst, src, 1);
1407 }
1408 void vinsertf64x4_high(XMMRegister dst, XMMRegister src) {
1409 Assembler::vinsertf64x4(dst, dst, src, 1);
1410 }
1411 void vextracti64x4_high(XMMRegister dst, XMMRegister src) {
1412 Assembler::vextracti64x4(dst, src, 1);
1413 }
1414 void vextractf64x4_high(XMMRegister dst, XMMRegister src) {
1415 Assembler::vextractf64x4(dst, src, 1);
1416 }
1417 void vextractf64x4_high(Address dst, XMMRegister src) {
1418 Assembler::vextractf64x4(dst, src, 1);
1419 }
1420 void vinsertf64x4_high(XMMRegister dst, Address src) {
1421 Assembler::vinsertf64x4(dst, dst, src, 1);
1422 }
1423
1424 // 128bit copy to/from low 128 bits of 256bit (YMM) vector registers
1425 void vinserti128_low(XMMRegister dst, XMMRegister src) {
1426 vinserti128(dst, dst, src, 0);
1427 }
1428 void vinserti128_low(XMMRegister dst, Address src) {
1429 vinserti128(dst, dst, src, 0);
1430 }
1431 void vextracti128_low(XMMRegister dst, XMMRegister src) {
1432 vextracti128(dst, src, 0);
1433 }
1434 void vextracti128_low(Address dst, XMMRegister src) {
1435 vextracti128(dst, src, 0);
1436 }
1437
1438 void vinsertf128_low(XMMRegister dst, XMMRegister src) {
1439 if (UseAVX > 2) {
1440 Assembler::vinsertf32x4(dst, dst, src, 0);
1441 } else {
1442 Assembler::vinsertf128(dst, dst, src, 0);
1443 }
1444 }
1445
1446 void vinsertf128_low(XMMRegister dst, Address src) {
1447 if (UseAVX > 2) {
1448 Assembler::vinsertf32x4(dst, dst, src, 0);
1449 } else {
1450 Assembler::vinsertf128(dst, dst, src, 0);
1451 }
1452 }
1453
1454 void vextractf128_low(XMMRegister dst, XMMRegister src) {
1455 if (UseAVX > 2) {
1456 Assembler::vextractf32x4(dst, src, 0);
1457 } else {
1458 Assembler::vextractf128(dst, src, 0);
1459 }
1460 }
1461
1462 void vextractf128_low(Address dst, XMMRegister src) {
1463 if (UseAVX > 2) {
1464 Assembler::vextractf32x4(dst, src, 0);
1465 } else {
1466 Assembler::vextractf128(dst, src, 0);
1467 }
1468 }
1469
1470 // 256bit copy to/from low 256 bits of 512bit (ZMM) vector registers
1471 void vinserti64x4_low(XMMRegister dst, XMMRegister src) {
1472 Assembler::vinserti64x4(dst, dst, src, 0);
1473 }
1474 void vinsertf64x4_low(XMMRegister dst, XMMRegister src) {
1475 Assembler::vinsertf64x4(dst, dst, src, 0);
1476 }
1477 void vextracti64x4_low(XMMRegister dst, XMMRegister src) {
1478 Assembler::vextracti64x4(dst, src, 0);
1479 }
1480 void vextractf64x4_low(XMMRegister dst, XMMRegister src) {
1481 Assembler::vextractf64x4(dst, src, 0);
1482 }
1483 void vextractf64x4_low(Address dst, XMMRegister src) {
1484 Assembler::vextractf64x4(dst, src, 0);
1485 }
1486 void vinsertf64x4_low(XMMRegister dst, Address src) {
1487 Assembler::vinsertf64x4(dst, dst, src, 0);
1488 }
1489
1490 // Carry-Less Multiplication Quadword
1491 void vpclmulldq(XMMRegister dst, XMMRegister nds, XMMRegister src) {
1492 // 0x00 - multiply lower 64 bits [0:63]
1493 Assembler::vpclmulqdq(dst, nds, src, 0x00);
1494 }
1495 void vpclmulhdq(XMMRegister dst, XMMRegister nds, XMMRegister src) {
1496 // 0x11 - multiply upper 64 bits [64:127]
1497 Assembler::vpclmulqdq(dst, nds, src, 0x11);
1498 }
1499 void evpclmulldq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
1500 // 0x00 - multiply lower 64 bits [0:63]
1501 Assembler::evpclmulqdq(dst, nds, src, 0x00, vector_len);
1502 }
1503 void evpclmulhdq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
1504 // 0x11 - multiply upper 64 bits [64:127]
1505 Assembler::evpclmulqdq(dst, nds, src, 0x11, vector_len);
1506 }
1507
1508 // Data
1509
1510 void cmov32( Condition cc, Register dst, Address src);
1511 void cmov32( Condition cc, Register dst, Register src);
1512
1513 void cmov( Condition cc, Register dst, Register src) { cmovptr(cc, dst, src); }
1514
1515 void cmovptr(Condition cc, Register dst, Address src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmov32(cc, dst, src)); }
1516 void cmovptr(Condition cc, Register dst, Register src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmov32(cc, dst, src)); }
1517
1518 void movoop(Register dst, jobject obj);
1519 void movoop(Address dst, jobject obj);
1520
1521 void mov_metadata(Register dst, Metadata* obj);
1522 void mov_metadata(Address dst, Metadata* obj);
1523
1524 void movptr(ArrayAddress dst, Register src);
1525 // can this do an lea?
1526 void movptr(Register dst, ArrayAddress src);
1527
1528 void movptr(Register dst, Address src);
1529
1530 #ifdef _LP64
1531 void movptr(Register dst, AddressLiteral src, Register scratch=rscratch1);
1532 #else
1533 void movptr(Register dst, AddressLiteral src, Register scratch=noreg); // Scratch reg is ignored in 32-bit
1534 #endif
1535
1536 void movptr(Register dst, intptr_t src);
1537 void movptr(Register dst, Register src);
1538 void movptr(Address dst, intptr_t src);
1539
1540 void movptr(Address dst, Register src);
1541
1542 void movptr(Register dst, RegisterOrConstant src) {
1543 if (src.is_constant()) movptr(dst, src.as_constant());
1544 else movptr(dst, src.as_register());
1545 }
1546
1547 #ifdef _LP64
1548 // Generally the next two are only used for moving NULL
1549 // Although there are situations in initializing the mark word where
1550 // they could be used. They are dangerous.
1551
1552 // They only exist on LP64 so that int32_t and intptr_t are not the same
1553 // and we have ambiguous declarations.
1554
1555 void movptr(Address dst, int32_t imm32);
1556 void movptr(Register dst, int32_t imm32);
1557 #endif // _LP64
1558
1559 // to avoid hiding movl
1560 void mov32(AddressLiteral dst, Register src);
1561 void mov32(Register dst, AddressLiteral src);
1562
1563 // to avoid hiding movb
1564 void movbyte(ArrayAddress dst, int src);
1565
1566 // Import other mov() methods from the parent class or else
1567 // they will be hidden by the following overriding declaration.
1568 using Assembler::movdl;
1569 using Assembler::movq;
1570 void movdl(XMMRegister dst, AddressLiteral src);
1571 void movq(XMMRegister dst, AddressLiteral src);
1572
1573 // Can push value or effective address
1574 void pushptr(AddressLiteral src);
1575
1576 void pushptr(Address src) { LP64_ONLY(pushq(src)) NOT_LP64(pushl(src)); }
1577 void popptr(Address src) { LP64_ONLY(popq(src)) NOT_LP64(popl(src)); }
1578
1579 void pushoop(jobject obj);
1580 void pushklass(Metadata* obj);
1581
1582 // sign extend as need a l to ptr sized element
1583 void movl2ptr(Register dst, Address src) { LP64_ONLY(movslq(dst, src)) NOT_LP64(movl(dst, src)); }
1584 void movl2ptr(Register dst, Register src) { LP64_ONLY(movslq(dst, src)) NOT_LP64(if (dst != src) movl(dst, src)); }
1585
1586 // C2 compiled method's prolog code.
1587 void verified_entry(int framesize, int stack_bang_size, bool fp_mode_24b);
1588
1589 // clear memory of size 'cnt' qwords, starting at 'base';
1590 // if 'is_large' is set, do not try to produce short loop
1591 void clear_mem(Register base, Register cnt, Register rtmp, XMMRegister xtmp, bool is_large);
1592
1593 // clear memory of size 'cnt' qwords, starting at 'base' using XMM/YMM registers
1594 void xmm_clear_mem(Register base, Register cnt, XMMRegister xtmp);
1595
1596 #ifdef COMPILER2
1597 void string_indexof_char(Register str1, Register cnt1, Register ch, Register result,
1598 XMMRegister vec1, XMMRegister vec2, XMMRegister vec3, Register tmp);
1599
1600 // IndexOf strings.
1601 // Small strings are loaded through stack if they cross page boundary.
1602 void string_indexof(Register str1, Register str2,
1603 Register cnt1, Register cnt2,
1604 int int_cnt2, Register result,
1605 XMMRegister vec, Register tmp,
1606 int ae);
1607
1608 // IndexOf for constant substrings with size >= 8 elements
1609 // which don't need to be loaded through stack.
1610 void string_indexofC8(Register str1, Register str2,
1611 Register cnt1, Register cnt2,
1612 int int_cnt2, Register result,
1613 XMMRegister vec, Register tmp,
1614 int ae);
1615
1616 // Smallest code: we don't need to load through stack,
1617 // check string tail.
1618
1619 // helper function for string_compare
1620 void load_next_elements(Register elem1, Register elem2, Register str1, Register str2,
1621 Address::ScaleFactor scale, Address::ScaleFactor scale1,
1622 Address::ScaleFactor scale2, Register index, int ae);
1623 // Compare strings.
1624 void string_compare(Register str1, Register str2,
1625 Register cnt1, Register cnt2, Register result,
1626 XMMRegister vec1, int ae);
1627
1628 // Search for Non-ASCII character (Negative byte value) in a byte array,
1629 // return true if it has any and false otherwise.
1630 void has_negatives(Register ary1, Register len,
1631 Register result, Register tmp1,
1632 XMMRegister vec1, XMMRegister vec2);
1633
1634 // Compare char[] or byte[] arrays.
1635 void arrays_equals(bool is_array_equ, Register ary1, Register ary2,
1636 Register limit, Register result, Register chr,
1637 XMMRegister vec1, XMMRegister vec2, bool is_char);
1638
1639 #endif
1640
1641 // Fill primitive arrays
1642 void generate_fill(BasicType t, bool aligned,
1643 Register to, Register value, Register count,
1644 Register rtmp, XMMRegister xtmp);
1645
1646 void encode_iso_array(Register src, Register dst, Register len,
1647 XMMRegister tmp1, XMMRegister tmp2, XMMRegister tmp3,
1648 XMMRegister tmp4, Register tmp5, Register result);
1649
1650 #ifdef _LP64
1651 void add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2);
1652 void multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
1653 Register y, Register y_idx, Register z,
1654 Register carry, Register product,
1655 Register idx, Register kdx);
1656 void multiply_add_128_x_128(Register x_xstart, Register y, Register z,
1657 Register yz_idx, Register idx,
1658 Register carry, Register product, int offset);
1659 void multiply_128_x_128_bmi2_loop(Register y, Register z,
1660 Register carry, Register carry2,
1661 Register idx, Register jdx,
1662 Register yz_idx1, Register yz_idx2,
1663 Register tmp, Register tmp3, Register tmp4);
1664 void multiply_128_x_128_loop(Register x_xstart, Register y, Register z,
1665 Register yz_idx, Register idx, Register jdx,
1666 Register carry, Register product,
1667 Register carry2);
1668 void multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z, Register zlen,
1669 Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5);
1670 void square_rshift(Register x, Register len, Register z, Register tmp1, Register tmp3,
1671 Register tmp4, Register tmp5, Register rdxReg, Register raxReg);
1672 void multiply_add_64_bmi2(Register sum, Register op1, Register op2, Register carry,
1673 Register tmp2);
1674 void multiply_add_64(Register sum, Register op1, Register op2, Register carry,
1675 Register rdxReg, Register raxReg);
1676 void add_one_64(Register z, Register zlen, Register carry, Register tmp1);
1677 void lshift_by_1(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2,
1678 Register tmp3, Register tmp4);
1679 void square_to_len(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2,
1680 Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg);
1681
1682 void mul_add_128_x_32_loop(Register out, Register in, Register offset, Register len, Register tmp1,
1683 Register tmp2, Register tmp3, Register tmp4, Register tmp5, Register rdxReg,
1684 Register raxReg);
1685 void mul_add(Register out, Register in, Register offset, Register len, Register k, Register tmp1,
1686 Register tmp2, Register tmp3, Register tmp4, Register tmp5, Register rdxReg,
1687 Register raxReg);
1688 void vectorized_mismatch(Register obja, Register objb, Register length, Register log2_array_indxscale,
1689 Register result, Register tmp1, Register tmp2,
1690 XMMRegister vec1, XMMRegister vec2, XMMRegister vec3);
1691 #endif
1692
1693 // CRC32 code for java.util.zip.CRC32::updateBytes() intrinsic.
1694 void update_byte_crc32(Register crc, Register val, Register table);
1695 void kernel_crc32(Register crc, Register buf, Register len, Register table, Register tmp);
1696 // CRC32C code for java.util.zip.CRC32C::updateBytes() intrinsic
1697 // Note on a naming convention:
1698 // Prefix w = register only used on a Westmere+ architecture
1699 // Prefix n = register only used on a Nehalem architecture
1700 #ifdef _LP64
1701 void crc32c_ipl_alg4(Register in_out, uint32_t n,
1702 Register tmp1, Register tmp2, Register tmp3);
1703 #else
1704 void crc32c_ipl_alg4(Register in_out, uint32_t n,
1705 Register tmp1, Register tmp2, Register tmp3,
1706 XMMRegister xtmp1, XMMRegister xtmp2);
1707 #endif
1708 void crc32c_pclmulqdq(XMMRegister w_xtmp1,
1709 Register in_out,
1710 uint32_t const_or_pre_comp_const_index, bool is_pclmulqdq_supported,
1711 XMMRegister w_xtmp2,
1712 Register tmp1,
1713 Register n_tmp2, Register n_tmp3);
1714 void crc32c_rec_alt2(uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, Register in_out, Register in1, Register in2,
1715 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
1716 Register tmp1, Register tmp2,
1717 Register n_tmp3);
1718 void crc32c_proc_chunk(uint32_t size, uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported,
1719 Register in_out1, Register in_out2, Register in_out3,
1720 Register tmp1, Register tmp2, Register tmp3,
1721 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
1722 Register tmp4, Register tmp5,
1723 Register n_tmp6);
1724 void crc32c_ipl_alg2_alt2(Register in_out, Register in1, Register in2,
1725 Register tmp1, Register tmp2, Register tmp3,
1726 Register tmp4, Register tmp5, Register tmp6,
1727 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
1728 bool is_pclmulqdq_supported);
1729 // Fold 128-bit data chunk
1730 void fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, int offset);
1731 void fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, XMMRegister xbuf);
1732 // Fold 8-bit data
1733 void fold_8bit_crc32(Register crc, Register table, Register tmp);
1734 void fold_8bit_crc32(XMMRegister crc, Register table, XMMRegister xtmp, Register tmp);
1735 void fold_128bit_crc32_avx512(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, int offset);
1736
1737 // Compress char[] array to byte[].
1738 void char_array_compress(Register src, Register dst, Register len,
1739 XMMRegister tmp1, XMMRegister tmp2, XMMRegister tmp3,
1740 XMMRegister tmp4, Register tmp5, Register result);
1741
1742 // Inflate byte[] array to char[].
1743 void byte_array_inflate(Register src, Register dst, Register len,
1744 XMMRegister tmp1, Register tmp2);
1745
1746 };
1747
1748 /**
1749 * class SkipIfEqual:
1750 *
1751 * Instantiating this class will result in assembly code being output that will
1752 * jump around any code emitted between the creation of the instance and it's
1753 * automatic destruction at the end of a scope block, depending on the value of
1754 * the flag passed to the constructor, which will be checked at run-time.
1755 */
1756 class SkipIfEqual {
1757 private:
1758 MacroAssembler* _masm;
1759 Label _label;
1760
1761 public:
1762 SkipIfEqual(MacroAssembler*, const bool* flag_addr, bool value);
1763 ~SkipIfEqual();
1764 };
1765
1766 #endif // CPU_X86_VM_MACROASSEMBLER_X86_HPP