1588       } else if (have_mm2 && !is_empty2()) {
1589         return true;   // is_empty() == true
1590       }
1591     }
1592     return false;
1593   }
1594 };
1595 
1596 //------------------------------Prefetch---------------------------------------
1597 
1598 // Allocation prefetch which may fault, TLAB size have to be adjusted.
1599 class PrefetchAllocationNode : public Node {
1600 public:
1601   PrefetchAllocationNode(Node *mem, Node *adr) : Node(0,mem,adr) {}
1602   virtual int Opcode() const;
1603   virtual uint ideal_reg() const { return NotAMachineReg; }
1604   virtual uint match_edge(uint idx) const { return idx==2; }
1605   virtual const Type *bottom_type() const { return ( AllocatePrefetchStyle == 3 ) ? Type::MEMORY : Type::ABIO; }
1606 };
1607 




































1608 #endif // SHARE_VM_OPTO_MEMNODE_HPP

1588       } else if (have_mm2 && !is_empty2()) {
1589         return true;   // is_empty() == true
1590       }
1591     }
1592     return false;
1593   }
1594 };
1595 
1596 //------------------------------Prefetch---------------------------------------
1597 
1598 // Allocation prefetch which may fault, TLAB size have to be adjusted.
1599 class PrefetchAllocationNode : public Node {
1600 public:
1601   PrefetchAllocationNode(Node *mem, Node *adr) : Node(0,mem,adr) {}
1602   virtual int Opcode() const;
1603   virtual uint ideal_reg() const { return NotAMachineReg; }
1604   virtual uint match_edge(uint idx) const { return idx==2; }
1605   virtual const Type *bottom_type() const { return ( AllocatePrefetchStyle == 3 ) ? Type::MEMORY : Type::ABIO; }
1606 };
1607 
1608 // cachewb node for guaranteeing writeback of the cache line at a
1609 // given address to (persistent) storage
1610 class CacheWBNode : public Node {
1611 public:
1612   CacheWBNode(Node *ctrl, Node *mem, Node *addr) : Node(ctrl, mem, addr) {}
1613   virtual int Opcode() const;
1614   virtual uint ideal_reg() const { return NotAMachineReg; }
1615   virtual uint match_edge(uint idx) const { return (idx == 2); }
1616   virtual const TypePtr *adr_type() const { return TypeRawPtr::BOTTOM; }
1617   virtual const Type *bottom_type() const { return Type::MEMORY; }
1618 };
1619 
1620 // cachewb pre sync node for ensuring that writebacks are serialised
1621 // relative to preceding or following stores
1622 class CacheWBPreSyncNode : public Node {
1623 public:
1624   CacheWBPreSyncNode(Node *ctrl, Node *mem) : Node(ctrl, mem) {}
1625   virtual int Opcode() const;
1626   virtual uint ideal_reg() const { return NotAMachineReg; }
1627   virtual uint match_edge(uint idx) const { return false; }
1628   virtual const TypePtr *adr_type() const { return TypeRawPtr::BOTTOM; }
1629   virtual const Type *bottom_type() const { return Type::MEMORY; }
1630 };
1631 
1632 // cachewb pre sync node for ensuring that writebacks are serialised
1633 // relative to preceding or following stores
1634 class CacheWBPostSyncNode : public Node {
1635 public:
1636   CacheWBPostSyncNode(Node *ctrl, Node *mem) : Node(ctrl, mem) {}
1637   virtual int Opcode() const;
1638   virtual uint ideal_reg() const { return NotAMachineReg; }
1639   virtual uint match_edge(uint idx) const { return false; }
1640   virtual const TypePtr *adr_type() const { return TypeRawPtr::BOTTOM; }
1641   virtual const Type *bottom_type() const { return Type::MEMORY; }
1642 };
1643 
1644 #endif // SHARE_VM_OPTO_MEMNODE_HPP