src/share/vm/opto/coalesce.cpp
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src/share/vm/opto/coalesce.cpp

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  35 #include "opto/regmask.hpp"
  36 
  37 //=============================================================================
  38 //------------------------------Dump-------------------------------------------
  39 #ifndef PRODUCT
  40 void PhaseCoalesce::dump(Node *n) const {
  41   // Being a const function means I cannot use 'Find'
  42   uint r = _phc._lrg_map.find(n);
  43   tty->print("L%d/N%d ",r,n->_idx);
  44 }
  45 
  46 //------------------------------dump-------------------------------------------
  47 void PhaseCoalesce::dump() const {
  48   // I know I have a block layout now, so I can print blocks in a loop
  49   for( uint i=0; i<_phc._cfg._num_blocks; i++ ) {
  50     uint j;
  51     Block *b = _phc._cfg._blocks[i];
  52     // Print a nice block header
  53     tty->print("B%d: ",b->_pre_order);
  54     for( j=1; j<b->num_preds(); j++ )
  55       tty->print("B%d ", _phc._cfg._bbs[b->pred(j)->_idx]->_pre_order);
  56     tty->print("-> ");
  57     for( j=0; j<b->_num_succs; j++ )
  58       tty->print("B%d ",b->_succs[j]->_pre_order);
  59     tty->print(" IDom: B%d/#%d\n", b->_idom ? b->_idom->_pre_order : 0, b->_dom_depth);
  60     uint cnt = b->_nodes.size();
  61     for( j=0; j<cnt; j++ ) {
  62       Node *n = b->_nodes[j];
  63       dump( n );
  64       tty->print("\t%s\t",n->Name());
  65 
  66       // Dump the inputs
  67       uint k;                   // Exit value of loop
  68       for( k=0; k<n->req(); k++ ) // For all required inputs
  69         if( n->in(k) ) dump( n->in(k) );
  70         else tty->print("_ ");
  71       int any_prec = 0;
  72       for( ; k<n->len(); k++ )          // For all precedence inputs
  73         if( n->in(k) ) {
  74           if( !any_prec++ ) tty->print(" |");
  75           dump( n->in(k) );


 191     if (_phc._lrg_map.find(n) == src_name) {
 192       kill_src_idx = i;
 193       break;
 194     }
 195     i--;
 196   }
 197   // Need a temp?  Last use of dst comes after the kill of src?
 198   if (last_use_idx >= kill_src_idx) {
 199     // Need to break a cycle with a temp
 200     uint idx = copy->is_Copy();
 201     Node *tmp = copy->clone();
 202     uint max_lrg_id = _phc._lrg_map.max_lrg_id();
 203     _phc.new_lrg(tmp, max_lrg_id);
 204     _phc._lrg_map.set_max_lrg_id(max_lrg_id + 1);
 205 
 206     // Insert new temp between copy and source
 207     tmp ->set_req(idx,copy->in(idx));
 208     copy->set_req(idx,tmp);
 209     // Save source in temp early, before source is killed
 210     b->_nodes.insert(kill_src_idx,tmp);
 211     _phc._cfg._bbs.map( tmp->_idx, b );
 212     last_use_idx++;
 213   }
 214 
 215   // Insert just after last use
 216   b->_nodes.insert(last_use_idx+1,copy);
 217 }
 218 
 219 //------------------------------insert_copies----------------------------------
 220 void PhaseAggressiveCoalesce::insert_copies( Matcher &matcher ) {
 221   // We do LRGs compressing and fix a liveout data only here since the other
 222   // place in Split() is guarded by the assert which we never hit.
 223   _phc._lrg_map.compress_uf_map_for_nodes();
 224   // Fix block's liveout data for compressed live ranges.
 225   for (uint lrg = 1; lrg < _phc._lrg_map.max_lrg_id(); lrg++) {
 226     uint compressed_lrg = _phc._lrg_map.find(lrg);
 227     if (lrg != compressed_lrg) {
 228       for (uint bidx = 0; bidx < _phc._cfg._num_blocks; bidx++) {
 229         IndexSet *liveout = _phc._live->live(_phc._cfg._blocks[bidx]);
 230         if (liveout->member(lrg)) {
 231           liveout->remove(lrg);


 269           n->replace_by(def);
 270           n->set_req(cidx,NULL);
 271           b->_nodes.remove(l);
 272           l--;
 273           continue;
 274         }
 275       }
 276 
 277       if (n->is_Phi()) {
 278         // Get the chosen name for the Phi
 279         uint phi_name = _phc._lrg_map.find(n);
 280         // Ignore the pre-allocated specials
 281         if (!phi_name) {
 282           continue;
 283         }
 284         // Check for mismatch inputs to Phi
 285         for (uint j = 1; j < cnt; j++) {
 286           Node *m = n->in(j);
 287           uint src_name = _phc._lrg_map.find(m);
 288           if (src_name != phi_name) {
 289             Block *pred = _phc._cfg._bbs[b->pred(j)->_idx];
 290             Node *copy;
 291             assert(!m->is_Con() || m->is_Mach(), "all Con must be Mach");
 292             // Rematerialize constants instead of copying them
 293             if( m->is_Mach() && m->as_Mach()->is_Con() &&
 294                 m->as_Mach()->rematerialize() ) {
 295               copy = m->clone();
 296               // Insert the copy in the predecessor basic block
 297               pred->add_inst(copy);
 298               // Copy any flags as well
 299               _phc.clone_projs(pred, pred->end_idx(), m, copy, _phc._lrg_map);
 300             } else {
 301               const RegMask *rm = C->matcher()->idealreg2spillmask[m->ideal_reg()];
 302               copy = new (C) MachSpillCopyNode(m, *rm, *rm);
 303               // Find a good place to insert.  Kinda tricky, use a subroutine
 304               insert_copy_with_overlap(pred,copy,phi_name,src_name);
 305             }
 306             // Insert the copy in the use-def chain
 307             n->set_req(j, copy);
 308             _phc._cfg._bbs.map( copy->_idx, pred );
 309             // Extend ("register allocate") the names array for the copy.
 310             _phc._lrg_map.extend(copy->_idx, phi_name);
 311           } // End of if Phi names do not match
 312         } // End of for all inputs to Phi
 313       } else { // End of if Phi
 314 
 315         // Now check for 2-address instructions
 316         uint idx;
 317         if( n->is_Mach() && (idx=n->as_Mach()->two_adr()) ) {
 318           // Get the chosen name for the Node
 319           uint name = _phc._lrg_map.find(n);
 320           assert (name, "no 2-address specials");
 321           // Check for name mis-match on the 2-address input
 322           Node *m = n->in(idx);
 323           if (_phc._lrg_map.find(m) != name) {
 324             Node *copy;
 325             assert(!m->is_Con() || m->is_Mach(), "all Con must be Mach");
 326             // At this point it is unsafe to extend live ranges (6550579).
 327             // Rematerialize only constants as we do for Phi above.
 328             if(m->is_Mach() && m->as_Mach()->is_Con() &&
 329                m->as_Mach()->rematerialize()) {
 330               copy = m->clone();
 331               // Insert the copy in the basic block, just before us
 332               b->_nodes.insert(l++, copy);
 333               if(_phc.clone_projs(b, l, m, copy, _phc._lrg_map)) {
 334                 l++;
 335               }
 336             } else {
 337               const RegMask *rm = C->matcher()->idealreg2spillmask[m->ideal_reg()];
 338               copy = new (C) MachSpillCopyNode(m, *rm, *rm);
 339               // Insert the copy in the basic block, just before us
 340               b->_nodes.insert(l++, copy);
 341             }
 342             // Insert the copy in the use-def chain
 343             n->set_req(idx, copy);
 344             // Extend ("register allocate") the names array for the copy.
 345             _phc._lrg_map.extend(copy->_idx, name);
 346             _phc._cfg._bbs.map( copy->_idx, b );
 347           }
 348 
 349         } // End of is two-adr
 350 
 351         // Insert a copy at a debug use for a lrg which has high frequency
 352         if (b->_freq < OPTO_DEBUG_SPLIT_FREQ || b->is_uncommon(_phc._cfg._bbs)) {
 353           // Walk the debug inputs to the node and check for lrg freq
 354           JVMState* jvms = n->jvms();
 355           uint debug_start = jvms ? jvms->debug_start() : 999999;
 356           uint debug_end   = jvms ? jvms->debug_end()   : 999999;
 357           for(uint inpidx = debug_start; inpidx < debug_end; inpidx++) {
 358             // Do not split monitors; they are only needed for debug table
 359             // entries and need no code.
 360             if (jvms->is_monitor_use(inpidx)) {
 361               continue;
 362             }
 363             Node *inp = n->in(inpidx);
 364             uint nidx = _phc._lrg_map.live_range_id(inp);
 365             LRG &lrg = lrgs(nidx);
 366 
 367             // If this lrg has a high frequency use/def
 368             if( lrg._maxfreq >= _phc.high_frequency_lrg() ) {
 369               // If the live range is also live out of this block (like it
 370               // would be for a fast/slow idiom), the normal spill mechanism
 371               // does an excellent job.  If it is not live out of this block
 372               // (like it would be for debug info to uncommon trap) splitting


 374               // frequency blocks.
 375               //   Build_IFG_virtual has converted the live sets to
 376               // live-IN info, not live-OUT info.
 377               uint k;
 378               for( k=0; k < b->_num_succs; k++ )
 379                 if( _phc._live->live(b->_succs[k])->member( nidx ) )
 380                   break;      // Live in to some successor block?
 381               if( k < b->_num_succs )
 382                 continue;     // Live out; do not pre-split
 383               // Split the lrg at this use
 384               const RegMask *rm = C->matcher()->idealreg2spillmask[inp->ideal_reg()];
 385               Node *copy = new (C) MachSpillCopyNode( inp, *rm, *rm );
 386               // Insert the copy in the use-def chain
 387               n->set_req(inpidx, copy );
 388               // Insert the copy in the basic block, just before us
 389               b->_nodes.insert( l++, copy );
 390               // Extend ("register allocate") the names array for the copy.
 391               uint max_lrg_id = _phc._lrg_map.max_lrg_id();
 392               _phc.new_lrg(copy, max_lrg_id);
 393               _phc._lrg_map.set_max_lrg_id(max_lrg_id + 1);
 394               _phc._cfg._bbs.map(copy->_idx, b);
 395               //tty->print_cr("Split a debug use in Aggressive Coalesce");
 396             }  // End of if high frequency use/def
 397           }  // End of for all debug inputs
 398         }  // End of if low frequency safepoint
 399 
 400       } // End of if Phi
 401 
 402     } // End of for all instructions
 403   } // End of for all blocks
 404 }
 405 
 406 //=============================================================================
 407 //------------------------------coalesce---------------------------------------
 408 // Aggressive (but pessimistic) copy coalescing of a single block
 409 
 410 // The following coalesce pass represents a single round of aggressive
 411 // pessimistic coalesce.  "Aggressive" means no attempt to preserve
 412 // colorability when coalescing.  This occasionally means more spills, but
 413 // it also means fewer rounds of coalescing for better code - and that means
 414 // faster compiles.


 420 // into one big live range, then check for self-interference.  Everywhere
 421 // the live range interferes with self it would have to be split.  Finding
 422 // the right split points can be done with some heuristics (based on
 423 // expected frequency of edges in the live range).  In short, it's a real
 424 // research problem and the timeline is too short to allow such research.
 425 // Further thoughts: (1) build the LR in a pass, (2) find self-interference
 426 // in another pass, (3) per each self-conflict, split, (4) split by finding
 427 // the low-cost cut (min-cut) of the LR, (5) edges in the LR are weighted
 428 // according to the GCM algorithm (or just exec freq on CFG edges).
 429 
 430 void PhaseAggressiveCoalesce::coalesce( Block *b ) {
 431   // Copies are still "virtual" - meaning we have not made them explicitly
 432   // copies.  Instead, Phi functions of successor blocks have mis-matched
 433   // live-ranges.  If I fail to coalesce, I'll have to insert a copy to line
 434   // up the live-ranges.  Check for Phis in successor blocks.
 435   uint i;
 436   for( i=0; i<b->_num_succs; i++ ) {
 437     Block *bs = b->_succs[i];
 438     // Find index of 'b' in 'bs' predecessors
 439     uint j=1;
 440     while( _phc._cfg._bbs[bs->pred(j)->_idx] != b ) j++;



 441     // Visit all the Phis in successor block
 442     for( uint k = 1; k<bs->_nodes.size(); k++ ) {
 443       Node *n = bs->_nodes[k];
 444       if( !n->is_Phi() ) break;
 445       combine_these_two( n, n->in(j) );
 446     }
 447   } // End of for all successor blocks
 448 
 449 
 450   // Check _this_ block for 2-address instructions and copies.
 451   uint cnt = b->end_idx();
 452   for( i = 1; i<cnt; i++ ) {
 453     Node *n = b->_nodes[i];
 454     uint idx;
 455     // 2-address instructions have a virtual Copy matching their input
 456     // to their output
 457     if (n->is_Mach() && (idx = n->as_Mach()->two_adr())) {
 458       MachNode *mach = n->as_Mach();
 459       combine_these_two(mach, mach->in(idx));
 460     }


 493   lrgs(lr1)._is_oop |= lrgs(lr2)._is_oop;
 494   lrgs(lr2)._is_oop = 0;    // In particular, not an oop for GC info
 495 
 496   if (lrgs(lr1)._maxfreq < lrgs(lr2)._maxfreq)
 497     lrgs(lr1)._maxfreq = lrgs(lr2)._maxfreq;
 498 
 499   // Copy original value instead.  Intermediate copies go dead, and
 500   // the dst_copy becomes useless.
 501   int didx = dst_copy->is_Copy();
 502   dst_copy->set_req( didx, src_def );
 503   // Add copy to free list
 504   // _phc.free_spillcopy(b->_nodes[bindex]);
 505   assert( b->_nodes[bindex] == dst_copy, "" );
 506   dst_copy->replace_by( dst_copy->in(didx) );
 507   dst_copy->set_req( didx, NULL);
 508   b->_nodes.remove(bindex);
 509   if( bindex < b->_ihrp_index ) b->_ihrp_index--;
 510   if( bindex < b->_fhrp_index ) b->_fhrp_index--;
 511 
 512   // Stretched lr1; add it to liveness of intermediate blocks
 513   Block *b2 = _phc._cfg._bbs[src_copy->_idx];
 514   while( b != b2 ) {
 515     b = _phc._cfg._bbs[b->pred(1)->_idx];
 516     _phc._live->live(b)->insert(lr1);
 517   }
 518 }
 519 
 520 //------------------------------compute_separating_interferences---------------
 521 // Factored code from copy_copy that computes extra interferences from
 522 // lengthening a live range by double-coalescing.
 523 uint PhaseConservativeCoalesce::compute_separating_interferences(Node *dst_copy, Node *src_copy, Block *b, uint bindex, RegMask &rm, uint reg_degree, uint rm_size, uint lr1, uint lr2 ) {
 524 
 525   assert(!lrgs(lr1)._fat_proj, "cannot coalesce fat_proj");
 526   assert(!lrgs(lr2)._fat_proj, "cannot coalesce fat_proj");
 527   Node *prev_copy = dst_copy->in(dst_copy->is_Copy());
 528   Block *b2 = b;
 529   uint bindex2 = bindex;
 530   while( 1 ) {
 531     // Find previous instruction
 532     bindex2--;                  // Chain backwards 1 instruction
 533     while( bindex2 == 0 ) {     // At block start, find prior block
 534       assert( b2->num_preds() == 2, "cannot double coalesce across c-flow" );
 535       b2 = _phc._cfg._bbs[b2->pred(1)->_idx];
 536       bindex2 = b2->end_idx()-1;
 537     }
 538     // Get prior instruction
 539     assert(bindex2 < b2->_nodes.size(), "index out of bounds");
 540     Node *x = b2->_nodes[bindex2];
 541     if( x == prev_copy ) {      // Previous copy in copy chain?
 542       if( prev_copy == src_copy)// Found end of chain and all interferences
 543         break;                  // So break out of loop
 544       // Else work back one in copy chain
 545       prev_copy = prev_copy->in(prev_copy->is_Copy());
 546     } else {                    // Else collect interferences
 547       uint lidx = _phc._lrg_map.find(x);
 548       // Found another def of live-range being stretched?
 549       if(lidx == lr1) {
 550         return max_juint;
 551       }
 552       if(lidx == lr2) {
 553         return max_juint;
 554       }
 555 


 659     return false;
 660   }
 661 
 662   // Sort; use smaller live-range number
 663   Node *lr1_node = dst_copy;
 664   Node *lr2_node = src_def;
 665   if (lr1 > lr2) {
 666     uint tmp = lr1; lr1 = lr2; lr2 = tmp;
 667     lr1_node = src_def;  lr2_node = dst_copy;
 668   }
 669 
 670   // Check for compatibility of the 2 live ranges by
 671   // intersecting their allowed register sets.
 672   RegMask rm = lrgs(lr1).mask();
 673   rm.AND(lrgs(lr2).mask());
 674   // Number of bits free
 675   uint rm_size = rm.Size();
 676 
 677   if (UseFPUForSpilling && rm.is_AllStack() ) {
 678     // Don't coalesce when frequency difference is large
 679     Block *dst_b = _phc._cfg._bbs[dst_copy->_idx];
 680     Block *src_def_b = _phc._cfg._bbs[src_def->_idx];
 681     if (src_def_b->_freq > 10*dst_b->_freq )
 682       return false;
 683   }
 684 
 685   // If we can use any stack slot, then effective size is infinite
 686   if( rm.is_AllStack() ) rm_size += 1000000;
 687   // Incompatible masks, no way to coalesce
 688   if( rm_size == 0 ) return false;
 689 
 690   // Another early bail-out test is when we are double-coalescing and the
 691   // 2 copies are separated by some control flow.
 692   if( dst_copy != src_copy ) {
 693     Block *src_b = _phc._cfg._bbs[src_copy->_idx];
 694     Block *b2 = b;
 695     while( b2 != src_b ) {
 696       if( b2->num_preds() > 2 ){// Found merge-point
 697         _phc._lost_opp_cflow_coalesce++;
 698         // extra record_bias commented out because Chris believes it is not
 699         // productive.  Since we can record only 1 bias, we want to choose one
 700         // that stands a chance of working and this one probably does not.
 701         //record_bias( _phc._lrgs, lr1, lr2 );
 702         return false;           // To hard to find all interferences
 703       }
 704       b2 = _phc._cfg._bbs[b2->pred(1)->_idx];
 705     }
 706   }
 707 
 708   // Union the two interference sets together into '_ulr'
 709   uint reg_degree = _ulr.lrg_union( lr1, lr2, rm_size, _phc._ifg, rm );
 710 
 711   if( reg_degree >= rm_size ) {
 712     record_bias( _phc._ifg, lr1, lr2 );
 713     return false;
 714   }
 715 
 716   // Now I need to compute all the interferences between dst_copy and
 717   // src_copy.  I'm not willing visit the entire interference graph, so
 718   // I limit my search to things in dst_copy's block or in a straight
 719   // line of previous blocks.  I give up at merge points or when I get
 720   // more interferences than my degree.  I can stop when I find src_copy.
 721   if( dst_copy != src_copy ) {
 722     reg_degree = compute_separating_interferences(dst_copy, src_copy, b, bindex, rm, rm_size, reg_degree, lr1, lr2 );
 723     if( reg_degree == max_juint ) {
 724       record_bias( _phc._ifg, lr1, lr2 );


 769   lrgs(lr1).set_mask(rm);
 770   lrgs(lr1).compute_set_mask_size();
 771   lrgs(lr1)._cost += lrgs(lr2)._cost;
 772   lrgs(lr1)._area += lrgs(lr2)._area;
 773 
 774   // While its uncommon to successfully coalesce live ranges that started out
 775   // being not-lo-degree, it can happen.  In any case the combined coalesced
 776   // live range better Simplify nicely.
 777   lrgs(lr1)._was_lo = 1;
 778 
 779   // kinda expensive to do all the time
 780   //tty->print_cr("warning: slow verify happening");
 781   //_phc._ifg->verify( &_phc );
 782   return true;
 783 }
 784 
 785 //------------------------------coalesce---------------------------------------
 786 // Conservative (but pessimistic) copy coalescing of a single block
 787 void PhaseConservativeCoalesce::coalesce( Block *b ) {
 788   // Bail out on infrequent blocks
 789   if( b->is_uncommon(_phc._cfg._bbs) )
 790     return;

 791   // Check this block for copies.
 792   for( uint i = 1; i<b->end_idx(); i++ ) {
 793     // Check for actual copies on inputs.  Coalesce a copy into its
 794     // input if use and copy's input are compatible.
 795     Node *copy1 = b->_nodes[i];
 796     uint idx1 = copy1->is_Copy();
 797     if( !idx1 ) continue;       // Not a copy
 798 
 799     if( copy_copy(copy1,copy1,b,i) ) {
 800       i--;                      // Retry, same location in block
 801       PhaseChaitin::_conserv_coalesce++;  // Collect stats on success
 802       continue;
 803     }
 804   }
 805 }


  35 #include "opto/regmask.hpp"
  36 
  37 //=============================================================================
  38 //------------------------------Dump-------------------------------------------
  39 #ifndef PRODUCT
  40 void PhaseCoalesce::dump(Node *n) const {
  41   // Being a const function means I cannot use 'Find'
  42   uint r = _phc._lrg_map.find(n);
  43   tty->print("L%d/N%d ",r,n->_idx);
  44 }
  45 
  46 //------------------------------dump-------------------------------------------
  47 void PhaseCoalesce::dump() const {
  48   // I know I have a block layout now, so I can print blocks in a loop
  49   for( uint i=0; i<_phc._cfg._num_blocks; i++ ) {
  50     uint j;
  51     Block *b = _phc._cfg._blocks[i];
  52     // Print a nice block header
  53     tty->print("B%d: ",b->_pre_order);
  54     for( j=1; j<b->num_preds(); j++ )
  55       tty->print("B%d ", _phc._cfg.get_block_for_node(b->pred(j))->_pre_order);
  56     tty->print("-> ");
  57     for( j=0; j<b->_num_succs; j++ )
  58       tty->print("B%d ",b->_succs[j]->_pre_order);
  59     tty->print(" IDom: B%d/#%d\n", b->_idom ? b->_idom->_pre_order : 0, b->_dom_depth);
  60     uint cnt = b->_nodes.size();
  61     for( j=0; j<cnt; j++ ) {
  62       Node *n = b->_nodes[j];
  63       dump( n );
  64       tty->print("\t%s\t",n->Name());
  65 
  66       // Dump the inputs
  67       uint k;                   // Exit value of loop
  68       for( k=0; k<n->req(); k++ ) // For all required inputs
  69         if( n->in(k) ) dump( n->in(k) );
  70         else tty->print("_ ");
  71       int any_prec = 0;
  72       for( ; k<n->len(); k++ )          // For all precedence inputs
  73         if( n->in(k) ) {
  74           if( !any_prec++ ) tty->print(" |");
  75           dump( n->in(k) );


 191     if (_phc._lrg_map.find(n) == src_name) {
 192       kill_src_idx = i;
 193       break;
 194     }
 195     i--;
 196   }
 197   // Need a temp?  Last use of dst comes after the kill of src?
 198   if (last_use_idx >= kill_src_idx) {
 199     // Need to break a cycle with a temp
 200     uint idx = copy->is_Copy();
 201     Node *tmp = copy->clone();
 202     uint max_lrg_id = _phc._lrg_map.max_lrg_id();
 203     _phc.new_lrg(tmp, max_lrg_id);
 204     _phc._lrg_map.set_max_lrg_id(max_lrg_id + 1);
 205 
 206     // Insert new temp between copy and source
 207     tmp ->set_req(idx,copy->in(idx));
 208     copy->set_req(idx,tmp);
 209     // Save source in temp early, before source is killed
 210     b->_nodes.insert(kill_src_idx,tmp);
 211     _phc._cfg.map_node_to_block(tmp, b);
 212     last_use_idx++;
 213   }
 214 
 215   // Insert just after last use
 216   b->_nodes.insert(last_use_idx+1,copy);
 217 }
 218 
 219 //------------------------------insert_copies----------------------------------
 220 void PhaseAggressiveCoalesce::insert_copies( Matcher &matcher ) {
 221   // We do LRGs compressing and fix a liveout data only here since the other
 222   // place in Split() is guarded by the assert which we never hit.
 223   _phc._lrg_map.compress_uf_map_for_nodes();
 224   // Fix block's liveout data for compressed live ranges.
 225   for (uint lrg = 1; lrg < _phc._lrg_map.max_lrg_id(); lrg++) {
 226     uint compressed_lrg = _phc._lrg_map.find(lrg);
 227     if (lrg != compressed_lrg) {
 228       for (uint bidx = 0; bidx < _phc._cfg._num_blocks; bidx++) {
 229         IndexSet *liveout = _phc._live->live(_phc._cfg._blocks[bidx]);
 230         if (liveout->member(lrg)) {
 231           liveout->remove(lrg);


 269           n->replace_by(def);
 270           n->set_req(cidx,NULL);
 271           b->_nodes.remove(l);
 272           l--;
 273           continue;
 274         }
 275       }
 276 
 277       if (n->is_Phi()) {
 278         // Get the chosen name for the Phi
 279         uint phi_name = _phc._lrg_map.find(n);
 280         // Ignore the pre-allocated specials
 281         if (!phi_name) {
 282           continue;
 283         }
 284         // Check for mismatch inputs to Phi
 285         for (uint j = 1; j < cnt; j++) {
 286           Node *m = n->in(j);
 287           uint src_name = _phc._lrg_map.find(m);
 288           if (src_name != phi_name) {
 289             Block *pred = _phc._cfg.get_block_for_node(b->pred(j));
 290             Node *copy;
 291             assert(!m->is_Con() || m->is_Mach(), "all Con must be Mach");
 292             // Rematerialize constants instead of copying them
 293             if( m->is_Mach() && m->as_Mach()->is_Con() &&
 294                 m->as_Mach()->rematerialize() ) {
 295               copy = m->clone();
 296               // Insert the copy in the predecessor basic block
 297               pred->add_inst(copy);
 298               // Copy any flags as well
 299               _phc.clone_projs(pred, pred->end_idx(), m, copy, _phc._lrg_map);
 300             } else {
 301               const RegMask *rm = C->matcher()->idealreg2spillmask[m->ideal_reg()];
 302               copy = new (C) MachSpillCopyNode(m, *rm, *rm);
 303               // Find a good place to insert.  Kinda tricky, use a subroutine
 304               insert_copy_with_overlap(pred,copy,phi_name,src_name);
 305             }
 306             // Insert the copy in the use-def chain
 307             n->set_req(j, copy);
 308             _phc._cfg.map_node_to_block(copy, pred);
 309             // Extend ("register allocate") the names array for the copy.
 310             _phc._lrg_map.extend(copy->_idx, phi_name);
 311           } // End of if Phi names do not match
 312         } // End of for all inputs to Phi
 313       } else { // End of if Phi
 314 
 315         // Now check for 2-address instructions
 316         uint idx;
 317         if( n->is_Mach() && (idx=n->as_Mach()->two_adr()) ) {
 318           // Get the chosen name for the Node
 319           uint name = _phc._lrg_map.find(n);
 320           assert (name, "no 2-address specials");
 321           // Check for name mis-match on the 2-address input
 322           Node *m = n->in(idx);
 323           if (_phc._lrg_map.find(m) != name) {
 324             Node *copy;
 325             assert(!m->is_Con() || m->is_Mach(), "all Con must be Mach");
 326             // At this point it is unsafe to extend live ranges (6550579).
 327             // Rematerialize only constants as we do for Phi above.
 328             if(m->is_Mach() && m->as_Mach()->is_Con() &&
 329                m->as_Mach()->rematerialize()) {
 330               copy = m->clone();
 331               // Insert the copy in the basic block, just before us
 332               b->_nodes.insert(l++, copy);
 333               if(_phc.clone_projs(b, l, m, copy, _phc._lrg_map)) {
 334                 l++;
 335               }
 336             } else {
 337               const RegMask *rm = C->matcher()->idealreg2spillmask[m->ideal_reg()];
 338               copy = new (C) MachSpillCopyNode(m, *rm, *rm);
 339               // Insert the copy in the basic block, just before us
 340               b->_nodes.insert(l++, copy);
 341             }
 342             // Insert the copy in the use-def chain
 343             n->set_req(idx, copy);
 344             // Extend ("register allocate") the names array for the copy.
 345             _phc._lrg_map.extend(copy->_idx, name);
 346             _phc._cfg.map_node_to_block(copy, b);
 347           }
 348 
 349         } // End of is two-adr
 350 
 351         // Insert a copy at a debug use for a lrg which has high frequency
 352         if (b->_freq < OPTO_DEBUG_SPLIT_FREQ || b->is_uncommon(&_phc._cfg)) {
 353           // Walk the debug inputs to the node and check for lrg freq
 354           JVMState* jvms = n->jvms();
 355           uint debug_start = jvms ? jvms->debug_start() : 999999;
 356           uint debug_end   = jvms ? jvms->debug_end()   : 999999;
 357           for(uint inpidx = debug_start; inpidx < debug_end; inpidx++) {
 358             // Do not split monitors; they are only needed for debug table
 359             // entries and need no code.
 360             if (jvms->is_monitor_use(inpidx)) {
 361               continue;
 362             }
 363             Node *inp = n->in(inpidx);
 364             uint nidx = _phc._lrg_map.live_range_id(inp);
 365             LRG &lrg = lrgs(nidx);
 366 
 367             // If this lrg has a high frequency use/def
 368             if( lrg._maxfreq >= _phc.high_frequency_lrg() ) {
 369               // If the live range is also live out of this block (like it
 370               // would be for a fast/slow idiom), the normal spill mechanism
 371               // does an excellent job.  If it is not live out of this block
 372               // (like it would be for debug info to uncommon trap) splitting


 374               // frequency blocks.
 375               //   Build_IFG_virtual has converted the live sets to
 376               // live-IN info, not live-OUT info.
 377               uint k;
 378               for( k=0; k < b->_num_succs; k++ )
 379                 if( _phc._live->live(b->_succs[k])->member( nidx ) )
 380                   break;      // Live in to some successor block?
 381               if( k < b->_num_succs )
 382                 continue;     // Live out; do not pre-split
 383               // Split the lrg at this use
 384               const RegMask *rm = C->matcher()->idealreg2spillmask[inp->ideal_reg()];
 385               Node *copy = new (C) MachSpillCopyNode( inp, *rm, *rm );
 386               // Insert the copy in the use-def chain
 387               n->set_req(inpidx, copy );
 388               // Insert the copy in the basic block, just before us
 389               b->_nodes.insert( l++, copy );
 390               // Extend ("register allocate") the names array for the copy.
 391               uint max_lrg_id = _phc._lrg_map.max_lrg_id();
 392               _phc.new_lrg(copy, max_lrg_id);
 393               _phc._lrg_map.set_max_lrg_id(max_lrg_id + 1);
 394               _phc._cfg.map_node_to_block(copy, b);
 395               //tty->print_cr("Split a debug use in Aggressive Coalesce");
 396             }  // End of if high frequency use/def
 397           }  // End of for all debug inputs
 398         }  // End of if low frequency safepoint
 399 
 400       } // End of if Phi
 401 
 402     } // End of for all instructions
 403   } // End of for all blocks
 404 }
 405 
 406 //=============================================================================
 407 //------------------------------coalesce---------------------------------------
 408 // Aggressive (but pessimistic) copy coalescing of a single block
 409 
 410 // The following coalesce pass represents a single round of aggressive
 411 // pessimistic coalesce.  "Aggressive" means no attempt to preserve
 412 // colorability when coalescing.  This occasionally means more spills, but
 413 // it also means fewer rounds of coalescing for better code - and that means
 414 // faster compiles.


 420 // into one big live range, then check for self-interference.  Everywhere
 421 // the live range interferes with self it would have to be split.  Finding
 422 // the right split points can be done with some heuristics (based on
 423 // expected frequency of edges in the live range).  In short, it's a real
 424 // research problem and the timeline is too short to allow such research.
 425 // Further thoughts: (1) build the LR in a pass, (2) find self-interference
 426 // in another pass, (3) per each self-conflict, split, (4) split by finding
 427 // the low-cost cut (min-cut) of the LR, (5) edges in the LR are weighted
 428 // according to the GCM algorithm (or just exec freq on CFG edges).
 429 
 430 void PhaseAggressiveCoalesce::coalesce( Block *b ) {
 431   // Copies are still "virtual" - meaning we have not made them explicitly
 432   // copies.  Instead, Phi functions of successor blocks have mis-matched
 433   // live-ranges.  If I fail to coalesce, I'll have to insert a copy to line
 434   // up the live-ranges.  Check for Phis in successor blocks.
 435   uint i;
 436   for( i=0; i<b->_num_succs; i++ ) {
 437     Block *bs = b->_succs[i];
 438     // Find index of 'b' in 'bs' predecessors
 439     uint j=1;
 440     while (_phc._cfg.get_block_for_node(bs->pred(j)) != b) {
 441       j++;
 442     }
 443 
 444     // Visit all the Phis in successor block
 445     for( uint k = 1; k<bs->_nodes.size(); k++ ) {
 446       Node *n = bs->_nodes[k];
 447       if( !n->is_Phi() ) break;
 448       combine_these_two( n, n->in(j) );
 449     }
 450   } // End of for all successor blocks
 451 
 452 
 453   // Check _this_ block for 2-address instructions and copies.
 454   uint cnt = b->end_idx();
 455   for( i = 1; i<cnt; i++ ) {
 456     Node *n = b->_nodes[i];
 457     uint idx;
 458     // 2-address instructions have a virtual Copy matching their input
 459     // to their output
 460     if (n->is_Mach() && (idx = n->as_Mach()->two_adr())) {
 461       MachNode *mach = n->as_Mach();
 462       combine_these_two(mach, mach->in(idx));
 463     }


 496   lrgs(lr1)._is_oop |= lrgs(lr2)._is_oop;
 497   lrgs(lr2)._is_oop = 0;    // In particular, not an oop for GC info
 498 
 499   if (lrgs(lr1)._maxfreq < lrgs(lr2)._maxfreq)
 500     lrgs(lr1)._maxfreq = lrgs(lr2)._maxfreq;
 501 
 502   // Copy original value instead.  Intermediate copies go dead, and
 503   // the dst_copy becomes useless.
 504   int didx = dst_copy->is_Copy();
 505   dst_copy->set_req( didx, src_def );
 506   // Add copy to free list
 507   // _phc.free_spillcopy(b->_nodes[bindex]);
 508   assert( b->_nodes[bindex] == dst_copy, "" );
 509   dst_copy->replace_by( dst_copy->in(didx) );
 510   dst_copy->set_req( didx, NULL);
 511   b->_nodes.remove(bindex);
 512   if( bindex < b->_ihrp_index ) b->_ihrp_index--;
 513   if( bindex < b->_fhrp_index ) b->_fhrp_index--;
 514 
 515   // Stretched lr1; add it to liveness of intermediate blocks
 516   Block *b2 = _phc._cfg.get_block_for_node(src_copy);
 517   while( b != b2 ) {
 518     b = _phc._cfg.get_block_for_node(b->pred(1));
 519     _phc._live->live(b)->insert(lr1);
 520   }
 521 }
 522 
 523 //------------------------------compute_separating_interferences---------------
 524 // Factored code from copy_copy that computes extra interferences from
 525 // lengthening a live range by double-coalescing.
 526 uint PhaseConservativeCoalesce::compute_separating_interferences(Node *dst_copy, Node *src_copy, Block *b, uint bindex, RegMask &rm, uint reg_degree, uint rm_size, uint lr1, uint lr2 ) {
 527 
 528   assert(!lrgs(lr1)._fat_proj, "cannot coalesce fat_proj");
 529   assert(!lrgs(lr2)._fat_proj, "cannot coalesce fat_proj");
 530   Node *prev_copy = dst_copy->in(dst_copy->is_Copy());
 531   Block *b2 = b;
 532   uint bindex2 = bindex;
 533   while( 1 ) {
 534     // Find previous instruction
 535     bindex2--;                  // Chain backwards 1 instruction
 536     while( bindex2 == 0 ) {     // At block start, find prior block
 537       assert( b2->num_preds() == 2, "cannot double coalesce across c-flow" );
 538       b2 = _phc._cfg.get_block_for_node(b2->pred(1));
 539       bindex2 = b2->end_idx()-1;
 540     }
 541     // Get prior instruction
 542     assert(bindex2 < b2->_nodes.size(), "index out of bounds");
 543     Node *x = b2->_nodes[bindex2];
 544     if( x == prev_copy ) {      // Previous copy in copy chain?
 545       if( prev_copy == src_copy)// Found end of chain and all interferences
 546         break;                  // So break out of loop
 547       // Else work back one in copy chain
 548       prev_copy = prev_copy->in(prev_copy->is_Copy());
 549     } else {                    // Else collect interferences
 550       uint lidx = _phc._lrg_map.find(x);
 551       // Found another def of live-range being stretched?
 552       if(lidx == lr1) {
 553         return max_juint;
 554       }
 555       if(lidx == lr2) {
 556         return max_juint;
 557       }
 558 


 662     return false;
 663   }
 664 
 665   // Sort; use smaller live-range number
 666   Node *lr1_node = dst_copy;
 667   Node *lr2_node = src_def;
 668   if (lr1 > lr2) {
 669     uint tmp = lr1; lr1 = lr2; lr2 = tmp;
 670     lr1_node = src_def;  lr2_node = dst_copy;
 671   }
 672 
 673   // Check for compatibility of the 2 live ranges by
 674   // intersecting their allowed register sets.
 675   RegMask rm = lrgs(lr1).mask();
 676   rm.AND(lrgs(lr2).mask());
 677   // Number of bits free
 678   uint rm_size = rm.Size();
 679 
 680   if (UseFPUForSpilling && rm.is_AllStack() ) {
 681     // Don't coalesce when frequency difference is large
 682     Block *dst_b = _phc._cfg.get_block_for_node(dst_copy);
 683     Block *src_def_b = _phc._cfg.get_block_for_node(src_def);
 684     if (src_def_b->_freq > 10*dst_b->_freq )
 685       return false;
 686   }
 687 
 688   // If we can use any stack slot, then effective size is infinite
 689   if( rm.is_AllStack() ) rm_size += 1000000;
 690   // Incompatible masks, no way to coalesce
 691   if( rm_size == 0 ) return false;
 692 
 693   // Another early bail-out test is when we are double-coalescing and the
 694   // 2 copies are separated by some control flow.
 695   if( dst_copy != src_copy ) {
 696     Block *src_b = _phc._cfg.get_block_for_node(src_copy);
 697     Block *b2 = b;
 698     while( b2 != src_b ) {
 699       if( b2->num_preds() > 2 ){// Found merge-point
 700         _phc._lost_opp_cflow_coalesce++;
 701         // extra record_bias commented out because Chris believes it is not
 702         // productive.  Since we can record only 1 bias, we want to choose one
 703         // that stands a chance of working and this one probably does not.
 704         //record_bias( _phc._lrgs, lr1, lr2 );
 705         return false;           // To hard to find all interferences
 706       }
 707       b2 = _phc._cfg.get_block_for_node(b2->pred(1));
 708     }
 709   }
 710 
 711   // Union the two interference sets together into '_ulr'
 712   uint reg_degree = _ulr.lrg_union( lr1, lr2, rm_size, _phc._ifg, rm );
 713 
 714   if( reg_degree >= rm_size ) {
 715     record_bias( _phc._ifg, lr1, lr2 );
 716     return false;
 717   }
 718 
 719   // Now I need to compute all the interferences between dst_copy and
 720   // src_copy.  I'm not willing visit the entire interference graph, so
 721   // I limit my search to things in dst_copy's block or in a straight
 722   // line of previous blocks.  I give up at merge points or when I get
 723   // more interferences than my degree.  I can stop when I find src_copy.
 724   if( dst_copy != src_copy ) {
 725     reg_degree = compute_separating_interferences(dst_copy, src_copy, b, bindex, rm, rm_size, reg_degree, lr1, lr2 );
 726     if( reg_degree == max_juint ) {
 727       record_bias( _phc._ifg, lr1, lr2 );


 772   lrgs(lr1).set_mask(rm);
 773   lrgs(lr1).compute_set_mask_size();
 774   lrgs(lr1)._cost += lrgs(lr2)._cost;
 775   lrgs(lr1)._area += lrgs(lr2)._area;
 776 
 777   // While its uncommon to successfully coalesce live ranges that started out
 778   // being not-lo-degree, it can happen.  In any case the combined coalesced
 779   // live range better Simplify nicely.
 780   lrgs(lr1)._was_lo = 1;
 781 
 782   // kinda expensive to do all the time
 783   //tty->print_cr("warning: slow verify happening");
 784   //_phc._ifg->verify( &_phc );
 785   return true;
 786 }
 787 
 788 //------------------------------coalesce---------------------------------------
 789 // Conservative (but pessimistic) copy coalescing of a single block
 790 void PhaseConservativeCoalesce::coalesce( Block *b ) {
 791   // Bail out on infrequent blocks
 792   if (b->is_uncommon(&_phc._cfg)) {
 793     return;
 794   }
 795   // Check this block for copies.
 796   for( uint i = 1; i<b->end_idx(); i++ ) {
 797     // Check for actual copies on inputs.  Coalesce a copy into its
 798     // input if use and copy's input are compatible.
 799     Node *copy1 = b->_nodes[i];
 800     uint idx1 = copy1->is_Copy();
 801     if( !idx1 ) continue;       // Not a copy
 802 
 803     if( copy_copy(copy1,copy1,b,i) ) {
 804       i--;                      // Retry, same location in block
 805       PhaseChaitin::_conserv_coalesce++;  // Collect stats on success
 806       continue;
 807     }
 808   }
 809 }
src/share/vm/opto/coalesce.cpp
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