1 /*
   2  * Copyright (c) 2000, 2013, Oracle and/or its affiliates. All rights reserved.
   3  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   4  *
   5  * This code is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 only, as
   7  * published by the Free Software Foundation.
   8  *
   9  * This code is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  * version 2 for more details (a copy is included in the LICENSE file that
  13  * accompanied this code).
  14  *
  15  * You should have received a copy of the GNU General Public License version
  16  * 2 along with this work; if not, write to the Free Software Foundation,
  17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  18  *
  19  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  20  * or visit www.oracle.com if you need additional information or have any
  21  * questions.
  22  *
  23  */
  24 
  25 #include "precompiled.hpp"
  26 #include "compiler/compileLog.hpp"
  27 #include "compiler/oopMap.hpp"
  28 #include "memory/allocation.inline.hpp"
  29 #include "opto/addnode.hpp"
  30 #include "opto/block.hpp"
  31 #include "opto/callnode.hpp"
  32 #include "opto/cfgnode.hpp"
  33 #include "opto/chaitin.hpp"
  34 #include "opto/coalesce.hpp"
  35 #include "opto/connode.hpp"
  36 #include "opto/idealGraphPrinter.hpp"
  37 #include "opto/indexSet.hpp"
  38 #include "opto/machnode.hpp"
  39 #include "opto/memnode.hpp"
  40 #include "opto/opcodes.hpp"
  41 #include "opto/rootnode.hpp"
  42 
  43 //=============================================================================
  44 
  45 #ifndef PRODUCT
  46 void LRG::dump( ) const {
  47   ttyLocker ttyl;
  48   tty->print("%d ",num_regs());
  49   _mask.dump();
  50   if( _msize_valid ) {
  51     if( mask_size() == compute_mask_size() ) tty->print(", #%d ",_mask_size);
  52     else tty->print(", #!!!_%d_vs_%d ",_mask_size,_mask.Size());
  53   } else {
  54     tty->print(", #?(%d) ",_mask.Size());
  55   }
  56 
  57   tty->print("EffDeg: ");
  58   if( _degree_valid ) tty->print( "%d ", _eff_degree );
  59   else tty->print("? ");
  60 
  61   if( is_multidef() ) {
  62     tty->print("MultiDef ");
  63     if (_defs != NULL) {
  64       tty->print("(");
  65       for (int i = 0; i < _defs->length(); i++) {
  66         tty->print("N%d ", _defs->at(i)->_idx);
  67       }
  68       tty->print(") ");
  69     }
  70   }
  71   else if( _def == 0 ) tty->print("Dead ");
  72   else tty->print("Def: N%d ",_def->_idx);
  73 
  74   tty->print("Cost:%4.2g Area:%4.2g Score:%4.2g ",_cost,_area, score());
  75   // Flags
  76   if( _is_oop ) tty->print("Oop ");
  77   if( _is_float ) tty->print("Float ");
  78   if( _is_vector ) tty->print("Vector ");
  79   if( _was_spilled1 ) tty->print("Spilled ");
  80   if( _was_spilled2 ) tty->print("Spilled2 ");
  81   if( _direct_conflict ) tty->print("Direct_conflict ");
  82   if( _fat_proj ) tty->print("Fat ");
  83   if( _was_lo ) tty->print("Lo ");
  84   if( _has_copy ) tty->print("Copy ");
  85   if( _at_risk ) tty->print("Risk ");
  86 
  87   if( _must_spill ) tty->print("Must_spill ");
  88   if( _is_bound ) tty->print("Bound ");
  89   if( _msize_valid ) {
  90     if( _degree_valid && lo_degree() ) tty->print("Trivial ");
  91   }
  92 
  93   tty->cr();
  94 }
  95 #endif
  96 
  97 //------------------------------score------------------------------------------
  98 // Compute score from cost and area.  Low score is best to spill.
  99 static double raw_score( double cost, double area ) {
 100   return cost - (area*RegisterCostAreaRatio) * 1.52588e-5;
 101 }
 102 
 103 double LRG::score() const {
 104   // Scale _area by RegisterCostAreaRatio/64K then subtract from cost.
 105   // Bigger area lowers score, encourages spilling this live range.
 106   // Bigger cost raise score, prevents spilling this live range.
 107   // (Note: 1/65536 is the magic constant below; I dont trust the C optimizer
 108   // to turn a divide by a constant into a multiply by the reciprical).
 109   double score = raw_score( _cost, _area);
 110 
 111   // Account for area.  Basically, LRGs covering large areas are better
 112   // to spill because more other LRGs get freed up.
 113   if( _area == 0.0 )            // No area?  Then no progress to spill
 114     return 1e35;
 115 
 116   if( _was_spilled2 )           // If spilled once before, we are unlikely
 117     return score + 1e30;        // to make progress again.
 118 
 119   if( _cost >= _area*3.0 )      // Tiny area relative to cost
 120     return score + 1e17;        // Probably no progress to spill
 121 
 122   if( (_cost+_cost) >= _area*3.0 ) // Small area relative to cost
 123     return score + 1e10;        // Likely no progress to spill
 124 
 125   return score;
 126 }
 127 
 128 //------------------------------LRG_List---------------------------------------
 129 LRG_List::LRG_List( uint max ) : _cnt(max), _max(max), _lidxs(NEW_RESOURCE_ARRAY(uint,max)) {
 130   memset( _lidxs, 0, sizeof(uint)*max );
 131 }
 132 
 133 void LRG_List::extend( uint nidx, uint lidx ) {
 134   _nesting.check();
 135   if( nidx >= _max ) {
 136     uint size = 16;
 137     while( size <= nidx ) size <<=1;
 138     _lidxs = REALLOC_RESOURCE_ARRAY( uint, _lidxs, _max, size );
 139     _max = size;
 140   }
 141   while( _cnt <= nidx )
 142     _lidxs[_cnt++] = 0;
 143   _lidxs[nidx] = lidx;
 144 }
 145 
 146 #define NUMBUCKS 3
 147 
 148 // Straight out of Tarjan's union-find algorithm
 149 uint LiveRangeMap::find_compress(uint lrg) {
 150   uint cur = lrg;
 151   uint next = _uf_map[cur];
 152   while (next != cur) { // Scan chain of equivalences
 153     assert( next < cur, "always union smaller");
 154     cur = next; // until find a fixed-point
 155     next = _uf_map[cur];
 156   }
 157 
 158   // Core of union-find algorithm: update chain of
 159   // equivalences to be equal to the root.
 160   while (lrg != next) {
 161     uint tmp = _uf_map[lrg];
 162     _uf_map.map(lrg, next);
 163     lrg = tmp;
 164   }
 165   return lrg;
 166 }
 167 
 168 // Reset the Union-Find map to identity
 169 void LiveRangeMap::reset_uf_map(uint max_lrg_id) {
 170   _max_lrg_id= max_lrg_id;
 171   // Force the Union-Find mapping to be at least this large
 172   _uf_map.extend(_max_lrg_id, 0);
 173   // Initialize it to be the ID mapping.
 174   for (uint i = 0; i < _max_lrg_id; ++i) {
 175     _uf_map.map(i, i);
 176   }
 177 }
 178 
 179 // Make all Nodes map directly to their final live range; no need for
 180 // the Union-Find mapping after this call.
 181 void LiveRangeMap::compress_uf_map_for_nodes() {
 182   // For all Nodes, compress mapping
 183   uint unique = _names.Size();
 184   for (uint i = 0; i < unique; ++i) {
 185     uint lrg = _names[i];
 186     uint compressed_lrg = find(lrg);
 187     if (lrg != compressed_lrg) {
 188       _names.map(i, compressed_lrg);
 189     }
 190   }
 191 }
 192 
 193 // Like Find above, but no path compress, so bad asymptotic behavior
 194 uint LiveRangeMap::find_const(uint lrg) const {
 195   if (!lrg) {
 196     return lrg; // Ignore the zero LRG
 197   }
 198 
 199   // Off the end?  This happens during debugging dumps when you got
 200   // brand new live ranges but have not told the allocator yet.
 201   if (lrg >= _max_lrg_id) {
 202     return lrg;
 203   }
 204 
 205   uint next = _uf_map[lrg];
 206   while (next != lrg) { // Scan chain of equivalences
 207     assert(next < lrg, "always union smaller");
 208     lrg = next; // until find a fixed-point
 209     next = _uf_map[lrg];
 210   }
 211   return next;
 212 }
 213 
 214 //------------------------------Chaitin----------------------------------------
 215 PhaseChaitin::PhaseChaitin(uint unique, PhaseCFG &cfg, Matcher &matcher)
 216   : PhaseRegAlloc(unique, cfg, matcher,
 217 #ifndef PRODUCT
 218        print_chaitin_statistics
 219 #else
 220        NULL
 221 #endif
 222        )
 223   , _lrg_map(unique)
 224   , _live(0)
 225   , _spilled_once(Thread::current()->resource_area())
 226   , _spilled_twice(Thread::current()->resource_area())
 227   , _lo_degree(0), _lo_stk_degree(0), _hi_degree(0), _simplified(0)
 228   , _oldphi(unique)
 229 #ifndef PRODUCT
 230   , _trace_spilling(TraceSpilling || C->method_has_option("TraceSpilling"))
 231 #endif
 232 {
 233   NOT_PRODUCT( Compile::TracePhase t3("ctorChaitin", &_t_ctorChaitin, TimeCompiler); )
 234 
 235   _high_frequency_lrg = MIN2(float(OPTO_LRG_HIGH_FREQ), _cfg._outer_loop_freq);
 236 
 237   // Build a list of basic blocks, sorted by frequency
 238   _blks = NEW_RESOURCE_ARRAY( Block *, _cfg._num_blocks );
 239   // Experiment with sorting strategies to speed compilation
 240   double  cutoff = BLOCK_FREQUENCY(1.0); // Cutoff for high frequency bucket
 241   Block **buckets[NUMBUCKS];             // Array of buckets
 242   uint    buckcnt[NUMBUCKS];             // Array of bucket counters
 243   double  buckval[NUMBUCKS];             // Array of bucket value cutoffs
 244   for (uint i = 0; i < NUMBUCKS; i++) {
 245     buckets[i] = NEW_RESOURCE_ARRAY(Block *, _cfg._num_blocks);
 246     buckcnt[i] = 0;
 247     // Bump by three orders of magnitude each time
 248     cutoff *= 0.001;
 249     buckval[i] = cutoff;
 250     for (uint j = 0; j < _cfg._num_blocks; j++) {
 251       buckets[i][j] = NULL;
 252     }
 253   }
 254   // Sort blocks into buckets
 255   for (uint i = 0; i < _cfg._num_blocks; i++) {
 256     for (uint j = 0; j < NUMBUCKS; j++) {
 257       if ((j == NUMBUCKS - 1) || (_cfg._blocks[i]->_freq > buckval[j])) {
 258         // Assign block to end of list for appropriate bucket
 259         buckets[j][buckcnt[j]++] = _cfg._blocks[i];
 260         break; // kick out of inner loop
 261       }
 262     }
 263   }
 264   // Dump buckets into final block array
 265   uint blkcnt = 0;
 266   for (uint i = 0; i < NUMBUCKS; i++) {
 267     for (uint j = 0; j < buckcnt[i]; j++) {
 268       _blks[blkcnt++] = buckets[i][j];
 269     }
 270   }
 271 
 272   assert(blkcnt == _cfg._num_blocks, "Block array not totally filled");
 273 }
 274 
 275 //------------------------------Union------------------------------------------
 276 // union 2 sets together.
 277 void PhaseChaitin::Union( const Node *src_n, const Node *dst_n ) {
 278   uint src = _lrg_map.find(src_n);
 279   uint dst = _lrg_map.find(dst_n);
 280   assert(src, "");
 281   assert(dst, "");
 282   assert(src < _lrg_map.max_lrg_id(), "oob");
 283   assert(dst < _lrg_map.max_lrg_id(), "oob");
 284   assert(src < dst, "always union smaller");
 285   _lrg_map.uf_map(dst, src);
 286 }
 287 
 288 //------------------------------new_lrg----------------------------------------
 289 void PhaseChaitin::new_lrg(const Node *x, uint lrg) {
 290   // Make the Node->LRG mapping
 291   _lrg_map.extend(x->_idx,lrg);
 292   // Make the Union-Find mapping an identity function
 293   _lrg_map.uf_extend(lrg, lrg);
 294 }
 295 
 296 
 297 bool PhaseChaitin::clone_projs_shared(Block *b, uint idx, Node *con, Node *copy, uint max_lrg_id) {
 298   Block* bcon = _cfg.get_block_for_node(con);
 299   uint cindex = bcon->find_node(con);
 300   Node *con_next = bcon->_nodes[cindex+1];
 301   if (con_next->in(0) != con || !con_next->is_MachProj()) {
 302     return false;               // No MachProj's follow
 303   }
 304 
 305   // Copy kills after the cloned constant
 306   Node *kills = con_next->clone();
 307   kills->set_req(0, copy);
 308   b->_nodes.insert(idx, kills);
 309   _cfg.map_node_to_block(kills, b);
 310   new_lrg(kills, max_lrg_id);
 311   return true;
 312 }
 313 
 314 //------------------------------compact----------------------------------------
 315 // Renumber the live ranges to compact them.  Makes the IFG smaller.
 316 void PhaseChaitin::compact() {
 317   // Current the _uf_map contains a series of short chains which are headed
 318   // by a self-cycle.  All the chains run from big numbers to little numbers.
 319   // The Find() call chases the chains & shortens them for the next Find call.
 320   // We are going to change this structure slightly.  Numbers above a moving
 321   // wave 'i' are unchanged.  Numbers below 'j' point directly to their
 322   // compacted live range with no further chaining.  There are no chains or
 323   // cycles below 'i', so the Find call no longer works.
 324   uint j=1;
 325   uint i;
 326   for (i = 1; i < _lrg_map.max_lrg_id(); i++) {
 327     uint lr = _lrg_map.uf_live_range_id(i);
 328     // Ignore unallocated live ranges
 329     if (!lr) {
 330       continue;
 331     }
 332     assert(lr <= i, "");
 333     _lrg_map.uf_map(i, ( lr == i ) ? j++ : _lrg_map.uf_live_range_id(lr));
 334   }
 335   // Now change the Node->LR mapping to reflect the compacted names
 336   uint unique = _lrg_map.size();
 337   for (i = 0; i < unique; i++) {
 338     uint lrg_id = _lrg_map.live_range_id(i);
 339     _lrg_map.map(i, _lrg_map.uf_live_range_id(lrg_id));
 340   }
 341 
 342   // Reset the Union-Find mapping
 343   _lrg_map.reset_uf_map(j);
 344 }
 345 
 346 void PhaseChaitin::Register_Allocate() {
 347 
 348   // Above the OLD FP (and in registers) are the incoming arguments.  Stack
 349   // slots in this area are called "arg_slots".  Above the NEW FP (and in
 350   // registers) is the outgoing argument area; above that is the spill/temp
 351   // area.  These are all "frame_slots".  Arg_slots start at the zero
 352   // stack_slots and count up to the known arg_size.  Frame_slots start at
 353   // the stack_slot #arg_size and go up.  After allocation I map stack
 354   // slots to actual offsets.  Stack-slots in the arg_slot area are biased
 355   // by the frame_size; stack-slots in the frame_slot area are biased by 0.
 356 
 357   _trip_cnt = 0;
 358   _alternate = 0;
 359   _matcher._allocation_started = true;
 360 
 361   ResourceArea split_arena;     // Arena for Split local resources
 362   ResourceArea live_arena;      // Arena for liveness & IFG info
 363   ResourceMark rm(&live_arena);
 364 
 365   // Need live-ness for the IFG; need the IFG for coalescing.  If the
 366   // liveness is JUST for coalescing, then I can get some mileage by renaming
 367   // all copy-related live ranges low and then using the max copy-related
 368   // live range as a cut-off for LIVE and the IFG.  In other words, I can
 369   // build a subset of LIVE and IFG just for copies.
 370   PhaseLive live(_cfg, _lrg_map.names(), &live_arena);
 371 
 372   // Need IFG for coalescing and coloring
 373   PhaseIFG ifg(&live_arena);
 374   _ifg = &ifg;
 375 
 376   // Come out of SSA world to the Named world.  Assign (virtual) registers to
 377   // Nodes.  Use the same register for all inputs and the output of PhiNodes
 378   // - effectively ending SSA form.  This requires either coalescing live
 379   // ranges or inserting copies.  For the moment, we insert "virtual copies"
 380   // - we pretend there is a copy prior to each Phi in predecessor blocks.
 381   // We will attempt to coalesce such "virtual copies" before we manifest
 382   // them for real.
 383   de_ssa();
 384 
 385 #ifdef ASSERT
 386   // Veify the graph before RA.
 387   verify(&live_arena);
 388 #endif
 389 
 390   {
 391     NOT_PRODUCT( Compile::TracePhase t3("computeLive", &_t_computeLive, TimeCompiler); )
 392     _live = NULL;                 // Mark live as being not available
 393     rm.reset_to_mark();           // Reclaim working storage
 394     IndexSet::reset_memory(C, &live_arena);
 395     ifg.init(_lrg_map.max_lrg_id()); // Empty IFG
 396     gather_lrg_masks( false );    // Collect LRG masks
 397     live.compute(_lrg_map.max_lrg_id()); // Compute liveness
 398     _live = &live;                // Mark LIVE as being available
 399   }
 400 
 401   // Base pointers are currently "used" by instructions which define new
 402   // derived pointers.  This makes base pointers live up to the where the
 403   // derived pointer is made, but not beyond.  Really, they need to be live
 404   // across any GC point where the derived value is live.  So this code looks
 405   // at all the GC points, and "stretches" the live range of any base pointer
 406   // to the GC point.
 407   if (stretch_base_pointer_live_ranges(&live_arena)) {
 408     NOT_PRODUCT(Compile::TracePhase t3("computeLive (sbplr)", &_t_computeLive, TimeCompiler);)
 409     // Since some live range stretched, I need to recompute live
 410     _live = NULL;
 411     rm.reset_to_mark();         // Reclaim working storage
 412     IndexSet::reset_memory(C, &live_arena);
 413     ifg.init(_lrg_map.max_lrg_id());
 414     gather_lrg_masks(false);
 415     live.compute(_lrg_map.max_lrg_id());
 416     _live = &live;
 417   }
 418   // Create the interference graph using virtual copies
 419   build_ifg_virtual();  // Include stack slots this time
 420 
 421   // Aggressive (but pessimistic) copy coalescing.
 422   // This pass works on virtual copies.  Any virtual copies which are not
 423   // coalesced get manifested as actual copies
 424   {
 425     // The IFG is/was triangular.  I am 'squaring it up' so Union can run
 426     // faster.  Union requires a 'for all' operation which is slow on the
 427     // triangular adjacency matrix (quick reminder: the IFG is 'sparse' -
 428     // meaning I can visit all the Nodes neighbors less than a Node in time
 429     // O(# of neighbors), but I have to visit all the Nodes greater than a
 430     // given Node and search them for an instance, i.e., time O(#MaxLRG)).
 431     _ifg->SquareUp();
 432 
 433     PhaseAggressiveCoalesce coalesce(*this);
 434     coalesce.coalesce_driver();
 435     // Insert un-coalesced copies.  Visit all Phis.  Where inputs to a Phi do
 436     // not match the Phi itself, insert a copy.
 437     coalesce.insert_copies(_matcher);
 438     if (C->failing()) {
 439       return;
 440     }
 441   }
 442 
 443   // After aggressive coalesce, attempt a first cut at coloring.
 444   // To color, we need the IFG and for that we need LIVE.
 445   {
 446     NOT_PRODUCT( Compile::TracePhase t3("computeLive", &_t_computeLive, TimeCompiler); )
 447     _live = NULL;
 448     rm.reset_to_mark();           // Reclaim working storage
 449     IndexSet::reset_memory(C, &live_arena);
 450     ifg.init(_lrg_map.max_lrg_id());
 451     gather_lrg_masks( true );
 452     live.compute(_lrg_map.max_lrg_id());
 453     _live = &live;
 454   }
 455 
 456   // Build physical interference graph
 457   uint must_spill = 0;
 458   must_spill = build_ifg_physical(&live_arena);
 459   // If we have a guaranteed spill, might as well spill now
 460   if (must_spill) {
 461     if(!_lrg_map.max_lrg_id()) {
 462       return;
 463     }
 464     // Bail out if unique gets too large (ie - unique > MaxNodeLimit)
 465     C->check_node_count(10*must_spill, "out of nodes before split");
 466     if (C->failing()) {
 467       return;
 468     }
 469 
 470     uint new_max_lrg_id = Split(_lrg_map.max_lrg_id(), &split_arena);  // Split spilling LRG everywhere
 471     _lrg_map.set_max_lrg_id(new_max_lrg_id);
 472     // Bail out if unique gets too large (ie - unique > MaxNodeLimit - 2*NodeLimitFudgeFactor)
 473     // or we failed to split
 474     C->check_node_count(2*NodeLimitFudgeFactor, "out of nodes after physical split");
 475     if (C->failing()) {
 476       return;
 477     }
 478 
 479     NOT_PRODUCT(C->verify_graph_edges();)
 480 
 481     compact();                  // Compact LRGs; return new lower max lrg
 482 
 483     {
 484       NOT_PRODUCT( Compile::TracePhase t3("computeLive", &_t_computeLive, TimeCompiler); )
 485       _live = NULL;
 486       rm.reset_to_mark();         // Reclaim working storage
 487       IndexSet::reset_memory(C, &live_arena);
 488       ifg.init(_lrg_map.max_lrg_id()); // Build a new interference graph
 489       gather_lrg_masks( true );   // Collect intersect mask
 490       live.compute(_lrg_map.max_lrg_id()); // Compute LIVE
 491       _live = &live;
 492     }
 493     build_ifg_physical(&live_arena);
 494     _ifg->SquareUp();
 495     _ifg->Compute_Effective_Degree();
 496     // Only do conservative coalescing if requested
 497     if (OptoCoalesce) {
 498       // Conservative (and pessimistic) copy coalescing of those spills
 499       PhaseConservativeCoalesce coalesce(*this);
 500       // If max live ranges greater than cutoff, don't color the stack.
 501       // This cutoff can be larger than below since it is only done once.
 502       coalesce.coalesce_driver();
 503     }
 504     _lrg_map.compress_uf_map_for_nodes();
 505 
 506 #ifdef ASSERT
 507     verify(&live_arena, true);
 508 #endif
 509   } else {
 510     ifg.SquareUp();
 511     ifg.Compute_Effective_Degree();
 512 #ifdef ASSERT
 513     set_was_low();
 514 #endif
 515   }
 516 
 517   // Prepare for Simplify & Select
 518   cache_lrg_info();           // Count degree of LRGs
 519 
 520   // Simplify the InterFerence Graph by removing LRGs of low degree.
 521   // LRGs of low degree are trivially colorable.
 522   Simplify();
 523 
 524   // Select colors by re-inserting LRGs back into the IFG in reverse order.
 525   // Return whether or not something spills.
 526   uint spills = Select( );
 527 
 528   // If we spill, split and recycle the entire thing
 529   while( spills ) {
 530     if( _trip_cnt++ > 24 ) {
 531       DEBUG_ONLY( dump_for_spill_split_recycle(); )
 532       if( _trip_cnt > 27 ) {
 533         C->record_method_not_compilable("failed spill-split-recycle sanity check");
 534         return;
 535       }
 536     }
 537 
 538     if (!_lrg_map.max_lrg_id()) {
 539       return;
 540     }
 541     uint new_max_lrg_id = Split(_lrg_map.max_lrg_id(), &split_arena);  // Split spilling LRG everywhere
 542     _lrg_map.set_max_lrg_id(new_max_lrg_id);
 543     // Bail out if unique gets too large (ie - unique > MaxNodeLimit - 2*NodeLimitFudgeFactor)
 544     C->check_node_count(2 * NodeLimitFudgeFactor, "out of nodes after split");
 545     if (C->failing()) {
 546       return;
 547     }
 548 
 549     compact(); // Compact LRGs; return new lower max lrg
 550 
 551     // Nuke the live-ness and interference graph and LiveRanGe info
 552     {
 553       NOT_PRODUCT( Compile::TracePhase t3("computeLive", &_t_computeLive, TimeCompiler); )
 554       _live = NULL;
 555       rm.reset_to_mark();         // Reclaim working storage
 556       IndexSet::reset_memory(C, &live_arena);
 557       ifg.init(_lrg_map.max_lrg_id());
 558 
 559       // Create LiveRanGe array.
 560       // Intersect register masks for all USEs and DEFs
 561       gather_lrg_masks(true);
 562       live.compute(_lrg_map.max_lrg_id());
 563       _live = &live;
 564     }
 565     must_spill = build_ifg_physical(&live_arena);
 566     _ifg->SquareUp();
 567     _ifg->Compute_Effective_Degree();
 568 
 569     // Only do conservative coalescing if requested
 570     if (OptoCoalesce) {
 571       // Conservative (and pessimistic) copy coalescing
 572       PhaseConservativeCoalesce coalesce(*this);
 573       // Check for few live ranges determines how aggressive coalesce is.
 574       coalesce.coalesce_driver();
 575     }
 576     _lrg_map.compress_uf_map_for_nodes();
 577 #ifdef ASSERT
 578     verify(&live_arena, true);
 579 #endif
 580     cache_lrg_info();           // Count degree of LRGs
 581 
 582     // Simplify the InterFerence Graph by removing LRGs of low degree.
 583     // LRGs of low degree are trivially colorable.
 584     Simplify();
 585 
 586     // Select colors by re-inserting LRGs back into the IFG in reverse order.
 587     // Return whether or not something spills.
 588     spills = Select();
 589   }
 590 
 591   // Count number of Simplify-Select trips per coloring success.
 592   _allocator_attempts += _trip_cnt + 1;
 593   _allocator_successes += 1;
 594 
 595   // Peephole remove copies
 596   post_allocate_copy_removal();
 597 
 598 #ifdef ASSERT
 599   // Veify the graph after RA.
 600   verify(&live_arena);
 601 #endif
 602 
 603   // max_reg is past the largest *register* used.
 604   // Convert that to a frame_slot number.
 605   if (_max_reg <= _matcher._new_SP) {
 606     _framesize = C->out_preserve_stack_slots();
 607   }
 608   else {
 609     _framesize = _max_reg -_matcher._new_SP;
 610   }
 611   assert((int)(_matcher._new_SP+_framesize) >= (int)_matcher._out_arg_limit, "framesize must be large enough");
 612 
 613   // This frame must preserve the required fp alignment
 614   _framesize = round_to(_framesize, Matcher::stack_alignment_in_slots());
 615   assert( _framesize >= 0 && _framesize <= 1000000, "sanity check" );
 616 #ifndef PRODUCT
 617   _total_framesize += _framesize;
 618   if ((int)_framesize > _max_framesize) {
 619     _max_framesize = _framesize;
 620   }
 621 #endif
 622 
 623   // Convert CISC spills
 624   fixup_spills();
 625 
 626   // Log regalloc results
 627   CompileLog* log = Compile::current()->log();
 628   if (log != NULL) {
 629     log->elem("regalloc attempts='%d' success='%d'", _trip_cnt, !C->failing());
 630   }
 631 
 632   if (C->failing()) {
 633     return;
 634   }
 635 
 636   NOT_PRODUCT(C->verify_graph_edges();)
 637 
 638   // Move important info out of the live_arena to longer lasting storage.
 639   alloc_node_regs(_lrg_map.size());
 640   for (uint i=0; i < _lrg_map.size(); i++) {
 641     if (_lrg_map.live_range_id(i)) { // Live range associated with Node?
 642       LRG &lrg = lrgs(_lrg_map.live_range_id(i));
 643       if (!lrg.alive()) {
 644         set_bad(i);
 645       } else if (lrg.num_regs() == 1) {
 646         set1(i, lrg.reg());
 647       } else {                  // Must be a register-set
 648         if (!lrg._fat_proj) {   // Must be aligned adjacent register set
 649           // Live ranges record the highest register in their mask.
 650           // We want the low register for the AD file writer's convenience.
 651           OptoReg::Name hi = lrg.reg(); // Get hi register
 652           OptoReg::Name lo = OptoReg::add(hi, (1-lrg.num_regs())); // Find lo
 653           // We have to use pair [lo,lo+1] even for wide vectors because
 654           // the rest of code generation works only with pairs. It is safe
 655           // since for registers encoding only 'lo' is used.
 656           // Second reg from pair is used in ScheduleAndBundle on SPARC where
 657           // vector max size is 8 which corresponds to registers pair.
 658           // It is also used in BuildOopMaps but oop operations are not
 659           // vectorized.
 660           set2(i, lo);
 661         } else {                // Misaligned; extract 2 bits
 662           OptoReg::Name hi = lrg.reg(); // Get hi register
 663           lrg.Remove(hi);       // Yank from mask
 664           int lo = lrg.mask().find_first_elem(); // Find lo
 665           set_pair(i, hi, lo);
 666         }
 667       }
 668       if( lrg._is_oop ) _node_oops.set(i);
 669     } else {
 670       set_bad(i);
 671     }
 672   }
 673 
 674   // Done!
 675   _live = NULL;
 676   _ifg = NULL;
 677   C->set_indexSet_arena(NULL);  // ResourceArea is at end of scope
 678 }
 679 
 680 //------------------------------de_ssa-----------------------------------------
 681 void PhaseChaitin::de_ssa() {
 682   // Set initial Names for all Nodes.  Most Nodes get the virtual register
 683   // number.  A few get the ZERO live range number.  These do not
 684   // get allocated, but instead rely on correct scheduling to ensure that
 685   // only one instance is simultaneously live at a time.
 686   uint lr_counter = 1;
 687   for( uint i = 0; i < _cfg._num_blocks; i++ ) {
 688     Block *b = _cfg._blocks[i];
 689     uint cnt = b->_nodes.size();
 690 
 691     // Handle all the normal Nodes in the block
 692     for( uint j = 0; j < cnt; j++ ) {
 693       Node *n = b->_nodes[j];
 694       // Pre-color to the zero live range, or pick virtual register
 695       const RegMask &rm = n->out_RegMask();
 696       _lrg_map.map(n->_idx, rm.is_NotEmpty() ? lr_counter++ : 0);
 697     }
 698   }
 699   // Reset the Union-Find mapping to be identity
 700   _lrg_map.reset_uf_map(lr_counter);
 701 }
 702 
 703 
 704 //------------------------------gather_lrg_masks-------------------------------
 705 // Gather LiveRanGe information, including register masks.  Modification of
 706 // cisc spillable in_RegMasks should not be done before AggressiveCoalesce.
 707 void PhaseChaitin::gather_lrg_masks( bool after_aggressive ) {
 708 
 709   // Nail down the frame pointer live range
 710   uint fp_lrg = _lrg_map.live_range_id(_cfg._root->in(1)->in(TypeFunc::FramePtr));
 711   lrgs(fp_lrg)._cost += 1e12;   // Cost is infinite
 712 
 713   // For all blocks
 714   for( uint i = 0; i < _cfg._num_blocks; i++ ) {
 715     Block *b = _cfg._blocks[i];
 716 
 717     // For all instructions
 718     for( uint j = 1; j < b->_nodes.size(); j++ ) {
 719       Node *n = b->_nodes[j];
 720       uint input_edge_start =1; // Skip control most nodes
 721       if( n->is_Mach() ) input_edge_start = n->as_Mach()->oper_input_base();
 722       uint idx = n->is_Copy();
 723 
 724       // Get virtual register number, same as LiveRanGe index
 725       uint vreg = _lrg_map.live_range_id(n);
 726       LRG &lrg = lrgs(vreg);
 727       if( vreg ) {              // No vreg means un-allocable (e.g. memory)
 728 
 729         // Collect has-copy bit
 730         if( idx ) {
 731           lrg._has_copy = 1;
 732           uint clidx = _lrg_map.live_range_id(n->in(idx));
 733           LRG &copy_src = lrgs(clidx);
 734           copy_src._has_copy = 1;
 735         }
 736 
 737         // Check for float-vs-int live range (used in register-pressure
 738         // calculations)
 739         const Type *n_type = n->bottom_type();
 740         if (n_type->is_floatingpoint())
 741           lrg._is_float = 1;
 742 
 743         // Check for twice prior spilling.  Once prior spilling might have
 744         // spilled 'soft', 2nd prior spill should have spilled 'hard' and
 745         // further spilling is unlikely to make progress.
 746         if( _spilled_once.test(n->_idx) ) {
 747           lrg._was_spilled1 = 1;
 748           if( _spilled_twice.test(n->_idx) )
 749             lrg._was_spilled2 = 1;
 750         }
 751 
 752 #ifndef PRODUCT
 753         if (trace_spilling() && lrg._def != NULL) {
 754           // collect defs for MultiDef printing
 755           if (lrg._defs == NULL) {
 756             lrg._defs = new (_ifg->_arena) GrowableArray<Node*>(_ifg->_arena, 2, 0, NULL);
 757             lrg._defs->append(lrg._def);
 758           }
 759           lrg._defs->append(n);
 760         }
 761 #endif
 762 
 763         // Check for a single def LRG; these can spill nicely
 764         // via rematerialization.  Flag as NULL for no def found
 765         // yet, or 'n' for single def or -1 for many defs.
 766         lrg._def = lrg._def ? NodeSentinel : n;
 767 
 768         // Limit result register mask to acceptable registers
 769         const RegMask &rm = n->out_RegMask();
 770         lrg.AND( rm );
 771 
 772         int ireg = n->ideal_reg();
 773         assert( !n->bottom_type()->isa_oop_ptr() || ireg == Op_RegP,
 774                 "oops must be in Op_RegP's" );
 775 
 776         // Check for vector live range (only if vector register is used).
 777         // On SPARC vector uses RegD which could be misaligned so it is not
 778         // processes as vector in RA.
 779         if (RegMask::is_vector(ireg))
 780           lrg._is_vector = 1;
 781         assert(n_type->isa_vect() == NULL || lrg._is_vector || ireg == Op_RegD,
 782                "vector must be in vector registers");
 783 
 784         // Check for bound register masks
 785         const RegMask &lrgmask = lrg.mask();
 786         if (lrgmask.is_bound(ireg))
 787           lrg._is_bound = 1;
 788 
 789         // Check for maximum frequency value
 790         if (lrg._maxfreq < b->_freq)
 791           lrg._maxfreq = b->_freq;
 792 
 793         // Check for oop-iness, or long/double
 794         // Check for multi-kill projection
 795         switch( ireg ) {
 796         case MachProjNode::fat_proj:
 797           // Fat projections have size equal to number of registers killed
 798           lrg.set_num_regs(rm.Size());
 799           lrg.set_reg_pressure(lrg.num_regs());
 800           lrg._fat_proj = 1;
 801           lrg._is_bound = 1;
 802           break;
 803         case Op_RegP:
 804 #ifdef _LP64
 805           lrg.set_num_regs(2);  // Size is 2 stack words
 806 #else
 807           lrg.set_num_regs(1);  // Size is 1 stack word
 808 #endif
 809           // Register pressure is tracked relative to the maximum values
 810           // suggested for that platform, INTPRESSURE and FLOATPRESSURE,
 811           // and relative to other types which compete for the same regs.
 812           //
 813           // The following table contains suggested values based on the
 814           // architectures as defined in each .ad file.
 815           // INTPRESSURE and FLOATPRESSURE may be tuned differently for
 816           // compile-speed or performance.
 817           // Note1:
 818           // SPARC and SPARCV9 reg_pressures are at 2 instead of 1
 819           // since .ad registers are defined as high and low halves.
 820           // These reg_pressure values remain compatible with the code
 821           // in is_high_pressure() which relates get_invalid_mask_size(),
 822           // Block::_reg_pressure and INTPRESSURE, FLOATPRESSURE.
 823           // Note2:
 824           // SPARC -d32 has 24 registers available for integral values,
 825           // but only 10 of these are safe for 64-bit longs.
 826           // Using set_reg_pressure(2) for both int and long means
 827           // the allocator will believe it can fit 26 longs into
 828           // registers.  Using 2 for longs and 1 for ints means the
 829           // allocator will attempt to put 52 integers into registers.
 830           // The settings below limit this problem to methods with
 831           // many long values which are being run on 32-bit SPARC.
 832           //
 833           // ------------------- reg_pressure --------------------
 834           // Each entry is reg_pressure_per_value,number_of_regs
 835           //         RegL  RegI  RegFlags   RegF RegD    INTPRESSURE  FLOATPRESSURE
 836           // IA32     2     1     1          1    1          6           6
 837           // IA64     1     1     1          1    1         50          41
 838           // SPARC    2     2     2          2    2         48 (24)     52 (26)
 839           // SPARCV9  2     2     2          2    2         48 (24)     52 (26)
 840           // AMD64    1     1     1          1    1         14          15
 841           // -----------------------------------------------------
 842 #if defined(SPARC)
 843           lrg.set_reg_pressure(2);  // use for v9 as well
 844 #else
 845           lrg.set_reg_pressure(1);  // normally one value per register
 846 #endif
 847           if( n_type->isa_oop_ptr() ) {
 848             lrg._is_oop = 1;
 849           }
 850           break;
 851         case Op_RegL:           // Check for long or double
 852         case Op_RegD:
 853           lrg.set_num_regs(2);
 854           // Define platform specific register pressure
 855 #if defined(SPARC) || defined(ARM)
 856           lrg.set_reg_pressure(2);
 857 #elif defined(IA32)
 858           if( ireg == Op_RegL ) {
 859             lrg.set_reg_pressure(2);
 860           } else {
 861             lrg.set_reg_pressure(1);
 862           }
 863 #else
 864           lrg.set_reg_pressure(1);  // normally one value per register
 865 #endif
 866           // If this def of a double forces a mis-aligned double,
 867           // flag as '_fat_proj' - really flag as allowing misalignment
 868           // AND changes how we count interferences.  A mis-aligned
 869           // double can interfere with TWO aligned pairs, or effectively
 870           // FOUR registers!
 871           if (rm.is_misaligned_pair()) {
 872             lrg._fat_proj = 1;
 873             lrg._is_bound = 1;
 874           }
 875           break;
 876         case Op_RegF:
 877         case Op_RegI:
 878         case Op_RegN:
 879         case Op_RegFlags:
 880         case 0:                 // not an ideal register
 881           lrg.set_num_regs(1);
 882 #ifdef SPARC
 883           lrg.set_reg_pressure(2);
 884 #else
 885           lrg.set_reg_pressure(1);
 886 #endif
 887           break;
 888         case Op_VecS:
 889           assert(Matcher::vector_size_supported(T_BYTE,4), "sanity");
 890           assert(RegMask::num_registers(Op_VecS) == RegMask::SlotsPerVecS, "sanity");
 891           lrg.set_num_regs(RegMask::SlotsPerVecS);
 892           lrg.set_reg_pressure(1);
 893           break;
 894         case Op_VecD:
 895           assert(Matcher::vector_size_supported(T_FLOAT,RegMask::SlotsPerVecD), "sanity");
 896           assert(RegMask::num_registers(Op_VecD) == RegMask::SlotsPerVecD, "sanity");
 897           assert(lrgmask.is_aligned_sets(RegMask::SlotsPerVecD), "vector should be aligned");
 898           lrg.set_num_regs(RegMask::SlotsPerVecD);
 899           lrg.set_reg_pressure(1);
 900           break;
 901         case Op_VecX:
 902           assert(Matcher::vector_size_supported(T_FLOAT,RegMask::SlotsPerVecX), "sanity");
 903           assert(RegMask::num_registers(Op_VecX) == RegMask::SlotsPerVecX, "sanity");
 904           assert(lrgmask.is_aligned_sets(RegMask::SlotsPerVecX), "vector should be aligned");
 905           lrg.set_num_regs(RegMask::SlotsPerVecX);
 906           lrg.set_reg_pressure(1);
 907           break;
 908         case Op_VecY:
 909           assert(Matcher::vector_size_supported(T_FLOAT,RegMask::SlotsPerVecY), "sanity");
 910           assert(RegMask::num_registers(Op_VecY) == RegMask::SlotsPerVecY, "sanity");
 911           assert(lrgmask.is_aligned_sets(RegMask::SlotsPerVecY), "vector should be aligned");
 912           lrg.set_num_regs(RegMask::SlotsPerVecY);
 913           lrg.set_reg_pressure(1);
 914           break;
 915         default:
 916           ShouldNotReachHere();
 917         }
 918       }
 919 
 920       // Now do the same for inputs
 921       uint cnt = n->req();
 922       // Setup for CISC SPILLING
 923       uint inp = (uint)AdlcVMDeps::Not_cisc_spillable;
 924       if( UseCISCSpill && after_aggressive ) {
 925         inp = n->cisc_operand();
 926         if( inp != (uint)AdlcVMDeps::Not_cisc_spillable )
 927           // Convert operand number to edge index number
 928           inp = n->as_Mach()->operand_index(inp);
 929       }
 930       // Prepare register mask for each input
 931       for( uint k = input_edge_start; k < cnt; k++ ) {
 932         uint vreg = _lrg_map.live_range_id(n->in(k));
 933         if (!vreg) {
 934           continue;
 935         }
 936 
 937         // If this instruction is CISC Spillable, add the flags
 938         // bit to its appropriate input
 939         if( UseCISCSpill && after_aggressive && inp == k ) {
 940 #ifndef PRODUCT
 941           if( TraceCISCSpill ) {
 942             tty->print("  use_cisc_RegMask: ");
 943             n->dump();
 944           }
 945 #endif
 946           n->as_Mach()->use_cisc_RegMask();
 947         }
 948 
 949         LRG &lrg = lrgs(vreg);
 950         // // Testing for floating point code shape
 951         // Node *test = n->in(k);
 952         // if( test->is_Mach() ) {
 953         //   MachNode *m = test->as_Mach();
 954         //   int  op = m->ideal_Opcode();
 955         //   if (n->is_Call() && (op == Op_AddF || op == Op_MulF) ) {
 956         //     int zzz = 1;
 957         //   }
 958         // }
 959 
 960         // Limit result register mask to acceptable registers.
 961         // Do not limit registers from uncommon uses before
 962         // AggressiveCoalesce.  This effectively pre-virtual-splits
 963         // around uncommon uses of common defs.
 964         const RegMask &rm = n->in_RegMask(k);
 965         if (!after_aggressive && _cfg.get_block_for_node(n->in(k))->_freq > 1000 * b->_freq) {
 966           // Since we are BEFORE aggressive coalesce, leave the register
 967           // mask untrimmed by the call.  This encourages more coalescing.
 968           // Later, AFTER aggressive, this live range will have to spill
 969           // but the spiller handles slow-path calls very nicely.
 970         } else {
 971           lrg.AND( rm );
 972         }
 973 
 974         // Check for bound register masks
 975         const RegMask &lrgmask = lrg.mask();
 976         int kreg = n->in(k)->ideal_reg();
 977         bool is_vect = RegMask::is_vector(kreg);
 978         assert(n->in(k)->bottom_type()->isa_vect() == NULL ||
 979                is_vect || kreg == Op_RegD,
 980                "vector must be in vector registers");
 981         if (lrgmask.is_bound(kreg))
 982           lrg._is_bound = 1;
 983 
 984         // If this use of a double forces a mis-aligned double,
 985         // flag as '_fat_proj' - really flag as allowing misalignment
 986         // AND changes how we count interferences.  A mis-aligned
 987         // double can interfere with TWO aligned pairs, or effectively
 988         // FOUR registers!
 989 #ifdef ASSERT
 990         if (is_vect) {
 991           assert(lrgmask.is_aligned_sets(lrg.num_regs()), "vector should be aligned");
 992           assert(!lrg._fat_proj, "sanity");
 993           assert(RegMask::num_registers(kreg) == lrg.num_regs(), "sanity");
 994         }
 995 #endif
 996         if (!is_vect && lrg.num_regs() == 2 && !lrg._fat_proj && rm.is_misaligned_pair()) {
 997           lrg._fat_proj = 1;
 998           lrg._is_bound = 1;
 999         }
1000         // if the LRG is an unaligned pair, we will have to spill
1001         // so clear the LRG's register mask if it is not already spilled
1002         if (!is_vect && !n->is_SpillCopy() &&
1003             (lrg._def == NULL || lrg.is_multidef() || !lrg._def->is_SpillCopy()) &&
1004             lrgmask.is_misaligned_pair()) {
1005           lrg.Clear();
1006         }
1007 
1008         // Check for maximum frequency value
1009         if( lrg._maxfreq < b->_freq )
1010           lrg._maxfreq = b->_freq;
1011 
1012       } // End for all allocated inputs
1013     } // end for all instructions
1014   } // end for all blocks
1015 
1016   // Final per-liverange setup
1017   for (uint i2 = 0; i2 < _lrg_map.max_lrg_id(); i2++) {
1018     LRG &lrg = lrgs(i2);
1019     assert(!lrg._is_vector || !lrg._fat_proj, "sanity");
1020     if (lrg.num_regs() > 1 && !lrg._fat_proj) {
1021       lrg.clear_to_sets();
1022     }
1023     lrg.compute_set_mask_size();
1024     if (lrg.not_free()) {      // Handle case where we lose from the start
1025       lrg.set_reg(OptoReg::Name(LRG::SPILL_REG));
1026       lrg._direct_conflict = 1;
1027     }
1028     lrg.set_degree(0);          // no neighbors in IFG yet
1029   }
1030 }
1031 
1032 //------------------------------set_was_low------------------------------------
1033 // Set the was-lo-degree bit.  Conservative coalescing should not change the
1034 // colorability of the graph.  If any live range was of low-degree before
1035 // coalescing, it should Simplify.  This call sets the was-lo-degree bit.
1036 // The bit is checked in Simplify.
1037 void PhaseChaitin::set_was_low() {
1038 #ifdef ASSERT
1039   for (uint i = 1; i < _lrg_map.max_lrg_id(); i++) {
1040     int size = lrgs(i).num_regs();
1041     uint old_was_lo = lrgs(i)._was_lo;
1042     lrgs(i)._was_lo = 0;
1043     if( lrgs(i).lo_degree() ) {
1044       lrgs(i)._was_lo = 1;      // Trivially of low degree
1045     } else {                    // Else check the Brigg's assertion
1046       // Brigg's observation is that the lo-degree neighbors of a
1047       // hi-degree live range will not interfere with the color choices
1048       // of said hi-degree live range.  The Simplify reverse-stack-coloring
1049       // order takes care of the details.  Hence you do not have to count
1050       // low-degree neighbors when determining if this guy colors.
1051       int briggs_degree = 0;
1052       IndexSet *s = _ifg->neighbors(i);
1053       IndexSetIterator elements(s);
1054       uint lidx;
1055       while((lidx = elements.next()) != 0) {
1056         if( !lrgs(lidx).lo_degree() )
1057           briggs_degree += MAX2(size,lrgs(lidx).num_regs());
1058       }
1059       if( briggs_degree < lrgs(i).degrees_of_freedom() )
1060         lrgs(i)._was_lo = 1;    // Low degree via the briggs assertion
1061     }
1062     assert(old_was_lo <= lrgs(i)._was_lo, "_was_lo may not decrease");
1063   }
1064 #endif
1065 }
1066 
1067 #define REGISTER_CONSTRAINED 16
1068 
1069 //------------------------------cache_lrg_info---------------------------------
1070 // Compute cost/area ratio, in case we spill.  Build the lo-degree list.
1071 void PhaseChaitin::cache_lrg_info( ) {
1072 
1073   for (uint i = 1; i < _lrg_map.max_lrg_id(); i++) {
1074     LRG &lrg = lrgs(i);
1075 
1076     // Check for being of low degree: means we can be trivially colored.
1077     // Low degree, dead or must-spill guys just get to simplify right away
1078     if( lrg.lo_degree() ||
1079        !lrg.alive() ||
1080         lrg._must_spill ) {
1081       // Split low degree list into those guys that must get a
1082       // register and those that can go to register or stack.
1083       // The idea is LRGs that can go register or stack color first when
1084       // they have a good chance of getting a register.  The register-only
1085       // lo-degree live ranges always get a register.
1086       OptoReg::Name hi_reg = lrg.mask().find_last_elem();
1087       if( OptoReg::is_stack(hi_reg)) { // Can go to stack?
1088         lrg._next = _lo_stk_degree;
1089         _lo_stk_degree = i;
1090       } else {
1091         lrg._next = _lo_degree;
1092         _lo_degree = i;
1093       }
1094     } else {                    // Else high degree
1095       lrgs(_hi_degree)._prev = i;
1096       lrg._next = _hi_degree;
1097       lrg._prev = 0;
1098       _hi_degree = i;
1099     }
1100   }
1101 }
1102 
1103 //------------------------------Pre-Simplify-----------------------------------
1104 // Simplify the IFG by removing LRGs of low degree that have NO copies
1105 void PhaseChaitin::Pre_Simplify( ) {
1106 
1107   // Warm up the lo-degree no-copy list
1108   int lo_no_copy = 0;
1109   for (uint i = 1; i < _lrg_map.max_lrg_id(); i++) {
1110     if ((lrgs(i).lo_degree() && !lrgs(i)._has_copy) ||
1111         !lrgs(i).alive() ||
1112         lrgs(i)._must_spill) {
1113       lrgs(i)._next = lo_no_copy;
1114       lo_no_copy = i;
1115     }
1116   }
1117 
1118   while( lo_no_copy ) {
1119     uint lo = lo_no_copy;
1120     lo_no_copy = lrgs(lo)._next;
1121     int size = lrgs(lo).num_regs();
1122 
1123     // Put the simplified guy on the simplified list.
1124     lrgs(lo)._next = _simplified;
1125     _simplified = lo;
1126 
1127     // Yank this guy from the IFG.
1128     IndexSet *adj = _ifg->remove_node( lo );
1129 
1130     // If any neighbors' degrees fall below their number of
1131     // allowed registers, then put that neighbor on the low degree
1132     // list.  Note that 'degree' can only fall and 'numregs' is
1133     // unchanged by this action.  Thus the two are equal at most once,
1134     // so LRGs hit the lo-degree worklists at most once.
1135     IndexSetIterator elements(adj);
1136     uint neighbor;
1137     while ((neighbor = elements.next()) != 0) {
1138       LRG *n = &lrgs(neighbor);
1139       assert( _ifg->effective_degree(neighbor) == n->degree(), "" );
1140 
1141       // Check for just becoming of-low-degree
1142       if( n->just_lo_degree() && !n->_has_copy ) {
1143         assert(!(*_ifg->_yanked)[neighbor],"Cannot move to lo degree twice");
1144         // Put on lo-degree list
1145         n->_next = lo_no_copy;
1146         lo_no_copy = neighbor;
1147       }
1148     }
1149   } // End of while lo-degree no_copy worklist not empty
1150 
1151   // No more lo-degree no-copy live ranges to simplify
1152 }
1153 
1154 //------------------------------Simplify---------------------------------------
1155 // Simplify the IFG by removing LRGs of low degree.
1156 void PhaseChaitin::Simplify( ) {
1157 
1158   while( 1 ) {                  // Repeat till simplified it all
1159     // May want to explore simplifying lo_degree before _lo_stk_degree.
1160     // This might result in more spills coloring into registers during
1161     // Select().
1162     while( _lo_degree || _lo_stk_degree ) {
1163       // If possible, pull from lo_stk first
1164       uint lo;
1165       if( _lo_degree ) {
1166         lo = _lo_degree;
1167         _lo_degree = lrgs(lo)._next;
1168       } else {
1169         lo = _lo_stk_degree;
1170         _lo_stk_degree = lrgs(lo)._next;
1171       }
1172 
1173       // Put the simplified guy on the simplified list.
1174       lrgs(lo)._next = _simplified;
1175       _simplified = lo;
1176       // If this guy is "at risk" then mark his current neighbors
1177       if( lrgs(lo)._at_risk ) {
1178         IndexSetIterator elements(_ifg->neighbors(lo));
1179         uint datum;
1180         while ((datum = elements.next()) != 0) {
1181           lrgs(datum)._risk_bias = lo;
1182         }
1183       }
1184 
1185       // Yank this guy from the IFG.
1186       IndexSet *adj = _ifg->remove_node( lo );
1187 
1188       // If any neighbors' degrees fall below their number of
1189       // allowed registers, then put that neighbor on the low degree
1190       // list.  Note that 'degree' can only fall and 'numregs' is
1191       // unchanged by this action.  Thus the two are equal at most once,
1192       // so LRGs hit the lo-degree worklist at most once.
1193       IndexSetIterator elements(adj);
1194       uint neighbor;
1195       while ((neighbor = elements.next()) != 0) {
1196         LRG *n = &lrgs(neighbor);
1197 #ifdef ASSERT
1198         if( VerifyOpto || VerifyRegisterAllocator ) {
1199           assert( _ifg->effective_degree(neighbor) == n->degree(), "" );
1200         }
1201 #endif
1202 
1203         // Check for just becoming of-low-degree just counting registers.
1204         // _must_spill live ranges are already on the low degree list.
1205         if( n->just_lo_degree() && !n->_must_spill ) {
1206           assert(!(*_ifg->_yanked)[neighbor],"Cannot move to lo degree twice");
1207           // Pull from hi-degree list
1208           uint prev = n->_prev;
1209           uint next = n->_next;
1210           if( prev ) lrgs(prev)._next = next;
1211           else _hi_degree = next;
1212           lrgs(next)._prev = prev;
1213           n->_next = _lo_degree;
1214           _lo_degree = neighbor;
1215         }
1216       }
1217     } // End of while lo-degree/lo_stk_degree worklist not empty
1218 
1219     // Check for got everything: is hi-degree list empty?
1220     if( !_hi_degree ) break;
1221 
1222     // Time to pick a potential spill guy
1223     uint lo_score = _hi_degree;
1224     double score = lrgs(lo_score).score();
1225     double area = lrgs(lo_score)._area;
1226     double cost = lrgs(lo_score)._cost;
1227     bool bound = lrgs(lo_score)._is_bound;
1228 
1229     // Find cheapest guy
1230     debug_only( int lo_no_simplify=0; );
1231     for( uint i = _hi_degree; i; i = lrgs(i)._next ) {
1232       assert( !(*_ifg->_yanked)[i], "" );
1233       // It's just vaguely possible to move hi-degree to lo-degree without
1234       // going through a just-lo-degree stage: If you remove a double from
1235       // a float live range it's degree will drop by 2 and you can skip the
1236       // just-lo-degree stage.  It's very rare (shows up after 5000+ methods
1237       // in -Xcomp of Java2Demo).  So just choose this guy to simplify next.
1238       if( lrgs(i).lo_degree() ) {
1239         lo_score = i;
1240         break;
1241       }
1242       debug_only( if( lrgs(i)._was_lo ) lo_no_simplify=i; );
1243       double iscore = lrgs(i).score();
1244       double iarea = lrgs(i)._area;
1245       double icost = lrgs(i)._cost;
1246       bool ibound = lrgs(i)._is_bound;
1247 
1248       // Compare cost/area of i vs cost/area of lo_score.  Smaller cost/area
1249       // wins.  Ties happen because all live ranges in question have spilled
1250       // a few times before and the spill-score adds a huge number which
1251       // washes out the low order bits.  We are choosing the lesser of 2
1252       // evils; in this case pick largest area to spill.
1253       // Ties also happen when live ranges are defined and used only inside
1254       // one block. In which case their area is 0 and score set to max.
1255       // In such case choose bound live range over unbound to free registers
1256       // or with smaller cost to spill.
1257       if( iscore < score ||
1258           (iscore == score && iarea > area && lrgs(lo_score)._was_spilled2) ||
1259           (iscore == score && iarea == area &&
1260            ( (ibound && !bound) || ibound == bound && (icost < cost) )) ) {
1261         lo_score = i;
1262         score = iscore;
1263         area = iarea;
1264         cost = icost;
1265         bound = ibound;
1266       }
1267     }
1268     LRG *lo_lrg = &lrgs(lo_score);
1269     // The live range we choose for spilling is either hi-degree, or very
1270     // rarely it can be low-degree.  If we choose a hi-degree live range
1271     // there better not be any lo-degree choices.
1272     assert( lo_lrg->lo_degree() || !lo_no_simplify, "Live range was lo-degree before coalesce; should simplify" );
1273 
1274     // Pull from hi-degree list
1275     uint prev = lo_lrg->_prev;
1276     uint next = lo_lrg->_next;
1277     if( prev ) lrgs(prev)._next = next;
1278     else _hi_degree = next;
1279     lrgs(next)._prev = prev;
1280     // Jam him on the lo-degree list, despite his high degree.
1281     // Maybe he'll get a color, and maybe he'll spill.
1282     // Only Select() will know.
1283     lrgs(lo_score)._at_risk = true;
1284     _lo_degree = lo_score;
1285     lo_lrg->_next = 0;
1286 
1287   } // End of while not simplified everything
1288 
1289 }
1290 
1291 //------------------------------is_legal_reg-----------------------------------
1292 // Is 'reg' register legal for 'lrg'?
1293 static bool is_legal_reg(LRG &lrg, OptoReg::Name reg, int chunk) {
1294   if (reg >= chunk && reg < (chunk + RegMask::CHUNK_SIZE) &&
1295       lrg.mask().Member(OptoReg::add(reg,-chunk))) {
1296     // RA uses OptoReg which represent the highest element of a registers set.
1297     // For example, vectorX (128bit) on x86 uses [XMM,XMMb,XMMc,XMMd] set
1298     // in which XMMd is used by RA to represent such vectors. A double value
1299     // uses [XMM,XMMb] pairs and XMMb is used by RA for it.
1300     // The register mask uses largest bits set of overlapping register sets.
1301     // On x86 with AVX it uses 8 bits for each XMM registers set.
1302     //
1303     // The 'lrg' already has cleared-to-set register mask (done in Select()
1304     // before calling choose_color()). Passing mask.Member(reg) check above
1305     // indicates that the size (num_regs) of 'reg' set is less or equal to
1306     // 'lrg' set size.
1307     // For set size 1 any register which is member of 'lrg' mask is legal.
1308     if (lrg.num_regs()==1)
1309       return true;
1310     // For larger sets only an aligned register with the same set size is legal.
1311     int mask = lrg.num_regs()-1;
1312     if ((reg&mask) == mask)
1313       return true;
1314   }
1315   return false;
1316 }
1317 
1318 //------------------------------bias_color-------------------------------------
1319 // Choose a color using the biasing heuristic
1320 OptoReg::Name PhaseChaitin::bias_color( LRG &lrg, int chunk ) {
1321 
1322   // Check for "at_risk" LRG's
1323   uint risk_lrg = _lrg_map.find(lrg._risk_bias);
1324   if( risk_lrg != 0 ) {
1325     // Walk the colored neighbors of the "at_risk" candidate
1326     // Choose a color which is both legal and already taken by a neighbor
1327     // of the "at_risk" candidate in order to improve the chances of the
1328     // "at_risk" candidate of coloring
1329     IndexSetIterator elements(_ifg->neighbors(risk_lrg));
1330     uint datum;
1331     while ((datum = elements.next()) != 0) {
1332       OptoReg::Name reg = lrgs(datum).reg();
1333       // If this LRG's register is legal for us, choose it
1334       if (is_legal_reg(lrg, reg, chunk))
1335         return reg;
1336     }
1337   }
1338 
1339   uint copy_lrg = _lrg_map.find(lrg._copy_bias);
1340   if( copy_lrg != 0 ) {
1341     // If he has a color,
1342     if( !(*(_ifg->_yanked))[copy_lrg] ) {
1343       OptoReg::Name reg = lrgs(copy_lrg).reg();
1344       //  And it is legal for you,
1345       if (is_legal_reg(lrg, reg, chunk))
1346         return reg;
1347     } else if( chunk == 0 ) {
1348       // Choose a color which is legal for him
1349       RegMask tempmask = lrg.mask();
1350       tempmask.AND(lrgs(copy_lrg).mask());
1351       tempmask.clear_to_sets(lrg.num_regs());
1352       OptoReg::Name reg = tempmask.find_first_set(lrg.num_regs());
1353       if (OptoReg::is_valid(reg))
1354         return reg;
1355     }
1356   }
1357 
1358   // If no bias info exists, just go with the register selection ordering
1359   if (lrg._is_vector || lrg.num_regs() == 2) {
1360     // Find an aligned set
1361     return OptoReg::add(lrg.mask().find_first_set(lrg.num_regs()),chunk);
1362   }
1363 
1364   // CNC - Fun hack.  Alternate 1st and 2nd selection.  Enables post-allocate
1365   // copy removal to remove many more copies, by preventing a just-assigned
1366   // register from being repeatedly assigned.
1367   OptoReg::Name reg = lrg.mask().find_first_elem();
1368   if( (++_alternate & 1) && OptoReg::is_valid(reg) ) {
1369     // This 'Remove; find; Insert' idiom is an expensive way to find the
1370     // SECOND element in the mask.
1371     lrg.Remove(reg);
1372     OptoReg::Name reg2 = lrg.mask().find_first_elem();
1373     lrg.Insert(reg);
1374     if( OptoReg::is_reg(reg2))
1375       reg = reg2;
1376   }
1377   return OptoReg::add( reg, chunk );
1378 }
1379 
1380 //------------------------------choose_color-----------------------------------
1381 // Choose a color in the current chunk
1382 OptoReg::Name PhaseChaitin::choose_color( LRG &lrg, int chunk ) {
1383   assert( C->in_preserve_stack_slots() == 0 || chunk != 0 || lrg._is_bound || lrg.mask().is_bound1() || !lrg.mask().Member(OptoReg::Name(_matcher._old_SP-1)), "must not allocate stack0 (inside preserve area)");
1384   assert(C->out_preserve_stack_slots() == 0 || chunk != 0 || lrg._is_bound || lrg.mask().is_bound1() || !lrg.mask().Member(OptoReg::Name(_matcher._old_SP+0)), "must not allocate stack0 (inside preserve area)");
1385 
1386   if( lrg.num_regs() == 1 ||    // Common Case
1387       !lrg._fat_proj )          // Aligned+adjacent pairs ok
1388     // Use a heuristic to "bias" the color choice
1389     return bias_color(lrg, chunk);
1390 
1391   assert(!lrg._is_vector, "should be not vector here" );
1392   assert( lrg.num_regs() >= 2, "dead live ranges do not color" );
1393 
1394   // Fat-proj case or misaligned double argument.
1395   assert(lrg.compute_mask_size() == lrg.num_regs() ||
1396          lrg.num_regs() == 2,"fat projs exactly color" );
1397   assert( !chunk, "always color in 1st chunk" );
1398   // Return the highest element in the set.
1399   return lrg.mask().find_last_elem();
1400 }
1401 
1402 //------------------------------Select-----------------------------------------
1403 // Select colors by re-inserting LRGs back into the IFG.  LRGs are re-inserted
1404 // in reverse order of removal.  As long as nothing of hi-degree was yanked,
1405 // everything going back is guaranteed a color.  Select that color.  If some
1406 // hi-degree LRG cannot get a color then we record that we must spill.
1407 uint PhaseChaitin::Select( ) {
1408   uint spill_reg = LRG::SPILL_REG;
1409   _max_reg = OptoReg::Name(0);  // Past max register used
1410   while( _simplified ) {
1411     // Pull next LRG from the simplified list - in reverse order of removal
1412     uint lidx = _simplified;
1413     LRG *lrg = &lrgs(lidx);
1414     _simplified = lrg->_next;
1415 
1416 
1417 #ifndef PRODUCT
1418     if (trace_spilling()) {
1419       ttyLocker ttyl;
1420       tty->print_cr("L%d selecting degree %d degrees_of_freedom %d", lidx, lrg->degree(),
1421                     lrg->degrees_of_freedom());
1422       lrg->dump();
1423     }
1424 #endif
1425 
1426     // Re-insert into the IFG
1427     _ifg->re_insert(lidx);
1428     if( !lrg->alive() ) continue;
1429     // capture allstackedness flag before mask is hacked
1430     const int is_allstack = lrg->mask().is_AllStack();
1431 
1432     // Yeah, yeah, yeah, I know, I know.  I can refactor this
1433     // to avoid the GOTO, although the refactored code will not
1434     // be much clearer.  We arrive here IFF we have a stack-based
1435     // live range that cannot color in the current chunk, and it
1436     // has to move into the next free stack chunk.
1437     int chunk = 0;              // Current chunk is first chunk
1438     retry_next_chunk:
1439 
1440     // Remove neighbor colors
1441     IndexSet *s = _ifg->neighbors(lidx);
1442 
1443     debug_only(RegMask orig_mask = lrg->mask();)
1444     IndexSetIterator elements(s);
1445     uint neighbor;
1446     while ((neighbor = elements.next()) != 0) {
1447       // Note that neighbor might be a spill_reg.  In this case, exclusion
1448       // of its color will be a no-op, since the spill_reg chunk is in outer
1449       // space.  Also, if neighbor is in a different chunk, this exclusion
1450       // will be a no-op.  (Later on, if lrg runs out of possible colors in
1451       // its chunk, a new chunk of color may be tried, in which case
1452       // examination of neighbors is started again, at retry_next_chunk.)
1453       LRG &nlrg = lrgs(neighbor);
1454       OptoReg::Name nreg = nlrg.reg();
1455       // Only subtract masks in the same chunk
1456       if( nreg >= chunk && nreg < chunk + RegMask::CHUNK_SIZE ) {
1457 #ifndef PRODUCT
1458         uint size = lrg->mask().Size();
1459         RegMask rm = lrg->mask();
1460 #endif
1461         lrg->SUBTRACT(nlrg.mask());
1462 #ifndef PRODUCT
1463         if (trace_spilling() && lrg->mask().Size() != size) {
1464           ttyLocker ttyl;
1465           tty->print("L%d ", lidx);
1466           rm.dump();
1467           tty->print(" intersected L%d ", neighbor);
1468           nlrg.mask().dump();
1469           tty->print(" removed ");
1470           rm.SUBTRACT(lrg->mask());
1471           rm.dump();
1472           tty->print(" leaving ");
1473           lrg->mask().dump();
1474           tty->cr();
1475         }
1476 #endif
1477       }
1478     }
1479     //assert(is_allstack == lrg->mask().is_AllStack(), "nbrs must not change AllStackedness");
1480     // Aligned pairs need aligned masks
1481     assert(!lrg->_is_vector || !lrg->_fat_proj, "sanity");
1482     if (lrg->num_regs() > 1 && !lrg->_fat_proj) {
1483       lrg->clear_to_sets();
1484     }
1485 
1486     // Check if a color is available and if so pick the color
1487     OptoReg::Name reg = choose_color( *lrg, chunk );
1488 #ifdef SPARC
1489     debug_only(lrg->compute_set_mask_size());
1490     assert(lrg->num_regs() < 2 || lrg->is_bound() || is_even(reg-1), "allocate all doubles aligned");
1491 #endif
1492 
1493     //---------------
1494     // If we fail to color and the AllStack flag is set, trigger
1495     // a chunk-rollover event
1496     if(!OptoReg::is_valid(OptoReg::add(reg,-chunk)) && is_allstack) {
1497       // Bump register mask up to next stack chunk
1498       chunk += RegMask::CHUNK_SIZE;
1499       lrg->Set_All();
1500 
1501       goto retry_next_chunk;
1502     }
1503 
1504     //---------------
1505     // Did we get a color?
1506     else if( OptoReg::is_valid(reg)) {
1507 #ifndef PRODUCT
1508       RegMask avail_rm = lrg->mask();
1509 #endif
1510 
1511       // Record selected register
1512       lrg->set_reg(reg);
1513 
1514       if( reg >= _max_reg )     // Compute max register limit
1515         _max_reg = OptoReg::add(reg,1);
1516       // Fold reg back into normal space
1517       reg = OptoReg::add(reg,-chunk);
1518 
1519       // If the live range is not bound, then we actually had some choices
1520       // to make.  In this case, the mask has more bits in it than the colors
1521       // chosen.  Restrict the mask to just what was picked.
1522       int n_regs = lrg->num_regs();
1523       assert(!lrg->_is_vector || !lrg->_fat_proj, "sanity");
1524       if (n_regs == 1 || !lrg->_fat_proj) {
1525         assert(!lrg->_is_vector || n_regs <= RegMask::SlotsPerVecY, "sanity");
1526         lrg->Clear();           // Clear the mask
1527         lrg->Insert(reg);       // Set regmask to match selected reg
1528         // For vectors and pairs, also insert the low bit of the pair
1529         for (int i = 1; i < n_regs; i++)
1530           lrg->Insert(OptoReg::add(reg,-i));
1531         lrg->set_mask_size(n_regs);
1532       } else {                  // Else fatproj
1533         // mask must be equal to fatproj bits, by definition
1534       }
1535 #ifndef PRODUCT
1536       if (trace_spilling()) {
1537         ttyLocker ttyl;
1538         tty->print("L%d selected ", lidx);
1539         lrg->mask().dump();
1540         tty->print(" from ");
1541         avail_rm.dump();
1542         tty->cr();
1543       }
1544 #endif
1545       // Note that reg is the highest-numbered register in the newly-bound mask.
1546     } // end color available case
1547 
1548     //---------------
1549     // Live range is live and no colors available
1550     else {
1551       assert( lrg->alive(), "" );
1552       assert( !lrg->_fat_proj || lrg->is_multidef() ||
1553               lrg->_def->outcnt() > 0, "fat_proj cannot spill");
1554       assert( !orig_mask.is_AllStack(), "All Stack does not spill" );
1555 
1556       // Assign the special spillreg register
1557       lrg->set_reg(OptoReg::Name(spill_reg++));
1558       // Do not empty the regmask; leave mask_size lying around
1559       // for use during Spilling
1560 #ifndef PRODUCT
1561       if( trace_spilling() ) {
1562         ttyLocker ttyl;
1563         tty->print("L%d spilling with neighbors: ", lidx);
1564         s->dump();
1565         debug_only(tty->print(" original mask: "));
1566         debug_only(orig_mask.dump());
1567         dump_lrg(lidx);
1568       }
1569 #endif
1570     } // end spill case
1571 
1572   }
1573 
1574   return spill_reg-LRG::SPILL_REG;      // Return number of spills
1575 }
1576 
1577 
1578 //------------------------------copy_was_spilled-------------------------------
1579 // Copy 'was_spilled'-edness from the source Node to the dst Node.
1580 void PhaseChaitin::copy_was_spilled( Node *src, Node *dst ) {
1581   if( _spilled_once.test(src->_idx) ) {
1582     _spilled_once.set(dst->_idx);
1583     lrgs(_lrg_map.find(dst))._was_spilled1 = 1;
1584     if( _spilled_twice.test(src->_idx) ) {
1585       _spilled_twice.set(dst->_idx);
1586       lrgs(_lrg_map.find(dst))._was_spilled2 = 1;
1587     }
1588   }
1589 }
1590 
1591 //------------------------------set_was_spilled--------------------------------
1592 // Set the 'spilled_once' or 'spilled_twice' flag on a node.
1593 void PhaseChaitin::set_was_spilled( Node *n ) {
1594   if( _spilled_once.test_set(n->_idx) )
1595     _spilled_twice.set(n->_idx);
1596 }
1597 
1598 //------------------------------fixup_spills-----------------------------------
1599 // Convert Ideal spill instructions into proper FramePtr + offset Loads and
1600 // Stores.  Use-def chains are NOT preserved, but Node->LRG->reg maps are.
1601 void PhaseChaitin::fixup_spills() {
1602   // This function does only cisc spill work.
1603   if( !UseCISCSpill ) return;
1604 
1605   NOT_PRODUCT( Compile::TracePhase t3("fixupSpills", &_t_fixupSpills, TimeCompiler); )
1606 
1607   // Grab the Frame Pointer
1608   Node *fp = _cfg._broot->head()->in(1)->in(TypeFunc::FramePtr);
1609 
1610   // For all blocks
1611   for( uint i = 0; i < _cfg._num_blocks; i++ ) {
1612     Block *b = _cfg._blocks[i];
1613 
1614     // For all instructions in block
1615     uint last_inst = b->end_idx();
1616     for( uint j = 1; j <= last_inst; j++ ) {
1617       Node *n = b->_nodes[j];
1618 
1619       // Dead instruction???
1620       assert( n->outcnt() != 0 ||// Nothing dead after post alloc
1621               C->top() == n ||  // Or the random TOP node
1622               n->is_Proj(),     // Or a fat-proj kill node
1623               "No dead instructions after post-alloc" );
1624 
1625       int inp = n->cisc_operand();
1626       if( inp != AdlcVMDeps::Not_cisc_spillable ) {
1627         // Convert operand number to edge index number
1628         MachNode *mach = n->as_Mach();
1629         inp = mach->operand_index(inp);
1630         Node *src = n->in(inp);   // Value to load or store
1631         LRG &lrg_cisc = lrgs(_lrg_map.find_const(src));
1632         OptoReg::Name src_reg = lrg_cisc.reg();
1633         // Doubles record the HIGH register of an adjacent pair.
1634         src_reg = OptoReg::add(src_reg,1-lrg_cisc.num_regs());
1635         if( OptoReg::is_stack(src_reg) ) { // If input is on stack
1636           // This is a CISC Spill, get stack offset and construct new node
1637 #ifndef PRODUCT
1638           if( TraceCISCSpill ) {
1639             tty->print("    reg-instr:  ");
1640             n->dump();
1641           }
1642 #endif
1643           int stk_offset = reg2offset(src_reg);
1644           // Bailout if we might exceed node limit when spilling this instruction
1645           C->check_node_count(0, "out of nodes fixing spills");
1646           if (C->failing())  return;
1647           // Transform node
1648           MachNode *cisc = mach->cisc_version(stk_offset, C)->as_Mach();
1649           cisc->set_req(inp,fp);          // Base register is frame pointer
1650           if( cisc->oper_input_base() > 1 && mach->oper_input_base() <= 1 ) {
1651             assert( cisc->oper_input_base() == 2, "Only adding one edge");
1652             cisc->ins_req(1,src);         // Requires a memory edge
1653           }
1654           b->_nodes.map(j,cisc);          // Insert into basic block
1655           n->subsume_by(cisc, C); // Correct graph
1656           //
1657           ++_used_cisc_instructions;
1658 #ifndef PRODUCT
1659           if( TraceCISCSpill ) {
1660             tty->print("    cisc-instr: ");
1661             cisc->dump();
1662           }
1663 #endif
1664         } else {
1665 #ifndef PRODUCT
1666           if( TraceCISCSpill ) {
1667             tty->print("    using reg-instr: ");
1668             n->dump();
1669           }
1670 #endif
1671           ++_unused_cisc_instructions;    // input can be on stack
1672         }
1673       }
1674 
1675     } // End of for all instructions
1676 
1677   } // End of for all blocks
1678 }
1679 
1680 //------------------------------find_base_for_derived--------------------------
1681 // Helper to stretch above; recursively discover the base Node for a
1682 // given derived Node.  Easy for AddP-related machine nodes, but needs
1683 // to be recursive for derived Phis.
1684 Node *PhaseChaitin::find_base_for_derived( Node **derived_base_map, Node *derived, uint &maxlrg ) {
1685   // See if already computed; if so return it
1686   if( derived_base_map[derived->_idx] )
1687     return derived_base_map[derived->_idx];
1688 
1689   // See if this happens to be a base.
1690   // NOTE: we use TypePtr instead of TypeOopPtr because we can have
1691   // pointers derived from NULL!  These are always along paths that
1692   // can't happen at run-time but the optimizer cannot deduce it so
1693   // we have to handle it gracefully.
1694   assert(!derived->bottom_type()->isa_narrowoop() ||
1695           derived->bottom_type()->make_ptr()->is_ptr()->_offset == 0, "sanity");
1696   const TypePtr *tj = derived->bottom_type()->isa_ptr();
1697   // If its an OOP with a non-zero offset, then it is derived.
1698   if( tj == NULL || tj->_offset == 0 ) {
1699     derived_base_map[derived->_idx] = derived;
1700     return derived;
1701   }
1702   // Derived is NULL+offset?  Base is NULL!
1703   if( derived->is_Con() ) {
1704     Node *base = _matcher.mach_null();
1705     assert(base != NULL, "sanity");
1706     if (base->in(0) == NULL) {
1707       // Initialize it once and make it shared:
1708       // set control to _root and place it into Start block
1709       // (where top() node is placed).
1710       base->init_req(0, _cfg._root);
1711       Block *startb = _cfg.get_block_for_node(C->top());
1712       startb->_nodes.insert(startb->find_node(C->top()), base );
1713       _cfg.map_node_to_block(base, startb);
1714       assert(_lrg_map.live_range_id(base) == 0, "should not have LRG yet");
1715     }
1716     if (_lrg_map.live_range_id(base) == 0) {
1717       new_lrg(base, maxlrg++);
1718     }
1719     assert(base->in(0) == _cfg._root && _cfg.get_block_for_node(base) == _cfg.get_block_for_node(C->top()), "base NULL should be shared");
1720     derived_base_map[derived->_idx] = base;
1721     return base;
1722   }
1723 
1724   // Check for AddP-related opcodes
1725   if (!derived->is_Phi()) {
1726     assert(derived->as_Mach()->ideal_Opcode() == Op_AddP, err_msg_res("but is: %s", derived->Name()));
1727     Node *base = derived->in(AddPNode::Base);
1728     derived_base_map[derived->_idx] = base;
1729     return base;
1730   }
1731 
1732   // Recursively find bases for Phis.
1733   // First check to see if we can avoid a base Phi here.
1734   Node *base = find_base_for_derived( derived_base_map, derived->in(1),maxlrg);
1735   uint i;
1736   for( i = 2; i < derived->req(); i++ )
1737     if( base != find_base_for_derived( derived_base_map,derived->in(i),maxlrg))
1738       break;
1739   // Went to the end without finding any different bases?
1740   if( i == derived->req() ) {   // No need for a base Phi here
1741     derived_base_map[derived->_idx] = base;
1742     return base;
1743   }
1744 
1745   // Now we see we need a base-Phi here to merge the bases
1746   const Type *t = base->bottom_type();
1747   base = new (C) PhiNode( derived->in(0), t );
1748   for( i = 1; i < derived->req(); i++ ) {
1749     base->init_req(i, find_base_for_derived(derived_base_map, derived->in(i), maxlrg));
1750     t = t->meet(base->in(i)->bottom_type());
1751   }
1752   base->as_Phi()->set_type(t);
1753 
1754   // Search the current block for an existing base-Phi
1755   Block *b = _cfg.get_block_for_node(derived);
1756   for( i = 1; i <= b->end_idx(); i++ ) {// Search for matching Phi
1757     Node *phi = b->_nodes[i];
1758     if( !phi->is_Phi() ) {      // Found end of Phis with no match?
1759       b->_nodes.insert( i, base ); // Must insert created Phi here as base
1760       _cfg.map_node_to_block(base, b);
1761       new_lrg(base,maxlrg++);
1762       break;
1763     }
1764     // See if Phi matches.
1765     uint j;
1766     for( j = 1; j < base->req(); j++ )
1767       if( phi->in(j) != base->in(j) &&
1768           !(phi->in(j)->is_Con() && base->in(j)->is_Con()) ) // allow different NULLs
1769         break;
1770     if( j == base->req() ) {    // All inputs match?
1771       base = phi;               // Then use existing 'phi' and drop 'base'
1772       break;
1773     }
1774   }
1775 
1776 
1777   // Cache info for later passes
1778   derived_base_map[derived->_idx] = base;
1779   return base;
1780 }
1781 
1782 
1783 //------------------------------stretch_base_pointer_live_ranges---------------
1784 // At each Safepoint, insert extra debug edges for each pair of derived value/
1785 // base pointer that is live across the Safepoint for oopmap building.  The
1786 // edge pairs get added in after sfpt->jvmtail()->oopoff(), but are in the
1787 // required edge set.
1788 bool PhaseChaitin::stretch_base_pointer_live_ranges(ResourceArea *a) {
1789   int must_recompute_live = false;
1790   uint maxlrg = _lrg_map.max_lrg_id();
1791   Node **derived_base_map = (Node**)a->Amalloc(sizeof(Node*)*C->unique());
1792   memset( derived_base_map, 0, sizeof(Node*)*C->unique() );
1793 
1794   // For all blocks in RPO do...
1795   for( uint i=0; i<_cfg._num_blocks; i++ ) {
1796     Block *b = _cfg._blocks[i];
1797     // Note use of deep-copy constructor.  I cannot hammer the original
1798     // liveout bits, because they are needed by the following coalesce pass.
1799     IndexSet liveout(_live->live(b));
1800 
1801     for( uint j = b->end_idx() + 1; j > 1; j-- ) {
1802       Node *n = b->_nodes[j-1];
1803 
1804       // Pre-split compares of loop-phis.  Loop-phis form a cycle we would
1805       // like to see in the same register.  Compare uses the loop-phi and so
1806       // extends its live range BUT cannot be part of the cycle.  If this
1807       // extended live range overlaps with the update of the loop-phi value
1808       // we need both alive at the same time -- which requires at least 1
1809       // copy.  But because Intel has only 2-address registers we end up with
1810       // at least 2 copies, one before the loop-phi update instruction and
1811       // one after.  Instead we split the input to the compare just after the
1812       // phi.
1813       if( n->is_Mach() && n->as_Mach()->ideal_Opcode() == Op_CmpI ) {
1814         Node *phi = n->in(1);
1815         if( phi->is_Phi() && phi->as_Phi()->region()->is_Loop() ) {
1816           Block *phi_block = _cfg.get_block_for_node(phi);
1817           if (_cfg.get_block_for_node(phi_block->pred(2)) == b) {
1818             const RegMask *mask = C->matcher()->idealreg2spillmask[Op_RegI];
1819             Node *spill = new (C) MachSpillCopyNode( phi, *mask, *mask );
1820             insert_proj( phi_block, 1, spill, maxlrg++ );
1821             n->set_req(1,spill);
1822             must_recompute_live = true;
1823           }
1824         }
1825       }
1826 
1827       // Get value being defined
1828       uint lidx = _lrg_map.live_range_id(n);
1829       // Ignore the occasional brand-new live range
1830       if (lidx && lidx < _lrg_map.max_lrg_id()) {
1831         // Remove from live-out set
1832         liveout.remove(lidx);
1833 
1834         // Copies do not define a new value and so do not interfere.
1835         // Remove the copies source from the liveout set before interfering.
1836         uint idx = n->is_Copy();
1837         if (idx) {
1838           liveout.remove(_lrg_map.live_range_id(n->in(idx)));
1839         }
1840       }
1841 
1842       // Found a safepoint?
1843       JVMState *jvms = n->jvms();
1844       if( jvms ) {
1845         // Now scan for a live derived pointer
1846         IndexSetIterator elements(&liveout);
1847         uint neighbor;
1848         while ((neighbor = elements.next()) != 0) {
1849           // Find reaching DEF for base and derived values
1850           // This works because we are still in SSA during this call.
1851           Node *derived = lrgs(neighbor)._def;
1852           const TypePtr *tj = derived->bottom_type()->isa_ptr();
1853           assert(!derived->bottom_type()->isa_narrowoop() ||
1854                   derived->bottom_type()->make_ptr()->is_ptr()->_offset == 0, "sanity");
1855           // If its an OOP with a non-zero offset, then it is derived.
1856           if( tj && tj->_offset != 0 && tj->isa_oop_ptr() ) {
1857             Node *base = find_base_for_derived(derived_base_map, derived, maxlrg);
1858             assert(base->_idx < _lrg_map.size(), "");
1859             // Add reaching DEFs of derived pointer and base pointer as a
1860             // pair of inputs
1861             n->add_req(derived);
1862             n->add_req(base);
1863 
1864             // See if the base pointer is already live to this point.
1865             // Since I'm working on the SSA form, live-ness amounts to
1866             // reaching def's.  So if I find the base's live range then
1867             // I know the base's def reaches here.
1868             if ((_lrg_map.live_range_id(base) >= _lrg_map.max_lrg_id() || // (Brand new base (hence not live) or
1869                  !liveout.member(_lrg_map.live_range_id(base))) && // not live) AND
1870                  (_lrg_map.live_range_id(base) > 0) && // not a constant
1871                  _cfg.get_block_for_node(base) != b) { // base not def'd in blk)
1872               // Base pointer is not currently live.  Since I stretched
1873               // the base pointer to here and it crosses basic-block
1874               // boundaries, the global live info is now incorrect.
1875               // Recompute live.
1876               must_recompute_live = true;
1877             } // End of if base pointer is not live to debug info
1878           }
1879         } // End of scan all live data for derived ptrs crossing GC point
1880       } // End of if found a GC point
1881 
1882       // Make all inputs live
1883       if (!n->is_Phi()) {      // Phi function uses come from prior block
1884         for (uint k = 1; k < n->req(); k++) {
1885           uint lidx = _lrg_map.live_range_id(n->in(k));
1886           if (lidx < _lrg_map.max_lrg_id()) {
1887             liveout.insert(lidx);
1888           }
1889         }
1890       }
1891 
1892     } // End of forall instructions in block
1893     liveout.clear();  // Free the memory used by liveout.
1894 
1895   } // End of forall blocks
1896   _lrg_map.set_max_lrg_id(maxlrg);
1897 
1898   // If I created a new live range I need to recompute live
1899   if (maxlrg != _ifg->_maxlrg) {
1900     must_recompute_live = true;
1901   }
1902 
1903   return must_recompute_live != 0;
1904 }
1905 
1906 
1907 //------------------------------add_reference----------------------------------
1908 // Extend the node to LRG mapping
1909 
1910 void PhaseChaitin::add_reference(const Node *node, const Node *old_node) {
1911   _lrg_map.extend(node->_idx, _lrg_map.live_range_id(old_node));
1912 }
1913 
1914 //------------------------------dump-------------------------------------------
1915 #ifndef PRODUCT
1916 void PhaseChaitin::dump(const Node *n) const {
1917   uint r = (n->_idx < _lrg_map.size()) ? _lrg_map.find_const(n) : 0;
1918   tty->print("L%d",r);
1919   if (r && n->Opcode() != Op_Phi) {
1920     if( _node_regs ) {          // Got a post-allocation copy of allocation?
1921       tty->print("[");
1922       OptoReg::Name second = get_reg_second(n);
1923       if( OptoReg::is_valid(second) ) {
1924         if( OptoReg::is_reg(second) )
1925           tty->print("%s:",Matcher::regName[second]);
1926         else
1927           tty->print("%s+%d:",OptoReg::regname(OptoReg::c_frame_pointer), reg2offset_unchecked(second));
1928       }
1929       OptoReg::Name first = get_reg_first(n);
1930       if( OptoReg::is_reg(first) )
1931         tty->print("%s]",Matcher::regName[first]);
1932       else
1933          tty->print("%s+%d]",OptoReg::regname(OptoReg::c_frame_pointer), reg2offset_unchecked(first));
1934     } else
1935     n->out_RegMask().dump();
1936   }
1937   tty->print("/N%d\t",n->_idx);
1938   tty->print("%s === ", n->Name());
1939   uint k;
1940   for (k = 0; k < n->req(); k++) {
1941     Node *m = n->in(k);
1942     if (!m) {
1943       tty->print("_ ");
1944     }
1945     else {
1946       uint r = (m->_idx < _lrg_map.size()) ? _lrg_map.find_const(m) : 0;
1947       tty->print("L%d",r);
1948       // Data MultiNode's can have projections with no real registers.
1949       // Don't die while dumping them.
1950       int op = n->Opcode();
1951       if( r && op != Op_Phi && op != Op_Proj && op != Op_SCMemProj) {
1952         if( _node_regs ) {
1953           tty->print("[");
1954           OptoReg::Name second = get_reg_second(n->in(k));
1955           if( OptoReg::is_valid(second) ) {
1956             if( OptoReg::is_reg(second) )
1957               tty->print("%s:",Matcher::regName[second]);
1958             else
1959               tty->print("%s+%d:",OptoReg::regname(OptoReg::c_frame_pointer),
1960                          reg2offset_unchecked(second));
1961           }
1962           OptoReg::Name first = get_reg_first(n->in(k));
1963           if( OptoReg::is_reg(first) )
1964             tty->print("%s]",Matcher::regName[first]);
1965           else
1966             tty->print("%s+%d]",OptoReg::regname(OptoReg::c_frame_pointer),
1967                        reg2offset_unchecked(first));
1968         } else
1969           n->in_RegMask(k).dump();
1970       }
1971       tty->print("/N%d ",m->_idx);
1972     }
1973   }
1974   if( k < n->len() && n->in(k) ) tty->print("| ");
1975   for( ; k < n->len(); k++ ) {
1976     Node *m = n->in(k);
1977     if(!m) {
1978       break;
1979     }
1980     uint r = (m->_idx < _lrg_map.size()) ? _lrg_map.find_const(m) : 0;
1981     tty->print("L%d",r);
1982     tty->print("/N%d ",m->_idx);
1983   }
1984   if( n->is_Mach() ) n->as_Mach()->dump_spec(tty);
1985   else n->dump_spec(tty);
1986   if( _spilled_once.test(n->_idx ) ) {
1987     tty->print(" Spill_1");
1988     if( _spilled_twice.test(n->_idx ) )
1989       tty->print(" Spill_2");
1990   }
1991   tty->print("\n");
1992 }
1993 
1994 void PhaseChaitin::dump(const Block *b) const {
1995   b->dump_head(&_cfg);
1996 
1997   // For all instructions
1998   for( uint j = 0; j < b->_nodes.size(); j++ )
1999     dump(b->_nodes[j]);
2000   // Print live-out info at end of block
2001   if( _live ) {
2002     tty->print("Liveout: ");
2003     IndexSet *live = _live->live(b);
2004     IndexSetIterator elements(live);
2005     tty->print("{");
2006     uint i;
2007     while ((i = elements.next()) != 0) {
2008       tty->print("L%d ", _lrg_map.find_const(i));
2009     }
2010     tty->print_cr("}");
2011   }
2012   tty->print("\n");
2013 }
2014 
2015 void PhaseChaitin::dump() const {
2016   tty->print( "--- Chaitin -- argsize: %d  framesize: %d ---\n",
2017               _matcher._new_SP, _framesize );
2018 
2019   // For all blocks
2020   for( uint i = 0; i < _cfg._num_blocks; i++ )
2021     dump(_cfg._blocks[i]);
2022   // End of per-block dump
2023   tty->print("\n");
2024 
2025   if (!_ifg) {
2026     tty->print("(No IFG.)\n");
2027     return;
2028   }
2029 
2030   // Dump LRG array
2031   tty->print("--- Live RanGe Array ---\n");
2032   for (uint i2 = 1; i2 < _lrg_map.max_lrg_id(); i2++) {
2033     tty->print("L%d: ",i2);
2034     if (i2 < _ifg->_maxlrg) {
2035       lrgs(i2).dump();
2036     }
2037     else {
2038       tty->print_cr("new LRG");
2039     }
2040   }
2041   tty->print_cr("");
2042 
2043   // Dump lo-degree list
2044   tty->print("Lo degree: ");
2045   for(uint i3 = _lo_degree; i3; i3 = lrgs(i3)._next )
2046     tty->print("L%d ",i3);
2047   tty->print_cr("");
2048 
2049   // Dump lo-stk-degree list
2050   tty->print("Lo stk degree: ");
2051   for(uint i4 = _lo_stk_degree; i4; i4 = lrgs(i4)._next )
2052     tty->print("L%d ",i4);
2053   tty->print_cr("");
2054 
2055   // Dump lo-degree list
2056   tty->print("Hi degree: ");
2057   for(uint i5 = _hi_degree; i5; i5 = lrgs(i5)._next )
2058     tty->print("L%d ",i5);
2059   tty->print_cr("");
2060 }
2061 
2062 //------------------------------dump_degree_lists------------------------------
2063 void PhaseChaitin::dump_degree_lists() const {
2064   // Dump lo-degree list
2065   tty->print("Lo degree: ");
2066   for( uint i = _lo_degree; i; i = lrgs(i)._next )
2067     tty->print("L%d ",i);
2068   tty->print_cr("");
2069 
2070   // Dump lo-stk-degree list
2071   tty->print("Lo stk degree: ");
2072   for(uint i2 = _lo_stk_degree; i2; i2 = lrgs(i2)._next )
2073     tty->print("L%d ",i2);
2074   tty->print_cr("");
2075 
2076   // Dump lo-degree list
2077   tty->print("Hi degree: ");
2078   for(uint i3 = _hi_degree; i3; i3 = lrgs(i3)._next )
2079     tty->print("L%d ",i3);
2080   tty->print_cr("");
2081 }
2082 
2083 //------------------------------dump_simplified--------------------------------
2084 void PhaseChaitin::dump_simplified() const {
2085   tty->print("Simplified: ");
2086   for( uint i = _simplified; i; i = lrgs(i)._next )
2087     tty->print("L%d ",i);
2088   tty->print_cr("");
2089 }
2090 
2091 static char *print_reg( OptoReg::Name reg, const PhaseChaitin *pc, char *buf ) {
2092   if ((int)reg < 0)
2093     sprintf(buf, "<OptoReg::%d>", (int)reg);
2094   else if (OptoReg::is_reg(reg))
2095     strcpy(buf, Matcher::regName[reg]);
2096   else
2097     sprintf(buf,"%s + #%d",OptoReg::regname(OptoReg::c_frame_pointer),
2098             pc->reg2offset(reg));
2099   return buf+strlen(buf);
2100 }
2101 
2102 //------------------------------dump_register----------------------------------
2103 // Dump a register name into a buffer.  Be intelligent if we get called
2104 // before allocation is complete.
2105 char *PhaseChaitin::dump_register( const Node *n, char *buf  ) const {
2106   if( !this ) {                 // Not got anything?
2107     sprintf(buf,"N%d",n->_idx); // Then use Node index
2108   } else if( _node_regs ) {
2109     // Post allocation, use direct mappings, no LRG info available
2110     print_reg( get_reg_first(n), this, buf );
2111   } else {
2112     uint lidx = _lrg_map.find_const(n); // Grab LRG number
2113     if( !_ifg ) {
2114       sprintf(buf,"L%d",lidx);  // No register binding yet
2115     } else if( !lidx ) {        // Special, not allocated value
2116       strcpy(buf,"Special");
2117     } else {
2118       if (lrgs(lidx)._is_vector) {
2119         if (lrgs(lidx).mask().is_bound_set(lrgs(lidx).num_regs()))
2120           print_reg( lrgs(lidx).reg(), this, buf ); // a bound machine register
2121         else
2122           sprintf(buf,"L%d",lidx); // No register binding yet
2123       } else if( (lrgs(lidx).num_regs() == 1)
2124                  ? lrgs(lidx).mask().is_bound1()
2125                  : lrgs(lidx).mask().is_bound_pair() ) {
2126         // Hah!  We have a bound machine register
2127         print_reg( lrgs(lidx).reg(), this, buf );
2128       } else {
2129         sprintf(buf,"L%d",lidx); // No register binding yet
2130       }
2131     }
2132   }
2133   return buf+strlen(buf);
2134 }
2135 
2136 //----------------------dump_for_spill_split_recycle--------------------------
2137 void PhaseChaitin::dump_for_spill_split_recycle() const {
2138   if( WizardMode && (PrintCompilation || PrintOpto) ) {
2139     // Display which live ranges need to be split and the allocator's state
2140     tty->print_cr("Graph-Coloring Iteration %d will split the following live ranges", _trip_cnt);
2141     for (uint bidx = 1; bidx < _lrg_map.max_lrg_id(); bidx++) {
2142       if( lrgs(bidx).alive() && lrgs(bidx).reg() >= LRG::SPILL_REG ) {
2143         tty->print("L%d: ", bidx);
2144         lrgs(bidx).dump();
2145       }
2146     }
2147     tty->cr();
2148     dump();
2149   }
2150 }
2151 
2152 //------------------------------dump_frame------------------------------------
2153 void PhaseChaitin::dump_frame() const {
2154   const char *fp = OptoReg::regname(OptoReg::c_frame_pointer);
2155   const TypeTuple *domain = C->tf()->domain();
2156   const int        argcnt = domain->cnt() - TypeFunc::Parms;
2157 
2158   // Incoming arguments in registers dump
2159   for( int k = 0; k < argcnt; k++ ) {
2160     OptoReg::Name parmreg = _matcher._parm_regs[k].first();
2161     if( OptoReg::is_reg(parmreg))  {
2162       const char *reg_name = OptoReg::regname(parmreg);
2163       tty->print("#r%3.3d %s", parmreg, reg_name);
2164       parmreg = _matcher._parm_regs[k].second();
2165       if( OptoReg::is_reg(parmreg))  {
2166         tty->print(":%s", OptoReg::regname(parmreg));
2167       }
2168       tty->print("   : parm %d: ", k);
2169       domain->field_at(k + TypeFunc::Parms)->dump();
2170       tty->print_cr("");
2171     }
2172   }
2173 
2174   // Check for un-owned padding above incoming args
2175   OptoReg::Name reg = _matcher._new_SP;
2176   if( reg > _matcher._in_arg_limit ) {
2177     reg = OptoReg::add(reg, -1);
2178     tty->print_cr("#r%3.3d %s+%2d: pad0, owned by CALLER", reg, fp, reg2offset_unchecked(reg));
2179   }
2180 
2181   // Incoming argument area dump
2182   OptoReg::Name begin_in_arg = OptoReg::add(_matcher._old_SP,C->out_preserve_stack_slots());
2183   while( reg > begin_in_arg ) {
2184     reg = OptoReg::add(reg, -1);
2185     tty->print("#r%3.3d %s+%2d: ",reg,fp,reg2offset_unchecked(reg));
2186     int j;
2187     for( j = 0; j < argcnt; j++) {
2188       if( _matcher._parm_regs[j].first() == reg ||
2189           _matcher._parm_regs[j].second() == reg ) {
2190         tty->print("parm %d: ",j);
2191         domain->field_at(j + TypeFunc::Parms)->dump();
2192         tty->print_cr("");
2193         break;
2194       }
2195     }
2196     if( j >= argcnt )
2197       tty->print_cr("HOLE, owned by SELF");
2198   }
2199 
2200   // Old outgoing preserve area
2201   while( reg > _matcher._old_SP ) {
2202     reg = OptoReg::add(reg, -1);
2203     tty->print_cr("#r%3.3d %s+%2d: old out preserve",reg,fp,reg2offset_unchecked(reg));
2204   }
2205 
2206   // Old SP
2207   tty->print_cr("# -- Old %s -- Framesize: %d --",fp,
2208     reg2offset_unchecked(OptoReg::add(_matcher._old_SP,-1)) - reg2offset_unchecked(_matcher._new_SP)+jintSize);
2209 
2210   // Preserve area dump
2211   int fixed_slots = C->fixed_slots();
2212   OptoReg::Name begin_in_preserve = OptoReg::add(_matcher._old_SP, -(int)C->in_preserve_stack_slots());
2213   OptoReg::Name return_addr = _matcher.return_addr();
2214 
2215   reg = OptoReg::add(reg, -1);
2216   while (OptoReg::is_stack(reg)) {
2217     tty->print("#r%3.3d %s+%2d: ",reg,fp,reg2offset_unchecked(reg));
2218     if (return_addr == reg) {
2219       tty->print_cr("return address");
2220     } else if (reg >= begin_in_preserve) {
2221       // Preserved slots are present on x86
2222       if (return_addr == OptoReg::add(reg, VMRegImpl::slots_per_word))
2223         tty->print_cr("saved fp register");
2224       else if (return_addr == OptoReg::add(reg, 2*VMRegImpl::slots_per_word) &&
2225                VerifyStackAtCalls)
2226         tty->print_cr("0xBADB100D   +VerifyStackAtCalls");
2227       else
2228         tty->print_cr("in_preserve");
2229     } else if ((int)OptoReg::reg2stack(reg) < fixed_slots) {
2230       tty->print_cr("Fixed slot %d", OptoReg::reg2stack(reg));
2231     } else {
2232       tty->print_cr("pad2, stack alignment");
2233     }
2234     reg = OptoReg::add(reg, -1);
2235   }
2236 
2237   // Spill area dump
2238   reg = OptoReg::add(_matcher._new_SP, _framesize );
2239   while( reg > _matcher._out_arg_limit ) {
2240     reg = OptoReg::add(reg, -1);
2241     tty->print_cr("#r%3.3d %s+%2d: spill",reg,fp,reg2offset_unchecked(reg));
2242   }
2243 
2244   // Outgoing argument area dump
2245   while( reg > OptoReg::add(_matcher._new_SP, C->out_preserve_stack_slots()) ) {
2246     reg = OptoReg::add(reg, -1);
2247     tty->print_cr("#r%3.3d %s+%2d: outgoing argument",reg,fp,reg2offset_unchecked(reg));
2248   }
2249 
2250   // Outgoing new preserve area
2251   while( reg > _matcher._new_SP ) {
2252     reg = OptoReg::add(reg, -1);
2253     tty->print_cr("#r%3.3d %s+%2d: new out preserve",reg,fp,reg2offset_unchecked(reg));
2254   }
2255   tty->print_cr("#");
2256 }
2257 
2258 //------------------------------dump_bb----------------------------------------
2259 void PhaseChaitin::dump_bb( uint pre_order ) const {
2260   tty->print_cr("---dump of B%d---",pre_order);
2261   for( uint i = 0; i < _cfg._num_blocks; i++ ) {
2262     Block *b = _cfg._blocks[i];
2263     if( b->_pre_order == pre_order )
2264       dump(b);
2265   }
2266 }
2267 
2268 //------------------------------dump_lrg---------------------------------------
2269 void PhaseChaitin::dump_lrg( uint lidx, bool defs_only ) const {
2270   tty->print_cr("---dump of L%d---",lidx);
2271 
2272   if (_ifg) {
2273     if (lidx >= _lrg_map.max_lrg_id()) {
2274       tty->print("Attempt to print live range index beyond max live range.\n");
2275       return;
2276     }
2277     tty->print("L%d: ",lidx);
2278     if (lidx < _ifg->_maxlrg) {
2279       lrgs(lidx).dump();
2280     } else {
2281       tty->print_cr("new LRG");
2282     }
2283   }
2284   if( _ifg && lidx < _ifg->_maxlrg) {
2285     tty->print("Neighbors: %d - ", _ifg->neighbor_cnt(lidx));
2286     _ifg->neighbors(lidx)->dump();
2287     tty->cr();
2288   }
2289   // For all blocks
2290   for( uint i = 0; i < _cfg._num_blocks; i++ ) {
2291     Block *b = _cfg._blocks[i];
2292     int dump_once = 0;
2293 
2294     // For all instructions
2295     for( uint j = 0; j < b->_nodes.size(); j++ ) {
2296       Node *n = b->_nodes[j];
2297       if (_lrg_map.find_const(n) == lidx) {
2298         if (!dump_once++) {
2299           tty->cr();
2300           b->dump_head(&_cfg);
2301         }
2302         dump(n);
2303         continue;
2304       }
2305       if (!defs_only) {
2306         uint cnt = n->req();
2307         for( uint k = 1; k < cnt; k++ ) {
2308           Node *m = n->in(k);
2309           if (!m)  {
2310             continue;  // be robust in the dumper
2311           }
2312           if (_lrg_map.find_const(m) == lidx) {
2313             if (!dump_once++) {
2314               tty->cr();
2315               b->dump_head(&_cfg);
2316             }
2317             dump(n);
2318           }
2319         }
2320       }
2321     }
2322   } // End of per-block dump
2323   tty->cr();
2324 }
2325 #endif // not PRODUCT
2326 
2327 //------------------------------print_chaitin_statistics-------------------------------
2328 int PhaseChaitin::_final_loads  = 0;
2329 int PhaseChaitin::_final_stores = 0;
2330 int PhaseChaitin::_final_memoves= 0;
2331 int PhaseChaitin::_final_copies = 0;
2332 double PhaseChaitin::_final_load_cost  = 0;
2333 double PhaseChaitin::_final_store_cost = 0;
2334 double PhaseChaitin::_final_memove_cost= 0;
2335 double PhaseChaitin::_final_copy_cost  = 0;
2336 int PhaseChaitin::_conserv_coalesce = 0;
2337 int PhaseChaitin::_conserv_coalesce_pair = 0;
2338 int PhaseChaitin::_conserv_coalesce_trie = 0;
2339 int PhaseChaitin::_conserv_coalesce_quad = 0;
2340 int PhaseChaitin::_post_alloc = 0;
2341 int PhaseChaitin::_lost_opp_pp_coalesce = 0;
2342 int PhaseChaitin::_lost_opp_cflow_coalesce = 0;
2343 int PhaseChaitin::_used_cisc_instructions   = 0;
2344 int PhaseChaitin::_unused_cisc_instructions = 0;
2345 int PhaseChaitin::_allocator_attempts       = 0;
2346 int PhaseChaitin::_allocator_successes      = 0;
2347 
2348 #ifndef PRODUCT
2349 uint PhaseChaitin::_high_pressure           = 0;
2350 uint PhaseChaitin::_low_pressure            = 0;
2351 
2352 void PhaseChaitin::print_chaitin_statistics() {
2353   tty->print_cr("Inserted %d spill loads, %d spill stores, %d mem-mem moves and %d copies.", _final_loads, _final_stores, _final_memoves, _final_copies);
2354   tty->print_cr("Total load cost= %6.0f, store cost = %6.0f, mem-mem cost = %5.2f, copy cost = %5.0f.", _final_load_cost, _final_store_cost, _final_memove_cost, _final_copy_cost);
2355   tty->print_cr("Adjusted spill cost = %7.0f.",
2356                 _final_load_cost*4.0 + _final_store_cost  * 2.0 +
2357                 _final_copy_cost*1.0 + _final_memove_cost*12.0);
2358   tty->print("Conservatively coalesced %d copies, %d pairs",
2359                 _conserv_coalesce, _conserv_coalesce_pair);
2360   if( _conserv_coalesce_trie || _conserv_coalesce_quad )
2361     tty->print(", %d tries, %d quads", _conserv_coalesce_trie, _conserv_coalesce_quad);
2362   tty->print_cr(", %d post alloc.", _post_alloc);
2363   if( _lost_opp_pp_coalesce || _lost_opp_cflow_coalesce )
2364     tty->print_cr("Lost coalesce opportunity, %d private-private, and %d cflow interfered.",
2365                   _lost_opp_pp_coalesce, _lost_opp_cflow_coalesce );
2366   if( _used_cisc_instructions || _unused_cisc_instructions )
2367     tty->print_cr("Used cisc instruction  %d,  remained in register %d",
2368                    _used_cisc_instructions, _unused_cisc_instructions);
2369   if( _allocator_successes != 0 )
2370     tty->print_cr("Average allocation trips %f", (float)_allocator_attempts/(float)_allocator_successes);
2371   tty->print_cr("High Pressure Blocks = %d, Low Pressure Blocks = %d", _high_pressure, _low_pressure);
2372 }
2373 #endif // not PRODUCT