278 uint src = _lrg_map.find(src_n);
279 uint dst = _lrg_map.find(dst_n);
280 assert(src, "");
281 assert(dst, "");
282 assert(src < _lrg_map.max_lrg_id(), "oob");
283 assert(dst < _lrg_map.max_lrg_id(), "oob");
284 assert(src < dst, "always union smaller");
285 _lrg_map.uf_map(dst, src);
286 }
287
288 //------------------------------new_lrg----------------------------------------
289 void PhaseChaitin::new_lrg(const Node *x, uint lrg) {
290 // Make the Node->LRG mapping
291 _lrg_map.extend(x->_idx,lrg);
292 // Make the Union-Find mapping an identity function
293 _lrg_map.uf_extend(lrg, lrg);
294 }
295
296
297 bool PhaseChaitin::clone_projs_shared(Block *b, uint idx, Node *con, Node *copy, uint max_lrg_id) {
298 Block *bcon = _cfg._bbs[con->_idx];
299 uint cindex = bcon->find_node(con);
300 Node *con_next = bcon->_nodes[cindex+1];
301 if (con_next->in(0) != con || !con_next->is_MachProj()) {
302 return false; // No MachProj's follow
303 }
304
305 // Copy kills after the cloned constant
306 Node *kills = con_next->clone();
307 kills->set_req(0, copy);
308 b->_nodes.insert(idx, kills);
309 _cfg._bbs.map(kills->_idx, b);
310 new_lrg(kills, max_lrg_id);
311 return true;
312 }
313
314 //------------------------------compact----------------------------------------
315 // Renumber the live ranges to compact them. Makes the IFG smaller.
316 void PhaseChaitin::compact() {
317 // Current the _uf_map contains a series of short chains which are headed
318 // by a self-cycle. All the chains run from big numbers to little numbers.
319 // The Find() call chases the chains & shortens them for the next Find call.
320 // We are going to change this structure slightly. Numbers above a moving
321 // wave 'i' are unchanged. Numbers below 'j' point directly to their
322 // compacted live range with no further chaining. There are no chains or
323 // cycles below 'i', so the Find call no longer works.
324 uint j=1;
325 uint i;
326 for (i = 1; i < _lrg_map.max_lrg_id(); i++) {
327 uint lr = _lrg_map.uf_live_range_id(i);
328 // Ignore unallocated live ranges
329 if (!lr) {
945 #endif
946 n->as_Mach()->use_cisc_RegMask();
947 }
948
949 LRG &lrg = lrgs(vreg);
950 // // Testing for floating point code shape
951 // Node *test = n->in(k);
952 // if( test->is_Mach() ) {
953 // MachNode *m = test->as_Mach();
954 // int op = m->ideal_Opcode();
955 // if (n->is_Call() && (op == Op_AddF || op == Op_MulF) ) {
956 // int zzz = 1;
957 // }
958 // }
959
960 // Limit result register mask to acceptable registers.
961 // Do not limit registers from uncommon uses before
962 // AggressiveCoalesce. This effectively pre-virtual-splits
963 // around uncommon uses of common defs.
964 const RegMask &rm = n->in_RegMask(k);
965 if( !after_aggressive &&
966 _cfg._bbs[n->in(k)->_idx]->_freq > 1000*b->_freq ) {
967 // Since we are BEFORE aggressive coalesce, leave the register
968 // mask untrimmed by the call. This encourages more coalescing.
969 // Later, AFTER aggressive, this live range will have to spill
970 // but the spiller handles slow-path calls very nicely.
971 } else {
972 lrg.AND( rm );
973 }
974
975 // Check for bound register masks
976 const RegMask &lrgmask = lrg.mask();
977 int kreg = n->in(k)->ideal_reg();
978 bool is_vect = RegMask::is_vector(kreg);
979 assert(n->in(k)->bottom_type()->isa_vect() == NULL ||
980 is_vect || kreg == Op_RegD,
981 "vector must be in vector registers");
982 if (lrgmask.is_bound(kreg))
983 lrg._is_bound = 1;
984
985 // If this use of a double forces a mis-aligned double,
986 // flag as '_fat_proj' - really flag as allowing misalignment
1692 // pointers derived from NULL! These are always along paths that
1693 // can't happen at run-time but the optimizer cannot deduce it so
1694 // we have to handle it gracefully.
1695 assert(!derived->bottom_type()->isa_narrowoop() ||
1696 derived->bottom_type()->make_ptr()->is_ptr()->_offset == 0, "sanity");
1697 const TypePtr *tj = derived->bottom_type()->isa_ptr();
1698 // If its an OOP with a non-zero offset, then it is derived.
1699 if( tj == NULL || tj->_offset == 0 ) {
1700 derived_base_map[derived->_idx] = derived;
1701 return derived;
1702 }
1703 // Derived is NULL+offset? Base is NULL!
1704 if( derived->is_Con() ) {
1705 Node *base = _matcher.mach_null();
1706 assert(base != NULL, "sanity");
1707 if (base->in(0) == NULL) {
1708 // Initialize it once and make it shared:
1709 // set control to _root and place it into Start block
1710 // (where top() node is placed).
1711 base->init_req(0, _cfg._root);
1712 Block *startb = _cfg._bbs[C->top()->_idx];
1713 startb->_nodes.insert(startb->find_node(C->top()), base );
1714 _cfg._bbs.map( base->_idx, startb );
1715 assert(_lrg_map.live_range_id(base) == 0, "should not have LRG yet");
1716 }
1717 if (_lrg_map.live_range_id(base) == 0) {
1718 new_lrg(base, maxlrg++);
1719 }
1720 assert(base->in(0) == _cfg._root &&
1721 _cfg._bbs[base->_idx] == _cfg._bbs[C->top()->_idx], "base NULL should be shared");
1722 derived_base_map[derived->_idx] = base;
1723 return base;
1724 }
1725
1726 // Check for AddP-related opcodes
1727 if (!derived->is_Phi()) {
1728 assert(derived->as_Mach()->ideal_Opcode() == Op_AddP, err_msg_res("but is: %s", derived->Name()));
1729 Node *base = derived->in(AddPNode::Base);
1730 derived_base_map[derived->_idx] = base;
1731 return base;
1732 }
1733
1734 // Recursively find bases for Phis.
1735 // First check to see if we can avoid a base Phi here.
1736 Node *base = find_base_for_derived( derived_base_map, derived->in(1),maxlrg);
1737 uint i;
1738 for( i = 2; i < derived->req(); i++ )
1739 if( base != find_base_for_derived( derived_base_map,derived->in(i),maxlrg))
1740 break;
1741 // Went to the end without finding any different bases?
1742 if( i == derived->req() ) { // No need for a base Phi here
1743 derived_base_map[derived->_idx] = base;
1744 return base;
1745 }
1746
1747 // Now we see we need a base-Phi here to merge the bases
1748 const Type *t = base->bottom_type();
1749 base = new (C) PhiNode( derived->in(0), t );
1750 for( i = 1; i < derived->req(); i++ ) {
1751 base->init_req(i, find_base_for_derived(derived_base_map, derived->in(i), maxlrg));
1752 t = t->meet(base->in(i)->bottom_type());
1753 }
1754 base->as_Phi()->set_type(t);
1755
1756 // Search the current block for an existing base-Phi
1757 Block *b = _cfg._bbs[derived->_idx];
1758 for( i = 1; i <= b->end_idx(); i++ ) {// Search for matching Phi
1759 Node *phi = b->_nodes[i];
1760 if( !phi->is_Phi() ) { // Found end of Phis with no match?
1761 b->_nodes.insert( i, base ); // Must insert created Phi here as base
1762 _cfg._bbs.map( base->_idx, b );
1763 new_lrg(base,maxlrg++);
1764 break;
1765 }
1766 // See if Phi matches.
1767 uint j;
1768 for( j = 1; j < base->req(); j++ )
1769 if( phi->in(j) != base->in(j) &&
1770 !(phi->in(j)->is_Con() && base->in(j)->is_Con()) ) // allow different NULLs
1771 break;
1772 if( j == base->req() ) { // All inputs match?
1773 base = phi; // Then use existing 'phi' and drop 'base'
1774 break;
1775 }
1776 }
1777
1778
1779 // Cache info for later passes
1780 derived_base_map[derived->_idx] = base;
1781 return base;
1782 }
1798 Block *b = _cfg._blocks[i];
1799 // Note use of deep-copy constructor. I cannot hammer the original
1800 // liveout bits, because they are needed by the following coalesce pass.
1801 IndexSet liveout(_live->live(b));
1802
1803 for( uint j = b->end_idx() + 1; j > 1; j-- ) {
1804 Node *n = b->_nodes[j-1];
1805
1806 // Pre-split compares of loop-phis. Loop-phis form a cycle we would
1807 // like to see in the same register. Compare uses the loop-phi and so
1808 // extends its live range BUT cannot be part of the cycle. If this
1809 // extended live range overlaps with the update of the loop-phi value
1810 // we need both alive at the same time -- which requires at least 1
1811 // copy. But because Intel has only 2-address registers we end up with
1812 // at least 2 copies, one before the loop-phi update instruction and
1813 // one after. Instead we split the input to the compare just after the
1814 // phi.
1815 if( n->is_Mach() && n->as_Mach()->ideal_Opcode() == Op_CmpI ) {
1816 Node *phi = n->in(1);
1817 if( phi->is_Phi() && phi->as_Phi()->region()->is_Loop() ) {
1818 Block *phi_block = _cfg._bbs[phi->_idx];
1819 if( _cfg._bbs[phi_block->pred(2)->_idx] == b ) {
1820 const RegMask *mask = C->matcher()->idealreg2spillmask[Op_RegI];
1821 Node *spill = new (C) MachSpillCopyNode( phi, *mask, *mask );
1822 insert_proj( phi_block, 1, spill, maxlrg++ );
1823 n->set_req(1,spill);
1824 must_recompute_live = true;
1825 }
1826 }
1827 }
1828
1829 // Get value being defined
1830 uint lidx = _lrg_map.live_range_id(n);
1831 // Ignore the occasional brand-new live range
1832 if (lidx && lidx < _lrg_map.max_lrg_id()) {
1833 // Remove from live-out set
1834 liveout.remove(lidx);
1835
1836 // Copies do not define a new value and so do not interfere.
1837 // Remove the copies source from the liveout set before interfering.
1838 uint idx = n->is_Copy();
1839 if (idx) {
1853 Node *derived = lrgs(neighbor)._def;
1854 const TypePtr *tj = derived->bottom_type()->isa_ptr();
1855 assert(!derived->bottom_type()->isa_narrowoop() ||
1856 derived->bottom_type()->make_ptr()->is_ptr()->_offset == 0, "sanity");
1857 // If its an OOP with a non-zero offset, then it is derived.
1858 if( tj && tj->_offset != 0 && tj->isa_oop_ptr() ) {
1859 Node *base = find_base_for_derived(derived_base_map, derived, maxlrg);
1860 assert(base->_idx < _lrg_map.size(), "");
1861 // Add reaching DEFs of derived pointer and base pointer as a
1862 // pair of inputs
1863 n->add_req(derived);
1864 n->add_req(base);
1865
1866 // See if the base pointer is already live to this point.
1867 // Since I'm working on the SSA form, live-ness amounts to
1868 // reaching def's. So if I find the base's live range then
1869 // I know the base's def reaches here.
1870 if ((_lrg_map.live_range_id(base) >= _lrg_map.max_lrg_id() || // (Brand new base (hence not live) or
1871 !liveout.member(_lrg_map.live_range_id(base))) && // not live) AND
1872 (_lrg_map.live_range_id(base) > 0) && // not a constant
1873 _cfg._bbs[base->_idx] != b) { // base not def'd in blk)
1874 // Base pointer is not currently live. Since I stretched
1875 // the base pointer to here and it crosses basic-block
1876 // boundaries, the global live info is now incorrect.
1877 // Recompute live.
1878 must_recompute_live = true;
1879 } // End of if base pointer is not live to debug info
1880 }
1881 } // End of scan all live data for derived ptrs crossing GC point
1882 } // End of if found a GC point
1883
1884 // Make all inputs live
1885 if (!n->is_Phi()) { // Phi function uses come from prior block
1886 for (uint k = 1; k < n->req(); k++) {
1887 uint lidx = _lrg_map.live_range_id(n->in(k));
1888 if (lidx < _lrg_map.max_lrg_id()) {
1889 liveout.insert(lidx);
1890 }
1891 }
1892 }
1893
1976 if( k < n->len() && n->in(k) ) tty->print("| ");
1977 for( ; k < n->len(); k++ ) {
1978 Node *m = n->in(k);
1979 if(!m) {
1980 break;
1981 }
1982 uint r = (m->_idx < _lrg_map.size()) ? _lrg_map.find_const(m) : 0;
1983 tty->print("L%d",r);
1984 tty->print("/N%d ",m->_idx);
1985 }
1986 if( n->is_Mach() ) n->as_Mach()->dump_spec(tty);
1987 else n->dump_spec(tty);
1988 if( _spilled_once.test(n->_idx ) ) {
1989 tty->print(" Spill_1");
1990 if( _spilled_twice.test(n->_idx ) )
1991 tty->print(" Spill_2");
1992 }
1993 tty->print("\n");
1994 }
1995
1996 void PhaseChaitin::dump( const Block * b ) const {
1997 b->dump_head( &_cfg._bbs );
1998
1999 // For all instructions
2000 for( uint j = 0; j < b->_nodes.size(); j++ )
2001 dump(b->_nodes[j]);
2002 // Print live-out info at end of block
2003 if( _live ) {
2004 tty->print("Liveout: ");
2005 IndexSet *live = _live->live(b);
2006 IndexSetIterator elements(live);
2007 tty->print("{");
2008 uint i;
2009 while ((i = elements.next()) != 0) {
2010 tty->print("L%d ", _lrg_map.find_const(i));
2011 }
2012 tty->print_cr("}");
2013 }
2014 tty->print("\n");
2015 }
2016
2017 void PhaseChaitin::dump() const {
2282 } else {
2283 tty->print_cr("new LRG");
2284 }
2285 }
2286 if( _ifg && lidx < _ifg->_maxlrg) {
2287 tty->print("Neighbors: %d - ", _ifg->neighbor_cnt(lidx));
2288 _ifg->neighbors(lidx)->dump();
2289 tty->cr();
2290 }
2291 // For all blocks
2292 for( uint i = 0; i < _cfg._num_blocks; i++ ) {
2293 Block *b = _cfg._blocks[i];
2294 int dump_once = 0;
2295
2296 // For all instructions
2297 for( uint j = 0; j < b->_nodes.size(); j++ ) {
2298 Node *n = b->_nodes[j];
2299 if (_lrg_map.find_const(n) == lidx) {
2300 if (!dump_once++) {
2301 tty->cr();
2302 b->dump_head( &_cfg._bbs );
2303 }
2304 dump(n);
2305 continue;
2306 }
2307 if (!defs_only) {
2308 uint cnt = n->req();
2309 for( uint k = 1; k < cnt; k++ ) {
2310 Node *m = n->in(k);
2311 if (!m) {
2312 continue; // be robust in the dumper
2313 }
2314 if (_lrg_map.find_const(m) == lidx) {
2315 if (!dump_once++) {
2316 tty->cr();
2317 b->dump_head(&_cfg._bbs);
2318 }
2319 dump(n);
2320 }
2321 }
2322 }
2323 }
2324 } // End of per-block dump
2325 tty->cr();
2326 }
2327 #endif // not PRODUCT
2328
2329 //------------------------------print_chaitin_statistics-------------------------------
2330 int PhaseChaitin::_final_loads = 0;
2331 int PhaseChaitin::_final_stores = 0;
2332 int PhaseChaitin::_final_memoves= 0;
2333 int PhaseChaitin::_final_copies = 0;
2334 double PhaseChaitin::_final_load_cost = 0;
2335 double PhaseChaitin::_final_store_cost = 0;
2336 double PhaseChaitin::_final_memove_cost= 0;
2337 double PhaseChaitin::_final_copy_cost = 0;
|
278 uint src = _lrg_map.find(src_n);
279 uint dst = _lrg_map.find(dst_n);
280 assert(src, "");
281 assert(dst, "");
282 assert(src < _lrg_map.max_lrg_id(), "oob");
283 assert(dst < _lrg_map.max_lrg_id(), "oob");
284 assert(src < dst, "always union smaller");
285 _lrg_map.uf_map(dst, src);
286 }
287
288 //------------------------------new_lrg----------------------------------------
289 void PhaseChaitin::new_lrg(const Node *x, uint lrg) {
290 // Make the Node->LRG mapping
291 _lrg_map.extend(x->_idx,lrg);
292 // Make the Union-Find mapping an identity function
293 _lrg_map.uf_extend(lrg, lrg);
294 }
295
296
297 bool PhaseChaitin::clone_projs_shared(Block *b, uint idx, Node *con, Node *copy, uint max_lrg_id) {
298 Block* bcon = _cfg.get_block_for_node(con);
299 uint cindex = bcon->find_node(con);
300 Node *con_next = bcon->_nodes[cindex+1];
301 if (con_next->in(0) != con || !con_next->is_MachProj()) {
302 return false; // No MachProj's follow
303 }
304
305 // Copy kills after the cloned constant
306 Node *kills = con_next->clone();
307 kills->set_req(0, copy);
308 b->_nodes.insert(idx, kills);
309 _cfg.map_node_to_block(kills, b);
310 new_lrg(kills, max_lrg_id);
311 return true;
312 }
313
314 //------------------------------compact----------------------------------------
315 // Renumber the live ranges to compact them. Makes the IFG smaller.
316 void PhaseChaitin::compact() {
317 // Current the _uf_map contains a series of short chains which are headed
318 // by a self-cycle. All the chains run from big numbers to little numbers.
319 // The Find() call chases the chains & shortens them for the next Find call.
320 // We are going to change this structure slightly. Numbers above a moving
321 // wave 'i' are unchanged. Numbers below 'j' point directly to their
322 // compacted live range with no further chaining. There are no chains or
323 // cycles below 'i', so the Find call no longer works.
324 uint j=1;
325 uint i;
326 for (i = 1; i < _lrg_map.max_lrg_id(); i++) {
327 uint lr = _lrg_map.uf_live_range_id(i);
328 // Ignore unallocated live ranges
329 if (!lr) {
945 #endif
946 n->as_Mach()->use_cisc_RegMask();
947 }
948
949 LRG &lrg = lrgs(vreg);
950 // // Testing for floating point code shape
951 // Node *test = n->in(k);
952 // if( test->is_Mach() ) {
953 // MachNode *m = test->as_Mach();
954 // int op = m->ideal_Opcode();
955 // if (n->is_Call() && (op == Op_AddF || op == Op_MulF) ) {
956 // int zzz = 1;
957 // }
958 // }
959
960 // Limit result register mask to acceptable registers.
961 // Do not limit registers from uncommon uses before
962 // AggressiveCoalesce. This effectively pre-virtual-splits
963 // around uncommon uses of common defs.
964 const RegMask &rm = n->in_RegMask(k);
965 if (!after_aggressive && _cfg.get_block_for_node(n->in(k))->_freq > 1000 * b->_freq) {
966 // Since we are BEFORE aggressive coalesce, leave the register
967 // mask untrimmed by the call. This encourages more coalescing.
968 // Later, AFTER aggressive, this live range will have to spill
969 // but the spiller handles slow-path calls very nicely.
970 } else {
971 lrg.AND( rm );
972 }
973
974 // Check for bound register masks
975 const RegMask &lrgmask = lrg.mask();
976 int kreg = n->in(k)->ideal_reg();
977 bool is_vect = RegMask::is_vector(kreg);
978 assert(n->in(k)->bottom_type()->isa_vect() == NULL ||
979 is_vect || kreg == Op_RegD,
980 "vector must be in vector registers");
981 if (lrgmask.is_bound(kreg))
982 lrg._is_bound = 1;
983
984 // If this use of a double forces a mis-aligned double,
985 // flag as '_fat_proj' - really flag as allowing misalignment
1691 // pointers derived from NULL! These are always along paths that
1692 // can't happen at run-time but the optimizer cannot deduce it so
1693 // we have to handle it gracefully.
1694 assert(!derived->bottom_type()->isa_narrowoop() ||
1695 derived->bottom_type()->make_ptr()->is_ptr()->_offset == 0, "sanity");
1696 const TypePtr *tj = derived->bottom_type()->isa_ptr();
1697 // If its an OOP with a non-zero offset, then it is derived.
1698 if( tj == NULL || tj->_offset == 0 ) {
1699 derived_base_map[derived->_idx] = derived;
1700 return derived;
1701 }
1702 // Derived is NULL+offset? Base is NULL!
1703 if( derived->is_Con() ) {
1704 Node *base = _matcher.mach_null();
1705 assert(base != NULL, "sanity");
1706 if (base->in(0) == NULL) {
1707 // Initialize it once and make it shared:
1708 // set control to _root and place it into Start block
1709 // (where top() node is placed).
1710 base->init_req(0, _cfg._root);
1711 Block *startb = _cfg.get_block_for_node(C->top());
1712 startb->_nodes.insert(startb->find_node(C->top()), base );
1713 _cfg.map_node_to_block(base, startb);
1714 assert(_lrg_map.live_range_id(base) == 0, "should not have LRG yet");
1715 }
1716 if (_lrg_map.live_range_id(base) == 0) {
1717 new_lrg(base, maxlrg++);
1718 }
1719 assert(base->in(0) == _cfg._root && _cfg.get_block_for_node(base) == _cfg.get_block_for_node(C->top()), "base NULL should be shared");
1720 derived_base_map[derived->_idx] = base;
1721 return base;
1722 }
1723
1724 // Check for AddP-related opcodes
1725 if (!derived->is_Phi()) {
1726 assert(derived->as_Mach()->ideal_Opcode() == Op_AddP, err_msg_res("but is: %s", derived->Name()));
1727 Node *base = derived->in(AddPNode::Base);
1728 derived_base_map[derived->_idx] = base;
1729 return base;
1730 }
1731
1732 // Recursively find bases for Phis.
1733 // First check to see if we can avoid a base Phi here.
1734 Node *base = find_base_for_derived( derived_base_map, derived->in(1),maxlrg);
1735 uint i;
1736 for( i = 2; i < derived->req(); i++ )
1737 if( base != find_base_for_derived( derived_base_map,derived->in(i),maxlrg))
1738 break;
1739 // Went to the end without finding any different bases?
1740 if( i == derived->req() ) { // No need for a base Phi here
1741 derived_base_map[derived->_idx] = base;
1742 return base;
1743 }
1744
1745 // Now we see we need a base-Phi here to merge the bases
1746 const Type *t = base->bottom_type();
1747 base = new (C) PhiNode( derived->in(0), t );
1748 for( i = 1; i < derived->req(); i++ ) {
1749 base->init_req(i, find_base_for_derived(derived_base_map, derived->in(i), maxlrg));
1750 t = t->meet(base->in(i)->bottom_type());
1751 }
1752 base->as_Phi()->set_type(t);
1753
1754 // Search the current block for an existing base-Phi
1755 Block *b = _cfg.get_block_for_node(derived);
1756 for( i = 1; i <= b->end_idx(); i++ ) {// Search for matching Phi
1757 Node *phi = b->_nodes[i];
1758 if( !phi->is_Phi() ) { // Found end of Phis with no match?
1759 b->_nodes.insert( i, base ); // Must insert created Phi here as base
1760 _cfg.map_node_to_block(base, b);
1761 new_lrg(base,maxlrg++);
1762 break;
1763 }
1764 // See if Phi matches.
1765 uint j;
1766 for( j = 1; j < base->req(); j++ )
1767 if( phi->in(j) != base->in(j) &&
1768 !(phi->in(j)->is_Con() && base->in(j)->is_Con()) ) // allow different NULLs
1769 break;
1770 if( j == base->req() ) { // All inputs match?
1771 base = phi; // Then use existing 'phi' and drop 'base'
1772 break;
1773 }
1774 }
1775
1776
1777 // Cache info for later passes
1778 derived_base_map[derived->_idx] = base;
1779 return base;
1780 }
1796 Block *b = _cfg._blocks[i];
1797 // Note use of deep-copy constructor. I cannot hammer the original
1798 // liveout bits, because they are needed by the following coalesce pass.
1799 IndexSet liveout(_live->live(b));
1800
1801 for( uint j = b->end_idx() + 1; j > 1; j-- ) {
1802 Node *n = b->_nodes[j-1];
1803
1804 // Pre-split compares of loop-phis. Loop-phis form a cycle we would
1805 // like to see in the same register. Compare uses the loop-phi and so
1806 // extends its live range BUT cannot be part of the cycle. If this
1807 // extended live range overlaps with the update of the loop-phi value
1808 // we need both alive at the same time -- which requires at least 1
1809 // copy. But because Intel has only 2-address registers we end up with
1810 // at least 2 copies, one before the loop-phi update instruction and
1811 // one after. Instead we split the input to the compare just after the
1812 // phi.
1813 if( n->is_Mach() && n->as_Mach()->ideal_Opcode() == Op_CmpI ) {
1814 Node *phi = n->in(1);
1815 if( phi->is_Phi() && phi->as_Phi()->region()->is_Loop() ) {
1816 Block *phi_block = _cfg.get_block_for_node(phi);
1817 if (_cfg.get_block_for_node(phi_block->pred(2)) == b) {
1818 const RegMask *mask = C->matcher()->idealreg2spillmask[Op_RegI];
1819 Node *spill = new (C) MachSpillCopyNode( phi, *mask, *mask );
1820 insert_proj( phi_block, 1, spill, maxlrg++ );
1821 n->set_req(1,spill);
1822 must_recompute_live = true;
1823 }
1824 }
1825 }
1826
1827 // Get value being defined
1828 uint lidx = _lrg_map.live_range_id(n);
1829 // Ignore the occasional brand-new live range
1830 if (lidx && lidx < _lrg_map.max_lrg_id()) {
1831 // Remove from live-out set
1832 liveout.remove(lidx);
1833
1834 // Copies do not define a new value and so do not interfere.
1835 // Remove the copies source from the liveout set before interfering.
1836 uint idx = n->is_Copy();
1837 if (idx) {
1851 Node *derived = lrgs(neighbor)._def;
1852 const TypePtr *tj = derived->bottom_type()->isa_ptr();
1853 assert(!derived->bottom_type()->isa_narrowoop() ||
1854 derived->bottom_type()->make_ptr()->is_ptr()->_offset == 0, "sanity");
1855 // If its an OOP with a non-zero offset, then it is derived.
1856 if( tj && tj->_offset != 0 && tj->isa_oop_ptr() ) {
1857 Node *base = find_base_for_derived(derived_base_map, derived, maxlrg);
1858 assert(base->_idx < _lrg_map.size(), "");
1859 // Add reaching DEFs of derived pointer and base pointer as a
1860 // pair of inputs
1861 n->add_req(derived);
1862 n->add_req(base);
1863
1864 // See if the base pointer is already live to this point.
1865 // Since I'm working on the SSA form, live-ness amounts to
1866 // reaching def's. So if I find the base's live range then
1867 // I know the base's def reaches here.
1868 if ((_lrg_map.live_range_id(base) >= _lrg_map.max_lrg_id() || // (Brand new base (hence not live) or
1869 !liveout.member(_lrg_map.live_range_id(base))) && // not live) AND
1870 (_lrg_map.live_range_id(base) > 0) && // not a constant
1871 _cfg.get_block_for_node(base) != b) { // base not def'd in blk)
1872 // Base pointer is not currently live. Since I stretched
1873 // the base pointer to here and it crosses basic-block
1874 // boundaries, the global live info is now incorrect.
1875 // Recompute live.
1876 must_recompute_live = true;
1877 } // End of if base pointer is not live to debug info
1878 }
1879 } // End of scan all live data for derived ptrs crossing GC point
1880 } // End of if found a GC point
1881
1882 // Make all inputs live
1883 if (!n->is_Phi()) { // Phi function uses come from prior block
1884 for (uint k = 1; k < n->req(); k++) {
1885 uint lidx = _lrg_map.live_range_id(n->in(k));
1886 if (lidx < _lrg_map.max_lrg_id()) {
1887 liveout.insert(lidx);
1888 }
1889 }
1890 }
1891
1974 if( k < n->len() && n->in(k) ) tty->print("| ");
1975 for( ; k < n->len(); k++ ) {
1976 Node *m = n->in(k);
1977 if(!m) {
1978 break;
1979 }
1980 uint r = (m->_idx < _lrg_map.size()) ? _lrg_map.find_const(m) : 0;
1981 tty->print("L%d",r);
1982 tty->print("/N%d ",m->_idx);
1983 }
1984 if( n->is_Mach() ) n->as_Mach()->dump_spec(tty);
1985 else n->dump_spec(tty);
1986 if( _spilled_once.test(n->_idx ) ) {
1987 tty->print(" Spill_1");
1988 if( _spilled_twice.test(n->_idx ) )
1989 tty->print(" Spill_2");
1990 }
1991 tty->print("\n");
1992 }
1993
1994 void PhaseChaitin::dump(const Block *b) const {
1995 b->dump_head(&_cfg);
1996
1997 // For all instructions
1998 for( uint j = 0; j < b->_nodes.size(); j++ )
1999 dump(b->_nodes[j]);
2000 // Print live-out info at end of block
2001 if( _live ) {
2002 tty->print("Liveout: ");
2003 IndexSet *live = _live->live(b);
2004 IndexSetIterator elements(live);
2005 tty->print("{");
2006 uint i;
2007 while ((i = elements.next()) != 0) {
2008 tty->print("L%d ", _lrg_map.find_const(i));
2009 }
2010 tty->print_cr("}");
2011 }
2012 tty->print("\n");
2013 }
2014
2015 void PhaseChaitin::dump() const {
2280 } else {
2281 tty->print_cr("new LRG");
2282 }
2283 }
2284 if( _ifg && lidx < _ifg->_maxlrg) {
2285 tty->print("Neighbors: %d - ", _ifg->neighbor_cnt(lidx));
2286 _ifg->neighbors(lidx)->dump();
2287 tty->cr();
2288 }
2289 // For all blocks
2290 for( uint i = 0; i < _cfg._num_blocks; i++ ) {
2291 Block *b = _cfg._blocks[i];
2292 int dump_once = 0;
2293
2294 // For all instructions
2295 for( uint j = 0; j < b->_nodes.size(); j++ ) {
2296 Node *n = b->_nodes[j];
2297 if (_lrg_map.find_const(n) == lidx) {
2298 if (!dump_once++) {
2299 tty->cr();
2300 b->dump_head(&_cfg);
2301 }
2302 dump(n);
2303 continue;
2304 }
2305 if (!defs_only) {
2306 uint cnt = n->req();
2307 for( uint k = 1; k < cnt; k++ ) {
2308 Node *m = n->in(k);
2309 if (!m) {
2310 continue; // be robust in the dumper
2311 }
2312 if (_lrg_map.find_const(m) == lidx) {
2313 if (!dump_once++) {
2314 tty->cr();
2315 b->dump_head(&_cfg);
2316 }
2317 dump(n);
2318 }
2319 }
2320 }
2321 }
2322 } // End of per-block dump
2323 tty->cr();
2324 }
2325 #endif // not PRODUCT
2326
2327 //------------------------------print_chaitin_statistics-------------------------------
2328 int PhaseChaitin::_final_loads = 0;
2329 int PhaseChaitin::_final_stores = 0;
2330 int PhaseChaitin::_final_memoves= 0;
2331 int PhaseChaitin::_final_copies = 0;
2332 double PhaseChaitin::_final_load_cost = 0;
2333 double PhaseChaitin::_final_store_cost = 0;
2334 double PhaseChaitin::_final_memove_cost= 0;
2335 double PhaseChaitin::_final_copy_cost = 0;
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