--- old/src/share/vm/opto/coalesce.cpp 2014-01-28 10:58:56.114406099 +0100 +++ new/src/share/vm/opto/coalesce.cpp 2014-01-28 10:58:56.014406094 +0100 @@ -291,7 +291,7 @@ _phc.clone_projs(pred, pred->end_idx(), m, copy, _phc._lrg_map); } else { const RegMask *rm = C->matcher()->idealreg2spillmask[m->ideal_reg()]; - copy = new (C) MachSpillCopyNode(m, *rm, *rm); + copy = new (C) PhiInputSpillNode(m, *rm, *rm); // Find a good place to insert. Kinda tricky, use a subroutine insert_copy_with_overlap(pred,copy,phi_name,src_name); } @@ -325,7 +325,7 @@ l += _phc.clone_projs(b, l, m, copy, _phc._lrg_map); } else { const RegMask *rm = C->matcher()->idealreg2spillmask[m->ideal_reg()]; - copy = new (C) MachSpillCopyNode(m, *rm, *rm); + copy = new (C) TwoAddressSpillNode(m, *rm, *rm); // Insert the copy in the basic block, just before us b->insert_node(copy, l++); } @@ -372,7 +372,7 @@ continue; // Live out; do not pre-split // Split the lrg at this use const RegMask *rm = C->matcher()->idealreg2spillmask[inp->ideal_reg()]; - Node *copy = new (C) MachSpillCopyNode( inp, *rm, *rm ); + Node* copy = new (C) DebugUseSpillNode(inp, *rm, *rm); // Insert the copy in the use-def chain n->set_req(inpidx, copy ); // Insert the copy in the basic block, just before us --- old/src/share/vm/opto/chaitin.cpp 2014-01-28 10:58:56.118406099 +0100 +++ new/src/share/vm/opto/chaitin.cpp 2014-01-28 10:58:56.014406094 +0100 @@ -1799,7 +1799,7 @@ Block *phi_block = _cfg.get_block_for_node(phi); if (_cfg.get_block_for_node(phi_block->pred(2)) == block) { const RegMask *mask = C->matcher()->idealreg2spillmask[Op_RegI]; - Node *spill = new (C) MachSpillCopyNode( phi, *mask, *mask ); + Node *spill = new (C) LoopPhiInputSpillNode(phi, *mask, *mask); insert_proj( phi_block, 1, spill, maxlrg++ ); n->set_req(1,spill); must_recompute_live = true; --- old/src/share/vm/opto/machnode.hpp 2014-01-28 10:58:56.122406099 +0100 +++ new/src/share/vm/opto/machnode.hpp 2014-01-28 10:58:56.018406094 +0100 @@ -511,6 +511,126 @@ #endif }; +// Inserted when coalescing of a two-address-instruction node and its input fails +class TwoAddressSpillNode : public MachSpillCopyNode { +public: + TwoAddressSpillNode(Node *n, const RegMask &in, const RegMask &out) : MachSpillCopyNode(n, in, out) {} +#ifndef PRODUCT + virtual const char* Name() const { return "TwoAddressSpill"; } +#endif +}; + +// Inserted when coalescing of a phi node and its input fails +class PhiInputSpillNode : public MachSpillCopyNode { +public: + PhiInputSpillNode(Node *n, const RegMask &in, const RegMask &out) : MachSpillCopyNode(n, in, out) {} +#ifndef PRODUCT + virtual const char* Name() const { return "PhiInputSpill"; } +#endif +}; + +// Inserted as debug info spills to safepoints in non-frequent blocks +class DebugUseSpillNode : public MachSpillCopyNode { +public: + DebugUseSpillNode(Node *n, const RegMask &in, const RegMask &out) : MachSpillCopyNode(n, in, out) {} +#ifndef PRODUCT + virtual const char* Name() const { return "DebugUseSpill"; } +#endif +}; + +// Pre-split compares of loop-phis +class LoopPhiInputSpillNode : public MachSpillCopyNode { +public: + LoopPhiInputSpillNode(Node *n, const RegMask &in, const RegMask &out) : MachSpillCopyNode(n, in, out) {} +#ifndef PRODUCT + virtual const char* Name() const { return "LoopPhiInputSpill"; } +#endif +}; + +// An lrg marked as spilled will be spilled to memory right +// after its definition, if in high pressure region or the lrg is bound +class DefinitionSpillNode : public MachSpillCopyNode { +public: + DefinitionSpillNode(Node *n, const RegMask &in, const RegMask &out) : MachSpillCopyNode(n, in, out) {} +#ifndef PRODUCT + virtual const char* Name() const { return "DefinitionSpill"; } +#endif +}; + +// A register to register move +class RegToRegSpillNode : public MachSpillCopyNode { +public: + RegToRegSpillNode(Node *n, const RegMask &in, const RegMask &out) : MachSpillCopyNode(n, in, out) {} +#ifndef PRODUCT + virtual const char* Name() const { return "RegToRegSpill"; } +#endif +}; + +// A register to memory move +class RegToMemSpillNode : public MachSpillCopyNode { +public: + RegToMemSpillNode(Node *n, const RegMask &in, const RegMask &out) : MachSpillCopyNode(n, in, out) {} +#ifndef PRODUCT + virtual const char* Name() const { return "RegToMemSpill"; } +#endif +}; + +// A memory to register move +class MemToRegSpillNode : public MachSpillCopyNode { +public: + MemToRegSpillNode(Node *n, const RegMask &in, const RegMask &out) : MachSpillCopyNode(n, in, out) {} +#ifndef PRODUCT + virtual const char* Name() const { return "MemToRegSpill"; } +#endif +}; + +// When coalescing phi nodes in PhaseChaitin::Split(), a move spill is inserted if the phi and its input +// resides at different locations (i.e. reg or mem) +class PhiLocationDifferToInputLocationSpillNode : public MachSpillCopyNode { +public: + PhiLocationDifferToInputLocationSpillNode(Node *n, const RegMask &in, const RegMask &out) : MachSpillCopyNode(n, in, out) {} +#ifndef PRODUCT + virtual const char* Name() const { return "PhiLocationDifferToInputLocationSpill"; } +#endif +}; + +// Spill base pointer to memory at safepoint +class BasePointerToMemSpillNode : public MachSpillCopyNode { +public: + BasePointerToMemSpillNode(Node *n, const RegMask &in, const RegMask &out) : MachSpillCopyNode(n, in, out) {} +#ifndef PRODUCT + virtual const char* Name() const { return "BasePointerToMemSpill"; } +#endif +}; + +// When rematerializing a node we stretch the inputs liveranges, and they might be stretched beyond a new +// definition point, therefore we split out new copies instead +class InputToRematerializationSpillNode : public MachSpillCopyNode { +public: + InputToRematerializationSpillNode(Node *n, const RegMask &in, const RegMask &out) : MachSpillCopyNode(n, in, out) {} +#ifndef PRODUCT + virtual const char* Name() const { return "InputToRematerializationSpill"; } +#endif +}; + +// Spill use at a call +class CallUseSpillNode : public MachSpillCopyNode { +public: + CallUseSpillNode(Node *n, const RegMask &in, const RegMask &out) : MachSpillCopyNode(n, in, out) {} +#ifndef PRODUCT + virtual const char* Name() const { return "CallUseSpill"; } +#endif +}; + +// An lrg marked as spill that is bound and needs to be spilled at a use +class BoundSpillNode : public MachSpillCopyNode { +public: + BoundSpillNode(Node *n, const RegMask &in, const RegMask &out) : MachSpillCopyNode(n, in, out) {} +#ifndef PRODUCT + virtual const char* Name() const { return "BoundSpill"; } +#endif +}; + //------------------------------MachBranchNode-------------------------------- // Abstract machine branch Node class MachBranchNode : public MachIdealNode { --- old/src/share/vm/opto/chaitin.hpp 2014-01-28 10:58:56.126406099 +0100 +++ new/src/share/vm/opto/chaitin.hpp 2014-01-28 10:58:56.022406095 +0100 @@ -425,6 +425,7 @@ // Helper functions for Split() uint split_DEF( Node *def, Block *b, int loc, uint max, Node **Reachblock, Node **debug_defs, GrowableArray splits, int slidx ); + template uint split_USE( Node *def, Block *b, Node *use, uint useidx, uint max, bool def_down, bool cisc_sp, GrowableArray splits, int slidx ); //------------------------------clone_projs------------------------------------ @@ -447,6 +448,7 @@ int slidx, uint *lrg2reach, Node **Reachblock, bool walkThru); // True if lidx is used before any real register is def'd in the block bool prompt_use( Block *b, uint lidx ); + template Node *get_spillcopy_wide( Node *def, Node *use, uint uidx ); // Insert the spill at chosen location. Skip over any intervening Proj's or // Phis. Skip over a CatchNode and projs, inserting in the fall-through block --- old/src/share/vm/opto/reg_split.cpp 2014-01-28 10:58:56.142406100 +0100 +++ new/src/share/vm/opto/reg_split.cpp 2014-01-28 10:58:56.030406095 +0100 @@ -55,6 +55,7 @@ // Get a SpillCopy node with wide-enough masks. Use the 'wide-mask', the // wide ideal-register spill-mask if possible. If the 'wide-mask' does // not cover the input (or output), use the input (or output) mask instead. +template Node *PhaseChaitin::get_spillcopy_wide( Node *def, Node *use, uint uidx ) { // If ideal reg doesn't exist we've got a bad schedule happening // that is forcing us to spill something that isn't spillable. @@ -93,7 +94,7 @@ // Here we assume a trip through memory is required. w_i_mask = &C->FIRST_STACK_mask(); } - return new (C) MachSpillCopyNode( def, *w_i_mask, *w_o_mask ); + return new (C) T( def, *w_i_mask, *w_o_mask ); } //------------------------------insert_proj------------------------------------ @@ -159,7 +160,7 @@ assert( loc >= 0, "must insert past block head" ); // Get a def-side SpillCopy - Node *spill = get_spillcopy_wide(def,NULL,0); + Node *spill = get_spillcopy_wide(def, NULL, 0); // Did we fail to split?, then bail if (!spill) { return 0; @@ -180,6 +181,7 @@ //------------------------------split_USE-------------------------------------- // Splits at uses can involve redeffing the LRG, so no CISC Spilling there. // Debug uses want to know if def is already stack enabled. +template uint PhaseChaitin::split_USE( Node *def, Block *b, Node *use, uint useidx, uint maxlrg, bool def_down, bool cisc_sp, GrowableArray splits, int slidx ) { #ifdef ASSERT // Increment the counter for this lrg @@ -216,7 +218,7 @@ // DEF is UP, so must copy it DOWN and hook in USE // Insert SpillCopy before the USE, which uses DEF as its input, // and defs a new live range, which is used by this node. - Node *spill = get_spillcopy_wide(def,use,useidx); + Node *spill = get_spillcopy_wide(def,use,useidx); // did we fail to split? if (!spill) { // Bail @@ -268,7 +270,7 @@ bindex = b->find_node(use); } - Node *spill = get_spillcopy_wide( def, use, useidx ); + Node *spill = get_spillcopy_wide(def, use, useidx ); if( !spill ) return 0; // Bailed out // Insert SpillCopy before the USE, which uses the reaching DEF as // its input, and defs a new live range, which is used by this node. @@ -327,7 +329,7 @@ Block *b_def = _cfg.get_block_for_node(def); int idx_def = b_def->find_node(def); - Node *in_spill = get_spillcopy_wide( in, def, i ); + Node *in_spill = get_spillcopy_wide( in, def, i ); if( !in_spill ) return 0; // Bailed out insert_proj(b_def,idx_def,in_spill,maxlrg++); if( b_def == b ) @@ -935,7 +937,7 @@ // This def has been rematerialized a couple of times without // progress. It doesn't care if it lives UP or DOWN, so // spill it down now. - maxlrg = split_USE(def,b,n,inpidx,maxlrg,false,false,splits,slidx); + maxlrg = split_USE(def,b,n,inpidx,maxlrg,false,false,splits,slidx); // If it wasn't split bail if (!maxlrg) { return 0; @@ -1015,7 +1017,7 @@ !is_vect && umask.is_misaligned_pair())) { // These need a Split regardless of overlap or pressure // SPLIT - NO DEF - NO CISC SPILL - maxlrg = split_USE(def,b,n,inpidx,maxlrg,dup,false, splits,slidx); + maxlrg = split_USE(def,b,n,inpidx,maxlrg,dup,false, splits,slidx); // If it wasn't split bail if (!maxlrg) { return 0; @@ -1027,7 +1029,7 @@ if (UseFPUForSpilling && n->is_MachCall() && !uup && !dup ) { // The use at the call can force the def down so insert // a split before the use to allow the def more freedom. - maxlrg = split_USE(def,b,n,inpidx,maxlrg,dup,false, splits,slidx); + maxlrg = split_USE(def,b,n,inpidx,maxlrg,dup,false, splits,slidx); // If it wasn't split bail if (!maxlrg) { return 0; @@ -1063,7 +1065,7 @@ else { // Both are either up or down, and there is no overlap if( dup ) { // If UP, reg->reg copy // COPY ACROSS HERE - NO DEF - NO CISC SPILL - maxlrg = split_USE(def,b,n,inpidx,maxlrg,false,false, splits,slidx); + maxlrg = split_USE(def,b,n,inpidx,maxlrg,false,false, splits,slidx); // If it wasn't split bail if (!maxlrg) { return 0; @@ -1075,10 +1077,10 @@ // First Split-UP to move value into Register uint def_ideal = def->ideal_reg(); const RegMask* tmp_rm = Matcher::idealreg2regmask[def_ideal]; - Node *spill = new (C) MachSpillCopyNode(def, dmask, *tmp_rm); + Node *spill = new (C) MemToRegSpillNode(def, dmask, *tmp_rm); insert_proj( b, insidx, spill, maxlrg ); // Then Split-DOWN as if previous Split was DEF - maxlrg = split_USE(spill,b,n,inpidx,maxlrg,false,false, splits,slidx); + maxlrg = split_USE(spill,b,n,inpidx,maxlrg,false,false, splits,slidx); // If it wasn't split bail if (!maxlrg) { return 0; @@ -1103,7 +1105,7 @@ } } // COPY DOWN HERE - NO DEF - NO CISC SPILL - maxlrg = split_USE(def,b,n,inpidx,maxlrg,false,false, splits,slidx); + maxlrg = split_USE(def,b,n,inpidx,maxlrg,false,false, splits,slidx); // If it wasn't split bail if (!maxlrg) { return 0; @@ -1118,7 +1120,7 @@ else { // DOWN, Split-UP and check register pressure if( is_high_pressure( b, &lrgs(useidx), insidx ) ) { // COPY UP HERE - NO DEF - CISC SPILL - maxlrg = split_USE(def,b,n,inpidx,maxlrg,true,true, splits,slidx); + maxlrg = split_USE(def,b,n,inpidx,maxlrg,true,true, splits,slidx); // If it wasn't split bail if (!maxlrg) { return 0; @@ -1126,7 +1128,7 @@ insidx++; // Reset iterator to skip USE side split } else { // LRP // COPY UP HERE - WITH DEF - NO CISC SPILL - maxlrg = split_USE(def,b,n,inpidx,maxlrg,true,false, splits,slidx); + maxlrg = split_USE(def,b,n,inpidx,maxlrg,true,false, splits,slidx); // If it wasn't split bail if (!maxlrg) { return 0; @@ -1229,7 +1231,7 @@ if (C->check_node_count(NodeLimitFudgeFactor, out_of_nodes)) { // Check when generating nodes return 0; } - Node *spill = new (C) MachSpillCopyNode(use,use_rm,def_rm); + Node *spill = new (C) MemToRegSpillNode(use,use_rm,def_rm); n->set_req(copyidx,spill); n->as_MachSpillCopy()->set_in_RegMask(def_rm); // Put the spill just before the copy @@ -1336,7 +1338,7 @@ // Grab the UP/DOWN sense for the input u1 = UP[pidx][slidx]; if( u1 != (phi_up != 0)) { - maxlrg = split_USE(def, b, phi, i, maxlrg, !u1, false, splits,slidx); + maxlrg = split_USE(def, b, phi, i, maxlrg, !u1, false, splits,slidx); // If it wasn't split bail if (!maxlrg) { return 0;