274 continue;
275 }
276 // Check for mismatch inputs to Phi
277 for (uint j = 1; j < cnt; j++) {
278 Node *m = n->in(j);
279 uint src_name = _phc._lrg_map.find(m);
280 if (src_name != phi_name) {
281 Block *pred = _phc._cfg.get_block_for_node(b->pred(j));
282 Node *copy;
283 assert(!m->is_Con() || m->is_Mach(), "all Con must be Mach");
284 // Rematerialize constants instead of copying them
285 if( m->is_Mach() && m->as_Mach()->is_Con() &&
286 m->as_Mach()->rematerialize() ) {
287 copy = m->clone();
288 // Insert the copy in the predecessor basic block
289 pred->add_inst(copy);
290 // Copy any flags as well
291 _phc.clone_projs(pred, pred->end_idx(), m, copy, _phc._lrg_map);
292 } else {
293 const RegMask *rm = C->matcher()->idealreg2spillmask[m->ideal_reg()];
294 copy = new (C) MachSpillCopyNode(m, *rm, *rm);
295 // Find a good place to insert. Kinda tricky, use a subroutine
296 insert_copy_with_overlap(pred,copy,phi_name,src_name);
297 }
298 // Insert the copy in the use-def chain
299 n->set_req(j, copy);
300 _phc._cfg.map_node_to_block(copy, pred);
301 // Extend ("register allocate") the names array for the copy.
302 _phc._lrg_map.extend(copy->_idx, phi_name);
303 } // End of if Phi names do not match
304 } // End of for all inputs to Phi
305 } else { // End of if Phi
306
307 // Now check for 2-address instructions
308 uint idx;
309 if( n->is_Mach() && (idx=n->as_Mach()->two_adr()) ) {
310 // Get the chosen name for the Node
311 uint name = _phc._lrg_map.find(n);
312 assert (name, "no 2-address specials");
313 // Check for name mis-match on the 2-address input
314 Node *m = n->in(idx);
315 if (_phc._lrg_map.find(m) != name) {
316 Node *copy;
317 assert(!m->is_Con() || m->is_Mach(), "all Con must be Mach");
318 // At this point it is unsafe to extend live ranges (6550579).
319 // Rematerialize only constants as we do for Phi above.
320 if(m->is_Mach() && m->as_Mach()->is_Con() &&
321 m->as_Mach()->rematerialize()) {
322 copy = m->clone();
323 // Insert the copy in the basic block, just before us
324 b->insert_node(copy, l++);
325 l += _phc.clone_projs(b, l, m, copy, _phc._lrg_map);
326 } else {
327 const RegMask *rm = C->matcher()->idealreg2spillmask[m->ideal_reg()];
328 copy = new (C) MachSpillCopyNode(m, *rm, *rm);
329 // Insert the copy in the basic block, just before us
330 b->insert_node(copy, l++);
331 }
332 // Insert the copy in the use-def chain
333 n->set_req(idx, copy);
334 // Extend ("register allocate") the names array for the copy.
335 _phc._lrg_map.extend(copy->_idx, name);
336 _phc._cfg.map_node_to_block(copy, b);
337 }
338
339 } // End of is two-adr
340
341 // Insert a copy at a debug use for a lrg which has high frequency
342 if (b->_freq < OPTO_DEBUG_SPLIT_FREQ || _phc._cfg.is_uncommon(b)) {
343 // Walk the debug inputs to the node and check for lrg freq
344 JVMState* jvms = n->jvms();
345 uint debug_start = jvms ? jvms->debug_start() : 999999;
346 uint debug_end = jvms ? jvms->debug_end() : 999999;
347 for(uint inpidx = debug_start; inpidx < debug_end; inpidx++) {
348 // Do not split monitors; they are only needed for debug table
355 LRG &lrg = lrgs(nidx);
356
357 // If this lrg has a high frequency use/def
358 if( lrg._maxfreq >= _phc.high_frequency_lrg() ) {
359 // If the live range is also live out of this block (like it
360 // would be for a fast/slow idiom), the normal spill mechanism
361 // does an excellent job. If it is not live out of this block
362 // (like it would be for debug info to uncommon trap) splitting
363 // the live range now allows a better allocation in the high
364 // frequency blocks.
365 // Build_IFG_virtual has converted the live sets to
366 // live-IN info, not live-OUT info.
367 uint k;
368 for( k=0; k < b->_num_succs; k++ )
369 if( _phc._live->live(b->_succs[k])->member( nidx ) )
370 break; // Live in to some successor block?
371 if( k < b->_num_succs )
372 continue; // Live out; do not pre-split
373 // Split the lrg at this use
374 const RegMask *rm = C->matcher()->idealreg2spillmask[inp->ideal_reg()];
375 Node *copy = new (C) MachSpillCopyNode( inp, *rm, *rm );
376 // Insert the copy in the use-def chain
377 n->set_req(inpidx, copy );
378 // Insert the copy in the basic block, just before us
379 b->insert_node(copy, l++);
380 // Extend ("register allocate") the names array for the copy.
381 uint max_lrg_id = _phc._lrg_map.max_lrg_id();
382 _phc.new_lrg(copy, max_lrg_id);
383 _phc._lrg_map.set_max_lrg_id(max_lrg_id + 1);
384 _phc._cfg.map_node_to_block(copy, b);
385 //tty->print_cr("Split a debug use in Aggressive Coalesce");
386 } // End of if high frequency use/def
387 } // End of for all debug inputs
388 } // End of if low frequency safepoint
389
390 } // End of if Phi
391
392 } // End of for all instructions
393 } // End of for all blocks
394 }
395
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274 continue;
275 }
276 // Check for mismatch inputs to Phi
277 for (uint j = 1; j < cnt; j++) {
278 Node *m = n->in(j);
279 uint src_name = _phc._lrg_map.find(m);
280 if (src_name != phi_name) {
281 Block *pred = _phc._cfg.get_block_for_node(b->pred(j));
282 Node *copy;
283 assert(!m->is_Con() || m->is_Mach(), "all Con must be Mach");
284 // Rematerialize constants instead of copying them
285 if( m->is_Mach() && m->as_Mach()->is_Con() &&
286 m->as_Mach()->rematerialize() ) {
287 copy = m->clone();
288 // Insert the copy in the predecessor basic block
289 pred->add_inst(copy);
290 // Copy any flags as well
291 _phc.clone_projs(pred, pred->end_idx(), m, copy, _phc._lrg_map);
292 } else {
293 const RegMask *rm = C->matcher()->idealreg2spillmask[m->ideal_reg()];
294 copy = new (C) PhiInputSpillNode(m, *rm, *rm);
295 // Find a good place to insert. Kinda tricky, use a subroutine
296 insert_copy_with_overlap(pred,copy,phi_name,src_name);
297 }
298 // Insert the copy in the use-def chain
299 n->set_req(j, copy);
300 _phc._cfg.map_node_to_block(copy, pred);
301 // Extend ("register allocate") the names array for the copy.
302 _phc._lrg_map.extend(copy->_idx, phi_name);
303 } // End of if Phi names do not match
304 } // End of for all inputs to Phi
305 } else { // End of if Phi
306
307 // Now check for 2-address instructions
308 uint idx;
309 if( n->is_Mach() && (idx=n->as_Mach()->two_adr()) ) {
310 // Get the chosen name for the Node
311 uint name = _phc._lrg_map.find(n);
312 assert (name, "no 2-address specials");
313 // Check for name mis-match on the 2-address input
314 Node *m = n->in(idx);
315 if (_phc._lrg_map.find(m) != name) {
316 Node *copy;
317 assert(!m->is_Con() || m->is_Mach(), "all Con must be Mach");
318 // At this point it is unsafe to extend live ranges (6550579).
319 // Rematerialize only constants as we do for Phi above.
320 if(m->is_Mach() && m->as_Mach()->is_Con() &&
321 m->as_Mach()->rematerialize()) {
322 copy = m->clone();
323 // Insert the copy in the basic block, just before us
324 b->insert_node(copy, l++);
325 l += _phc.clone_projs(b, l, m, copy, _phc._lrg_map);
326 } else {
327 const RegMask *rm = C->matcher()->idealreg2spillmask[m->ideal_reg()];
328 copy = new (C) TwoAddressSpillNode(m, *rm, *rm);
329 // Insert the copy in the basic block, just before us
330 b->insert_node(copy, l++);
331 }
332 // Insert the copy in the use-def chain
333 n->set_req(idx, copy);
334 // Extend ("register allocate") the names array for the copy.
335 _phc._lrg_map.extend(copy->_idx, name);
336 _phc._cfg.map_node_to_block(copy, b);
337 }
338
339 } // End of is two-adr
340
341 // Insert a copy at a debug use for a lrg which has high frequency
342 if (b->_freq < OPTO_DEBUG_SPLIT_FREQ || _phc._cfg.is_uncommon(b)) {
343 // Walk the debug inputs to the node and check for lrg freq
344 JVMState* jvms = n->jvms();
345 uint debug_start = jvms ? jvms->debug_start() : 999999;
346 uint debug_end = jvms ? jvms->debug_end() : 999999;
347 for(uint inpidx = debug_start; inpidx < debug_end; inpidx++) {
348 // Do not split monitors; they are only needed for debug table
355 LRG &lrg = lrgs(nidx);
356
357 // If this lrg has a high frequency use/def
358 if( lrg._maxfreq >= _phc.high_frequency_lrg() ) {
359 // If the live range is also live out of this block (like it
360 // would be for a fast/slow idiom), the normal spill mechanism
361 // does an excellent job. If it is not live out of this block
362 // (like it would be for debug info to uncommon trap) splitting
363 // the live range now allows a better allocation in the high
364 // frequency blocks.
365 // Build_IFG_virtual has converted the live sets to
366 // live-IN info, not live-OUT info.
367 uint k;
368 for( k=0; k < b->_num_succs; k++ )
369 if( _phc._live->live(b->_succs[k])->member( nidx ) )
370 break; // Live in to some successor block?
371 if( k < b->_num_succs )
372 continue; // Live out; do not pre-split
373 // Split the lrg at this use
374 const RegMask *rm = C->matcher()->idealreg2spillmask[inp->ideal_reg()];
375 Node* copy = new (C) DebugUseSpillNode(inp, *rm, *rm);
376 // Insert the copy in the use-def chain
377 n->set_req(inpidx, copy );
378 // Insert the copy in the basic block, just before us
379 b->insert_node(copy, l++);
380 // Extend ("register allocate") the names array for the copy.
381 uint max_lrg_id = _phc._lrg_map.max_lrg_id();
382 _phc.new_lrg(copy, max_lrg_id);
383 _phc._lrg_map.set_max_lrg_id(max_lrg_id + 1);
384 _phc._cfg.map_node_to_block(copy, b);
385 //tty->print_cr("Split a debug use in Aggressive Coalesce");
386 } // End of if high frequency use/def
387 } // End of for all debug inputs
388 } // End of if low frequency safepoint
389
390 } // End of if Phi
391
392 } // End of for all instructions
393 } // End of for all blocks
394 }
395
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