1 /* 2 * Copyright (c) 1998, 2013, Oracle and/or its affiliates. All rights reserved. 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 4 * 5 * This code is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 only, as 7 * published by the Free Software Foundation. 8 * 9 * This code is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * version 2 for more details (a copy is included in the LICENSE file that 13 * accompanied this code). 14 * 15 * You should have received a copy of the GNU General Public License version 16 * 2 along with this work; if not, write to the Free Software Foundation, 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 18 * 19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 20 * or visit www.oracle.com if you need additional information or have any 21 * questions. 22 * 23 */ 24 25 #include "precompiled.hpp" 26 #include "compiler/oopMap.hpp" 27 #include "memory/allocation.inline.hpp" 28 #include "opto/addnode.hpp" 29 #include "opto/block.hpp" 30 #include "opto/callnode.hpp" 31 #include "opto/cfgnode.hpp" 32 #include "opto/chaitin.hpp" 33 #include "opto/coalesce.hpp" 34 #include "opto/connode.hpp" 35 #include "opto/indexSet.hpp" 36 #include "opto/machnode.hpp" 37 #include "opto/memnode.hpp" 38 #include "opto/opcodes.hpp" 39 40 PhaseIFG::PhaseIFG( Arena *arena ) : Phase(Interference_Graph), _arena(arena) { 41 } 42 43 void PhaseIFG::init( uint maxlrg ) { 44 _maxlrg = maxlrg; 45 _yanked = new (_arena) VectorSet(_arena); 46 _is_square = false; 47 // Make uninitialized adjacency lists 48 _adjs = (IndexSet*)_arena->Amalloc(sizeof(IndexSet)*maxlrg); 49 // Also make empty live range structures 50 _lrgs = (LRG *)_arena->Amalloc( maxlrg * sizeof(LRG) ); 51 memset(_lrgs,0,sizeof(LRG)*maxlrg); 52 // Init all to empty 53 for( uint i = 0; i < maxlrg; i++ ) { 54 _adjs[i].initialize(maxlrg); 55 _lrgs[i].Set_All(); 56 } 57 } 58 59 // Add edge between vertices a & b. These are sorted (triangular matrix), 60 // then the smaller number is inserted in the larger numbered array. 61 int PhaseIFG::add_edge( uint a, uint b ) { 62 lrgs(a).invalid_degree(); 63 lrgs(b).invalid_degree(); 64 // Sort a and b, so that a is bigger 65 assert( !_is_square, "only on triangular" ); 66 if( a < b ) { uint tmp = a; a = b; b = tmp; } 67 return _adjs[a].insert( b ); 68 } 69 70 // Add an edge between 'a' and everything in the vector. 71 void PhaseIFG::add_vector( uint a, IndexSet *vec ) { 72 // IFG is triangular, so do the inserts where 'a' < 'b'. 73 assert( !_is_square, "only on triangular" ); 74 IndexSet *adjs_a = &_adjs[a]; 75 if( !vec->count() ) return; 76 77 IndexSetIterator elements(vec); 78 uint neighbor; 79 while ((neighbor = elements.next()) != 0) { 80 add_edge( a, neighbor ); 81 } 82 } 83 84 // Is there an edge between a and b? 85 int PhaseIFG::test_edge( uint a, uint b ) const { 86 // Sort a and b, so that a is larger 87 assert( !_is_square, "only on triangular" ); 88 if( a < b ) { uint tmp = a; a = b; b = tmp; } 89 return _adjs[a].member(b); 90 } 91 92 // Convert triangular matrix to square matrix 93 void PhaseIFG::SquareUp() { 94 assert( !_is_square, "only on triangular" ); 95 96 // Simple transpose 97 for( uint i = 0; i < _maxlrg; i++ ) { 98 IndexSetIterator elements(&_adjs[i]); 99 uint datum; 100 while ((datum = elements.next()) != 0) { 101 _adjs[datum].insert( i ); 102 } 103 } 104 _is_square = true; 105 } 106 107 // Compute effective degree in bulk 108 void PhaseIFG::Compute_Effective_Degree() { 109 assert( _is_square, "only on square" ); 110 111 for( uint i = 0; i < _maxlrg; i++ ) 112 lrgs(i).set_degree(effective_degree(i)); 113 } 114 115 int PhaseIFG::test_edge_sq( uint a, uint b ) const { 116 assert( _is_square, "only on square" ); 117 // Swap, so that 'a' has the lesser count. Then binary search is on 118 // the smaller of a's list and b's list. 119 if( neighbor_cnt(a) > neighbor_cnt(b) ) { uint tmp = a; a = b; b = tmp; } 120 //return _adjs[a].unordered_member(b); 121 return _adjs[a].member(b); 122 } 123 124 // Union edges of B into A 125 void PhaseIFG::Union( uint a, uint b ) { 126 assert( _is_square, "only on square" ); 127 IndexSet *A = &_adjs[a]; 128 IndexSetIterator b_elements(&_adjs[b]); 129 uint datum; 130 while ((datum = b_elements.next()) != 0) { 131 if(A->insert(datum)) { 132 _adjs[datum].insert(a); 133 lrgs(a).invalid_degree(); 134 lrgs(datum).invalid_degree(); 135 } 136 } 137 } 138 139 // Yank a Node and all connected edges from the IFG. Return a 140 // list of neighbors (edges) yanked. 141 IndexSet *PhaseIFG::remove_node( uint a ) { 142 assert( _is_square, "only on square" ); 143 assert( !_yanked->test(a), "" ); 144 _yanked->set(a); 145 146 // I remove the LRG from all neighbors. 147 IndexSetIterator elements(&_adjs[a]); 148 LRG &lrg_a = lrgs(a); 149 uint datum; 150 while ((datum = elements.next()) != 0) { 151 _adjs[datum].remove(a); 152 lrgs(datum).inc_degree( -lrg_a.compute_degree(lrgs(datum)) ); 153 } 154 return neighbors(a); 155 } 156 157 // Re-insert a yanked Node. 158 void PhaseIFG::re_insert( uint a ) { 159 assert( _is_square, "only on square" ); 160 assert( _yanked->test(a), "" ); 161 (*_yanked) >>= a; 162 163 IndexSetIterator elements(&_adjs[a]); 164 uint datum; 165 while ((datum = elements.next()) != 0) { 166 _adjs[datum].insert(a); 167 lrgs(datum).invalid_degree(); 168 } 169 } 170 171 // Compute the degree between 2 live ranges. If both live ranges are 172 // aligned-adjacent powers-of-2 then we use the MAX size. If either is 173 // mis-aligned (or for Fat-Projections, not-adjacent) then we have to 174 // MULTIPLY the sizes. Inspect Brigg's thesis on register pairs to see why 175 // this is so. 176 int LRG::compute_degree( LRG &l ) const { 177 int tmp; 178 int num_regs = _num_regs; 179 int nregs = l.num_regs(); 180 tmp = (_fat_proj || l._fat_proj) // either is a fat-proj? 181 ? (num_regs * nregs) // then use product 182 : MAX2(num_regs,nregs); // else use max 183 return tmp; 184 } 185 186 // Compute effective degree for this live range. If both live ranges are 187 // aligned-adjacent powers-of-2 then we use the MAX size. If either is 188 // mis-aligned (or for Fat-Projections, not-adjacent) then we have to 189 // MULTIPLY the sizes. Inspect Brigg's thesis on register pairs to see why 190 // this is so. 191 int PhaseIFG::effective_degree( uint lidx ) const { 192 int eff = 0; 193 int num_regs = lrgs(lidx).num_regs(); 194 int fat_proj = lrgs(lidx)._fat_proj; 195 IndexSet *s = neighbors(lidx); 196 IndexSetIterator elements(s); 197 uint nidx; 198 while((nidx = elements.next()) != 0) { 199 LRG &lrgn = lrgs(nidx); 200 int nregs = lrgn.num_regs(); 201 eff += (fat_proj || lrgn._fat_proj) // either is a fat-proj? 202 ? (num_regs * nregs) // then use product 203 : MAX2(num_regs,nregs); // else use max 204 } 205 return eff; 206 } 207 208 209 #ifndef PRODUCT 210 void PhaseIFG::dump() const { 211 tty->print_cr("-- Interference Graph --%s--", 212 _is_square ? "square" : "triangular" ); 213 if( _is_square ) { 214 for( uint i = 0; i < _maxlrg; i++ ) { 215 tty->print( (*_yanked)[i] ? "XX " : " "); 216 tty->print("L%d: { ",i); 217 IndexSetIterator elements(&_adjs[i]); 218 uint datum; 219 while ((datum = elements.next()) != 0) { 220 tty->print("L%d ", datum); 221 } 222 tty->print_cr("}"); 223 224 } 225 return; 226 } 227 228 // Triangular 229 for( uint i = 0; i < _maxlrg; i++ ) { 230 uint j; 231 tty->print( (*_yanked)[i] ? "XX " : " "); 232 tty->print("L%d: { ",i); 233 for( j = _maxlrg; j > i; j-- ) 234 if( test_edge(j - 1,i) ) { 235 tty->print("L%d ",j - 1); 236 } 237 tty->print("| "); 238 IndexSetIterator elements(&_adjs[i]); 239 uint datum; 240 while ((datum = elements.next()) != 0) { 241 tty->print("L%d ", datum); 242 } 243 tty->print("}\n"); 244 } 245 tty->print("\n"); 246 } 247 248 void PhaseIFG::stats() const { 249 ResourceMark rm; 250 int *h_cnt = NEW_RESOURCE_ARRAY(int,_maxlrg*2); 251 memset( h_cnt, 0, sizeof(int)*_maxlrg*2 ); 252 uint i; 253 for( i = 0; i < _maxlrg; i++ ) { 254 h_cnt[neighbor_cnt(i)]++; 255 } 256 tty->print_cr("--Histogram of counts--"); 257 for( i = 0; i < _maxlrg*2; i++ ) 258 if( h_cnt[i] ) 259 tty->print("%d/%d ",i,h_cnt[i]); 260 tty->print_cr(""); 261 } 262 263 void PhaseIFG::verify( const PhaseChaitin *pc ) const { 264 // IFG is square, sorted and no need for Find 265 for( uint i = 0; i < _maxlrg; i++ ) { 266 assert(!((*_yanked)[i]) || !neighbor_cnt(i), "Is removed completely" ); 267 IndexSet *set = &_adjs[i]; 268 IndexSetIterator elements(set); 269 uint idx; 270 uint last = 0; 271 while ((idx = elements.next()) != 0) { 272 assert(idx != i, "Must have empty diagonal"); 273 assert(pc->_lrg_map.find_const(idx) == idx, "Must not need Find"); 274 assert(_adjs[idx].member(i), "IFG not square"); 275 assert(!(*_yanked)[idx], "No yanked neighbors"); 276 assert(last < idx, "not sorted increasing"); 277 last = idx; 278 } 279 assert(!lrgs(i)._degree_valid || effective_degree(i) == lrgs(i).degree(), "degree is valid but wrong"); 280 } 281 } 282 #endif 283 284 /* 285 * Interfere this register with everything currently live. 286 * Check for interference by checking overlap of regmasks. 287 * Only interfere if acceptable register masks overlap. 288 */ 289 void PhaseChaitin::interfere_with_live(uint lid, IndexSet* liveout) { 290 LRG& lrg = lrgs(lid); 291 const RegMask& rm = lrg.mask(); 292 IndexSetIterator elements(liveout); 293 uint interfering_lid = elements.next(); 294 while (interfering_lid != 0) { 295 LRG& interfering_lrg = lrgs(interfering_lid); 296 if (rm.overlap(interfering_lrg.mask())) { 297 _ifg->add_edge(lid, interfering_lid); 298 } 299 interfering_lid = elements.next(); 300 } 301 } 302 303 // Actually build the interference graph. Uses virtual registers only, no 304 // physical register masks. This allows me to be very aggressive when 305 // coalescing copies. Some of this aggressiveness will have to be undone 306 // later, but I'd rather get all the copies I can now (since unremoved copies 307 // at this point can end up in bad places). Copies I re-insert later I have 308 // more opportunity to insert them in low-frequency locations. 309 void PhaseChaitin::build_ifg_virtual( ) { 310 311 // For all blocks (in any order) do... 312 for (uint i = 0; i < _cfg.number_of_blocks(); i++) { 313 Block* block = _cfg.get_block(i); 314 IndexSet* liveout = _live->live(block); 315 316 // The IFG is built by a single reverse pass over each basic block. 317 // Starting with the known live-out set, we remove things that get 318 // defined and add things that become live (essentially executing one 319 // pass of a standard LIVE analysis). Just before a Node defines a value 320 // (and removes it from the live-ness set) that value is certainly live. 321 // The defined value interferes with everything currently live. The 322 // value is then removed from the live-ness set and it's inputs are 323 // added to the live-ness set. 324 for (uint j = block->end_idx() + 1; j > 1; j--) { 325 Node* n = block->get_node(j - 1); 326 327 // Get value being defined 328 uint r = _lrg_map.live_range_id(n); 329 330 // Some special values do not allocate 331 if (r) { 332 333 // Remove from live-out set 334 liveout->remove(r); 335 336 // Copies do not define a new value and so do not interfere. 337 // Remove the copies source from the liveout set before interfering. 338 uint idx = n->is_Copy(); 339 if (idx != 0) { 340 liveout->remove(_lrg_map.live_range_id(n->in(idx))); 341 } 342 343 // Interfere with everything live 344 interfere_with_live(r, liveout); 345 } 346 347 // Make all inputs live 348 if (!n->is_Phi()) { // Phi function uses come from prior block 349 for(uint k = 1; k < n->req(); k++) { 350 liveout->insert(_lrg_map.live_range_id(n->in(k))); 351 } 352 } 353 354 // 2-address instructions always have the defined value live 355 // on entry to the instruction, even though it is being defined 356 // by the instruction. We pretend a virtual copy sits just prior 357 // to the instruction and kills the src-def'd register. 358 // In other words, for 2-address instructions the defined value 359 // interferes with all inputs. 360 uint idx; 361 if( n->is_Mach() && (idx = n->as_Mach()->two_adr()) ) { 362 const MachNode *mach = n->as_Mach(); 363 // Sometimes my 2-address ADDs are commuted in a bad way. 364 // We generally want the USE-DEF register to refer to the 365 // loop-varying quantity, to avoid a copy. 366 uint op = mach->ideal_Opcode(); 367 // Check that mach->num_opnds() == 3 to ensure instruction is 368 // not subsuming constants, effectively excludes addI_cin_imm 369 // Can NOT swap for instructions like addI_cin_imm since it 370 // is adding zero to yhi + carry and the second ideal-input 371 // points to the result of adding low-halves. 372 // Checking req() and num_opnds() does NOT distinguish addI_cout from addI_cout_imm 373 if( (op == Op_AddI && mach->req() == 3 && mach->num_opnds() == 3) && 374 n->in(1)->bottom_type()->base() == Type::Int && 375 // See if the ADD is involved in a tight data loop the wrong way 376 n->in(2)->is_Phi() && 377 n->in(2)->in(2) == n ) { 378 Node *tmp = n->in(1); 379 n->set_req( 1, n->in(2) ); 380 n->set_req( 2, tmp ); 381 } 382 // Defined value interferes with all inputs 383 uint lidx = _lrg_map.live_range_id(n->in(idx)); 384 for (uint k = 1; k < n->req(); k++) { 385 uint kidx = _lrg_map.live_range_id(n->in(k)); 386 if (kidx != lidx) { 387 _ifg->add_edge(r, kidx); 388 } 389 } 390 } 391 } // End of forall instructions in block 392 } // End of forall blocks 393 } 394 395 #ifdef ASSERT 396 uint PhaseChaitin::count_int_pressure(IndexSet* liveout) { 397 IndexSetIterator elements(liveout); 398 uint lidx = elements.next(); 399 uint cnt = 0; 400 while (lidx != 0) { 401 LRG& lrg = lrgs(lidx); 402 if (lrg.mask_is_nonempty_and_up() && 403 !lrg.is_float_or_vector() && 404 lrg.mask().overlap(*Matcher::idealreg2regmask[Op_RegI])) { 405 cnt += lrg.reg_pressure(); 406 } 407 lidx = elements.next(); 408 } 409 return cnt; 410 } 411 412 uint PhaseChaitin::count_float_pressure(IndexSet* liveout) { 413 IndexSetIterator elements(liveout); 414 uint lidx = elements.next(); 415 uint cnt = 0; 416 while (lidx != 0) { 417 LRG& lrg = lrgs(lidx); 418 if (lrg.mask_is_nonempty_and_up() && lrg.is_float_or_vector()) { 419 cnt += lrg.reg_pressure(); 420 } 421 lidx = elements.next(); 422 } 423 return cnt; 424 } 425 #endif 426 427 /* 428 * Adjust register pressure down by 1. Capture last hi-to-low transition, 429 */ 430 void PhaseChaitin::lower_pressure(Block* b, uint location, LRG& lrg, IndexSet* liveout, Pressure& int_pressure, Pressure& float_pressure) { 431 if (lrg.mask_is_nonempty_and_up()) { 432 if (lrg.is_float_or_vector()) { 433 float_pressure.lower(lrg, location); 434 } else { 435 // Do not count the SP and flag registers 436 const RegMask& r = lrg.mask(); 437 if (r.overlap(*Matcher::idealreg2regmask[Op_RegI])) { 438 int_pressure.lower(lrg, location); 439 } 440 } 441 } 442 assert(int_pressure._current_pressure == count_int_pressure(liveout), "the int pressure is incorrect"); 443 assert(float_pressure._current_pressure == count_float_pressure(liveout), "the float pressure is incorrect"); 444 } 445 446 /* Go to the first non-phi index in a block */ 447 static uint first_nonphi_index(Block* b) { 448 uint i; 449 uint end_idx = b->end_idx(); 450 for (i = 1; i < end_idx; i++) { 451 Node* n = b->get_node(i); 452 if (!n->is_Phi()) { 453 break; 454 } 455 } 456 return i; 457 } 458 459 /* 460 * Spills could be inserted before a CreateEx node which should be the first 461 * instruction in a block after Phi nodes. If so, move the CreateEx node up. 462 */ 463 static void move_exception_node_up(Block* b, uint first_inst, uint last_inst) { 464 for (uint i = first_inst; i < last_inst; i++) { 465 Node* ex = b->get_node(i); 466 if (ex->is_SpillCopy()) { 467 continue; 468 } 469 470 if (i > first_inst && 471 ex->is_Mach() && ex->as_Mach()->ideal_Opcode() == Op_CreateEx) { 472 b->remove_node(i); 473 b->insert_node(ex, first_inst); 474 } 475 // Stop once a CreateEx or any other node is found 476 break; 477 } 478 } 479 480 /* 481 * When new live ranges are live, we raise the register pressure 482 */ 483 void PhaseChaitin::raise_pressure(Block* b, LRG& lrg, Pressure& int_pressure, Pressure& float_pressure) { 484 if (lrg.mask_is_nonempty_and_up()) { 485 if (lrg.is_float_or_vector()) { 486 float_pressure.raise(lrg); 487 } else { 488 // Do not count the SP and flag registers 489 const RegMask& rm = lrg.mask(); 490 if (rm.overlap(*Matcher::idealreg2regmask[Op_RegI])) { 491 int_pressure.raise(lrg); 492 } 493 } 494 } 495 } 496 497 498 /* 499 * Computes the initial register pressure of a block, looking at all live 500 * ranges in the liveout. The register pressure is computed for both float 501 * and int/pointer registers. 502 * Live ranges in the liveout are presumed live for the whole block. 503 * We add the cost for the whole block to the area of the live ranges initially. 504 * If a live range gets killed in the block, we'll subtract the unused part of 505 * the block from the area. 506 */ 507 void PhaseChaitin::compute_initial_block_pressure(Block* b, IndexSet* liveout, Pressure& int_pressure, Pressure& float_pressure, double cost) { 508 IndexSetIterator elements(liveout); 509 uint lid = elements.next(); 510 while (lid != 0) { 511 LRG& lrg = lrgs(lid); 512 lrg._area += cost; 513 raise_pressure(b, lrg, int_pressure, float_pressure); 514 lid = elements.next(); 515 } 516 assert(int_pressure._current_pressure == count_int_pressure(liveout), "the int pressure is incorrect"); 517 assert(float_pressure._current_pressure == count_float_pressure(liveout), "the float pressure is incorrect"); 518 } 519 520 /* 521 * Remove dead node if it's not used. 522 * We only remove projection nodes if the node "defining" the projection is 523 * dead, for example on x86, if we have a dead Add node we remove its 524 * RFLAGS node. 525 */ 526 bool PhaseChaitin::remove_node_if_not_used(Block* b, uint location, Node* n, uint lid, IndexSet* liveout) { 527 Node* def = n->in(0); 528 if (!n->is_Proj() || 529 (_lrg_map.live_range_id(def) && !liveout->member(_lrg_map.live_range_id(def)))) { 530 b->remove_node(location); 531 LRG& lrg = lrgs(lid); 532 if (lrg._def == n) { 533 lrg._def = 0; 534 } 535 n->disconnect_inputs(NULL, C); 536 _cfg.unmap_node_from_block(n); 537 n->replace_by(C->top()); 538 return true; 539 } 540 return false; 541 } 542 543 /* 544 * When encountering a fat projection, we might go from a low to high to low 545 * (since the fat proj only lives at this instruction) going backwards in the 546 * block. If we find a low to high transition, we record it. 547 */ 548 void PhaseChaitin::check_for_high_pressure_transition_at_fatproj(uint& block_reg_pressure, uint location, LRG& lrg, Pressure& pressure, const int op_regtype) { 549 RegMask mask_tmp = lrg.mask(); 550 mask_tmp.AND(*Matcher::idealreg2regmask[op_regtype]); 551 // this pressure is only valid at this instruction, i.e. we don't need to lower 552 // the register pressure since the fat proj was never live before (going backwards) 553 uint new_pressure = pressure._current_pressure + mask_tmp.Size(); 554 if (new_pressure > pressure._final_pressure) { 555 pressure._final_pressure = new_pressure; 556 } 557 // if we were at a low pressure and now at the fat proj is at high pressure, record the fat proj location 558 // as coming from a low to high (to low again) 559 if (pressure._current_pressure <= pressure._high_pressure_limit && new_pressure > pressure._high_pressure_limit) { 560 pressure._high_pressure_index = location; 561 } 562 } 563 564 /* 565 * Insure high score for immediate-use spill copies so they get a color. 566 * All single-use MachSpillCopy(s) that immediately precede their 567 * use must color early. If a longer live range steals their 568 * color, the spill copy will split and may push another spill copy 569 * further away resulting in an infinite spill-split-retry cycle. 570 * Assigning a zero area results in a high score() and a good 571 * location in the simplify list. 572 */ 573 void PhaseChaitin::assign_high_score_to_immediate_copies(Block* b, Node* n, LRG& lrg, uint next_inst, uint last_inst) { 574 if (n->is_SpillCopy() && 575 lrg.is_singledef() && // A multi defined live range can still split 576 n->outcnt() == 1 && // and use must be in this block 577 _cfg.get_block_for_node(n->unique_out()) == b) { 578 579 Node* single_use = n->unique_out(); 580 assert(b->find_node(single_use) >= next_inst, "Use must be later in block"); 581 // Use can be earlier in block if it is a Phi, but then I should be a MultiDef 582 583 // Find first non SpillCopy 'm' that follows the current instruction 584 // (current_inst - 1) is index for current instruction 'n' 585 Node* m = n; 586 for (uint i = next_inst; i <= last_inst && m->is_SpillCopy(); ++i) { 587 m = b->get_node(i); 588 } 589 if (m == single_use) { 590 lrg._area = 0.0; 591 } 592 } 593 } 594 595 /* 596 * Copies do not define a new value and so do not interfere. 597 * Remove the copies source from the liveout set before interfering. 598 */ 599 void PhaseChaitin::remove_interference_from_copy(Block* b, uint location, uint lid_copy, IndexSet* liveout, double cost, Pressure& int_pressure, Pressure& float_pressure) { 600 if (liveout->remove(lid_copy)) { 601 LRG& lrg_copy = lrgs(lid_copy); 602 lrg_copy._area -= cost; 603 604 // Lower register pressure since copy and definition can share the same register 605 lower_pressure(b, location, lrg_copy, liveout, int_pressure, float_pressure); 606 } 607 } 608 609 /* 610 * The defined value must go in a particular register. Remove that register from 611 * all conflicting parties and avoid the interference. 612 */ 613 void PhaseChaitin::remove_bound_register_from_interfering_live_ranges(LRG& lrg, IndexSet* liveout, uint& must_spill) { 614 // Check for common case 615 const RegMask& rm = lrg.mask(); 616 int r_size = lrg.num_regs(); 617 // Smear odd bits 618 IndexSetIterator elements(liveout); 619 uint l = elements.next(); 620 while (l != 0) { 621 LRG& interfering_lrg = lrgs(l); 622 // If 'l' must spill already, do not further hack his bits. 623 // He'll get some interferences and be forced to spill later. 624 if (interfering_lrg._must_spill) { 625 l = elements.next(); 626 continue; 627 } 628 629 // Remove bound register(s) from 'l's choices 630 RegMask old = interfering_lrg.mask(); 631 uint old_size = interfering_lrg.mask_size(); 632 633 // Remove the bits from LRG 'rm' from LRG 'l' so 'l' no 634 // longer interferes with 'rm'. If 'l' requires aligned 635 // adjacent pairs, subtract out bit pairs. 636 assert(!interfering_lrg._is_vector || !interfering_lrg._fat_proj, "sanity"); 637 638 if (interfering_lrg.num_regs() > 1 && !interfering_lrg._fat_proj) { 639 RegMask r2mask = rm; 640 // Leave only aligned set of bits. 641 r2mask.smear_to_sets(interfering_lrg.num_regs()); 642 // It includes vector case. 643 interfering_lrg.SUBTRACT(r2mask); 644 interfering_lrg.compute_set_mask_size(); 645 } else if (r_size != 1) { 646 // fat proj 647 interfering_lrg.SUBTRACT(rm); 648 interfering_lrg.compute_set_mask_size(); 649 } else { 650 // Common case: size 1 bound removal 651 OptoReg::Name r_reg = rm.find_first_elem(); 652 if (interfering_lrg.mask().Member(r_reg)) { 653 interfering_lrg.Remove(r_reg); 654 interfering_lrg.set_mask_size(interfering_lrg.mask().is_AllStack() ? LRG::AllStack_size : old_size - 1); 655 } 656 } 657 658 // If 'l' goes completely dry, it must spill. 659 if (interfering_lrg.not_free()) { 660 // Give 'l' some kind of reasonable mask, so it picks up 661 // interferences (and will spill later). 662 interfering_lrg.set_mask(old); 663 interfering_lrg.set_mask_size(old_size); 664 must_spill++; 665 interfering_lrg._must_spill = 1; 666 interfering_lrg.set_reg(OptoReg::Name(LRG::SPILL_REG)); 667 } 668 l = elements.next(); 669 } 670 } 671 672 /* 673 * Start loop at 1 (skip control edge) for most Nodes. SCMemProj's might be the 674 * sole use of a StoreLConditional. While StoreLConditionals set memory (the 675 * SCMemProj use) they also def flags; if that flag def is unused the allocator 676 * sees a flag-setting instruction with no use of the flags and assumes it's 677 * dead. This keeps the (useless) flag-setting behavior alive while also 678 * keeping the (useful) memory update effect. 679 */ 680 void PhaseChaitin::add_input_to_liveout(Block* b, Node* n, IndexSet* liveout, double cost, Pressure& int_pressure, Pressure& float_pressure) { 681 JVMState* jvms = n->jvms(); 682 uint debug_start = jvms ? jvms->debug_start() : 999999; 683 684 for (uint k = ((n->Opcode() == Op_SCMemProj) ? 0:1); k < n->req(); k++) { 685 Node* def = n->in(k); 686 uint lid = _lrg_map.live_range_id(def); 687 if (!lid) { 688 continue; 689 } 690 LRG& lrg = lrgs(lid); 691 692 // No use-side cost for spilling debug info 693 if (k < debug_start) { 694 // A USE costs twice block frequency (once for the Load, once 695 // for a Load-delay). Rematerialized uses only cost once. 696 lrg._cost += (def->rematerialize() ? b->_freq : (b->_freq * 2)); 697 } 698 699 if (liveout->insert(lid)) { 700 // Newly live things assumed live from here to top of block 701 lrg._area += cost; 702 raise_pressure(b, lrg, int_pressure, float_pressure); 703 assert(int_pressure._current_pressure == count_int_pressure(liveout), "the int pressure is incorrect"); 704 assert(float_pressure._current_pressure == count_float_pressure(liveout), "the float pressure is incorrect"); 705 } 706 assert(!(lrg._area < 0.0), "negative spill area" ); 707 } 708 } 709 710 /* 711 * If we run off the top of the block with high pressure just record that the 712 * whole block is high pressure. (Even though we might have a transition 713 * lower down in the block) 714 */ 715 void PhaseChaitin::check_for_high_pressure_block(Pressure& pressure) { 716 // current pressure now means the pressure before the first instruction in the block 717 // (since we have stepped through all instructions backwards) 718 if (pressure._current_pressure > pressure._high_pressure_limit) { 719 pressure._high_pressure_index = 0; 720 } 721 } 722 723 /* 724 * Compute high pressure indice; avoid landing in the middle of projnodes 725 * and set the high pressure index for the block 726 */ 727 void PhaseChaitin::adjust_high_pressure_index(Block* b, uint& block_hrp_index, Pressure& pressure) { 728 uint i = pressure._high_pressure_index; 729 if (i < b->number_of_nodes() && i < b->end_idx() + 1) { 730 Node* cur = b->get_node(i); 731 while (cur->is_Proj() || (cur->is_MachNullCheck()) || cur->is_Catch()) { 732 cur = b->get_node(--i); 733 } 734 } 735 block_hrp_index = i; 736 } 737 738 /* Build an interference graph: 739 * That is, if 2 live ranges are simultaneously alive but in their acceptable 740 * register sets do not overlap, then they do not interfere. The IFG is built 741 * by a single reverse pass over each basic block. Starting with the known 742 * live-out set, we remove things that get defined and add things that become 743 * live (essentially executing one pass of a standard LIVE analysis). Just 744 * before a Node defines a value (and removes it from the live-ness set) that 745 * value is certainly live. The defined value interferes with everything 746 * currently live. The value is then removed from the live-ness set and it's 747 * inputs are added to the live-ness set. 748 * Compute register pressure for each block: 749 * We store the biggest register pressure for each block and also the first 750 * low to high register pressure transition within the block (if any). 751 */ 752 uint PhaseChaitin::build_ifg_physical( ResourceArea *a ) { 753 NOT_PRODUCT(Compile::TracePhase t3("buildIFG", &_t_buildIFGphysical, TimeCompiler);) 754 755 uint must_spill = 0; 756 for (uint i = 0; i < _cfg.number_of_blocks(); i++) { 757 Block* block = _cfg.get_block(i); 758 759 // Clone (rather than smash in place) the liveout info, so it is alive 760 // for the "collect_gc_info" phase later. 761 IndexSet liveout(_live->live(block)); 762 763 uint first_inst = first_nonphi_index(block); 764 uint last_inst = block->end_idx(); 765 766 move_exception_node_up(block, first_inst, last_inst); 767 768 Pressure int_pressure(last_inst + 1, INTPRESSURE); 769 Pressure float_pressure(last_inst + 1, FLOATPRESSURE); 770 block->_reg_pressure = 0; 771 block->_freg_pressure = 0; 772 773 int inst_count = last_inst - first_inst; 774 double cost = (inst_count <= 0) ? 0.0 : block->_freq * double(inst_count); 775 assert(!(cost < 0.0), "negative spill cost" ); 776 777 compute_initial_block_pressure(block, &liveout, int_pressure, float_pressure, cost); 778 779 for (uint location = last_inst; location > 0; location--) { 780 Node* n = block->get_node(location); 781 uint lid = _lrg_map.live_range_id(n); 782 783 if(lid) { 784 LRG& lrg = lrgs(lid); 785 786 // A DEF normally costs block frequency; rematerialized values are 787 // removed from the DEF sight, so LOWER costs here. 788 lrg._cost += n->rematerialize() ? 0 : block->_freq; 789 790 if (!liveout.member(lid) && n->Opcode() != Op_SafePoint) { 791 if (remove_node_if_not_used(block, location, n, lid, &liveout)) { 792 float_pressure._high_pressure_index--; 793 int_pressure._high_pressure_index--; 794 continue; 795 } 796 if (lrg._fat_proj) { 797 check_for_high_pressure_transition_at_fatproj(block->_reg_pressure, location, lrg, int_pressure, Op_RegI); 798 check_for_high_pressure_transition_at_fatproj(block->_freg_pressure, location, lrg, float_pressure, Op_RegD); 799 } 800 } else { 801 // A live range ends at its definition, remove the remaining area. 802 lrg._area -= cost; 803 assert(lrg._area >= 0.0, "negative spill area" ); 804 805 assign_high_score_to_immediate_copies(block, n, lrg, location + 1, last_inst); 806 807 if (liveout.remove(lid)) { 808 lower_pressure(block, location, lrg, &liveout, int_pressure, float_pressure); 809 } 810 uint copy_idx = n->is_Copy(); 811 if (copy_idx) { 812 uint lid_copy = _lrg_map.live_range_id(n->in(copy_idx)); 813 remove_interference_from_copy(block, location, lid_copy, &liveout, cost, int_pressure, float_pressure); 814 } 815 } 816 817 // Since rematerializable DEFs are not bound but the live range is, 818 // some uses must be bound. If we spill live range 'r', it can 819 // rematerialize at each use site according to its bindings. 820 if (lrg.is_bound() && !n->rematerialize() && lrg.mask().is_NotEmpty()) { 821 remove_bound_register_from_interfering_live_ranges(lrg, &liveout, must_spill); 822 } 823 interfere_with_live(lid, &liveout); 824 } 825 826 // Area remaining in the block 827 inst_count--; 828 cost = (inst_count <= 0) ? 0.0 : block->_freq * double(inst_count); 829 830 if (!n->is_Phi()) { 831 add_input_to_liveout(block, n, &liveout, cost, int_pressure, float_pressure); 832 } 833 } 834 835 check_for_high_pressure_block(int_pressure); 836 check_for_high_pressure_block(float_pressure); 837 adjust_high_pressure_index(block, block->_ihrp_index, int_pressure); 838 adjust_high_pressure_index(block, block->_fhrp_index, float_pressure); 839 // set the final_pressure as the register pressure for the block 840 block->_reg_pressure = int_pressure._final_pressure; 841 block->_freg_pressure = float_pressure._final_pressure; 842 843 #ifndef PRODUCT 844 // Gather Register Pressure Statistics 845 if (PrintOptoStatistics) { 846 if (block->_reg_pressure > int_pressure._high_pressure_limit || block->_freg_pressure > float_pressure._high_pressure_limit) { 847 _high_pressure++; 848 } else { 849 _low_pressure++; 850 } 851 } 852 #endif 853 } 854 855 return must_spill; 856 }