1 /*
2 * Copyright (c) 1997, 2015, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
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23 */
24
25 #ifndef CPU_SPARC_VM_ASSEMBLER_SPARC_HPP
26 #define CPU_SPARC_VM_ASSEMBLER_SPARC_HPP
27
28 #include "asm/register.hpp"
29
30 // The SPARC Assembler: Pure assembler doing NO optimizations on the instruction
31 // level; i.e., what you write
32 // is what you get. The Assembler is generating code into a CodeBuffer.
33
34 class Assembler : public AbstractAssembler {
35 friend class AbstractAssembler;
36 friend class AddressLiteral;
37
38 // code patchers need various routines like inv_wdisp()
39 friend class NativeInstruction;
40 friend class NativeGeneralJump;
41 friend class Relocation;
42 friend class Label;
43
44 public:
45 // op carries format info; see page 62 & 267
46
47 enum ops {
48 call_op = 1, // fmt 1
49 branch_op = 0, // also sethi (fmt2)
50 arith_op = 2, // fmt 3, arith & misc
51 ldst_op = 3 // fmt 3, load/store
52 };
53
54 enum op2s {
55 bpr_op2 = 3,
56 fb_op2 = 6,
57 fbp_op2 = 5,
58 br_op2 = 2,
59 bp_op2 = 1,
60 sethi_op2 = 4
61 };
62
63 enum op3s {
64 // selected op3s
65 add_op3 = 0x00,
66 and_op3 = 0x01,
67 or_op3 = 0x02,
68 xor_op3 = 0x03,
69 sub_op3 = 0x04,
70 andn_op3 = 0x05,
71 orn_op3 = 0x06,
72 xnor_op3 = 0x07,
73 addc_op3 = 0x08,
74 mulx_op3 = 0x09,
75 umul_op3 = 0x0a,
76 smul_op3 = 0x0b,
77 subc_op3 = 0x0c,
78 udivx_op3 = 0x0d,
79 udiv_op3 = 0x0e,
80 sdiv_op3 = 0x0f,
81
82 addcc_op3 = 0x10,
83 andcc_op3 = 0x11,
84 orcc_op3 = 0x12,
85 xorcc_op3 = 0x13,
86 subcc_op3 = 0x14,
87 andncc_op3 = 0x15,
88 orncc_op3 = 0x16,
89 xnorcc_op3 = 0x17,
90 addccc_op3 = 0x18,
91 aes4_op3 = 0x19,
92 umulcc_op3 = 0x1a,
93 smulcc_op3 = 0x1b,
94 subccc_op3 = 0x1c,
95 udivcc_op3 = 0x1e,
96 sdivcc_op3 = 0x1f,
97
98 taddcc_op3 = 0x20,
99 tsubcc_op3 = 0x21,
100 taddcctv_op3 = 0x22,
101 tsubcctv_op3 = 0x23,
102 mulscc_op3 = 0x24,
103 sll_op3 = 0x25,
104 sllx_op3 = 0x25,
105 srl_op3 = 0x26,
106 srlx_op3 = 0x26,
107 sra_op3 = 0x27,
108 srax_op3 = 0x27,
109 rdreg_op3 = 0x28,
110 membar_op3 = 0x28,
111
112 flushw_op3 = 0x2b,
113 movcc_op3 = 0x2c,
114 sdivx_op3 = 0x2d,
115 popc_op3 = 0x2e,
116 movr_op3 = 0x2f,
117
118 sir_op3 = 0x30,
119 wrreg_op3 = 0x30,
120 saved_op3 = 0x31,
121
122 fpop1_op3 = 0x34,
123 fpop2_op3 = 0x35,
124 impdep1_op3 = 0x36,
125 aes3_op3 = 0x36,
126 sha_op3 = 0x36,
127 bmask_op3 = 0x36,
128 bshuffle_op3 = 0x36,
129 alignaddr_op3 = 0x36,
130 faligndata_op3 = 0x36,
131 flog3_op3 = 0x36,
132 edge_op3 = 0x36,
133 fzero_op3 = 0x36,
134 fsrc_op3 = 0x36,
135 fnot_op3 = 0x36,
136 xmulx_op3 = 0x36,
137 crc32c_op3 = 0x36,
138 impdep2_op3 = 0x37,
139 stpartialf_op3 = 0x37,
140 jmpl_op3 = 0x38,
141 rett_op3 = 0x39,
142 trap_op3 = 0x3a,
143 flush_op3 = 0x3b,
144 save_op3 = 0x3c,
145 restore_op3 = 0x3d,
146 done_op3 = 0x3e,
147 retry_op3 = 0x3e,
148
149 lduw_op3 = 0x00,
150 ldub_op3 = 0x01,
151 lduh_op3 = 0x02,
152 ldd_op3 = 0x03,
153 stw_op3 = 0x04,
154 stb_op3 = 0x05,
155 sth_op3 = 0x06,
156 std_op3 = 0x07,
157 ldsw_op3 = 0x08,
158 ldsb_op3 = 0x09,
159 ldsh_op3 = 0x0a,
160 ldx_op3 = 0x0b,
161
162 stx_op3 = 0x0e,
163 swap_op3 = 0x0f,
164
165 stwa_op3 = 0x14,
166 stxa_op3 = 0x1e,
167
168 ldf_op3 = 0x20,
169 ldfsr_op3 = 0x21,
170 ldqf_op3 = 0x22,
171 lddf_op3 = 0x23,
172 stf_op3 = 0x24,
173 stfsr_op3 = 0x25,
174 stqf_op3 = 0x26,
175 stdf_op3 = 0x27,
176
177 prefetch_op3 = 0x2d,
178
179 casa_op3 = 0x3c,
180 casxa_op3 = 0x3e,
181
182 mftoi_op3 = 0x36,
183
184 alt_bit_op3 = 0x10,
185 cc_bit_op3 = 0x10
186 };
187
188 enum opfs {
189 // selected opfs
190 edge8n_opf = 0x01,
191
192 fmovs_opf = 0x01,
193 fmovd_opf = 0x02,
194
195 fnegs_opf = 0x05,
196 fnegd_opf = 0x06,
197
198 alignaddr_opf = 0x18,
199 bmask_opf = 0x19,
200
201 fadds_opf = 0x41,
202 faddd_opf = 0x42,
203 fsubs_opf = 0x45,
204 fsubd_opf = 0x46,
205
206 faligndata_opf = 0x48,
207
208 fmuls_opf = 0x49,
209 fmuld_opf = 0x4a,
210 bshuffle_opf = 0x4c,
211 fdivs_opf = 0x4d,
212 fdivd_opf = 0x4e,
213
214 fcmps_opf = 0x51,
215 fcmpd_opf = 0x52,
216
217 fstox_opf = 0x81,
218 fdtox_opf = 0x82,
219 fxtos_opf = 0x84,
220 fxtod_opf = 0x88,
221 fitos_opf = 0xc4,
222 fdtos_opf = 0xc6,
223 fitod_opf = 0xc8,
224 fstod_opf = 0xc9,
225 fstoi_opf = 0xd1,
226 fdtoi_opf = 0xd2,
227
228 mdtox_opf = 0x110,
229 mstouw_opf = 0x111,
230 mstosw_opf = 0x113,
231 xmulx_opf = 0x115,
232 xmulxhi_opf = 0x116,
233 mxtod_opf = 0x118,
234 mwtos_opf = 0x119,
235
236 aes_kexpand0_opf = 0x130,
237 aes_kexpand2_opf = 0x131,
238
239 sha1_opf = 0x141,
240 sha256_opf = 0x142,
241 sha512_opf = 0x143,
242
243 crc32c_opf = 0x147
244 };
245
246 enum op5s {
247 aes_eround01_op5 = 0x00,
248 aes_eround23_op5 = 0x01,
249 aes_dround01_op5 = 0x02,
250 aes_dround23_op5 = 0x03,
251 aes_eround01_l_op5 = 0x04,
252 aes_eround23_l_op5 = 0x05,
253 aes_dround01_l_op5 = 0x06,
254 aes_dround23_l_op5 = 0x07,
255 aes_kexpand1_op5 = 0x08
256 };
257
258 enum RCondition { rc_z = 1, rc_lez = 2, rc_lz = 3, rc_nz = 5, rc_gz = 6, rc_gez = 7, rc_last = rc_gez };
259
260 enum Condition {
261 // for FBfcc & FBPfcc instruction
262 f_never = 0,
263 f_notEqual = 1,
264 f_notZero = 1,
265 f_lessOrGreater = 2,
266 f_unorderedOrLess = 3,
267 f_less = 4,
268 f_unorderedOrGreater = 5,
269 f_greater = 6,
270 f_unordered = 7,
271 f_always = 8,
272 f_equal = 9,
273 f_zero = 9,
274 f_unorderedOrEqual = 10,
275 f_greaterOrEqual = 11,
276 f_unorderedOrGreaterOrEqual = 12,
277 f_lessOrEqual = 13,
278 f_unorderedOrLessOrEqual = 14,
279 f_ordered = 15,
280
281 // V8 coproc, pp 123 v8 manual
282
283 cp_always = 8,
284 cp_never = 0,
285 cp_3 = 7,
286 cp_2 = 6,
287 cp_2or3 = 5,
288 cp_1 = 4,
289 cp_1or3 = 3,
290 cp_1or2 = 2,
291 cp_1or2or3 = 1,
292 cp_0 = 9,
293 cp_0or3 = 10,
294 cp_0or2 = 11,
295 cp_0or2or3 = 12,
296 cp_0or1 = 13,
297 cp_0or1or3 = 14,
298 cp_0or1or2 = 15,
299
300
301 // for integers
302
303 never = 0,
304 equal = 1,
305 zero = 1,
306 lessEqual = 2,
307 less = 3,
308 lessEqualUnsigned = 4,
309 lessUnsigned = 5,
310 carrySet = 5,
311 negative = 6,
312 overflowSet = 7,
313 always = 8,
314 notEqual = 9,
315 notZero = 9,
316 greater = 10,
317 greaterEqual = 11,
318 greaterUnsigned = 12,
319 greaterEqualUnsigned = 13,
320 carryClear = 13,
321 positive = 14,
322 overflowClear = 15
323 };
324
325 enum CC {
326 icc = 0, xcc = 2,
327 // ptr_cc is the correct condition code for a pointer or intptr_t:
328 ptr_cc = NOT_LP64(icc) LP64_ONLY(xcc),
329 fcc0 = 0, fcc1 = 1, fcc2 = 2, fcc3 = 3
330 };
331
332 enum PrefetchFcn {
333 severalReads = 0, oneRead = 1, severalWritesAndPossiblyReads = 2, oneWrite = 3, page = 4
334 };
335
336 public:
337 // Helper functions for groups of instructions
338
339 enum Predict { pt = 1, pn = 0 }; // pt = predict taken
340
341 enum Membar_mask_bits { // page 184, v9
342 StoreStore = 1 << 3,
343 LoadStore = 1 << 2,
344 StoreLoad = 1 << 1,
345 LoadLoad = 1 << 0,
346
347 Sync = 1 << 6,
348 MemIssue = 1 << 5,
349 Lookaside = 1 << 4
350 };
351
352 static bool is_in_wdisp_range(address a, address b, int nbits) {
353 intptr_t d = intptr_t(b) - intptr_t(a);
354 return is_simm(d, nbits + 2);
355 }
356
357 address target_distance(Label& L) {
358 // Assembler::target(L) should be called only when
359 // a branch instruction is emitted since non-bound
360 // labels record current pc() as a branch address.
361 if (L.is_bound()) return target(L);
362 // Return current address for non-bound labels.
363 return pc();
364 }
365
366 // test if label is in simm16 range in words (wdisp16).
367 bool is_in_wdisp16_range(Label& L) {
368 return is_in_wdisp_range(target_distance(L), pc(), 16);
369 }
370 // test if the distance between two addresses fits in simm30 range in words
371 static bool is_in_wdisp30_range(address a, address b) {
372 return is_in_wdisp_range(a, b, 30);
373 }
374
375 enum ASIs { // page 72, v9
376 ASI_PRIMARY = 0x80,
377 ASI_PRIMARY_NOFAULT = 0x82,
378 ASI_PRIMARY_LITTLE = 0x88,
379 // 8x8-bit partial store
380 ASI_PST8_PRIMARY = 0xC0,
381 // Block initializing store
382 ASI_ST_BLKINIT_PRIMARY = 0xE2,
383 // Most-Recently-Used (MRU) BIS variant
384 ASI_ST_BLKINIT_MRU_PRIMARY = 0xF2
385 // add more from book as needed
386 };
387
388 protected:
389 // helpers
390
391 // x is supposed to fit in a field "nbits" wide
392 // and be sign-extended. Check the range.
393
394 static void assert_signed_range(intptr_t x, int nbits) {
395 assert(nbits == 32 || (-(1 << nbits-1) <= x && x < ( 1 << nbits-1)),
396 "value out of range: x=" INTPTR_FORMAT ", nbits=%d", x, nbits);
397 }
398
399 static void assert_signed_word_disp_range(intptr_t x, int nbits) {
400 assert( (x & 3) == 0, "not word aligned");
401 assert_signed_range(x, nbits + 2);
402 }
403
404 static void assert_unsigned_const(int x, int nbits) {
405 assert( juint(x) < juint(1 << nbits), "unsigned constant out of range");
406 }
407
408 // fields: note bits numbered from LSB = 0,
409 // fields known by inclusive bit range
410
411 static int fmask(juint hi_bit, juint lo_bit) {
412 assert( hi_bit >= lo_bit && 0 <= lo_bit && hi_bit < 32, "bad bits");
413 return (1 << ( hi_bit-lo_bit + 1 )) - 1;
414 }
415
416 // inverse of u_field
417
418 static int inv_u_field(int x, int hi_bit, int lo_bit) {
419 juint r = juint(x) >> lo_bit;
420 r &= fmask( hi_bit, lo_bit);
421 return int(r);
422 }
423
424
425 // signed version: extract from field and sign-extend
426
427 static int inv_s_field(int x, int hi_bit, int lo_bit) {
428 int sign_shift = 31 - hi_bit;
429 return inv_u_field( ((x << sign_shift) >> sign_shift), hi_bit, lo_bit);
430 }
431
432 // given a field that ranges from hi_bit to lo_bit (inclusive,
433 // LSB = 0), and an unsigned value for the field,
434 // shift it into the field
435
436 #ifdef ASSERT
437 static int u_field(int x, int hi_bit, int lo_bit) {
438 assert( ( x & ~fmask(hi_bit, lo_bit)) == 0,
439 "value out of range");
440 int r = x << lo_bit;
441 assert( inv_u_field(r, hi_bit, lo_bit) == x, "just checking");
442 return r;
443 }
444 #else
445 // make sure this is inlined as it will reduce code size significantly
446 #define u_field(x, hi_bit, lo_bit) ((x) << (lo_bit))
447 #endif
448
449 static int inv_op( int x ) { return inv_u_field(x, 31, 30); }
450 static int inv_op2( int x ) { return inv_u_field(x, 24, 22); }
451 static int inv_op3( int x ) { return inv_u_field(x, 24, 19); }
452 static int inv_cond( int x ){ return inv_u_field(x, 28, 25); }
453
454 static bool inv_immed( int x ) { return (x & Assembler::immed(true)) != 0; }
455
456 static Register inv_rd( int x ) { return as_Register(inv_u_field(x, 29, 25)); }
457 static Register inv_rs1( int x ) { return as_Register(inv_u_field(x, 18, 14)); }
458 static Register inv_rs2( int x ) { return as_Register(inv_u_field(x, 4, 0)); }
459
460 static int op( int x) { return u_field(x, 31, 30); }
461 static int rd( Register r) { return u_field(r->encoding(), 29, 25); }
462 static int fcn( int x) { return u_field(x, 29, 25); }
463 static int op3( int x) { return u_field(x, 24, 19); }
464 static int rs1( Register r) { return u_field(r->encoding(), 18, 14); }
465 static int rs2( Register r) { return u_field(r->encoding(), 4, 0); }
466 static int annul( bool a) { return u_field(a ? 1 : 0, 29, 29); }
467 static int cond( int x) { return u_field(x, 28, 25); }
468 static int cond_mov( int x) { return u_field(x, 17, 14); }
469 static int rcond( RCondition x) { return u_field(x, 12, 10); }
470 static int op2( int x) { return u_field(x, 24, 22); }
471 static int predict( bool p) { return u_field(p ? 1 : 0, 19, 19); }
472 static int branchcc( CC fcca) { return u_field(fcca, 21, 20); }
473 static int cmpcc( CC fcca) { return u_field(fcca, 26, 25); }
474 static int imm_asi( int x) { return u_field(x, 12, 5); }
475 static int immed( bool i) { return u_field(i ? 1 : 0, 13, 13); }
476 static int opf_low6( int w) { return u_field(w, 10, 5); }
477 static int opf_low5( int w) { return u_field(w, 9, 5); }
478 static int op5( int x) { return u_field(x, 8, 5); }
479 static int trapcc( CC cc) { return u_field(cc, 12, 11); }
480 static int sx( int i) { return u_field(i, 12, 12); } // shift x=1 means 64-bit
481 static int opf( int x) { return u_field(x, 13, 5); }
482
483 static bool is_cbcond( int x ) {
484 return (VM_Version::has_cbcond() && (inv_cond(x) > rc_last) &&
485 inv_op(x) == branch_op && inv_op2(x) == bpr_op2);
486 }
487 static bool is_cxb( int x ) {
488 assert(is_cbcond(x), "wrong instruction");
489 return (x & (1<<21)) != 0;
490 }
491 static int cond_cbcond( int x) { return u_field((((x & 8)<<1) + 8 + (x & 7)), 29, 25); }
492 static int inv_cond_cbcond(int x) {
493 assert(is_cbcond(x), "wrong instruction");
494 return inv_u_field(x, 27, 25) | (inv_u_field(x, 29, 29)<<3);
495 }
496
497 static int opf_cc( CC c, bool useFloat ) { return u_field((useFloat ? 0 : 4) + c, 13, 11); }
498 static int mov_cc( CC c, bool useFloat ) { return u_field(useFloat ? 0 : 1, 18, 18) | u_field(c, 12, 11); }
499
500 static int fd( FloatRegister r, FloatRegisterImpl::Width fwa) { return u_field(r->encoding(fwa), 29, 25); };
501 static int fs1(FloatRegister r, FloatRegisterImpl::Width fwa) { return u_field(r->encoding(fwa), 18, 14); };
502 static int fs2(FloatRegister r, FloatRegisterImpl::Width fwa) { return u_field(r->encoding(fwa), 4, 0); };
503 static int fs3(FloatRegister r, FloatRegisterImpl::Width fwa) { return u_field(r->encoding(fwa), 13, 9); };
504
505 // some float instructions use this encoding on the op3 field
506 static int alt_op3(int op, FloatRegisterImpl::Width w) {
507 int r;
508 switch(w) {
509 case FloatRegisterImpl::S: r = op + 0; break;
510 case FloatRegisterImpl::D: r = op + 3; break;
511 case FloatRegisterImpl::Q: r = op + 2; break;
512 default: ShouldNotReachHere(); break;
513 }
514 return op3(r);
515 }
516
517
518 // compute inverse of simm
519 static int inv_simm(int x, int nbits) {
520 return (int)(x << (32 - nbits)) >> (32 - nbits);
521 }
522
523 static int inv_simm13( int x ) { return inv_simm(x, 13); }
524
525 // signed immediate, in low bits, nbits long
526 static int simm(int x, int nbits) {
527 assert_signed_range(x, nbits);
528 return x & (( 1 << nbits ) - 1);
529 }
530
531 // compute inverse of wdisp16
532 static intptr_t inv_wdisp16(int x, intptr_t pos) {
533 int lo = x & (( 1 << 14 ) - 1);
534 int hi = (x >> 20) & 3;
535 if (hi >= 2) hi |= ~1;
536 return (((hi << 14) | lo) << 2) + pos;
537 }
538
539 // word offset, 14 bits at LSend, 2 bits at B21, B20
540 static int wdisp16(intptr_t x, intptr_t off) {
541 intptr_t xx = x - off;
542 assert_signed_word_disp_range(xx, 16);
543 int r = (xx >> 2) & ((1 << 14) - 1)
544 | ( ( (xx>>(2+14)) & 3 ) << 20 );
545 assert( inv_wdisp16(r, off) == x, "inverse is not inverse");
546 return r;
547 }
548
549 // compute inverse of wdisp10
550 static intptr_t inv_wdisp10(int x, intptr_t pos) {
551 assert(is_cbcond(x), "wrong instruction");
552 int lo = inv_u_field(x, 12, 5);
553 int hi = (x >> 19) & 3;
554 if (hi >= 2) hi |= ~1;
555 return (((hi << 8) | lo) << 2) + pos;
556 }
557
558 // word offset for cbcond, 8 bits at [B12,B5], 2 bits at [B20,B19]
559 static int wdisp10(intptr_t x, intptr_t off) {
560 assert(VM_Version::has_cbcond(), "This CPU does not have CBCOND instruction");
561 intptr_t xx = x - off;
562 assert_signed_word_disp_range(xx, 10);
563 int r = ( ( (xx >> 2 ) & ((1 << 8) - 1) ) << 5 )
564 | ( ( (xx >> (2+8)) & 3 ) << 19 );
565 // Have to fake cbcond instruction to pass assert in inv_wdisp10()
566 assert(inv_wdisp10((r | op(branch_op) | cond_cbcond(rc_last+1) | op2(bpr_op2)), off) == x, "inverse is not inverse");
567 return r;
568 }
569
570 // word displacement in low-order nbits bits
571
572 static intptr_t inv_wdisp( int x, intptr_t pos, int nbits ) {
573 int pre_sign_extend = x & (( 1 << nbits ) - 1);
574 int r = pre_sign_extend >= ( 1 << (nbits-1) )
575 ? pre_sign_extend | ~(( 1 << nbits ) - 1)
576 : pre_sign_extend;
577 return (r << 2) + pos;
578 }
579
580 static int wdisp( intptr_t x, intptr_t off, int nbits ) {
581 intptr_t xx = x - off;
582 assert_signed_word_disp_range(xx, nbits);
583 int r = (xx >> 2) & (( 1 << nbits ) - 1);
584 assert( inv_wdisp( r, off, nbits ) == x, "inverse not inverse");
585 return r;
586 }
587
588
589 // Extract the top 32 bits in a 64 bit word
590 static int32_t hi32( int64_t x ) {
591 int32_t r = int32_t( (uint64_t)x >> 32 );
592 return r;
593 }
594
595 // given a sethi instruction, extract the constant, left-justified
596 static int inv_hi22( int x ) {
597 return x << 10;
598 }
599
600 // create an imm22 field, given a 32-bit left-justified constant
601 static int hi22( int x ) {
602 int r = int( juint(x) >> 10 );
603 assert( (r & ~((1 << 22) - 1)) == 0, "just checkin'");
604 return r;
605 }
606
607 // create a low10 __value__ (not a field) for a given a 32-bit constant
608 static int low10( int x ) {
609 return x & ((1 << 10) - 1);
610 }
611
612 // create a low12 __value__ (not a field) for a given a 32-bit constant
613 static int low12( int x ) {
614 return x & ((1 << 12) - 1);
615 }
616
617 // AES crypto instructions supported only on certain processors
618 static void aes_only() { assert( VM_Version::has_aes(), "This instruction only works on SPARC with AES instructions support"); }
619
620 // SHA crypto instructions supported only on certain processors
621 static void sha1_only() { assert( VM_Version::has_sha1(), "This instruction only works on SPARC with SHA1"); }
622 static void sha256_only() { assert( VM_Version::has_sha256(), "This instruction only works on SPARC with SHA256"); }
623 static void sha512_only() { assert( VM_Version::has_sha512(), "This instruction only works on SPARC with SHA512"); }
624
625 // CRC32C instruction supported only on certain processors
626 static void crc32c_only() { assert( VM_Version::has_crc32c(), "This instruction only works on SPARC with CRC32C"); }
627
628 // instruction only in VIS1
629 static void vis1_only() { assert( VM_Version::has_vis1(), "This instruction only works on SPARC with VIS1"); }
630
631 // instruction only in VIS2
632 static void vis2_only() { assert( VM_Version::has_vis2(), "This instruction only works on SPARC with VIS2"); }
633
634 // instruction only in VIS3
635 static void vis3_only() { assert( VM_Version::has_vis3(), "This instruction only works on SPARC with VIS3"); }
636
637 // instruction only in v9
638 static void v9_only() { } // do nothing
639
640 // instruction deprecated in v9
641 static void v9_dep() { } // do nothing for now
642
643 // v8 has no CC field
644 static void v8_no_cc(CC cc) { if (cc) v9_only(); }
645
646 protected:
647 // Simple delay-slot scheme:
648 // In order to check the programmer, the assembler keeps track of deley slots.
649 // It forbids CTIs in delay slots (conservative, but should be OK).
650 // Also, when putting an instruction into a delay slot, you must say
651 // asm->delayed()->add(...), in order to check that you don't omit
652 // delay-slot instructions.
653 // To implement this, we use a simple FSA
654
655 #ifdef ASSERT
656 #define CHECK_DELAY
657 #endif
658 #ifdef CHECK_DELAY
659 enum Delay_state { no_delay, at_delay_slot, filling_delay_slot } delay_state;
660 #endif
661
662 public:
663 // Tells assembler next instruction must NOT be in delay slot.
664 // Use at start of multinstruction macros.
665 void assert_not_delayed() {
666 // This is a separate overloading to avoid creation of string constants
667 // in non-asserted code--with some compilers this pollutes the object code.
668 #ifdef CHECK_DELAY
669 assert_not_delayed("next instruction should not be a delay slot");
670 #endif
671 }
672 void assert_not_delayed(const char* msg) {
673 #ifdef CHECK_DELAY
674 assert(delay_state == no_delay, msg);
675 #endif
676 }
677
678 protected:
679 // Insert a nop if the previous is cbcond
680 inline void insert_nop_after_cbcond();
681
682 // Delay slot helpers
683 // cti is called when emitting control-transfer instruction,
684 // BEFORE doing the emitting.
685 // Only effective when assertion-checking is enabled.
686 void cti() {
687 // A cbcond instruction immediately followed by a CTI
688 // instruction introduces pipeline stalls, we need to avoid that.
689 no_cbcond_before();
690 #ifdef CHECK_DELAY
691 assert_not_delayed("cti should not be in delay slot");
692 #endif
693 }
694
695 // called when emitting cti with a delay slot, AFTER emitting
696 void has_delay_slot() {
697 #ifdef CHECK_DELAY
698 assert_not_delayed("just checking");
699 delay_state = at_delay_slot;
700 #endif
701 }
702
703 // cbcond instruction should not be generated one after an other
704 bool cbcond_before() {
705 if (offset() == 0) return false; // it is first instruction
706 int x = *(int*)(intptr_t(pc()) - 4); // previous instruction
707 return is_cbcond(x);
708 }
709
710 void no_cbcond_before() {
711 assert(offset() == 0 || !cbcond_before(), "cbcond should not follow an other cbcond");
712 }
713 public:
714
715 bool use_cbcond(Label& L) {
716 if (!UseCBCond || cbcond_before()) return false;
717 intptr_t x = intptr_t(target_distance(L)) - intptr_t(pc());
718 assert( (x & 3) == 0, "not word aligned");
719 return is_simm12(x);
720 }
721
722 // Tells assembler you know that next instruction is delayed
723 Assembler* delayed() {
724 #ifdef CHECK_DELAY
725 assert ( delay_state == at_delay_slot, "delayed instruction is not in delay slot");
726 delay_state = filling_delay_slot;
727 #endif
728 return this;
729 }
730
731 void flush() {
732 #ifdef CHECK_DELAY
733 assert ( delay_state == no_delay, "ending code with a delay slot");
734 #endif
735 AbstractAssembler::flush();
736 }
737
738 inline void emit_int32(int); // shadows AbstractAssembler::emit_int32
739 inline void emit_data(int x);
740 inline void emit_data(int, RelocationHolder const&);
741 inline void emit_data(int, relocInfo::relocType rtype);
742 // helper for above fcns
743 inline void check_delay();
744
745
746 public:
747 // instructions, refer to page numbers in the SPARC Architecture Manual, V9
748
749 // pp 135 (addc was addx in v8)
750
751 inline void add(Register s1, Register s2, Register d );
752 inline void add(Register s1, int simm13a, Register d );
753
754 inline void addcc( Register s1, Register s2, Register d );
755 inline void addcc( Register s1, int simm13a, Register d );
756 inline void addc( Register s1, Register s2, Register d );
757 inline void addc( Register s1, int simm13a, Register d );
758 inline void addccc( Register s1, Register s2, Register d );
759 inline void addccc( Register s1, int simm13a, Register d );
760
761
762 // 4-operand AES instructions
763
764 inline void aes_eround01( FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d );
765 inline void aes_eround23( FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d );
766 inline void aes_dround01( FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d );
767 inline void aes_dround23( FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d );
768 inline void aes_eround01_l( FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d );
769 inline void aes_eround23_l( FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d );
770 inline void aes_dround01_l( FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d );
771 inline void aes_dround23_l( FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d );
772 inline void aes_kexpand1( FloatRegister s1, FloatRegister s2, int imm5a, FloatRegister d );
773
774
775 // 3-operand AES instructions
776
777 inline void aes_kexpand0( FloatRegister s1, FloatRegister s2, FloatRegister d );
778 inline void aes_kexpand2( FloatRegister s1, FloatRegister s2, FloatRegister d );
779
780 // pp 136
781
782 inline void bpr(RCondition c, bool a, Predict p, Register s1, address d, relocInfo::relocType rt = relocInfo::none);
783 inline void bpr(RCondition c, bool a, Predict p, Register s1, Label& L);
784
785 // compare and branch
786 inline void cbcond(Condition c, CC cc, Register s1, Register s2, Label& L);
787 inline void cbcond(Condition c, CC cc, Register s1, int simm5, Label& L);
788
789 protected: // use MacroAssembler::br instead
790
791 // pp 138
792
793 inline void fb( Condition c, bool a, address d, relocInfo::relocType rt = relocInfo::none );
794 inline void fb( Condition c, bool a, Label& L );
795
796 // pp 141
797
798 inline void fbp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt = relocInfo::none );
799 inline void fbp( Condition c, bool a, CC cc, Predict p, Label& L );
800
801 // pp 144
802
803 inline void br( Condition c, bool a, address d, relocInfo::relocType rt = relocInfo::none );
804 inline void br( Condition c, bool a, Label& L );
805
806 // pp 146
807
808 inline void bp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt = relocInfo::none );
809 inline void bp( Condition c, bool a, CC cc, Predict p, Label& L );
810
811 // pp 149
812
813 inline void call( address d, relocInfo::relocType rt = relocInfo::runtime_call_type );
814 inline void call( Label& L, relocInfo::relocType rt = relocInfo::runtime_call_type );
815
816 inline void call( address d, RelocationHolder const& rspec );
817
818 public:
819
820 // pp 150
821
822 // These instructions compare the contents of s2 with the contents of
823 // memory at address in s1. If the values are equal, the contents of memory
824 // at address s1 is swapped with the data in d. If the values are not equal,
825 // the the contents of memory at s1 is loaded into d, without the swap.
826
827 inline void casa( Register s1, Register s2, Register d, int ia = -1 );
828 inline void casxa( Register s1, Register s2, Register d, int ia = -1 );
829
830 // pp 152
831
832 inline void udiv( Register s1, Register s2, Register d );
833 inline void udiv( Register s1, int simm13a, Register d );
834 inline void sdiv( Register s1, Register s2, Register d );
835 inline void sdiv( Register s1, int simm13a, Register d );
836 inline void udivcc( Register s1, Register s2, Register d );
837 inline void udivcc( Register s1, int simm13a, Register d );
838 inline void sdivcc( Register s1, Register s2, Register d );
839 inline void sdivcc( Register s1, int simm13a, Register d );
840
841 // pp 155
842
843 inline void done();
844 inline void retry();
845
846 // pp 156
847
848 inline void fadd( FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d );
849 inline void fsub( FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d );
850
851 // pp 157
852
853 inline void fcmp( FloatRegisterImpl::Width w, CC cc, FloatRegister s1, FloatRegister s2);
854 inline void fcmpe( FloatRegisterImpl::Width w, CC cc, FloatRegister s1, FloatRegister s2);
855
856 // pp 159
857
858 inline void ftox( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d );
859 inline void ftoi( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d );
860
861 // pp 160
862
863 inline void ftof( FloatRegisterImpl::Width sw, FloatRegisterImpl::Width dw, FloatRegister s, FloatRegister d );
864
865 // pp 161
866
867 inline void fxtof( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d );
868 inline void fitof( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d );
869
870 // pp 162
871
872 inline void fmov( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d );
873
874 inline void fneg( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d );
875
876 inline void fabs( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d );
877
878 // pp 163
879
880 inline void fmul( FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d );
881 inline void fmul( FloatRegisterImpl::Width sw, FloatRegisterImpl::Width dw, FloatRegister s1, FloatRegister s2, FloatRegister d );
882 inline void fdiv( FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d );
883
884 // FXORs/FXORd instructions
885
886 inline void fxor( FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d );
887
888 // pp 164
889
890 inline void fsqrt( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d );
891
892 // pp 165
893
894 inline void flush( Register s1, Register s2 );
895 inline void flush( Register s1, int simm13a);
896
897 // pp 167
898
899 void flushw();
900
901 // pp 168
902
903 void illtrap( int const22a);
904 // v8 unimp == illtrap(0)
905
906 // pp 169
907
908 void impdep1( int id1, int const19a );
909 void impdep2( int id1, int const19a );
910
911 // pp 170
912
913 void jmpl( Register s1, Register s2, Register d );
914 void jmpl( Register s1, int simm13a, Register d, RelocationHolder const& rspec = RelocationHolder() );
915
916 // 171
917
918 inline void ldf(FloatRegisterImpl::Width w, Register s1, Register s2, FloatRegister d);
919 inline void ldf(FloatRegisterImpl::Width w, Register s1, int simm13a, FloatRegister d, RelocationHolder const& rspec = RelocationHolder());
920
921
922 inline void ldfsr( Register s1, Register s2 );
923 inline void ldfsr( Register s1, int simm13a);
924 inline void ldxfsr( Register s1, Register s2 );
925 inline void ldxfsr( Register s1, int simm13a);
926
927 // 173
928
929 inline void ldfa( FloatRegisterImpl::Width w, Register s1, Register s2, int ia, FloatRegister d );
930 inline void ldfa( FloatRegisterImpl::Width w, Register s1, int simm13a, FloatRegister d );
931
932 // pp 175, lduw is ld on v8
933
934 inline void ldsb( Register s1, Register s2, Register d );
935 inline void ldsb( Register s1, int simm13a, Register d);
936 inline void ldsh( Register s1, Register s2, Register d );
937 inline void ldsh( Register s1, int simm13a, Register d);
938 inline void ldsw( Register s1, Register s2, Register d );
939 inline void ldsw( Register s1, int simm13a, Register d);
940 inline void ldub( Register s1, Register s2, Register d );
941 inline void ldub( Register s1, int simm13a, Register d);
942 inline void lduh( Register s1, Register s2, Register d );
943 inline void lduh( Register s1, int simm13a, Register d);
944 inline void lduw( Register s1, Register s2, Register d );
945 inline void lduw( Register s1, int simm13a, Register d);
946 inline void ldx( Register s1, Register s2, Register d );
947 inline void ldx( Register s1, int simm13a, Register d);
948 inline void ldd( Register s1, Register s2, Register d );
949 inline void ldd( Register s1, int simm13a, Register d);
950
951 // pp 177
952
953 inline void ldsba( Register s1, Register s2, int ia, Register d );
954 inline void ldsba( Register s1, int simm13a, Register d );
955 inline void ldsha( Register s1, Register s2, int ia, Register d );
956 inline void ldsha( Register s1, int simm13a, Register d );
957 inline void ldswa( Register s1, Register s2, int ia, Register d );
958 inline void ldswa( Register s1, int simm13a, Register d );
959 inline void lduba( Register s1, Register s2, int ia, Register d );
960 inline void lduba( Register s1, int simm13a, Register d );
961 inline void lduha( Register s1, Register s2, int ia, Register d );
962 inline void lduha( Register s1, int simm13a, Register d );
963 inline void lduwa( Register s1, Register s2, int ia, Register d );
964 inline void lduwa( Register s1, int simm13a, Register d );
965 inline void ldxa( Register s1, Register s2, int ia, Register d );
966 inline void ldxa( Register s1, int simm13a, Register d );
967
968 // pp 181
969
970 inline void and3( Register s1, Register s2, Register d );
971 inline void and3( Register s1, int simm13a, Register d );
972 inline void andcc( Register s1, Register s2, Register d );
973 inline void andcc( Register s1, int simm13a, Register d );
974 inline void andn( Register s1, Register s2, Register d );
975 inline void andn( Register s1, int simm13a, Register d );
976 inline void andncc( Register s1, Register s2, Register d );
977 inline void andncc( Register s1, int simm13a, Register d );
978 inline void or3( Register s1, Register s2, Register d );
979 inline void or3( Register s1, int simm13a, Register d );
980 inline void orcc( Register s1, Register s2, Register d );
981 inline void orcc( Register s1, int simm13a, Register d );
982 inline void orn( Register s1, Register s2, Register d );
983 inline void orn( Register s1, int simm13a, Register d );
984 inline void orncc( Register s1, Register s2, Register d );
985 inline void orncc( Register s1, int simm13a, Register d );
986 inline void xor3( Register s1, Register s2, Register d );
987 inline void xor3( Register s1, int simm13a, Register d );
988 inline void xorcc( Register s1, Register s2, Register d );
989 inline void xorcc( Register s1, int simm13a, Register d );
990 inline void xnor( Register s1, Register s2, Register d );
991 inline void xnor( Register s1, int simm13a, Register d );
992 inline void xnorcc( Register s1, Register s2, Register d );
993 inline void xnorcc( Register s1, int simm13a, Register d );
994
995 // pp 183
996
997 inline void membar( Membar_mask_bits const7a );
998
999 // pp 185
1000
1001 inline void fmov( FloatRegisterImpl::Width w, Condition c, bool floatCC, CC cca, FloatRegister s2, FloatRegister d );
1002
1003 // pp 189
1004
1005 inline void fmov( FloatRegisterImpl::Width w, RCondition c, Register s1, FloatRegister s2, FloatRegister d );
1006
1007 // pp 191
1008
1009 inline void movcc( Condition c, bool floatCC, CC cca, Register s2, Register d );
1010 inline void movcc( Condition c, bool floatCC, CC cca, int simm11a, Register d );
1011
1012 // pp 195
1013
1014 inline void movr( RCondition c, Register s1, Register s2, Register d );
1015 inline void movr( RCondition c, Register s1, int simm10a, Register d );
1016
1017 // pp 196
1018
1019 inline void mulx( Register s1, Register s2, Register d );
1020 inline void mulx( Register s1, int simm13a, Register d );
1021 inline void sdivx( Register s1, Register s2, Register d );
1022 inline void sdivx( Register s1, int simm13a, Register d );
1023 inline void udivx( Register s1, Register s2, Register d );
1024 inline void udivx( Register s1, int simm13a, Register d );
1025
1026 // pp 197
1027
1028 inline void umul( Register s1, Register s2, Register d );
1029 inline void umul( Register s1, int simm13a, Register d );
1030 inline void smul( Register s1, Register s2, Register d );
1031 inline void smul( Register s1, int simm13a, Register d );
1032 inline void umulcc( Register s1, Register s2, Register d );
1033 inline void umulcc( Register s1, int simm13a, Register d );
1034 inline void smulcc( Register s1, Register s2, Register d );
1035 inline void smulcc( Register s1, int simm13a, Register d );
1036
1037 // pp 201
1038
1039 inline void nop();
1040
1041 inline void sw_count();
1042
1043 // pp 202
1044
1045 inline void popc( Register s, Register d);
1046 inline void popc( int simm13a, Register d);
1047
1048 // pp 203
1049
1050 inline void prefetch( Register s1, Register s2, PrefetchFcn f);
1051 inline void prefetch( Register s1, int simm13a, PrefetchFcn f);
1052
1053 inline void prefetcha( Register s1, Register s2, int ia, PrefetchFcn f );
1054 inline void prefetcha( Register s1, int simm13a, PrefetchFcn f );
1055
1056 // pp 208
1057
1058 // not implementing read privileged register
1059
1060 inline void rdy( Register d);
1061 inline void rdccr( Register d);
1062 inline void rdasi( Register d);
1063 inline void rdtick( Register d);
1064 inline void rdpc( Register d);
1065 inline void rdfprs( Register d);
1066
1067 // pp 213
1068
1069 inline void rett( Register s1, Register s2);
1070 inline void rett( Register s1, int simm13a, relocInfo::relocType rt = relocInfo::none);
1071
1072 // pp 214
1073
1074 inline void save( Register s1, Register s2, Register d );
1075 inline void save( Register s1, int simm13a, Register d );
1076
1077 inline void restore( Register s1 = G0, Register s2 = G0, Register d = G0 );
1078 inline void restore( Register s1, int simm13a, Register d );
1079
1080 // pp 216
1081
1082 inline void saved();
1083 inline void restored();
1084
1085 // pp 217
1086
1087 inline void sethi( int imm22a, Register d, RelocationHolder const& rspec = RelocationHolder() );
1088 // pp 218
1089
1090 inline void sll( Register s1, Register s2, Register d );
1091 inline void sll( Register s1, int imm5a, Register d );
1092 inline void srl( Register s1, Register s2, Register d );
1093 inline void srl( Register s1, int imm5a, Register d );
1094 inline void sra( Register s1, Register s2, Register d );
1095 inline void sra( Register s1, int imm5a, Register d );
1096
1097 inline void sllx( Register s1, Register s2, Register d );
1098 inline void sllx( Register s1, int imm6a, Register d );
1099 inline void srlx( Register s1, Register s2, Register d );
1100 inline void srlx( Register s1, int imm6a, Register d );
1101 inline void srax( Register s1, Register s2, Register d );
1102 inline void srax( Register s1, int imm6a, Register d );
1103
1104 // pp 220
1105
1106 inline void sir( int simm13a );
1107
1108 // pp 221
1109
1110 inline void stbar();
1111
1112 // pp 222
1113
1114 inline void stf( FloatRegisterImpl::Width w, FloatRegister d, Register s1, Register s2);
1115 inline void stf( FloatRegisterImpl::Width w, FloatRegister d, Register s1, int simm13a);
1116
1117 inline void stfsr( Register s1, Register s2 );
1118 inline void stfsr( Register s1, int simm13a);
1119 inline void stxfsr( Register s1, Register s2 );
1120 inline void stxfsr( Register s1, int simm13a);
1121
1122 // pp 224
1123
1124 inline void stfa( FloatRegisterImpl::Width w, FloatRegister d, Register s1, Register s2, int ia );
1125 inline void stfa( FloatRegisterImpl::Width w, FloatRegister d, Register s1, int simm13a );
1126
1127 // p 226
1128
1129 inline void stb( Register d, Register s1, Register s2 );
1130 inline void stb( Register d, Register s1, int simm13a);
1131 inline void sth( Register d, Register s1, Register s2 );
1132 inline void sth( Register d, Register s1, int simm13a);
1133 inline void stw( Register d, Register s1, Register s2 );
1134 inline void stw( Register d, Register s1, int simm13a);
1135 inline void stx( Register d, Register s1, Register s2 );
1136 inline void stx( Register d, Register s1, int simm13a);
1137 inline void std( Register d, Register s1, Register s2 );
1138 inline void std( Register d, Register s1, int simm13a);
1139
1140 // pp 177
1141
1142 inline void stba( Register d, Register s1, Register s2, int ia );
1143 inline void stba( Register d, Register s1, int simm13a );
1144 inline void stha( Register d, Register s1, Register s2, int ia );
1145 inline void stha( Register d, Register s1, int simm13a );
1146 inline void stwa( Register d, Register s1, Register s2, int ia );
1147 inline void stwa( Register d, Register s1, int simm13a );
1148 inline void stxa( Register d, Register s1, Register s2, int ia );
1149 inline void stxa( Register d, Register s1, int simm13a );
1150 inline void stda( Register d, Register s1, Register s2, int ia );
1151 inline void stda( Register d, Register s1, int simm13a );
1152
1153 // pp 230
1154
1155 inline void sub( Register s1, Register s2, Register d );
1156 inline void sub( Register s1, int simm13a, Register d );
1157
1158 inline void subcc( Register s1, Register s2, Register d );
1159 inline void subcc( Register s1, int simm13a, Register d );
1160 inline void subc( Register s1, Register s2, Register d );
1161 inline void subc( Register s1, int simm13a, Register d );
1162 inline void subccc( Register s1, Register s2, Register d );
1163 inline void subccc( Register s1, int simm13a, Register d );
1164
1165 // pp 231
1166
1167 inline void swap( Register s1, Register s2, Register d );
1168 inline void swap( Register s1, int simm13a, Register d);
1169
1170 // pp 232
1171
1172 inline void swapa( Register s1, Register s2, int ia, Register d );
1173 inline void swapa( Register s1, int simm13a, Register d );
1174
1175 // pp 234, note op in book is wrong, see pp 268
1176
1177 inline void taddcc( Register s1, Register s2, Register d );
1178 inline void taddcc( Register s1, int simm13a, Register d );
1179
1180 // pp 235
1181
1182 inline void tsubcc( Register s1, Register s2, Register d );
1183 inline void tsubcc( Register s1, int simm13a, Register d );
1184
1185 // pp 237
1186
1187 inline void trap( Condition c, CC cc, Register s1, Register s2 );
1188 inline void trap( Condition c, CC cc, Register s1, int trapa );
1189 // simple uncond. trap
1190 inline void trap( int trapa );
1191
1192 // pp 239 omit write priv register for now
1193
1194 inline void wry( Register d);
1195 inline void wrccr(Register s);
1196 inline void wrccr(Register s, int simm13a);
1197 inline void wrasi(Register d);
1198 // wrasi(d, imm) stores (d xor imm) to asi
1199 inline void wrasi(Register d, int simm13a);
1200 inline void wrfprs( Register d);
1201
1202 // VIS1 instructions
1203
1204 inline void alignaddr( Register s1, Register s2, Register d );
1205
1206 inline void faligndata( FloatRegister s1, FloatRegister s2, FloatRegister d );
1207
1208 inline void fzero( FloatRegisterImpl::Width w, FloatRegister d );
1209
1210 inline void fsrc2( FloatRegisterImpl::Width w, FloatRegister s2, FloatRegister d );
1211
1212 inline void fnot1( FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister d );
1213
1214 inline void fpmerge( FloatRegister s1, FloatRegister s2, FloatRegister d );
1215
1216 inline void stpartialf( Register s1, Register s2, FloatRegister d, int ia = -1 );
1217
1218 // VIS2 instructions
1219
1220 inline void edge8n( Register s1, Register s2, Register d );
1221
1222 inline void bmask( Register s1, Register s2, Register d );
1223 inline void bshuffle( FloatRegister s1, FloatRegister s2, FloatRegister d );
1224
1225 // VIS3 instructions
1226
1227 inline void movstosw( FloatRegister s, Register d );
1228 inline void movstouw( FloatRegister s, Register d );
1229 inline void movdtox( FloatRegister s, Register d );
1230
1231 inline void movwtos( Register s, FloatRegister d );
1232 inline void movxtod( Register s, FloatRegister d );
1233
1234 inline void xmulx(Register s1, Register s2, Register d);
1235 inline void xmulxhi(Register s1, Register s2, Register d);
1236
1237 // Crypto SHA instructions
1238
1239 inline void sha1();
1240 inline void sha256();
1241 inline void sha512();
1242
1243 // CRC32C instruction
1244
1245 inline void crc32c( FloatRegister s1, FloatRegister s2, FloatRegister d );
1246
1247 // Creation
1248 Assembler(CodeBuffer* code) : AbstractAssembler(code) {
1249 #ifdef CHECK_DELAY
1250 delay_state = no_delay;
1251 #endif
1252 }
1253 };
1254
1255 #endif // CPU_SPARC_VM_ASSEMBLER_SPARC_HPP