1 /*
2 * Copyright (c) 1997, 2015, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
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23 */
24
25 #ifndef CPU_SPARC_VM_ASSEMBLER_SPARC_HPP
26 #define CPU_SPARC_VM_ASSEMBLER_SPARC_HPP
27
28 #include "asm/register.hpp"
29
30 // The SPARC Assembler: Pure assembler doing NO optimizations on the instruction
31 // level; i.e., what you write
32 // is what you get. The Assembler is generating code into a CodeBuffer.
33
34 class Assembler : public AbstractAssembler {
35 friend class AbstractAssembler;
36 friend class AddressLiteral;
37
38 // code patchers need various routines like inv_wdisp()
39 friend class NativeInstruction;
40 friend class NativeGeneralJump;
41 friend class Relocation;
42 friend class Label;
43
44 public:
45 // op carries format info; see page 62 & 267
46
47 enum ops {
48 call_op = 1, // fmt 1
49 branch_op = 0, // also sethi (fmt2)
50 arith_op = 2, // fmt 3, arith & misc
51 ldst_op = 3 // fmt 3, load/store
52 };
53
54 enum op2s {
55 bpr_op2 = 3,
56 fb_op2 = 6,
57 fbp_op2 = 5,
58 br_op2 = 2,
59 bp_op2 = 1,
60 sethi_op2 = 4
61 };
62
63 enum op3s {
64 // selected op3s
65 add_op3 = 0x00,
66 and_op3 = 0x01,
67 or_op3 = 0x02,
68 xor_op3 = 0x03,
69 sub_op3 = 0x04,
70 andn_op3 = 0x05,
71 orn_op3 = 0x06,
72 xnor_op3 = 0x07,
73 addc_op3 = 0x08,
74 mulx_op3 = 0x09,
75 umul_op3 = 0x0a,
76 smul_op3 = 0x0b,
77 subc_op3 = 0x0c,
78 udivx_op3 = 0x0d,
79 udiv_op3 = 0x0e,
80 sdiv_op3 = 0x0f,
81
82 addcc_op3 = 0x10,
83 andcc_op3 = 0x11,
84 orcc_op3 = 0x12,
85 xorcc_op3 = 0x13,
86 subcc_op3 = 0x14,
87 andncc_op3 = 0x15,
88 orncc_op3 = 0x16,
89 xnorcc_op3 = 0x17,
90 addccc_op3 = 0x18,
91 aes4_op3 = 0x19,
92 umulcc_op3 = 0x1a,
93 smulcc_op3 = 0x1b,
94 subccc_op3 = 0x1c,
95 udivcc_op3 = 0x1e,
96 sdivcc_op3 = 0x1f,
97
98 taddcc_op3 = 0x20,
99 tsubcc_op3 = 0x21,
100 taddcctv_op3 = 0x22,
101 tsubcctv_op3 = 0x23,
102 mulscc_op3 = 0x24,
103 sll_op3 = 0x25,
104 sllx_op3 = 0x25,
105 srl_op3 = 0x26,
106 srlx_op3 = 0x26,
107 sra_op3 = 0x27,
108 srax_op3 = 0x27,
109 rdreg_op3 = 0x28,
110 membar_op3 = 0x28,
111
112 flushw_op3 = 0x2b,
113 movcc_op3 = 0x2c,
114 sdivx_op3 = 0x2d,
115 popc_op3 = 0x2e,
116 movr_op3 = 0x2f,
117
118 sir_op3 = 0x30,
119 wrreg_op3 = 0x30,
120 saved_op3 = 0x31,
121
122 fpop1_op3 = 0x34,
123 fpop2_op3 = 0x35,
124 impdep1_op3 = 0x36,
125 aes3_op3 = 0x36,
126 sha_op3 = 0x36,
127 bmask_op3 = 0x36,
128 bshuffle_op3 = 0x36,
129 alignaddr_op3 = 0x36,
130 faligndata_op3 = 0x36,
131 flog3_op3 = 0x36,
132 edge_op3 = 0x36,
133 fzero_op3 = 0x36,
134 fsrc_op3 = 0x36,
135 fnot_op3 = 0x36,
136 lzcnt_op3 = 0x36,
137 xmulx_op3 = 0x36,
138 crc32c_op3 = 0x36,
139 impdep2_op3 = 0x37,
140 stpartialf_op3 = 0x37,
141 jmpl_op3 = 0x38,
142 rett_op3 = 0x39,
143 trap_op3 = 0x3a,
144 flush_op3 = 0x3b,
145 save_op3 = 0x3c,
146 restore_op3 = 0x3d,
147 done_op3 = 0x3e,
148 retry_op3 = 0x3e,
149
150 lduw_op3 = 0x00,
151 ldub_op3 = 0x01,
152 lduh_op3 = 0x02,
153 ldd_op3 = 0x03,
154 stw_op3 = 0x04,
155 stb_op3 = 0x05,
156 sth_op3 = 0x06,
157 std_op3 = 0x07,
158 ldsw_op3 = 0x08,
159 ldsb_op3 = 0x09,
160 ldsh_op3 = 0x0a,
161 ldx_op3 = 0x0b,
162
163 stx_op3 = 0x0e,
164 swap_op3 = 0x0f,
165
166 stwa_op3 = 0x14,
167 stxa_op3 = 0x1e,
168
169 ldf_op3 = 0x20,
170 ldfsr_op3 = 0x21,
171 ldqf_op3 = 0x22,
172 lddf_op3 = 0x23,
173 stf_op3 = 0x24,
174 stfsr_op3 = 0x25,
175 stqf_op3 = 0x26,
176 stdf_op3 = 0x27,
177
178 prefetch_op3 = 0x2d,
179
180 casa_op3 = 0x3c,
181 casxa_op3 = 0x3e,
182
183 mftoi_op3 = 0x36,
184
185 alt_bit_op3 = 0x10,
186 cc_bit_op3 = 0x10
187 };
188
189 enum opfs {
190 // selected opfs
191 edge8n_opf = 0x01,
192
193 fmovs_opf = 0x01,
194 fmovd_opf = 0x02,
195
196 fnegs_opf = 0x05,
197 fnegd_opf = 0x06,
198
199 lzcnt_opf = 0x17,
200 alignaddr_opf = 0x18,
201 bmask_opf = 0x19,
202
203 fadds_opf = 0x41,
204 faddd_opf = 0x42,
205 fsubs_opf = 0x45,
206 fsubd_opf = 0x46,
207
208 faligndata_opf = 0x48,
209
210 fmuls_opf = 0x49,
211 fmuld_opf = 0x4a,
212 bshuffle_opf = 0x4c,
213 fdivs_opf = 0x4d,
214 fdivd_opf = 0x4e,
215
216 fcmps_opf = 0x51,
217 fcmpd_opf = 0x52,
218
219 fstox_opf = 0x81,
220 fdtox_opf = 0x82,
221 fxtos_opf = 0x84,
222 fxtod_opf = 0x88,
223 fitos_opf = 0xc4,
224 fdtos_opf = 0xc6,
225 fitod_opf = 0xc8,
226 fstod_opf = 0xc9,
227 fstoi_opf = 0xd1,
228 fdtoi_opf = 0xd2,
229
230 mdtox_opf = 0x110,
231 mstouw_opf = 0x111,
232 mstosw_opf = 0x113,
233 xmulx_opf = 0x115,
234 xmulxhi_opf = 0x116,
235 mxtod_opf = 0x118,
236 mwtos_opf = 0x119,
237
238 aes_kexpand0_opf = 0x130,
239 aes_kexpand2_opf = 0x131,
240
241 sha1_opf = 0x141,
242 sha256_opf = 0x142,
243 sha512_opf = 0x143,
244
245 crc32c_opf = 0x147
246 };
247
248 enum op5s {
249 aes_eround01_op5 = 0x00,
250 aes_eround23_op5 = 0x01,
251 aes_dround01_op5 = 0x02,
252 aes_dround23_op5 = 0x03,
253 aes_eround01_l_op5 = 0x04,
254 aes_eround23_l_op5 = 0x05,
255 aes_dround01_l_op5 = 0x06,
256 aes_dround23_l_op5 = 0x07,
257 aes_kexpand1_op5 = 0x08
258 };
259
260 enum RCondition { rc_z = 1, rc_lez = 2, rc_lz = 3, rc_nz = 5, rc_gz = 6, rc_gez = 7, rc_last = rc_gez };
261
262 enum Condition {
263 // for FBfcc & FBPfcc instruction
264 f_never = 0,
265 f_notEqual = 1,
266 f_notZero = 1,
267 f_lessOrGreater = 2,
268 f_unorderedOrLess = 3,
269 f_less = 4,
270 f_unorderedOrGreater = 5,
271 f_greater = 6,
272 f_unordered = 7,
273 f_always = 8,
274 f_equal = 9,
275 f_zero = 9,
276 f_unorderedOrEqual = 10,
277 f_greaterOrEqual = 11,
278 f_unorderedOrGreaterOrEqual = 12,
279 f_lessOrEqual = 13,
280 f_unorderedOrLessOrEqual = 14,
281 f_ordered = 15,
282
283 // V8 coproc, pp 123 v8 manual
284
285 cp_always = 8,
286 cp_never = 0,
287 cp_3 = 7,
288 cp_2 = 6,
289 cp_2or3 = 5,
290 cp_1 = 4,
291 cp_1or3 = 3,
292 cp_1or2 = 2,
293 cp_1or2or3 = 1,
294 cp_0 = 9,
295 cp_0or3 = 10,
296 cp_0or2 = 11,
297 cp_0or2or3 = 12,
298 cp_0or1 = 13,
299 cp_0or1or3 = 14,
300 cp_0or1or2 = 15,
301
302
303 // for integers
304
305 never = 0,
306 equal = 1,
307 zero = 1,
308 lessEqual = 2,
309 less = 3,
310 lessEqualUnsigned = 4,
311 lessUnsigned = 5,
312 carrySet = 5,
313 negative = 6,
314 overflowSet = 7,
315 always = 8,
316 notEqual = 9,
317 notZero = 9,
318 greater = 10,
319 greaterEqual = 11,
320 greaterUnsigned = 12,
321 greaterEqualUnsigned = 13,
322 carryClear = 13,
323 positive = 14,
324 overflowClear = 15
325 };
326
327 enum CC {
328 icc = 0, xcc = 2,
329 // ptr_cc is the correct condition code for a pointer or intptr_t:
330 ptr_cc = NOT_LP64(icc) LP64_ONLY(xcc),
331 fcc0 = 0, fcc1 = 1, fcc2 = 2, fcc3 = 3
332 };
333
334 enum PrefetchFcn {
335 severalReads = 0, oneRead = 1, severalWritesAndPossiblyReads = 2, oneWrite = 3, page = 4
336 };
337
338 public:
339 // Helper functions for groups of instructions
340
341 enum Predict { pt = 1, pn = 0 }; // pt = predict taken
342
343 enum Membar_mask_bits { // page 184, v9
344 StoreStore = 1 << 3,
345 LoadStore = 1 << 2,
346 StoreLoad = 1 << 1,
347 LoadLoad = 1 << 0,
348
349 Sync = 1 << 6,
350 MemIssue = 1 << 5,
351 Lookaside = 1 << 4
352 };
353
354 static bool is_in_wdisp_range(address a, address b, int nbits) {
355 intptr_t d = intptr_t(b) - intptr_t(a);
356 return is_simm(d, nbits + 2);
357 }
358
359 address target_distance(Label& L) {
360 // Assembler::target(L) should be called only when
361 // a branch instruction is emitted since non-bound
362 // labels record current pc() as a branch address.
363 if (L.is_bound()) return target(L);
364 // Return current address for non-bound labels.
365 return pc();
366 }
367
368 // test if label is in simm16 range in words (wdisp16).
369 bool is_in_wdisp16_range(Label& L) {
370 return is_in_wdisp_range(target_distance(L), pc(), 16);
371 }
372 // test if the distance between two addresses fits in simm30 range in words
373 static bool is_in_wdisp30_range(address a, address b) {
374 return is_in_wdisp_range(a, b, 30);
375 }
376
377 enum ASIs { // page 72, v9
378 ASI_PRIMARY = 0x80,
379 ASI_PRIMARY_NOFAULT = 0x82,
380 ASI_PRIMARY_LITTLE = 0x88,
381 // 8x8-bit partial store
382 ASI_PST8_PRIMARY = 0xC0,
383 // Block initializing store
384 ASI_ST_BLKINIT_PRIMARY = 0xE2,
385 // Most-Recently-Used (MRU) BIS variant
386 ASI_ST_BLKINIT_MRU_PRIMARY = 0xF2
387 // add more from book as needed
388 };
389
390 protected:
391 // helpers
392
393 // x is supposed to fit in a field "nbits" wide
394 // and be sign-extended. Check the range.
395
396 static void assert_signed_range(intptr_t x, int nbits) {
397 assert(nbits == 32 || (-(1 << nbits-1) <= x && x < ( 1 << nbits-1)),
398 "value out of range: x=" INTPTR_FORMAT ", nbits=%d", x, nbits);
399 }
400
401 static void assert_signed_word_disp_range(intptr_t x, int nbits) {
402 assert( (x & 3) == 0, "not word aligned");
403 assert_signed_range(x, nbits + 2);
404 }
405
406 static void assert_unsigned_const(int x, int nbits) {
407 assert( juint(x) < juint(1 << nbits), "unsigned constant out of range");
408 }
409
410 // fields: note bits numbered from LSB = 0,
411 // fields known by inclusive bit range
412
413 static int fmask(juint hi_bit, juint lo_bit) {
414 assert( hi_bit >= lo_bit && 0 <= lo_bit && hi_bit < 32, "bad bits");
415 return (1 << ( hi_bit-lo_bit + 1 )) - 1;
416 }
417
418 // inverse of u_field
419
420 static int inv_u_field(int x, int hi_bit, int lo_bit) {
421 juint r = juint(x) >> lo_bit;
422 r &= fmask( hi_bit, lo_bit);
423 return int(r);
424 }
425
426
427 // signed version: extract from field and sign-extend
428
429 static int inv_s_field(int x, int hi_bit, int lo_bit) {
430 int sign_shift = 31 - hi_bit;
431 return inv_u_field( ((x << sign_shift) >> sign_shift), hi_bit, lo_bit);
432 }
433
434 // given a field that ranges from hi_bit to lo_bit (inclusive,
435 // LSB = 0), and an unsigned value for the field,
436 // shift it into the field
437
438 #ifdef ASSERT
439 static int u_field(int x, int hi_bit, int lo_bit) {
440 assert( ( x & ~fmask(hi_bit, lo_bit)) == 0,
441 "value out of range");
442 int r = x << lo_bit;
443 assert( inv_u_field(r, hi_bit, lo_bit) == x, "just checking");
444 return r;
445 }
446 #else
447 // make sure this is inlined as it will reduce code size significantly
448 #define u_field(x, hi_bit, lo_bit) ((x) << (lo_bit))
449 #endif
450
451 static int inv_op( int x ) { return inv_u_field(x, 31, 30); }
452 static int inv_op2( int x ) { return inv_u_field(x, 24, 22); }
453 static int inv_op3( int x ) { return inv_u_field(x, 24, 19); }
454 static int inv_cond( int x ){ return inv_u_field(x, 28, 25); }
455
456 static bool inv_immed( int x ) { return (x & Assembler::immed(true)) != 0; }
457
458 static Register inv_rd( int x ) { return as_Register(inv_u_field(x, 29, 25)); }
459 static Register inv_rs1( int x ) { return as_Register(inv_u_field(x, 18, 14)); }
460 static Register inv_rs2( int x ) { return as_Register(inv_u_field(x, 4, 0)); }
461
462 static int op( int x) { return u_field(x, 31, 30); }
463 static int rd( Register r) { return u_field(r->encoding(), 29, 25); }
464 static int fcn( int x) { return u_field(x, 29, 25); }
465 static int op3( int x) { return u_field(x, 24, 19); }
466 static int rs1( Register r) { return u_field(r->encoding(), 18, 14); }
467 static int rs2( Register r) { return u_field(r->encoding(), 4, 0); }
468 static int annul( bool a) { return u_field(a ? 1 : 0, 29, 29); }
469 static int cond( int x) { return u_field(x, 28, 25); }
470 static int cond_mov( int x) { return u_field(x, 17, 14); }
471 static int rcond( RCondition x) { return u_field(x, 12, 10); }
472 static int op2( int x) { return u_field(x, 24, 22); }
473 static int predict( bool p) { return u_field(p ? 1 : 0, 19, 19); }
474 static int branchcc( CC fcca) { return u_field(fcca, 21, 20); }
475 static int cmpcc( CC fcca) { return u_field(fcca, 26, 25); }
476 static int imm_asi( int x) { return u_field(x, 12, 5); }
477 static int immed( bool i) { return u_field(i ? 1 : 0, 13, 13); }
478 static int opf_low6( int w) { return u_field(w, 10, 5); }
479 static int opf_low5( int w) { return u_field(w, 9, 5); }
480 static int op5( int x) { return u_field(x, 8, 5); }
481 static int trapcc( CC cc) { return u_field(cc, 12, 11); }
482 static int sx( int i) { return u_field(i, 12, 12); } // shift x=1 means 64-bit
483 static int opf( int x) { return u_field(x, 13, 5); }
484
485 static bool is_cbcond( int x ) {
486 return (VM_Version::has_cbcond() && (inv_cond(x) > rc_last) &&
487 inv_op(x) == branch_op && inv_op2(x) == bpr_op2);
488 }
489 static bool is_cxb( int x ) {
490 assert(is_cbcond(x), "wrong instruction");
491 return (x & (1<<21)) != 0;
492 }
493 static int cond_cbcond( int x) { return u_field((((x & 8)<<1) + 8 + (x & 7)), 29, 25); }
494 static int inv_cond_cbcond(int x) {
495 assert(is_cbcond(x), "wrong instruction");
496 return inv_u_field(x, 27, 25) | (inv_u_field(x, 29, 29)<<3);
497 }
498
499 static int opf_cc( CC c, bool useFloat ) { return u_field((useFloat ? 0 : 4) + c, 13, 11); }
500 static int mov_cc( CC c, bool useFloat ) { return u_field(useFloat ? 0 : 1, 18, 18) | u_field(c, 12, 11); }
501
502 static int fd( FloatRegister r, FloatRegisterImpl::Width fwa) { return u_field(r->encoding(fwa), 29, 25); };
503 static int fs1(FloatRegister r, FloatRegisterImpl::Width fwa) { return u_field(r->encoding(fwa), 18, 14); };
504 static int fs2(FloatRegister r, FloatRegisterImpl::Width fwa) { return u_field(r->encoding(fwa), 4, 0); };
505 static int fs3(FloatRegister r, FloatRegisterImpl::Width fwa) { return u_field(r->encoding(fwa), 13, 9); };
506
507 // some float instructions use this encoding on the op3 field
508 static int alt_op3(int op, FloatRegisterImpl::Width w) {
509 int r;
510 switch(w) {
511 case FloatRegisterImpl::S: r = op + 0; break;
512 case FloatRegisterImpl::D: r = op + 3; break;
513 case FloatRegisterImpl::Q: r = op + 2; break;
514 default: ShouldNotReachHere(); break;
515 }
516 return op3(r);
517 }
518
519
520 // compute inverse of simm
521 static int inv_simm(int x, int nbits) {
522 return (int)(x << (32 - nbits)) >> (32 - nbits);
523 }
524
525 static int inv_simm13( int x ) { return inv_simm(x, 13); }
526
527 // signed immediate, in low bits, nbits long
528 static int simm(int x, int nbits) {
529 assert_signed_range(x, nbits);
530 return x & (( 1 << nbits ) - 1);
531 }
532
533 // compute inverse of wdisp16
534 static intptr_t inv_wdisp16(int x, intptr_t pos) {
535 int lo = x & (( 1 << 14 ) - 1);
536 int hi = (x >> 20) & 3;
537 if (hi >= 2) hi |= ~1;
538 return (((hi << 14) | lo) << 2) + pos;
539 }
540
541 // word offset, 14 bits at LSend, 2 bits at B21, B20
542 static int wdisp16(intptr_t x, intptr_t off) {
543 intptr_t xx = x - off;
544 assert_signed_word_disp_range(xx, 16);
545 int r = (xx >> 2) & ((1 << 14) - 1)
546 | ( ( (xx>>(2+14)) & 3 ) << 20 );
547 assert( inv_wdisp16(r, off) == x, "inverse is not inverse");
548 return r;
549 }
550
551 // compute inverse of wdisp10
552 static intptr_t inv_wdisp10(int x, intptr_t pos) {
553 assert(is_cbcond(x), "wrong instruction");
554 int lo = inv_u_field(x, 12, 5);
555 int hi = (x >> 19) & 3;
556 if (hi >= 2) hi |= ~1;
557 return (((hi << 8) | lo) << 2) + pos;
558 }
559
560 // word offset for cbcond, 8 bits at [B12,B5], 2 bits at [B20,B19]
561 static int wdisp10(intptr_t x, intptr_t off) {
562 assert(VM_Version::has_cbcond(), "This CPU does not have CBCOND instruction");
563 intptr_t xx = x - off;
564 assert_signed_word_disp_range(xx, 10);
565 int r = ( ( (xx >> 2 ) & ((1 << 8) - 1) ) << 5 )
566 | ( ( (xx >> (2+8)) & 3 ) << 19 );
567 // Have to fake cbcond instruction to pass assert in inv_wdisp10()
568 assert(inv_wdisp10((r | op(branch_op) | cond_cbcond(rc_last+1) | op2(bpr_op2)), off) == x, "inverse is not inverse");
569 return r;
570 }
571
572 // word displacement in low-order nbits bits
573
574 static intptr_t inv_wdisp( int x, intptr_t pos, int nbits ) {
575 int pre_sign_extend = x & (( 1 << nbits ) - 1);
576 int r = pre_sign_extend >= ( 1 << (nbits-1) )
577 ? pre_sign_extend | ~(( 1 << nbits ) - 1)
578 : pre_sign_extend;
579 return (r << 2) + pos;
580 }
581
582 static int wdisp( intptr_t x, intptr_t off, int nbits ) {
583 intptr_t xx = x - off;
584 assert_signed_word_disp_range(xx, nbits);
585 int r = (xx >> 2) & (( 1 << nbits ) - 1);
586 assert( inv_wdisp( r, off, nbits ) == x, "inverse not inverse");
587 return r;
588 }
589
590
591 // Extract the top 32 bits in a 64 bit word
592 static int32_t hi32( int64_t x ) {
593 int32_t r = int32_t( (uint64_t)x >> 32 );
594 return r;
595 }
596
597 // given a sethi instruction, extract the constant, left-justified
598 static int inv_hi22( int x ) {
599 return x << 10;
600 }
601
602 // create an imm22 field, given a 32-bit left-justified constant
603 static int hi22( int x ) {
604 int r = int( juint(x) >> 10 );
605 assert( (r & ~((1 << 22) - 1)) == 0, "just checkin'");
606 return r;
607 }
608
609 // create a low10 __value__ (not a field) for a given a 32-bit constant
610 static int low10( int x ) {
611 return x & ((1 << 10) - 1);
612 }
613
614 // create a low12 __value__ (not a field) for a given a 32-bit constant
615 static int low12( int x ) {
616 return x & ((1 << 12) - 1);
617 }
618
619 // AES crypto instructions supported only on certain processors
620 static void aes_only() { assert( VM_Version::has_aes(), "This instruction only works on SPARC with AES instructions support"); }
621
622 // SHA crypto instructions supported only on certain processors
623 static void sha1_only() { assert( VM_Version::has_sha1(), "This instruction only works on SPARC with SHA1"); }
624 static void sha256_only() { assert( VM_Version::has_sha256(), "This instruction only works on SPARC with SHA256"); }
625 static void sha512_only() { assert( VM_Version::has_sha512(), "This instruction only works on SPARC with SHA512"); }
626
627 // CRC32C instruction supported only on certain processors
628 static void crc32c_only() { assert( VM_Version::has_crc32c(), "This instruction only works on SPARC with CRC32C"); }
629
630 // instruction only in VIS1
631 static void vis1_only() { assert( VM_Version::has_vis1(), "This instruction only works on SPARC with VIS1"); }
632
633 // instruction only in VIS2
634 static void vis2_only() { assert( VM_Version::has_vis2(), "This instruction only works on SPARC with VIS2"); }
635
636 // instruction only in VIS3
637 static void vis3_only() { assert( VM_Version::has_vis3(), "This instruction only works on SPARC with VIS3"); }
638
639 // instruction only in v9
640 static void v9_only() { } // do nothing
641
642 // instruction deprecated in v9
643 static void v9_dep() { } // do nothing for now
644
645 // v8 has no CC field
646 static void v8_no_cc(CC cc) { if (cc) v9_only(); }
647
648 protected:
649 // Simple delay-slot scheme:
650 // In order to check the programmer, the assembler keeps track of deley slots.
651 // It forbids CTIs in delay slots (conservative, but should be OK).
652 // Also, when putting an instruction into a delay slot, you must say
653 // asm->delayed()->add(...), in order to check that you don't omit
654 // delay-slot instructions.
655 // To implement this, we use a simple FSA
656
657 #ifdef ASSERT
658 #define CHECK_DELAY
659 #endif
660 #ifdef CHECK_DELAY
661 enum Delay_state { no_delay, at_delay_slot, filling_delay_slot } delay_state;
662 #endif
663
664 public:
665 // Tells assembler next instruction must NOT be in delay slot.
666 // Use at start of multinstruction macros.
667 void assert_not_delayed() {
668 // This is a separate overloading to avoid creation of string constants
669 // in non-asserted code--with some compilers this pollutes the object code.
670 #ifdef CHECK_DELAY
671 assert_not_delayed("next instruction should not be a delay slot");
672 #endif
673 }
674 void assert_not_delayed(const char* msg) {
675 #ifdef CHECK_DELAY
676 assert(delay_state == no_delay, msg);
677 #endif
678 }
679
680 protected:
681 // Insert a nop if the previous is cbcond
682 inline void insert_nop_after_cbcond();
683
684 // Delay slot helpers
685 // cti is called when emitting control-transfer instruction,
686 // BEFORE doing the emitting.
687 // Only effective when assertion-checking is enabled.
688 void cti() {
689 // A cbcond instruction immediately followed by a CTI
690 // instruction introduces pipeline stalls, we need to avoid that.
691 no_cbcond_before();
692 #ifdef CHECK_DELAY
693 assert_not_delayed("cti should not be in delay slot");
694 #endif
695 }
696
697 // called when emitting cti with a delay slot, AFTER emitting
698 void has_delay_slot() {
699 #ifdef CHECK_DELAY
700 assert_not_delayed("just checking");
701 delay_state = at_delay_slot;
702 #endif
703 }
704
705 // cbcond instruction should not be generated one after an other
706 bool cbcond_before() {
707 if (offset() == 0) return false; // it is first instruction
708 int x = *(int*)(intptr_t(pc()) - 4); // previous instruction
709 return is_cbcond(x);
710 }
711
712 void no_cbcond_before() {
713 assert(offset() == 0 || !cbcond_before(), "cbcond should not follow an other cbcond");
714 }
715 public:
716
717 bool use_cbcond(Label& L) {
718 if (!UseCBCond || cbcond_before()) return false;
719 intptr_t x = intptr_t(target_distance(L)) - intptr_t(pc());
720 assert( (x & 3) == 0, "not word aligned");
721 return is_simm12(x);
722 }
723
724 // Tells assembler you know that next instruction is delayed
725 Assembler* delayed() {
726 #ifdef CHECK_DELAY
727 assert ( delay_state == at_delay_slot, "delayed instruction is not in delay slot");
728 delay_state = filling_delay_slot;
729 #endif
730 return this;
731 }
732
733 void flush() {
734 #ifdef CHECK_DELAY
735 assert ( delay_state == no_delay, "ending code with a delay slot");
736 #endif
737 AbstractAssembler::flush();
738 }
739
740 inline void emit_int32(int); // shadows AbstractAssembler::emit_int32
741 inline void emit_data(int x);
742 inline void emit_data(int, RelocationHolder const&);
743 inline void emit_data(int, relocInfo::relocType rtype);
744 // helper for above fcns
745 inline void check_delay();
746
747
748 public:
749 // instructions, refer to page numbers in the SPARC Architecture Manual, V9
750
751 // pp 135 (addc was addx in v8)
752
753 inline void add(Register s1, Register s2, Register d );
754 inline void add(Register s1, int simm13a, Register d );
755
756 inline void addcc( Register s1, Register s2, Register d );
757 inline void addcc( Register s1, int simm13a, Register d );
758 inline void addc( Register s1, Register s2, Register d );
759 inline void addc( Register s1, int simm13a, Register d );
760 inline void addccc( Register s1, Register s2, Register d );
761 inline void addccc( Register s1, int simm13a, Register d );
762
763
764 // 4-operand AES instructions
765
766 inline void aes_eround01( FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d );
767 inline void aes_eround23( FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d );
768 inline void aes_dround01( FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d );
769 inline void aes_dround23( FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d );
770 inline void aes_eround01_l( FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d );
771 inline void aes_eround23_l( FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d );
772 inline void aes_dround01_l( FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d );
773 inline void aes_dround23_l( FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d );
774 inline void aes_kexpand1( FloatRegister s1, FloatRegister s2, int imm5a, FloatRegister d );
775
776
777 // 3-operand AES instructions
778
779 inline void aes_kexpand0( FloatRegister s1, FloatRegister s2, FloatRegister d );
780 inline void aes_kexpand2( FloatRegister s1, FloatRegister s2, FloatRegister d );
781
782 // pp 136
783
784 inline void bpr(RCondition c, bool a, Predict p, Register s1, address d, relocInfo::relocType rt = relocInfo::none);
785 inline void bpr(RCondition c, bool a, Predict p, Register s1, Label& L);
786
787 // compare and branch
788 inline void cbcond(Condition c, CC cc, Register s1, Register s2, Label& L);
789 inline void cbcond(Condition c, CC cc, Register s1, int simm5, Label& L);
790
791 protected: // use MacroAssembler::br instead
792
793 // pp 138
794
795 inline void fb( Condition c, bool a, address d, relocInfo::relocType rt = relocInfo::none );
796 inline void fb( Condition c, bool a, Label& L );
797
798 // pp 141
799
800 inline void fbp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt = relocInfo::none );
801 inline void fbp( Condition c, bool a, CC cc, Predict p, Label& L );
802
803 // pp 144
804
805 inline void br( Condition c, bool a, address d, relocInfo::relocType rt = relocInfo::none );
806 inline void br( Condition c, bool a, Label& L );
807
808 // pp 146
809
810 inline void bp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt = relocInfo::none );
811 inline void bp( Condition c, bool a, CC cc, Predict p, Label& L );
812
813 // pp 149
814
815 inline void call( address d, relocInfo::relocType rt = relocInfo::runtime_call_type );
816 inline void call( Label& L, relocInfo::relocType rt = relocInfo::runtime_call_type );
817
818 inline void call( address d, RelocationHolder const& rspec );
819
820 public:
821
822 // pp 150
823
824 // These instructions compare the contents of s2 with the contents of
825 // memory at address in s1. If the values are equal, the contents of memory
826 // at address s1 is swapped with the data in d. If the values are not equal,
827 // the the contents of memory at s1 is loaded into d, without the swap.
828
829 inline void casa( Register s1, Register s2, Register d, int ia = -1 );
830 inline void casxa( Register s1, Register s2, Register d, int ia = -1 );
831
832 // pp 152
833
834 inline void udiv( Register s1, Register s2, Register d );
835 inline void udiv( Register s1, int simm13a, Register d );
836 inline void sdiv( Register s1, Register s2, Register d );
837 inline void sdiv( Register s1, int simm13a, Register d );
838 inline void udivcc( Register s1, Register s2, Register d );
839 inline void udivcc( Register s1, int simm13a, Register d );
840 inline void sdivcc( Register s1, Register s2, Register d );
841 inline void sdivcc( Register s1, int simm13a, Register d );
842
843 // pp 155
844
845 inline void done();
846 inline void retry();
847
848 // pp 156
849
850 inline void fadd( FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d );
851 inline void fsub( FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d );
852
853 // pp 157
854
855 inline void fcmp( FloatRegisterImpl::Width w, CC cc, FloatRegister s1, FloatRegister s2);
856 inline void fcmpe( FloatRegisterImpl::Width w, CC cc, FloatRegister s1, FloatRegister s2);
857
858 // pp 159
859
860 inline void ftox( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d );
861 inline void ftoi( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d );
862
863 // pp 160
864
865 inline void ftof( FloatRegisterImpl::Width sw, FloatRegisterImpl::Width dw, FloatRegister s, FloatRegister d );
866
867 // pp 161
868
869 inline void fxtof( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d );
870 inline void fitof( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d );
871
872 // pp 162
873
874 inline void fmov( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d );
875
876 inline void fneg( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d );
877
878 inline void fabs( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d );
879
880 // pp 163
881
882 inline void fmul( FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d );
883 inline void fmul( FloatRegisterImpl::Width sw, FloatRegisterImpl::Width dw, FloatRegister s1, FloatRegister s2, FloatRegister d );
884 inline void fdiv( FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d );
885
886 // FXORs/FXORd instructions
887
888 inline void fxor( FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d );
889
890 // pp 164
891
892 inline void fsqrt( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d );
893
894 // pp 165
895
896 inline void flush( Register s1, Register s2 );
897 inline void flush( Register s1, int simm13a);
898
899 // pp 167
900
901 void flushw();
902
903 // pp 168
904
905 void illtrap( int const22a);
906 // v8 unimp == illtrap(0)
907
908 // pp 169
909
910 void impdep1( int id1, int const19a );
911 void impdep2( int id1, int const19a );
912
913 // pp 170
914
915 void jmpl( Register s1, Register s2, Register d );
916 void jmpl( Register s1, int simm13a, Register d, RelocationHolder const& rspec = RelocationHolder() );
917
918 // 171
919
920 inline void ldf(FloatRegisterImpl::Width w, Register s1, Register s2, FloatRegister d);
921 inline void ldf(FloatRegisterImpl::Width w, Register s1, int simm13a, FloatRegister d, RelocationHolder const& rspec = RelocationHolder());
922
923
924 inline void ldfsr( Register s1, Register s2 );
925 inline void ldfsr( Register s1, int simm13a);
926 inline void ldxfsr( Register s1, Register s2 );
927 inline void ldxfsr( Register s1, int simm13a);
928
929 // 173
930
931 inline void ldfa( FloatRegisterImpl::Width w, Register s1, Register s2, int ia, FloatRegister d );
932 inline void ldfa( FloatRegisterImpl::Width w, Register s1, int simm13a, FloatRegister d );
933
934 // pp 175, lduw is ld on v8
935
936 inline void ldsb( Register s1, Register s2, Register d );
937 inline void ldsb( Register s1, int simm13a, Register d);
938 inline void ldsh( Register s1, Register s2, Register d );
939 inline void ldsh( Register s1, int simm13a, Register d);
940 inline void ldsw( Register s1, Register s2, Register d );
941 inline void ldsw( Register s1, int simm13a, Register d);
942 inline void ldub( Register s1, Register s2, Register d );
943 inline void ldub( Register s1, int simm13a, Register d);
944 inline void lduh( Register s1, Register s2, Register d );
945 inline void lduh( Register s1, int simm13a, Register d);
946 inline void lduw( Register s1, Register s2, Register d );
947 inline void lduw( Register s1, int simm13a, Register d);
948 inline void ldx( Register s1, Register s2, Register d );
949 inline void ldx( Register s1, int simm13a, Register d);
950 inline void ldd( Register s1, Register s2, Register d );
951 inline void ldd( Register s1, int simm13a, Register d);
952
953 // pp 177
954
955 inline void ldsba( Register s1, Register s2, int ia, Register d );
956 inline void ldsba( Register s1, int simm13a, Register d );
957 inline void ldsha( Register s1, Register s2, int ia, Register d );
958 inline void ldsha( Register s1, int simm13a, Register d );
959 inline void ldswa( Register s1, Register s2, int ia, Register d );
960 inline void ldswa( Register s1, int simm13a, Register d );
961 inline void lduba( Register s1, Register s2, int ia, Register d );
962 inline void lduba( Register s1, int simm13a, Register d );
963 inline void lduha( Register s1, Register s2, int ia, Register d );
964 inline void lduha( Register s1, int simm13a, Register d );
965 inline void lduwa( Register s1, Register s2, int ia, Register d );
966 inline void lduwa( Register s1, int simm13a, Register d );
967 inline void ldxa( Register s1, Register s2, int ia, Register d );
968 inline void ldxa( Register s1, int simm13a, Register d );
969
970 // pp 181
971
972 inline void and3( Register s1, Register s2, Register d );
973 inline void and3( Register s1, int simm13a, Register d );
974 inline void andcc( Register s1, Register s2, Register d );
975 inline void andcc( Register s1, int simm13a, Register d );
976 inline void andn( Register s1, Register s2, Register d );
977 inline void andn( Register s1, int simm13a, Register d );
978 inline void andncc( Register s1, Register s2, Register d );
979 inline void andncc( Register s1, int simm13a, Register d );
980 inline void or3( Register s1, Register s2, Register d );
981 inline void or3( Register s1, int simm13a, Register d );
982 inline void orcc( Register s1, Register s2, Register d );
983 inline void orcc( Register s1, int simm13a, Register d );
984 inline void orn( Register s1, Register s2, Register d );
985 inline void orn( Register s1, int simm13a, Register d );
986 inline void orncc( Register s1, Register s2, Register d );
987 inline void orncc( Register s1, int simm13a, Register d );
988 inline void xor3( Register s1, Register s2, Register d );
989 inline void xor3( Register s1, int simm13a, Register d );
990 inline void xorcc( Register s1, Register s2, Register d );
991 inline void xorcc( Register s1, int simm13a, Register d );
992 inline void xnor( Register s1, Register s2, Register d );
993 inline void xnor( Register s1, int simm13a, Register d );
994 inline void xnorcc( Register s1, Register s2, Register d );
995 inline void xnorcc( Register s1, int simm13a, Register d );
996
997 // pp 183
998
999 inline void membar( Membar_mask_bits const7a );
1000
1001 // pp 185
1002
1003 inline void fmov( FloatRegisterImpl::Width w, Condition c, bool floatCC, CC cca, FloatRegister s2, FloatRegister d );
1004
1005 // pp 189
1006
1007 inline void fmov( FloatRegisterImpl::Width w, RCondition c, Register s1, FloatRegister s2, FloatRegister d );
1008
1009 // pp 191
1010
1011 inline void movcc( Condition c, bool floatCC, CC cca, Register s2, Register d );
1012 inline void movcc( Condition c, bool floatCC, CC cca, int simm11a, Register d );
1013
1014 // pp 195
1015
1016 inline void movr( RCondition c, Register s1, Register s2, Register d );
1017 inline void movr( RCondition c, Register s1, int simm10a, Register d );
1018
1019 // pp 196
1020
1021 inline void mulx( Register s1, Register s2, Register d );
1022 inline void mulx( Register s1, int simm13a, Register d );
1023 inline void sdivx( Register s1, Register s2, Register d );
1024 inline void sdivx( Register s1, int simm13a, Register d );
1025 inline void udivx( Register s1, Register s2, Register d );
1026 inline void udivx( Register s1, int simm13a, Register d );
1027
1028 // pp 197
1029
1030 inline void umul( Register s1, Register s2, Register d );
1031 inline void umul( Register s1, int simm13a, Register d );
1032 inline void smul( Register s1, Register s2, Register d );
1033 inline void smul( Register s1, int simm13a, Register d );
1034 inline void umulcc( Register s1, Register s2, Register d );
1035 inline void umulcc( Register s1, int simm13a, Register d );
1036 inline void smulcc( Register s1, Register s2, Register d );
1037 inline void smulcc( Register s1, int simm13a, Register d );
1038
1039 // pp 201
1040
1041 inline void nop();
1042
1043 inline void sw_count();
1044
1045 // pp 202
1046
1047 inline void popc( Register s, Register d);
1048 inline void popc( int simm13a, Register d);
1049
1050 // pp 203
1051
1052 inline void prefetch( Register s1, Register s2, PrefetchFcn f);
1053 inline void prefetch( Register s1, int simm13a, PrefetchFcn f);
1054
1055 inline void prefetcha( Register s1, Register s2, int ia, PrefetchFcn f );
1056 inline void prefetcha( Register s1, int simm13a, PrefetchFcn f );
1057
1058 // pp 208
1059
1060 // not implementing read privileged register
1061
1062 inline void rdy( Register d);
1063 inline void rdccr( Register d);
1064 inline void rdasi( Register d);
1065 inline void rdtick( Register d);
1066 inline void rdpc( Register d);
1067 inline void rdfprs( Register d);
1068
1069 // pp 213
1070
1071 inline void rett( Register s1, Register s2);
1072 inline void rett( Register s1, int simm13a, relocInfo::relocType rt = relocInfo::none);
1073
1074 // pp 214
1075
1076 inline void save( Register s1, Register s2, Register d );
1077 inline void save( Register s1, int simm13a, Register d );
1078
1079 inline void restore( Register s1 = G0, Register s2 = G0, Register d = G0 );
1080 inline void restore( Register s1, int simm13a, Register d );
1081
1082 // pp 216
1083
1084 inline void saved();
1085 inline void restored();
1086
1087 // pp 217
1088
1089 inline void sethi( int imm22a, Register d, RelocationHolder const& rspec = RelocationHolder() );
1090 // pp 218
1091
1092 inline void sll( Register s1, Register s2, Register d );
1093 inline void sll( Register s1, int imm5a, Register d );
1094 inline void srl( Register s1, Register s2, Register d );
1095 inline void srl( Register s1, int imm5a, Register d );
1096 inline void sra( Register s1, Register s2, Register d );
1097 inline void sra( Register s1, int imm5a, Register d );
1098
1099 inline void sllx( Register s1, Register s2, Register d );
1100 inline void sllx( Register s1, int imm6a, Register d );
1101 inline void srlx( Register s1, Register s2, Register d );
1102 inline void srlx( Register s1, int imm6a, Register d );
1103 inline void srax( Register s1, Register s2, Register d );
1104 inline void srax( Register s1, int imm6a, Register d );
1105
1106 // pp 220
1107
1108 inline void sir( int simm13a );
1109
1110 // pp 221
1111
1112 inline void stbar();
1113
1114 // pp 222
1115
1116 inline void stf( FloatRegisterImpl::Width w, FloatRegister d, Register s1, Register s2);
1117 inline void stf( FloatRegisterImpl::Width w, FloatRegister d, Register s1, int simm13a);
1118
1119 inline void stfsr( Register s1, Register s2 );
1120 inline void stfsr( Register s1, int simm13a);
1121 inline void stxfsr( Register s1, Register s2 );
1122 inline void stxfsr( Register s1, int simm13a);
1123
1124 // pp 224
1125
1126 inline void stfa( FloatRegisterImpl::Width w, FloatRegister d, Register s1, Register s2, int ia );
1127 inline void stfa( FloatRegisterImpl::Width w, FloatRegister d, Register s1, int simm13a );
1128
1129 // p 226
1130
1131 inline void stb( Register d, Register s1, Register s2 );
1132 inline void stb( Register d, Register s1, int simm13a);
1133 inline void sth( Register d, Register s1, Register s2 );
1134 inline void sth( Register d, Register s1, int simm13a);
1135 inline void stw( Register d, Register s1, Register s2 );
1136 inline void stw( Register d, Register s1, int simm13a);
1137 inline void stx( Register d, Register s1, Register s2 );
1138 inline void stx( Register d, Register s1, int simm13a);
1139 inline void std( Register d, Register s1, Register s2 );
1140 inline void std( Register d, Register s1, int simm13a);
1141
1142 // pp 177
1143
1144 inline void stba( Register d, Register s1, Register s2, int ia );
1145 inline void stba( Register d, Register s1, int simm13a );
1146 inline void stha( Register d, Register s1, Register s2, int ia );
1147 inline void stha( Register d, Register s1, int simm13a );
1148 inline void stwa( Register d, Register s1, Register s2, int ia );
1149 inline void stwa( Register d, Register s1, int simm13a );
1150 inline void stxa( Register d, Register s1, Register s2, int ia );
1151 inline void stxa( Register d, Register s1, int simm13a );
1152 inline void stda( Register d, Register s1, Register s2, int ia );
1153 inline void stda( Register d, Register s1, int simm13a );
1154
1155 // pp 230
1156
1157 inline void sub( Register s1, Register s2, Register d );
1158 inline void sub( Register s1, int simm13a, Register d );
1159
1160 inline void subcc( Register s1, Register s2, Register d );
1161 inline void subcc( Register s1, int simm13a, Register d );
1162 inline void subc( Register s1, Register s2, Register d );
1163 inline void subc( Register s1, int simm13a, Register d );
1164 inline void subccc( Register s1, Register s2, Register d );
1165 inline void subccc( Register s1, int simm13a, Register d );
1166
1167 // pp 231
1168
1169 inline void swap( Register s1, Register s2, Register d );
1170 inline void swap( Register s1, int simm13a, Register d);
1171
1172 // pp 232
1173
1174 inline void swapa( Register s1, Register s2, int ia, Register d );
1175 inline void swapa( Register s1, int simm13a, Register d );
1176
1177 // pp 234, note op in book is wrong, see pp 268
1178
1179 inline void taddcc( Register s1, Register s2, Register d );
1180 inline void taddcc( Register s1, int simm13a, Register d );
1181
1182 // pp 235
1183
1184 inline void tsubcc( Register s1, Register s2, Register d );
1185 inline void tsubcc( Register s1, int simm13a, Register d );
1186
1187 // pp 237
1188
1189 inline void trap( Condition c, CC cc, Register s1, Register s2 );
1190 inline void trap( Condition c, CC cc, Register s1, int trapa );
1191 // simple uncond. trap
1192 inline void trap( int trapa );
1193
1194 // pp 239 omit write priv register for now
1195
1196 inline void wry( Register d);
1197 inline void wrccr(Register s);
1198 inline void wrccr(Register s, int simm13a);
1199 inline void wrasi(Register d);
1200 // wrasi(d, imm) stores (d xor imm) to asi
1201 inline void wrasi(Register d, int simm13a);
1202 inline void wrfprs( Register d);
1203
1204 // VIS1 instructions
1205
1206 inline void alignaddr( Register s1, Register s2, Register d );
1207
1208 inline void faligndata( FloatRegister s1, FloatRegister s2, FloatRegister d );
1209
1210 inline void fzero( FloatRegisterImpl::Width w, FloatRegister d );
1211
1212 inline void fsrc2( FloatRegisterImpl::Width w, FloatRegister s2, FloatRegister d );
1213
1214 inline void fnot1( FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister d );
1215
1216 inline void fpmerge( FloatRegister s1, FloatRegister s2, FloatRegister d );
1217
1218 inline void stpartialf( Register s1, Register s2, FloatRegister d, int ia = -1 );
1219
1220 // VIS2 instructions
1221
1222 inline void edge8n( Register s1, Register s2, Register d );
1223
1224 inline void bmask( Register s1, Register s2, Register d );
1225 inline void bshuffle( FloatRegister s1, FloatRegister s2, FloatRegister d );
1226
1227 // VIS3 instructions
1228
1229 inline void lzcnt( Register s, Register d );
1230
1231 inline void movstosw( FloatRegister s, Register d );
1232 inline void movstouw( FloatRegister s, Register d );
1233 inline void movdtox( FloatRegister s, Register d );
1234
1235 inline void movwtos( Register s, FloatRegister d );
1236 inline void movxtod( Register s, FloatRegister d );
1237
1238 inline void xmulx(Register s1, Register s2, Register d);
1239 inline void xmulxhi(Register s1, Register s2, Register d);
1240
1241 // Crypto SHA instructions
1242
1243 inline void sha1();
1244 inline void sha256();
1245 inline void sha512();
1246
1247 // CRC32C instruction
1248
1249 inline void crc32c( FloatRegister s1, FloatRegister s2, FloatRegister d );
1250
1251 // Creation
1252 Assembler(CodeBuffer* code) : AbstractAssembler(code) {
1253 #ifdef CHECK_DELAY
1254 delay_state = no_delay;
1255 #endif
1256 }
1257 };
1258
1259 #endif // CPU_SPARC_VM_ASSEMBLER_SPARC_HPP