Print this page
*** NO COMMENTS ***

Split Close
Expand all
Collapse all
          --- old/src/cpu/sparc/vm/assembler_sparc.hpp
          +++ new/src/cpu/sparc/vm/assembler_sparc.hpp
↓ open down ↓ 125 lines elided ↑ open up ↑
 126  126      sha_op3      = 0x36,
 127  127      bmask_op3    = 0x36,
 128  128      bshuffle_op3   = 0x36,
 129  129      alignaddr_op3  = 0x36,
 130  130      faligndata_op3 = 0x36,
 131  131      flog3_op3    = 0x36,
 132  132      edge_op3     = 0x36,
 133  133      fzero_op3    = 0x36,
 134  134      fsrc_op3     = 0x36,
 135  135      fnot_op3     = 0x36,
      136 +    lzcnt_op3    = 0x36,
 136  137      xmulx_op3    = 0x36,
 137  138      crc32c_op3   = 0x36,
 138  139      impdep2_op3  = 0x37,
 139  140      stpartialf_op3 = 0x37,
 140  141      jmpl_op3     = 0x38,
 141  142      rett_op3     = 0x39,
 142  143      trap_op3     = 0x3a,
 143  144      flush_op3    = 0x3b,
 144  145      save_op3     = 0x3c,
 145  146      restore_op3  = 0x3d,
↓ open down ↓ 42 lines elided ↑ open up ↑
 188  189    enum opfs {
 189  190      // selected opfs
 190  191      edge8n_opf         = 0x01,
 191  192  
 192  193      fmovs_opf          = 0x01,
 193  194      fmovd_opf          = 0x02,
 194  195  
 195  196      fnegs_opf          = 0x05,
 196  197      fnegd_opf          = 0x06,
 197  198  
      199 +    lzcnt_opf          = 0x17,
 198  200      alignaddr_opf      = 0x18,
 199  201      bmask_opf          = 0x19,
 200  202  
 201  203      fadds_opf          = 0x41,
 202  204      faddd_opf          = 0x42,
 203  205      fsubs_opf          = 0x45,
 204  206      fsubd_opf          = 0x46,
 205  207  
 206  208      faligndata_opf     = 0x48,
 207  209  
↓ open down ↓ 1009 lines elided ↑ open up ↑
1217 1219  
1218 1220    //  VIS2 instructions
1219 1221  
1220 1222    inline void edge8n( Register s1, Register s2, Register d );
1221 1223  
1222 1224    inline void bmask( Register s1, Register s2, Register d );
1223 1225    inline void bshuffle( FloatRegister s1, FloatRegister s2, FloatRegister d );
1224 1226  
1225 1227    // VIS3 instructions
1226 1228  
     1229 +  inline void lzcnt( Register s, Register d );
     1230 +
1227 1231    inline void movstosw( FloatRegister s, Register d );
1228 1232    inline void movstouw( FloatRegister s, Register d );
1229 1233    inline void movdtox(  FloatRegister s, Register d );
1230 1234  
1231 1235    inline void movwtos( Register s, FloatRegister d );
1232 1236    inline void movxtod( Register s, FloatRegister d );
1233 1237  
1234 1238    inline void xmulx(Register s1, Register s2, Register d);
1235 1239    inline void xmulxhi(Register s1, Register s2, Register d);
1236 1240  
↓ open down ↓ 19 lines elided ↑ open up ↑
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX