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--- old/src/cpu/sparc/vm/assembler_sparc.hpp
+++ new/src/cpu/sparc/vm/assembler_sparc.hpp
1 1 /*
2 2 * Copyright (c) 1997, 2015, Oracle and/or its affiliates. All rights reserved.
3 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 4 *
5 5 * This code is free software; you can redistribute it and/or modify it
6 6 * under the terms of the GNU General Public License version 2 only, as
7 7 * published by the Free Software Foundation.
8 8 *
9 9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 12 * version 2 for more details (a copy is included in the LICENSE file that
13 13 * accompanied this code).
14 14 *
15 15 * You should have received a copy of the GNU General Public License version
16 16 * 2 along with this work; if not, write to the Free Software Foundation,
17 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 18 *
19 19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 20 * or visit www.oracle.com if you need additional information or have any
21 21 * questions.
22 22 *
23 23 */
24 24
25 25 #ifndef CPU_SPARC_VM_ASSEMBLER_SPARC_HPP
26 26 #define CPU_SPARC_VM_ASSEMBLER_SPARC_HPP
27 27
28 28 #include "asm/register.hpp"
29 29
30 30 // The SPARC Assembler: Pure assembler doing NO optimizations on the instruction
31 31 // level; i.e., what you write
32 32 // is what you get. The Assembler is generating code into a CodeBuffer.
33 33
34 34 class Assembler : public AbstractAssembler {
35 35 friend class AbstractAssembler;
36 36 friend class AddressLiteral;
37 37
38 38 // code patchers need various routines like inv_wdisp()
39 39 friend class NativeInstruction;
40 40 friend class NativeGeneralJump;
41 41 friend class Relocation;
42 42 friend class Label;
43 43
44 44 public:
45 45 // op carries format info; see page 62 & 267
46 46
47 47 enum ops {
48 48 call_op = 1, // fmt 1
49 49 branch_op = 0, // also sethi (fmt2)
50 50 arith_op = 2, // fmt 3, arith & misc
51 51 ldst_op = 3 // fmt 3, load/store
52 52 };
53 53
54 54 enum op2s {
55 55 bpr_op2 = 3,
56 56 fb_op2 = 6,
57 57 fbp_op2 = 5,
58 58 br_op2 = 2,
59 59 bp_op2 = 1,
60 60 sethi_op2 = 4
61 61 };
62 62
63 63 enum op3s {
64 64 // selected op3s
65 65 add_op3 = 0x00,
66 66 and_op3 = 0x01,
67 67 or_op3 = 0x02,
68 68 xor_op3 = 0x03,
69 69 sub_op3 = 0x04,
70 70 andn_op3 = 0x05,
71 71 orn_op3 = 0x06,
72 72 xnor_op3 = 0x07,
73 73 addc_op3 = 0x08,
74 74 mulx_op3 = 0x09,
75 75 umul_op3 = 0x0a,
76 76 smul_op3 = 0x0b,
77 77 subc_op3 = 0x0c,
78 78 udivx_op3 = 0x0d,
79 79 udiv_op3 = 0x0e,
80 80 sdiv_op3 = 0x0f,
81 81
82 82 addcc_op3 = 0x10,
83 83 andcc_op3 = 0x11,
84 84 orcc_op3 = 0x12,
85 85 xorcc_op3 = 0x13,
86 86 subcc_op3 = 0x14,
87 87 andncc_op3 = 0x15,
88 88 orncc_op3 = 0x16,
89 89 xnorcc_op3 = 0x17,
90 90 addccc_op3 = 0x18,
91 91 aes4_op3 = 0x19,
92 92 umulcc_op3 = 0x1a,
93 93 smulcc_op3 = 0x1b,
94 94 subccc_op3 = 0x1c,
95 95 udivcc_op3 = 0x1e,
96 96 sdivcc_op3 = 0x1f,
97 97
98 98 taddcc_op3 = 0x20,
99 99 tsubcc_op3 = 0x21,
100 100 taddcctv_op3 = 0x22,
101 101 tsubcctv_op3 = 0x23,
102 102 mulscc_op3 = 0x24,
103 103 sll_op3 = 0x25,
104 104 sllx_op3 = 0x25,
105 105 srl_op3 = 0x26,
106 106 srlx_op3 = 0x26,
107 107 sra_op3 = 0x27,
108 108 srax_op3 = 0x27,
109 109 rdreg_op3 = 0x28,
110 110 membar_op3 = 0x28,
111 111
112 112 flushw_op3 = 0x2b,
113 113 movcc_op3 = 0x2c,
114 114 sdivx_op3 = 0x2d,
115 115 popc_op3 = 0x2e,
116 116 movr_op3 = 0x2f,
117 117
118 118 sir_op3 = 0x30,
119 119 wrreg_op3 = 0x30,
120 120 saved_op3 = 0x31,
121 121
122 122 fpop1_op3 = 0x34,
123 123 fpop2_op3 = 0x35,
124 124 impdep1_op3 = 0x36,
125 125 aes3_op3 = 0x36,
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126 126 sha_op3 = 0x36,
127 127 bmask_op3 = 0x36,
128 128 bshuffle_op3 = 0x36,
129 129 alignaddr_op3 = 0x36,
130 130 faligndata_op3 = 0x36,
131 131 flog3_op3 = 0x36,
132 132 edge_op3 = 0x36,
133 133 fzero_op3 = 0x36,
134 134 fsrc_op3 = 0x36,
135 135 fnot_op3 = 0x36,
136 + lzcnt_op3 = 0x36,
136 137 xmulx_op3 = 0x36,
137 138 crc32c_op3 = 0x36,
138 139 impdep2_op3 = 0x37,
139 140 stpartialf_op3 = 0x37,
140 141 jmpl_op3 = 0x38,
141 142 rett_op3 = 0x39,
142 143 trap_op3 = 0x3a,
143 144 flush_op3 = 0x3b,
144 145 save_op3 = 0x3c,
145 146 restore_op3 = 0x3d,
146 147 done_op3 = 0x3e,
147 148 retry_op3 = 0x3e,
148 149
149 150 lduw_op3 = 0x00,
150 151 ldub_op3 = 0x01,
151 152 lduh_op3 = 0x02,
152 153 ldd_op3 = 0x03,
153 154 stw_op3 = 0x04,
154 155 stb_op3 = 0x05,
155 156 sth_op3 = 0x06,
156 157 std_op3 = 0x07,
157 158 ldsw_op3 = 0x08,
158 159 ldsb_op3 = 0x09,
159 160 ldsh_op3 = 0x0a,
160 161 ldx_op3 = 0x0b,
161 162
162 163 stx_op3 = 0x0e,
163 164 swap_op3 = 0x0f,
164 165
165 166 stwa_op3 = 0x14,
166 167 stxa_op3 = 0x1e,
167 168
168 169 ldf_op3 = 0x20,
169 170 ldfsr_op3 = 0x21,
170 171 ldqf_op3 = 0x22,
171 172 lddf_op3 = 0x23,
172 173 stf_op3 = 0x24,
173 174 stfsr_op3 = 0x25,
174 175 stqf_op3 = 0x26,
175 176 stdf_op3 = 0x27,
176 177
177 178 prefetch_op3 = 0x2d,
178 179
179 180 casa_op3 = 0x3c,
180 181 casxa_op3 = 0x3e,
181 182
182 183 mftoi_op3 = 0x36,
183 184
184 185 alt_bit_op3 = 0x10,
185 186 cc_bit_op3 = 0x10
186 187 };
187 188
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188 189 enum opfs {
189 190 // selected opfs
190 191 edge8n_opf = 0x01,
191 192
192 193 fmovs_opf = 0x01,
193 194 fmovd_opf = 0x02,
194 195
195 196 fnegs_opf = 0x05,
196 197 fnegd_opf = 0x06,
197 198
199 + lzcnt_opf = 0x17,
198 200 alignaddr_opf = 0x18,
199 201 bmask_opf = 0x19,
200 202
201 203 fadds_opf = 0x41,
202 204 faddd_opf = 0x42,
203 205 fsubs_opf = 0x45,
204 206 fsubd_opf = 0x46,
205 207
206 208 faligndata_opf = 0x48,
207 209
208 210 fmuls_opf = 0x49,
209 211 fmuld_opf = 0x4a,
210 212 bshuffle_opf = 0x4c,
211 213 fdivs_opf = 0x4d,
212 214 fdivd_opf = 0x4e,
213 215
214 216 fcmps_opf = 0x51,
215 217 fcmpd_opf = 0x52,
216 218
217 219 fstox_opf = 0x81,
218 220 fdtox_opf = 0x82,
219 221 fxtos_opf = 0x84,
220 222 fxtod_opf = 0x88,
221 223 fitos_opf = 0xc4,
222 224 fdtos_opf = 0xc6,
223 225 fitod_opf = 0xc8,
224 226 fstod_opf = 0xc9,
225 227 fstoi_opf = 0xd1,
226 228 fdtoi_opf = 0xd2,
227 229
228 230 mdtox_opf = 0x110,
229 231 mstouw_opf = 0x111,
230 232 mstosw_opf = 0x113,
231 233 xmulx_opf = 0x115,
232 234 xmulxhi_opf = 0x116,
233 235 mxtod_opf = 0x118,
234 236 mwtos_opf = 0x119,
235 237
236 238 aes_kexpand0_opf = 0x130,
237 239 aes_kexpand2_opf = 0x131,
238 240
239 241 sha1_opf = 0x141,
240 242 sha256_opf = 0x142,
241 243 sha512_opf = 0x143,
242 244
243 245 crc32c_opf = 0x147
244 246 };
245 247
246 248 enum op5s {
247 249 aes_eround01_op5 = 0x00,
248 250 aes_eround23_op5 = 0x01,
249 251 aes_dround01_op5 = 0x02,
250 252 aes_dround23_op5 = 0x03,
251 253 aes_eround01_l_op5 = 0x04,
252 254 aes_eround23_l_op5 = 0x05,
253 255 aes_dround01_l_op5 = 0x06,
254 256 aes_dround23_l_op5 = 0x07,
255 257 aes_kexpand1_op5 = 0x08
256 258 };
257 259
258 260 enum RCondition { rc_z = 1, rc_lez = 2, rc_lz = 3, rc_nz = 5, rc_gz = 6, rc_gez = 7, rc_last = rc_gez };
259 261
260 262 enum Condition {
261 263 // for FBfcc & FBPfcc instruction
262 264 f_never = 0,
263 265 f_notEqual = 1,
264 266 f_notZero = 1,
265 267 f_lessOrGreater = 2,
266 268 f_unorderedOrLess = 3,
267 269 f_less = 4,
268 270 f_unorderedOrGreater = 5,
269 271 f_greater = 6,
270 272 f_unordered = 7,
271 273 f_always = 8,
272 274 f_equal = 9,
273 275 f_zero = 9,
274 276 f_unorderedOrEqual = 10,
275 277 f_greaterOrEqual = 11,
276 278 f_unorderedOrGreaterOrEqual = 12,
277 279 f_lessOrEqual = 13,
278 280 f_unorderedOrLessOrEqual = 14,
279 281 f_ordered = 15,
280 282
281 283 // V8 coproc, pp 123 v8 manual
282 284
283 285 cp_always = 8,
284 286 cp_never = 0,
285 287 cp_3 = 7,
286 288 cp_2 = 6,
287 289 cp_2or3 = 5,
288 290 cp_1 = 4,
289 291 cp_1or3 = 3,
290 292 cp_1or2 = 2,
291 293 cp_1or2or3 = 1,
292 294 cp_0 = 9,
293 295 cp_0or3 = 10,
294 296 cp_0or2 = 11,
295 297 cp_0or2or3 = 12,
296 298 cp_0or1 = 13,
297 299 cp_0or1or3 = 14,
298 300 cp_0or1or2 = 15,
299 301
300 302
301 303 // for integers
302 304
303 305 never = 0,
304 306 equal = 1,
305 307 zero = 1,
306 308 lessEqual = 2,
307 309 less = 3,
308 310 lessEqualUnsigned = 4,
309 311 lessUnsigned = 5,
310 312 carrySet = 5,
311 313 negative = 6,
312 314 overflowSet = 7,
313 315 always = 8,
314 316 notEqual = 9,
315 317 notZero = 9,
316 318 greater = 10,
317 319 greaterEqual = 11,
318 320 greaterUnsigned = 12,
319 321 greaterEqualUnsigned = 13,
320 322 carryClear = 13,
321 323 positive = 14,
322 324 overflowClear = 15
323 325 };
324 326
325 327 enum CC {
326 328 icc = 0, xcc = 2,
327 329 // ptr_cc is the correct condition code for a pointer or intptr_t:
328 330 ptr_cc = NOT_LP64(icc) LP64_ONLY(xcc),
329 331 fcc0 = 0, fcc1 = 1, fcc2 = 2, fcc3 = 3
330 332 };
331 333
332 334 enum PrefetchFcn {
333 335 severalReads = 0, oneRead = 1, severalWritesAndPossiblyReads = 2, oneWrite = 3, page = 4
334 336 };
335 337
336 338 public:
337 339 // Helper functions for groups of instructions
338 340
339 341 enum Predict { pt = 1, pn = 0 }; // pt = predict taken
340 342
341 343 enum Membar_mask_bits { // page 184, v9
342 344 StoreStore = 1 << 3,
343 345 LoadStore = 1 << 2,
344 346 StoreLoad = 1 << 1,
345 347 LoadLoad = 1 << 0,
346 348
347 349 Sync = 1 << 6,
348 350 MemIssue = 1 << 5,
349 351 Lookaside = 1 << 4
350 352 };
351 353
352 354 static bool is_in_wdisp_range(address a, address b, int nbits) {
353 355 intptr_t d = intptr_t(b) - intptr_t(a);
354 356 return is_simm(d, nbits + 2);
355 357 }
356 358
357 359 address target_distance(Label& L) {
358 360 // Assembler::target(L) should be called only when
359 361 // a branch instruction is emitted since non-bound
360 362 // labels record current pc() as a branch address.
361 363 if (L.is_bound()) return target(L);
362 364 // Return current address for non-bound labels.
363 365 return pc();
364 366 }
365 367
366 368 // test if label is in simm16 range in words (wdisp16).
367 369 bool is_in_wdisp16_range(Label& L) {
368 370 return is_in_wdisp_range(target_distance(L), pc(), 16);
369 371 }
370 372 // test if the distance between two addresses fits in simm30 range in words
371 373 static bool is_in_wdisp30_range(address a, address b) {
372 374 return is_in_wdisp_range(a, b, 30);
373 375 }
374 376
375 377 enum ASIs { // page 72, v9
376 378 ASI_PRIMARY = 0x80,
377 379 ASI_PRIMARY_NOFAULT = 0x82,
378 380 ASI_PRIMARY_LITTLE = 0x88,
379 381 // 8x8-bit partial store
380 382 ASI_PST8_PRIMARY = 0xC0,
381 383 // Block initializing store
382 384 ASI_ST_BLKINIT_PRIMARY = 0xE2,
383 385 // Most-Recently-Used (MRU) BIS variant
384 386 ASI_ST_BLKINIT_MRU_PRIMARY = 0xF2
385 387 // add more from book as needed
386 388 };
387 389
388 390 protected:
389 391 // helpers
390 392
391 393 // x is supposed to fit in a field "nbits" wide
392 394 // and be sign-extended. Check the range.
393 395
394 396 static void assert_signed_range(intptr_t x, int nbits) {
395 397 assert(nbits == 32 || (-(1 << nbits-1) <= x && x < ( 1 << nbits-1)),
396 398 "value out of range: x=" INTPTR_FORMAT ", nbits=%d", x, nbits);
397 399 }
398 400
399 401 static void assert_signed_word_disp_range(intptr_t x, int nbits) {
400 402 assert( (x & 3) == 0, "not word aligned");
401 403 assert_signed_range(x, nbits + 2);
402 404 }
403 405
404 406 static void assert_unsigned_const(int x, int nbits) {
405 407 assert( juint(x) < juint(1 << nbits), "unsigned constant out of range");
406 408 }
407 409
408 410 // fields: note bits numbered from LSB = 0,
409 411 // fields known by inclusive bit range
410 412
411 413 static int fmask(juint hi_bit, juint lo_bit) {
412 414 assert( hi_bit >= lo_bit && 0 <= lo_bit && hi_bit < 32, "bad bits");
413 415 return (1 << ( hi_bit-lo_bit + 1 )) - 1;
414 416 }
415 417
416 418 // inverse of u_field
417 419
418 420 static int inv_u_field(int x, int hi_bit, int lo_bit) {
419 421 juint r = juint(x) >> lo_bit;
420 422 r &= fmask( hi_bit, lo_bit);
421 423 return int(r);
422 424 }
423 425
424 426
425 427 // signed version: extract from field and sign-extend
426 428
427 429 static int inv_s_field(int x, int hi_bit, int lo_bit) {
428 430 int sign_shift = 31 - hi_bit;
429 431 return inv_u_field( ((x << sign_shift) >> sign_shift), hi_bit, lo_bit);
430 432 }
431 433
432 434 // given a field that ranges from hi_bit to lo_bit (inclusive,
433 435 // LSB = 0), and an unsigned value for the field,
434 436 // shift it into the field
435 437
436 438 #ifdef ASSERT
437 439 static int u_field(int x, int hi_bit, int lo_bit) {
438 440 assert( ( x & ~fmask(hi_bit, lo_bit)) == 0,
439 441 "value out of range");
440 442 int r = x << lo_bit;
441 443 assert( inv_u_field(r, hi_bit, lo_bit) == x, "just checking");
442 444 return r;
443 445 }
444 446 #else
445 447 // make sure this is inlined as it will reduce code size significantly
446 448 #define u_field(x, hi_bit, lo_bit) ((x) << (lo_bit))
447 449 #endif
448 450
449 451 static int inv_op( int x ) { return inv_u_field(x, 31, 30); }
450 452 static int inv_op2( int x ) { return inv_u_field(x, 24, 22); }
451 453 static int inv_op3( int x ) { return inv_u_field(x, 24, 19); }
452 454 static int inv_cond( int x ){ return inv_u_field(x, 28, 25); }
453 455
454 456 static bool inv_immed( int x ) { return (x & Assembler::immed(true)) != 0; }
455 457
456 458 static Register inv_rd( int x ) { return as_Register(inv_u_field(x, 29, 25)); }
457 459 static Register inv_rs1( int x ) { return as_Register(inv_u_field(x, 18, 14)); }
458 460 static Register inv_rs2( int x ) { return as_Register(inv_u_field(x, 4, 0)); }
459 461
460 462 static int op( int x) { return u_field(x, 31, 30); }
461 463 static int rd( Register r) { return u_field(r->encoding(), 29, 25); }
462 464 static int fcn( int x) { return u_field(x, 29, 25); }
463 465 static int op3( int x) { return u_field(x, 24, 19); }
464 466 static int rs1( Register r) { return u_field(r->encoding(), 18, 14); }
465 467 static int rs2( Register r) { return u_field(r->encoding(), 4, 0); }
466 468 static int annul( bool a) { return u_field(a ? 1 : 0, 29, 29); }
467 469 static int cond( int x) { return u_field(x, 28, 25); }
468 470 static int cond_mov( int x) { return u_field(x, 17, 14); }
469 471 static int rcond( RCondition x) { return u_field(x, 12, 10); }
470 472 static int op2( int x) { return u_field(x, 24, 22); }
471 473 static int predict( bool p) { return u_field(p ? 1 : 0, 19, 19); }
472 474 static int branchcc( CC fcca) { return u_field(fcca, 21, 20); }
473 475 static int cmpcc( CC fcca) { return u_field(fcca, 26, 25); }
474 476 static int imm_asi( int x) { return u_field(x, 12, 5); }
475 477 static int immed( bool i) { return u_field(i ? 1 : 0, 13, 13); }
476 478 static int opf_low6( int w) { return u_field(w, 10, 5); }
477 479 static int opf_low5( int w) { return u_field(w, 9, 5); }
478 480 static int op5( int x) { return u_field(x, 8, 5); }
479 481 static int trapcc( CC cc) { return u_field(cc, 12, 11); }
480 482 static int sx( int i) { return u_field(i, 12, 12); } // shift x=1 means 64-bit
481 483 static int opf( int x) { return u_field(x, 13, 5); }
482 484
483 485 static bool is_cbcond( int x ) {
484 486 return (VM_Version::has_cbcond() && (inv_cond(x) > rc_last) &&
485 487 inv_op(x) == branch_op && inv_op2(x) == bpr_op2);
486 488 }
487 489 static bool is_cxb( int x ) {
488 490 assert(is_cbcond(x), "wrong instruction");
489 491 return (x & (1<<21)) != 0;
490 492 }
491 493 static int cond_cbcond( int x) { return u_field((((x & 8)<<1) + 8 + (x & 7)), 29, 25); }
492 494 static int inv_cond_cbcond(int x) {
493 495 assert(is_cbcond(x), "wrong instruction");
494 496 return inv_u_field(x, 27, 25) | (inv_u_field(x, 29, 29)<<3);
495 497 }
496 498
497 499 static int opf_cc( CC c, bool useFloat ) { return u_field((useFloat ? 0 : 4) + c, 13, 11); }
498 500 static int mov_cc( CC c, bool useFloat ) { return u_field(useFloat ? 0 : 1, 18, 18) | u_field(c, 12, 11); }
499 501
500 502 static int fd( FloatRegister r, FloatRegisterImpl::Width fwa) { return u_field(r->encoding(fwa), 29, 25); };
501 503 static int fs1(FloatRegister r, FloatRegisterImpl::Width fwa) { return u_field(r->encoding(fwa), 18, 14); };
502 504 static int fs2(FloatRegister r, FloatRegisterImpl::Width fwa) { return u_field(r->encoding(fwa), 4, 0); };
503 505 static int fs3(FloatRegister r, FloatRegisterImpl::Width fwa) { return u_field(r->encoding(fwa), 13, 9); };
504 506
505 507 // some float instructions use this encoding on the op3 field
506 508 static int alt_op3(int op, FloatRegisterImpl::Width w) {
507 509 int r;
508 510 switch(w) {
509 511 case FloatRegisterImpl::S: r = op + 0; break;
510 512 case FloatRegisterImpl::D: r = op + 3; break;
511 513 case FloatRegisterImpl::Q: r = op + 2; break;
512 514 default: ShouldNotReachHere(); break;
513 515 }
514 516 return op3(r);
515 517 }
516 518
517 519
518 520 // compute inverse of simm
519 521 static int inv_simm(int x, int nbits) {
520 522 return (int)(x << (32 - nbits)) >> (32 - nbits);
521 523 }
522 524
523 525 static int inv_simm13( int x ) { return inv_simm(x, 13); }
524 526
525 527 // signed immediate, in low bits, nbits long
526 528 static int simm(int x, int nbits) {
527 529 assert_signed_range(x, nbits);
528 530 return x & (( 1 << nbits ) - 1);
529 531 }
530 532
531 533 // compute inverse of wdisp16
532 534 static intptr_t inv_wdisp16(int x, intptr_t pos) {
533 535 int lo = x & (( 1 << 14 ) - 1);
534 536 int hi = (x >> 20) & 3;
535 537 if (hi >= 2) hi |= ~1;
536 538 return (((hi << 14) | lo) << 2) + pos;
537 539 }
538 540
539 541 // word offset, 14 bits at LSend, 2 bits at B21, B20
540 542 static int wdisp16(intptr_t x, intptr_t off) {
541 543 intptr_t xx = x - off;
542 544 assert_signed_word_disp_range(xx, 16);
543 545 int r = (xx >> 2) & ((1 << 14) - 1)
544 546 | ( ( (xx>>(2+14)) & 3 ) << 20 );
545 547 assert( inv_wdisp16(r, off) == x, "inverse is not inverse");
546 548 return r;
547 549 }
548 550
549 551 // compute inverse of wdisp10
550 552 static intptr_t inv_wdisp10(int x, intptr_t pos) {
551 553 assert(is_cbcond(x), "wrong instruction");
552 554 int lo = inv_u_field(x, 12, 5);
553 555 int hi = (x >> 19) & 3;
554 556 if (hi >= 2) hi |= ~1;
555 557 return (((hi << 8) | lo) << 2) + pos;
556 558 }
557 559
558 560 // word offset for cbcond, 8 bits at [B12,B5], 2 bits at [B20,B19]
559 561 static int wdisp10(intptr_t x, intptr_t off) {
560 562 assert(VM_Version::has_cbcond(), "This CPU does not have CBCOND instruction");
561 563 intptr_t xx = x - off;
562 564 assert_signed_word_disp_range(xx, 10);
563 565 int r = ( ( (xx >> 2 ) & ((1 << 8) - 1) ) << 5 )
564 566 | ( ( (xx >> (2+8)) & 3 ) << 19 );
565 567 // Have to fake cbcond instruction to pass assert in inv_wdisp10()
566 568 assert(inv_wdisp10((r | op(branch_op) | cond_cbcond(rc_last+1) | op2(bpr_op2)), off) == x, "inverse is not inverse");
567 569 return r;
568 570 }
569 571
570 572 // word displacement in low-order nbits bits
571 573
572 574 static intptr_t inv_wdisp( int x, intptr_t pos, int nbits ) {
573 575 int pre_sign_extend = x & (( 1 << nbits ) - 1);
574 576 int r = pre_sign_extend >= ( 1 << (nbits-1) )
575 577 ? pre_sign_extend | ~(( 1 << nbits ) - 1)
576 578 : pre_sign_extend;
577 579 return (r << 2) + pos;
578 580 }
579 581
580 582 static int wdisp( intptr_t x, intptr_t off, int nbits ) {
581 583 intptr_t xx = x - off;
582 584 assert_signed_word_disp_range(xx, nbits);
583 585 int r = (xx >> 2) & (( 1 << nbits ) - 1);
584 586 assert( inv_wdisp( r, off, nbits ) == x, "inverse not inverse");
585 587 return r;
586 588 }
587 589
588 590
589 591 // Extract the top 32 bits in a 64 bit word
590 592 static int32_t hi32( int64_t x ) {
591 593 int32_t r = int32_t( (uint64_t)x >> 32 );
592 594 return r;
593 595 }
594 596
595 597 // given a sethi instruction, extract the constant, left-justified
596 598 static int inv_hi22( int x ) {
597 599 return x << 10;
598 600 }
599 601
600 602 // create an imm22 field, given a 32-bit left-justified constant
601 603 static int hi22( int x ) {
602 604 int r = int( juint(x) >> 10 );
603 605 assert( (r & ~((1 << 22) - 1)) == 0, "just checkin'");
604 606 return r;
605 607 }
606 608
607 609 // create a low10 __value__ (not a field) for a given a 32-bit constant
608 610 static int low10( int x ) {
609 611 return x & ((1 << 10) - 1);
610 612 }
611 613
612 614 // create a low12 __value__ (not a field) for a given a 32-bit constant
613 615 static int low12( int x ) {
614 616 return x & ((1 << 12) - 1);
615 617 }
616 618
617 619 // AES crypto instructions supported only on certain processors
618 620 static void aes_only() { assert( VM_Version::has_aes(), "This instruction only works on SPARC with AES instructions support"); }
619 621
620 622 // SHA crypto instructions supported only on certain processors
621 623 static void sha1_only() { assert( VM_Version::has_sha1(), "This instruction only works on SPARC with SHA1"); }
622 624 static void sha256_only() { assert( VM_Version::has_sha256(), "This instruction only works on SPARC with SHA256"); }
623 625 static void sha512_only() { assert( VM_Version::has_sha512(), "This instruction only works on SPARC with SHA512"); }
624 626
625 627 // CRC32C instruction supported only on certain processors
626 628 static void crc32c_only() { assert( VM_Version::has_crc32c(), "This instruction only works on SPARC with CRC32C"); }
627 629
628 630 // instruction only in VIS1
629 631 static void vis1_only() { assert( VM_Version::has_vis1(), "This instruction only works on SPARC with VIS1"); }
630 632
631 633 // instruction only in VIS2
632 634 static void vis2_only() { assert( VM_Version::has_vis2(), "This instruction only works on SPARC with VIS2"); }
633 635
634 636 // instruction only in VIS3
635 637 static void vis3_only() { assert( VM_Version::has_vis3(), "This instruction only works on SPARC with VIS3"); }
636 638
637 639 // instruction only in v9
638 640 static void v9_only() { } // do nothing
639 641
640 642 // instruction deprecated in v9
641 643 static void v9_dep() { } // do nothing for now
642 644
643 645 // v8 has no CC field
644 646 static void v8_no_cc(CC cc) { if (cc) v9_only(); }
645 647
646 648 protected:
647 649 // Simple delay-slot scheme:
648 650 // In order to check the programmer, the assembler keeps track of deley slots.
649 651 // It forbids CTIs in delay slots (conservative, but should be OK).
650 652 // Also, when putting an instruction into a delay slot, you must say
651 653 // asm->delayed()->add(...), in order to check that you don't omit
652 654 // delay-slot instructions.
653 655 // To implement this, we use a simple FSA
654 656
655 657 #ifdef ASSERT
656 658 #define CHECK_DELAY
657 659 #endif
658 660 #ifdef CHECK_DELAY
659 661 enum Delay_state { no_delay, at_delay_slot, filling_delay_slot } delay_state;
660 662 #endif
661 663
662 664 public:
663 665 // Tells assembler next instruction must NOT be in delay slot.
664 666 // Use at start of multinstruction macros.
665 667 void assert_not_delayed() {
666 668 // This is a separate overloading to avoid creation of string constants
667 669 // in non-asserted code--with some compilers this pollutes the object code.
668 670 #ifdef CHECK_DELAY
669 671 assert_not_delayed("next instruction should not be a delay slot");
670 672 #endif
671 673 }
672 674 void assert_not_delayed(const char* msg) {
673 675 #ifdef CHECK_DELAY
674 676 assert(delay_state == no_delay, msg);
675 677 #endif
676 678 }
677 679
678 680 protected:
679 681 // Insert a nop if the previous is cbcond
680 682 inline void insert_nop_after_cbcond();
681 683
682 684 // Delay slot helpers
683 685 // cti is called when emitting control-transfer instruction,
684 686 // BEFORE doing the emitting.
685 687 // Only effective when assertion-checking is enabled.
686 688 void cti() {
687 689 // A cbcond instruction immediately followed by a CTI
688 690 // instruction introduces pipeline stalls, we need to avoid that.
689 691 no_cbcond_before();
690 692 #ifdef CHECK_DELAY
691 693 assert_not_delayed("cti should not be in delay slot");
692 694 #endif
693 695 }
694 696
695 697 // called when emitting cti with a delay slot, AFTER emitting
696 698 void has_delay_slot() {
697 699 #ifdef CHECK_DELAY
698 700 assert_not_delayed("just checking");
699 701 delay_state = at_delay_slot;
700 702 #endif
701 703 }
702 704
703 705 // cbcond instruction should not be generated one after an other
704 706 bool cbcond_before() {
705 707 if (offset() == 0) return false; // it is first instruction
706 708 int x = *(int*)(intptr_t(pc()) - 4); // previous instruction
707 709 return is_cbcond(x);
708 710 }
709 711
710 712 void no_cbcond_before() {
711 713 assert(offset() == 0 || !cbcond_before(), "cbcond should not follow an other cbcond");
712 714 }
713 715 public:
714 716
715 717 bool use_cbcond(Label& L) {
716 718 if (!UseCBCond || cbcond_before()) return false;
717 719 intptr_t x = intptr_t(target_distance(L)) - intptr_t(pc());
718 720 assert( (x & 3) == 0, "not word aligned");
719 721 return is_simm12(x);
720 722 }
721 723
722 724 // Tells assembler you know that next instruction is delayed
723 725 Assembler* delayed() {
724 726 #ifdef CHECK_DELAY
725 727 assert ( delay_state == at_delay_slot, "delayed instruction is not in delay slot");
726 728 delay_state = filling_delay_slot;
727 729 #endif
728 730 return this;
729 731 }
730 732
731 733 void flush() {
732 734 #ifdef CHECK_DELAY
733 735 assert ( delay_state == no_delay, "ending code with a delay slot");
734 736 #endif
735 737 AbstractAssembler::flush();
736 738 }
737 739
738 740 inline void emit_int32(int); // shadows AbstractAssembler::emit_int32
739 741 inline void emit_data(int x);
740 742 inline void emit_data(int, RelocationHolder const&);
741 743 inline void emit_data(int, relocInfo::relocType rtype);
742 744 // helper for above fcns
743 745 inline void check_delay();
744 746
745 747
746 748 public:
747 749 // instructions, refer to page numbers in the SPARC Architecture Manual, V9
748 750
749 751 // pp 135 (addc was addx in v8)
750 752
751 753 inline void add(Register s1, Register s2, Register d );
752 754 inline void add(Register s1, int simm13a, Register d );
753 755
754 756 inline void addcc( Register s1, Register s2, Register d );
755 757 inline void addcc( Register s1, int simm13a, Register d );
756 758 inline void addc( Register s1, Register s2, Register d );
757 759 inline void addc( Register s1, int simm13a, Register d );
758 760 inline void addccc( Register s1, Register s2, Register d );
759 761 inline void addccc( Register s1, int simm13a, Register d );
760 762
761 763
762 764 // 4-operand AES instructions
763 765
764 766 inline void aes_eround01( FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d );
765 767 inline void aes_eround23( FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d );
766 768 inline void aes_dround01( FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d );
767 769 inline void aes_dround23( FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d );
768 770 inline void aes_eround01_l( FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d );
769 771 inline void aes_eround23_l( FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d );
770 772 inline void aes_dround01_l( FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d );
771 773 inline void aes_dround23_l( FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d );
772 774 inline void aes_kexpand1( FloatRegister s1, FloatRegister s2, int imm5a, FloatRegister d );
773 775
774 776
775 777 // 3-operand AES instructions
776 778
777 779 inline void aes_kexpand0( FloatRegister s1, FloatRegister s2, FloatRegister d );
778 780 inline void aes_kexpand2( FloatRegister s1, FloatRegister s2, FloatRegister d );
779 781
780 782 // pp 136
781 783
782 784 inline void bpr(RCondition c, bool a, Predict p, Register s1, address d, relocInfo::relocType rt = relocInfo::none);
783 785 inline void bpr(RCondition c, bool a, Predict p, Register s1, Label& L);
784 786
785 787 // compare and branch
786 788 inline void cbcond(Condition c, CC cc, Register s1, Register s2, Label& L);
787 789 inline void cbcond(Condition c, CC cc, Register s1, int simm5, Label& L);
788 790
789 791 protected: // use MacroAssembler::br instead
790 792
791 793 // pp 138
792 794
793 795 inline void fb( Condition c, bool a, address d, relocInfo::relocType rt = relocInfo::none );
794 796 inline void fb( Condition c, bool a, Label& L );
795 797
796 798 // pp 141
797 799
798 800 inline void fbp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt = relocInfo::none );
799 801 inline void fbp( Condition c, bool a, CC cc, Predict p, Label& L );
800 802
801 803 // pp 144
802 804
803 805 inline void br( Condition c, bool a, address d, relocInfo::relocType rt = relocInfo::none );
804 806 inline void br( Condition c, bool a, Label& L );
805 807
806 808 // pp 146
807 809
808 810 inline void bp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt = relocInfo::none );
809 811 inline void bp( Condition c, bool a, CC cc, Predict p, Label& L );
810 812
811 813 // pp 149
812 814
813 815 inline void call( address d, relocInfo::relocType rt = relocInfo::runtime_call_type );
814 816 inline void call( Label& L, relocInfo::relocType rt = relocInfo::runtime_call_type );
815 817
816 818 inline void call( address d, RelocationHolder const& rspec );
817 819
818 820 public:
819 821
820 822 // pp 150
821 823
822 824 // These instructions compare the contents of s2 with the contents of
823 825 // memory at address in s1. If the values are equal, the contents of memory
824 826 // at address s1 is swapped with the data in d. If the values are not equal,
825 827 // the the contents of memory at s1 is loaded into d, without the swap.
826 828
827 829 inline void casa( Register s1, Register s2, Register d, int ia = -1 );
828 830 inline void casxa( Register s1, Register s2, Register d, int ia = -1 );
829 831
830 832 // pp 152
831 833
832 834 inline void udiv( Register s1, Register s2, Register d );
833 835 inline void udiv( Register s1, int simm13a, Register d );
834 836 inline void sdiv( Register s1, Register s2, Register d );
835 837 inline void sdiv( Register s1, int simm13a, Register d );
836 838 inline void udivcc( Register s1, Register s2, Register d );
837 839 inline void udivcc( Register s1, int simm13a, Register d );
838 840 inline void sdivcc( Register s1, Register s2, Register d );
839 841 inline void sdivcc( Register s1, int simm13a, Register d );
840 842
841 843 // pp 155
842 844
843 845 inline void done();
844 846 inline void retry();
845 847
846 848 // pp 156
847 849
848 850 inline void fadd( FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d );
849 851 inline void fsub( FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d );
850 852
851 853 // pp 157
852 854
853 855 inline void fcmp( FloatRegisterImpl::Width w, CC cc, FloatRegister s1, FloatRegister s2);
854 856 inline void fcmpe( FloatRegisterImpl::Width w, CC cc, FloatRegister s1, FloatRegister s2);
855 857
856 858 // pp 159
857 859
858 860 inline void ftox( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d );
859 861 inline void ftoi( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d );
860 862
861 863 // pp 160
862 864
863 865 inline void ftof( FloatRegisterImpl::Width sw, FloatRegisterImpl::Width dw, FloatRegister s, FloatRegister d );
864 866
865 867 // pp 161
866 868
867 869 inline void fxtof( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d );
868 870 inline void fitof( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d );
869 871
870 872 // pp 162
871 873
872 874 inline void fmov( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d );
873 875
874 876 inline void fneg( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d );
875 877
876 878 inline void fabs( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d );
877 879
878 880 // pp 163
879 881
880 882 inline void fmul( FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d );
881 883 inline void fmul( FloatRegisterImpl::Width sw, FloatRegisterImpl::Width dw, FloatRegister s1, FloatRegister s2, FloatRegister d );
882 884 inline void fdiv( FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d );
883 885
884 886 // FXORs/FXORd instructions
885 887
886 888 inline void fxor( FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d );
887 889
888 890 // pp 164
889 891
890 892 inline void fsqrt( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d );
891 893
892 894 // pp 165
893 895
894 896 inline void flush( Register s1, Register s2 );
895 897 inline void flush( Register s1, int simm13a);
896 898
897 899 // pp 167
898 900
899 901 void flushw();
900 902
901 903 // pp 168
902 904
903 905 void illtrap( int const22a);
904 906 // v8 unimp == illtrap(0)
905 907
906 908 // pp 169
907 909
908 910 void impdep1( int id1, int const19a );
909 911 void impdep2( int id1, int const19a );
910 912
911 913 // pp 170
912 914
913 915 void jmpl( Register s1, Register s2, Register d );
914 916 void jmpl( Register s1, int simm13a, Register d, RelocationHolder const& rspec = RelocationHolder() );
915 917
916 918 // 171
917 919
918 920 inline void ldf(FloatRegisterImpl::Width w, Register s1, Register s2, FloatRegister d);
919 921 inline void ldf(FloatRegisterImpl::Width w, Register s1, int simm13a, FloatRegister d, RelocationHolder const& rspec = RelocationHolder());
920 922
921 923
922 924 inline void ldfsr( Register s1, Register s2 );
923 925 inline void ldfsr( Register s1, int simm13a);
924 926 inline void ldxfsr( Register s1, Register s2 );
925 927 inline void ldxfsr( Register s1, int simm13a);
926 928
927 929 // 173
928 930
929 931 inline void ldfa( FloatRegisterImpl::Width w, Register s1, Register s2, int ia, FloatRegister d );
930 932 inline void ldfa( FloatRegisterImpl::Width w, Register s1, int simm13a, FloatRegister d );
931 933
932 934 // pp 175, lduw is ld on v8
933 935
934 936 inline void ldsb( Register s1, Register s2, Register d );
935 937 inline void ldsb( Register s1, int simm13a, Register d);
936 938 inline void ldsh( Register s1, Register s2, Register d );
937 939 inline void ldsh( Register s1, int simm13a, Register d);
938 940 inline void ldsw( Register s1, Register s2, Register d );
939 941 inline void ldsw( Register s1, int simm13a, Register d);
940 942 inline void ldub( Register s1, Register s2, Register d );
941 943 inline void ldub( Register s1, int simm13a, Register d);
942 944 inline void lduh( Register s1, Register s2, Register d );
943 945 inline void lduh( Register s1, int simm13a, Register d);
944 946 inline void lduw( Register s1, Register s2, Register d );
945 947 inline void lduw( Register s1, int simm13a, Register d);
946 948 inline void ldx( Register s1, Register s2, Register d );
947 949 inline void ldx( Register s1, int simm13a, Register d);
948 950 inline void ldd( Register s1, Register s2, Register d );
949 951 inline void ldd( Register s1, int simm13a, Register d);
950 952
951 953 // pp 177
952 954
953 955 inline void ldsba( Register s1, Register s2, int ia, Register d );
954 956 inline void ldsba( Register s1, int simm13a, Register d );
955 957 inline void ldsha( Register s1, Register s2, int ia, Register d );
956 958 inline void ldsha( Register s1, int simm13a, Register d );
957 959 inline void ldswa( Register s1, Register s2, int ia, Register d );
958 960 inline void ldswa( Register s1, int simm13a, Register d );
959 961 inline void lduba( Register s1, Register s2, int ia, Register d );
960 962 inline void lduba( Register s1, int simm13a, Register d );
961 963 inline void lduha( Register s1, Register s2, int ia, Register d );
962 964 inline void lduha( Register s1, int simm13a, Register d );
963 965 inline void lduwa( Register s1, Register s2, int ia, Register d );
964 966 inline void lduwa( Register s1, int simm13a, Register d );
965 967 inline void ldxa( Register s1, Register s2, int ia, Register d );
966 968 inline void ldxa( Register s1, int simm13a, Register d );
967 969
968 970 // pp 181
969 971
970 972 inline void and3( Register s1, Register s2, Register d );
971 973 inline void and3( Register s1, int simm13a, Register d );
972 974 inline void andcc( Register s1, Register s2, Register d );
973 975 inline void andcc( Register s1, int simm13a, Register d );
974 976 inline void andn( Register s1, Register s2, Register d );
975 977 inline void andn( Register s1, int simm13a, Register d );
976 978 inline void andncc( Register s1, Register s2, Register d );
977 979 inline void andncc( Register s1, int simm13a, Register d );
978 980 inline void or3( Register s1, Register s2, Register d );
979 981 inline void or3( Register s1, int simm13a, Register d );
980 982 inline void orcc( Register s1, Register s2, Register d );
981 983 inline void orcc( Register s1, int simm13a, Register d );
982 984 inline void orn( Register s1, Register s2, Register d );
983 985 inline void orn( Register s1, int simm13a, Register d );
984 986 inline void orncc( Register s1, Register s2, Register d );
985 987 inline void orncc( Register s1, int simm13a, Register d );
986 988 inline void xor3( Register s1, Register s2, Register d );
987 989 inline void xor3( Register s1, int simm13a, Register d );
988 990 inline void xorcc( Register s1, Register s2, Register d );
989 991 inline void xorcc( Register s1, int simm13a, Register d );
990 992 inline void xnor( Register s1, Register s2, Register d );
991 993 inline void xnor( Register s1, int simm13a, Register d );
992 994 inline void xnorcc( Register s1, Register s2, Register d );
993 995 inline void xnorcc( Register s1, int simm13a, Register d );
994 996
995 997 // pp 183
996 998
997 999 inline void membar( Membar_mask_bits const7a );
998 1000
999 1001 // pp 185
1000 1002
1001 1003 inline void fmov( FloatRegisterImpl::Width w, Condition c, bool floatCC, CC cca, FloatRegister s2, FloatRegister d );
1002 1004
1003 1005 // pp 189
1004 1006
1005 1007 inline void fmov( FloatRegisterImpl::Width w, RCondition c, Register s1, FloatRegister s2, FloatRegister d );
1006 1008
1007 1009 // pp 191
1008 1010
1009 1011 inline void movcc( Condition c, bool floatCC, CC cca, Register s2, Register d );
1010 1012 inline void movcc( Condition c, bool floatCC, CC cca, int simm11a, Register d );
1011 1013
1012 1014 // pp 195
1013 1015
1014 1016 inline void movr( RCondition c, Register s1, Register s2, Register d );
1015 1017 inline void movr( RCondition c, Register s1, int simm10a, Register d );
1016 1018
1017 1019 // pp 196
1018 1020
1019 1021 inline void mulx( Register s1, Register s2, Register d );
1020 1022 inline void mulx( Register s1, int simm13a, Register d );
1021 1023 inline void sdivx( Register s1, Register s2, Register d );
1022 1024 inline void sdivx( Register s1, int simm13a, Register d );
1023 1025 inline void udivx( Register s1, Register s2, Register d );
1024 1026 inline void udivx( Register s1, int simm13a, Register d );
1025 1027
1026 1028 // pp 197
1027 1029
1028 1030 inline void umul( Register s1, Register s2, Register d );
1029 1031 inline void umul( Register s1, int simm13a, Register d );
1030 1032 inline void smul( Register s1, Register s2, Register d );
1031 1033 inline void smul( Register s1, int simm13a, Register d );
1032 1034 inline void umulcc( Register s1, Register s2, Register d );
1033 1035 inline void umulcc( Register s1, int simm13a, Register d );
1034 1036 inline void smulcc( Register s1, Register s2, Register d );
1035 1037 inline void smulcc( Register s1, int simm13a, Register d );
1036 1038
1037 1039 // pp 201
1038 1040
1039 1041 inline void nop();
1040 1042
1041 1043 inline void sw_count();
1042 1044
1043 1045 // pp 202
1044 1046
1045 1047 inline void popc( Register s, Register d);
1046 1048 inline void popc( int simm13a, Register d);
1047 1049
1048 1050 // pp 203
1049 1051
1050 1052 inline void prefetch( Register s1, Register s2, PrefetchFcn f);
1051 1053 inline void prefetch( Register s1, int simm13a, PrefetchFcn f);
1052 1054
1053 1055 inline void prefetcha( Register s1, Register s2, int ia, PrefetchFcn f );
1054 1056 inline void prefetcha( Register s1, int simm13a, PrefetchFcn f );
1055 1057
1056 1058 // pp 208
1057 1059
1058 1060 // not implementing read privileged register
1059 1061
1060 1062 inline void rdy( Register d);
1061 1063 inline void rdccr( Register d);
1062 1064 inline void rdasi( Register d);
1063 1065 inline void rdtick( Register d);
1064 1066 inline void rdpc( Register d);
1065 1067 inline void rdfprs( Register d);
1066 1068
1067 1069 // pp 213
1068 1070
1069 1071 inline void rett( Register s1, Register s2);
1070 1072 inline void rett( Register s1, int simm13a, relocInfo::relocType rt = relocInfo::none);
1071 1073
1072 1074 // pp 214
1073 1075
1074 1076 inline void save( Register s1, Register s2, Register d );
1075 1077 inline void save( Register s1, int simm13a, Register d );
1076 1078
1077 1079 inline void restore( Register s1 = G0, Register s2 = G0, Register d = G0 );
1078 1080 inline void restore( Register s1, int simm13a, Register d );
1079 1081
1080 1082 // pp 216
1081 1083
1082 1084 inline void saved();
1083 1085 inline void restored();
1084 1086
1085 1087 // pp 217
1086 1088
1087 1089 inline void sethi( int imm22a, Register d, RelocationHolder const& rspec = RelocationHolder() );
1088 1090 // pp 218
1089 1091
1090 1092 inline void sll( Register s1, Register s2, Register d );
1091 1093 inline void sll( Register s1, int imm5a, Register d );
1092 1094 inline void srl( Register s1, Register s2, Register d );
1093 1095 inline void srl( Register s1, int imm5a, Register d );
1094 1096 inline void sra( Register s1, Register s2, Register d );
1095 1097 inline void sra( Register s1, int imm5a, Register d );
1096 1098
1097 1099 inline void sllx( Register s1, Register s2, Register d );
1098 1100 inline void sllx( Register s1, int imm6a, Register d );
1099 1101 inline void srlx( Register s1, Register s2, Register d );
1100 1102 inline void srlx( Register s1, int imm6a, Register d );
1101 1103 inline void srax( Register s1, Register s2, Register d );
1102 1104 inline void srax( Register s1, int imm6a, Register d );
1103 1105
1104 1106 // pp 220
1105 1107
1106 1108 inline void sir( int simm13a );
1107 1109
1108 1110 // pp 221
1109 1111
1110 1112 inline void stbar();
1111 1113
1112 1114 // pp 222
1113 1115
1114 1116 inline void stf( FloatRegisterImpl::Width w, FloatRegister d, Register s1, Register s2);
1115 1117 inline void stf( FloatRegisterImpl::Width w, FloatRegister d, Register s1, int simm13a);
1116 1118
1117 1119 inline void stfsr( Register s1, Register s2 );
1118 1120 inline void stfsr( Register s1, int simm13a);
1119 1121 inline void stxfsr( Register s1, Register s2 );
1120 1122 inline void stxfsr( Register s1, int simm13a);
1121 1123
1122 1124 // pp 224
1123 1125
1124 1126 inline void stfa( FloatRegisterImpl::Width w, FloatRegister d, Register s1, Register s2, int ia );
1125 1127 inline void stfa( FloatRegisterImpl::Width w, FloatRegister d, Register s1, int simm13a );
1126 1128
1127 1129 // p 226
1128 1130
1129 1131 inline void stb( Register d, Register s1, Register s2 );
1130 1132 inline void stb( Register d, Register s1, int simm13a);
1131 1133 inline void sth( Register d, Register s1, Register s2 );
1132 1134 inline void sth( Register d, Register s1, int simm13a);
1133 1135 inline void stw( Register d, Register s1, Register s2 );
1134 1136 inline void stw( Register d, Register s1, int simm13a);
1135 1137 inline void stx( Register d, Register s1, Register s2 );
1136 1138 inline void stx( Register d, Register s1, int simm13a);
1137 1139 inline void std( Register d, Register s1, Register s2 );
1138 1140 inline void std( Register d, Register s1, int simm13a);
1139 1141
1140 1142 // pp 177
1141 1143
1142 1144 inline void stba( Register d, Register s1, Register s2, int ia );
1143 1145 inline void stba( Register d, Register s1, int simm13a );
1144 1146 inline void stha( Register d, Register s1, Register s2, int ia );
1145 1147 inline void stha( Register d, Register s1, int simm13a );
1146 1148 inline void stwa( Register d, Register s1, Register s2, int ia );
1147 1149 inline void stwa( Register d, Register s1, int simm13a );
1148 1150 inline void stxa( Register d, Register s1, Register s2, int ia );
1149 1151 inline void stxa( Register d, Register s1, int simm13a );
1150 1152 inline void stda( Register d, Register s1, Register s2, int ia );
1151 1153 inline void stda( Register d, Register s1, int simm13a );
1152 1154
1153 1155 // pp 230
1154 1156
1155 1157 inline void sub( Register s1, Register s2, Register d );
1156 1158 inline void sub( Register s1, int simm13a, Register d );
1157 1159
1158 1160 inline void subcc( Register s1, Register s2, Register d );
1159 1161 inline void subcc( Register s1, int simm13a, Register d );
1160 1162 inline void subc( Register s1, Register s2, Register d );
1161 1163 inline void subc( Register s1, int simm13a, Register d );
1162 1164 inline void subccc( Register s1, Register s2, Register d );
1163 1165 inline void subccc( Register s1, int simm13a, Register d );
1164 1166
1165 1167 // pp 231
1166 1168
1167 1169 inline void swap( Register s1, Register s2, Register d );
1168 1170 inline void swap( Register s1, int simm13a, Register d);
1169 1171
1170 1172 // pp 232
1171 1173
1172 1174 inline void swapa( Register s1, Register s2, int ia, Register d );
1173 1175 inline void swapa( Register s1, int simm13a, Register d );
1174 1176
1175 1177 // pp 234, note op in book is wrong, see pp 268
1176 1178
1177 1179 inline void taddcc( Register s1, Register s2, Register d );
1178 1180 inline void taddcc( Register s1, int simm13a, Register d );
1179 1181
1180 1182 // pp 235
1181 1183
1182 1184 inline void tsubcc( Register s1, Register s2, Register d );
1183 1185 inline void tsubcc( Register s1, int simm13a, Register d );
1184 1186
1185 1187 // pp 237
1186 1188
1187 1189 inline void trap( Condition c, CC cc, Register s1, Register s2 );
1188 1190 inline void trap( Condition c, CC cc, Register s1, int trapa );
1189 1191 // simple uncond. trap
1190 1192 inline void trap( int trapa );
1191 1193
1192 1194 // pp 239 omit write priv register for now
1193 1195
1194 1196 inline void wry( Register d);
1195 1197 inline void wrccr(Register s);
1196 1198 inline void wrccr(Register s, int simm13a);
1197 1199 inline void wrasi(Register d);
1198 1200 // wrasi(d, imm) stores (d xor imm) to asi
1199 1201 inline void wrasi(Register d, int simm13a);
1200 1202 inline void wrfprs( Register d);
1201 1203
1202 1204 // VIS1 instructions
1203 1205
1204 1206 inline void alignaddr( Register s1, Register s2, Register d );
1205 1207
1206 1208 inline void faligndata( FloatRegister s1, FloatRegister s2, FloatRegister d );
1207 1209
1208 1210 inline void fzero( FloatRegisterImpl::Width w, FloatRegister d );
1209 1211
1210 1212 inline void fsrc2( FloatRegisterImpl::Width w, FloatRegister s2, FloatRegister d );
1211 1213
1212 1214 inline void fnot1( FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister d );
1213 1215
1214 1216 inline void fpmerge( FloatRegister s1, FloatRegister s2, FloatRegister d );
1215 1217
1216 1218 inline void stpartialf( Register s1, Register s2, FloatRegister d, int ia = -1 );
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1217 1219
1218 1220 // VIS2 instructions
1219 1221
1220 1222 inline void edge8n( Register s1, Register s2, Register d );
1221 1223
1222 1224 inline void bmask( Register s1, Register s2, Register d );
1223 1225 inline void bshuffle( FloatRegister s1, FloatRegister s2, FloatRegister d );
1224 1226
1225 1227 // VIS3 instructions
1226 1228
1229 + inline void lzcnt( Register s, Register d );
1230 +
1227 1231 inline void movstosw( FloatRegister s, Register d );
1228 1232 inline void movstouw( FloatRegister s, Register d );
1229 1233 inline void movdtox( FloatRegister s, Register d );
1230 1234
1231 1235 inline void movwtos( Register s, FloatRegister d );
1232 1236 inline void movxtod( Register s, FloatRegister d );
1233 1237
1234 1238 inline void xmulx(Register s1, Register s2, Register d);
1235 1239 inline void xmulxhi(Register s1, Register s2, Register d);
1236 1240
1237 1241 // Crypto SHA instructions
1238 1242
1239 1243 inline void sha1();
1240 1244 inline void sha256();
1241 1245 inline void sha512();
1242 1246
1243 1247 // CRC32C instruction
1244 1248
1245 1249 inline void crc32c( FloatRegister s1, FloatRegister s2, FloatRegister d );
1246 1250
1247 1251 // Creation
1248 1252 Assembler(CodeBuffer* code) : AbstractAssembler(code) {
1249 1253 #ifdef CHECK_DELAY
1250 1254 delay_state = no_delay;
1251 1255 #endif
1252 1256 }
1253 1257 };
1254 1258
1255 1259 #endif // CPU_SPARC_VM_ASSEMBLER_SPARC_HPP
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