1 //
2 // Copyright (c) 1998, 2016, Oracle and/or its affiliates. All rights reserved.
3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 //
5 // This code is free software; you can redistribute it and/or modify it
6 // under the terms of the GNU General Public License version 2 only, as
7 // published by the Free Software Foundation.
8 //
9 // This code is distributed in the hope that it will be useful, but WITHOUT
10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 // version 2 for more details (a copy is included in the LICENSE file that
13 // accompanied this code).
14 //
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20 // or visit www.oracle.com if you need additional information or have any
21 // questions.
22 //
23 //
24
25 // SPARC Architecture Description File
26
27 //----------REGISTER DEFINITION BLOCK------------------------------------------
28 // This information is used by the matcher and the register allocator to
29 // describe individual registers and classes of registers within the target
30 // archtecture.
31 register %{
32 //----------Architecture Description Register Definitions----------------------
33 // General Registers
34 // "reg_def" name ( register save type, C convention save type,
35 // ideal register type, encoding, vm name );
36 // Register Save Types:
37 //
38 // NS = No-Save: The register allocator assumes that these registers
39 // can be used without saving upon entry to the method, &
40 // that they do not need to be saved at call sites.
41 //
42 // SOC = Save-On-Call: The register allocator assumes that these registers
43 // can be used without saving upon entry to the method,
44 // but that they must be saved at call sites.
45 //
46 // SOE = Save-On-Entry: The register allocator assumes that these registers
47 // must be saved before using them upon entry to the
48 // method, but they do not need to be saved at call
49 // sites.
50 //
51 // AS = Always-Save: The register allocator assumes that these registers
52 // must be saved before using them upon entry to the
53 // method, & that they must be saved at call sites.
54 //
55 // Ideal Register Type is used to determine how to save & restore a
56 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
57 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
58 //
59 // The encoding number is the actual bit-pattern placed into the opcodes.
60
61
62 // ----------------------------
63 // Integer/Long Registers
64 // ----------------------------
65
66 // Need to expose the hi/lo aspect of 64-bit registers
67 // This register set is used for both the 64-bit build and
68 // the 32-bit build with 1-register longs.
69
70 // Global Registers 0-7
71 reg_def R_G0H( NS, NS, Op_RegI,128, G0->as_VMReg()->next());
72 reg_def R_G0 ( NS, NS, Op_RegI, 0, G0->as_VMReg());
73 reg_def R_G1H(SOC, SOC, Op_RegI,129, G1->as_VMReg()->next());
74 reg_def R_G1 (SOC, SOC, Op_RegI, 1, G1->as_VMReg());
75 reg_def R_G2H( NS, NS, Op_RegI,130, G2->as_VMReg()->next());
76 reg_def R_G2 ( NS, NS, Op_RegI, 2, G2->as_VMReg());
77 reg_def R_G3H(SOC, SOC, Op_RegI,131, G3->as_VMReg()->next());
78 reg_def R_G3 (SOC, SOC, Op_RegI, 3, G3->as_VMReg());
79 reg_def R_G4H(SOC, SOC, Op_RegI,132, G4->as_VMReg()->next());
80 reg_def R_G4 (SOC, SOC, Op_RegI, 4, G4->as_VMReg());
81 reg_def R_G5H(SOC, SOC, Op_RegI,133, G5->as_VMReg()->next());
82 reg_def R_G5 (SOC, SOC, Op_RegI, 5, G5->as_VMReg());
83 reg_def R_G6H( NS, NS, Op_RegI,134, G6->as_VMReg()->next());
84 reg_def R_G6 ( NS, NS, Op_RegI, 6, G6->as_VMReg());
85 reg_def R_G7H( NS, NS, Op_RegI,135, G7->as_VMReg()->next());
86 reg_def R_G7 ( NS, NS, Op_RegI, 7, G7->as_VMReg());
87
88 // Output Registers 0-7
89 reg_def R_O0H(SOC, SOC, Op_RegI,136, O0->as_VMReg()->next());
90 reg_def R_O0 (SOC, SOC, Op_RegI, 8, O0->as_VMReg());
91 reg_def R_O1H(SOC, SOC, Op_RegI,137, O1->as_VMReg()->next());
92 reg_def R_O1 (SOC, SOC, Op_RegI, 9, O1->as_VMReg());
93 reg_def R_O2H(SOC, SOC, Op_RegI,138, O2->as_VMReg()->next());
94 reg_def R_O2 (SOC, SOC, Op_RegI, 10, O2->as_VMReg());
95 reg_def R_O3H(SOC, SOC, Op_RegI,139, O3->as_VMReg()->next());
96 reg_def R_O3 (SOC, SOC, Op_RegI, 11, O3->as_VMReg());
97 reg_def R_O4H(SOC, SOC, Op_RegI,140, O4->as_VMReg()->next());
98 reg_def R_O4 (SOC, SOC, Op_RegI, 12, O4->as_VMReg());
99 reg_def R_O5H(SOC, SOC, Op_RegI,141, O5->as_VMReg()->next());
100 reg_def R_O5 (SOC, SOC, Op_RegI, 13, O5->as_VMReg());
101 reg_def R_SPH( NS, NS, Op_RegI,142, SP->as_VMReg()->next());
102 reg_def R_SP ( NS, NS, Op_RegI, 14, SP->as_VMReg());
103 reg_def R_O7H(SOC, SOC, Op_RegI,143, O7->as_VMReg()->next());
104 reg_def R_O7 (SOC, SOC, Op_RegI, 15, O7->as_VMReg());
105
106 // Local Registers 0-7
107 reg_def R_L0H( NS, NS, Op_RegI,144, L0->as_VMReg()->next());
108 reg_def R_L0 ( NS, NS, Op_RegI, 16, L0->as_VMReg());
109 reg_def R_L1H( NS, NS, Op_RegI,145, L1->as_VMReg()->next());
110 reg_def R_L1 ( NS, NS, Op_RegI, 17, L1->as_VMReg());
111 reg_def R_L2H( NS, NS, Op_RegI,146, L2->as_VMReg()->next());
112 reg_def R_L2 ( NS, NS, Op_RegI, 18, L2->as_VMReg());
113 reg_def R_L3H( NS, NS, Op_RegI,147, L3->as_VMReg()->next());
114 reg_def R_L3 ( NS, NS, Op_RegI, 19, L3->as_VMReg());
115 reg_def R_L4H( NS, NS, Op_RegI,148, L4->as_VMReg()->next());
116 reg_def R_L4 ( NS, NS, Op_RegI, 20, L4->as_VMReg());
117 reg_def R_L5H( NS, NS, Op_RegI,149, L5->as_VMReg()->next());
118 reg_def R_L5 ( NS, NS, Op_RegI, 21, L5->as_VMReg());
119 reg_def R_L6H( NS, NS, Op_RegI,150, L6->as_VMReg()->next());
120 reg_def R_L6 ( NS, NS, Op_RegI, 22, L6->as_VMReg());
121 reg_def R_L7H( NS, NS, Op_RegI,151, L7->as_VMReg()->next());
122 reg_def R_L7 ( NS, NS, Op_RegI, 23, L7->as_VMReg());
123
124 // Input Registers 0-7
125 reg_def R_I0H( NS, NS, Op_RegI,152, I0->as_VMReg()->next());
126 reg_def R_I0 ( NS, NS, Op_RegI, 24, I0->as_VMReg());
127 reg_def R_I1H( NS, NS, Op_RegI,153, I1->as_VMReg()->next());
128 reg_def R_I1 ( NS, NS, Op_RegI, 25, I1->as_VMReg());
129 reg_def R_I2H( NS, NS, Op_RegI,154, I2->as_VMReg()->next());
130 reg_def R_I2 ( NS, NS, Op_RegI, 26, I2->as_VMReg());
131 reg_def R_I3H( NS, NS, Op_RegI,155, I3->as_VMReg()->next());
132 reg_def R_I3 ( NS, NS, Op_RegI, 27, I3->as_VMReg());
133 reg_def R_I4H( NS, NS, Op_RegI,156, I4->as_VMReg()->next());
134 reg_def R_I4 ( NS, NS, Op_RegI, 28, I4->as_VMReg());
135 reg_def R_I5H( NS, NS, Op_RegI,157, I5->as_VMReg()->next());
136 reg_def R_I5 ( NS, NS, Op_RegI, 29, I5->as_VMReg());
137 reg_def R_FPH( NS, NS, Op_RegI,158, FP->as_VMReg()->next());
138 reg_def R_FP ( NS, NS, Op_RegI, 30, FP->as_VMReg());
139 reg_def R_I7H( NS, NS, Op_RegI,159, I7->as_VMReg()->next());
140 reg_def R_I7 ( NS, NS, Op_RegI, 31, I7->as_VMReg());
141
142 // ----------------------------
143 // Float/Double Registers
144 // ----------------------------
145
146 // Float Registers
147 reg_def R_F0 ( SOC, SOC, Op_RegF, 0, F0->as_VMReg());
148 reg_def R_F1 ( SOC, SOC, Op_RegF, 1, F1->as_VMReg());
149 reg_def R_F2 ( SOC, SOC, Op_RegF, 2, F2->as_VMReg());
150 reg_def R_F3 ( SOC, SOC, Op_RegF, 3, F3->as_VMReg());
151 reg_def R_F4 ( SOC, SOC, Op_RegF, 4, F4->as_VMReg());
152 reg_def R_F5 ( SOC, SOC, Op_RegF, 5, F5->as_VMReg());
153 reg_def R_F6 ( SOC, SOC, Op_RegF, 6, F6->as_VMReg());
154 reg_def R_F7 ( SOC, SOC, Op_RegF, 7, F7->as_VMReg());
155 reg_def R_F8 ( SOC, SOC, Op_RegF, 8, F8->as_VMReg());
156 reg_def R_F9 ( SOC, SOC, Op_RegF, 9, F9->as_VMReg());
157 reg_def R_F10( SOC, SOC, Op_RegF, 10, F10->as_VMReg());
158 reg_def R_F11( SOC, SOC, Op_RegF, 11, F11->as_VMReg());
159 reg_def R_F12( SOC, SOC, Op_RegF, 12, F12->as_VMReg());
160 reg_def R_F13( SOC, SOC, Op_RegF, 13, F13->as_VMReg());
161 reg_def R_F14( SOC, SOC, Op_RegF, 14, F14->as_VMReg());
162 reg_def R_F15( SOC, SOC, Op_RegF, 15, F15->as_VMReg());
163 reg_def R_F16( SOC, SOC, Op_RegF, 16, F16->as_VMReg());
164 reg_def R_F17( SOC, SOC, Op_RegF, 17, F17->as_VMReg());
165 reg_def R_F18( SOC, SOC, Op_RegF, 18, F18->as_VMReg());
166 reg_def R_F19( SOC, SOC, Op_RegF, 19, F19->as_VMReg());
167 reg_def R_F20( SOC, SOC, Op_RegF, 20, F20->as_VMReg());
168 reg_def R_F21( SOC, SOC, Op_RegF, 21, F21->as_VMReg());
169 reg_def R_F22( SOC, SOC, Op_RegF, 22, F22->as_VMReg());
170 reg_def R_F23( SOC, SOC, Op_RegF, 23, F23->as_VMReg());
171 reg_def R_F24( SOC, SOC, Op_RegF, 24, F24->as_VMReg());
172 reg_def R_F25( SOC, SOC, Op_RegF, 25, F25->as_VMReg());
173 reg_def R_F26( SOC, SOC, Op_RegF, 26, F26->as_VMReg());
174 reg_def R_F27( SOC, SOC, Op_RegF, 27, F27->as_VMReg());
175 reg_def R_F28( SOC, SOC, Op_RegF, 28, F28->as_VMReg());
176 reg_def R_F29( SOC, SOC, Op_RegF, 29, F29->as_VMReg());
177 reg_def R_F30( SOC, SOC, Op_RegF, 30, F30->as_VMReg());
178 reg_def R_F31( SOC, SOC, Op_RegF, 31, F31->as_VMReg());
179
180 // Double Registers
181 // The rules of ADL require that double registers be defined in pairs.
182 // Each pair must be two 32-bit values, but not necessarily a pair of
183 // single float registers. In each pair, ADLC-assigned register numbers
184 // must be adjacent, with the lower number even. Finally, when the
185 // CPU stores such a register pair to memory, the word associated with
186 // the lower ADLC-assigned number must be stored to the lower address.
187
188 // These definitions specify the actual bit encodings of the sparc
189 // double fp register numbers. FloatRegisterImpl in register_sparc.hpp
190 // wants 0-63, so we have to convert every time we want to use fp regs
191 // with the macroassembler, using reg_to_DoubleFloatRegister_object().
192 // 255 is a flag meaning "don't go here".
193 // I believe we can't handle callee-save doubles D32 and up until
194 // the place in the sparc stack crawler that asserts on the 255 is
195 // fixed up.
196 reg_def R_D32 (SOC, SOC, Op_RegD, 1, F32->as_VMReg());
197 reg_def R_D32x(SOC, SOC, Op_RegD,255, F32->as_VMReg()->next());
198 reg_def R_D34 (SOC, SOC, Op_RegD, 3, F34->as_VMReg());
199 reg_def R_D34x(SOC, SOC, Op_RegD,255, F34->as_VMReg()->next());
200 reg_def R_D36 (SOC, SOC, Op_RegD, 5, F36->as_VMReg());
201 reg_def R_D36x(SOC, SOC, Op_RegD,255, F36->as_VMReg()->next());
202 reg_def R_D38 (SOC, SOC, Op_RegD, 7, F38->as_VMReg());
203 reg_def R_D38x(SOC, SOC, Op_RegD,255, F38->as_VMReg()->next());
204 reg_def R_D40 (SOC, SOC, Op_RegD, 9, F40->as_VMReg());
205 reg_def R_D40x(SOC, SOC, Op_RegD,255, F40->as_VMReg()->next());
206 reg_def R_D42 (SOC, SOC, Op_RegD, 11, F42->as_VMReg());
207 reg_def R_D42x(SOC, SOC, Op_RegD,255, F42->as_VMReg()->next());
208 reg_def R_D44 (SOC, SOC, Op_RegD, 13, F44->as_VMReg());
209 reg_def R_D44x(SOC, SOC, Op_RegD,255, F44->as_VMReg()->next());
210 reg_def R_D46 (SOC, SOC, Op_RegD, 15, F46->as_VMReg());
211 reg_def R_D46x(SOC, SOC, Op_RegD,255, F46->as_VMReg()->next());
212 reg_def R_D48 (SOC, SOC, Op_RegD, 17, F48->as_VMReg());
213 reg_def R_D48x(SOC, SOC, Op_RegD,255, F48->as_VMReg()->next());
214 reg_def R_D50 (SOC, SOC, Op_RegD, 19, F50->as_VMReg());
215 reg_def R_D50x(SOC, SOC, Op_RegD,255, F50->as_VMReg()->next());
216 reg_def R_D52 (SOC, SOC, Op_RegD, 21, F52->as_VMReg());
217 reg_def R_D52x(SOC, SOC, Op_RegD,255, F52->as_VMReg()->next());
218 reg_def R_D54 (SOC, SOC, Op_RegD, 23, F54->as_VMReg());
219 reg_def R_D54x(SOC, SOC, Op_RegD,255, F54->as_VMReg()->next());
220 reg_def R_D56 (SOC, SOC, Op_RegD, 25, F56->as_VMReg());
221 reg_def R_D56x(SOC, SOC, Op_RegD,255, F56->as_VMReg()->next());
222 reg_def R_D58 (SOC, SOC, Op_RegD, 27, F58->as_VMReg());
223 reg_def R_D58x(SOC, SOC, Op_RegD,255, F58->as_VMReg()->next());
224 reg_def R_D60 (SOC, SOC, Op_RegD, 29, F60->as_VMReg());
225 reg_def R_D60x(SOC, SOC, Op_RegD,255, F60->as_VMReg()->next());
226 reg_def R_D62 (SOC, SOC, Op_RegD, 31, F62->as_VMReg());
227 reg_def R_D62x(SOC, SOC, Op_RegD,255, F62->as_VMReg()->next());
228
229
230 // ----------------------------
231 // Special Registers
232 // Condition Codes Flag Registers
233 // I tried to break out ICC and XCC but it's not very pretty.
234 // Every Sparc instruction which defs/kills one also kills the other.
235 // Hence every compare instruction which defs one kind of flags ends
236 // up needing a kill of the other.
237 reg_def CCR (SOC, SOC, Op_RegFlags, 0, VMRegImpl::Bad());
238
239 reg_def FCC0(SOC, SOC, Op_RegFlags, 0, VMRegImpl::Bad());
240 reg_def FCC1(SOC, SOC, Op_RegFlags, 1, VMRegImpl::Bad());
241 reg_def FCC2(SOC, SOC, Op_RegFlags, 2, VMRegImpl::Bad());
242 reg_def FCC3(SOC, SOC, Op_RegFlags, 3, VMRegImpl::Bad());
243
244 // ----------------------------
245 // Specify the enum values for the registers. These enums are only used by the
246 // OptoReg "class". We can convert these enum values at will to VMReg when needed
247 // for visibility to the rest of the vm. The order of this enum influences the
248 // register allocator so having the freedom to set this order and not be stuck
249 // with the order that is natural for the rest of the vm is worth it.
250 alloc_class chunk0(
251 R_L0,R_L0H, R_L1,R_L1H, R_L2,R_L2H, R_L3,R_L3H, R_L4,R_L4H, R_L5,R_L5H, R_L6,R_L6H, R_L7,R_L7H,
252 R_G0,R_G0H, R_G1,R_G1H, R_G2,R_G2H, R_G3,R_G3H, R_G4,R_G4H, R_G5,R_G5H, R_G6,R_G6H, R_G7,R_G7H,
253 R_O7,R_O7H, R_SP,R_SPH, R_O0,R_O0H, R_O1,R_O1H, R_O2,R_O2H, R_O3,R_O3H, R_O4,R_O4H, R_O5,R_O5H,
254 R_I0,R_I0H, R_I1,R_I1H, R_I2,R_I2H, R_I3,R_I3H, R_I4,R_I4H, R_I5,R_I5H, R_FP,R_FPH, R_I7,R_I7H);
255
256 // Note that a register is not allocatable unless it is also mentioned
257 // in a widely-used reg_class below. Thus, R_G7 and R_G0 are outside i_reg.
258
259 alloc_class chunk1(
260 // The first registers listed here are those most likely to be used
261 // as temporaries. We move F0..F7 away from the front of the list,
262 // to reduce the likelihood of interferences with parameters and
263 // return values. Likewise, we avoid using F0/F1 for parameters,
264 // since they are used for return values.
265 // This FPU fine-tuning is worth about 1% on the SPEC geomean.
266 R_F8 ,R_F9 ,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,
267 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,
268 R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,R_F30,R_F31,
269 R_F0 ,R_F1 ,R_F2 ,R_F3 ,R_F4 ,R_F5 ,R_F6 ,R_F7 , // used for arguments and return values
270 R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x,
271 R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x,
272 R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x,
273 R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x);
274
275 alloc_class chunk2(CCR, FCC0, FCC1, FCC2, FCC3);
276
277 //----------Architecture Description Register Classes--------------------------
278 // Several register classes are automatically defined based upon information in
279 // this architecture description.
280 // 1) reg_class inline_cache_reg ( as defined in frame section )
281 // 2) reg_class interpreter_method_oop_reg ( as defined in frame section )
282 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
283 //
284
285 // G0 is not included in integer class since it has special meaning.
286 reg_class g0_reg(R_G0);
287
288 // ----------------------------
289 // Integer Register Classes
290 // ----------------------------
291 // Exclusions from i_reg:
292 // R_G0: hardwired zero
293 // R_G2: reserved by HotSpot to the TLS register (invariant within Java)
294 // R_G6: reserved by Solaris ABI to tools
295 // R_G7: reserved by Solaris ABI to libthread
296 // R_O7: Used as a temp in many encodings
297 reg_class int_reg(R_G1,R_G3,R_G4,R_G5,R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
298
299 // Class for all integer registers, except the G registers. This is used for
300 // encodings which use G registers as temps. The regular inputs to such
301 // instructions use a "notemp_" prefix, as a hack to ensure that the allocator
302 // will not put an input into a temp register.
303 reg_class notemp_int_reg(R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
304
305 reg_class g1_regI(R_G1);
306 reg_class g3_regI(R_G3);
307 reg_class g4_regI(R_G4);
308 reg_class o0_regI(R_O0);
309 reg_class o7_regI(R_O7);
310
311 // ----------------------------
312 // Pointer Register Classes
313 // ----------------------------
314 #ifdef _LP64
315 // 64-bit build means 64-bit pointers means hi/lo pairs
316 reg_class ptr_reg( R_G1H,R_G1, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5,
317 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5,
318 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7,
319 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 );
320 // Lock encodings use G3 and G4 internally
321 reg_class lock_ptr_reg( R_G1H,R_G1, R_G5H,R_G5,
322 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5,
323 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7,
324 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 );
325 // Special class for storeP instructions, which can store SP or RPC to TLS.
326 // It is also used for memory addressing, allowing direct TLS addressing.
327 reg_class sp_ptr_reg( R_G1H,R_G1, R_G2H,R_G2, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5,
328 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5, R_SPH,R_SP,
329 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7,
330 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5, R_FPH,R_FP );
331 // R_L7 is the lowest-priority callee-save (i.e., NS) register
332 // We use it to save R_G2 across calls out of Java.
333 reg_class l7_regP(R_L7H,R_L7);
334
335 // Other special pointer regs
336 reg_class g1_regP(R_G1H,R_G1);
337 reg_class g2_regP(R_G2H,R_G2);
338 reg_class g3_regP(R_G3H,R_G3);
339 reg_class g4_regP(R_G4H,R_G4);
340 reg_class g5_regP(R_G5H,R_G5);
341 reg_class i0_regP(R_I0H,R_I0);
342 reg_class o0_regP(R_O0H,R_O0);
343 reg_class o1_regP(R_O1H,R_O1);
344 reg_class o2_regP(R_O2H,R_O2);
345 reg_class o7_regP(R_O7H,R_O7);
346
347 #else // _LP64
348 // 32-bit build means 32-bit pointers means 1 register.
349 reg_class ptr_reg( R_G1, R_G3,R_G4,R_G5,
350 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,
351 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,
352 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
353 // Lock encodings use G3 and G4 internally
354 reg_class lock_ptr_reg(R_G1, R_G5,
355 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,
356 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,
357 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
358 // Special class for storeP instructions, which can store SP or RPC to TLS.
359 // It is also used for memory addressing, allowing direct TLS addressing.
360 reg_class sp_ptr_reg( R_G1,R_G2,R_G3,R_G4,R_G5,
361 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_SP,
362 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,
363 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5,R_FP);
364 // R_L7 is the lowest-priority callee-save (i.e., NS) register
365 // We use it to save R_G2 across calls out of Java.
366 reg_class l7_regP(R_L7);
367
368 // Other special pointer regs
369 reg_class g1_regP(R_G1);
370 reg_class g2_regP(R_G2);
371 reg_class g3_regP(R_G3);
372 reg_class g4_regP(R_G4);
373 reg_class g5_regP(R_G5);
374 reg_class i0_regP(R_I0);
375 reg_class o0_regP(R_O0);
376 reg_class o1_regP(R_O1);
377 reg_class o2_regP(R_O2);
378 reg_class o7_regP(R_O7);
379 #endif // _LP64
380
381
382 // ----------------------------
383 // Long Register Classes
384 // ----------------------------
385 // Longs in 1 register. Aligned adjacent hi/lo pairs.
386 // Note: O7 is never in this class; it is sometimes used as an encoding temp.
387 reg_class long_reg( R_G1H,R_G1, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5
388 ,R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5
389 #ifdef _LP64
390 // 64-bit, longs in 1 register: use all 64-bit integer registers
391 // 32-bit, longs in 1 register: cannot use I's and L's. Restrict to O's and G's.
392 ,R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7
393 ,R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5
394 #endif // _LP64
395 );
396
397 reg_class g1_regL(R_G1H,R_G1);
398 reg_class g3_regL(R_G3H,R_G3);
399 reg_class o2_regL(R_O2H,R_O2);
400 reg_class o7_regL(R_O7H,R_O7);
401
402 // ----------------------------
403 // Special Class for Condition Code Flags Register
404 reg_class int_flags(CCR);
405 reg_class float_flags(FCC0,FCC1,FCC2,FCC3);
406 reg_class float_flag0(FCC0);
407
408
409 // ----------------------------
410 // Float Point Register Classes
411 // ----------------------------
412 // Skip F30/F31, they are reserved for mem-mem copies
413 reg_class sflt_reg(R_F0,R_F1,R_F2,R_F3,R_F4,R_F5,R_F6,R_F7,R_F8,R_F9,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29);
414
415 // Paired floating point registers--they show up in the same order as the floats,
416 // but they are used with the "Op_RegD" type, and always occur in even/odd pairs.
417 reg_class dflt_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,
418 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,
419 /* Use extra V9 double registers; this AD file does not support V8 */
420 R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x,R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x,
421 R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x,R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x
422 );
423
424 // Paired floating point registers--they show up in the same order as the floats,
425 // but they are used with the "Op_RegD" type, and always occur in even/odd pairs.
426 // This class is usable for mis-aligned loads as happen in I2C adapters.
427 reg_class dflt_low_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,
428 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29);
429 %}
430
431 //----------DEFINITION BLOCK---------------------------------------------------
432 // Define name --> value mappings to inform the ADLC of an integer valued name
433 // Current support includes integer values in the range [0, 0x7FFFFFFF]
434 // Format:
435 // int_def <name> ( <int_value>, <expression>);
436 // Generated Code in ad_<arch>.hpp
437 // #define <name> (<expression>)
438 // // value == <int_value>
439 // Generated code in ad_<arch>.cpp adlc_verification()
440 // assert( <name> == <int_value>, "Expect (<expression>) to equal <int_value>");
441 //
442 definitions %{
443 // The default cost (of an ALU instruction).
444 int_def DEFAULT_COST ( 100, 100);
445 int_def HUGE_COST (1000000, 1000000);
446
447 // Memory refs are twice as expensive as run-of-the-mill.
448 int_def MEMORY_REF_COST ( 200, DEFAULT_COST * 2);
449
450 // Branches are even more expensive.
451 int_def BRANCH_COST ( 300, DEFAULT_COST * 3);
452 int_def CALL_COST ( 300, DEFAULT_COST * 3);
453 %}
454
455
456 //----------SOURCE BLOCK-------------------------------------------------------
457 // This is a block of C++ code which provides values, functions, and
458 // definitions necessary in the rest of the architecture description
459 source_hpp %{
460 // Header information of the source block.
461 // Method declarations/definitions which are used outside
462 // the ad-scope can conveniently be defined here.
463 //
464 // To keep related declarations/definitions/uses close together,
465 // we switch between source %{ }% and source_hpp %{ }% freely as needed.
466
467 // Must be visible to the DFA in dfa_sparc.cpp
468 extern bool can_branch_register( Node *bol, Node *cmp );
469
470 extern bool use_block_zeroing(Node* count);
471
472 // Macros to extract hi & lo halves from a long pair.
473 // G0 is not part of any long pair, so assert on that.
474 // Prevents accidentally using G1 instead of G0.
475 #define LONG_HI_REG(x) (x)
476 #define LONG_LO_REG(x) (x)
477
478 class CallStubImpl {
479
480 //--------------------------------------------------------------
481 //---< Used for optimization in Compile::Shorten_branches >---
482 //--------------------------------------------------------------
483
484 public:
485 // Size of call trampoline stub.
486 static uint size_call_trampoline() {
487 return 0; // no call trampolines on this platform
488 }
489
490 // number of relocations needed by a call trampoline stub
491 static uint reloc_call_trampoline() {
492 return 0; // no call trampolines on this platform
493 }
494 };
495
496 class HandlerImpl {
497
498 public:
499
500 static int emit_exception_handler(CodeBuffer &cbuf);
501 static int emit_deopt_handler(CodeBuffer& cbuf);
502
503 static uint size_exception_handler() {
504 return ( NativeJump::instruction_size ); // sethi;jmp;nop
505 }
506
507 static uint size_deopt_handler() {
508 return ( 4+ NativeJump::instruction_size ); // save;sethi;jmp;restore
509 }
510 };
511
512 %}
513
514 source %{
515 #define __ _masm.
516
517 // tertiary op of a LoadP or StoreP encoding
518 #define REGP_OP true
519
520 static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding);
521 static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding);
522 static Register reg_to_register_object(int register_encoding);
523
524 // Used by the DFA in dfa_sparc.cpp.
525 // Check for being able to use a V9 branch-on-register. Requires a
526 // compare-vs-zero, equal/not-equal, of a value which was zero- or sign-
527 // extended. Doesn't work following an integer ADD, for example, because of
528 // overflow (-1 incremented yields 0 plus a carry in the high-order word). On
529 // 32-bit V9 systems, interrupts currently blow away the high-order 32 bits and
530 // replace them with zero, which could become sign-extension in a different OS
531 // release. There's no obvious reason why an interrupt will ever fill these
532 // bits with non-zero junk (the registers are reloaded with standard LD
533 // instructions which either zero-fill or sign-fill).
534 bool can_branch_register( Node *bol, Node *cmp ) {
535 if( !BranchOnRegister ) return false;
536 #ifdef _LP64
537 if( cmp->Opcode() == Op_CmpP )
538 return true; // No problems with pointer compares
539 #endif
540 if( cmp->Opcode() == Op_CmpL )
541 return true; // No problems with long compares
542
543 if( !SparcV9RegsHiBitsZero ) return false;
544 if( bol->as_Bool()->_test._test != BoolTest::ne &&
545 bol->as_Bool()->_test._test != BoolTest::eq )
546 return false;
547
548 // Check for comparing against a 'safe' value. Any operation which
549 // clears out the high word is safe. Thus, loads and certain shifts
550 // are safe, as are non-negative constants. Any operation which
551 // preserves zero bits in the high word is safe as long as each of its
552 // inputs are safe. Thus, phis and bitwise booleans are safe if their
553 // inputs are safe. At present, the only important case to recognize
554 // seems to be loads. Constants should fold away, and shifts &
555 // logicals can use the 'cc' forms.
556 Node *x = cmp->in(1);
557 if( x->is_Load() ) return true;
558 if( x->is_Phi() ) {
559 for( uint i = 1; i < x->req(); i++ )
560 if( !x->in(i)->is_Load() )
561 return false;
562 return true;
563 }
564 return false;
565 }
566
567 bool use_block_zeroing(Node* count) {
568 // Use BIS for zeroing if count is not constant
569 // or it is >= BlockZeroingLowLimit.
570 return UseBlockZeroing && (count->find_intptr_t_con(BlockZeroingLowLimit) >= BlockZeroingLowLimit);
571 }
572
573 // ****************************************************************************
574
575 // REQUIRED FUNCTIONALITY
576
577 // !!!!! Special hack to get all type of calls to specify the byte offset
578 // from the start of the call to the point where the return address
579 // will point.
580 // The "return address" is the address of the call instruction, plus 8.
581
582 int MachCallStaticJavaNode::ret_addr_offset() {
583 int offset = NativeCall::instruction_size; // call; delay slot
584 if (_method_handle_invoke)
585 offset += 4; // restore SP
586 return offset;
587 }
588
589 int MachCallDynamicJavaNode::ret_addr_offset() {
590 int vtable_index = this->_vtable_index;
591 if (vtable_index < 0) {
592 // must be invalid_vtable_index, not nonvirtual_vtable_index
593 assert(vtable_index == Method::invalid_vtable_index, "correct sentinel value");
594 return (NativeMovConstReg::instruction_size +
595 NativeCall::instruction_size); // sethi; setlo; call; delay slot
596 } else {
597 assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
598 int entry_offset = in_bytes(Klass::vtable_start_offset()) + vtable_index*vtableEntry::size_in_bytes();
599 int v_off = entry_offset + vtableEntry::method_offset_in_bytes();
600 int klass_load_size;
601 if (UseCompressedClassPointers) {
602 assert(Universe::heap() != NULL, "java heap should be initialized");
603 klass_load_size = MacroAssembler::instr_size_for_decode_klass_not_null() + 1*BytesPerInstWord;
604 } else {
605 klass_load_size = 1*BytesPerInstWord;
606 }
607 if (Assembler::is_simm13(v_off)) {
608 return klass_load_size +
609 (2*BytesPerInstWord + // ld_ptr, ld_ptr
610 NativeCall::instruction_size); // call; delay slot
611 } else {
612 return klass_load_size +
613 (4*BytesPerInstWord + // set_hi, set, ld_ptr, ld_ptr
614 NativeCall::instruction_size); // call; delay slot
615 }
616 }
617 }
618
619 int MachCallRuntimeNode::ret_addr_offset() {
620 #ifdef _LP64
621 if (MacroAssembler::is_far_target(entry_point())) {
622 return NativeFarCall::instruction_size;
623 } else {
624 return NativeCall::instruction_size;
625 }
626 #else
627 return NativeCall::instruction_size; // call; delay slot
628 #endif
629 }
630
631 // Indicate if the safepoint node needs the polling page as an input.
632 // Since Sparc does not have absolute addressing, it does.
633 bool SafePointNode::needs_polling_address_input() {
634 return true;
635 }
636
637 // emit an interrupt that is caught by the debugger (for debugging compiler)
638 void emit_break(CodeBuffer &cbuf) {
639 MacroAssembler _masm(&cbuf);
640 __ breakpoint_trap();
641 }
642
643 #ifndef PRODUCT
644 void MachBreakpointNode::format( PhaseRegAlloc *, outputStream *st ) const {
645 st->print("TA");
646 }
647 #endif
648
649 void MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
650 emit_break(cbuf);
651 }
652
653 uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const {
654 return MachNode::size(ra_);
655 }
656
657 // Traceable jump
658 void emit_jmpl(CodeBuffer &cbuf, int jump_target) {
659 MacroAssembler _masm(&cbuf);
660 Register rdest = reg_to_register_object(jump_target);
661 __ JMP(rdest, 0);
662 __ delayed()->nop();
663 }
664
665 // Traceable jump and set exception pc
666 void emit_jmpl_set_exception_pc(CodeBuffer &cbuf, int jump_target) {
667 MacroAssembler _masm(&cbuf);
668 Register rdest = reg_to_register_object(jump_target);
669 __ JMP(rdest, 0);
670 __ delayed()->add(O7, frame::pc_return_offset, Oissuing_pc );
671 }
672
673 void emit_nop(CodeBuffer &cbuf) {
674 MacroAssembler _masm(&cbuf);
675 __ nop();
676 }
677
678 void emit_illtrap(CodeBuffer &cbuf) {
679 MacroAssembler _masm(&cbuf);
680 __ illtrap(0);
681 }
682
683
684 intptr_t get_offset_from_base(const MachNode* n, const TypePtr* atype, int disp32) {
685 assert(n->rule() != loadUB_rule, "");
686
687 intptr_t offset = 0;
688 const TypePtr *adr_type = TYPE_PTR_SENTINAL; // Check for base==RegI, disp==immP
689 const Node* addr = n->get_base_and_disp(offset, adr_type);
690 assert(adr_type == (const TypePtr*)-1, "VerifyOops: no support for sparc operands with base==RegI, disp==immP");
691 assert(addr != NULL && addr != (Node*)-1, "invalid addr");
692 assert(addr->bottom_type()->isa_oopptr() == atype, "");
693 atype = atype->add_offset(offset);
694 assert(disp32 == offset, "wrong disp32");
695 return atype->_offset;
696 }
697
698
699 intptr_t get_offset_from_base_2(const MachNode* n, const TypePtr* atype, int disp32) {
700 assert(n->rule() != loadUB_rule, "");
701
702 intptr_t offset = 0;
703 Node* addr = n->in(2);
704 assert(addr->bottom_type()->isa_oopptr() == atype, "");
705 if (addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP) {
706 Node* a = addr->in(2/*AddPNode::Address*/);
707 Node* o = addr->in(3/*AddPNode::Offset*/);
708 offset = o->is_Con() ? o->bottom_type()->is_intptr_t()->get_con() : Type::OffsetBot;
709 atype = a->bottom_type()->is_ptr()->add_offset(offset);
710 assert(atype->isa_oop_ptr(), "still an oop");
711 }
712 offset = atype->is_ptr()->_offset;
713 if (offset != Type::OffsetBot) offset += disp32;
714 return offset;
715 }
716
717 static inline jlong replicate_immI(int con, int count, int width) {
718 // Load a constant replicated "count" times with width "width"
719 assert(count*width == 8 && width <= 4, "sanity");
720 int bit_width = width * 8;
721 jlong val = con;
722 val &= (((jlong) 1) << bit_width) - 1; // mask off sign bits
723 for (int i = 0; i < count - 1; i++) {
724 val |= (val << bit_width);
725 }
726 return val;
727 }
728
729 static inline jlong replicate_immF(float con) {
730 // Replicate float con 2 times and pack into vector.
731 int val = *((int*)&con);
732 jlong lval = val;
733 lval = (lval << 32) | (lval & 0xFFFFFFFFl);
734 return lval;
735 }
736
737 // Standard Sparc opcode form2 field breakdown
738 static inline void emit2_19(CodeBuffer &cbuf, int f30, int f29, int f25, int f22, int f20, int f19, int f0 ) {
739 f0 &= (1<<19)-1; // Mask displacement to 19 bits
740 int op = (f30 << 30) |
741 (f29 << 29) |
742 (f25 << 25) |
743 (f22 << 22) |
744 (f20 << 20) |
745 (f19 << 19) |
746 (f0 << 0);
747 cbuf.insts()->emit_int32(op);
748 }
749
750 // Standard Sparc opcode form2 field breakdown
751 static inline void emit2_22(CodeBuffer &cbuf, int f30, int f25, int f22, int f0 ) {
752 f0 >>= 10; // Drop 10 bits
753 f0 &= (1<<22)-1; // Mask displacement to 22 bits
754 int op = (f30 << 30) |
755 (f25 << 25) |
756 (f22 << 22) |
757 (f0 << 0);
758 cbuf.insts()->emit_int32(op);
759 }
760
761 // Standard Sparc opcode form3 field breakdown
762 static inline void emit3(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int f5, int f0 ) {
763 int op = (f30 << 30) |
764 (f25 << 25) |
765 (f19 << 19) |
766 (f14 << 14) |
767 (f5 << 5) |
768 (f0 << 0);
769 cbuf.insts()->emit_int32(op);
770 }
771
772 // Standard Sparc opcode form3 field breakdown
773 static inline void emit3_simm13(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm13 ) {
774 simm13 &= (1<<13)-1; // Mask to 13 bits
775 int op = (f30 << 30) |
776 (f25 << 25) |
777 (f19 << 19) |
778 (f14 << 14) |
779 (1 << 13) | // bit to indicate immediate-mode
780 (simm13<<0);
781 cbuf.insts()->emit_int32(op);
782 }
783
784 static inline void emit3_simm10(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm10 ) {
785 simm10 &= (1<<10)-1; // Mask to 10 bits
786 emit3_simm13(cbuf,f30,f25,f19,f14,simm10);
787 }
788
789 #ifdef ASSERT
790 // Helper function for VerifyOops in emit_form3_mem_reg
791 void verify_oops_warning(const MachNode *n, int ideal_op, int mem_op) {
792 warning("VerifyOops encountered unexpected instruction:");
793 n->dump(2);
794 warning("Instruction has ideal_Opcode==Op_%s and op_ld==Op_%s \n", NodeClassNames[ideal_op], NodeClassNames[mem_op]);
795 }
796 #endif
797
798
799 void emit_form3_mem_reg(CodeBuffer &cbuf, PhaseRegAlloc* ra, const MachNode* n, int primary, int tertiary,
800 int src1_enc, int disp32, int src2_enc, int dst_enc) {
801
802 #ifdef ASSERT
803 // The following code implements the +VerifyOops feature.
804 // It verifies oop values which are loaded into or stored out of
805 // the current method activation. +VerifyOops complements techniques
806 // like ScavengeALot, because it eagerly inspects oops in transit,
807 // as they enter or leave the stack, as opposed to ScavengeALot,
808 // which inspects oops "at rest", in the stack or heap, at safepoints.
809 // For this reason, +VerifyOops can sometimes detect bugs very close
810 // to their point of creation. It can also serve as a cross-check
811 // on the validity of oop maps, when used toegether with ScavengeALot.
812
813 // It would be good to verify oops at other points, especially
814 // when an oop is used as a base pointer for a load or store.
815 // This is presently difficult, because it is hard to know when
816 // a base address is biased or not. (If we had such information,
817 // it would be easy and useful to make a two-argument version of
818 // verify_oop which unbiases the base, and performs verification.)
819
820 assert((uint)tertiary == 0xFFFFFFFF || tertiary == REGP_OP, "valid tertiary");
821 bool is_verified_oop_base = false;
822 bool is_verified_oop_load = false;
823 bool is_verified_oop_store = false;
824 int tmp_enc = -1;
825 if (VerifyOops && src1_enc != R_SP_enc) {
826 // classify the op, mainly for an assert check
827 int st_op = 0, ld_op = 0;
828 switch (primary) {
829 case Assembler::stb_op3: st_op = Op_StoreB; break;
830 case Assembler::sth_op3: st_op = Op_StoreC; break;
831 case Assembler::stx_op3: // may become StoreP or stay StoreI or StoreD0
832 case Assembler::stw_op3: st_op = Op_StoreI; break;
833 case Assembler::std_op3: st_op = Op_StoreL; break;
834 case Assembler::stf_op3: st_op = Op_StoreF; break;
835 case Assembler::stdf_op3: st_op = Op_StoreD; break;
836
837 case Assembler::ldsb_op3: ld_op = Op_LoadB; break;
838 case Assembler::ldub_op3: ld_op = Op_LoadUB; break;
839 case Assembler::lduh_op3: ld_op = Op_LoadUS; break;
840 case Assembler::ldsh_op3: ld_op = Op_LoadS; break;
841 case Assembler::ldx_op3: // may become LoadP or stay LoadI
842 case Assembler::ldsw_op3: // may become LoadP or stay LoadI
843 case Assembler::lduw_op3: ld_op = Op_LoadI; break;
844 case Assembler::ldd_op3: ld_op = Op_LoadL; break;
845 case Assembler::ldf_op3: ld_op = Op_LoadF; break;
846 case Assembler::lddf_op3: ld_op = Op_LoadD; break;
847 case Assembler::prefetch_op3: ld_op = Op_LoadI; break;
848
849 default: ShouldNotReachHere();
850 }
851 if (tertiary == REGP_OP) {
852 if (st_op == Op_StoreI) st_op = Op_StoreP;
853 else if (ld_op == Op_LoadI) ld_op = Op_LoadP;
854 else ShouldNotReachHere();
855 if (st_op) {
856 // a store
857 // inputs are (0:control, 1:memory, 2:address, 3:value)
858 Node* n2 = n->in(3);
859 if (n2 != NULL) {
860 const Type* t = n2->bottom_type();
861 is_verified_oop_store = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false;
862 }
863 } else {
864 // a load
865 const Type* t = n->bottom_type();
866 is_verified_oop_load = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false;
867 }
868 }
869
870 if (ld_op) {
871 // a Load
872 // inputs are (0:control, 1:memory, 2:address)
873 if (!(n->ideal_Opcode()==ld_op) && // Following are special cases
874 !(n->ideal_Opcode()==Op_LoadPLocked && ld_op==Op_LoadP) &&
875 !(n->ideal_Opcode()==Op_LoadI && ld_op==Op_LoadF) &&
876 !(n->ideal_Opcode()==Op_LoadF && ld_op==Op_LoadI) &&
877 !(n->ideal_Opcode()==Op_LoadRange && ld_op==Op_LoadI) &&
878 !(n->ideal_Opcode()==Op_LoadKlass && ld_op==Op_LoadP) &&
879 !(n->ideal_Opcode()==Op_LoadL && ld_op==Op_LoadI) &&
880 !(n->ideal_Opcode()==Op_LoadL_unaligned && ld_op==Op_LoadI) &&
881 !(n->ideal_Opcode()==Op_LoadD_unaligned && ld_op==Op_LoadF) &&
882 !(n->ideal_Opcode()==Op_ConvI2F && ld_op==Op_LoadF) &&
883 !(n->ideal_Opcode()==Op_ConvI2D && ld_op==Op_LoadF) &&
884 !(n->ideal_Opcode()==Op_PrefetchAllocation && ld_op==Op_LoadI) &&
885 !(n->ideal_Opcode()==Op_LoadVector && ld_op==Op_LoadD) &&
886 !(n->rule() == loadUB_rule)) {
887 verify_oops_warning(n, n->ideal_Opcode(), ld_op);
888 }
889 } else if (st_op) {
890 // a Store
891 // inputs are (0:control, 1:memory, 2:address, 3:value)
892 if (!(n->ideal_Opcode()==st_op) && // Following are special cases
893 !(n->ideal_Opcode()==Op_StoreCM && st_op==Op_StoreB) &&
894 !(n->ideal_Opcode()==Op_StoreI && st_op==Op_StoreF) &&
895 !(n->ideal_Opcode()==Op_StoreF && st_op==Op_StoreI) &&
896 !(n->ideal_Opcode()==Op_StoreL && st_op==Op_StoreI) &&
897 !(n->ideal_Opcode()==Op_StoreVector && st_op==Op_StoreD) &&
898 !(n->ideal_Opcode()==Op_StoreD && st_op==Op_StoreI && n->rule() == storeD0_rule)) {
899 verify_oops_warning(n, n->ideal_Opcode(), st_op);
900 }
901 }
902
903 if (src2_enc == R_G0_enc && n->rule() != loadUB_rule && n->ideal_Opcode() != Op_StoreCM ) {
904 Node* addr = n->in(2);
905 if (!(addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP)) {
906 const TypeOopPtr* atype = addr->bottom_type()->isa_instptr(); // %%% oopptr?
907 if (atype != NULL) {
908 intptr_t offset = get_offset_from_base(n, atype, disp32);
909 intptr_t offset_2 = get_offset_from_base_2(n, atype, disp32);
910 if (offset != offset_2) {
911 get_offset_from_base(n, atype, disp32);
912 get_offset_from_base_2(n, atype, disp32);
913 }
914 assert(offset == offset_2, "different offsets");
915 if (offset == disp32) {
916 // we now know that src1 is a true oop pointer
917 is_verified_oop_base = true;
918 if (ld_op && src1_enc == dst_enc && ld_op != Op_LoadF && ld_op != Op_LoadD) {
919 if( primary == Assembler::ldd_op3 ) {
920 is_verified_oop_base = false; // Cannot 'ldd' into O7
921 } else {
922 tmp_enc = dst_enc;
923 dst_enc = R_O7_enc; // Load into O7; preserve source oop
924 assert(src1_enc != dst_enc, "");
925 }
926 }
927 }
928 if (st_op && (( offset == oopDesc::klass_offset_in_bytes())
929 || offset == oopDesc::mark_offset_in_bytes())) {
930 // loading the mark should not be allowed either, but
931 // we don't check this since it conflicts with InlineObjectHash
932 // usage of LoadINode to get the mark. We could keep the
933 // check if we create a new LoadMarkNode
934 // but do not verify the object before its header is initialized
935 ShouldNotReachHere();
936 }
937 }
938 }
939 }
940 }
941 #endif
942
943 uint instr = (Assembler::ldst_op << 30)
944 | (dst_enc << 25)
945 | (primary << 19)
946 | (src1_enc << 14);
947
948 uint index = src2_enc;
949 int disp = disp32;
950
951 if (src1_enc == R_SP_enc || src1_enc == R_FP_enc) {
952 disp += STACK_BIAS;
953 // Check that stack offset fits, load into O7 if not
954 if (!Assembler::is_simm13(disp)) {
955 MacroAssembler _masm(&cbuf);
956 __ set(disp, O7);
957 if (index != R_G0_enc) {
958 __ add(O7, reg_to_register_object(index), O7);
959 }
960 index = R_O7_enc;
961 disp = 0;
962 }
963 }
964
965 if( disp == 0 ) {
966 // use reg-reg form
967 // bit 13 is already zero
968 instr |= index;
969 } else {
970 // use reg-imm form
971 instr |= 0x00002000; // set bit 13 to one
972 instr |= disp & 0x1FFF;
973 }
974
975 cbuf.insts()->emit_int32(instr);
976
977 #ifdef ASSERT
978 if (VerifyOops) {
979 MacroAssembler _masm(&cbuf);
980 if (is_verified_oop_base) {
981 __ verify_oop(reg_to_register_object(src1_enc));
982 }
983 if (is_verified_oop_store) {
984 __ verify_oop(reg_to_register_object(dst_enc));
985 }
986 if (tmp_enc != -1) {
987 __ mov(O7, reg_to_register_object(tmp_enc));
988 }
989 if (is_verified_oop_load) {
990 __ verify_oop(reg_to_register_object(dst_enc));
991 }
992 }
993 #endif
994 }
995
996 void emit_call_reloc(CodeBuffer &cbuf, intptr_t entry_point, RelocationHolder const& rspec, bool preserve_g2 = false) {
997 // The method which records debug information at every safepoint
998 // expects the call to be the first instruction in the snippet as
999 // it creates a PcDesc structure which tracks the offset of a call
1000 // from the start of the codeBlob. This offset is computed as
1001 // code_end() - code_begin() of the code which has been emitted
1002 // so far.
1003 // In this particular case we have skirted around the problem by
1004 // putting the "mov" instruction in the delay slot but the problem
1005 // may bite us again at some other point and a cleaner/generic
1006 // solution using relocations would be needed.
1007 MacroAssembler _masm(&cbuf);
1008 __ set_inst_mark();
1009
1010 // We flush the current window just so that there is a valid stack copy
1011 // the fact that the current window becomes active again instantly is
1012 // not a problem there is nothing live in it.
1013
1014 #ifdef ASSERT
1015 int startpos = __ offset();
1016 #endif /* ASSERT */
1017
1018 __ call((address)entry_point, rspec);
1019
1020 if (preserve_g2) __ delayed()->mov(G2, L7);
1021 else __ delayed()->nop();
1022
1023 if (preserve_g2) __ mov(L7, G2);
1024
1025 #ifdef ASSERT
1026 if (preserve_g2 && (VerifyCompiledCode || VerifyOops)) {
1027 #ifdef _LP64
1028 // Trash argument dump slots.
1029 __ set(0xb0b8ac0db0b8ac0d, G1);
1030 __ mov(G1, G5);
1031 __ stx(G1, SP, STACK_BIAS + 0x80);
1032 __ stx(G1, SP, STACK_BIAS + 0x88);
1033 __ stx(G1, SP, STACK_BIAS + 0x90);
1034 __ stx(G1, SP, STACK_BIAS + 0x98);
1035 __ stx(G1, SP, STACK_BIAS + 0xA0);
1036 __ stx(G1, SP, STACK_BIAS + 0xA8);
1037 #else // _LP64
1038 // this is also a native call, so smash the first 7 stack locations,
1039 // and the various registers
1040
1041 // Note: [SP+0x40] is sp[callee_aggregate_return_pointer_sp_offset],
1042 // while [SP+0x44..0x58] are the argument dump slots.
1043 __ set((intptr_t)0xbaadf00d, G1);
1044 __ mov(G1, G5);
1045 __ sllx(G1, 32, G1);
1046 __ or3(G1, G5, G1);
1047 __ mov(G1, G5);
1048 __ stx(G1, SP, 0x40);
1049 __ stx(G1, SP, 0x48);
1050 __ stx(G1, SP, 0x50);
1051 __ stw(G1, SP, 0x58); // Do not trash [SP+0x5C] which is a usable spill slot
1052 #endif // _LP64
1053 }
1054 #endif /*ASSERT*/
1055 }
1056
1057 //=============================================================================
1058 // REQUIRED FUNCTIONALITY for encoding
1059 void emit_lo(CodeBuffer &cbuf, int val) { }
1060 void emit_hi(CodeBuffer &cbuf, int val) { }
1061
1062
1063 //=============================================================================
1064 const RegMask& MachConstantBaseNode::_out_RegMask = PTR_REG_mask();
1065
1066 int Compile::ConstantTable::calculate_table_base_offset() const {
1067 if (UseRDPCForConstantTableBase) {
1068 // The table base offset might be less but then it fits into
1069 // simm13 anyway and we are good (cf. MachConstantBaseNode::emit).
1070 return Assembler::min_simm13();
1071 } else {
1072 int offset = -(size() / 2);
1073 if (!Assembler::is_simm13(offset)) {
1074 offset = Assembler::min_simm13();
1075 }
1076 return offset;
1077 }
1078 }
1079
1080 bool MachConstantBaseNode::requires_postalloc_expand() const { return false; }
1081 void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) {
1082 ShouldNotReachHere();
1083 }
1084
1085 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
1086 Compile* C = ra_->C;
1087 Compile::ConstantTable& constant_table = C->constant_table();
1088 MacroAssembler _masm(&cbuf);
1089
1090 Register r = as_Register(ra_->get_encode(this));
1091 CodeSection* consts_section = __ code()->consts();
1092 int consts_size = consts_section->align_at_start(consts_section->size());
1093 assert(constant_table.size() == consts_size, "must be: %d == %d", constant_table.size(), consts_size);
1094
1095 if (UseRDPCForConstantTableBase) {
1096 // For the following RDPC logic to work correctly the consts
1097 // section must be allocated right before the insts section. This
1098 // assert checks for that. The layout and the SECT_* constants
1099 // are defined in src/share/vm/asm/codeBuffer.hpp.
1100 assert(CodeBuffer::SECT_CONSTS + 1 == CodeBuffer::SECT_INSTS, "must be");
1101 int insts_offset = __ offset();
1102
1103 // Layout:
1104 //
1105 // |----------- consts section ------------|----------- insts section -----------...
1106 // |------ constant table -----|- padding -|------------------x----
1107 // \ current PC (RDPC instruction)
1108 // |<------------- consts_size ----------->|<- insts_offset ->|
1109 // \ table base
1110 // The table base offset is later added to the load displacement
1111 // so it has to be negative.
1112 int table_base_offset = -(consts_size + insts_offset);
1113 int disp;
1114
1115 // If the displacement from the current PC to the constant table
1116 // base fits into simm13 we set the constant table base to the
1117 // current PC.
1118 if (Assembler::is_simm13(table_base_offset)) {
1119 constant_table.set_table_base_offset(table_base_offset);
1120 disp = 0;
1121 } else {
1122 // Otherwise we set the constant table base offset to the
1123 // maximum negative displacement of load instructions to keep
1124 // the disp as small as possible:
1125 //
1126 // |<------------- consts_size ----------->|<- insts_offset ->|
1127 // |<--------- min_simm13 --------->|<-------- disp --------->|
1128 // \ table base
1129 table_base_offset = Assembler::min_simm13();
1130 constant_table.set_table_base_offset(table_base_offset);
1131 disp = (consts_size + insts_offset) + table_base_offset;
1132 }
1133
1134 __ rdpc(r);
1135
1136 if (disp != 0) {
1137 assert(r != O7, "need temporary");
1138 __ sub(r, __ ensure_simm13_or_reg(disp, O7), r);
1139 }
1140 }
1141 else {
1142 // Materialize the constant table base.
1143 address baseaddr = consts_section->start() + -(constant_table.table_base_offset());
1144 RelocationHolder rspec = internal_word_Relocation::spec(baseaddr);
1145 AddressLiteral base(baseaddr, rspec);
1146 __ set(base, r);
1147 }
1148 }
1149
1150 uint MachConstantBaseNode::size(PhaseRegAlloc*) const {
1151 if (UseRDPCForConstantTableBase) {
1152 // This is really the worst case but generally it's only 1 instruction.
1153 return (1 /*rdpc*/ + 1 /*sub*/ + MacroAssembler::worst_case_insts_for_set()) * BytesPerInstWord;
1154 } else {
1155 return MacroAssembler::worst_case_insts_for_set() * BytesPerInstWord;
1156 }
1157 }
1158
1159 #ifndef PRODUCT
1160 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
1161 char reg[128];
1162 ra_->dump_register(this, reg);
1163 if (UseRDPCForConstantTableBase) {
1164 st->print("RDPC %s\t! constant table base", reg);
1165 } else {
1166 st->print("SET &constanttable,%s\t! constant table base", reg);
1167 }
1168 }
1169 #endif
1170
1171
1172 //=============================================================================
1173
1174 #ifndef PRODUCT
1175 void MachPrologNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1176 Compile* C = ra_->C;
1177
1178 for (int i = 0; i < OptoPrologueNops; i++) {
1179 st->print_cr("NOP"); st->print("\t");
1180 }
1181
1182 if( VerifyThread ) {
1183 st->print_cr("Verify_Thread"); st->print("\t");
1184 }
1185
1186 size_t framesize = C->frame_size_in_bytes();
1187 int bangsize = C->bang_size_in_bytes();
1188
1189 // Calls to C2R adapters often do not accept exceptional returns.
1190 // We require that their callers must bang for them. But be careful, because
1191 // some VM calls (such as call site linkage) can use several kilobytes of
1192 // stack. But the stack safety zone should account for that.
1193 // See bugs 4446381, 4468289, 4497237.
1194 if (C->need_stack_bang(bangsize)) {
1195 st->print_cr("! stack bang (%d bytes)", bangsize); st->print("\t");
1196 }
1197
1198 if (Assembler::is_simm13(-framesize)) {
1199 st->print ("SAVE R_SP,-" SIZE_FORMAT ",R_SP",framesize);
1200 } else {
1201 st->print_cr("SETHI R_SP,hi%%(-" SIZE_FORMAT "),R_G3",framesize); st->print("\t");
1202 st->print_cr("ADD R_G3,lo%%(-" SIZE_FORMAT "),R_G3",framesize); st->print("\t");
1203 st->print ("SAVE R_SP,R_G3,R_SP");
1204 }
1205
1206 }
1207 #endif
1208
1209 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1210 Compile* C = ra_->C;
1211 MacroAssembler _masm(&cbuf);
1212
1213 for (int i = 0; i < OptoPrologueNops; i++) {
1214 __ nop();
1215 }
1216
1217 __ verify_thread();
1218
1219 size_t framesize = C->frame_size_in_bytes();
1220 assert(framesize >= 16*wordSize, "must have room for reg. save area");
1221 assert(framesize%(2*wordSize) == 0, "must preserve 2*wordSize alignment");
1222 int bangsize = C->bang_size_in_bytes();
1223
1224 // Calls to C2R adapters often do not accept exceptional returns.
1225 // We require that their callers must bang for them. But be careful, because
1226 // some VM calls (such as call site linkage) can use several kilobytes of
1227 // stack. But the stack safety zone should account for that.
1228 // See bugs 4446381, 4468289, 4497237.
1229 if (C->need_stack_bang(bangsize)) {
1230 __ generate_stack_overflow_check(bangsize);
1231 }
1232
1233 if (Assembler::is_simm13(-framesize)) {
1234 __ save(SP, -framesize, SP);
1235 } else {
1236 __ sethi(-framesize & ~0x3ff, G3);
1237 __ add(G3, -framesize & 0x3ff, G3);
1238 __ save(SP, G3, SP);
1239 }
1240 C->set_frame_complete( __ offset() );
1241
1242 if (!UseRDPCForConstantTableBase && C->has_mach_constant_base_node()) {
1243 // NOTE: We set the table base offset here because users might be
1244 // emitted before MachConstantBaseNode.
1245 Compile::ConstantTable& constant_table = C->constant_table();
1246 constant_table.set_table_base_offset(constant_table.calculate_table_base_offset());
1247 }
1248 }
1249
1250 uint MachPrologNode::size(PhaseRegAlloc *ra_) const {
1251 return MachNode::size(ra_);
1252 }
1253
1254 int MachPrologNode::reloc() const {
1255 return 10; // a large enough number
1256 }
1257
1258 //=============================================================================
1259 #ifndef PRODUCT
1260 void MachEpilogNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1261 Compile* C = ra_->C;
1262
1263 if(do_polling() && ra_->C->is_method_compilation()) {
1264 st->print("SETHI #PollAddr,L0\t! Load Polling address\n\t");
1265 #ifdef _LP64
1266 st->print("LDX [L0],G0\t!Poll for Safepointing\n\t");
1267 #else
1268 st->print("LDUW [L0],G0\t!Poll for Safepointing\n\t");
1269 #endif
1270 }
1271
1272 if(do_polling()) {
1273 if (UseCBCond && !ra_->C->is_method_compilation()) {
1274 st->print("NOP\n\t");
1275 }
1276 st->print("RET\n\t");
1277 }
1278
1279 st->print("RESTORE");
1280 }
1281 #endif
1282
1283 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1284 MacroAssembler _masm(&cbuf);
1285 Compile* C = ra_->C;
1286
1287 __ verify_thread();
1288
1289 if (StackReservedPages > 0 && C->has_reserved_stack_access()) {
1290 __ reserved_stack_check();
1291 }
1292
1293 // If this does safepoint polling, then do it here
1294 if(do_polling() && ra_->C->is_method_compilation()) {
1295 AddressLiteral polling_page(os::get_polling_page());
1296 __ sethi(polling_page, L0);
1297 __ relocate(relocInfo::poll_return_type);
1298 __ ld_ptr(L0, 0, G0);
1299 }
1300
1301 // If this is a return, then stuff the restore in the delay slot
1302 if(do_polling()) {
1303 if (UseCBCond && !ra_->C->is_method_compilation()) {
1304 // Insert extra padding for the case when the epilogue is preceded by
1305 // a cbcond jump, which can't be followed by a CTI instruction
1306 __ nop();
1307 }
1308 __ ret();
1309 __ delayed()->restore();
1310 } else {
1311 __ restore();
1312 }
1313 }
1314
1315 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const {
1316 return MachNode::size(ra_);
1317 }
1318
1319 int MachEpilogNode::reloc() const {
1320 return 16; // a large enough number
1321 }
1322
1323 const Pipeline * MachEpilogNode::pipeline() const {
1324 return MachNode::pipeline_class();
1325 }
1326
1327 int MachEpilogNode::safepoint_offset() const {
1328 assert( do_polling(), "no return for this epilog node");
1329 return MacroAssembler::insts_for_sethi(os::get_polling_page()) * BytesPerInstWord;
1330 }
1331
1332 //=============================================================================
1333
1334 // Figure out which register class each belongs in: rc_int, rc_float, rc_stack
1335 enum RC { rc_bad, rc_int, rc_float, rc_stack };
1336 static enum RC rc_class( OptoReg::Name reg ) {
1337 if (!OptoReg::is_valid(reg)) return rc_bad;
1338 if (OptoReg::is_stack(reg)) return rc_stack;
1339 VMReg r = OptoReg::as_VMReg(reg);
1340 if (r->is_Register()) return rc_int;
1341 assert(r->is_FloatRegister(), "must be");
1342 return rc_float;
1343 }
1344
1345 #ifndef PRODUCT
1346 ATTRIBUTE_PRINTF(2, 3)
1347 static void print_helper(outputStream* st, const char* format, ...) {
1348 if (st->position() > 0) {
1349 st->cr();
1350 st->sp();
1351 }
1352 va_list ap;
1353 va_start(ap, format);
1354 st->vprint(format, ap);
1355 va_end(ap);
1356 }
1357 #endif // !PRODUCT
1358
1359 static void impl_helper(const MachNode* mach, CodeBuffer* cbuf, PhaseRegAlloc* ra, bool is_load, int offset, int reg, int opcode, const char *op_str, outputStream* st) {
1360 if (cbuf) {
1361 emit_form3_mem_reg(*cbuf, ra, mach, opcode, -1, R_SP_enc, offset, 0, Matcher::_regEncode[reg]);
1362 }
1363 #ifndef PRODUCT
1364 else {
1365 if (is_load) {
1366 print_helper(st, "%s [R_SP + #%d],R_%s\t! spill", op_str, offset, OptoReg::regname(reg));
1367 } else {
1368 print_helper(st, "%s R_%s,[R_SP + #%d]\t! spill", op_str, OptoReg::regname(reg), offset);
1369 }
1370 }
1371 #endif
1372 }
1373
1374 static void impl_mov_helper(CodeBuffer *cbuf, int src, int dst, int op1, int op2, const char *op_str, outputStream* st) {
1375 if (cbuf) {
1376 emit3(*cbuf, Assembler::arith_op, Matcher::_regEncode[dst], op1, 0, op2, Matcher::_regEncode[src]);
1377 }
1378 #ifndef PRODUCT
1379 else {
1380 print_helper(st, "%s R_%s,R_%s\t! spill", op_str, OptoReg::regname(src), OptoReg::regname(dst));
1381 }
1382 #endif
1383 }
1384
1385 static void mach_spill_copy_implementation_helper(const MachNode* mach,
1386 CodeBuffer *cbuf,
1387 PhaseRegAlloc *ra_,
1388 outputStream* st) {
1389 // Get registers to move
1390 OptoReg::Name src_second = ra_->get_reg_second(mach->in(1));
1391 OptoReg::Name src_first = ra_->get_reg_first(mach->in(1));
1392 OptoReg::Name dst_second = ra_->get_reg_second(mach);
1393 OptoReg::Name dst_first = ra_->get_reg_first(mach);
1394
1395 enum RC src_second_rc = rc_class(src_second);
1396 enum RC src_first_rc = rc_class(src_first);
1397 enum RC dst_second_rc = rc_class(dst_second);
1398 enum RC dst_first_rc = rc_class(dst_first);
1399
1400 assert(OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), "must move at least 1 register");
1401
1402 if (src_first == dst_first && src_second == dst_second) {
1403 return; // Self copy, no move
1404 }
1405
1406 // --------------------------------------
1407 // Check for mem-mem move. Load into unused float registers and fall into
1408 // the float-store case.
1409 if (src_first_rc == rc_stack && dst_first_rc == rc_stack) {
1410 int offset = ra_->reg2offset(src_first);
1411 // Further check for aligned-adjacent pair, so we can use a double load
1412 if ((src_first&1) == 0 && src_first+1 == src_second) {
1413 src_second = OptoReg::Name(R_F31_num);
1414 src_second_rc = rc_float;
1415 impl_helper(mach, cbuf, ra_, true, offset, R_F30_num, Assembler::lddf_op3, "LDDF", st);
1416 } else {
1417 impl_helper(mach, cbuf, ra_, true, offset, R_F30_num, Assembler::ldf_op3, "LDF ", st);
1418 }
1419 src_first = OptoReg::Name(R_F30_num);
1420 src_first_rc = rc_float;
1421 }
1422
1423 if( src_second_rc == rc_stack && dst_second_rc == rc_stack ) {
1424 int offset = ra_->reg2offset(src_second);
1425 impl_helper(mach, cbuf, ra_, true, offset, R_F31_num, Assembler::ldf_op3, "LDF ", st);
1426 src_second = OptoReg::Name(R_F31_num);
1427 src_second_rc = rc_float;
1428 }
1429
1430 // --------------------------------------
1431 // Check for float->int copy; requires a trip through memory
1432 if (src_first_rc == rc_float && dst_first_rc == rc_int && UseVIS < 3) {
1433 int offset = frame::register_save_words*wordSize;
1434 if (cbuf) {
1435 emit3_simm13(*cbuf, Assembler::arith_op, R_SP_enc, Assembler::sub_op3, R_SP_enc, 16);
1436 impl_helper(mach, cbuf, ra_, false, offset, src_first, Assembler::stf_op3, "STF ", st);
1437 impl_helper(mach, cbuf, ra_, true, offset, dst_first, Assembler::lduw_op3, "LDUW", st);
1438 emit3_simm13(*cbuf, Assembler::arith_op, R_SP_enc, Assembler::add_op3, R_SP_enc, 16);
1439 }
1440 #ifndef PRODUCT
1441 else {
1442 print_helper(st, "SUB R_SP,16,R_SP");
1443 impl_helper(mach, cbuf, ra_, false, offset, src_first, Assembler::stf_op3, "STF ", st);
1444 impl_helper(mach, cbuf, ra_, true, offset, dst_first, Assembler::lduw_op3, "LDUW", st);
1445 print_helper(st, "ADD R_SP,16,R_SP");
1446 }
1447 #endif
1448 }
1449
1450 // Check for float->int copy on T4
1451 if (src_first_rc == rc_float && dst_first_rc == rc_int && UseVIS >= 3) {
1452 // Further check for aligned-adjacent pair, so we can use a double move
1453 if ((src_first & 1) == 0 && src_first + 1 == src_second && (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1454 impl_mov_helper(cbuf, src_first, dst_first, Assembler::mftoi_op3, Assembler::mdtox_opf, "MOVDTOX", st);
1455 return;
1456 }
1457 impl_mov_helper(cbuf, src_first, dst_first, Assembler::mftoi_op3, Assembler::mstouw_opf, "MOVSTOUW", st);
1458 }
1459 // Check for int->float copy on T4
1460 if (src_first_rc == rc_int && dst_first_rc == rc_float && UseVIS >= 3) {
1461 // Further check for aligned-adjacent pair, so we can use a double move
1462 if ((src_first & 1) == 0 && src_first + 1 == src_second && (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1463 impl_mov_helper(cbuf, src_first, dst_first, Assembler::mftoi_op3, Assembler::mxtod_opf, "MOVXTOD", st);
1464 return;
1465 }
1466 impl_mov_helper(cbuf, src_first, dst_first, Assembler::mftoi_op3, Assembler::mwtos_opf, "MOVWTOS", st);
1467 }
1468
1469 // --------------------------------------
1470 // In the 32-bit 1-reg-longs build ONLY, I see mis-aligned long destinations.
1471 // In such cases, I have to do the big-endian swap. For aligned targets, the
1472 // hardware does the flop for me. Doubles are always aligned, so no problem
1473 // there. Misaligned sources only come from native-long-returns (handled
1474 // special below).
1475 #ifndef _LP64
1476 if (src_first_rc == rc_int && // source is already big-endian
1477 src_second_rc != rc_bad && // 64-bit move
1478 ((dst_first & 1) != 0 || dst_second != dst_first + 1)) { // misaligned dst
1479 assert((src_first & 1) == 0 && src_second == src_first + 1, "source must be aligned");
1480 // Do the big-endian flop.
1481 OptoReg::Name tmp = dst_first ; dst_first = dst_second ; dst_second = tmp ;
1482 enum RC tmp_rc = dst_first_rc; dst_first_rc = dst_second_rc; dst_second_rc = tmp_rc;
1483 }
1484 #endif
1485
1486 // --------------------------------------
1487 // Check for integer reg-reg copy
1488 if (src_first_rc == rc_int && dst_first_rc == rc_int) {
1489 #ifndef _LP64
1490 if (src_first == R_O0_num && src_second == R_O1_num) { // Check for the evil O0/O1 native long-return case
1491 // Note: The _first and _second suffixes refer to the addresses of the the 2 halves of the 64-bit value
1492 // as stored in memory. On a big-endian machine like SPARC, this means that the _second
1493 // operand contains the least significant word of the 64-bit value and vice versa.
1494 OptoReg::Name tmp = OptoReg::Name(R_O7_num);
1495 assert((dst_first & 1) == 0 && dst_second == dst_first + 1, "return a native O0/O1 long to an aligned-adjacent 64-bit reg" );
1496 // Shift O0 left in-place, zero-extend O1, then OR them into the dst
1497 if ( cbuf ) {
1498 emit3_simm13(*cbuf, Assembler::arith_op, Matcher::_regEncode[tmp], Assembler::sllx_op3, Matcher::_regEncode[src_first], 0x1020);
1499 emit3_simm13(*cbuf, Assembler::arith_op, Matcher::_regEncode[src_second], Assembler::srl_op3, Matcher::_regEncode[src_second], 0x0000);
1500 emit3 (*cbuf, Assembler::arith_op, Matcher::_regEncode[dst_first], Assembler:: or_op3, Matcher::_regEncode[tmp], 0, Matcher::_regEncode[src_second]);
1501 #ifndef PRODUCT
1502 } else {
1503 print_helper(st, "SLLX R_%s,32,R_%s\t! Move O0-first to O7-high\n\t", OptoReg::regname(src_first), OptoReg::regname(tmp));
1504 print_helper(st, "SRL R_%s, 0,R_%s\t! Zero-extend O1\n\t", OptoReg::regname(src_second), OptoReg::regname(src_second));
1505 print_helper(st, "OR R_%s,R_%s,R_%s\t! spill",OptoReg::regname(tmp), OptoReg::regname(src_second), OptoReg::regname(dst_first));
1506 #endif
1507 }
1508 return;
1509 } else if (dst_first == R_I0_num && dst_second == R_I1_num) {
1510 // returning a long value in I0/I1
1511 // a SpillCopy must be able to target a return instruction's reg_class
1512 // Note: The _first and _second suffixes refer to the addresses of the the 2 halves of the 64-bit value
1513 // as stored in memory. On a big-endian machine like SPARC, this means that the _second
1514 // operand contains the least significant word of the 64-bit value and vice versa.
1515 OptoReg::Name tdest = dst_first;
1516
1517 if (src_first == dst_first) {
1518 tdest = OptoReg::Name(R_O7_num);
1519 }
1520
1521 if (cbuf) {
1522 assert((src_first & 1) == 0 && (src_first + 1) == src_second, "return value was in an aligned-adjacent 64-bit reg");
1523 // Shift value in upper 32-bits of src to lower 32-bits of I0; move lower 32-bits to I1
1524 // ShrL_reg_imm6
1525 emit3_simm13(*cbuf, Assembler::arith_op, Matcher::_regEncode[tdest], Assembler::srlx_op3, Matcher::_regEncode[src_second], 32 | 0x1000);
1526 // ShrR_reg_imm6 src, 0, dst
1527 emit3_simm13(*cbuf, Assembler::arith_op, Matcher::_regEncode[dst_second], Assembler::srl_op3, Matcher::_regEncode[src_first], 0x0000);
1528 if (tdest != dst_first) {
1529 emit3 (*cbuf, Assembler::arith_op, Matcher::_regEncode[dst_first], Assembler::or_op3, 0/*G0*/, 0/*op2*/, Matcher::_regEncode[tdest]);
1530 }
1531 }
1532 #ifndef PRODUCT
1533 else {
1534 print_helper(st, "SRLX R_%s,32,R_%s\t! Extract MSW\n\t",OptoReg::regname(src_second),OptoReg::regname(tdest));
1535 print_helper(st, "SRL R_%s, 0,R_%s\t! Extract LSW\n\t",OptoReg::regname(src_first),OptoReg::regname(dst_second));
1536 if (tdest != dst_first) {
1537 print_helper(st, "MOV R_%s,R_%s\t! spill\n\t", OptoReg::regname(tdest), OptoReg::regname(dst_first));
1538 }
1539 }
1540 #endif // PRODUCT
1541 return size+8;
1542 }
1543 #endif // !_LP64
1544 // Else normal reg-reg copy
1545 assert(src_second != dst_first, "smashed second before evacuating it");
1546 impl_mov_helper(cbuf, src_first, dst_first, Assembler::or_op3, 0, "MOV ", st);
1547 assert((src_first & 1) == 0 && (dst_first & 1) == 0, "never move second-halves of int registers");
1548 // This moves an aligned adjacent pair.
1549 // See if we are done.
1550 if (src_first + 1 == src_second && dst_first + 1 == dst_second) {
1551 return;
1552 }
1553 }
1554
1555 // Check for integer store
1556 if (src_first_rc == rc_int && dst_first_rc == rc_stack) {
1557 int offset = ra_->reg2offset(dst_first);
1558 // Further check for aligned-adjacent pair, so we can use a double store
1559 if ((src_first & 1) == 0 && src_first + 1 == src_second && (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1560 impl_helper(mach, cbuf, ra_, false, offset, src_first, Assembler::stx_op3, "STX ", st);
1561 return;
1562 }
1563 impl_helper(mach, cbuf, ra_, false, offset, src_first, Assembler::stw_op3, "STW ", st);
1564 }
1565
1566 // Check for integer load
1567 if (dst_first_rc == rc_int && src_first_rc == rc_stack) {
1568 int offset = ra_->reg2offset(src_first);
1569 // Further check for aligned-adjacent pair, so we can use a double load
1570 if ((src_first & 1) == 0 && src_first + 1 == src_second && (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1571 impl_helper(mach, cbuf, ra_, true, offset, dst_first, Assembler::ldx_op3, "LDX ", st);
1572 return;
1573 }
1574 impl_helper(mach, cbuf, ra_, true, offset, dst_first, Assembler::lduw_op3, "LDUW", st);
1575 }
1576
1577 // Check for float reg-reg copy
1578 if (src_first_rc == rc_float && dst_first_rc == rc_float) {
1579 // Further check for aligned-adjacent pair, so we can use a double move
1580 if ((src_first & 1) == 0 && src_first + 1 == src_second && (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1581 impl_mov_helper(cbuf, src_first, dst_first, Assembler::fpop1_op3, Assembler::fmovd_opf, "FMOVD", st);
1582 return;
1583 }
1584 impl_mov_helper(cbuf, src_first, dst_first, Assembler::fpop1_op3, Assembler::fmovs_opf, "FMOVS", st);
1585 }
1586
1587 // Check for float store
1588 if (src_first_rc == rc_float && dst_first_rc == rc_stack) {
1589 int offset = ra_->reg2offset(dst_first);
1590 // Further check for aligned-adjacent pair, so we can use a double store
1591 if ((src_first & 1) == 0 && src_first + 1 == src_second && (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1592 impl_helper(mach, cbuf, ra_, false, offset, src_first, Assembler::stdf_op3, "STDF", st);
1593 return;
1594 }
1595 impl_helper(mach, cbuf, ra_, false, offset, src_first, Assembler::stf_op3, "STF ", st);
1596 }
1597
1598 // Check for float load
1599 if (dst_first_rc == rc_float && src_first_rc == rc_stack) {
1600 int offset = ra_->reg2offset(src_first);
1601 // Further check for aligned-adjacent pair, so we can use a double load
1602 if ((src_first & 1) == 0 && src_first + 1 == src_second && (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1603 impl_helper(mach, cbuf, ra_, true, offset, dst_first, Assembler::lddf_op3, "LDDF", st);
1604 return;
1605 }
1606 impl_helper(mach, cbuf, ra_, true, offset, dst_first, Assembler::ldf_op3, "LDF ", st);
1607 }
1608
1609 // --------------------------------------------------------------------
1610 // Check for hi bits still needing moving. Only happens for misaligned
1611 // arguments to native calls.
1612 if (src_second == dst_second) {
1613 return; // Self copy; no move
1614 }
1615 assert(src_second_rc != rc_bad && dst_second_rc != rc_bad, "src_second & dst_second cannot be Bad");
1616
1617 #ifndef _LP64
1618 // In the LP64 build, all registers can be moved as aligned/adjacent
1619 // pairs, so there's never any need to move the high bits separately.
1620 // The 32-bit builds have to deal with the 32-bit ABI which can force
1621 // all sorts of silly alignment problems.
1622
1623 // Check for integer reg-reg copy. Hi bits are stuck up in the top
1624 // 32-bits of a 64-bit register, but are needed in low bits of another
1625 // register (else it's a hi-bits-to-hi-bits copy which should have
1626 // happened already as part of a 64-bit move)
1627 if (src_second_rc == rc_int && dst_second_rc == rc_int) {
1628 assert((src_second & 1) == 1, "its the evil O0/O1 native return case");
1629 assert((dst_second & 1) == 0, "should have moved with 1 64-bit move");
1630 // Shift src_second down to dst_second's low bits.
1631 if (cbuf) {
1632 emit3_simm13(*cbuf, Assembler::arith_op, Matcher::_regEncode[dst_second], Assembler::srlx_op3, Matcher::_regEncode[src_second-1], 0x1020);
1633 #ifndef PRODUCT
1634 } else {
1635 print_helper(st, "SRLX R_%s,32,R_%s\t! spill: Move high bits down low", OptoReg::regname(src_second - 1), OptoReg::regname(dst_second));
1636 #endif
1637 }
1638 return;
1639 }
1640
1641 // Check for high word integer store. Must down-shift the hi bits
1642 // into a temp register, then fall into the case of storing int bits.
1643 if (src_second_rc == rc_int && dst_second_rc == rc_stack && (src_second & 1) == 1) {
1644 // Shift src_second down to dst_second's low bits.
1645 if (cbuf) {
1646 emit3_simm13(*cbuf, Assembler::arith_op, Matcher::_regEncode[R_O7_num], Assembler::srlx_op3, Matcher::_regEncode[src_second-1], 0x1020);
1647 #ifndef PRODUCT
1648 } else {
1649 print_helper(st, "SRLX R_%s,32,R_%s\t! spill: Move high bits down low", OptoReg::regname(src_second-1), OptoReg::regname(R_O7_num));
1650 #endif
1651 }
1652 src_second = OptoReg::Name(R_O7_num); // Not R_O7H_num!
1653 }
1654
1655 // Check for high word integer load
1656 if (dst_second_rc == rc_int && src_second_rc == rc_stack)
1657 return impl_helper(this, cbuf, ra_, true, ra_->reg2offset(src_second), dst_second, Assembler::lduw_op3, "LDUW", size, st);
1658
1659 // Check for high word integer store
1660 if (src_second_rc == rc_int && dst_second_rc == rc_stack)
1661 return impl_helper(this, cbuf, ra_, false, ra_->reg2offset(dst_second), src_second, Assembler::stw_op3, "STW ", size, st);
1662
1663 // Check for high word float store
1664 if (src_second_rc == rc_float && dst_second_rc == rc_stack)
1665 return impl_helper(this, cbuf, ra_, false, ra_->reg2offset(dst_second), src_second, Assembler::stf_op3, "STF ", size, st);
1666
1667 #endif // !_LP64
1668
1669 Unimplemented();
1670 }
1671
1672 uint MachSpillCopyNode::implementation(CodeBuffer *cbuf,
1673 PhaseRegAlloc *ra_,
1674 bool do_size,
1675 outputStream* st) const {
1676 assert(!do_size, "not supported");
1677 mach_spill_copy_implementation_helper(this, cbuf, ra_, st);
1678 return 0;
1679 }
1680
1681 #ifndef PRODUCT
1682 void MachSpillCopyNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1683 implementation( NULL, ra_, false, st );
1684 }
1685 #endif
1686
1687 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1688 implementation( &cbuf, ra_, false, NULL );
1689 }
1690
1691 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1692 return MachNode::size(ra_);
1693 }
1694
1695 //=============================================================================
1696 #ifndef PRODUCT
1697 void MachNopNode::format(PhaseRegAlloc *, outputStream *st) const {
1698 st->print("NOP \t# %d bytes pad for loops and calls", 4 * _count);
1699 }
1700 #endif
1701
1702 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *) const {
1703 MacroAssembler _masm(&cbuf);
1704 for (int i = 0; i < _count; i += 1) {
1705 __ nop();
1706 }
1707 }
1708
1709 uint MachNopNode::size(PhaseRegAlloc *ra_) const {
1710 return 4 * _count;
1711 }
1712
1713
1714 //=============================================================================
1715 #ifndef PRODUCT
1716 void BoxLockNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1717 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1718 int reg = ra_->get_reg_first(this);
1719 st->print("LEA [R_SP+#%d+BIAS],%s",offset,Matcher::regName[reg]);
1720 }
1721 #endif
1722
1723 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1724 MacroAssembler _masm(&cbuf);
1725 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()) + STACK_BIAS;
1726 int reg = ra_->get_encode(this);
1727
1728 if (Assembler::is_simm13(offset)) {
1729 __ add(SP, offset, reg_to_register_object(reg));
1730 } else {
1731 __ set(offset, O7);
1732 __ add(SP, O7, reg_to_register_object(reg));
1733 }
1734 }
1735
1736 uint BoxLockNode::size(PhaseRegAlloc *ra_) const {
1737 // BoxLockNode is not a MachNode, so we can't just call MachNode::size(ra_)
1738 assert(ra_ == ra_->C->regalloc(), "sanity");
1739 return ra_->C->scratch_emit_size(this);
1740 }
1741
1742 //=============================================================================
1743 #ifndef PRODUCT
1744 void MachUEPNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1745 st->print_cr("\nUEP:");
1746 #ifdef _LP64
1747 if (UseCompressedClassPointers) {
1748 assert(Universe::heap() != NULL, "java heap should be initialized");
1749 st->print_cr("\tLDUW [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check - compressed klass");
1750 if (Universe::narrow_klass_base() != 0) {
1751 st->print_cr("\tSET Universe::narrow_klass_base,R_G6_heap_base");
1752 if (Universe::narrow_klass_shift() != 0) {
1753 st->print_cr("\tSLL R_G5,Universe::narrow_klass_shift,R_G5");
1754 }
1755 st->print_cr("\tADD R_G5,R_G6_heap_base,R_G5");
1756 st->print_cr("\tSET Universe::narrow_ptrs_base,R_G6_heap_base");
1757 } else {
1758 st->print_cr("\tSLL R_G5,Universe::narrow_klass_shift,R_G5");
1759 }
1760 } else {
1761 st->print_cr("\tLDX [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check");
1762 }
1763 st->print_cr("\tCMP R_G5,R_G3" );
1764 st->print ("\tTne xcc,R_G0+ST_RESERVED_FOR_USER_0+2");
1765 #else // _LP64
1766 st->print_cr("\tLDUW [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check");
1767 st->print_cr("\tCMP R_G5,R_G3" );
1768 st->print ("\tTne icc,R_G0+ST_RESERVED_FOR_USER_0+2");
1769 #endif // _LP64
1770 }
1771 #endif
1772
1773 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1774 MacroAssembler _masm(&cbuf);
1775 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode());
1776 Register temp_reg = G3;
1777 assert( G5_ic_reg != temp_reg, "conflicting registers" );
1778
1779 // Load klass from receiver
1780 __ load_klass(O0, temp_reg);
1781 // Compare against expected klass
1782 __ cmp(temp_reg, G5_ic_reg);
1783 // Branch to miss code, checks xcc or icc depending
1784 __ trap(Assembler::notEqual, Assembler::ptr_cc, G0, ST_RESERVED_FOR_USER_0+2);
1785 }
1786
1787 uint MachUEPNode::size(PhaseRegAlloc *ra_) const {
1788 return MachNode::size(ra_);
1789 }
1790
1791
1792 //=============================================================================
1793
1794
1795 // Emit exception handler code.
1796 int HandlerImpl::emit_exception_handler(CodeBuffer& cbuf) {
1797 Register temp_reg = G3;
1798 AddressLiteral exception_blob(OptoRuntime::exception_blob()->entry_point());
1799 MacroAssembler _masm(&cbuf);
1800
1801 address base = __ start_a_stub(size_exception_handler());
1802 if (base == NULL) {
1803 ciEnv::current()->record_failure("CodeCache is full");
1804 return 0; // CodeBuffer::expand failed
1805 }
1806
1807 int offset = __ offset();
1808
1809 __ JUMP(exception_blob, temp_reg, 0); // sethi;jmp
1810 __ delayed()->nop();
1811
1812 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow");
1813
1814 __ end_a_stub();
1815
1816 return offset;
1817 }
1818
1819 int HandlerImpl::emit_deopt_handler(CodeBuffer& cbuf) {
1820 // Can't use any of the current frame's registers as we may have deopted
1821 // at a poll and everything (including G3) can be live.
1822 Register temp_reg = L0;
1823 AddressLiteral deopt_blob(SharedRuntime::deopt_blob()->unpack());
1824 MacroAssembler _masm(&cbuf);
1825
1826 address base = __ start_a_stub(size_deopt_handler());
1827 if (base == NULL) {
1828 ciEnv::current()->record_failure("CodeCache is full");
1829 return 0; // CodeBuffer::expand failed
1830 }
1831
1832 int offset = __ offset();
1833 __ save_frame(0);
1834 __ JUMP(deopt_blob, temp_reg, 0); // sethi;jmp
1835 __ delayed()->restore();
1836
1837 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow");
1838
1839 __ end_a_stub();
1840 return offset;
1841
1842 }
1843
1844 // Given a register encoding, produce a Integer Register object
1845 static Register reg_to_register_object(int register_encoding) {
1846 assert(L5->encoding() == R_L5_enc && G1->encoding() == R_G1_enc, "right coding");
1847 return as_Register(register_encoding);
1848 }
1849
1850 // Given a register encoding, produce a single-precision Float Register object
1851 static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding) {
1852 assert(F5->encoding(FloatRegisterImpl::S) == R_F5_enc && F12->encoding(FloatRegisterImpl::S) == R_F12_enc, "right coding");
1853 return as_SingleFloatRegister(register_encoding);
1854 }
1855
1856 // Given a register encoding, produce a double-precision Float Register object
1857 static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding) {
1858 assert(F4->encoding(FloatRegisterImpl::D) == R_F4_enc, "right coding");
1859 assert(F32->encoding(FloatRegisterImpl::D) == R_D32_enc, "right coding");
1860 return as_DoubleFloatRegister(register_encoding);
1861 }
1862
1863 const bool Matcher::match_rule_supported(int opcode) {
1864 if (!has_match_rule(opcode))
1865 return false;
1866
1867 switch (opcode) {
1868 case Op_CountLeadingZerosI:
1869 case Op_CountLeadingZerosL:
1870 if (!(UsePopCountInstruction || UseCountLeadingZerosInstruction))
1871 return false;
1872 break;
1873 case Op_CountTrailingZerosI:
1874 case Op_CountTrailingZerosL:
1875 case Op_PopCountI:
1876 case Op_PopCountL:
1877 if (!UsePopCountInstruction)
1878 return false;
1879 case Op_CompareAndSwapL:
1880 #ifdef _LP64
1881 case Op_CompareAndSwapP:
1882 #endif
1883 if (!VM_Version::supports_cx8())
1884 return false;
1885 break;
1886 }
1887
1888 return true; // Per default match rules are supported.
1889 }
1890
1891 const bool Matcher::match_rule_supported_vector(int opcode, int vlen) {
1892
1893 // TODO
1894 // identify extra cases that we might want to provide match rules for
1895 // e.g. Op_ vector nodes and other intrinsics while guarding with vlen
1896 bool ret_value = match_rule_supported(opcode);
1897 // Add rules here.
1898
1899 return ret_value; // Per default match rules are supported.
1900 }
1901
1902 const bool Matcher::has_predicated_vectors(void) {
1903 return false;
1904 }
1905
1906 const int Matcher::float_pressure(int default_pressure_threshold) {
1907 return default_pressure_threshold;
1908 }
1909
1910 int Matcher::regnum_to_fpu_offset(int regnum) {
1911 return regnum - 32; // The FP registers are in the second chunk
1912 }
1913
1914 #ifdef ASSERT
1915 address last_rethrow = NULL; // debugging aid for Rethrow encoding
1916 #endif
1917
1918 // Vector width in bytes
1919 const int Matcher::vector_width_in_bytes(BasicType bt) {
1920 assert(MaxVectorSize == 8, "");
1921 return 8;
1922 }
1923
1924 // Vector ideal reg
1925 const int Matcher::vector_ideal_reg(int size) {
1926 assert(MaxVectorSize == 8, "");
1927 return Op_RegD;
1928 }
1929
1930 const int Matcher::vector_shift_count_ideal_reg(int size) {
1931 fatal("vector shift is not supported");
1932 return Node::NotAMachineReg;
1933 }
1934
1935 // Limits on vector size (number of elements) loaded into vector.
1936 const int Matcher::max_vector_size(const BasicType bt) {
1937 assert(is_java_primitive(bt), "only primitive type vectors");
1938 return vector_width_in_bytes(bt)/type2aelembytes(bt);
1939 }
1940
1941 const int Matcher::min_vector_size(const BasicType bt) {
1942 return max_vector_size(bt); // Same as max.
1943 }
1944
1945 // SPARC doesn't support misaligned vectors store/load.
1946 const bool Matcher::misaligned_vectors_ok() {
1947 return false;
1948 }
1949
1950 // Current (2013) SPARC platforms need to read original key
1951 // to construct decryption expanded key
1952 const bool Matcher::pass_original_key_for_aes() {
1953 return true;
1954 }
1955
1956 // USII supports fxtof through the whole range of number, USIII doesn't
1957 const bool Matcher::convL2FSupported(void) {
1958 return VM_Version::has_fast_fxtof();
1959 }
1960
1961 // Is this branch offset short enough that a short branch can be used?
1962 //
1963 // NOTE: If the platform does not provide any short branch variants, then
1964 // this method should return false for offset 0.
1965 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
1966 // The passed offset is relative to address of the branch.
1967 // Don't need to adjust the offset.
1968 return UseCBCond && Assembler::is_simm12(offset);
1969 }
1970
1971 const bool Matcher::isSimpleConstant64(jlong value) {
1972 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?.
1973 // Depends on optimizations in MacroAssembler::setx.
1974 int hi = (int)(value >> 32);
1975 int lo = (int)(value & ~0);
1976 return (hi == 0) || (hi == -1) || (lo == 0);
1977 }
1978
1979 // No scaling for the parameter the ClearArray node.
1980 const bool Matcher::init_array_count_is_in_bytes = true;
1981
1982 // No additional cost for CMOVL.
1983 const int Matcher::long_cmove_cost() { return 0; }
1984
1985 // CMOVF/CMOVD are expensive on T4 and on SPARC64.
1986 const int Matcher::float_cmove_cost() {
1987 return (VM_Version::is_T4() || VM_Version::is_sparc64()) ? ConditionalMoveLimit : 0;
1988 }
1989
1990 // Does the CPU require late expand (see block.cpp for description of late expand)?
1991 const bool Matcher::require_postalloc_expand = false;
1992
1993 // Do we need to mask the count passed to shift instructions or does
1994 // the cpu only look at the lower 5/6 bits anyway?
1995 const bool Matcher::need_masked_shift_count = false;
1996
1997 bool Matcher::narrow_oop_use_complex_address() {
1998 NOT_LP64(ShouldNotCallThis());
1999 assert(UseCompressedOops, "only for compressed oops code");
2000 return false;
2001 }
2002
2003 bool Matcher::narrow_klass_use_complex_address() {
2004 NOT_LP64(ShouldNotCallThis());
2005 assert(UseCompressedClassPointers, "only for compressed klass code");
2006 return false;
2007 }
2008
2009 bool Matcher::const_oop_prefer_decode() {
2010 // TODO: Check if loading ConP from TOC in heap-based mode is better:
2011 // Prefer ConN+DecodeN over ConP in simple compressed oops mode.
2012 // return Universe::narrow_oop_base() == NULL;
2013 return true;
2014 }
2015
2016 bool Matcher::const_klass_prefer_decode() {
2017 // TODO: Check if loading ConP from TOC in heap-based mode is better:
2018 // Prefer ConNKlass+DecodeNKlass over ConP in simple compressed klass mode.
2019 // return Universe::narrow_klass_base() == NULL;
2020 return true;
2021 }
2022
2023 // Is it better to copy float constants, or load them directly from memory?
2024 // Intel can load a float constant from a direct address, requiring no
2025 // extra registers. Most RISCs will have to materialize an address into a
2026 // register first, so they would do better to copy the constant from stack.
2027 const bool Matcher::rematerialize_float_constants = false;
2028
2029 // If CPU can load and store mis-aligned doubles directly then no fixup is
2030 // needed. Else we split the double into 2 integer pieces and move it
2031 // piece-by-piece. Only happens when passing doubles into C code as the
2032 // Java calling convention forces doubles to be aligned.
2033 #ifdef _LP64
2034 const bool Matcher::misaligned_doubles_ok = true;
2035 #else
2036 const bool Matcher::misaligned_doubles_ok = false;
2037 #endif
2038
2039 // No-op on SPARC.
2040 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {
2041 }
2042
2043 // Advertise here if the CPU requires explicit rounding operations
2044 // to implement the UseStrictFP mode.
2045 const bool Matcher::strict_fp_requires_explicit_rounding = false;
2046
2047 // Are floats converted to double when stored to stack during deoptimization?
2048 // Sparc does not handle callee-save floats.
2049 bool Matcher::float_in_double() { return false; }
2050
2051 // Do ints take an entire long register or just half?
2052 // Note that we if-def off of _LP64.
2053 // The relevant question is how the int is callee-saved. In _LP64
2054 // the whole long is written but de-opt'ing will have to extract
2055 // the relevant 32 bits, in not-_LP64 only the low 32 bits is written.
2056 #ifdef _LP64
2057 const bool Matcher::int_in_long = true;
2058 #else
2059 const bool Matcher::int_in_long = false;
2060 #endif
2061
2062 // Return whether or not this register is ever used as an argument. This
2063 // function is used on startup to build the trampoline stubs in generateOptoStub.
2064 // Registers not mentioned will be killed by the VM call in the trampoline, and
2065 // arguments in those registers not be available to the callee.
2066 bool Matcher::can_be_java_arg( int reg ) {
2067 // Standard sparc 6 args in registers
2068 if( reg == R_I0_num ||
2069 reg == R_I1_num ||
2070 reg == R_I2_num ||
2071 reg == R_I3_num ||
2072 reg == R_I4_num ||
2073 reg == R_I5_num ) return true;
2074 #ifdef _LP64
2075 // 64-bit builds can pass 64-bit pointers and longs in
2076 // the high I registers
2077 if( reg == R_I0H_num ||
2078 reg == R_I1H_num ||
2079 reg == R_I2H_num ||
2080 reg == R_I3H_num ||
2081 reg == R_I4H_num ||
2082 reg == R_I5H_num ) return true;
2083
2084 if ((UseCompressedOops) && (reg == R_G6_num || reg == R_G6H_num)) {
2085 return true;
2086 }
2087
2088 #else
2089 // 32-bit builds with longs-in-one-entry pass longs in G1 & G4.
2090 // Longs cannot be passed in O regs, because O regs become I regs
2091 // after a 'save' and I regs get their high bits chopped off on
2092 // interrupt.
2093 if( reg == R_G1H_num || reg == R_G1_num ) return true;
2094 if( reg == R_G4H_num || reg == R_G4_num ) return true;
2095 #endif
2096 // A few float args in registers
2097 if( reg >= R_F0_num && reg <= R_F7_num ) return true;
2098
2099 return false;
2100 }
2101
2102 bool Matcher::is_spillable_arg( int reg ) {
2103 return can_be_java_arg(reg);
2104 }
2105
2106 bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) {
2107 // Use hardware SDIVX instruction when it is
2108 // faster than a code which use multiply.
2109 return VM_Version::has_fast_idiv();
2110 }
2111
2112 // Register for DIVI projection of divmodI
2113 RegMask Matcher::divI_proj_mask() {
2114 ShouldNotReachHere();
2115 return RegMask();
2116 }
2117
2118 // Register for MODI projection of divmodI
2119 RegMask Matcher::modI_proj_mask() {
2120 ShouldNotReachHere();
2121 return RegMask();
2122 }
2123
2124 // Register for DIVL projection of divmodL
2125 RegMask Matcher::divL_proj_mask() {
2126 ShouldNotReachHere();
2127 return RegMask();
2128 }
2129
2130 // Register for MODL projection of divmodL
2131 RegMask Matcher::modL_proj_mask() {
2132 ShouldNotReachHere();
2133 return RegMask();
2134 }
2135
2136 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
2137 return L7_REGP_mask();
2138 }
2139
2140
2141 const bool Matcher::convi2l_type_required = true;
2142
2143 // Should the Matcher clone shifts on addressing modes, expecting them
2144 // to be subsumed into complex addressing expressions or compute them
2145 // into registers?
2146 bool Matcher::clone_address_expressions(AddPNode* m, Matcher::MStack& mstack, VectorSet& address_visited) {
2147 return clone_base_plus_offset_address(m, mstack, address_visited);
2148 }
2149
2150 void Compile::reshape_address(AddPNode* addp) {
2151 }
2152
2153 %}
2154
2155
2156 // The intptr_t operand types, defined by textual substitution.
2157 // (Cf. opto/type.hpp. This lets us avoid many, many other ifdefs.)
2158 #ifdef _LP64
2159 #define immX immL
2160 #define immX13 immL13
2161 #define immX13m7 immL13m7
2162 #define iRegX iRegL
2163 #define g1RegX g1RegL
2164 #else
2165 #define immX immI
2166 #define immX13 immI13
2167 #define immX13m7 immI13m7
2168 #define iRegX iRegI
2169 #define g1RegX g1RegI
2170 #endif
2171
2172 //----------ENCODING BLOCK-----------------------------------------------------
2173 // This block specifies the encoding classes used by the compiler to output
2174 // byte streams. Encoding classes are parameterized macros used by
2175 // Machine Instruction Nodes in order to generate the bit encoding of the
2176 // instruction. Operands specify their base encoding interface with the
2177 // interface keyword. There are currently supported four interfaces,
2178 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an
2179 // operand to generate a function which returns its register number when
2180 // queried. CONST_INTER causes an operand to generate a function which
2181 // returns the value of the constant when queried. MEMORY_INTER causes an
2182 // operand to generate four functions which return the Base Register, the
2183 // Index Register, the Scale Value, and the Offset Value of the operand when
2184 // queried. COND_INTER causes an operand to generate six functions which
2185 // return the encoding code (ie - encoding bits for the instruction)
2186 // associated with each basic boolean condition for a conditional instruction.
2187 //
2188 // Instructions specify two basic values for encoding. Again, a function
2189 // is available to check if the constant displacement is an oop. They use the
2190 // ins_encode keyword to specify their encoding classes (which must be
2191 // a sequence of enc_class names, and their parameters, specified in
2192 // the encoding block), and they use the
2193 // opcode keyword to specify, in order, their primary, secondary, and
2194 // tertiary opcode. Only the opcode sections which a particular instruction
2195 // needs for encoding need to be specified.
2196 encode %{
2197 enc_class enc_untested %{
2198 #ifdef ASSERT
2199 MacroAssembler _masm(&cbuf);
2200 __ untested("encoding");
2201 #endif
2202 %}
2203
2204 enc_class form3_mem_reg( memory mem, iRegI dst ) %{
2205 emit_form3_mem_reg(cbuf, ra_, this, $primary, $tertiary,
2206 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg);
2207 %}
2208
2209 enc_class simple_form3_mem_reg( memory mem, iRegI dst ) %{
2210 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1,
2211 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg);
2212 %}
2213
2214 enc_class form3_mem_prefetch_read( memory mem ) %{
2215 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1,
2216 $mem$$base, $mem$$disp, $mem$$index, 0/*prefetch function many-reads*/);
2217 %}
2218
2219 enc_class form3_mem_prefetch_write( memory mem ) %{
2220 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1,
2221 $mem$$base, $mem$$disp, $mem$$index, 2/*prefetch function many-writes*/);
2222 %}
2223
2224 enc_class form3_mem_reg_long_unaligned_marshal( memory mem, iRegL reg ) %{
2225 assert(Assembler::is_simm13($mem$$disp ), "need disp and disp+4");
2226 assert(Assembler::is_simm13($mem$$disp+4), "need disp and disp+4");
2227 guarantee($mem$$index == R_G0_enc, "double index?");
2228 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, R_O7_enc );
2229 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg );
2230 emit3_simm13( cbuf, Assembler::arith_op, $reg$$reg, Assembler::sllx_op3, $reg$$reg, 0x1020 );
2231 emit3( cbuf, Assembler::arith_op, $reg$$reg, Assembler::or_op3, $reg$$reg, 0, R_O7_enc );
2232 %}
2233
2234 enc_class form3_mem_reg_double_unaligned( memory mem, RegD_low reg ) %{
2235 assert(Assembler::is_simm13($mem$$disp ), "need disp and disp+4");
2236 assert(Assembler::is_simm13($mem$$disp+4), "need disp and disp+4");
2237 guarantee($mem$$index == R_G0_enc, "double index?");
2238 // Load long with 2 instructions
2239 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg+0 );
2240 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, $reg$$reg+1 );
2241 %}
2242
2243 //%%% form3_mem_plus_4_reg is a hack--get rid of it
2244 enc_class form3_mem_plus_4_reg( memory mem, iRegI dst ) %{
2245 guarantee($mem$$disp, "cannot offset a reg-reg operand by 4");
2246 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp + 4, $mem$$index, $dst$$reg);
2247 %}
2248
2249 enc_class form3_g0_rs2_rd_move( iRegI rs2, iRegI rd ) %{
2250 // Encode a reg-reg copy. If it is useless, then empty encoding.
2251 if( $rs2$$reg != $rd$$reg )
2252 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, $rs2$$reg );
2253 %}
2254
2255 // Target lo half of long
2256 enc_class form3_g0_rs2_rd_move_lo( iRegI rs2, iRegL rd ) %{
2257 // Encode a reg-reg copy. If it is useless, then empty encoding.
2258 if( $rs2$$reg != LONG_LO_REG($rd$$reg) )
2259 emit3( cbuf, Assembler::arith_op, LONG_LO_REG($rd$$reg), Assembler::or_op3, 0, 0, $rs2$$reg );
2260 %}
2261
2262 // Source lo half of long
2263 enc_class form3_g0_rs2_rd_move_lo2( iRegL rs2, iRegI rd ) %{
2264 // Encode a reg-reg copy. If it is useless, then empty encoding.
2265 if( LONG_LO_REG($rs2$$reg) != $rd$$reg )
2266 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_LO_REG($rs2$$reg) );
2267 %}
2268
2269 // Target hi half of long
2270 enc_class form3_rs1_rd_copysign_hi( iRegI rs1, iRegL rd ) %{
2271 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 31 );
2272 %}
2273
2274 // Source lo half of long, and leave it sign extended.
2275 enc_class form3_rs1_rd_signextend_lo1( iRegL rs1, iRegI rd ) %{
2276 // Sign extend low half
2277 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 0, 0 );
2278 %}
2279
2280 // Source hi half of long, and leave it sign extended.
2281 enc_class form3_rs1_rd_copy_hi1( iRegL rs1, iRegI rd ) %{
2282 // Shift high half to low half
2283 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::srlx_op3, $rs1$$reg, 32 );
2284 %}
2285
2286 // Source hi half of long
2287 enc_class form3_g0_rs2_rd_move_hi2( iRegL rs2, iRegI rd ) %{
2288 // Encode a reg-reg copy. If it is useless, then empty encoding.
2289 if( LONG_HI_REG($rs2$$reg) != $rd$$reg )
2290 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_HI_REG($rs2$$reg) );
2291 %}
2292
2293 enc_class form3_rs1_rs2_rd( iRegI rs1, iRegI rs2, iRegI rd ) %{
2294 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0, $rs2$$reg );
2295 %}
2296
2297 enc_class enc_to_bool( iRegI src, iRegI dst ) %{
2298 emit3 ( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, 0, 0, $src$$reg );
2299 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::addc_op3 , 0, 0 );
2300 %}
2301
2302 enc_class enc_ltmask( iRegI p, iRegI q, iRegI dst ) %{
2303 emit3 ( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, $p$$reg, 0, $q$$reg );
2304 // clear if nothing else is happening
2305 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, 0 );
2306 // blt,a,pn done
2307 emit2_19 ( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less, Assembler::bp_op2, Assembler::icc, 0/*predict not taken*/, 2 );
2308 // mov dst,-1 in delay slot
2309 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 );
2310 %}
2311
2312 enc_class form3_rs1_imm5_rd( iRegI rs1, immU5 imm5, iRegI rd ) %{
2313 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $imm5$$constant & 0x1F );
2314 %}
2315
2316 enc_class form3_sd_rs1_imm6_rd( iRegL rs1, immU6 imm6, iRegL rd ) %{
2317 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, ($imm6$$constant & 0x3F) | 0x1000 );
2318 %}
2319
2320 enc_class form3_sd_rs1_rs2_rd( iRegL rs1, iRegI rs2, iRegL rd ) %{
2321 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0x80, $rs2$$reg );
2322 %}
2323
2324 enc_class form3_rs1_simm13_rd( iRegI rs1, immI13 simm13, iRegI rd ) %{
2325 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $simm13$$constant );
2326 %}
2327
2328 enc_class move_return_pc_to_o1() %{
2329 emit3_simm13( cbuf, Assembler::arith_op, R_O1_enc, Assembler::add_op3, R_O7_enc, frame::pc_return_offset );
2330 %}
2331
2332 #ifdef _LP64
2333 /* %%% merge with enc_to_bool */
2334 enc_class enc_convP2B( iRegI dst, iRegP src ) %{
2335 MacroAssembler _masm(&cbuf);
2336
2337 Register src_reg = reg_to_register_object($src$$reg);
2338 Register dst_reg = reg_to_register_object($dst$$reg);
2339 __ movr(Assembler::rc_nz, src_reg, 1, dst_reg);
2340 %}
2341 #endif
2342
2343 enc_class enc_cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp ) %{
2344 // (Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)))
2345 MacroAssembler _masm(&cbuf);
2346
2347 Register p_reg = reg_to_register_object($p$$reg);
2348 Register q_reg = reg_to_register_object($q$$reg);
2349 Register y_reg = reg_to_register_object($y$$reg);
2350 Register tmp_reg = reg_to_register_object($tmp$$reg);
2351
2352 __ subcc( p_reg, q_reg, p_reg );
2353 __ add ( p_reg, y_reg, tmp_reg );
2354 __ movcc( Assembler::less, false, Assembler::icc, tmp_reg, p_reg );
2355 %}
2356
2357 enc_class form_d2i_helper(regD src, regF dst) %{
2358 // fcmp %fcc0,$src,$src
2359 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg );
2360 // branch %fcc0 not-nan, predict taken
2361 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2362 // fdtoi $src,$dst
2363 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fdtoi_opf, $src$$reg );
2364 // fitos $dst,$dst (if nan)
2365 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fitos_opf, $dst$$reg );
2366 // clear $dst (if nan)
2367 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg );
2368 // carry on here...
2369 %}
2370
2371 enc_class form_d2l_helper(regD src, regD dst) %{
2372 // fcmp %fcc0,$src,$src check for NAN
2373 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg );
2374 // branch %fcc0 not-nan, predict taken
2375 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2376 // fdtox $src,$dst convert in delay slot
2377 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fdtox_opf, $src$$reg );
2378 // fxtod $dst,$dst (if nan)
2379 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fxtod_opf, $dst$$reg );
2380 // clear $dst (if nan)
2381 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg );
2382 // carry on here...
2383 %}
2384
2385 enc_class form_f2i_helper(regF src, regF dst) %{
2386 // fcmps %fcc0,$src,$src
2387 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg );
2388 // branch %fcc0 not-nan, predict taken
2389 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2390 // fstoi $src,$dst
2391 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fstoi_opf, $src$$reg );
2392 // fitos $dst,$dst (if nan)
2393 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fitos_opf, $dst$$reg );
2394 // clear $dst (if nan)
2395 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg );
2396 // carry on here...
2397 %}
2398
2399 enc_class form_f2l_helper(regF src, regD dst) %{
2400 // fcmps %fcc0,$src,$src
2401 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg );
2402 // branch %fcc0 not-nan, predict taken
2403 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2404 // fstox $src,$dst
2405 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fstox_opf, $src$$reg );
2406 // fxtod $dst,$dst (if nan)
2407 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fxtod_opf, $dst$$reg );
2408 // clear $dst (if nan)
2409 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg );
2410 // carry on here...
2411 %}
2412
2413 enc_class form3_opf_rs2F_rdF(regF rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2414 enc_class form3_opf_rs2F_rdD(regF rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2415 enc_class form3_opf_rs2D_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2416 enc_class form3_opf_rs2D_rdD(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2417
2418 enc_class form3_opf_rs2D_lo_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg+1); %}
2419
2420 enc_class form3_opf_rs2D_hi_rdD_hi(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2421 enc_class form3_opf_rs2D_lo_rdD_lo(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg+1,$primary,0,$tertiary,$rs2$$reg+1); %}
2422
2423 enc_class form3_opf_rs1F_rs2F_rdF( regF rs1, regF rs2, regF rd ) %{
2424 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2425 %}
2426
2427 enc_class form3_opf_rs1D_rs2D_rdD( regD rs1, regD rs2, regD rd ) %{
2428 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2429 %}
2430
2431 enc_class form3_opf_rs1F_rs2F_fcc( regF rs1, regF rs2, flagsRegF fcc ) %{
2432 emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2433 %}
2434
2435 enc_class form3_opf_rs1D_rs2D_fcc( regD rs1, regD rs2, flagsRegF fcc ) %{
2436 emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2437 %}
2438
2439 enc_class form3_convI2F(regF rs2, regF rd) %{
2440 emit3(cbuf,Assembler::arith_op,$rd$$reg,Assembler::fpop1_op3,0,$secondary,$rs2$$reg);
2441 %}
2442
2443 // Encloding class for traceable jumps
2444 enc_class form_jmpl(g3RegP dest) %{
2445 emit_jmpl(cbuf, $dest$$reg);
2446 %}
2447
2448 enc_class form_jmpl_set_exception_pc(g1RegP dest) %{
2449 emit_jmpl_set_exception_pc(cbuf, $dest$$reg);
2450 %}
2451
2452 enc_class form2_nop() %{
2453 emit_nop(cbuf);
2454 %}
2455
2456 enc_class form2_illtrap() %{
2457 emit_illtrap(cbuf);
2458 %}
2459
2460
2461 // Compare longs and convert into -1, 0, 1.
2462 enc_class cmpl_flag( iRegL src1, iRegL src2, iRegI dst ) %{
2463 // CMP $src1,$src2
2464 emit3( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, $src1$$reg, 0, $src2$$reg );
2465 // blt,a,pn done
2466 emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less , Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 5 );
2467 // mov dst,-1 in delay slot
2468 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 );
2469 // bgt,a,pn done
2470 emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::greater, Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 3 );
2471 // mov dst,1 in delay slot
2472 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, 1 );
2473 // CLR $dst
2474 emit3( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3 , 0, 0, 0 );
2475 %}
2476
2477 enc_class enc_PartialSubtypeCheck() %{
2478 MacroAssembler _masm(&cbuf);
2479 __ call(StubRoutines::Sparc::partial_subtype_check(), relocInfo::runtime_call_type);
2480 __ delayed()->nop();
2481 %}
2482
2483 enc_class enc_bp( label labl, cmpOp cmp, flagsReg cc ) %{
2484 MacroAssembler _masm(&cbuf);
2485 Label* L = $labl$$label;
2486 Assembler::Predict predict_taken =
2487 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
2488
2489 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
2490 __ delayed()->nop();
2491 %}
2492
2493 enc_class enc_bpr( label labl, cmpOp_reg cmp, iRegI op1 ) %{
2494 MacroAssembler _masm(&cbuf);
2495 Label* L = $labl$$label;
2496 Assembler::Predict predict_taken =
2497 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
2498
2499 __ bpr( (Assembler::RCondition)($cmp$$cmpcode), false, predict_taken, as_Register($op1$$reg), *L);
2500 __ delayed()->nop();
2501 %}
2502
2503 enc_class enc_cmov_reg( cmpOp cmp, iRegI dst, iRegI src, immI pcc) %{
2504 int op = (Assembler::arith_op << 30) |
2505 ($dst$$reg << 25) |
2506 (Assembler::movcc_op3 << 19) |
2507 (1 << 18) | // cc2 bit for 'icc'
2508 ($cmp$$cmpcode << 14) |
2509 (0 << 13) | // select register move
2510 ($pcc$$constant << 11) | // cc1, cc0 bits for 'icc' or 'xcc'
2511 ($src$$reg << 0);
2512 cbuf.insts()->emit_int32(op);
2513 %}
2514
2515 enc_class enc_cmov_imm( cmpOp cmp, iRegI dst, immI11 src, immI pcc ) %{
2516 int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits
2517 int op = (Assembler::arith_op << 30) |
2518 ($dst$$reg << 25) |
2519 (Assembler::movcc_op3 << 19) |
2520 (1 << 18) | // cc2 bit for 'icc'
2521 ($cmp$$cmpcode << 14) |
2522 (1 << 13) | // select immediate move
2523 ($pcc$$constant << 11) | // cc1, cc0 bits for 'icc'
2524 (simm11 << 0);
2525 cbuf.insts()->emit_int32(op);
2526 %}
2527
2528 enc_class enc_cmov_reg_f( cmpOpF cmp, iRegI dst, iRegI src, flagsRegF fcc ) %{
2529 int op = (Assembler::arith_op << 30) |
2530 ($dst$$reg << 25) |
2531 (Assembler::movcc_op3 << 19) |
2532 (0 << 18) | // cc2 bit for 'fccX'
2533 ($cmp$$cmpcode << 14) |
2534 (0 << 13) | // select register move
2535 ($fcc$$reg << 11) | // cc1, cc0 bits for fcc0-fcc3
2536 ($src$$reg << 0);
2537 cbuf.insts()->emit_int32(op);
2538 %}
2539
2540 enc_class enc_cmov_imm_f( cmpOp cmp, iRegI dst, immI11 src, flagsRegF fcc ) %{
2541 int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits
2542 int op = (Assembler::arith_op << 30) |
2543 ($dst$$reg << 25) |
2544 (Assembler::movcc_op3 << 19) |
2545 (0 << 18) | // cc2 bit for 'fccX'
2546 ($cmp$$cmpcode << 14) |
2547 (1 << 13) | // select immediate move
2548 ($fcc$$reg << 11) | // cc1, cc0 bits for fcc0-fcc3
2549 (simm11 << 0);
2550 cbuf.insts()->emit_int32(op);
2551 %}
2552
2553 enc_class enc_cmovf_reg( cmpOp cmp, regD dst, regD src, immI pcc ) %{
2554 int op = (Assembler::arith_op << 30) |
2555 ($dst$$reg << 25) |
2556 (Assembler::fpop2_op3 << 19) |
2557 (0 << 18) |
2558 ($cmp$$cmpcode << 14) |
2559 (1 << 13) | // select register move
2560 ($pcc$$constant << 11) | // cc1-cc0 bits for 'icc' or 'xcc'
2561 ($primary << 5) | // select single, double or quad
2562 ($src$$reg << 0);
2563 cbuf.insts()->emit_int32(op);
2564 %}
2565
2566 enc_class enc_cmovff_reg( cmpOpF cmp, flagsRegF fcc, regD dst, regD src ) %{
2567 int op = (Assembler::arith_op << 30) |
2568 ($dst$$reg << 25) |
2569 (Assembler::fpop2_op3 << 19) |
2570 (0 << 18) |
2571 ($cmp$$cmpcode << 14) |
2572 ($fcc$$reg << 11) | // cc2-cc0 bits for 'fccX'
2573 ($primary << 5) | // select single, double or quad
2574 ($src$$reg << 0);
2575 cbuf.insts()->emit_int32(op);
2576 %}
2577
2578 // Used by the MIN/MAX encodings. Same as a CMOV, but
2579 // the condition comes from opcode-field instead of an argument.
2580 enc_class enc_cmov_reg_minmax( iRegI dst, iRegI src ) %{
2581 int op = (Assembler::arith_op << 30) |
2582 ($dst$$reg << 25) |
2583 (Assembler::movcc_op3 << 19) |
2584 (1 << 18) | // cc2 bit for 'icc'
2585 ($primary << 14) |
2586 (0 << 13) | // select register move
2587 (0 << 11) | // cc1, cc0 bits for 'icc'
2588 ($src$$reg << 0);
2589 cbuf.insts()->emit_int32(op);
2590 %}
2591
2592 enc_class enc_cmov_reg_minmax_long( iRegL dst, iRegL src ) %{
2593 int op = (Assembler::arith_op << 30) |
2594 ($dst$$reg << 25) |
2595 (Assembler::movcc_op3 << 19) |
2596 (6 << 16) | // cc2 bit for 'xcc'
2597 ($primary << 14) |
2598 (0 << 13) | // select register move
2599 (0 << 11) | // cc1, cc0 bits for 'icc'
2600 ($src$$reg << 0);
2601 cbuf.insts()->emit_int32(op);
2602 %}
2603
2604 enc_class Set13( immI13 src, iRegI rd ) %{
2605 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, $src$$constant );
2606 %}
2607
2608 enc_class SetHi22( immI src, iRegI rd ) %{
2609 emit2_22( cbuf, Assembler::branch_op, $rd$$reg, Assembler::sethi_op2, $src$$constant );
2610 %}
2611
2612 enc_class Set32( immI src, iRegI rd ) %{
2613 MacroAssembler _masm(&cbuf);
2614 __ set($src$$constant, reg_to_register_object($rd$$reg));
2615 %}
2616
2617 enc_class call_epilog %{
2618 if( VerifyStackAtCalls ) {
2619 MacroAssembler _masm(&cbuf);
2620 int framesize = ra_->C->frame_size_in_bytes();
2621 Register temp_reg = G3;
2622 __ add(SP, framesize, temp_reg);
2623 __ cmp(temp_reg, FP);
2624 __ breakpoint_trap(Assembler::notEqual, Assembler::ptr_cc);
2625 }
2626 %}
2627
2628 // Long values come back from native calls in O0:O1 in the 32-bit VM, copy the value
2629 // to G1 so the register allocator will not have to deal with the misaligned register
2630 // pair.
2631 enc_class adjust_long_from_native_call %{
2632 #ifndef _LP64
2633 if (returns_long()) {
2634 // sllx O0,32,O0
2635 emit3_simm13( cbuf, Assembler::arith_op, R_O0_enc, Assembler::sllx_op3, R_O0_enc, 0x1020 );
2636 // srl O1,0,O1
2637 emit3_simm13( cbuf, Assembler::arith_op, R_O1_enc, Assembler::srl_op3, R_O1_enc, 0x0000 );
2638 // or O0,O1,G1
2639 emit3 ( cbuf, Assembler::arith_op, R_G1_enc, Assembler:: or_op3, R_O0_enc, 0, R_O1_enc );
2640 }
2641 #endif
2642 %}
2643
2644 enc_class Java_To_Runtime (method meth) %{ // CALL Java_To_Runtime
2645 // CALL directly to the runtime
2646 // The user of this is responsible for ensuring that R_L7 is empty (killed).
2647 emit_call_reloc(cbuf, $meth$$method, runtime_call_Relocation::spec(), /*preserve_g2=*/true);
2648 %}
2649
2650 enc_class preserve_SP %{
2651 MacroAssembler _masm(&cbuf);
2652 __ mov(SP, L7_mh_SP_save);
2653 %}
2654
2655 enc_class restore_SP %{
2656 MacroAssembler _masm(&cbuf);
2657 __ mov(L7_mh_SP_save, SP);
2658 %}
2659
2660 enc_class Java_Static_Call (method meth) %{ // JAVA STATIC CALL
2661 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine
2662 // who we intended to call.
2663 if (!_method) {
2664 emit_call_reloc(cbuf, $meth$$method, runtime_call_Relocation::spec());
2665 } else {
2666 int method_index = resolved_method_index(cbuf);
2667 RelocationHolder rspec = _optimized_virtual ? opt_virtual_call_Relocation::spec(method_index)
2668 : static_call_Relocation::spec(method_index);
2669 emit_call_reloc(cbuf, $meth$$method, rspec);
2670
2671 // Emit stub for static call.
2672 address stub = CompiledStaticCall::emit_to_interp_stub(cbuf);
2673 if (stub == NULL) {
2674 ciEnv::current()->record_failure("CodeCache is full");
2675 return;
2676 }
2677 }
2678 %}
2679
2680 enc_class Java_Dynamic_Call (method meth) %{ // JAVA DYNAMIC CALL
2681 MacroAssembler _masm(&cbuf);
2682 __ set_inst_mark();
2683 int vtable_index = this->_vtable_index;
2684 // MachCallDynamicJavaNode::ret_addr_offset uses this same test
2685 if (vtable_index < 0) {
2686 // must be invalid_vtable_index, not nonvirtual_vtable_index
2687 assert(vtable_index == Method::invalid_vtable_index, "correct sentinel value");
2688 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode());
2689 assert(G5_ic_reg == G5_inline_cache_reg, "G5_inline_cache_reg used in assemble_ic_buffer_code()");
2690 assert(G5_ic_reg == G5_megamorphic_method, "G5_megamorphic_method used in megamorphic call stub");
2691 __ ic_call((address)$meth$$method, /*emit_delay=*/true, resolved_method_index(cbuf));
2692 } else {
2693 assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
2694 // Just go thru the vtable
2695 // get receiver klass (receiver already checked for non-null)
2696 // If we end up going thru a c2i adapter interpreter expects method in G5
2697 int off = __ offset();
2698 __ load_klass(O0, G3_scratch);
2699 int klass_load_size;
2700 if (UseCompressedClassPointers) {
2701 assert(Universe::heap() != NULL, "java heap should be initialized");
2702 klass_load_size = MacroAssembler::instr_size_for_decode_klass_not_null() + 1*BytesPerInstWord;
2703 } else {
2704 klass_load_size = 1*BytesPerInstWord;
2705 }
2706 int entry_offset = in_bytes(Klass::vtable_start_offset()) + vtable_index*vtableEntry::size_in_bytes();
2707 int v_off = entry_offset + vtableEntry::method_offset_in_bytes();
2708 if (Assembler::is_simm13(v_off)) {
2709 __ ld_ptr(G3, v_off, G5_method);
2710 } else {
2711 // Generate 2 instructions
2712 __ Assembler::sethi(v_off & ~0x3ff, G5_method);
2713 __ or3(G5_method, v_off & 0x3ff, G5_method);
2714 // ld_ptr, set_hi, set
2715 assert(__ offset() - off == klass_load_size + 2*BytesPerInstWord,
2716 "Unexpected instruction size(s)");
2717 __ ld_ptr(G3, G5_method, G5_method);
2718 }
2719 // NOTE: for vtable dispatches, the vtable entry will never be null.
2720 // However it may very well end up in handle_wrong_method if the
2721 // method is abstract for the particular class.
2722 __ ld_ptr(G5_method, in_bytes(Method::from_compiled_offset()), G3_scratch);
2723 // jump to target (either compiled code or c2iadapter)
2724 __ jmpl(G3_scratch, G0, O7);
2725 __ delayed()->nop();
2726 }
2727 %}
2728
2729 enc_class Java_Compiled_Call (method meth) %{ // JAVA COMPILED CALL
2730 MacroAssembler _masm(&cbuf);
2731
2732 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode());
2733 Register temp_reg = G3; // caller must kill G3! We cannot reuse G5_ic_reg here because
2734 // we might be calling a C2I adapter which needs it.
2735
2736 assert(temp_reg != G5_ic_reg, "conflicting registers");
2737 // Load nmethod
2738 __ ld_ptr(G5_ic_reg, in_bytes(Method::from_compiled_offset()), temp_reg);
2739
2740 // CALL to compiled java, indirect the contents of G3
2741 __ set_inst_mark();
2742 __ callr(temp_reg, G0);
2743 __ delayed()->nop();
2744 %}
2745
2746 enc_class idiv_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst) %{
2747 MacroAssembler _masm(&cbuf);
2748 Register Rdividend = reg_to_register_object($src1$$reg);
2749 Register Rdivisor = reg_to_register_object($src2$$reg);
2750 Register Rresult = reg_to_register_object($dst$$reg);
2751
2752 __ sra(Rdivisor, 0, Rdivisor);
2753 __ sra(Rdividend, 0, Rdividend);
2754 __ sdivx(Rdividend, Rdivisor, Rresult);
2755 %}
2756
2757 enc_class idiv_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst) %{
2758 MacroAssembler _masm(&cbuf);
2759
2760 Register Rdividend = reg_to_register_object($src1$$reg);
2761 int divisor = $imm$$constant;
2762 Register Rresult = reg_to_register_object($dst$$reg);
2763
2764 __ sra(Rdividend, 0, Rdividend);
2765 __ sdivx(Rdividend, divisor, Rresult);
2766 %}
2767
2768 enc_class enc_mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2) %{
2769 MacroAssembler _masm(&cbuf);
2770 Register Rsrc1 = reg_to_register_object($src1$$reg);
2771 Register Rsrc2 = reg_to_register_object($src2$$reg);
2772 Register Rdst = reg_to_register_object($dst$$reg);
2773
2774 __ sra( Rsrc1, 0, Rsrc1 );
2775 __ sra( Rsrc2, 0, Rsrc2 );
2776 __ mulx( Rsrc1, Rsrc2, Rdst );
2777 __ srlx( Rdst, 32, Rdst );
2778 %}
2779
2780 enc_class irem_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst, o7RegL scratch) %{
2781 MacroAssembler _masm(&cbuf);
2782 Register Rdividend = reg_to_register_object($src1$$reg);
2783 Register Rdivisor = reg_to_register_object($src2$$reg);
2784 Register Rresult = reg_to_register_object($dst$$reg);
2785 Register Rscratch = reg_to_register_object($scratch$$reg);
2786
2787 assert(Rdividend != Rscratch, "");
2788 assert(Rdivisor != Rscratch, "");
2789
2790 __ sra(Rdividend, 0, Rdividend);
2791 __ sra(Rdivisor, 0, Rdivisor);
2792 __ sdivx(Rdividend, Rdivisor, Rscratch);
2793 __ mulx(Rscratch, Rdivisor, Rscratch);
2794 __ sub(Rdividend, Rscratch, Rresult);
2795 %}
2796
2797 enc_class irem_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst, o7RegL scratch) %{
2798 MacroAssembler _masm(&cbuf);
2799
2800 Register Rdividend = reg_to_register_object($src1$$reg);
2801 int divisor = $imm$$constant;
2802 Register Rresult = reg_to_register_object($dst$$reg);
2803 Register Rscratch = reg_to_register_object($scratch$$reg);
2804
2805 assert(Rdividend != Rscratch, "");
2806
2807 __ sra(Rdividend, 0, Rdividend);
2808 __ sdivx(Rdividend, divisor, Rscratch);
2809 __ mulx(Rscratch, divisor, Rscratch);
2810 __ sub(Rdividend, Rscratch, Rresult);
2811 %}
2812
2813 enc_class fabss (sflt_reg dst, sflt_reg src) %{
2814 MacroAssembler _masm(&cbuf);
2815
2816 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg);
2817 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg);
2818
2819 __ fabs(FloatRegisterImpl::S, Fsrc, Fdst);
2820 %}
2821
2822 enc_class fabsd (dflt_reg dst, dflt_reg src) %{
2823 MacroAssembler _masm(&cbuf);
2824
2825 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2826 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2827
2828 __ fabs(FloatRegisterImpl::D, Fsrc, Fdst);
2829 %}
2830
2831 enc_class fnegd (dflt_reg dst, dflt_reg src) %{
2832 MacroAssembler _masm(&cbuf);
2833
2834 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2835 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2836
2837 __ fneg(FloatRegisterImpl::D, Fsrc, Fdst);
2838 %}
2839
2840 enc_class fsqrts (sflt_reg dst, sflt_reg src) %{
2841 MacroAssembler _masm(&cbuf);
2842
2843 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg);
2844 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg);
2845
2846 __ fsqrt(FloatRegisterImpl::S, Fsrc, Fdst);
2847 %}
2848
2849 enc_class fsqrtd (dflt_reg dst, dflt_reg src) %{
2850 MacroAssembler _masm(&cbuf);
2851
2852 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2853 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2854
2855 __ fsqrt(FloatRegisterImpl::D, Fsrc, Fdst);
2856 %}
2857
2858 enc_class fmovs (dflt_reg dst, dflt_reg src) %{
2859 MacroAssembler _masm(&cbuf);
2860
2861 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg);
2862 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg);
2863
2864 __ fmov(FloatRegisterImpl::S, Fsrc, Fdst);
2865 %}
2866
2867 enc_class fmovd (dflt_reg dst, dflt_reg src) %{
2868 MacroAssembler _masm(&cbuf);
2869
2870 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2871 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2872
2873 __ fmov(FloatRegisterImpl::D, Fsrc, Fdst);
2874 %}
2875
2876 enc_class Fast_Lock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{
2877 MacroAssembler _masm(&cbuf);
2878
2879 Register Roop = reg_to_register_object($oop$$reg);
2880 Register Rbox = reg_to_register_object($box$$reg);
2881 Register Rscratch = reg_to_register_object($scratch$$reg);
2882 Register Rmark = reg_to_register_object($scratch2$$reg);
2883
2884 assert(Roop != Rscratch, "");
2885 assert(Roop != Rmark, "");
2886 assert(Rbox != Rscratch, "");
2887 assert(Rbox != Rmark, "");
2888
2889 __ compiler_lock_object(Roop, Rmark, Rbox, Rscratch, _counters, UseBiasedLocking && !UseOptoBiasInlining);
2890 %}
2891
2892 enc_class Fast_Unlock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{
2893 MacroAssembler _masm(&cbuf);
2894
2895 Register Roop = reg_to_register_object($oop$$reg);
2896 Register Rbox = reg_to_register_object($box$$reg);
2897 Register Rscratch = reg_to_register_object($scratch$$reg);
2898 Register Rmark = reg_to_register_object($scratch2$$reg);
2899
2900 assert(Roop != Rscratch, "");
2901 assert(Roop != Rmark, "");
2902 assert(Rbox != Rscratch, "");
2903 assert(Rbox != Rmark, "");
2904
2905 __ compiler_unlock_object(Roop, Rmark, Rbox, Rscratch, UseBiasedLocking && !UseOptoBiasInlining);
2906 %}
2907
2908 enc_class enc_cas( iRegP mem, iRegP old, iRegP new ) %{
2909 MacroAssembler _masm(&cbuf);
2910 Register Rmem = reg_to_register_object($mem$$reg);
2911 Register Rold = reg_to_register_object($old$$reg);
2912 Register Rnew = reg_to_register_object($new$$reg);
2913
2914 __ cas_ptr(Rmem, Rold, Rnew); // Swap(*Rmem,Rnew) if *Rmem == Rold
2915 __ cmp( Rold, Rnew );
2916 %}
2917
2918 enc_class enc_casx( iRegP mem, iRegL old, iRegL new) %{
2919 Register Rmem = reg_to_register_object($mem$$reg);
2920 Register Rold = reg_to_register_object($old$$reg);
2921 Register Rnew = reg_to_register_object($new$$reg);
2922
2923 MacroAssembler _masm(&cbuf);
2924 __ mov(Rnew, O7);
2925 __ casx(Rmem, Rold, O7);
2926 __ cmp( Rold, O7 );
2927 %}
2928
2929 // raw int cas, used for compareAndSwap
2930 enc_class enc_casi( iRegP mem, iRegL old, iRegL new) %{
2931 Register Rmem = reg_to_register_object($mem$$reg);
2932 Register Rold = reg_to_register_object($old$$reg);
2933 Register Rnew = reg_to_register_object($new$$reg);
2934
2935 MacroAssembler _masm(&cbuf);
2936 __ mov(Rnew, O7);
2937 __ cas(Rmem, Rold, O7);
2938 __ cmp( Rold, O7 );
2939 %}
2940
2941 // raw int cas without using tmp register for compareAndExchange
2942 enc_class enc_casi_exch( iRegP mem, iRegL old, iRegL new) %{
2943 Register Rmem = reg_to_register_object($mem$$reg);
2944 Register Rold = reg_to_register_object($old$$reg);
2945 Register Rnew = reg_to_register_object($new$$reg);
2946
2947 MacroAssembler _masm(&cbuf);
2948 __ cas(Rmem, Rold, Rnew);
2949 %}
2950
2951 // 64-bit cas without using tmp register for compareAndExchange
2952 enc_class enc_casx_exch( iRegP mem, iRegL old, iRegL new) %{
2953 Register Rmem = reg_to_register_object($mem$$reg);
2954 Register Rold = reg_to_register_object($old$$reg);
2955 Register Rnew = reg_to_register_object($new$$reg);
2956
2957 MacroAssembler _masm(&cbuf);
2958 __ casx(Rmem, Rold, Rnew);
2959 %}
2960
2961 enc_class enc_lflags_ne_to_boolean( iRegI res ) %{
2962 Register Rres = reg_to_register_object($res$$reg);
2963
2964 MacroAssembler _masm(&cbuf);
2965 __ mov(1, Rres);
2966 __ movcc( Assembler::notEqual, false, Assembler::xcc, G0, Rres );
2967 %}
2968
2969 enc_class enc_iflags_ne_to_boolean( iRegI res ) %{
2970 Register Rres = reg_to_register_object($res$$reg);
2971
2972 MacroAssembler _masm(&cbuf);
2973 __ mov(1, Rres);
2974 __ movcc( Assembler::notEqual, false, Assembler::icc, G0, Rres );
2975 %}
2976
2977 enc_class floating_cmp ( iRegP dst, regF src1, regF src2 ) %{
2978 MacroAssembler _masm(&cbuf);
2979 Register Rdst = reg_to_register_object($dst$$reg);
2980 FloatRegister Fsrc1 = $primary ? reg_to_SingleFloatRegister_object($src1$$reg)
2981 : reg_to_DoubleFloatRegister_object($src1$$reg);
2982 FloatRegister Fsrc2 = $primary ? reg_to_SingleFloatRegister_object($src2$$reg)
2983 : reg_to_DoubleFloatRegister_object($src2$$reg);
2984
2985 // Convert condition code fcc0 into -1,0,1; unordered reports less-than (-1)
2986 __ float_cmp( $primary, -1, Fsrc1, Fsrc2, Rdst);
2987 %}
2988
2989 enc_class enc_rethrow() %{
2990 cbuf.set_insts_mark();
2991 Register temp_reg = G3;
2992 AddressLiteral rethrow_stub(OptoRuntime::rethrow_stub());
2993 assert(temp_reg != reg_to_register_object(R_I0_num), "temp must not break oop_reg");
2994 MacroAssembler _masm(&cbuf);
2995 #ifdef ASSERT
2996 __ save_frame(0);
2997 AddressLiteral last_rethrow_addrlit(&last_rethrow);
2998 __ sethi(last_rethrow_addrlit, L1);
2999 Address addr(L1, last_rethrow_addrlit.low10());
3000 __ rdpc(L2);
3001 __ inc(L2, 3 * BytesPerInstWord); // skip this & 2 more insns to point at jump_to
3002 __ st_ptr(L2, addr);
3003 __ restore();
3004 #endif
3005 __ JUMP(rethrow_stub, temp_reg, 0); // sethi;jmp
3006 __ delayed()->nop();
3007 %}
3008
3009 enc_class emit_mem_nop() %{
3010 // Generates the instruction LDUXA [o6,g0],#0x82,g0
3011 cbuf.insts()->emit_int32((unsigned int) 0xc0839040);
3012 %}
3013
3014 enc_class emit_fadd_nop() %{
3015 // Generates the instruction FMOVS f31,f31
3016 cbuf.insts()->emit_int32((unsigned int) 0xbfa0003f);
3017 %}
3018
3019 enc_class emit_br_nop() %{
3020 // Generates the instruction BPN,PN .
3021 cbuf.insts()->emit_int32((unsigned int) 0x00400000);
3022 %}
3023
3024 enc_class enc_membar_acquire %{
3025 MacroAssembler _masm(&cbuf);
3026 __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::LoadLoad) );
3027 %}
3028
3029 enc_class enc_membar_release %{
3030 MacroAssembler _masm(&cbuf);
3031 __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::StoreStore) );
3032 %}
3033
3034 enc_class enc_membar_volatile %{
3035 MacroAssembler _masm(&cbuf);
3036 __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad) );
3037 %}
3038
3039 %}
3040
3041 //----------FRAME--------------------------------------------------------------
3042 // Definition of frame structure and management information.
3043 //
3044 // S T A C K L A Y O U T Allocators stack-slot number
3045 // | (to get allocators register number
3046 // G Owned by | | v add VMRegImpl::stack0)
3047 // r CALLER | |
3048 // o | +--------+ pad to even-align allocators stack-slot
3049 // w V | pad0 | numbers; owned by CALLER
3050 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned
3051 // h ^ | in | 5
3052 // | | args | 4 Holes in incoming args owned by SELF
3053 // | | | | 3
3054 // | | +--------+
3055 // V | | old out| Empty on Intel, window on Sparc
3056 // | old |preserve| Must be even aligned.
3057 // | SP-+--------+----> Matcher::_old_SP, 8 (or 16 in LP64)-byte aligned
3058 // | | in | 3 area for Intel ret address
3059 // Owned by |preserve| Empty on Sparc.
3060 // SELF +--------+
3061 // | | pad2 | 2 pad to align old SP
3062 // | +--------+ 1
3063 // | | locks | 0
3064 // | +--------+----> VMRegImpl::stack0, 8 (or 16 in LP64)-byte aligned
3065 // | | pad1 | 11 pad to align new SP
3066 // | +--------+
3067 // | | | 10
3068 // | | spills | 9 spills
3069 // V | | 8 (pad0 slot for callee)
3070 // -----------+--------+----> Matcher::_out_arg_limit, unaligned
3071 // ^ | out | 7
3072 // | | args | 6 Holes in outgoing args owned by CALLEE
3073 // Owned by +--------+
3074 // CALLEE | new out| 6 Empty on Intel, window on Sparc
3075 // | new |preserve| Must be even-aligned.
3076 // | SP-+--------+----> Matcher::_new_SP, even aligned
3077 // | | |
3078 //
3079 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is
3080 // known from SELF's arguments and the Java calling convention.
3081 // Region 6-7 is determined per call site.
3082 // Note 2: If the calling convention leaves holes in the incoming argument
3083 // area, those holes are owned by SELF. Holes in the outgoing area
3084 // are owned by the CALLEE. Holes should not be nessecary in the
3085 // incoming area, as the Java calling convention is completely under
3086 // the control of the AD file. Doubles can be sorted and packed to
3087 // avoid holes. Holes in the outgoing arguments may be necessary for
3088 // varargs C calling conventions.
3089 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is
3090 // even aligned with pad0 as needed.
3091 // Region 6 is even aligned. Region 6-7 is NOT even aligned;
3092 // region 6-11 is even aligned; it may be padded out more so that
3093 // the region from SP to FP meets the minimum stack alignment.
3094
3095 frame %{
3096 // What direction does stack grow in (assumed to be same for native & Java)
3097 stack_direction(TOWARDS_LOW);
3098
3099 // These two registers define part of the calling convention
3100 // between compiled code and the interpreter.
3101 inline_cache_reg(R_G5); // Inline Cache Register or Method* for I2C
3102 interpreter_method_oop_reg(R_G5); // Method Oop Register when calling interpreter
3103
3104 // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset]
3105 cisc_spilling_operand_name(indOffset);
3106
3107 // Number of stack slots consumed by a Monitor enter
3108 #ifdef _LP64
3109 sync_stack_slots(2);
3110 #else
3111 sync_stack_slots(1);
3112 #endif
3113
3114 // Compiled code's Frame Pointer
3115 frame_pointer(R_SP);
3116
3117 // Stack alignment requirement
3118 stack_alignment(StackAlignmentInBytes);
3119 // LP64: Alignment size in bytes (128-bit -> 16 bytes)
3120 // !LP64: Alignment size in bytes (64-bit -> 8 bytes)
3121
3122 // Number of stack slots between incoming argument block and the start of
3123 // a new frame. The PROLOG must add this many slots to the stack. The
3124 // EPILOG must remove this many slots.
3125 in_preserve_stack_slots(0);
3126
3127 // Number of outgoing stack slots killed above the out_preserve_stack_slots
3128 // for calls to C. Supports the var-args backing area for register parms.
3129 // ADLC doesn't support parsing expressions, so I folded the math by hand.
3130 #ifdef _LP64
3131 // (callee_register_argument_save_area_words (6) + callee_aggregate_return_pointer_words (0)) * 2-stack-slots-per-word
3132 varargs_C_out_slots_killed(12);
3133 #else
3134 // (callee_register_argument_save_area_words (6) + callee_aggregate_return_pointer_words (1)) * 1-stack-slots-per-word
3135 varargs_C_out_slots_killed( 7);
3136 #endif
3137
3138 // The after-PROLOG location of the return address. Location of
3139 // return address specifies a type (REG or STACK) and a number
3140 // representing the register number (i.e. - use a register name) or
3141 // stack slot.
3142 return_addr(REG R_I7); // Ret Addr is in register I7
3143
3144 // Body of function which returns an OptoRegs array locating
3145 // arguments either in registers or in stack slots for calling
3146 // java
3147 calling_convention %{
3148 (void) SharedRuntime::java_calling_convention(sig_bt, regs, length, is_outgoing);
3149
3150 %}
3151
3152 // Body of function which returns an OptoRegs array locating
3153 // arguments either in registers or in stack slots for calling
3154 // C.
3155 c_calling_convention %{
3156 // This is obviously always outgoing
3157 (void) SharedRuntime::c_calling_convention(sig_bt, regs, /*regs2=*/NULL, length);
3158 %}
3159
3160 // Location of native (C/C++) and interpreter return values. This is specified to
3161 // be the same as Java. In the 32-bit VM, long values are actually returned from
3162 // native calls in O0:O1 and returned to the interpreter in I0:I1. The copying
3163 // to and from the register pairs is done by the appropriate call and epilog
3164 // opcodes. This simplifies the register allocator.
3165 c_return_value %{
3166 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
3167 #ifdef _LP64
3168 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_O0_num };
3169 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num, OptoReg::Bad, R_F1_num, R_O0H_num};
3170 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_I0_num };
3171 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num, OptoReg::Bad, R_F1_num, R_I0H_num};
3172 #else // !_LP64
3173 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_G1_num };
3174 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num };
3175 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_G1_num };
3176 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num };
3177 #endif
3178 return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg],
3179 (is_outgoing?lo_out:lo_in)[ideal_reg] );
3180 %}
3181
3182 // Location of compiled Java return values. Same as C
3183 return_value %{
3184 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
3185 #ifdef _LP64
3186 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_O0_num };
3187 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num, OptoReg::Bad, R_F1_num, R_O0H_num};
3188 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_I0_num };
3189 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num, OptoReg::Bad, R_F1_num, R_I0H_num};
3190 #else // !_LP64
3191 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_G1_num };
3192 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num};
3193 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_G1_num };
3194 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num};
3195 #endif
3196 return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg],
3197 (is_outgoing?lo_out:lo_in)[ideal_reg] );
3198 %}
3199
3200 %}
3201
3202
3203 //----------ATTRIBUTES---------------------------------------------------------
3204 //----------Operand Attributes-------------------------------------------------
3205 op_attrib op_cost(1); // Required cost attribute
3206
3207 //----------Instruction Attributes---------------------------------------------
3208 ins_attrib ins_cost(DEFAULT_COST); // Required cost attribute
3209 ins_attrib ins_size(32); // Required size attribute (in bits)
3210
3211 // avoid_back_to_back attribute is an expression that must return
3212 // one of the following values defined in MachNode:
3213 // AVOID_NONE - instruction can be placed anywhere
3214 // AVOID_BEFORE - instruction cannot be placed after an
3215 // instruction with MachNode::AVOID_AFTER
3216 // AVOID_AFTER - the next instruction cannot be the one
3217 // with MachNode::AVOID_BEFORE
3218 // AVOID_BEFORE_AND_AFTER - BEFORE and AFTER attributes at
3219 // the same time
3220 ins_attrib ins_avoid_back_to_back(MachNode::AVOID_NONE);
3221
3222 ins_attrib ins_short_branch(0); // Required flag: is this instruction a
3223 // non-matching short branch variant of some
3224 // long branch?
3225
3226 //----------OPERANDS-----------------------------------------------------------
3227 // Operand definitions must precede instruction definitions for correct parsing
3228 // in the ADLC because operands constitute user defined types which are used in
3229 // instruction definitions.
3230
3231 //----------Simple Operands----------------------------------------------------
3232 // Immediate Operands
3233 // Integer Immediate: 32-bit
3234 operand immI() %{
3235 match(ConI);
3236
3237 op_cost(0);
3238 // formats are generated automatically for constants and base registers
3239 format %{ %}
3240 interface(CONST_INTER);
3241 %}
3242
3243 // Integer Immediate: 0-bit
3244 operand immI0() %{
3245 predicate(n->get_int() == 0);
3246 match(ConI);
3247 op_cost(0);
3248
3249 format %{ %}
3250 interface(CONST_INTER);
3251 %}
3252
3253 // Integer Immediate: 5-bit
3254 operand immI5() %{
3255 predicate(Assembler::is_simm5(n->get_int()));
3256 match(ConI);
3257 op_cost(0);
3258 format %{ %}
3259 interface(CONST_INTER);
3260 %}
3261
3262 // Integer Immediate: 8-bit
3263 operand immI8() %{
3264 predicate(Assembler::is_simm8(n->get_int()));
3265 match(ConI);
3266 op_cost(0);
3267 format %{ %}
3268 interface(CONST_INTER);
3269 %}
3270
3271 // Integer Immediate: the value 10
3272 operand immI10() %{
3273 predicate(n->get_int() == 10);
3274 match(ConI);
3275 op_cost(0);
3276
3277 format %{ %}
3278 interface(CONST_INTER);
3279 %}
3280
3281 // Integer Immediate: 11-bit
3282 operand immI11() %{
3283 predicate(Assembler::is_simm11(n->get_int()));
3284 match(ConI);
3285 op_cost(0);
3286 format %{ %}
3287 interface(CONST_INTER);
3288 %}
3289
3290 // Integer Immediate: 13-bit
3291 operand immI13() %{
3292 predicate(Assembler::is_simm13(n->get_int()));
3293 match(ConI);
3294 op_cost(0);
3295
3296 format %{ %}
3297 interface(CONST_INTER);
3298 %}
3299
3300 // Integer Immediate: 13-bit minus 7
3301 operand immI13m7() %{
3302 predicate((-4096 < n->get_int()) && ((n->get_int() + 7) <= 4095));
3303 match(ConI);
3304 op_cost(0);
3305
3306 format %{ %}
3307 interface(CONST_INTER);
3308 %}
3309
3310 // Integer Immediate: 16-bit
3311 operand immI16() %{
3312 predicate(Assembler::is_simm16(n->get_int()));
3313 match(ConI);
3314 op_cost(0);
3315 format %{ %}
3316 interface(CONST_INTER);
3317 %}
3318
3319 // Integer Immediate: the values 1-31
3320 operand immI_1_31() %{
3321 predicate(n->get_int() >= 1 && n->get_int() <= 31);
3322 match(ConI);
3323 op_cost(0);
3324
3325 format %{ %}
3326 interface(CONST_INTER);
3327 %}
3328
3329 // Integer Immediate: the values 32-63
3330 operand immI_32_63() %{
3331 predicate(n->get_int() >= 32 && n->get_int() <= 63);
3332 match(ConI);
3333 op_cost(0);
3334
3335 format %{ %}
3336 interface(CONST_INTER);
3337 %}
3338
3339 // Immediates for special shifts (sign extend)
3340
3341 // Integer Immediate: the value 16
3342 operand immI_16() %{
3343 predicate(n->get_int() == 16);
3344 match(ConI);
3345 op_cost(0);
3346
3347 format %{ %}
3348 interface(CONST_INTER);
3349 %}
3350
3351 // Integer Immediate: the value 24
3352 operand immI_24() %{
3353 predicate(n->get_int() == 24);
3354 match(ConI);
3355 op_cost(0);
3356
3357 format %{ %}
3358 interface(CONST_INTER);
3359 %}
3360 // Integer Immediate: the value 255
3361 operand immI_255() %{
3362 predicate( n->get_int() == 255 );
3363 match(ConI);
3364 op_cost(0);
3365
3366 format %{ %}
3367 interface(CONST_INTER);
3368 %}
3369
3370 // Integer Immediate: the value 65535
3371 operand immI_65535() %{
3372 predicate(n->get_int() == 65535);
3373 match(ConI);
3374 op_cost(0);
3375
3376 format %{ %}
3377 interface(CONST_INTER);
3378 %}
3379
3380 // Integer Immediate: the values 0-31
3381 operand immU5() %{
3382 predicate(n->get_int() >= 0 && n->get_int() <= 31);
3383 match(ConI);
3384 op_cost(0);
3385
3386 format %{ %}
3387 interface(CONST_INTER);
3388 %}
3389
3390 // Integer Immediate: 6-bit
3391 operand immU6() %{
3392 predicate(n->get_int() >= 0 && n->get_int() <= 63);
3393 match(ConI);
3394 op_cost(0);
3395 format %{ %}
3396 interface(CONST_INTER);
3397 %}
3398
3399 // Unsigned Integer Immediate: 12-bit (non-negative that fits in simm13)
3400 operand immU12() %{
3401 predicate((0 <= n->get_int()) && Assembler::is_simm13(n->get_int()));
3402 match(ConI);
3403 op_cost(0);
3404
3405 format %{ %}
3406 interface(CONST_INTER);
3407 %}
3408
3409 // Integer Immediate non-negative
3410 operand immU31()
3411 %{
3412 predicate(n->get_int() >= 0);
3413 match(ConI);
3414
3415 op_cost(0);
3416 format %{ %}
3417 interface(CONST_INTER);
3418 %}
3419
3420 // Long Immediate: the value FF
3421 operand immL_FF() %{
3422 predicate( n->get_long() == 0xFFL );
3423 match(ConL);
3424 op_cost(0);
3425
3426 format %{ %}
3427 interface(CONST_INTER);
3428 %}
3429
3430 // Long Immediate: the value FFFF
3431 operand immL_FFFF() %{
3432 predicate( n->get_long() == 0xFFFFL );
3433 match(ConL);
3434 op_cost(0);
3435
3436 format %{ %}
3437 interface(CONST_INTER);
3438 %}
3439
3440 // Pointer Immediate: 32 or 64-bit
3441 operand immP() %{
3442 match(ConP);
3443
3444 op_cost(5);
3445 // formats are generated automatically for constants and base registers
3446 format %{ %}
3447 interface(CONST_INTER);
3448 %}
3449
3450 #ifdef _LP64
3451 // Pointer Immediate: 64-bit
3452 operand immP_set() %{
3453 predicate(!VM_Version::is_niagara_plus());
3454 match(ConP);
3455
3456 op_cost(5);
3457 // formats are generated automatically for constants and base registers
3458 format %{ %}
3459 interface(CONST_INTER);
3460 %}
3461
3462 // Pointer Immediate: 64-bit
3463 // From Niagara2 processors on a load should be better than materializing.
3464 operand immP_load() %{
3465 predicate(VM_Version::is_niagara_plus() && (n->bottom_type()->isa_oop_ptr() || (MacroAssembler::insts_for_set(n->get_ptr()) > 3)));
3466 match(ConP);
3467
3468 op_cost(5);
3469 // formats are generated automatically for constants and base registers
3470 format %{ %}
3471 interface(CONST_INTER);
3472 %}
3473
3474 // Pointer Immediate: 64-bit
3475 operand immP_no_oop_cheap() %{
3476 predicate(VM_Version::is_niagara_plus() && !n->bottom_type()->isa_oop_ptr() && (MacroAssembler::insts_for_set(n->get_ptr()) <= 3));
3477 match(ConP);
3478
3479 op_cost(5);
3480 // formats are generated automatically for constants and base registers
3481 format %{ %}
3482 interface(CONST_INTER);
3483 %}
3484 #endif
3485
3486 operand immP13() %{
3487 predicate((-4096 < n->get_ptr()) && (n->get_ptr() <= 4095));
3488 match(ConP);
3489 op_cost(0);
3490
3491 format %{ %}
3492 interface(CONST_INTER);
3493 %}
3494
3495 operand immP0() %{
3496 predicate(n->get_ptr() == 0);
3497 match(ConP);
3498 op_cost(0);
3499
3500 format %{ %}
3501 interface(CONST_INTER);
3502 %}
3503
3504 operand immP_poll() %{
3505 predicate(n->get_ptr() != 0 && n->get_ptr() == (intptr_t)os::get_polling_page());
3506 match(ConP);
3507
3508 // formats are generated automatically for constants and base registers
3509 format %{ %}
3510 interface(CONST_INTER);
3511 %}
3512
3513 // Pointer Immediate
3514 operand immN()
3515 %{
3516 match(ConN);
3517
3518 op_cost(10);
3519 format %{ %}
3520 interface(CONST_INTER);
3521 %}
3522
3523 operand immNKlass()
3524 %{
3525 match(ConNKlass);
3526
3527 op_cost(10);
3528 format %{ %}
3529 interface(CONST_INTER);
3530 %}
3531
3532 // NULL Pointer Immediate
3533 operand immN0()
3534 %{
3535 predicate(n->get_narrowcon() == 0);
3536 match(ConN);
3537
3538 op_cost(0);
3539 format %{ %}
3540 interface(CONST_INTER);
3541 %}
3542
3543 operand immL() %{
3544 match(ConL);
3545 op_cost(40);
3546 // formats are generated automatically for constants and base registers
3547 format %{ %}
3548 interface(CONST_INTER);
3549 %}
3550
3551 operand immL0() %{
3552 predicate(n->get_long() == 0L);
3553 match(ConL);
3554 op_cost(0);
3555 // formats are generated automatically for constants and base registers
3556 format %{ %}
3557 interface(CONST_INTER);
3558 %}
3559
3560 // Integer Immediate: 5-bit
3561 operand immL5() %{
3562 predicate(n->get_long() == (int)n->get_long() && Assembler::is_simm5((int)n->get_long()));
3563 match(ConL);
3564 op_cost(0);
3565 format %{ %}
3566 interface(CONST_INTER);
3567 %}
3568
3569 // Long Immediate: 13-bit
3570 operand immL13() %{
3571 predicate((-4096L < n->get_long()) && (n->get_long() <= 4095L));
3572 match(ConL);
3573 op_cost(0);
3574
3575 format %{ %}
3576 interface(CONST_INTER);
3577 %}
3578
3579 // Long Immediate: 13-bit minus 7
3580 operand immL13m7() %{
3581 predicate((-4096L < n->get_long()) && ((n->get_long() + 7L) <= 4095L));
3582 match(ConL);
3583 op_cost(0);
3584
3585 format %{ %}
3586 interface(CONST_INTER);
3587 %}
3588
3589 // Long Immediate: low 32-bit mask
3590 operand immL_32bits() %{
3591 predicate(n->get_long() == 0xFFFFFFFFL);
3592 match(ConL);
3593 op_cost(0);
3594
3595 format %{ %}
3596 interface(CONST_INTER);
3597 %}
3598
3599 // Long Immediate: cheap (materialize in <= 3 instructions)
3600 operand immL_cheap() %{
3601 predicate(!VM_Version::is_niagara_plus() || MacroAssembler::insts_for_set64(n->get_long()) <= 3);
3602 match(ConL);
3603 op_cost(0);
3604
3605 format %{ %}
3606 interface(CONST_INTER);
3607 %}
3608
3609 // Long Immediate: expensive (materialize in > 3 instructions)
3610 operand immL_expensive() %{
3611 predicate(VM_Version::is_niagara_plus() && MacroAssembler::insts_for_set64(n->get_long()) > 3);
3612 match(ConL);
3613 op_cost(0);
3614
3615 format %{ %}
3616 interface(CONST_INTER);
3617 %}
3618
3619 // Double Immediate
3620 operand immD() %{
3621 match(ConD);
3622
3623 op_cost(40);
3624 format %{ %}
3625 interface(CONST_INTER);
3626 %}
3627
3628 // Double Immediate: +0.0d
3629 operand immD0() %{
3630 predicate(jlong_cast(n->getd()) == 0);
3631 match(ConD);
3632
3633 op_cost(0);
3634 format %{ %}
3635 interface(CONST_INTER);
3636 %}
3637
3638 // Float Immediate
3639 operand immF() %{
3640 match(ConF);
3641
3642 op_cost(20);
3643 format %{ %}
3644 interface(CONST_INTER);
3645 %}
3646
3647 // Float Immediate: +0.0f
3648 operand immF0() %{
3649 predicate(jint_cast(n->getf()) == 0);
3650 match(ConF);
3651
3652 op_cost(0);
3653 format %{ %}
3654 interface(CONST_INTER);
3655 %}
3656
3657 // Integer Register Operands
3658 // Integer Register
3659 operand iRegI() %{
3660 constraint(ALLOC_IN_RC(int_reg));
3661 match(RegI);
3662
3663 match(notemp_iRegI);
3664 match(g1RegI);
3665 match(o0RegI);
3666 match(iRegIsafe);
3667
3668 format %{ %}
3669 interface(REG_INTER);
3670 %}
3671
3672 operand notemp_iRegI() %{
3673 constraint(ALLOC_IN_RC(notemp_int_reg));
3674 match(RegI);
3675
3676 match(o0RegI);
3677
3678 format %{ %}
3679 interface(REG_INTER);
3680 %}
3681
3682 operand o0RegI() %{
3683 constraint(ALLOC_IN_RC(o0_regI));
3684 match(iRegI);
3685
3686 format %{ %}
3687 interface(REG_INTER);
3688 %}
3689
3690 // Pointer Register
3691 operand iRegP() %{
3692 constraint(ALLOC_IN_RC(ptr_reg));
3693 match(RegP);
3694
3695 match(lock_ptr_RegP);
3696 match(g1RegP);
3697 match(g2RegP);
3698 match(g3RegP);
3699 match(g4RegP);
3700 match(i0RegP);
3701 match(o0RegP);
3702 match(o1RegP);
3703 match(l7RegP);
3704
3705 format %{ %}
3706 interface(REG_INTER);
3707 %}
3708
3709 operand sp_ptr_RegP() %{
3710 constraint(ALLOC_IN_RC(sp_ptr_reg));
3711 match(RegP);
3712 match(iRegP);
3713
3714 format %{ %}
3715 interface(REG_INTER);
3716 %}
3717
3718 operand lock_ptr_RegP() %{
3719 constraint(ALLOC_IN_RC(lock_ptr_reg));
3720 match(RegP);
3721 match(i0RegP);
3722 match(o0RegP);
3723 match(o1RegP);
3724 match(l7RegP);
3725
3726 format %{ %}
3727 interface(REG_INTER);
3728 %}
3729
3730 operand g1RegP() %{
3731 constraint(ALLOC_IN_RC(g1_regP));
3732 match(iRegP);
3733
3734 format %{ %}
3735 interface(REG_INTER);
3736 %}
3737
3738 operand g2RegP() %{
3739 constraint(ALLOC_IN_RC(g2_regP));
3740 match(iRegP);
3741
3742 format %{ %}
3743 interface(REG_INTER);
3744 %}
3745
3746 operand g3RegP() %{
3747 constraint(ALLOC_IN_RC(g3_regP));
3748 match(iRegP);
3749
3750 format %{ %}
3751 interface(REG_INTER);
3752 %}
3753
3754 operand g1RegI() %{
3755 constraint(ALLOC_IN_RC(g1_regI));
3756 match(iRegI);
3757
3758 format %{ %}
3759 interface(REG_INTER);
3760 %}
3761
3762 operand g3RegI() %{
3763 constraint(ALLOC_IN_RC(g3_regI));
3764 match(iRegI);
3765
3766 format %{ %}
3767 interface(REG_INTER);
3768 %}
3769
3770 operand g4RegI() %{
3771 constraint(ALLOC_IN_RC(g4_regI));
3772 match(iRegI);
3773
3774 format %{ %}
3775 interface(REG_INTER);
3776 %}
3777
3778 operand g4RegP() %{
3779 constraint(ALLOC_IN_RC(g4_regP));
3780 match(iRegP);
3781
3782 format %{ %}
3783 interface(REG_INTER);
3784 %}
3785
3786 operand i0RegP() %{
3787 constraint(ALLOC_IN_RC(i0_regP));
3788 match(iRegP);
3789
3790 format %{ %}
3791 interface(REG_INTER);
3792 %}
3793
3794 operand o0RegP() %{
3795 constraint(ALLOC_IN_RC(o0_regP));
3796 match(iRegP);
3797
3798 format %{ %}
3799 interface(REG_INTER);
3800 %}
3801
3802 operand o1RegP() %{
3803 constraint(ALLOC_IN_RC(o1_regP));
3804 match(iRegP);
3805
3806 format %{ %}
3807 interface(REG_INTER);
3808 %}
3809
3810 operand o2RegP() %{
3811 constraint(ALLOC_IN_RC(o2_regP));
3812 match(iRegP);
3813
3814 format %{ %}
3815 interface(REG_INTER);
3816 %}
3817
3818 operand o7RegP() %{
3819 constraint(ALLOC_IN_RC(o7_regP));
3820 match(iRegP);
3821
3822 format %{ %}
3823 interface(REG_INTER);
3824 %}
3825
3826 operand l7RegP() %{
3827 constraint(ALLOC_IN_RC(l7_regP));
3828 match(iRegP);
3829
3830 format %{ %}
3831 interface(REG_INTER);
3832 %}
3833
3834 operand o7RegI() %{
3835 constraint(ALLOC_IN_RC(o7_regI));
3836 match(iRegI);
3837
3838 format %{ %}
3839 interface(REG_INTER);
3840 %}
3841
3842 operand iRegN() %{
3843 constraint(ALLOC_IN_RC(int_reg));
3844 match(RegN);
3845
3846 format %{ %}
3847 interface(REG_INTER);
3848 %}
3849
3850 // Long Register
3851 operand iRegL() %{
3852 constraint(ALLOC_IN_RC(long_reg));
3853 match(RegL);
3854
3855 format %{ %}
3856 interface(REG_INTER);
3857 %}
3858
3859 operand o2RegL() %{
3860 constraint(ALLOC_IN_RC(o2_regL));
3861 match(iRegL);
3862
3863 format %{ %}
3864 interface(REG_INTER);
3865 %}
3866
3867 operand o7RegL() %{
3868 constraint(ALLOC_IN_RC(o7_regL));
3869 match(iRegL);
3870
3871 format %{ %}
3872 interface(REG_INTER);
3873 %}
3874
3875 operand g1RegL() %{
3876 constraint(ALLOC_IN_RC(g1_regL));
3877 match(iRegL);
3878
3879 format %{ %}
3880 interface(REG_INTER);
3881 %}
3882
3883 operand g3RegL() %{
3884 constraint(ALLOC_IN_RC(g3_regL));
3885 match(iRegL);
3886
3887 format %{ %}
3888 interface(REG_INTER);
3889 %}
3890
3891 // Int Register safe
3892 // This is 64bit safe
3893 operand iRegIsafe() %{
3894 constraint(ALLOC_IN_RC(long_reg));
3895
3896 match(iRegI);
3897
3898 format %{ %}
3899 interface(REG_INTER);
3900 %}
3901
3902 // Condition Code Flag Register
3903 operand flagsReg() %{
3904 constraint(ALLOC_IN_RC(int_flags));
3905 match(RegFlags);
3906
3907 format %{ "ccr" %} // both ICC and XCC
3908 interface(REG_INTER);
3909 %}
3910
3911 // Condition Code Register, unsigned comparisons.
3912 operand flagsRegU() %{
3913 constraint(ALLOC_IN_RC(int_flags));
3914 match(RegFlags);
3915
3916 format %{ "icc_U" %}
3917 interface(REG_INTER);
3918 %}
3919
3920 // Condition Code Register, pointer comparisons.
3921 operand flagsRegP() %{
3922 constraint(ALLOC_IN_RC(int_flags));
3923 match(RegFlags);
3924
3925 #ifdef _LP64
3926 format %{ "xcc_P" %}
3927 #else
3928 format %{ "icc_P" %}
3929 #endif
3930 interface(REG_INTER);
3931 %}
3932
3933 // Condition Code Register, long comparisons.
3934 operand flagsRegL() %{
3935 constraint(ALLOC_IN_RC(int_flags));
3936 match(RegFlags);
3937
3938 format %{ "xcc_L" %}
3939 interface(REG_INTER);
3940 %}
3941
3942 // Condition Code Register, floating comparisons, unordered same as "less".
3943 operand flagsRegF() %{
3944 constraint(ALLOC_IN_RC(float_flags));
3945 match(RegFlags);
3946 match(flagsRegF0);
3947
3948 format %{ %}
3949 interface(REG_INTER);
3950 %}
3951
3952 operand flagsRegF0() %{
3953 constraint(ALLOC_IN_RC(float_flag0));
3954 match(RegFlags);
3955
3956 format %{ %}
3957 interface(REG_INTER);
3958 %}
3959
3960
3961 // Condition Code Flag Register used by long compare
3962 operand flagsReg_long_LTGE() %{
3963 constraint(ALLOC_IN_RC(int_flags));
3964 match(RegFlags);
3965 format %{ "icc_LTGE" %}
3966 interface(REG_INTER);
3967 %}
3968 operand flagsReg_long_EQNE() %{
3969 constraint(ALLOC_IN_RC(int_flags));
3970 match(RegFlags);
3971 format %{ "icc_EQNE" %}
3972 interface(REG_INTER);
3973 %}
3974 operand flagsReg_long_LEGT() %{
3975 constraint(ALLOC_IN_RC(int_flags));
3976 match(RegFlags);
3977 format %{ "icc_LEGT" %}
3978 interface(REG_INTER);
3979 %}
3980
3981
3982 operand regD() %{
3983 constraint(ALLOC_IN_RC(dflt_reg));
3984 match(RegD);
3985
3986 match(regD_low);
3987
3988 format %{ %}
3989 interface(REG_INTER);
3990 %}
3991
3992 operand regF() %{
3993 constraint(ALLOC_IN_RC(sflt_reg));
3994 match(RegF);
3995
3996 format %{ %}
3997 interface(REG_INTER);
3998 %}
3999
4000 operand regD_low() %{
4001 constraint(ALLOC_IN_RC(dflt_low_reg));
4002 match(regD);
4003
4004 format %{ %}
4005 interface(REG_INTER);
4006 %}
4007
4008 // Special Registers
4009
4010 // Method Register
4011 operand inline_cache_regP(iRegP reg) %{
4012 constraint(ALLOC_IN_RC(g5_regP)); // G5=inline_cache_reg but uses 2 bits instead of 1
4013 match(reg);
4014 format %{ %}
4015 interface(REG_INTER);
4016 %}
4017
4018 operand interpreter_method_oop_regP(iRegP reg) %{
4019 constraint(ALLOC_IN_RC(g5_regP)); // G5=interpreter_method_oop_reg but uses 2 bits instead of 1
4020 match(reg);
4021 format %{ %}
4022 interface(REG_INTER);
4023 %}
4024
4025
4026 //----------Complex Operands---------------------------------------------------
4027 // Indirect Memory Reference
4028 operand indirect(sp_ptr_RegP reg) %{
4029 constraint(ALLOC_IN_RC(sp_ptr_reg));
4030 match(reg);
4031
4032 op_cost(100);
4033 format %{ "[$reg]" %}
4034 interface(MEMORY_INTER) %{
4035 base($reg);
4036 index(0x0);
4037 scale(0x0);
4038 disp(0x0);
4039 %}
4040 %}
4041
4042 // Indirect with simm13 Offset
4043 operand indOffset13(sp_ptr_RegP reg, immX13 offset) %{
4044 constraint(ALLOC_IN_RC(sp_ptr_reg));
4045 match(AddP reg offset);
4046
4047 op_cost(100);
4048 format %{ "[$reg + $offset]" %}
4049 interface(MEMORY_INTER) %{
4050 base($reg);
4051 index(0x0);
4052 scale(0x0);
4053 disp($offset);
4054 %}
4055 %}
4056
4057 // Indirect with simm13 Offset minus 7
4058 operand indOffset13m7(sp_ptr_RegP reg, immX13m7 offset) %{
4059 constraint(ALLOC_IN_RC(sp_ptr_reg));
4060 match(AddP reg offset);
4061
4062 op_cost(100);
4063 format %{ "[$reg + $offset]" %}
4064 interface(MEMORY_INTER) %{
4065 base($reg);
4066 index(0x0);
4067 scale(0x0);
4068 disp($offset);
4069 %}
4070 %}
4071
4072 // Note: Intel has a swapped version also, like this:
4073 //operand indOffsetX(iRegI reg, immP offset) %{
4074 // constraint(ALLOC_IN_RC(int_reg));
4075 // match(AddP offset reg);
4076 //
4077 // op_cost(100);
4078 // format %{ "[$reg + $offset]" %}
4079 // interface(MEMORY_INTER) %{
4080 // base($reg);
4081 // index(0x0);
4082 // scale(0x0);
4083 // disp($offset);
4084 // %}
4085 //%}
4086 //// However, it doesn't make sense for SPARC, since
4087 // we have no particularly good way to embed oops in
4088 // single instructions.
4089
4090 // Indirect with Register Index
4091 operand indIndex(iRegP addr, iRegX index) %{
4092 constraint(ALLOC_IN_RC(ptr_reg));
4093 match(AddP addr index);
4094
4095 op_cost(100);
4096 format %{ "[$addr + $index]" %}
4097 interface(MEMORY_INTER) %{
4098 base($addr);
4099 index($index);
4100 scale(0x0);
4101 disp(0x0);
4102 %}
4103 %}
4104
4105 //----------Special Memory Operands--------------------------------------------
4106 // Stack Slot Operand - This operand is used for loading and storing temporary
4107 // values on the stack where a match requires a value to
4108 // flow through memory.
4109 operand stackSlotI(sRegI reg) %{
4110 constraint(ALLOC_IN_RC(stack_slots));
4111 op_cost(100);
4112 //match(RegI);
4113 format %{ "[$reg]" %}
4114 interface(MEMORY_INTER) %{
4115 base(0xE); // R_SP
4116 index(0x0);
4117 scale(0x0);
4118 disp($reg); // Stack Offset
4119 %}
4120 %}
4121
4122 operand stackSlotP(sRegP reg) %{
4123 constraint(ALLOC_IN_RC(stack_slots));
4124 op_cost(100);
4125 //match(RegP);
4126 format %{ "[$reg]" %}
4127 interface(MEMORY_INTER) %{
4128 base(0xE); // R_SP
4129 index(0x0);
4130 scale(0x0);
4131 disp($reg); // Stack Offset
4132 %}
4133 %}
4134
4135 operand stackSlotF(sRegF reg) %{
4136 constraint(ALLOC_IN_RC(stack_slots));
4137 op_cost(100);
4138 //match(RegF);
4139 format %{ "[$reg]" %}
4140 interface(MEMORY_INTER) %{
4141 base(0xE); // R_SP
4142 index(0x0);
4143 scale(0x0);
4144 disp($reg); // Stack Offset
4145 %}
4146 %}
4147 operand stackSlotD(sRegD reg) %{
4148 constraint(ALLOC_IN_RC(stack_slots));
4149 op_cost(100);
4150 //match(RegD);
4151 format %{ "[$reg]" %}
4152 interface(MEMORY_INTER) %{
4153 base(0xE); // R_SP
4154 index(0x0);
4155 scale(0x0);
4156 disp($reg); // Stack Offset
4157 %}
4158 %}
4159 operand stackSlotL(sRegL reg) %{
4160 constraint(ALLOC_IN_RC(stack_slots));
4161 op_cost(100);
4162 //match(RegL);
4163 format %{ "[$reg]" %}
4164 interface(MEMORY_INTER) %{
4165 base(0xE); // R_SP
4166 index(0x0);
4167 scale(0x0);
4168 disp($reg); // Stack Offset
4169 %}
4170 %}
4171
4172 // Operands for expressing Control Flow
4173 // NOTE: Label is a predefined operand which should not be redefined in
4174 // the AD file. It is generically handled within the ADLC.
4175
4176 //----------Conditional Branch Operands----------------------------------------
4177 // Comparison Op - This is the operation of the comparison, and is limited to
4178 // the following set of codes:
4179 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
4180 //
4181 // Other attributes of the comparison, such as unsignedness, are specified
4182 // by the comparison instruction that sets a condition code flags register.
4183 // That result is represented by a flags operand whose subtype is appropriate
4184 // to the unsignedness (etc.) of the comparison.
4185 //
4186 // Later, the instruction which matches both the Comparison Op (a Bool) and
4187 // the flags (produced by the Cmp) specifies the coding of the comparison op
4188 // by matching a specific subtype of Bool operand below, such as cmpOpU.
4189
4190 operand cmpOp() %{
4191 match(Bool);
4192
4193 format %{ "" %}
4194 interface(COND_INTER) %{
4195 equal(0x1);
4196 not_equal(0x9);
4197 less(0x3);
4198 greater_equal(0xB);
4199 less_equal(0x2);
4200 greater(0xA);
4201 overflow(0x7);
4202 no_overflow(0xF);
4203 %}
4204 %}
4205
4206 // Comparison Op, unsigned
4207 operand cmpOpU() %{
4208 match(Bool);
4209 predicate(n->as_Bool()->_test._test != BoolTest::overflow &&
4210 n->as_Bool()->_test._test != BoolTest::no_overflow);
4211
4212 format %{ "u" %}
4213 interface(COND_INTER) %{
4214 equal(0x1);
4215 not_equal(0x9);
4216 less(0x5);
4217 greater_equal(0xD);
4218 less_equal(0x4);
4219 greater(0xC);
4220 overflow(0x7);
4221 no_overflow(0xF);
4222 %}
4223 %}
4224
4225 // Comparison Op, pointer (same as unsigned)
4226 operand cmpOpP() %{
4227 match(Bool);
4228 predicate(n->as_Bool()->_test._test != BoolTest::overflow &&
4229 n->as_Bool()->_test._test != BoolTest::no_overflow);
4230
4231 format %{ "p" %}
4232 interface(COND_INTER) %{
4233 equal(0x1);
4234 not_equal(0x9);
4235 less(0x5);
4236 greater_equal(0xD);
4237 less_equal(0x4);
4238 greater(0xC);
4239 overflow(0x7);
4240 no_overflow(0xF);
4241 %}
4242 %}
4243
4244 // Comparison Op, branch-register encoding
4245 operand cmpOp_reg() %{
4246 match(Bool);
4247 predicate(n->as_Bool()->_test._test != BoolTest::overflow &&
4248 n->as_Bool()->_test._test != BoolTest::no_overflow);
4249
4250 format %{ "" %}
4251 interface(COND_INTER) %{
4252 equal (0x1);
4253 not_equal (0x5);
4254 less (0x3);
4255 greater_equal(0x7);
4256 less_equal (0x2);
4257 greater (0x6);
4258 overflow(0x7); // not supported
4259 no_overflow(0xF); // not supported
4260 %}
4261 %}
4262
4263 // Comparison Code, floating, unordered same as less
4264 operand cmpOpF() %{
4265 match(Bool);
4266 predicate(n->as_Bool()->_test._test != BoolTest::overflow &&
4267 n->as_Bool()->_test._test != BoolTest::no_overflow);
4268
4269 format %{ "fl" %}
4270 interface(COND_INTER) %{
4271 equal(0x9);
4272 not_equal(0x1);
4273 less(0x3);
4274 greater_equal(0xB);
4275 less_equal(0xE);
4276 greater(0x6);
4277
4278 overflow(0x7); // not supported
4279 no_overflow(0xF); // not supported
4280 %}
4281 %}
4282
4283 // Used by long compare
4284 operand cmpOp_commute() %{
4285 match(Bool);
4286 predicate(n->as_Bool()->_test._test != BoolTest::overflow &&
4287 n->as_Bool()->_test._test != BoolTest::no_overflow);
4288
4289 format %{ "" %}
4290 interface(COND_INTER) %{
4291 equal(0x1);
4292 not_equal(0x9);
4293 less(0xA);
4294 greater_equal(0x2);
4295 less_equal(0xB);
4296 greater(0x3);
4297 overflow(0x7);
4298 no_overflow(0xF);
4299 %}
4300 %}
4301
4302 //----------OPERAND CLASSES----------------------------------------------------
4303 // Operand Classes are groups of operands that are used to simplify
4304 // instruction definitions by not requiring the AD writer to specify separate
4305 // instructions for every form of operand when the instruction accepts
4306 // multiple operand types with the same basic encoding and format. The classic
4307 // case of this is memory operands.
4308 opclass memory( indirect, indOffset13, indIndex );
4309 opclass indIndexMemory( indIndex );
4310
4311 //----------PIPELINE-----------------------------------------------------------
4312 pipeline %{
4313
4314 //----------ATTRIBUTES---------------------------------------------------------
4315 attributes %{
4316 fixed_size_instructions; // Fixed size instructions
4317 branch_has_delay_slot; // Branch has delay slot following
4318 max_instructions_per_bundle = 4; // Up to 4 instructions per bundle
4319 instruction_unit_size = 4; // An instruction is 4 bytes long
4320 instruction_fetch_unit_size = 16; // The processor fetches one line
4321 instruction_fetch_units = 1; // of 16 bytes
4322
4323 // List of nop instructions
4324 nops( Nop_A0, Nop_A1, Nop_MS, Nop_FA, Nop_BR );
4325 %}
4326
4327 //----------RESOURCES----------------------------------------------------------
4328 // Resources are the functional units available to the machine
4329 resources(A0, A1, MS, BR, FA, FM, IDIV, FDIV, IALU = A0 | A1);
4330
4331 //----------PIPELINE DESCRIPTION-----------------------------------------------
4332 // Pipeline Description specifies the stages in the machine's pipeline
4333
4334 pipe_desc(A, P, F, B, I, J, S, R, E, C, M, W, X, T, D);
4335
4336 //----------PIPELINE CLASSES---------------------------------------------------
4337 // Pipeline Classes describe the stages in which input and output are
4338 // referenced by the hardware pipeline.
4339
4340 // Integer ALU reg-reg operation
4341 pipe_class ialu_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
4342 single_instruction;
4343 dst : E(write);
4344 src1 : R(read);
4345 src2 : R(read);
4346 IALU : R;
4347 %}
4348
4349 // Integer ALU reg-reg long operation
4350 pipe_class ialu_reg_reg_2(iRegL dst, iRegL src1, iRegL src2) %{
4351 instruction_count(2);
4352 dst : E(write);
4353 src1 : R(read);
4354 src2 : R(read);
4355 IALU : R;
4356 IALU : R;
4357 %}
4358
4359 // Integer ALU reg-reg long dependent operation
4360 pipe_class ialu_reg_reg_2_dep(iRegL dst, iRegL src1, iRegL src2, flagsReg cr) %{
4361 instruction_count(1); multiple_bundles;
4362 dst : E(write);
4363 src1 : R(read);
4364 src2 : R(read);
4365 cr : E(write);
4366 IALU : R(2);
4367 %}
4368
4369 // Integer ALU reg-imm operaion
4370 pipe_class ialu_reg_imm(iRegI dst, iRegI src1, immI13 src2) %{
4371 single_instruction;
4372 dst : E(write);
4373 src1 : R(read);
4374 IALU : R;
4375 %}
4376
4377 // Integer ALU reg-reg operation with condition code
4378 pipe_class ialu_cc_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{
4379 single_instruction;
4380 dst : E(write);
4381 cr : E(write);
4382 src1 : R(read);
4383 src2 : R(read);
4384 IALU : R;
4385 %}
4386
4387 // Integer ALU reg-imm operation with condition code
4388 pipe_class ialu_cc_reg_imm(iRegI dst, iRegI src1, immI13 src2, flagsReg cr) %{
4389 single_instruction;
4390 dst : E(write);
4391 cr : E(write);
4392 src1 : R(read);
4393 IALU : R;
4394 %}
4395
4396 // Integer ALU zero-reg operation
4397 pipe_class ialu_zero_reg(iRegI dst, immI0 zero, iRegI src2) %{
4398 single_instruction;
4399 dst : E(write);
4400 src2 : R(read);
4401 IALU : R;
4402 %}
4403
4404 // Integer ALU zero-reg operation with condition code only
4405 pipe_class ialu_cconly_zero_reg(flagsReg cr, iRegI src) %{
4406 single_instruction;
4407 cr : E(write);
4408 src : R(read);
4409 IALU : R;
4410 %}
4411
4412 // Integer ALU reg-reg operation with condition code only
4413 pipe_class ialu_cconly_reg_reg(flagsReg cr, iRegI src1, iRegI src2) %{
4414 single_instruction;
4415 cr : E(write);
4416 src1 : R(read);
4417 src2 : R(read);
4418 IALU : R;
4419 %}
4420
4421 // Integer ALU reg-imm operation with condition code only
4422 pipe_class ialu_cconly_reg_imm(flagsReg cr, iRegI src1, immI13 src2) %{
4423 single_instruction;
4424 cr : E(write);
4425 src1 : R(read);
4426 IALU : R;
4427 %}
4428
4429 // Integer ALU reg-reg-zero operation with condition code only
4430 pipe_class ialu_cconly_reg_reg_zero(flagsReg cr, iRegI src1, iRegI src2, immI0 zero) %{
4431 single_instruction;
4432 cr : E(write);
4433 src1 : R(read);
4434 src2 : R(read);
4435 IALU : R;
4436 %}
4437
4438 // Integer ALU reg-imm-zero operation with condition code only
4439 pipe_class ialu_cconly_reg_imm_zero(flagsReg cr, iRegI src1, immI13 src2, immI0 zero) %{
4440 single_instruction;
4441 cr : E(write);
4442 src1 : R(read);
4443 IALU : R;
4444 %}
4445
4446 // Integer ALU reg-reg operation with condition code, src1 modified
4447 pipe_class ialu_cc_rwreg_reg(flagsReg cr, iRegI src1, iRegI src2) %{
4448 single_instruction;
4449 cr : E(write);
4450 src1 : E(write);
4451 src1 : R(read);
4452 src2 : R(read);
4453 IALU : R;
4454 %}
4455
4456 // Integer ALU reg-imm operation with condition code, src1 modified
4457 pipe_class ialu_cc_rwreg_imm(flagsReg cr, iRegI src1, immI13 src2) %{
4458 single_instruction;
4459 cr : E(write);
4460 src1 : E(write);
4461 src1 : R(read);
4462 IALU : R;
4463 %}
4464
4465 pipe_class cmpL_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg cr ) %{
4466 multiple_bundles;
4467 dst : E(write)+4;
4468 cr : E(write);
4469 src1 : R(read);
4470 src2 : R(read);
4471 IALU : R(3);
4472 BR : R(2);
4473 %}
4474
4475 // Integer ALU operation
4476 pipe_class ialu_none(iRegI dst) %{
4477 single_instruction;
4478 dst : E(write);
4479 IALU : R;
4480 %}
4481
4482 // Integer ALU reg operation
4483 pipe_class ialu_reg(iRegI dst, iRegI src) %{
4484 single_instruction; may_have_no_code;
4485 dst : E(write);
4486 src : R(read);
4487 IALU : R;
4488 %}
4489
4490 // Integer ALU reg conditional operation
4491 // This instruction has a 1 cycle stall, and cannot execute
4492 // in the same cycle as the instruction setting the condition
4493 // code. We kludge this by pretending to read the condition code
4494 // 1 cycle earlier, and by marking the functional units as busy
4495 // for 2 cycles with the result available 1 cycle later than
4496 // is really the case.
4497 pipe_class ialu_reg_flags( iRegI op2_out, iRegI op2_in, iRegI op1, flagsReg cr ) %{
4498 single_instruction;
4499 op2_out : C(write);
4500 op1 : R(read);
4501 cr : R(read); // This is really E, with a 1 cycle stall
4502 BR : R(2);
4503 MS : R(2);
4504 %}
4505
4506 #ifdef _LP64
4507 pipe_class ialu_clr_and_mover( iRegI dst, iRegP src ) %{
4508 instruction_count(1); multiple_bundles;
4509 dst : C(write)+1;
4510 src : R(read)+1;
4511 IALU : R(1);
4512 BR : E(2);
4513 MS : E(2);
4514 %}
4515 #endif
4516
4517 // Integer ALU reg operation
4518 pipe_class ialu_move_reg_L_to_I(iRegI dst, iRegL src) %{
4519 single_instruction; may_have_no_code;
4520 dst : E(write);
4521 src : R(read);
4522 IALU : R;
4523 %}
4524 pipe_class ialu_move_reg_I_to_L(iRegL dst, iRegI src) %{
4525 single_instruction; may_have_no_code;
4526 dst : E(write);
4527 src : R(read);
4528 IALU : R;
4529 %}
4530
4531 // Two integer ALU reg operations
4532 pipe_class ialu_reg_2(iRegL dst, iRegL src) %{
4533 instruction_count(2);
4534 dst : E(write);
4535 src : R(read);
4536 A0 : R;
4537 A1 : R;
4538 %}
4539
4540 // Two integer ALU reg operations
4541 pipe_class ialu_move_reg_L_to_L(iRegL dst, iRegL src) %{
4542 instruction_count(2); may_have_no_code;
4543 dst : E(write);
4544 src : R(read);
4545 A0 : R;
4546 A1 : R;
4547 %}
4548
4549 // Integer ALU imm operation
4550 pipe_class ialu_imm(iRegI dst, immI13 src) %{
4551 single_instruction;
4552 dst : E(write);
4553 IALU : R;
4554 %}
4555
4556 // Integer ALU reg-reg with carry operation
4557 pipe_class ialu_reg_reg_cy(iRegI dst, iRegI src1, iRegI src2, iRegI cy) %{
4558 single_instruction;
4559 dst : E(write);
4560 src1 : R(read);
4561 src2 : R(read);
4562 IALU : R;
4563 %}
4564
4565 // Integer ALU cc operation
4566 pipe_class ialu_cc(iRegI dst, flagsReg cc) %{
4567 single_instruction;
4568 dst : E(write);
4569 cc : R(read);
4570 IALU : R;
4571 %}
4572
4573 // Integer ALU cc / second IALU operation
4574 pipe_class ialu_reg_ialu( iRegI dst, iRegI src ) %{
4575 instruction_count(1); multiple_bundles;
4576 dst : E(write)+1;
4577 src : R(read);
4578 IALU : R;
4579 %}
4580
4581 // Integer ALU cc / second IALU operation
4582 pipe_class ialu_reg_reg_ialu( iRegI dst, iRegI p, iRegI q ) %{
4583 instruction_count(1); multiple_bundles;
4584 dst : E(write)+1;
4585 p : R(read);
4586 q : R(read);
4587 IALU : R;
4588 %}
4589
4590 // Integer ALU hi-lo-reg operation
4591 pipe_class ialu_hi_lo_reg(iRegI dst, immI src) %{
4592 instruction_count(1); multiple_bundles;
4593 dst : E(write)+1;
4594 IALU : R(2);
4595 %}
4596
4597 // Float ALU hi-lo-reg operation (with temp)
4598 pipe_class ialu_hi_lo_reg_temp(regF dst, immF src, g3RegP tmp) %{
4599 instruction_count(1); multiple_bundles;
4600 dst : E(write)+1;
4601 IALU : R(2);
4602 %}
4603
4604 // Long Constant
4605 pipe_class loadConL( iRegL dst, immL src ) %{
4606 instruction_count(2); multiple_bundles;
4607 dst : E(write)+1;
4608 IALU : R(2);
4609 IALU : R(2);
4610 %}
4611
4612 // Pointer Constant
4613 pipe_class loadConP( iRegP dst, immP src ) %{
4614 instruction_count(0); multiple_bundles;
4615 fixed_latency(6);
4616 %}
4617
4618 // Polling Address
4619 pipe_class loadConP_poll( iRegP dst, immP_poll src ) %{
4620 #ifdef _LP64
4621 instruction_count(0); multiple_bundles;
4622 fixed_latency(6);
4623 #else
4624 dst : E(write);
4625 IALU : R;
4626 #endif
4627 %}
4628
4629 // Long Constant small
4630 pipe_class loadConLlo( iRegL dst, immL src ) %{
4631 instruction_count(2);
4632 dst : E(write);
4633 IALU : R;
4634 IALU : R;
4635 %}
4636
4637 // [PHH] This is wrong for 64-bit. See LdImmF/D.
4638 pipe_class loadConFD(regF dst, immF src, g3RegP tmp) %{
4639 instruction_count(1); multiple_bundles;
4640 src : R(read);
4641 dst : M(write)+1;
4642 IALU : R;
4643 MS : E;
4644 %}
4645
4646 // Integer ALU nop operation
4647 pipe_class ialu_nop() %{
4648 single_instruction;
4649 IALU : R;
4650 %}
4651
4652 // Integer ALU nop operation
4653 pipe_class ialu_nop_A0() %{
4654 single_instruction;
4655 A0 : R;
4656 %}
4657
4658 // Integer ALU nop operation
4659 pipe_class ialu_nop_A1() %{
4660 single_instruction;
4661 A1 : R;
4662 %}
4663
4664 // Integer Multiply reg-reg operation
4665 pipe_class imul_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
4666 single_instruction;
4667 dst : E(write);
4668 src1 : R(read);
4669 src2 : R(read);
4670 MS : R(5);
4671 %}
4672
4673 // Integer Multiply reg-imm operation
4674 pipe_class imul_reg_imm(iRegI dst, iRegI src1, immI13 src2) %{
4675 single_instruction;
4676 dst : E(write);
4677 src1 : R(read);
4678 MS : R(5);
4679 %}
4680
4681 pipe_class mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
4682 single_instruction;
4683 dst : E(write)+4;
4684 src1 : R(read);
4685 src2 : R(read);
4686 MS : R(6);
4687 %}
4688
4689 pipe_class mulL_reg_imm(iRegL dst, iRegL src1, immL13 src2) %{
4690 single_instruction;
4691 dst : E(write)+4;
4692 src1 : R(read);
4693 MS : R(6);
4694 %}
4695
4696 // Integer Divide reg-reg
4697 pipe_class sdiv_reg_reg(iRegI dst, iRegI src1, iRegI src2, iRegI temp, flagsReg cr) %{
4698 instruction_count(1); multiple_bundles;
4699 dst : E(write);
4700 temp : E(write);
4701 src1 : R(read);
4702 src2 : R(read);
4703 temp : R(read);
4704 MS : R(38);
4705 %}
4706
4707 // Integer Divide reg-imm
4708 pipe_class sdiv_reg_imm(iRegI dst, iRegI src1, immI13 src2, iRegI temp, flagsReg cr) %{
4709 instruction_count(1); multiple_bundles;
4710 dst : E(write);
4711 temp : E(write);
4712 src1 : R(read);
4713 temp : R(read);
4714 MS : R(38);
4715 %}
4716
4717 // Long Divide
4718 pipe_class divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
4719 dst : E(write)+71;
4720 src1 : R(read);
4721 src2 : R(read)+1;
4722 MS : R(70);
4723 %}
4724
4725 pipe_class divL_reg_imm(iRegL dst, iRegL src1, immL13 src2) %{
4726 dst : E(write)+71;
4727 src1 : R(read);
4728 MS : R(70);
4729 %}
4730
4731 // Floating Point Add Float
4732 pipe_class faddF_reg_reg(regF dst, regF src1, regF src2) %{
4733 single_instruction;
4734 dst : X(write);
4735 src1 : E(read);
4736 src2 : E(read);
4737 FA : R;
4738 %}
4739
4740 // Floating Point Add Double
4741 pipe_class faddD_reg_reg(regD dst, regD src1, regD src2) %{
4742 single_instruction;
4743 dst : X(write);
4744 src1 : E(read);
4745 src2 : E(read);
4746 FA : R;
4747 %}
4748
4749 // Floating Point Conditional Move based on integer flags
4750 pipe_class int_conditional_float_move (cmpOp cmp, flagsReg cr, regF dst, regF src) %{
4751 single_instruction;
4752 dst : X(write);
4753 src : E(read);
4754 cr : R(read);
4755 FA : R(2);
4756 BR : R(2);
4757 %}
4758
4759 // Floating Point Conditional Move based on integer flags
4760 pipe_class int_conditional_double_move (cmpOp cmp, flagsReg cr, regD dst, regD src) %{
4761 single_instruction;
4762 dst : X(write);
4763 src : E(read);
4764 cr : R(read);
4765 FA : R(2);
4766 BR : R(2);
4767 %}
4768
4769 // Floating Point Multiply Float
4770 pipe_class fmulF_reg_reg(regF dst, regF src1, regF src2) %{
4771 single_instruction;
4772 dst : X(write);
4773 src1 : E(read);
4774 src2 : E(read);
4775 FM : R;
4776 %}
4777
4778 // Floating Point Multiply Double
4779 pipe_class fmulD_reg_reg(regD dst, regD src1, regD src2) %{
4780 single_instruction;
4781 dst : X(write);
4782 src1 : E(read);
4783 src2 : E(read);
4784 FM : R;
4785 %}
4786
4787 // Floating Point Divide Float
4788 pipe_class fdivF_reg_reg(regF dst, regF src1, regF src2) %{
4789 single_instruction;
4790 dst : X(write);
4791 src1 : E(read);
4792 src2 : E(read);
4793 FM : R;
4794 FDIV : C(14);
4795 %}
4796
4797 // Floating Point Divide Double
4798 pipe_class fdivD_reg_reg(regD dst, regD src1, regD src2) %{
4799 single_instruction;
4800 dst : X(write);
4801 src1 : E(read);
4802 src2 : E(read);
4803 FM : R;
4804 FDIV : C(17);
4805 %}
4806
4807 // Floating Point Move/Negate/Abs Float
4808 pipe_class faddF_reg(regF dst, regF src) %{
4809 single_instruction;
4810 dst : W(write);
4811 src : E(read);
4812 FA : R(1);
4813 %}
4814
4815 // Floating Point Move/Negate/Abs Double
4816 pipe_class faddD_reg(regD dst, regD src) %{
4817 single_instruction;
4818 dst : W(write);
4819 src : E(read);
4820 FA : R;
4821 %}
4822
4823 // Floating Point Convert F->D
4824 pipe_class fcvtF2D(regD dst, regF src) %{
4825 single_instruction;
4826 dst : X(write);
4827 src : E(read);
4828 FA : R;
4829 %}
4830
4831 // Floating Point Convert I->D
4832 pipe_class fcvtI2D(regD dst, regF src) %{
4833 single_instruction;
4834 dst : X(write);
4835 src : E(read);
4836 FA : R;
4837 %}
4838
4839 // Floating Point Convert LHi->D
4840 pipe_class fcvtLHi2D(regD dst, regD src) %{
4841 single_instruction;
4842 dst : X(write);
4843 src : E(read);
4844 FA : R;
4845 %}
4846
4847 // Floating Point Convert L->D
4848 pipe_class fcvtL2D(regD dst, regF src) %{
4849 single_instruction;
4850 dst : X(write);
4851 src : E(read);
4852 FA : R;
4853 %}
4854
4855 // Floating Point Convert L->F
4856 pipe_class fcvtL2F(regD dst, regF src) %{
4857 single_instruction;
4858 dst : X(write);
4859 src : E(read);
4860 FA : R;
4861 %}
4862
4863 // Floating Point Convert D->F
4864 pipe_class fcvtD2F(regD dst, regF src) %{
4865 single_instruction;
4866 dst : X(write);
4867 src : E(read);
4868 FA : R;
4869 %}
4870
4871 // Floating Point Convert I->L
4872 pipe_class fcvtI2L(regD dst, regF src) %{
4873 single_instruction;
4874 dst : X(write);
4875 src : E(read);
4876 FA : R;
4877 %}
4878
4879 // Floating Point Convert D->F
4880 pipe_class fcvtD2I(regF dst, regD src, flagsReg cr) %{
4881 instruction_count(1); multiple_bundles;
4882 dst : X(write)+6;
4883 src : E(read);
4884 FA : R;
4885 %}
4886
4887 // Floating Point Convert D->L
4888 pipe_class fcvtD2L(regD dst, regD src, flagsReg cr) %{
4889 instruction_count(1); multiple_bundles;
4890 dst : X(write)+6;
4891 src : E(read);
4892 FA : R;
4893 %}
4894
4895 // Floating Point Convert F->I
4896 pipe_class fcvtF2I(regF dst, regF src, flagsReg cr) %{
4897 instruction_count(1); multiple_bundles;
4898 dst : X(write)+6;
4899 src : E(read);
4900 FA : R;
4901 %}
4902
4903 // Floating Point Convert F->L
4904 pipe_class fcvtF2L(regD dst, regF src, flagsReg cr) %{
4905 instruction_count(1); multiple_bundles;
4906 dst : X(write)+6;
4907 src : E(read);
4908 FA : R;
4909 %}
4910
4911 // Floating Point Convert I->F
4912 pipe_class fcvtI2F(regF dst, regF src) %{
4913 single_instruction;
4914 dst : X(write);
4915 src : E(read);
4916 FA : R;
4917 %}
4918
4919 // Floating Point Compare
4920 pipe_class faddF_fcc_reg_reg_zero(flagsRegF cr, regF src1, regF src2, immI0 zero) %{
4921 single_instruction;
4922 cr : X(write);
4923 src1 : E(read);
4924 src2 : E(read);
4925 FA : R;
4926 %}
4927
4928 // Floating Point Compare
4929 pipe_class faddD_fcc_reg_reg_zero(flagsRegF cr, regD src1, regD src2, immI0 zero) %{
4930 single_instruction;
4931 cr : X(write);
4932 src1 : E(read);
4933 src2 : E(read);
4934 FA : R;
4935 %}
4936
4937 // Floating Add Nop
4938 pipe_class fadd_nop() %{
4939 single_instruction;
4940 FA : R;
4941 %}
4942
4943 // Integer Store to Memory
4944 pipe_class istore_mem_reg(memory mem, iRegI src) %{
4945 single_instruction;
4946 mem : R(read);
4947 src : C(read);
4948 MS : R;
4949 %}
4950
4951 // Integer Store to Memory
4952 pipe_class istore_mem_spORreg(memory mem, sp_ptr_RegP src) %{
4953 single_instruction;
4954 mem : R(read);
4955 src : C(read);
4956 MS : R;
4957 %}
4958
4959 // Integer Store Zero to Memory
4960 pipe_class istore_mem_zero(memory mem, immI0 src) %{
4961 single_instruction;
4962 mem : R(read);
4963 MS : R;
4964 %}
4965
4966 // Special Stack Slot Store
4967 pipe_class istore_stk_reg(stackSlotI stkSlot, iRegI src) %{
4968 single_instruction;
4969 stkSlot : R(read);
4970 src : C(read);
4971 MS : R;
4972 %}
4973
4974 // Special Stack Slot Store
4975 pipe_class lstoreI_stk_reg(stackSlotL stkSlot, iRegI src) %{
4976 instruction_count(2); multiple_bundles;
4977 stkSlot : R(read);
4978 src : C(read);
4979 MS : R(2);
4980 %}
4981
4982 // Float Store
4983 pipe_class fstoreF_mem_reg(memory mem, RegF src) %{
4984 single_instruction;
4985 mem : R(read);
4986 src : C(read);
4987 MS : R;
4988 %}
4989
4990 // Float Store
4991 pipe_class fstoreF_mem_zero(memory mem, immF0 src) %{
4992 single_instruction;
4993 mem : R(read);
4994 MS : R;
4995 %}
4996
4997 // Double Store
4998 pipe_class fstoreD_mem_reg(memory mem, RegD src) %{
4999 instruction_count(1);
5000 mem : R(read);
5001 src : C(read);
5002 MS : R;
5003 %}
5004
5005 // Double Store
5006 pipe_class fstoreD_mem_zero(memory mem, immD0 src) %{
5007 single_instruction;
5008 mem : R(read);
5009 MS : R;
5010 %}
5011
5012 // Special Stack Slot Float Store
5013 pipe_class fstoreF_stk_reg(stackSlotI stkSlot, RegF src) %{
5014 single_instruction;
5015 stkSlot : R(read);
5016 src : C(read);
5017 MS : R;
5018 %}
5019
5020 // Special Stack Slot Double Store
5021 pipe_class fstoreD_stk_reg(stackSlotI stkSlot, RegD src) %{
5022 single_instruction;
5023 stkSlot : R(read);
5024 src : C(read);
5025 MS : R;
5026 %}
5027
5028 // Integer Load (when sign bit propagation not needed)
5029 pipe_class iload_mem(iRegI dst, memory mem) %{
5030 single_instruction;
5031 mem : R(read);
5032 dst : C(write);
5033 MS : R;
5034 %}
5035
5036 // Integer Load from stack operand
5037 pipe_class iload_stkD(iRegI dst, stackSlotD mem ) %{
5038 single_instruction;
5039 mem : R(read);
5040 dst : C(write);
5041 MS : R;
5042 %}
5043
5044 // Integer Load (when sign bit propagation or masking is needed)
5045 pipe_class iload_mask_mem(iRegI dst, memory mem) %{
5046 single_instruction;
5047 mem : R(read);
5048 dst : M(write);
5049 MS : R;
5050 %}
5051
5052 // Float Load
5053 pipe_class floadF_mem(regF dst, memory mem) %{
5054 single_instruction;
5055 mem : R(read);
5056 dst : M(write);
5057 MS : R;
5058 %}
5059
5060 // Float Load
5061 pipe_class floadD_mem(regD dst, memory mem) %{
5062 instruction_count(1); multiple_bundles; // Again, unaligned argument is only multiple case
5063 mem : R(read);
5064 dst : M(write);
5065 MS : R;
5066 %}
5067
5068 // Float Load
5069 pipe_class floadF_stk(regF dst, stackSlotI stkSlot) %{
5070 single_instruction;
5071 stkSlot : R(read);
5072 dst : M(write);
5073 MS : R;
5074 %}
5075
5076 // Float Load
5077 pipe_class floadD_stk(regD dst, stackSlotI stkSlot) %{
5078 single_instruction;
5079 stkSlot : R(read);
5080 dst : M(write);
5081 MS : R;
5082 %}
5083
5084 // Memory Nop
5085 pipe_class mem_nop() %{
5086 single_instruction;
5087 MS : R;
5088 %}
5089
5090 pipe_class sethi(iRegP dst, immI src) %{
5091 single_instruction;
5092 dst : E(write);
5093 IALU : R;
5094 %}
5095
5096 pipe_class loadPollP(iRegP poll) %{
5097 single_instruction;
5098 poll : R(read);
5099 MS : R;
5100 %}
5101
5102 pipe_class br(Universe br, label labl) %{
5103 single_instruction_with_delay_slot;
5104 BR : R;
5105 %}
5106
5107 pipe_class br_cc(Universe br, cmpOp cmp, flagsReg cr, label labl) %{
5108 single_instruction_with_delay_slot;
5109 cr : E(read);
5110 BR : R;
5111 %}
5112
5113 pipe_class br_reg(Universe br, cmpOp cmp, iRegI op1, label labl) %{
5114 single_instruction_with_delay_slot;
5115 op1 : E(read);
5116 BR : R;
5117 MS : R;
5118 %}
5119
5120 // Compare and branch
5121 pipe_class cmp_br_reg_reg(Universe br, cmpOp cmp, iRegI src1, iRegI src2, label labl, flagsReg cr) %{
5122 instruction_count(2); has_delay_slot;
5123 cr : E(write);
5124 src1 : R(read);
5125 src2 : R(read);
5126 IALU : R;
5127 BR : R;
5128 %}
5129
5130 // Compare and branch
5131 pipe_class cmp_br_reg_imm(Universe br, cmpOp cmp, iRegI src1, immI13 src2, label labl, flagsReg cr) %{
5132 instruction_count(2); has_delay_slot;
5133 cr : E(write);
5134 src1 : R(read);
5135 IALU : R;
5136 BR : R;
5137 %}
5138
5139 // Compare and branch using cbcond
5140 pipe_class cbcond_reg_reg(Universe br, cmpOp cmp, iRegI src1, iRegI src2, label labl) %{
5141 single_instruction;
5142 src1 : E(read);
5143 src2 : E(read);
5144 IALU : R;
5145 BR : R;
5146 %}
5147
5148 // Compare and branch using cbcond
5149 pipe_class cbcond_reg_imm(Universe br, cmpOp cmp, iRegI src1, immI5 src2, label labl) %{
5150 single_instruction;
5151 src1 : E(read);
5152 IALU : R;
5153 BR : R;
5154 %}
5155
5156 pipe_class br_fcc(Universe br, cmpOpF cc, flagsReg cr, label labl) %{
5157 single_instruction_with_delay_slot;
5158 cr : E(read);
5159 BR : R;
5160 %}
5161
5162 pipe_class br_nop() %{
5163 single_instruction;
5164 BR : R;
5165 %}
5166
5167 pipe_class simple_call(method meth) %{
5168 instruction_count(2); multiple_bundles; force_serialization;
5169 fixed_latency(100);
5170 BR : R(1);
5171 MS : R(1);
5172 A0 : R(1);
5173 %}
5174
5175 pipe_class compiled_call(method meth) %{
5176 instruction_count(1); multiple_bundles; force_serialization;
5177 fixed_latency(100);
5178 MS : R(1);
5179 %}
5180
5181 pipe_class call(method meth) %{
5182 instruction_count(0); multiple_bundles; force_serialization;
5183 fixed_latency(100);
5184 %}
5185
5186 pipe_class tail_call(Universe ignore, label labl) %{
5187 single_instruction; has_delay_slot;
5188 fixed_latency(100);
5189 BR : R(1);
5190 MS : R(1);
5191 %}
5192
5193 pipe_class ret(Universe ignore) %{
5194 single_instruction; has_delay_slot;
5195 BR : R(1);
5196 MS : R(1);
5197 %}
5198
5199 pipe_class ret_poll(g3RegP poll) %{
5200 instruction_count(3); has_delay_slot;
5201 poll : E(read);
5202 MS : R;
5203 %}
5204
5205 // The real do-nothing guy
5206 pipe_class empty( ) %{
5207 instruction_count(0);
5208 %}
5209
5210 pipe_class long_memory_op() %{
5211 instruction_count(0); multiple_bundles; force_serialization;
5212 fixed_latency(25);
5213 MS : R(1);
5214 %}
5215
5216 // Check-cast
5217 pipe_class partial_subtype_check_pipe(Universe ignore, iRegP array, iRegP match ) %{
5218 array : R(read);
5219 match : R(read);
5220 IALU : R(2);
5221 BR : R(2);
5222 MS : R;
5223 %}
5224
5225 // Convert FPU flags into +1,0,-1
5226 pipe_class floating_cmp( iRegI dst, regF src1, regF src2 ) %{
5227 src1 : E(read);
5228 src2 : E(read);
5229 dst : E(write);
5230 FA : R;
5231 MS : R(2);
5232 BR : R(2);
5233 %}
5234
5235 // Compare for p < q, and conditionally add y
5236 pipe_class cadd_cmpltmask( iRegI p, iRegI q, iRegI y ) %{
5237 p : E(read);
5238 q : E(read);
5239 y : E(read);
5240 IALU : R(3)
5241 %}
5242
5243 // Perform a compare, then move conditionally in a branch delay slot.
5244 pipe_class min_max( iRegI src2, iRegI srcdst ) %{
5245 src2 : E(read);
5246 srcdst : E(read);
5247 IALU : R;
5248 BR : R;
5249 %}
5250
5251 // Define the class for the Nop node
5252 define %{
5253 MachNop = ialu_nop;
5254 %}
5255
5256 %}
5257
5258 //----------INSTRUCTIONS-------------------------------------------------------
5259
5260 //------------Special Stack Slot instructions - no match rules-----------------
5261 instruct stkI_to_regF(regF dst, stackSlotI src) %{
5262 // No match rule to avoid chain rule match.
5263 effect(DEF dst, USE src);
5264 ins_cost(MEMORY_REF_COST);
5265 format %{ "LDF $src,$dst\t! stkI to regF" %}
5266 opcode(Assembler::ldf_op3);
5267 ins_encode(simple_form3_mem_reg(src, dst));
5268 ins_pipe(floadF_stk);
5269 %}
5270
5271 instruct stkL_to_regD(regD dst, stackSlotL src) %{
5272 // No match rule to avoid chain rule match.
5273 effect(DEF dst, USE src);
5274 ins_cost(MEMORY_REF_COST);
5275 format %{ "LDDF $src,$dst\t! stkL to regD" %}
5276 opcode(Assembler::lddf_op3);
5277 ins_encode(simple_form3_mem_reg(src, dst));
5278 ins_pipe(floadD_stk);
5279 %}
5280
5281 instruct regF_to_stkI(stackSlotI dst, regF src) %{
5282 // No match rule to avoid chain rule match.
5283 effect(DEF dst, USE src);
5284 ins_cost(MEMORY_REF_COST);
5285 format %{ "STF $src,$dst\t! regF to stkI" %}
5286 opcode(Assembler::stf_op3);
5287 ins_encode(simple_form3_mem_reg(dst, src));
5288 ins_pipe(fstoreF_stk_reg);
5289 %}
5290
5291 instruct regD_to_stkL(stackSlotL dst, regD src) %{
5292 // No match rule to avoid chain rule match.
5293 effect(DEF dst, USE src);
5294 ins_cost(MEMORY_REF_COST);
5295 format %{ "STDF $src,$dst\t! regD to stkL" %}
5296 opcode(Assembler::stdf_op3);
5297 ins_encode(simple_form3_mem_reg(dst, src));
5298 ins_pipe(fstoreD_stk_reg);
5299 %}
5300
5301 instruct regI_to_stkLHi(stackSlotL dst, iRegI src) %{
5302 effect(DEF dst, USE src);
5303 ins_cost(MEMORY_REF_COST*2);
5304 format %{ "STW $src,$dst.hi\t! long\n\t"
5305 "STW R_G0,$dst.lo" %}
5306 opcode(Assembler::stw_op3);
5307 ins_encode(simple_form3_mem_reg(dst, src), form3_mem_plus_4_reg(dst, R_G0));
5308 ins_pipe(lstoreI_stk_reg);
5309 %}
5310
5311 instruct regL_to_stkD(stackSlotD dst, iRegL src) %{
5312 // No match rule to avoid chain rule match.
5313 effect(DEF dst, USE src);
5314 ins_cost(MEMORY_REF_COST);
5315 format %{ "STX $src,$dst\t! regL to stkD" %}
5316 opcode(Assembler::stx_op3);
5317 ins_encode(simple_form3_mem_reg( dst, src ) );
5318 ins_pipe(istore_stk_reg);
5319 %}
5320
5321 //---------- Chain stack slots between similar types --------
5322
5323 // Load integer from stack slot
5324 instruct stkI_to_regI( iRegI dst, stackSlotI src ) %{
5325 match(Set dst src);
5326 ins_cost(MEMORY_REF_COST);
5327
5328 format %{ "LDUW $src,$dst\t!stk" %}
5329 opcode(Assembler::lduw_op3);
5330 ins_encode(simple_form3_mem_reg( src, dst ) );
5331 ins_pipe(iload_mem);
5332 %}
5333
5334 // Store integer to stack slot
5335 instruct regI_to_stkI( stackSlotI dst, iRegI src ) %{
5336 match(Set dst src);
5337 ins_cost(MEMORY_REF_COST);
5338
5339 format %{ "STW $src,$dst\t!stk" %}
5340 opcode(Assembler::stw_op3);
5341 ins_encode(simple_form3_mem_reg( dst, src ) );
5342 ins_pipe(istore_mem_reg);
5343 %}
5344
5345 // Load long from stack slot
5346 instruct stkL_to_regL( iRegL dst, stackSlotL src ) %{
5347 match(Set dst src);
5348
5349 ins_cost(MEMORY_REF_COST);
5350 format %{ "LDX $src,$dst\t! long" %}
5351 opcode(Assembler::ldx_op3);
5352 ins_encode(simple_form3_mem_reg( src, dst ) );
5353 ins_pipe(iload_mem);
5354 %}
5355
5356 // Store long to stack slot
5357 instruct regL_to_stkL(stackSlotL dst, iRegL src) %{
5358 match(Set dst src);
5359
5360 ins_cost(MEMORY_REF_COST);
5361 format %{ "STX $src,$dst\t! long" %}
5362 opcode(Assembler::stx_op3);
5363 ins_encode(simple_form3_mem_reg( dst, src ) );
5364 ins_pipe(istore_mem_reg);
5365 %}
5366
5367 #ifdef _LP64
5368 // Load pointer from stack slot, 64-bit encoding
5369 instruct stkP_to_regP( iRegP dst, stackSlotP src ) %{
5370 match(Set dst src);
5371 ins_cost(MEMORY_REF_COST);
5372 format %{ "LDX $src,$dst\t!ptr" %}
5373 opcode(Assembler::ldx_op3);
5374 ins_encode(simple_form3_mem_reg( src, dst ) );
5375 ins_pipe(iload_mem);
5376 %}
5377
5378 // Store pointer to stack slot
5379 instruct regP_to_stkP(stackSlotP dst, iRegP src) %{
5380 match(Set dst src);
5381 ins_cost(MEMORY_REF_COST);
5382 format %{ "STX $src,$dst\t!ptr" %}
5383 opcode(Assembler::stx_op3);
5384 ins_encode(simple_form3_mem_reg( dst, src ) );
5385 ins_pipe(istore_mem_reg);
5386 %}
5387 #else // _LP64
5388 // Load pointer from stack slot, 32-bit encoding
5389 instruct stkP_to_regP( iRegP dst, stackSlotP src ) %{
5390 match(Set dst src);
5391 ins_cost(MEMORY_REF_COST);
5392 format %{ "LDUW $src,$dst\t!ptr" %}
5393 opcode(Assembler::lduw_op3, Assembler::ldst_op);
5394 ins_encode(simple_form3_mem_reg( src, dst ) );
5395 ins_pipe(iload_mem);
5396 %}
5397
5398 // Store pointer to stack slot
5399 instruct regP_to_stkP(stackSlotP dst, iRegP src) %{
5400 match(Set dst src);
5401 ins_cost(MEMORY_REF_COST);
5402 format %{ "STW $src,$dst\t!ptr" %}
5403 opcode(Assembler::stw_op3, Assembler::ldst_op);
5404 ins_encode(simple_form3_mem_reg( dst, src ) );
5405 ins_pipe(istore_mem_reg);
5406 %}
5407 #endif // _LP64
5408
5409 //------------Special Nop instructions for bundling - no match rules-----------
5410 // Nop using the A0 functional unit
5411 instruct Nop_A0() %{
5412 ins_cost(0);
5413
5414 format %{ "NOP ! Alu Pipeline" %}
5415 opcode(Assembler::or_op3, Assembler::arith_op);
5416 ins_encode( form2_nop() );
5417 ins_pipe(ialu_nop_A0);
5418 %}
5419
5420 // Nop using the A1 functional unit
5421 instruct Nop_A1( ) %{
5422 ins_cost(0);
5423
5424 format %{ "NOP ! Alu Pipeline" %}
5425 opcode(Assembler::or_op3, Assembler::arith_op);
5426 ins_encode( form2_nop() );
5427 ins_pipe(ialu_nop_A1);
5428 %}
5429
5430 // Nop using the memory functional unit
5431 instruct Nop_MS( ) %{
5432 ins_cost(0);
5433
5434 format %{ "NOP ! Memory Pipeline" %}
5435 ins_encode( emit_mem_nop );
5436 ins_pipe(mem_nop);
5437 %}
5438
5439 // Nop using the floating add functional unit
5440 instruct Nop_FA( ) %{
5441 ins_cost(0);
5442
5443 format %{ "NOP ! Floating Add Pipeline" %}
5444 ins_encode( emit_fadd_nop );
5445 ins_pipe(fadd_nop);
5446 %}
5447
5448 // Nop using the branch functional unit
5449 instruct Nop_BR( ) %{
5450 ins_cost(0);
5451
5452 format %{ "NOP ! Branch Pipeline" %}
5453 ins_encode( emit_br_nop );
5454 ins_pipe(br_nop);
5455 %}
5456
5457 //----------Load/Store/Move Instructions---------------------------------------
5458 //----------Load Instructions--------------------------------------------------
5459 // Load Byte (8bit signed)
5460 instruct loadB(iRegI dst, memory mem) %{
5461 match(Set dst (LoadB mem));
5462 ins_cost(MEMORY_REF_COST);
5463
5464 size(4);
5465 format %{ "LDSB $mem,$dst\t! byte" %}
5466 ins_encode %{
5467 __ ldsb($mem$$Address, $dst$$Register);
5468 %}
5469 ins_pipe(iload_mask_mem);
5470 %}
5471
5472 // Load Byte (8bit signed) into a Long Register
5473 instruct loadB2L(iRegL dst, memory mem) %{
5474 match(Set dst (ConvI2L (LoadB mem)));
5475 ins_cost(MEMORY_REF_COST);
5476
5477 size(4);
5478 format %{ "LDSB $mem,$dst\t! byte -> long" %}
5479 ins_encode %{
5480 __ ldsb($mem$$Address, $dst$$Register);
5481 %}
5482 ins_pipe(iload_mask_mem);
5483 %}
5484
5485 // Load Unsigned Byte (8bit UNsigned) into an int reg
5486 instruct loadUB(iRegI dst, memory mem) %{
5487 match(Set dst (LoadUB mem));
5488 ins_cost(MEMORY_REF_COST);
5489
5490 size(4);
5491 format %{ "LDUB $mem,$dst\t! ubyte" %}
5492 ins_encode %{
5493 __ ldub($mem$$Address, $dst$$Register);
5494 %}
5495 ins_pipe(iload_mem);
5496 %}
5497
5498 // Load Unsigned Byte (8bit UNsigned) into a Long Register
5499 instruct loadUB2L(iRegL dst, memory mem) %{
5500 match(Set dst (ConvI2L (LoadUB mem)));
5501 ins_cost(MEMORY_REF_COST);
5502
5503 size(4);
5504 format %{ "LDUB $mem,$dst\t! ubyte -> long" %}
5505 ins_encode %{
5506 __ ldub($mem$$Address, $dst$$Register);
5507 %}
5508 ins_pipe(iload_mem);
5509 %}
5510
5511 // Load Unsigned Byte (8 bit UNsigned) with 32-bit mask into Long Register
5512 instruct loadUB2L_immI(iRegL dst, memory mem, immI mask) %{
5513 match(Set dst (ConvI2L (AndI (LoadUB mem) mask)));
5514 ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5515
5516 size(2*4);
5517 format %{ "LDUB $mem,$dst\t# ubyte & 32-bit mask -> long\n\t"
5518 "AND $dst,right_n_bits($mask, 8),$dst" %}
5519 ins_encode %{
5520 __ ldub($mem$$Address, $dst$$Register);
5521 __ and3($dst$$Register, $mask$$constant & right_n_bits(8), $dst$$Register);
5522 %}
5523 ins_pipe(iload_mem);
5524 %}
5525
5526 // Load Short (16bit signed)
5527 instruct loadS(iRegI dst, memory mem) %{
5528 match(Set dst (LoadS mem));
5529 ins_cost(MEMORY_REF_COST);
5530
5531 size(4);
5532 format %{ "LDSH $mem,$dst\t! short" %}
5533 ins_encode %{
5534 __ ldsh($mem$$Address, $dst$$Register);
5535 %}
5536 ins_pipe(iload_mask_mem);
5537 %}
5538
5539 // Load Short (16 bit signed) to Byte (8 bit signed)
5540 instruct loadS2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{
5541 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour));
5542 ins_cost(MEMORY_REF_COST);
5543
5544 size(4);
5545
5546 format %{ "LDSB $mem+1,$dst\t! short -> byte" %}
5547 ins_encode %{
5548 __ ldsb($mem$$Address, $dst$$Register, 1);
5549 %}
5550 ins_pipe(iload_mask_mem);
5551 %}
5552
5553 // Load Short (16bit signed) into a Long Register
5554 instruct loadS2L(iRegL dst, memory mem) %{
5555 match(Set dst (ConvI2L (LoadS mem)));
5556 ins_cost(MEMORY_REF_COST);
5557
5558 size(4);
5559 format %{ "LDSH $mem,$dst\t! short -> long" %}
5560 ins_encode %{
5561 __ ldsh($mem$$Address, $dst$$Register);
5562 %}
5563 ins_pipe(iload_mask_mem);
5564 %}
5565
5566 // Load Unsigned Short/Char (16bit UNsigned)
5567 instruct loadUS(iRegI dst, memory mem) %{
5568 match(Set dst (LoadUS mem));
5569 ins_cost(MEMORY_REF_COST);
5570
5571 size(4);
5572 format %{ "LDUH $mem,$dst\t! ushort/char" %}
5573 ins_encode %{
5574 __ lduh($mem$$Address, $dst$$Register);
5575 %}
5576 ins_pipe(iload_mem);
5577 %}
5578
5579 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed)
5580 instruct loadUS2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{
5581 match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour));
5582 ins_cost(MEMORY_REF_COST);
5583
5584 size(4);
5585 format %{ "LDSB $mem+1,$dst\t! ushort -> byte" %}
5586 ins_encode %{
5587 __ ldsb($mem$$Address, $dst$$Register, 1);
5588 %}
5589 ins_pipe(iload_mask_mem);
5590 %}
5591
5592 // Load Unsigned Short/Char (16bit UNsigned) into a Long Register
5593 instruct loadUS2L(iRegL dst, memory mem) %{
5594 match(Set dst (ConvI2L (LoadUS mem)));
5595 ins_cost(MEMORY_REF_COST);
5596
5597 size(4);
5598 format %{ "LDUH $mem,$dst\t! ushort/char -> long" %}
5599 ins_encode %{
5600 __ lduh($mem$$Address, $dst$$Register);
5601 %}
5602 ins_pipe(iload_mem);
5603 %}
5604
5605 // Load Unsigned Short/Char (16bit UNsigned) with mask 0xFF into a Long Register
5606 instruct loadUS2L_immI_255(iRegL dst, indOffset13m7 mem, immI_255 mask) %{
5607 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5608 ins_cost(MEMORY_REF_COST);
5609
5610 size(4);
5611 format %{ "LDUB $mem+1,$dst\t! ushort/char & 0xFF -> long" %}
5612 ins_encode %{
5613 __ ldub($mem$$Address, $dst$$Register, 1); // LSB is index+1 on BE
5614 %}
5615 ins_pipe(iload_mem);
5616 %}
5617
5618 // Load Unsigned Short/Char (16bit UNsigned) with a 13-bit mask into a Long Register
5619 instruct loadUS2L_immI13(iRegL dst, memory mem, immI13 mask) %{
5620 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5621 ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5622
5623 size(2*4);
5624 format %{ "LDUH $mem,$dst\t! ushort/char & 13-bit mask -> long\n\t"
5625 "AND $dst,$mask,$dst" %}
5626 ins_encode %{
5627 Register Rdst = $dst$$Register;
5628 __ lduh($mem$$Address, Rdst);
5629 __ and3(Rdst, $mask$$constant, Rdst);
5630 %}
5631 ins_pipe(iload_mem);
5632 %}
5633
5634 // Load Unsigned Short/Char (16bit UNsigned) with a 32-bit mask into a Long Register
5635 instruct loadUS2L_immI(iRegL dst, memory mem, immI mask, iRegL tmp) %{
5636 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5637 effect(TEMP dst, TEMP tmp);
5638 ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST);
5639
5640 format %{ "LDUH $mem,$dst\t! ushort/char & 32-bit mask -> long\n\t"
5641 "SET right_n_bits($mask, 16),$tmp\n\t"
5642 "AND $dst,$tmp,$dst" %}
5643 ins_encode %{
5644 Register Rdst = $dst$$Register;
5645 Register Rtmp = $tmp$$Register;
5646 __ lduh($mem$$Address, Rdst);
5647 __ set($mask$$constant & right_n_bits(16), Rtmp);
5648 __ and3(Rdst, Rtmp, Rdst);
5649 %}
5650 ins_pipe(iload_mem);
5651 %}
5652
5653 // Load Integer
5654 instruct loadI(iRegI dst, memory mem) %{
5655 match(Set dst (LoadI mem));
5656 ins_cost(MEMORY_REF_COST);
5657
5658 size(4);
5659 format %{ "LDUW $mem,$dst\t! int" %}
5660 ins_encode %{
5661 __ lduw($mem$$Address, $dst$$Register);
5662 %}
5663 ins_pipe(iload_mem);
5664 %}
5665
5666 // Load Integer to Byte (8 bit signed)
5667 instruct loadI2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{
5668 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour));
5669 ins_cost(MEMORY_REF_COST);
5670
5671 size(4);
5672
5673 format %{ "LDSB $mem+3,$dst\t! int -> byte" %}
5674 ins_encode %{
5675 __ ldsb($mem$$Address, $dst$$Register, 3);
5676 %}
5677 ins_pipe(iload_mask_mem);
5678 %}
5679
5680 // Load Integer to Unsigned Byte (8 bit UNsigned)
5681 instruct loadI2UB(iRegI dst, indOffset13m7 mem, immI_255 mask) %{
5682 match(Set dst (AndI (LoadI mem) mask));
5683 ins_cost(MEMORY_REF_COST);
5684
5685 size(4);
5686
5687 format %{ "LDUB $mem+3,$dst\t! int -> ubyte" %}
5688 ins_encode %{
5689 __ ldub($mem$$Address, $dst$$Register, 3);
5690 %}
5691 ins_pipe(iload_mask_mem);
5692 %}
5693
5694 // Load Integer to Short (16 bit signed)
5695 instruct loadI2S(iRegI dst, indOffset13m7 mem, immI_16 sixteen) %{
5696 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen));
5697 ins_cost(MEMORY_REF_COST);
5698
5699 size(4);
5700
5701 format %{ "LDSH $mem+2,$dst\t! int -> short" %}
5702 ins_encode %{
5703 __ ldsh($mem$$Address, $dst$$Register, 2);
5704 %}
5705 ins_pipe(iload_mask_mem);
5706 %}
5707
5708 // Load Integer to Unsigned Short (16 bit UNsigned)
5709 instruct loadI2US(iRegI dst, indOffset13m7 mem, immI_65535 mask) %{
5710 match(Set dst (AndI (LoadI mem) mask));
5711 ins_cost(MEMORY_REF_COST);
5712
5713 size(4);
5714
5715 format %{ "LDUH $mem+2,$dst\t! int -> ushort/char" %}
5716 ins_encode %{
5717 __ lduh($mem$$Address, $dst$$Register, 2);
5718 %}
5719 ins_pipe(iload_mask_mem);
5720 %}
5721
5722 // Load Integer into a Long Register
5723 instruct loadI2L(iRegL dst, memory mem) %{
5724 match(Set dst (ConvI2L (LoadI mem)));
5725 ins_cost(MEMORY_REF_COST);
5726
5727 size(4);
5728 format %{ "LDSW $mem,$dst\t! int -> long" %}
5729 ins_encode %{
5730 __ ldsw($mem$$Address, $dst$$Register);
5731 %}
5732 ins_pipe(iload_mask_mem);
5733 %}
5734
5735 // Load Integer with mask 0xFF into a Long Register
5736 instruct loadI2L_immI_255(iRegL dst, indOffset13m7 mem, immI_255 mask) %{
5737 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5738 ins_cost(MEMORY_REF_COST);
5739
5740 size(4);
5741 format %{ "LDUB $mem+3,$dst\t! int & 0xFF -> long" %}
5742 ins_encode %{
5743 __ ldub($mem$$Address, $dst$$Register, 3); // LSB is index+3 on BE
5744 %}
5745 ins_pipe(iload_mem);
5746 %}
5747
5748 // Load Integer with mask 0xFFFF into a Long Register
5749 instruct loadI2L_immI_65535(iRegL dst, indOffset13m7 mem, immI_65535 mask) %{
5750 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5751 ins_cost(MEMORY_REF_COST);
5752
5753 size(4);
5754 format %{ "LDUH $mem+2,$dst\t! int & 0xFFFF -> long" %}
5755 ins_encode %{
5756 __ lduh($mem$$Address, $dst$$Register, 2); // LSW is index+2 on BE
5757 %}
5758 ins_pipe(iload_mem);
5759 %}
5760
5761 // Load Integer with a 12-bit mask into a Long Register
5762 instruct loadI2L_immU12(iRegL dst, memory mem, immU12 mask) %{
5763 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5764 ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5765
5766 size(2*4);
5767 format %{ "LDUW $mem,$dst\t! int & 12-bit mask -> long\n\t"
5768 "AND $dst,$mask,$dst" %}
5769 ins_encode %{
5770 Register Rdst = $dst$$Register;
5771 __ lduw($mem$$Address, Rdst);
5772 __ and3(Rdst, $mask$$constant, Rdst);
5773 %}
5774 ins_pipe(iload_mem);
5775 %}
5776
5777 // Load Integer with a 31-bit mask into a Long Register
5778 instruct loadI2L_immU31(iRegL dst, memory mem, immU31 mask, iRegL tmp) %{
5779 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5780 effect(TEMP dst, TEMP tmp);
5781 ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST);
5782
5783 format %{ "LDUW $mem,$dst\t! int & 31-bit mask -> long\n\t"
5784 "SET $mask,$tmp\n\t"
5785 "AND $dst,$tmp,$dst" %}
5786 ins_encode %{
5787 Register Rdst = $dst$$Register;
5788 Register Rtmp = $tmp$$Register;
5789 __ lduw($mem$$Address, Rdst);
5790 __ set($mask$$constant, Rtmp);
5791 __ and3(Rdst, Rtmp, Rdst);
5792 %}
5793 ins_pipe(iload_mem);
5794 %}
5795
5796 // Load Unsigned Integer into a Long Register
5797 instruct loadUI2L(iRegL dst, memory mem, immL_32bits mask) %{
5798 match(Set dst (AndL (ConvI2L (LoadI mem)) mask));
5799 ins_cost(MEMORY_REF_COST);
5800
5801 size(4);
5802 format %{ "LDUW $mem,$dst\t! uint -> long" %}
5803 ins_encode %{
5804 __ lduw($mem$$Address, $dst$$Register);
5805 %}
5806 ins_pipe(iload_mem);
5807 %}
5808
5809 // Load Long - aligned
5810 instruct loadL(iRegL dst, memory mem ) %{
5811 match(Set dst (LoadL mem));
5812 ins_cost(MEMORY_REF_COST);
5813
5814 size(4);
5815 format %{ "LDX $mem,$dst\t! long" %}
5816 ins_encode %{
5817 __ ldx($mem$$Address, $dst$$Register);
5818 %}
5819 ins_pipe(iload_mem);
5820 %}
5821
5822 // Load Long - UNaligned
5823 instruct loadL_unaligned(iRegL dst, memory mem, o7RegI tmp) %{
5824 match(Set dst (LoadL_unaligned mem));
5825 effect(KILL tmp);
5826 ins_cost(MEMORY_REF_COST*2+DEFAULT_COST);
5827 format %{ "LDUW $mem+4,R_O7\t! misaligned long\n"
5828 "\tLDUW $mem ,$dst\n"
5829 "\tSLLX #32, $dst, $dst\n"
5830 "\tOR $dst, R_O7, $dst" %}
5831 opcode(Assembler::lduw_op3);
5832 ins_encode(form3_mem_reg_long_unaligned_marshal( mem, dst ));
5833 ins_pipe(iload_mem);
5834 %}
5835
5836 // Load Range
5837 instruct loadRange(iRegI dst, memory mem) %{
5838 match(Set dst (LoadRange mem));
5839 ins_cost(MEMORY_REF_COST);
5840
5841 format %{ "LDUW $mem,$dst\t! range" %}
5842 opcode(Assembler::lduw_op3);
5843 ins_encode(simple_form3_mem_reg( mem, dst ) );
5844 ins_pipe(iload_mem);
5845 %}
5846
5847 // Load Integer into %f register (for fitos/fitod)
5848 instruct loadI_freg(regF dst, memory mem) %{
5849 match(Set dst (LoadI mem));
5850 ins_cost(MEMORY_REF_COST);
5851
5852 format %{ "LDF $mem,$dst\t! for fitos/fitod" %}
5853 opcode(Assembler::ldf_op3);
5854 ins_encode(simple_form3_mem_reg( mem, dst ) );
5855 ins_pipe(floadF_mem);
5856 %}
5857
5858 // Load Pointer
5859 instruct loadP(iRegP dst, memory mem) %{
5860 match(Set dst (LoadP mem));
5861 ins_cost(MEMORY_REF_COST);
5862 size(4);
5863
5864 #ifndef _LP64
5865 format %{ "LDUW $mem,$dst\t! ptr" %}
5866 ins_encode %{
5867 __ lduw($mem$$Address, $dst$$Register);
5868 %}
5869 #else
5870 format %{ "LDX $mem,$dst\t! ptr" %}
5871 ins_encode %{
5872 __ ldx($mem$$Address, $dst$$Register);
5873 %}
5874 #endif
5875 ins_pipe(iload_mem);
5876 %}
5877
5878 // Load Compressed Pointer
5879 instruct loadN(iRegN dst, memory mem) %{
5880 match(Set dst (LoadN mem));
5881 ins_cost(MEMORY_REF_COST);
5882 size(4);
5883
5884 format %{ "LDUW $mem,$dst\t! compressed ptr" %}
5885 ins_encode %{
5886 __ lduw($mem$$Address, $dst$$Register);
5887 %}
5888 ins_pipe(iload_mem);
5889 %}
5890
5891 // Load Klass Pointer
5892 instruct loadKlass(iRegP dst, memory mem) %{
5893 match(Set dst (LoadKlass mem));
5894 ins_cost(MEMORY_REF_COST);
5895 size(4);
5896
5897 #ifndef _LP64
5898 format %{ "LDUW $mem,$dst\t! klass ptr" %}
5899 ins_encode %{
5900 __ lduw($mem$$Address, $dst$$Register);
5901 %}
5902 #else
5903 format %{ "LDX $mem,$dst\t! klass ptr" %}
5904 ins_encode %{
5905 __ ldx($mem$$Address, $dst$$Register);
5906 %}
5907 #endif
5908 ins_pipe(iload_mem);
5909 %}
5910
5911 // Load narrow Klass Pointer
5912 instruct loadNKlass(iRegN dst, memory mem) %{
5913 match(Set dst (LoadNKlass mem));
5914 ins_cost(MEMORY_REF_COST);
5915 size(4);
5916
5917 format %{ "LDUW $mem,$dst\t! compressed klass ptr" %}
5918 ins_encode %{
5919 __ lduw($mem$$Address, $dst$$Register);
5920 %}
5921 ins_pipe(iload_mem);
5922 %}
5923
5924 // Load Double
5925 instruct loadD(regD dst, memory mem) %{
5926 match(Set dst (LoadD mem));
5927 ins_cost(MEMORY_REF_COST);
5928
5929 format %{ "LDDF $mem,$dst" %}
5930 opcode(Assembler::lddf_op3);
5931 ins_encode(simple_form3_mem_reg( mem, dst ) );
5932 ins_pipe(floadD_mem);
5933 %}
5934
5935 // Load Double - UNaligned
5936 instruct loadD_unaligned(regD_low dst, memory mem ) %{
5937 match(Set dst (LoadD_unaligned mem));
5938 ins_cost(MEMORY_REF_COST*2+DEFAULT_COST);
5939 format %{ "LDF $mem ,$dst.hi\t! misaligned double\n"
5940 "\tLDF $mem+4,$dst.lo\t!" %}
5941 opcode(Assembler::ldf_op3);
5942 ins_encode( form3_mem_reg_double_unaligned( mem, dst ));
5943 ins_pipe(iload_mem);
5944 %}
5945
5946 // Load Float
5947 instruct loadF(regF dst, memory mem) %{
5948 match(Set dst (LoadF mem));
5949 ins_cost(MEMORY_REF_COST);
5950
5951 format %{ "LDF $mem,$dst" %}
5952 opcode(Assembler::ldf_op3);
5953 ins_encode(simple_form3_mem_reg( mem, dst ) );
5954 ins_pipe(floadF_mem);
5955 %}
5956
5957 // Load Constant
5958 instruct loadConI( iRegI dst, immI src ) %{
5959 match(Set dst src);
5960 ins_cost(DEFAULT_COST * 3/2);
5961 format %{ "SET $src,$dst" %}
5962 ins_encode( Set32(src, dst) );
5963 ins_pipe(ialu_hi_lo_reg);
5964 %}
5965
5966 instruct loadConI13( iRegI dst, immI13 src ) %{
5967 match(Set dst src);
5968
5969 size(4);
5970 format %{ "MOV $src,$dst" %}
5971 ins_encode( Set13( src, dst ) );
5972 ins_pipe(ialu_imm);
5973 %}
5974
5975 #ifndef _LP64
5976 instruct loadConP(iRegP dst, immP con) %{
5977 match(Set dst con);
5978 ins_cost(DEFAULT_COST * 3/2);
5979 format %{ "SET $con,$dst\t!ptr" %}
5980 ins_encode %{
5981 relocInfo::relocType constant_reloc = _opnds[1]->constant_reloc();
5982 intptr_t val = $con$$constant;
5983 if (constant_reloc == relocInfo::oop_type) {
5984 __ set_oop_constant((jobject) val, $dst$$Register);
5985 } else if (constant_reloc == relocInfo::metadata_type) {
5986 __ set_metadata_constant((Metadata*)val, $dst$$Register);
5987 } else { // non-oop pointers, e.g. card mark base, heap top
5988 assert(constant_reloc == relocInfo::none, "unexpected reloc type");
5989 __ set(val, $dst$$Register);
5990 }
5991 %}
5992 ins_pipe(loadConP);
5993 %}
5994 #else
5995 instruct loadConP_set(iRegP dst, immP_set con) %{
5996 match(Set dst con);
5997 ins_cost(DEFAULT_COST * 3/2);
5998 format %{ "SET $con,$dst\t! ptr" %}
5999 ins_encode %{
6000 relocInfo::relocType constant_reloc = _opnds[1]->constant_reloc();
6001 intptr_t val = $con$$constant;
6002 if (constant_reloc == relocInfo::oop_type) {
6003 __ set_oop_constant((jobject) val, $dst$$Register);
6004 } else if (constant_reloc == relocInfo::metadata_type) {
6005 __ set_metadata_constant((Metadata*)val, $dst$$Register);
6006 } else { // non-oop pointers, e.g. card mark base, heap top
6007 assert(constant_reloc == relocInfo::none, "unexpected reloc type");
6008 __ set(val, $dst$$Register);
6009 }
6010 %}
6011 ins_pipe(loadConP);
6012 %}
6013
6014 instruct loadConP_load(iRegP dst, immP_load con) %{
6015 match(Set dst con);
6016 ins_cost(MEMORY_REF_COST);
6017 format %{ "LD [$constanttablebase + $constantoffset],$dst\t! load from constant table: ptr=$con" %}
6018 ins_encode %{
6019 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $dst$$Register);
6020 __ ld_ptr($constanttablebase, con_offset, $dst$$Register);
6021 %}
6022 ins_pipe(loadConP);
6023 %}
6024
6025 instruct loadConP_no_oop_cheap(iRegP dst, immP_no_oop_cheap con) %{
6026 match(Set dst con);
6027 ins_cost(DEFAULT_COST * 3/2);
6028 format %{ "SET $con,$dst\t! non-oop ptr" %}
6029 ins_encode %{
6030 if (_opnds[1]->constant_reloc() == relocInfo::metadata_type) {
6031 __ set_metadata_constant((Metadata*)$con$$constant, $dst$$Register);
6032 } else {
6033 __ set($con$$constant, $dst$$Register);
6034 }
6035 %}
6036 ins_pipe(loadConP);
6037 %}
6038 #endif // _LP64
6039
6040 instruct loadConP0(iRegP dst, immP0 src) %{
6041 match(Set dst src);
6042
6043 size(4);
6044 format %{ "CLR $dst\t!ptr" %}
6045 ins_encode %{
6046 __ clr($dst$$Register);
6047 %}
6048 ins_pipe(ialu_imm);
6049 %}
6050
6051 instruct loadConP_poll(iRegP dst, immP_poll src) %{
6052 match(Set dst src);
6053 ins_cost(DEFAULT_COST);
6054 format %{ "SET $src,$dst\t!ptr" %}
6055 ins_encode %{
6056 AddressLiteral polling_page(os::get_polling_page());
6057 __ sethi(polling_page, reg_to_register_object($dst$$reg));
6058 %}
6059 ins_pipe(loadConP_poll);
6060 %}
6061
6062 instruct loadConN0(iRegN dst, immN0 src) %{
6063 match(Set dst src);
6064
6065 size(4);
6066 format %{ "CLR $dst\t! compressed NULL ptr" %}
6067 ins_encode %{
6068 __ clr($dst$$Register);
6069 %}
6070 ins_pipe(ialu_imm);
6071 %}
6072
6073 instruct loadConN(iRegN dst, immN src) %{
6074 match(Set dst src);
6075 ins_cost(DEFAULT_COST * 3/2);
6076 format %{ "SET $src,$dst\t! compressed ptr" %}
6077 ins_encode %{
6078 Register dst = $dst$$Register;
6079 __ set_narrow_oop((jobject)$src$$constant, dst);
6080 %}
6081 ins_pipe(ialu_hi_lo_reg);
6082 %}
6083
6084 instruct loadConNKlass(iRegN dst, immNKlass src) %{
6085 match(Set dst src);
6086 ins_cost(DEFAULT_COST * 3/2);
6087 format %{ "SET $src,$dst\t! compressed klass ptr" %}
6088 ins_encode %{
6089 Register dst = $dst$$Register;
6090 __ set_narrow_klass((Klass*)$src$$constant, dst);
6091 %}
6092 ins_pipe(ialu_hi_lo_reg);
6093 %}
6094
6095 // Materialize long value (predicated by immL_cheap).
6096 instruct loadConL_set64(iRegL dst, immL_cheap con, o7RegL tmp) %{
6097 match(Set dst con);
6098 effect(KILL tmp);
6099 ins_cost(DEFAULT_COST * 3);
6100 format %{ "SET64 $con,$dst KILL $tmp\t! cheap long" %}
6101 ins_encode %{
6102 __ set64($con$$constant, $dst$$Register, $tmp$$Register);
6103 %}
6104 ins_pipe(loadConL);
6105 %}
6106
6107 // Load long value from constant table (predicated by immL_expensive).
6108 instruct loadConL_ldx(iRegL dst, immL_expensive con) %{
6109 match(Set dst con);
6110 ins_cost(MEMORY_REF_COST);
6111 format %{ "LDX [$constanttablebase + $constantoffset],$dst\t! load from constant table: long=$con" %}
6112 ins_encode %{
6113 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $dst$$Register);
6114 __ ldx($constanttablebase, con_offset, $dst$$Register);
6115 %}
6116 ins_pipe(loadConL);
6117 %}
6118
6119 instruct loadConL0( iRegL dst, immL0 src ) %{
6120 match(Set dst src);
6121 ins_cost(DEFAULT_COST);
6122 size(4);
6123 format %{ "CLR $dst\t! long" %}
6124 ins_encode( Set13( src, dst ) );
6125 ins_pipe(ialu_imm);
6126 %}
6127
6128 instruct loadConL13( iRegL dst, immL13 src ) %{
6129 match(Set dst src);
6130 ins_cost(DEFAULT_COST * 2);
6131
6132 size(4);
6133 format %{ "MOV $src,$dst\t! long" %}
6134 ins_encode( Set13( src, dst ) );
6135 ins_pipe(ialu_imm);
6136 %}
6137
6138 instruct loadConF(regF dst, immF con, o7RegI tmp) %{
6139 match(Set dst con);
6140 effect(KILL tmp);
6141 format %{ "LDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: float=$con" %}
6142 ins_encode %{
6143 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $tmp$$Register);
6144 __ ldf(FloatRegisterImpl::S, $constanttablebase, con_offset, $dst$$FloatRegister);
6145 %}
6146 ins_pipe(loadConFD);
6147 %}
6148
6149 instruct loadConD(regD dst, immD con, o7RegI tmp) %{
6150 match(Set dst con);
6151 effect(KILL tmp);
6152 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: double=$con" %}
6153 ins_encode %{
6154 // XXX This is a quick fix for 6833573.
6155 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset($con), $dst$$FloatRegister);
6156 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $tmp$$Register);
6157 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
6158 %}
6159 ins_pipe(loadConFD);
6160 %}
6161
6162 // Prefetch instructions for allocation.
6163 // Must be safe to execute with invalid address (cannot fault).
6164
6165 instruct prefetchAlloc( memory mem ) %{
6166 predicate(AllocatePrefetchInstr == 0);
6167 match( PrefetchAllocation mem );
6168 ins_cost(MEMORY_REF_COST);
6169
6170 format %{ "PREFETCH $mem,2\t! Prefetch allocation" %}
6171 opcode(Assembler::prefetch_op3);
6172 ins_encode( form3_mem_prefetch_write( mem ) );
6173 ins_pipe(iload_mem);
6174 %}
6175
6176 // Use BIS instruction to prefetch for allocation.
6177 // Could fault, need space at the end of TLAB.
6178 instruct prefetchAlloc_bis( iRegP dst ) %{
6179 predicate(AllocatePrefetchInstr == 1);
6180 match( PrefetchAllocation dst );
6181 ins_cost(MEMORY_REF_COST);
6182 size(4);
6183
6184 format %{ "STXA [$dst]\t! // Prefetch allocation using BIS" %}
6185 ins_encode %{
6186 __ stxa(G0, $dst$$Register, G0, Assembler::ASI_ST_BLKINIT_PRIMARY);
6187 %}
6188 ins_pipe(istore_mem_reg);
6189 %}
6190
6191 // Next code is used for finding next cache line address to prefetch.
6192 #ifndef _LP64
6193 instruct cacheLineAdr( iRegP dst, iRegP src, immI13 mask ) %{
6194 match(Set dst (CastX2P (AndI (CastP2X src) mask)));
6195 ins_cost(DEFAULT_COST);
6196 size(4);
6197
6198 format %{ "AND $src,$mask,$dst\t! next cache line address" %}
6199 ins_encode %{
6200 __ and3($src$$Register, $mask$$constant, $dst$$Register);
6201 %}
6202 ins_pipe(ialu_reg_imm);
6203 %}
6204 #else
6205 instruct cacheLineAdr( iRegP dst, iRegP src, immL13 mask ) %{
6206 match(Set dst (CastX2P (AndL (CastP2X src) mask)));
6207 ins_cost(DEFAULT_COST);
6208 size(4);
6209
6210 format %{ "AND $src,$mask,$dst\t! next cache line address" %}
6211 ins_encode %{
6212 __ and3($src$$Register, $mask$$constant, $dst$$Register);
6213 %}
6214 ins_pipe(ialu_reg_imm);
6215 %}
6216 #endif
6217
6218 //----------Store Instructions-------------------------------------------------
6219 // Store Byte
6220 instruct storeB(memory mem, iRegI src) %{
6221 match(Set mem (StoreB mem src));
6222 ins_cost(MEMORY_REF_COST);
6223
6224 format %{ "STB $src,$mem\t! byte" %}
6225 opcode(Assembler::stb_op3);
6226 ins_encode(simple_form3_mem_reg( mem, src ) );
6227 ins_pipe(istore_mem_reg);
6228 %}
6229
6230 instruct storeB0(memory mem, immI0 src) %{
6231 match(Set mem (StoreB mem src));
6232 ins_cost(MEMORY_REF_COST);
6233
6234 format %{ "STB $src,$mem\t! byte" %}
6235 opcode(Assembler::stb_op3);
6236 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6237 ins_pipe(istore_mem_zero);
6238 %}
6239
6240 instruct storeCM0(memory mem, immI0 src) %{
6241 match(Set mem (StoreCM mem src));
6242 ins_cost(MEMORY_REF_COST);
6243
6244 format %{ "STB $src,$mem\t! CMS card-mark byte 0" %}
6245 opcode(Assembler::stb_op3);
6246 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6247 ins_pipe(istore_mem_zero);
6248 %}
6249
6250 // Store Char/Short
6251 instruct storeC(memory mem, iRegI src) %{
6252 match(Set mem (StoreC mem src));
6253 ins_cost(MEMORY_REF_COST);
6254
6255 format %{ "STH $src,$mem\t! short" %}
6256 opcode(Assembler::sth_op3);
6257 ins_encode(simple_form3_mem_reg( mem, src ) );
6258 ins_pipe(istore_mem_reg);
6259 %}
6260
6261 instruct storeC0(memory mem, immI0 src) %{
6262 match(Set mem (StoreC mem src));
6263 ins_cost(MEMORY_REF_COST);
6264
6265 format %{ "STH $src,$mem\t! short" %}
6266 opcode(Assembler::sth_op3);
6267 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6268 ins_pipe(istore_mem_zero);
6269 %}
6270
6271 // Store Integer
6272 instruct storeI(memory mem, iRegI src) %{
6273 match(Set mem (StoreI mem src));
6274 ins_cost(MEMORY_REF_COST);
6275
6276 format %{ "STW $src,$mem" %}
6277 opcode(Assembler::stw_op3);
6278 ins_encode(simple_form3_mem_reg( mem, src ) );
6279 ins_pipe(istore_mem_reg);
6280 %}
6281
6282 // Store Long
6283 instruct storeL(memory mem, iRegL src) %{
6284 match(Set mem (StoreL mem src));
6285 ins_cost(MEMORY_REF_COST);
6286 format %{ "STX $src,$mem\t! long" %}
6287 opcode(Assembler::stx_op3);
6288 ins_encode(simple_form3_mem_reg( mem, src ) );
6289 ins_pipe(istore_mem_reg);
6290 %}
6291
6292 instruct storeI0(memory mem, immI0 src) %{
6293 match(Set mem (StoreI mem src));
6294 ins_cost(MEMORY_REF_COST);
6295
6296 format %{ "STW $src,$mem" %}
6297 opcode(Assembler::stw_op3);
6298 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6299 ins_pipe(istore_mem_zero);
6300 %}
6301
6302 instruct storeL0(memory mem, immL0 src) %{
6303 match(Set mem (StoreL mem src));
6304 ins_cost(MEMORY_REF_COST);
6305
6306 format %{ "STX $src,$mem" %}
6307 opcode(Assembler::stx_op3);
6308 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6309 ins_pipe(istore_mem_zero);
6310 %}
6311
6312 // Store Integer from float register (used after fstoi)
6313 instruct storeI_Freg(memory mem, regF src) %{
6314 match(Set mem (StoreI mem src));
6315 ins_cost(MEMORY_REF_COST);
6316
6317 format %{ "STF $src,$mem\t! after fstoi/fdtoi" %}
6318 opcode(Assembler::stf_op3);
6319 ins_encode(simple_form3_mem_reg( mem, src ) );
6320 ins_pipe(fstoreF_mem_reg);
6321 %}
6322
6323 // Store Pointer
6324 instruct storeP(memory dst, sp_ptr_RegP src) %{
6325 match(Set dst (StoreP dst src));
6326 ins_cost(MEMORY_REF_COST);
6327
6328 #ifndef _LP64
6329 format %{ "STW $src,$dst\t! ptr" %}
6330 opcode(Assembler::stw_op3, 0, REGP_OP);
6331 #else
6332 format %{ "STX $src,$dst\t! ptr" %}
6333 opcode(Assembler::stx_op3, 0, REGP_OP);
6334 #endif
6335 ins_encode( form3_mem_reg( dst, src ) );
6336 ins_pipe(istore_mem_spORreg);
6337 %}
6338
6339 instruct storeP0(memory dst, immP0 src) %{
6340 match(Set dst (StoreP dst src));
6341 ins_cost(MEMORY_REF_COST);
6342
6343 #ifndef _LP64
6344 format %{ "STW $src,$dst\t! ptr" %}
6345 opcode(Assembler::stw_op3, 0, REGP_OP);
6346 #else
6347 format %{ "STX $src,$dst\t! ptr" %}
6348 opcode(Assembler::stx_op3, 0, REGP_OP);
6349 #endif
6350 ins_encode( form3_mem_reg( dst, R_G0 ) );
6351 ins_pipe(istore_mem_zero);
6352 %}
6353
6354 // Store Compressed Pointer
6355 instruct storeN(memory dst, iRegN src) %{
6356 match(Set dst (StoreN dst src));
6357 ins_cost(MEMORY_REF_COST);
6358 size(4);
6359
6360 format %{ "STW $src,$dst\t! compressed ptr" %}
6361 ins_encode %{
6362 Register base = as_Register($dst$$base);
6363 Register index = as_Register($dst$$index);
6364 Register src = $src$$Register;
6365 if (index != G0) {
6366 __ stw(src, base, index);
6367 } else {
6368 __ stw(src, base, $dst$$disp);
6369 }
6370 %}
6371 ins_pipe(istore_mem_spORreg);
6372 %}
6373
6374 instruct storeNKlass(memory dst, iRegN src) %{
6375 match(Set dst (StoreNKlass dst src));
6376 ins_cost(MEMORY_REF_COST);
6377 size(4);
6378
6379 format %{ "STW $src,$dst\t! compressed klass ptr" %}
6380 ins_encode %{
6381 Register base = as_Register($dst$$base);
6382 Register index = as_Register($dst$$index);
6383 Register src = $src$$Register;
6384 if (index != G0) {
6385 __ stw(src, base, index);
6386 } else {
6387 __ stw(src, base, $dst$$disp);
6388 }
6389 %}
6390 ins_pipe(istore_mem_spORreg);
6391 %}
6392
6393 instruct storeN0(memory dst, immN0 src) %{
6394 match(Set dst (StoreN dst src));
6395 ins_cost(MEMORY_REF_COST);
6396 size(4);
6397
6398 format %{ "STW $src,$dst\t! compressed ptr" %}
6399 ins_encode %{
6400 Register base = as_Register($dst$$base);
6401 Register index = as_Register($dst$$index);
6402 if (index != G0) {
6403 __ stw(0, base, index);
6404 } else {
6405 __ stw(0, base, $dst$$disp);
6406 }
6407 %}
6408 ins_pipe(istore_mem_zero);
6409 %}
6410
6411 // Store Double
6412 instruct storeD( memory mem, regD src) %{
6413 match(Set mem (StoreD mem src));
6414 ins_cost(MEMORY_REF_COST);
6415
6416 format %{ "STDF $src,$mem" %}
6417 opcode(Assembler::stdf_op3);
6418 ins_encode(simple_form3_mem_reg( mem, src ) );
6419 ins_pipe(fstoreD_mem_reg);
6420 %}
6421
6422 instruct storeD0( memory mem, immD0 src) %{
6423 match(Set mem (StoreD mem src));
6424 ins_cost(MEMORY_REF_COST);
6425
6426 format %{ "STX $src,$mem" %}
6427 opcode(Assembler::stx_op3);
6428 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6429 ins_pipe(fstoreD_mem_zero);
6430 %}
6431
6432 // Store Float
6433 instruct storeF( memory mem, regF src) %{
6434 match(Set mem (StoreF mem src));
6435 ins_cost(MEMORY_REF_COST);
6436
6437 format %{ "STF $src,$mem" %}
6438 opcode(Assembler::stf_op3);
6439 ins_encode(simple_form3_mem_reg( mem, src ) );
6440 ins_pipe(fstoreF_mem_reg);
6441 %}
6442
6443 instruct storeF0( memory mem, immF0 src) %{
6444 match(Set mem (StoreF mem src));
6445 ins_cost(MEMORY_REF_COST);
6446
6447 format %{ "STW $src,$mem\t! storeF0" %}
6448 opcode(Assembler::stw_op3);
6449 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6450 ins_pipe(fstoreF_mem_zero);
6451 %}
6452
6453 // Convert oop pointer into compressed form
6454 instruct encodeHeapOop(iRegN dst, iRegP src) %{
6455 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull);
6456 match(Set dst (EncodeP src));
6457 format %{ "encode_heap_oop $src, $dst" %}
6458 ins_encode %{
6459 __ encode_heap_oop($src$$Register, $dst$$Register);
6460 %}
6461 ins_avoid_back_to_back(Universe::narrow_oop_base() == NULL ? AVOID_NONE : AVOID_BEFORE);
6462 ins_pipe(ialu_reg);
6463 %}
6464
6465 instruct encodeHeapOop_not_null(iRegN dst, iRegP src) %{
6466 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull);
6467 match(Set dst (EncodeP src));
6468 format %{ "encode_heap_oop_not_null $src, $dst" %}
6469 ins_encode %{
6470 __ encode_heap_oop_not_null($src$$Register, $dst$$Register);
6471 %}
6472 ins_pipe(ialu_reg);
6473 %}
6474
6475 instruct decodeHeapOop(iRegP dst, iRegN src) %{
6476 predicate(n->bottom_type()->is_oopptr()->ptr() != TypePtr::NotNull &&
6477 n->bottom_type()->is_oopptr()->ptr() != TypePtr::Constant);
6478 match(Set dst (DecodeN src));
6479 format %{ "decode_heap_oop $src, $dst" %}
6480 ins_encode %{
6481 __ decode_heap_oop($src$$Register, $dst$$Register);
6482 %}
6483 ins_pipe(ialu_reg);
6484 %}
6485
6486 instruct decodeHeapOop_not_null(iRegP dst, iRegN src) %{
6487 predicate(n->bottom_type()->is_oopptr()->ptr() == TypePtr::NotNull ||
6488 n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant);
6489 match(Set dst (DecodeN src));
6490 format %{ "decode_heap_oop_not_null $src, $dst" %}
6491 ins_encode %{
6492 __ decode_heap_oop_not_null($src$$Register, $dst$$Register);
6493 %}
6494 ins_pipe(ialu_reg);
6495 %}
6496
6497 instruct encodeKlass_not_null(iRegN dst, iRegP src) %{
6498 match(Set dst (EncodePKlass src));
6499 format %{ "encode_klass_not_null $src, $dst" %}
6500 ins_encode %{
6501 __ encode_klass_not_null($src$$Register, $dst$$Register);
6502 %}
6503 ins_pipe(ialu_reg);
6504 %}
6505
6506 instruct decodeKlass_not_null(iRegP dst, iRegN src) %{
6507 match(Set dst (DecodeNKlass src));
6508 format %{ "decode_klass_not_null $src, $dst" %}
6509 ins_encode %{
6510 __ decode_klass_not_null($src$$Register, $dst$$Register);
6511 %}
6512 ins_pipe(ialu_reg);
6513 %}
6514
6515 //----------MemBar Instructions-----------------------------------------------
6516 // Memory barrier flavors
6517
6518 instruct membar_acquire() %{
6519 match(MemBarAcquire);
6520 match(LoadFence);
6521 ins_cost(4*MEMORY_REF_COST);
6522
6523 size(0);
6524 format %{ "MEMBAR-acquire" %}
6525 ins_encode( enc_membar_acquire );
6526 ins_pipe(long_memory_op);
6527 %}
6528
6529 instruct membar_acquire_lock() %{
6530 match(MemBarAcquireLock);
6531 ins_cost(0);
6532
6533 size(0);
6534 format %{ "!MEMBAR-acquire (CAS in prior FastLock so empty encoding)" %}
6535 ins_encode( );
6536 ins_pipe(empty);
6537 %}
6538
6539 instruct membar_release() %{
6540 match(MemBarRelease);
6541 match(StoreFence);
6542 ins_cost(4*MEMORY_REF_COST);
6543
6544 size(0);
6545 format %{ "MEMBAR-release" %}
6546 ins_encode( enc_membar_release );
6547 ins_pipe(long_memory_op);
6548 %}
6549
6550 instruct membar_release_lock() %{
6551 match(MemBarReleaseLock);
6552 ins_cost(0);
6553
6554 size(0);
6555 format %{ "!MEMBAR-release (CAS in succeeding FastUnlock so empty encoding)" %}
6556 ins_encode( );
6557 ins_pipe(empty);
6558 %}
6559
6560 instruct membar_volatile() %{
6561 match(MemBarVolatile);
6562 ins_cost(4*MEMORY_REF_COST);
6563
6564 size(4);
6565 format %{ "MEMBAR-volatile" %}
6566 ins_encode( enc_membar_volatile );
6567 ins_pipe(long_memory_op);
6568 %}
6569
6570 instruct unnecessary_membar_volatile() %{
6571 match(MemBarVolatile);
6572 predicate(Matcher::post_store_load_barrier(n));
6573 ins_cost(0);
6574
6575 size(0);
6576 format %{ "!MEMBAR-volatile (unnecessary so empty encoding)" %}
6577 ins_encode( );
6578 ins_pipe(empty);
6579 %}
6580
6581 instruct membar_storestore() %{
6582 match(MemBarStoreStore);
6583 ins_cost(0);
6584
6585 size(0);
6586 format %{ "!MEMBAR-storestore (empty encoding)" %}
6587 ins_encode( );
6588 ins_pipe(empty);
6589 %}
6590
6591 //----------Register Move Instructions-----------------------------------------
6592 instruct roundDouble_nop(regD dst) %{
6593 match(Set dst (RoundDouble dst));
6594 ins_cost(0);
6595 // SPARC results are already "rounded" (i.e., normal-format IEEE)
6596 ins_encode( );
6597 ins_pipe(empty);
6598 %}
6599
6600
6601 instruct roundFloat_nop(regF dst) %{
6602 match(Set dst (RoundFloat dst));
6603 ins_cost(0);
6604 // SPARC results are already "rounded" (i.e., normal-format IEEE)
6605 ins_encode( );
6606 ins_pipe(empty);
6607 %}
6608
6609
6610 // Cast Index to Pointer for unsafe natives
6611 instruct castX2P(iRegX src, iRegP dst) %{
6612 match(Set dst (CastX2P src));
6613
6614 format %{ "MOV $src,$dst\t! IntX->Ptr" %}
6615 ins_encode( form3_g0_rs2_rd_move( src, dst ) );
6616 ins_pipe(ialu_reg);
6617 %}
6618
6619 // Cast Pointer to Index for unsafe natives
6620 instruct castP2X(iRegP src, iRegX dst) %{
6621 match(Set dst (CastP2X src));
6622
6623 format %{ "MOV $src,$dst\t! Ptr->IntX" %}
6624 ins_encode( form3_g0_rs2_rd_move( src, dst ) );
6625 ins_pipe(ialu_reg);
6626 %}
6627
6628 instruct stfSSD(stackSlotD stkSlot, regD src) %{
6629 // %%%% TO DO: Tell the coalescer that this kind of node is a copy!
6630 match(Set stkSlot src); // chain rule
6631 ins_cost(MEMORY_REF_COST);
6632 format %{ "STDF $src,$stkSlot\t!stk" %}
6633 opcode(Assembler::stdf_op3);
6634 ins_encode(simple_form3_mem_reg(stkSlot, src));
6635 ins_pipe(fstoreD_stk_reg);
6636 %}
6637
6638 instruct ldfSSD(regD dst, stackSlotD stkSlot) %{
6639 // %%%% TO DO: Tell the coalescer that this kind of node is a copy!
6640 match(Set dst stkSlot); // chain rule
6641 ins_cost(MEMORY_REF_COST);
6642 format %{ "LDDF $stkSlot,$dst\t!stk" %}
6643 opcode(Assembler::lddf_op3);
6644 ins_encode(simple_form3_mem_reg(stkSlot, dst));
6645 ins_pipe(floadD_stk);
6646 %}
6647
6648 instruct stfSSF(stackSlotF stkSlot, regF src) %{
6649 // %%%% TO DO: Tell the coalescer that this kind of node is a copy!
6650 match(Set stkSlot src); // chain rule
6651 ins_cost(MEMORY_REF_COST);
6652 format %{ "STF $src,$stkSlot\t!stk" %}
6653 opcode(Assembler::stf_op3);
6654 ins_encode(simple_form3_mem_reg(stkSlot, src));
6655 ins_pipe(fstoreF_stk_reg);
6656 %}
6657
6658 //----------Conditional Move---------------------------------------------------
6659 // Conditional move
6660 instruct cmovIP_reg(cmpOpP cmp, flagsRegP pcc, iRegI dst, iRegI src) %{
6661 match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src)));
6662 ins_cost(150);
6663 format %{ "MOV$cmp $pcc,$src,$dst" %}
6664 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6665 ins_pipe(ialu_reg);
6666 %}
6667
6668 instruct cmovIP_imm(cmpOpP cmp, flagsRegP pcc, iRegI dst, immI11 src) %{
6669 match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src)));
6670 ins_cost(140);
6671 format %{ "MOV$cmp $pcc,$src,$dst" %}
6672 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) );
6673 ins_pipe(ialu_imm);
6674 %}
6675
6676 instruct cmovII_reg(cmpOp cmp, flagsReg icc, iRegI dst, iRegI src) %{
6677 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6678 ins_cost(150);
6679 size(4);
6680 format %{ "MOV$cmp $icc,$src,$dst" %}
6681 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6682 ins_pipe(ialu_reg);
6683 %}
6684
6685 instruct cmovII_imm(cmpOp cmp, flagsReg icc, iRegI dst, immI11 src) %{
6686 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6687 ins_cost(140);
6688 size(4);
6689 format %{ "MOV$cmp $icc,$src,$dst" %}
6690 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6691 ins_pipe(ialu_imm);
6692 %}
6693
6694 instruct cmovIIu_reg(cmpOpU cmp, flagsRegU icc, iRegI dst, iRegI src) %{
6695 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6696 ins_cost(150);
6697 size(4);
6698 format %{ "MOV$cmp $icc,$src,$dst" %}
6699 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6700 ins_pipe(ialu_reg);
6701 %}
6702
6703 instruct cmovIIu_imm(cmpOpU cmp, flagsRegU icc, iRegI dst, immI11 src) %{
6704 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6705 ins_cost(140);
6706 size(4);
6707 format %{ "MOV$cmp $icc,$src,$dst" %}
6708 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6709 ins_pipe(ialu_imm);
6710 %}
6711
6712 instruct cmovIF_reg(cmpOpF cmp, flagsRegF fcc, iRegI dst, iRegI src) %{
6713 match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src)));
6714 ins_cost(150);
6715 size(4);
6716 format %{ "MOV$cmp $fcc,$src,$dst" %}
6717 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6718 ins_pipe(ialu_reg);
6719 %}
6720
6721 instruct cmovIF_imm(cmpOpF cmp, flagsRegF fcc, iRegI dst, immI11 src) %{
6722 match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src)));
6723 ins_cost(140);
6724 size(4);
6725 format %{ "MOV$cmp $fcc,$src,$dst" %}
6726 ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) );
6727 ins_pipe(ialu_imm);
6728 %}
6729
6730 // Conditional move for RegN. Only cmov(reg,reg).
6731 instruct cmovNP_reg(cmpOpP cmp, flagsRegP pcc, iRegN dst, iRegN src) %{
6732 match(Set dst (CMoveN (Binary cmp pcc) (Binary dst src)));
6733 ins_cost(150);
6734 format %{ "MOV$cmp $pcc,$src,$dst" %}
6735 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6736 ins_pipe(ialu_reg);
6737 %}
6738
6739 // This instruction also works with CmpN so we don't need cmovNN_reg.
6740 instruct cmovNI_reg(cmpOp cmp, flagsReg icc, iRegN dst, iRegN src) %{
6741 match(Set dst (CMoveN (Binary cmp icc) (Binary dst src)));
6742 ins_cost(150);
6743 size(4);
6744 format %{ "MOV$cmp $icc,$src,$dst" %}
6745 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6746 ins_pipe(ialu_reg);
6747 %}
6748
6749 // This instruction also works with CmpN so we don't need cmovNN_reg.
6750 instruct cmovNIu_reg(cmpOpU cmp, flagsRegU icc, iRegN dst, iRegN src) %{
6751 match(Set dst (CMoveN (Binary cmp icc) (Binary dst src)));
6752 ins_cost(150);
6753 size(4);
6754 format %{ "MOV$cmp $icc,$src,$dst" %}
6755 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6756 ins_pipe(ialu_reg);
6757 %}
6758
6759 instruct cmovNF_reg(cmpOpF cmp, flagsRegF fcc, iRegN dst, iRegN src) %{
6760 match(Set dst (CMoveN (Binary cmp fcc) (Binary dst src)));
6761 ins_cost(150);
6762 size(4);
6763 format %{ "MOV$cmp $fcc,$src,$dst" %}
6764 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6765 ins_pipe(ialu_reg);
6766 %}
6767
6768 // Conditional move
6769 instruct cmovPP_reg(cmpOpP cmp, flagsRegP pcc, iRegP dst, iRegP src) %{
6770 match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src)));
6771 ins_cost(150);
6772 format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %}
6773 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6774 ins_pipe(ialu_reg);
6775 %}
6776
6777 instruct cmovPP_imm(cmpOpP cmp, flagsRegP pcc, iRegP dst, immP0 src) %{
6778 match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src)));
6779 ins_cost(140);
6780 format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %}
6781 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) );
6782 ins_pipe(ialu_imm);
6783 %}
6784
6785 // This instruction also works with CmpN so we don't need cmovPN_reg.
6786 instruct cmovPI_reg(cmpOp cmp, flagsReg icc, iRegP dst, iRegP src) %{
6787 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6788 ins_cost(150);
6789
6790 size(4);
6791 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %}
6792 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6793 ins_pipe(ialu_reg);
6794 %}
6795
6796 instruct cmovPIu_reg(cmpOpU cmp, flagsRegU icc, iRegP dst, iRegP src) %{
6797 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6798 ins_cost(150);
6799
6800 size(4);
6801 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %}
6802 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6803 ins_pipe(ialu_reg);
6804 %}
6805
6806 instruct cmovPI_imm(cmpOp cmp, flagsReg icc, iRegP dst, immP0 src) %{
6807 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6808 ins_cost(140);
6809
6810 size(4);
6811 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %}
6812 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6813 ins_pipe(ialu_imm);
6814 %}
6815
6816 instruct cmovPIu_imm(cmpOpU cmp, flagsRegU icc, iRegP dst, immP0 src) %{
6817 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6818 ins_cost(140);
6819
6820 size(4);
6821 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %}
6822 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6823 ins_pipe(ialu_imm);
6824 %}
6825
6826 instruct cmovPF_reg(cmpOpF cmp, flagsRegF fcc, iRegP dst, iRegP src) %{
6827 match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src)));
6828 ins_cost(150);
6829 size(4);
6830 format %{ "MOV$cmp $fcc,$src,$dst" %}
6831 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6832 ins_pipe(ialu_imm);
6833 %}
6834
6835 instruct cmovPF_imm(cmpOpF cmp, flagsRegF fcc, iRegP dst, immP0 src) %{
6836 match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src)));
6837 ins_cost(140);
6838 size(4);
6839 format %{ "MOV$cmp $fcc,$src,$dst" %}
6840 ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) );
6841 ins_pipe(ialu_imm);
6842 %}
6843
6844 // Conditional move
6845 instruct cmovFP_reg(cmpOpP cmp, flagsRegP pcc, regF dst, regF src) %{
6846 match(Set dst (CMoveF (Binary cmp pcc) (Binary dst src)));
6847 ins_cost(150);
6848 opcode(0x101);
6849 format %{ "FMOVD$cmp $pcc,$src,$dst" %}
6850 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6851 ins_pipe(int_conditional_float_move);
6852 %}
6853
6854 instruct cmovFI_reg(cmpOp cmp, flagsReg icc, regF dst, regF src) %{
6855 match(Set dst (CMoveF (Binary cmp icc) (Binary dst src)));
6856 ins_cost(150);
6857
6858 size(4);
6859 format %{ "FMOVS$cmp $icc,$src,$dst" %}
6860 opcode(0x101);
6861 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
6862 ins_pipe(int_conditional_float_move);
6863 %}
6864
6865 instruct cmovFIu_reg(cmpOpU cmp, flagsRegU icc, regF dst, regF src) %{
6866 match(Set dst (CMoveF (Binary cmp icc) (Binary dst src)));
6867 ins_cost(150);
6868
6869 size(4);
6870 format %{ "FMOVS$cmp $icc,$src,$dst" %}
6871 opcode(0x101);
6872 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
6873 ins_pipe(int_conditional_float_move);
6874 %}
6875
6876 // Conditional move,
6877 instruct cmovFF_reg(cmpOpF cmp, flagsRegF fcc, regF dst, regF src) %{
6878 match(Set dst (CMoveF (Binary cmp fcc) (Binary dst src)));
6879 ins_cost(150);
6880 size(4);
6881 format %{ "FMOVF$cmp $fcc,$src,$dst" %}
6882 opcode(0x1);
6883 ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) );
6884 ins_pipe(int_conditional_double_move);
6885 %}
6886
6887 // Conditional move
6888 instruct cmovDP_reg(cmpOpP cmp, flagsRegP pcc, regD dst, regD src) %{
6889 match(Set dst (CMoveD (Binary cmp pcc) (Binary dst src)));
6890 ins_cost(150);
6891 size(4);
6892 opcode(0x102);
6893 format %{ "FMOVD$cmp $pcc,$src,$dst" %}
6894 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6895 ins_pipe(int_conditional_double_move);
6896 %}
6897
6898 instruct cmovDI_reg(cmpOp cmp, flagsReg icc, regD dst, regD src) %{
6899 match(Set dst (CMoveD (Binary cmp icc) (Binary dst src)));
6900 ins_cost(150);
6901
6902 size(4);
6903 format %{ "FMOVD$cmp $icc,$src,$dst" %}
6904 opcode(0x102);
6905 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
6906 ins_pipe(int_conditional_double_move);
6907 %}
6908
6909 instruct cmovDIu_reg(cmpOpU cmp, flagsRegU icc, regD dst, regD src) %{
6910 match(Set dst (CMoveD (Binary cmp icc) (Binary dst src)));
6911 ins_cost(150);
6912
6913 size(4);
6914 format %{ "FMOVD$cmp $icc,$src,$dst" %}
6915 opcode(0x102);
6916 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
6917 ins_pipe(int_conditional_double_move);
6918 %}
6919
6920 // Conditional move,
6921 instruct cmovDF_reg(cmpOpF cmp, flagsRegF fcc, regD dst, regD src) %{
6922 match(Set dst (CMoveD (Binary cmp fcc) (Binary dst src)));
6923 ins_cost(150);
6924 size(4);
6925 format %{ "FMOVD$cmp $fcc,$src,$dst" %}
6926 opcode(0x2);
6927 ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) );
6928 ins_pipe(int_conditional_double_move);
6929 %}
6930
6931 // Conditional move
6932 instruct cmovLP_reg(cmpOpP cmp, flagsRegP pcc, iRegL dst, iRegL src) %{
6933 match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src)));
6934 ins_cost(150);
6935 format %{ "MOV$cmp $pcc,$src,$dst\t! long" %}
6936 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6937 ins_pipe(ialu_reg);
6938 %}
6939
6940 instruct cmovLP_imm(cmpOpP cmp, flagsRegP pcc, iRegL dst, immI11 src) %{
6941 match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src)));
6942 ins_cost(140);
6943 format %{ "MOV$cmp $pcc,$src,$dst\t! long" %}
6944 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) );
6945 ins_pipe(ialu_imm);
6946 %}
6947
6948 instruct cmovLI_reg(cmpOp cmp, flagsReg icc, iRegL dst, iRegL src) %{
6949 match(Set dst (CMoveL (Binary cmp icc) (Binary dst src)));
6950 ins_cost(150);
6951
6952 size(4);
6953 format %{ "MOV$cmp $icc,$src,$dst\t! long" %}
6954 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6955 ins_pipe(ialu_reg);
6956 %}
6957
6958
6959 instruct cmovLIu_reg(cmpOpU cmp, flagsRegU icc, iRegL dst, iRegL src) %{
6960 match(Set dst (CMoveL (Binary cmp icc) (Binary dst src)));
6961 ins_cost(150);
6962
6963 size(4);
6964 format %{ "MOV$cmp $icc,$src,$dst\t! long" %}
6965 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6966 ins_pipe(ialu_reg);
6967 %}
6968
6969
6970 instruct cmovLF_reg(cmpOpF cmp, flagsRegF fcc, iRegL dst, iRegL src) %{
6971 match(Set dst (CMoveL (Binary cmp fcc) (Binary dst src)));
6972 ins_cost(150);
6973
6974 size(4);
6975 format %{ "MOV$cmp $fcc,$src,$dst\t! long" %}
6976 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6977 ins_pipe(ialu_reg);
6978 %}
6979
6980
6981
6982 //----------OS and Locking Instructions----------------------------------------
6983
6984 // This name is KNOWN by the ADLC and cannot be changed.
6985 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type
6986 // for this guy.
6987 instruct tlsLoadP(g2RegP dst) %{
6988 match(Set dst (ThreadLocal));
6989
6990 size(0);
6991 ins_cost(0);
6992 format %{ "# TLS is in G2" %}
6993 ins_encode( /*empty encoding*/ );
6994 ins_pipe(ialu_none);
6995 %}
6996
6997 instruct checkCastPP( iRegP dst ) %{
6998 match(Set dst (CheckCastPP dst));
6999
7000 size(0);
7001 format %{ "# checkcastPP of $dst" %}
7002 ins_encode( /*empty encoding*/ );
7003 ins_pipe(empty);
7004 %}
7005
7006
7007 instruct castPP( iRegP dst ) %{
7008 match(Set dst (CastPP dst));
7009 format %{ "# castPP of $dst" %}
7010 ins_encode( /*empty encoding*/ );
7011 ins_pipe(empty);
7012 %}
7013
7014 instruct castII( iRegI dst ) %{
7015 match(Set dst (CastII dst));
7016 format %{ "# castII of $dst" %}
7017 ins_encode( /*empty encoding*/ );
7018 ins_cost(0);
7019 ins_pipe(empty);
7020 %}
7021
7022 //----------Arithmetic Instructions--------------------------------------------
7023 // Addition Instructions
7024 // Register Addition
7025 instruct addI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7026 match(Set dst (AddI src1 src2));
7027
7028 size(4);
7029 format %{ "ADD $src1,$src2,$dst" %}
7030 ins_encode %{
7031 __ add($src1$$Register, $src2$$Register, $dst$$Register);
7032 %}
7033 ins_pipe(ialu_reg_reg);
7034 %}
7035
7036 // Immediate Addition
7037 instruct addI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7038 match(Set dst (AddI src1 src2));
7039
7040 size(4);
7041 format %{ "ADD $src1,$src2,$dst" %}
7042 opcode(Assembler::add_op3, Assembler::arith_op);
7043 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7044 ins_pipe(ialu_reg_imm);
7045 %}
7046
7047 // Pointer Register Addition
7048 instruct addP_reg_reg(iRegP dst, iRegP src1, iRegX src2) %{
7049 match(Set dst (AddP src1 src2));
7050
7051 size(4);
7052 format %{ "ADD $src1,$src2,$dst" %}
7053 opcode(Assembler::add_op3, Assembler::arith_op);
7054 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7055 ins_pipe(ialu_reg_reg);
7056 %}
7057
7058 // Pointer Immediate Addition
7059 instruct addP_reg_imm13(iRegP dst, iRegP src1, immX13 src2) %{
7060 match(Set dst (AddP src1 src2));
7061
7062 size(4);
7063 format %{ "ADD $src1,$src2,$dst" %}
7064 opcode(Assembler::add_op3, Assembler::arith_op);
7065 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7066 ins_pipe(ialu_reg_imm);
7067 %}
7068
7069 // Long Addition
7070 instruct addL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7071 match(Set dst (AddL src1 src2));
7072
7073 size(4);
7074 format %{ "ADD $src1,$src2,$dst\t! long" %}
7075 opcode(Assembler::add_op3, Assembler::arith_op);
7076 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7077 ins_pipe(ialu_reg_reg);
7078 %}
7079
7080 instruct addL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
7081 match(Set dst (AddL src1 con));
7082
7083 size(4);
7084 format %{ "ADD $src1,$con,$dst" %}
7085 opcode(Assembler::add_op3, Assembler::arith_op);
7086 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
7087 ins_pipe(ialu_reg_imm);
7088 %}
7089
7090 //----------Conditional_store--------------------------------------------------
7091 // Conditional-store of the updated heap-top.
7092 // Used during allocation of the shared heap.
7093 // Sets flags (EQ) on success. Implemented with a CASA on Sparc.
7094
7095 // LoadP-locked. Same as a regular pointer load when used with a compare-swap
7096 instruct loadPLocked(iRegP dst, memory mem) %{
7097 match(Set dst (LoadPLocked mem));
7098 ins_cost(MEMORY_REF_COST);
7099
7100 #ifndef _LP64
7101 format %{ "LDUW $mem,$dst\t! ptr" %}
7102 opcode(Assembler::lduw_op3, 0, REGP_OP);
7103 #else
7104 format %{ "LDX $mem,$dst\t! ptr" %}
7105 opcode(Assembler::ldx_op3, 0, REGP_OP);
7106 #endif
7107 ins_encode( form3_mem_reg( mem, dst ) );
7108 ins_pipe(iload_mem);
7109 %}
7110
7111 instruct storePConditional( iRegP heap_top_ptr, iRegP oldval, g3RegP newval, flagsRegP pcc ) %{
7112 match(Set pcc (StorePConditional heap_top_ptr (Binary oldval newval)));
7113 effect( KILL newval );
7114 format %{ "CASA [$heap_top_ptr],$oldval,R_G3\t! If $oldval==[$heap_top_ptr] Then store R_G3 into [$heap_top_ptr], set R_G3=[$heap_top_ptr] in any case\n\t"
7115 "CMP R_G3,$oldval\t\t! See if we made progress" %}
7116 ins_encode( enc_cas(heap_top_ptr,oldval,newval) );
7117 ins_pipe( long_memory_op );
7118 %}
7119
7120 // Conditional-store of an int value.
7121 instruct storeIConditional( iRegP mem_ptr, iRegI oldval, g3RegI newval, flagsReg icc ) %{
7122 match(Set icc (StoreIConditional mem_ptr (Binary oldval newval)));
7123 effect( KILL newval );
7124 format %{ "CASA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr], set $newval=[$mem_ptr] in any case\n\t"
7125 "CMP $oldval,$newval\t\t! See if we made progress" %}
7126 ins_encode( enc_cas(mem_ptr,oldval,newval) );
7127 ins_pipe( long_memory_op );
7128 %}
7129
7130 // Conditional-store of a long value.
7131 instruct storeLConditional( iRegP mem_ptr, iRegL oldval, g3RegL newval, flagsRegL xcc ) %{
7132 match(Set xcc (StoreLConditional mem_ptr (Binary oldval newval)));
7133 effect( KILL newval );
7134 format %{ "CASXA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr], set $newval=[$mem_ptr] in any case\n\t"
7135 "CMP $oldval,$newval\t\t! See if we made progress" %}
7136 ins_encode( enc_cas(mem_ptr,oldval,newval) );
7137 ins_pipe( long_memory_op );
7138 %}
7139
7140 // No flag versions for CompareAndSwap{P,I,L} because matcher can't match them
7141
7142 instruct compareAndSwapL_bool(iRegP mem_ptr, iRegL oldval, iRegL newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
7143 predicate(VM_Version::supports_cx8());
7144 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval)));
7145 match(Set res (WeakCompareAndSwapL mem_ptr (Binary oldval newval)));
7146 effect( USE mem_ptr, KILL ccr, KILL tmp1);
7147 format %{
7148 "MOV $newval,O7\n\t"
7149 "CASXA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
7150 "CMP $oldval,O7\t\t! See if we made progress\n\t"
7151 "MOV 1,$res\n\t"
7152 "MOVne xcc,R_G0,$res"
7153 %}
7154 ins_encode( enc_casx(mem_ptr, oldval, newval),
7155 enc_lflags_ne_to_boolean(res) );
7156 ins_pipe( long_memory_op );
7157 %}
7158
7159
7160 instruct compareAndSwapI_bool(iRegP mem_ptr, iRegI oldval, iRegI newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
7161 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval)));
7162 match(Set res (WeakCompareAndSwapI mem_ptr (Binary oldval newval)));
7163 effect( USE mem_ptr, KILL ccr, KILL tmp1);
7164 format %{
7165 "MOV $newval,O7\n\t"
7166 "CASA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
7167 "CMP $oldval,O7\t\t! See if we made progress\n\t"
7168 "MOV 1,$res\n\t"
7169 "MOVne icc,R_G0,$res"
7170 %}
7171 ins_encode( enc_casi(mem_ptr, oldval, newval),
7172 enc_iflags_ne_to_boolean(res) );
7173 ins_pipe( long_memory_op );
7174 %}
7175
7176 instruct compareAndSwapP_bool(iRegP mem_ptr, iRegP oldval, iRegP newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
7177 #ifdef _LP64
7178 predicate(VM_Version::supports_cx8());
7179 #endif
7180 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval)));
7181 match(Set res (WeakCompareAndSwapP mem_ptr (Binary oldval newval)));
7182 effect( USE mem_ptr, KILL ccr, KILL tmp1);
7183 format %{
7184 "MOV $newval,O7\n\t"
7185 "CASA_PTR [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
7186 "CMP $oldval,O7\t\t! See if we made progress\n\t"
7187 "MOV 1,$res\n\t"
7188 "MOVne xcc,R_G0,$res"
7189 %}
7190 #ifdef _LP64
7191 ins_encode( enc_casx(mem_ptr, oldval, newval),
7192 enc_lflags_ne_to_boolean(res) );
7193 #else
7194 ins_encode( enc_casi(mem_ptr, oldval, newval),
7195 enc_iflags_ne_to_boolean(res) );
7196 #endif
7197 ins_pipe( long_memory_op );
7198 %}
7199
7200 instruct compareAndSwapN_bool(iRegP mem_ptr, iRegN oldval, iRegN newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
7201 match(Set res (CompareAndSwapN mem_ptr (Binary oldval newval)));
7202 match(Set res (WeakCompareAndSwapN mem_ptr (Binary oldval newval)));
7203 effect( USE mem_ptr, KILL ccr, KILL tmp1);
7204 format %{
7205 "MOV $newval,O7\n\t"
7206 "CASA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
7207 "CMP $oldval,O7\t\t! See if we made progress\n\t"
7208 "MOV 1,$res\n\t"
7209 "MOVne icc,R_G0,$res"
7210 %}
7211 ins_encode( enc_casi(mem_ptr, oldval, newval),
7212 enc_iflags_ne_to_boolean(res) );
7213 ins_pipe( long_memory_op );
7214 %}
7215
7216 instruct compareAndExchangeI(iRegP mem_ptr, iRegI oldval, iRegI newval)
7217 %{
7218 match(Set newval (CompareAndExchangeI mem_ptr (Binary oldval newval)));
7219 effect( USE mem_ptr );
7220
7221 format %{
7222 "CASA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr] and set $newval=[$mem_ptr]\n\t"
7223 %}
7224 ins_encode( enc_casi_exch(mem_ptr, oldval, newval) );
7225 ins_pipe( long_memory_op );
7226 %}
7227
7228 instruct compareAndExchangeL(iRegP mem_ptr, iRegL oldval, iRegL newval)
7229 %{
7230 match(Set newval (CompareAndExchangeL mem_ptr (Binary oldval newval)));
7231 effect( USE mem_ptr );
7232
7233 format %{
7234 "CASXA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr] and set $newval=[$mem_ptr]\n\t"
7235 %}
7236 ins_encode( enc_casx_exch(mem_ptr, oldval, newval) );
7237 ins_pipe( long_memory_op );
7238 %}
7239
7240 instruct compareAndExchangeP(iRegP mem_ptr, iRegP oldval, iRegP newval)
7241 %{
7242 match(Set newval (CompareAndExchangeP mem_ptr (Binary oldval newval)));
7243 effect( USE mem_ptr );
7244
7245 format %{
7246 "CASXA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr] and set $newval=[$mem_ptr]\n\t"
7247 %}
7248 ins_encode( enc_casx_exch(mem_ptr, oldval, newval) );
7249 ins_pipe( long_memory_op );
7250 %}
7251
7252 instruct compareAndExchangeN(iRegP mem_ptr, iRegN oldval, iRegN newval)
7253 %{
7254 match(Set newval (CompareAndExchangeN mem_ptr (Binary oldval newval)));
7255 effect( USE mem_ptr );
7256
7257 format %{
7258 "CASA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr] and set $newval=[$mem_ptr]\n\t"
7259 %}
7260 ins_encode( enc_casi_exch(mem_ptr, oldval, newval) );
7261 ins_pipe( long_memory_op );
7262 %}
7263
7264 instruct xchgI( memory mem, iRegI newval) %{
7265 match(Set newval (GetAndSetI mem newval));
7266 format %{ "SWAP [$mem],$newval" %}
7267 size(4);
7268 ins_encode %{
7269 __ swap($mem$$Address, $newval$$Register);
7270 %}
7271 ins_pipe( long_memory_op );
7272 %}
7273
7274 #ifndef _LP64
7275 instruct xchgP( memory mem, iRegP newval) %{
7276 match(Set newval (GetAndSetP mem newval));
7277 format %{ "SWAP [$mem],$newval" %}
7278 size(4);
7279 ins_encode %{
7280 __ swap($mem$$Address, $newval$$Register);
7281 %}
7282 ins_pipe( long_memory_op );
7283 %}
7284 #endif
7285
7286 instruct xchgN( memory mem, iRegN newval) %{
7287 match(Set newval (GetAndSetN mem newval));
7288 format %{ "SWAP [$mem],$newval" %}
7289 size(4);
7290 ins_encode %{
7291 __ swap($mem$$Address, $newval$$Register);
7292 %}
7293 ins_pipe( long_memory_op );
7294 %}
7295
7296 //---------------------
7297 // Subtraction Instructions
7298 // Register Subtraction
7299 instruct subI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7300 match(Set dst (SubI src1 src2));
7301
7302 size(4);
7303 format %{ "SUB $src1,$src2,$dst" %}
7304 opcode(Assembler::sub_op3, Assembler::arith_op);
7305 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7306 ins_pipe(ialu_reg_reg);
7307 %}
7308
7309 // Immediate Subtraction
7310 instruct subI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7311 match(Set dst (SubI src1 src2));
7312
7313 size(4);
7314 format %{ "SUB $src1,$src2,$dst" %}
7315 opcode(Assembler::sub_op3, Assembler::arith_op);
7316 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7317 ins_pipe(ialu_reg_imm);
7318 %}
7319
7320 instruct subI_zero_reg(iRegI dst, immI0 zero, iRegI src2) %{
7321 match(Set dst (SubI zero src2));
7322
7323 size(4);
7324 format %{ "NEG $src2,$dst" %}
7325 opcode(Assembler::sub_op3, Assembler::arith_op);
7326 ins_encode( form3_rs1_rs2_rd( R_G0, src2, dst ) );
7327 ins_pipe(ialu_zero_reg);
7328 %}
7329
7330 // Long subtraction
7331 instruct subL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7332 match(Set dst (SubL src1 src2));
7333
7334 size(4);
7335 format %{ "SUB $src1,$src2,$dst\t! long" %}
7336 opcode(Assembler::sub_op3, Assembler::arith_op);
7337 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7338 ins_pipe(ialu_reg_reg);
7339 %}
7340
7341 // Immediate Subtraction
7342 instruct subL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
7343 match(Set dst (SubL src1 con));
7344
7345 size(4);
7346 format %{ "SUB $src1,$con,$dst\t! long" %}
7347 opcode(Assembler::sub_op3, Assembler::arith_op);
7348 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
7349 ins_pipe(ialu_reg_imm);
7350 %}
7351
7352 // Long negation
7353 instruct negL_reg_reg(iRegL dst, immL0 zero, iRegL src2) %{
7354 match(Set dst (SubL zero src2));
7355
7356 size(4);
7357 format %{ "NEG $src2,$dst\t! long" %}
7358 opcode(Assembler::sub_op3, Assembler::arith_op);
7359 ins_encode( form3_rs1_rs2_rd( R_G0, src2, dst ) );
7360 ins_pipe(ialu_zero_reg);
7361 %}
7362
7363 // Multiplication Instructions
7364 // Integer Multiplication
7365 // Register Multiplication
7366 instruct mulI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7367 match(Set dst (MulI src1 src2));
7368
7369 size(4);
7370 format %{ "MULX $src1,$src2,$dst" %}
7371 opcode(Assembler::mulx_op3, Assembler::arith_op);
7372 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7373 ins_pipe(imul_reg_reg);
7374 %}
7375
7376 // Immediate Multiplication
7377 instruct mulI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7378 match(Set dst (MulI src1 src2));
7379
7380 size(4);
7381 format %{ "MULX $src1,$src2,$dst" %}
7382 opcode(Assembler::mulx_op3, Assembler::arith_op);
7383 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7384 ins_pipe(imul_reg_imm);
7385 %}
7386
7387 instruct mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7388 match(Set dst (MulL src1 src2));
7389 ins_cost(DEFAULT_COST * 5);
7390 size(4);
7391 format %{ "MULX $src1,$src2,$dst\t! long" %}
7392 opcode(Assembler::mulx_op3, Assembler::arith_op);
7393 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7394 ins_pipe(mulL_reg_reg);
7395 %}
7396
7397 // Immediate Multiplication
7398 instruct mulL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{
7399 match(Set dst (MulL src1 src2));
7400 ins_cost(DEFAULT_COST * 5);
7401 size(4);
7402 format %{ "MULX $src1,$src2,$dst" %}
7403 opcode(Assembler::mulx_op3, Assembler::arith_op);
7404 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7405 ins_pipe(mulL_reg_imm);
7406 %}
7407
7408 // Integer Division
7409 // Register Division
7410 instruct divI_reg_reg(iRegI dst, iRegIsafe src1, iRegIsafe src2) %{
7411 match(Set dst (DivI src1 src2));
7412 ins_cost((2+71)*DEFAULT_COST);
7413
7414 format %{ "SRA $src2,0,$src2\n\t"
7415 "SRA $src1,0,$src1\n\t"
7416 "SDIVX $src1,$src2,$dst" %}
7417 ins_encode( idiv_reg( src1, src2, dst ) );
7418 ins_pipe(sdiv_reg_reg);
7419 %}
7420
7421 // Immediate Division
7422 instruct divI_reg_imm13(iRegI dst, iRegIsafe src1, immI13 src2) %{
7423 match(Set dst (DivI src1 src2));
7424 ins_cost((2+71)*DEFAULT_COST);
7425
7426 format %{ "SRA $src1,0,$src1\n\t"
7427 "SDIVX $src1,$src2,$dst" %}
7428 ins_encode( idiv_imm( src1, src2, dst ) );
7429 ins_pipe(sdiv_reg_imm);
7430 %}
7431
7432 //----------Div-By-10-Expansion------------------------------------------------
7433 // Extract hi bits of a 32x32->64 bit multiply.
7434 // Expand rule only, not matched
7435 instruct mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2 ) %{
7436 effect( DEF dst, USE src1, USE src2 );
7437 format %{ "MULX $src1,$src2,$dst\t! Used in div-by-10\n\t"
7438 "SRLX $dst,#32,$dst\t\t! Extract only hi word of result" %}
7439 ins_encode( enc_mul_hi(dst,src1,src2));
7440 ins_pipe(sdiv_reg_reg);
7441 %}
7442
7443 // Magic constant, reciprocal of 10
7444 instruct loadConI_x66666667(iRegIsafe dst) %{
7445 effect( DEF dst );
7446
7447 size(8);
7448 format %{ "SET 0x66666667,$dst\t! Used in div-by-10" %}
7449 ins_encode( Set32(0x66666667, dst) );
7450 ins_pipe(ialu_hi_lo_reg);
7451 %}
7452
7453 // Register Shift Right Arithmetic Long by 32-63
7454 instruct sra_31( iRegI dst, iRegI src ) %{
7455 effect( DEF dst, USE src );
7456 format %{ "SRA $src,31,$dst\t! Used in div-by-10" %}
7457 ins_encode( form3_rs1_rd_copysign_hi(src,dst) );
7458 ins_pipe(ialu_reg_reg);
7459 %}
7460
7461 // Arithmetic Shift Right by 8-bit immediate
7462 instruct sra_reg_2( iRegI dst, iRegI src ) %{
7463 effect( DEF dst, USE src );
7464 format %{ "SRA $src,2,$dst\t! Used in div-by-10" %}
7465 opcode(Assembler::sra_op3, Assembler::arith_op);
7466 ins_encode( form3_rs1_simm13_rd( src, 0x2, dst ) );
7467 ins_pipe(ialu_reg_imm);
7468 %}
7469
7470 // Integer DIV with 10
7471 instruct divI_10( iRegI dst, iRegIsafe src, immI10 div ) %{
7472 match(Set dst (DivI src div));
7473 ins_cost((6+6)*DEFAULT_COST);
7474 expand %{
7475 iRegIsafe tmp1; // Killed temps;
7476 iRegIsafe tmp2; // Killed temps;
7477 iRegI tmp3; // Killed temps;
7478 iRegI tmp4; // Killed temps;
7479 loadConI_x66666667( tmp1 ); // SET 0x66666667 -> tmp1
7480 mul_hi( tmp2, src, tmp1 ); // MUL hibits(src * tmp1) -> tmp2
7481 sra_31( tmp3, src ); // SRA src,31 -> tmp3
7482 sra_reg_2( tmp4, tmp2 ); // SRA tmp2,2 -> tmp4
7483 subI_reg_reg( dst,tmp4,tmp3); // SUB tmp4 - tmp3 -> dst
7484 %}
7485 %}
7486
7487 // Register Long Division
7488 instruct divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7489 match(Set dst (DivL src1 src2));
7490 ins_cost(DEFAULT_COST*71);
7491 size(4);
7492 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
7493 opcode(Assembler::sdivx_op3, Assembler::arith_op);
7494 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7495 ins_pipe(divL_reg_reg);
7496 %}
7497
7498 // Register Long Division
7499 instruct divL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{
7500 match(Set dst (DivL src1 src2));
7501 ins_cost(DEFAULT_COST*71);
7502 size(4);
7503 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
7504 opcode(Assembler::sdivx_op3, Assembler::arith_op);
7505 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7506 ins_pipe(divL_reg_imm);
7507 %}
7508
7509 // Integer Remainder
7510 // Register Remainder
7511 instruct modI_reg_reg(iRegI dst, iRegIsafe src1, iRegIsafe src2, o7RegP temp, flagsReg ccr ) %{
7512 match(Set dst (ModI src1 src2));
7513 effect( KILL ccr, KILL temp);
7514
7515 format %{ "SREM $src1,$src2,$dst" %}
7516 ins_encode( irem_reg(src1, src2, dst, temp) );
7517 ins_pipe(sdiv_reg_reg);
7518 %}
7519
7520 // Immediate Remainder
7521 instruct modI_reg_imm13(iRegI dst, iRegIsafe src1, immI13 src2, o7RegP temp, flagsReg ccr ) %{
7522 match(Set dst (ModI src1 src2));
7523 effect( KILL ccr, KILL temp);
7524
7525 format %{ "SREM $src1,$src2,$dst" %}
7526 ins_encode( irem_imm(src1, src2, dst, temp) );
7527 ins_pipe(sdiv_reg_imm);
7528 %}
7529
7530 // Register Long Remainder
7531 instruct divL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{
7532 effect(DEF dst, USE src1, USE src2);
7533 size(4);
7534 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
7535 opcode(Assembler::sdivx_op3, Assembler::arith_op);
7536 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7537 ins_pipe(divL_reg_reg);
7538 %}
7539
7540 // Register Long Division
7541 instruct divL_reg_imm13_1(iRegL dst, iRegL src1, immL13 src2) %{
7542 effect(DEF dst, USE src1, USE src2);
7543 size(4);
7544 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
7545 opcode(Assembler::sdivx_op3, Assembler::arith_op);
7546 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7547 ins_pipe(divL_reg_imm);
7548 %}
7549
7550 instruct mulL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{
7551 effect(DEF dst, USE src1, USE src2);
7552 size(4);
7553 format %{ "MULX $src1,$src2,$dst\t! long" %}
7554 opcode(Assembler::mulx_op3, Assembler::arith_op);
7555 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7556 ins_pipe(mulL_reg_reg);
7557 %}
7558
7559 // Immediate Multiplication
7560 instruct mulL_reg_imm13_1(iRegL dst, iRegL src1, immL13 src2) %{
7561 effect(DEF dst, USE src1, USE src2);
7562 size(4);
7563 format %{ "MULX $src1,$src2,$dst" %}
7564 opcode(Assembler::mulx_op3, Assembler::arith_op);
7565 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7566 ins_pipe(mulL_reg_imm);
7567 %}
7568
7569 instruct subL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{
7570 effect(DEF dst, USE src1, USE src2);
7571 size(4);
7572 format %{ "SUB $src1,$src2,$dst\t! long" %}
7573 opcode(Assembler::sub_op3, Assembler::arith_op);
7574 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7575 ins_pipe(ialu_reg_reg);
7576 %}
7577
7578 instruct subL_reg_reg_2(iRegL dst, iRegL src1, iRegL src2) %{
7579 effect(DEF dst, USE src1, USE src2);
7580 size(4);
7581 format %{ "SUB $src1,$src2,$dst\t! long" %}
7582 opcode(Assembler::sub_op3, Assembler::arith_op);
7583 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7584 ins_pipe(ialu_reg_reg);
7585 %}
7586
7587 // Register Long Remainder
7588 instruct modL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7589 match(Set dst (ModL src1 src2));
7590 ins_cost(DEFAULT_COST*(71 + 6 + 1));
7591 expand %{
7592 iRegL tmp1;
7593 iRegL tmp2;
7594 divL_reg_reg_1(tmp1, src1, src2);
7595 mulL_reg_reg_1(tmp2, tmp1, src2);
7596 subL_reg_reg_1(dst, src1, tmp2);
7597 %}
7598 %}
7599
7600 // Register Long Remainder
7601 instruct modL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{
7602 match(Set dst (ModL src1 src2));
7603 ins_cost(DEFAULT_COST*(71 + 6 + 1));
7604 expand %{
7605 iRegL tmp1;
7606 iRegL tmp2;
7607 divL_reg_imm13_1(tmp1, src1, src2);
7608 mulL_reg_imm13_1(tmp2, tmp1, src2);
7609 subL_reg_reg_2 (dst, src1, tmp2);
7610 %}
7611 %}
7612
7613 // Integer Shift Instructions
7614 // Register Shift Left
7615 instruct shlI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7616 match(Set dst (LShiftI src1 src2));
7617
7618 size(4);
7619 format %{ "SLL $src1,$src2,$dst" %}
7620 opcode(Assembler::sll_op3, Assembler::arith_op);
7621 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7622 ins_pipe(ialu_reg_reg);
7623 %}
7624
7625 // Register Shift Left Immediate
7626 instruct shlI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{
7627 match(Set dst (LShiftI src1 src2));
7628
7629 size(4);
7630 format %{ "SLL $src1,$src2,$dst" %}
7631 opcode(Assembler::sll_op3, Assembler::arith_op);
7632 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7633 ins_pipe(ialu_reg_imm);
7634 %}
7635
7636 // Register Shift Left
7637 instruct shlL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
7638 match(Set dst (LShiftL src1 src2));
7639
7640 size(4);
7641 format %{ "SLLX $src1,$src2,$dst" %}
7642 opcode(Assembler::sllx_op3, Assembler::arith_op);
7643 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) );
7644 ins_pipe(ialu_reg_reg);
7645 %}
7646
7647 // Register Shift Left Immediate
7648 instruct shlL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{
7649 match(Set dst (LShiftL src1 src2));
7650
7651 size(4);
7652 format %{ "SLLX $src1,$src2,$dst" %}
7653 opcode(Assembler::sllx_op3, Assembler::arith_op);
7654 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7655 ins_pipe(ialu_reg_imm);
7656 %}
7657
7658 // Register Arithmetic Shift Right
7659 instruct sarI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7660 match(Set dst (RShiftI src1 src2));
7661 size(4);
7662 format %{ "SRA $src1,$src2,$dst" %}
7663 opcode(Assembler::sra_op3, Assembler::arith_op);
7664 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7665 ins_pipe(ialu_reg_reg);
7666 %}
7667
7668 // Register Arithmetic Shift Right Immediate
7669 instruct sarI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{
7670 match(Set dst (RShiftI src1 src2));
7671
7672 size(4);
7673 format %{ "SRA $src1,$src2,$dst" %}
7674 opcode(Assembler::sra_op3, Assembler::arith_op);
7675 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7676 ins_pipe(ialu_reg_imm);
7677 %}
7678
7679 // Register Shift Right Arithmatic Long
7680 instruct sarL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
7681 match(Set dst (RShiftL src1 src2));
7682
7683 size(4);
7684 format %{ "SRAX $src1,$src2,$dst" %}
7685 opcode(Assembler::srax_op3, Assembler::arith_op);
7686 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) );
7687 ins_pipe(ialu_reg_reg);
7688 %}
7689
7690 // Register Shift Left Immediate
7691 instruct sarL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{
7692 match(Set dst (RShiftL src1 src2));
7693
7694 size(4);
7695 format %{ "SRAX $src1,$src2,$dst" %}
7696 opcode(Assembler::srax_op3, Assembler::arith_op);
7697 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7698 ins_pipe(ialu_reg_imm);
7699 %}
7700
7701 // Register Shift Right
7702 instruct shrI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7703 match(Set dst (URShiftI src1 src2));
7704
7705 size(4);
7706 format %{ "SRL $src1,$src2,$dst" %}
7707 opcode(Assembler::srl_op3, Assembler::arith_op);
7708 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7709 ins_pipe(ialu_reg_reg);
7710 %}
7711
7712 // Register Shift Right Immediate
7713 instruct shrI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{
7714 match(Set dst (URShiftI src1 src2));
7715
7716 size(4);
7717 format %{ "SRL $src1,$src2,$dst" %}
7718 opcode(Assembler::srl_op3, Assembler::arith_op);
7719 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7720 ins_pipe(ialu_reg_imm);
7721 %}
7722
7723 // Register Shift Right
7724 instruct shrL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
7725 match(Set dst (URShiftL src1 src2));
7726
7727 size(4);
7728 format %{ "SRLX $src1,$src2,$dst" %}
7729 opcode(Assembler::srlx_op3, Assembler::arith_op);
7730 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) );
7731 ins_pipe(ialu_reg_reg);
7732 %}
7733
7734 // Register Shift Right Immediate
7735 instruct shrL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{
7736 match(Set dst (URShiftL src1 src2));
7737
7738 size(4);
7739 format %{ "SRLX $src1,$src2,$dst" %}
7740 opcode(Assembler::srlx_op3, Assembler::arith_op);
7741 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7742 ins_pipe(ialu_reg_imm);
7743 %}
7744
7745 // Register Shift Right Immediate with a CastP2X
7746 #ifdef _LP64
7747 instruct shrP_reg_imm6(iRegL dst, iRegP src1, immU6 src2) %{
7748 match(Set dst (URShiftL (CastP2X src1) src2));
7749 size(4);
7750 format %{ "SRLX $src1,$src2,$dst\t! Cast ptr $src1 to long and shift" %}
7751 opcode(Assembler::srlx_op3, Assembler::arith_op);
7752 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7753 ins_pipe(ialu_reg_imm);
7754 %}
7755 #else
7756 instruct shrP_reg_imm5(iRegI dst, iRegP src1, immU5 src2) %{
7757 match(Set dst (URShiftI (CastP2X src1) src2));
7758 size(4);
7759 format %{ "SRL $src1,$src2,$dst\t! Cast ptr $src1 to int and shift" %}
7760 opcode(Assembler::srl_op3, Assembler::arith_op);
7761 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7762 ins_pipe(ialu_reg_imm);
7763 %}
7764 #endif
7765
7766
7767 //----------Floating Point Arithmetic Instructions-----------------------------
7768
7769 // Add float single precision
7770 instruct addF_reg_reg(regF dst, regF src1, regF src2) %{
7771 match(Set dst (AddF src1 src2));
7772
7773 size(4);
7774 format %{ "FADDS $src1,$src2,$dst" %}
7775 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fadds_opf);
7776 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7777 ins_pipe(faddF_reg_reg);
7778 %}
7779
7780 // Add float double precision
7781 instruct addD_reg_reg(regD dst, regD src1, regD src2) %{
7782 match(Set dst (AddD src1 src2));
7783
7784 size(4);
7785 format %{ "FADDD $src1,$src2,$dst" %}
7786 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::faddd_opf);
7787 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7788 ins_pipe(faddD_reg_reg);
7789 %}
7790
7791 // Sub float single precision
7792 instruct subF_reg_reg(regF dst, regF src1, regF src2) %{
7793 match(Set dst (SubF src1 src2));
7794
7795 size(4);
7796 format %{ "FSUBS $src1,$src2,$dst" %}
7797 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubs_opf);
7798 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7799 ins_pipe(faddF_reg_reg);
7800 %}
7801
7802 // Sub float double precision
7803 instruct subD_reg_reg(regD dst, regD src1, regD src2) %{
7804 match(Set dst (SubD src1 src2));
7805
7806 size(4);
7807 format %{ "FSUBD $src1,$src2,$dst" %}
7808 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubd_opf);
7809 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7810 ins_pipe(faddD_reg_reg);
7811 %}
7812
7813 // Mul float single precision
7814 instruct mulF_reg_reg(regF dst, regF src1, regF src2) %{
7815 match(Set dst (MulF src1 src2));
7816
7817 size(4);
7818 format %{ "FMULS $src1,$src2,$dst" %}
7819 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuls_opf);
7820 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7821 ins_pipe(fmulF_reg_reg);
7822 %}
7823
7824 // Mul float double precision
7825 instruct mulD_reg_reg(regD dst, regD src1, regD src2) %{
7826 match(Set dst (MulD src1 src2));
7827
7828 size(4);
7829 format %{ "FMULD $src1,$src2,$dst" %}
7830 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuld_opf);
7831 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7832 ins_pipe(fmulD_reg_reg);
7833 %}
7834
7835 // Div float single precision
7836 instruct divF_reg_reg(regF dst, regF src1, regF src2) %{
7837 match(Set dst (DivF src1 src2));
7838
7839 size(4);
7840 format %{ "FDIVS $src1,$src2,$dst" %}
7841 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdivs_opf);
7842 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7843 ins_pipe(fdivF_reg_reg);
7844 %}
7845
7846 // Div float double precision
7847 instruct divD_reg_reg(regD dst, regD src1, regD src2) %{
7848 match(Set dst (DivD src1 src2));
7849
7850 size(4);
7851 format %{ "FDIVD $src1,$src2,$dst" %}
7852 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdivd_opf);
7853 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7854 ins_pipe(fdivD_reg_reg);
7855 %}
7856
7857 // Absolute float double precision
7858 instruct absD_reg(regD dst, regD src) %{
7859 match(Set dst (AbsD src));
7860
7861 format %{ "FABSd $src,$dst" %}
7862 ins_encode(fabsd(dst, src));
7863 ins_pipe(faddD_reg);
7864 %}
7865
7866 // Absolute float single precision
7867 instruct absF_reg(regF dst, regF src) %{
7868 match(Set dst (AbsF src));
7869
7870 format %{ "FABSs $src,$dst" %}
7871 ins_encode(fabss(dst, src));
7872 ins_pipe(faddF_reg);
7873 %}
7874
7875 instruct negF_reg(regF dst, regF src) %{
7876 match(Set dst (NegF src));
7877
7878 size(4);
7879 format %{ "FNEGs $src,$dst" %}
7880 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fnegs_opf);
7881 ins_encode(form3_opf_rs2F_rdF(src, dst));
7882 ins_pipe(faddF_reg);
7883 %}
7884
7885 instruct negD_reg(regD dst, regD src) %{
7886 match(Set dst (NegD src));
7887
7888 format %{ "FNEGd $src,$dst" %}
7889 ins_encode(fnegd(dst, src));
7890 ins_pipe(faddD_reg);
7891 %}
7892
7893 // Sqrt float double precision
7894 instruct sqrtF_reg_reg(regF dst, regF src) %{
7895 match(Set dst (ConvD2F (SqrtD (ConvF2D src))));
7896
7897 size(4);
7898 format %{ "FSQRTS $src,$dst" %}
7899 ins_encode(fsqrts(dst, src));
7900 ins_pipe(fdivF_reg_reg);
7901 %}
7902
7903 // Sqrt float double precision
7904 instruct sqrtD_reg_reg(regD dst, regD src) %{
7905 match(Set dst (SqrtD src));
7906
7907 size(4);
7908 format %{ "FSQRTD $src,$dst" %}
7909 ins_encode(fsqrtd(dst, src));
7910 ins_pipe(fdivD_reg_reg);
7911 %}
7912
7913 //----------Logical Instructions-----------------------------------------------
7914 // And Instructions
7915 // Register And
7916 instruct andI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7917 match(Set dst (AndI src1 src2));
7918
7919 size(4);
7920 format %{ "AND $src1,$src2,$dst" %}
7921 opcode(Assembler::and_op3, Assembler::arith_op);
7922 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7923 ins_pipe(ialu_reg_reg);
7924 %}
7925
7926 // Immediate And
7927 instruct andI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7928 match(Set dst (AndI src1 src2));
7929
7930 size(4);
7931 format %{ "AND $src1,$src2,$dst" %}
7932 opcode(Assembler::and_op3, Assembler::arith_op);
7933 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7934 ins_pipe(ialu_reg_imm);
7935 %}
7936
7937 // Register And Long
7938 instruct andL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7939 match(Set dst (AndL src1 src2));
7940
7941 ins_cost(DEFAULT_COST);
7942 size(4);
7943 format %{ "AND $src1,$src2,$dst\t! long" %}
7944 opcode(Assembler::and_op3, Assembler::arith_op);
7945 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7946 ins_pipe(ialu_reg_reg);
7947 %}
7948
7949 instruct andL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
7950 match(Set dst (AndL src1 con));
7951
7952 ins_cost(DEFAULT_COST);
7953 size(4);
7954 format %{ "AND $src1,$con,$dst\t! long" %}
7955 opcode(Assembler::and_op3, Assembler::arith_op);
7956 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
7957 ins_pipe(ialu_reg_imm);
7958 %}
7959
7960 // Or Instructions
7961 // Register Or
7962 instruct orI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7963 match(Set dst (OrI src1 src2));
7964
7965 size(4);
7966 format %{ "OR $src1,$src2,$dst" %}
7967 opcode(Assembler::or_op3, Assembler::arith_op);
7968 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7969 ins_pipe(ialu_reg_reg);
7970 %}
7971
7972 // Immediate Or
7973 instruct orI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7974 match(Set dst (OrI src1 src2));
7975
7976 size(4);
7977 format %{ "OR $src1,$src2,$dst" %}
7978 opcode(Assembler::or_op3, Assembler::arith_op);
7979 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7980 ins_pipe(ialu_reg_imm);
7981 %}
7982
7983 // Register Or Long
7984 instruct orL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7985 match(Set dst (OrL src1 src2));
7986
7987 ins_cost(DEFAULT_COST);
7988 size(4);
7989 format %{ "OR $src1,$src2,$dst\t! long" %}
7990 opcode(Assembler::or_op3, Assembler::arith_op);
7991 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7992 ins_pipe(ialu_reg_reg);
7993 %}
7994
7995 instruct orL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
7996 match(Set dst (OrL src1 con));
7997 ins_cost(DEFAULT_COST*2);
7998
7999 ins_cost(DEFAULT_COST);
8000 size(4);
8001 format %{ "OR $src1,$con,$dst\t! long" %}
8002 opcode(Assembler::or_op3, Assembler::arith_op);
8003 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
8004 ins_pipe(ialu_reg_imm);
8005 %}
8006
8007 #ifndef _LP64
8008
8009 // Use sp_ptr_RegP to match G2 (TLS register) without spilling.
8010 instruct orI_reg_castP2X(iRegI dst, iRegI src1, sp_ptr_RegP src2) %{
8011 match(Set dst (OrI src1 (CastP2X src2)));
8012
8013 size(4);
8014 format %{ "OR $src1,$src2,$dst" %}
8015 opcode(Assembler::or_op3, Assembler::arith_op);
8016 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
8017 ins_pipe(ialu_reg_reg);
8018 %}
8019
8020 #else
8021
8022 instruct orL_reg_castP2X(iRegL dst, iRegL src1, sp_ptr_RegP src2) %{
8023 match(Set dst (OrL src1 (CastP2X src2)));
8024
8025 ins_cost(DEFAULT_COST);
8026 size(4);
8027 format %{ "OR $src1,$src2,$dst\t! long" %}
8028 opcode(Assembler::or_op3, Assembler::arith_op);
8029 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
8030 ins_pipe(ialu_reg_reg);
8031 %}
8032
8033 #endif
8034
8035 // Xor Instructions
8036 // Register Xor
8037 instruct xorI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
8038 match(Set dst (XorI src1 src2));
8039
8040 size(4);
8041 format %{ "XOR $src1,$src2,$dst" %}
8042 opcode(Assembler::xor_op3, Assembler::arith_op);
8043 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
8044 ins_pipe(ialu_reg_reg);
8045 %}
8046
8047 // Immediate Xor
8048 instruct xorI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
8049 match(Set dst (XorI src1 src2));
8050
8051 size(4);
8052 format %{ "XOR $src1,$src2,$dst" %}
8053 opcode(Assembler::xor_op3, Assembler::arith_op);
8054 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
8055 ins_pipe(ialu_reg_imm);
8056 %}
8057
8058 // Register Xor Long
8059 instruct xorL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
8060 match(Set dst (XorL src1 src2));
8061
8062 ins_cost(DEFAULT_COST);
8063 size(4);
8064 format %{ "XOR $src1,$src2,$dst\t! long" %}
8065 opcode(Assembler::xor_op3, Assembler::arith_op);
8066 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
8067 ins_pipe(ialu_reg_reg);
8068 %}
8069
8070 instruct xorL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
8071 match(Set dst (XorL src1 con));
8072
8073 ins_cost(DEFAULT_COST);
8074 size(4);
8075 format %{ "XOR $src1,$con,$dst\t! long" %}
8076 opcode(Assembler::xor_op3, Assembler::arith_op);
8077 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
8078 ins_pipe(ialu_reg_imm);
8079 %}
8080
8081 //----------Convert to Boolean-------------------------------------------------
8082 // Nice hack for 32-bit tests but doesn't work for
8083 // 64-bit pointers.
8084 instruct convI2B( iRegI dst, iRegI src, flagsReg ccr ) %{
8085 match(Set dst (Conv2B src));
8086 effect( KILL ccr );
8087 ins_cost(DEFAULT_COST*2);
8088 format %{ "CMP R_G0,$src\n\t"
8089 "ADDX R_G0,0,$dst" %}
8090 ins_encode( enc_to_bool( src, dst ) );
8091 ins_pipe(ialu_reg_ialu);
8092 %}
8093
8094 #ifndef _LP64
8095 instruct convP2B( iRegI dst, iRegP src, flagsReg ccr ) %{
8096 match(Set dst (Conv2B src));
8097 effect( KILL ccr );
8098 ins_cost(DEFAULT_COST*2);
8099 format %{ "CMP R_G0,$src\n\t"
8100 "ADDX R_G0,0,$dst" %}
8101 ins_encode( enc_to_bool( src, dst ) );
8102 ins_pipe(ialu_reg_ialu);
8103 %}
8104 #else
8105 instruct convP2B( iRegI dst, iRegP src ) %{
8106 match(Set dst (Conv2B src));
8107 ins_cost(DEFAULT_COST*2);
8108 format %{ "MOV $src,$dst\n\t"
8109 "MOVRNZ $src,1,$dst" %}
8110 ins_encode( form3_g0_rs2_rd_move( src, dst ), enc_convP2B( dst, src ) );
8111 ins_pipe(ialu_clr_and_mover);
8112 %}
8113 #endif
8114
8115 instruct cmpLTMask0( iRegI dst, iRegI src, immI0 zero, flagsReg ccr ) %{
8116 match(Set dst (CmpLTMask src zero));
8117 effect(KILL ccr);
8118 size(4);
8119 format %{ "SRA $src,#31,$dst\t# cmpLTMask0" %}
8120 ins_encode %{
8121 __ sra($src$$Register, 31, $dst$$Register);
8122 %}
8123 ins_pipe(ialu_reg_imm);
8124 %}
8125
8126 instruct cmpLTMask_reg_reg( iRegI dst, iRegI p, iRegI q, flagsReg ccr ) %{
8127 match(Set dst (CmpLTMask p q));
8128 effect( KILL ccr );
8129 ins_cost(DEFAULT_COST*4);
8130 format %{ "CMP $p,$q\n\t"
8131 "MOV #0,$dst\n\t"
8132 "BLT,a .+8\n\t"
8133 "MOV #-1,$dst" %}
8134 ins_encode( enc_ltmask(p,q,dst) );
8135 ins_pipe(ialu_reg_reg_ialu);
8136 %}
8137
8138 instruct cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp, flagsReg ccr ) %{
8139 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)));
8140 effect(KILL ccr, TEMP tmp);
8141 ins_cost(DEFAULT_COST*3);
8142
8143 format %{ "SUBcc $p,$q,$p\t! p' = p-q\n\t"
8144 "ADD $p,$y,$tmp\t! g3=p-q+y\n\t"
8145 "MOVlt $tmp,$p\t! p' < 0 ? p'+y : p'" %}
8146 ins_encode(enc_cadd_cmpLTMask(p, q, y, tmp));
8147 ins_pipe(cadd_cmpltmask);
8148 %}
8149
8150 instruct and_cmpLTMask(iRegI p, iRegI q, iRegI y, flagsReg ccr) %{
8151 match(Set p (AndI (CmpLTMask p q) y));
8152 effect(KILL ccr);
8153 ins_cost(DEFAULT_COST*3);
8154
8155 format %{ "CMP $p,$q\n\t"
8156 "MOV $y,$p\n\t"
8157 "MOVge G0,$p" %}
8158 ins_encode %{
8159 __ cmp($p$$Register, $q$$Register);
8160 __ mov($y$$Register, $p$$Register);
8161 __ movcc(Assembler::greaterEqual, false, Assembler::icc, G0, $p$$Register);
8162 %}
8163 ins_pipe(ialu_reg_reg_ialu);
8164 %}
8165
8166 //-----------------------------------------------------------------
8167 // Direct raw moves between float and general registers using VIS3.
8168
8169 // ins_pipe(faddF_reg);
8170 instruct MoveF2I_reg_reg(iRegI dst, regF src) %{
8171 predicate(UseVIS >= 3);
8172 match(Set dst (MoveF2I src));
8173
8174 format %{ "MOVSTOUW $src,$dst\t! MoveF2I" %}
8175 ins_encode %{
8176 __ movstouw($src$$FloatRegister, $dst$$Register);
8177 %}
8178 ins_pipe(ialu_reg_reg);
8179 %}
8180
8181 instruct MoveI2F_reg_reg(regF dst, iRegI src) %{
8182 predicate(UseVIS >= 3);
8183 match(Set dst (MoveI2F src));
8184
8185 format %{ "MOVWTOS $src,$dst\t! MoveI2F" %}
8186 ins_encode %{
8187 __ movwtos($src$$Register, $dst$$FloatRegister);
8188 %}
8189 ins_pipe(ialu_reg_reg);
8190 %}
8191
8192 instruct MoveD2L_reg_reg(iRegL dst, regD src) %{
8193 predicate(UseVIS >= 3);
8194 match(Set dst (MoveD2L src));
8195
8196 format %{ "MOVDTOX $src,$dst\t! MoveD2L" %}
8197 ins_encode %{
8198 __ movdtox(as_DoubleFloatRegister($src$$reg), $dst$$Register);
8199 %}
8200 ins_pipe(ialu_reg_reg);
8201 %}
8202
8203 instruct MoveL2D_reg_reg(regD dst, iRegL src) %{
8204 predicate(UseVIS >= 3);
8205 match(Set dst (MoveL2D src));
8206
8207 format %{ "MOVXTOD $src,$dst\t! MoveL2D" %}
8208 ins_encode %{
8209 __ movxtod($src$$Register, as_DoubleFloatRegister($dst$$reg));
8210 %}
8211 ins_pipe(ialu_reg_reg);
8212 %}
8213
8214
8215 // Raw moves between float and general registers using stack.
8216
8217 instruct MoveF2I_stack_reg(iRegI dst, stackSlotF src) %{
8218 match(Set dst (MoveF2I src));
8219 effect(DEF dst, USE src);
8220 ins_cost(MEMORY_REF_COST);
8221
8222 format %{ "LDUW $src,$dst\t! MoveF2I" %}
8223 opcode(Assembler::lduw_op3);
8224 ins_encode(simple_form3_mem_reg( src, dst ) );
8225 ins_pipe(iload_mem);
8226 %}
8227
8228 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{
8229 match(Set dst (MoveI2F src));
8230 effect(DEF dst, USE src);
8231 ins_cost(MEMORY_REF_COST);
8232
8233 format %{ "LDF $src,$dst\t! MoveI2F" %}
8234 opcode(Assembler::ldf_op3);
8235 ins_encode(simple_form3_mem_reg(src, dst));
8236 ins_pipe(floadF_stk);
8237 %}
8238
8239 instruct MoveD2L_stack_reg(iRegL dst, stackSlotD src) %{
8240 match(Set dst (MoveD2L src));
8241 effect(DEF dst, USE src);
8242 ins_cost(MEMORY_REF_COST);
8243
8244 format %{ "LDX $src,$dst\t! MoveD2L" %}
8245 opcode(Assembler::ldx_op3);
8246 ins_encode(simple_form3_mem_reg( src, dst ) );
8247 ins_pipe(iload_mem);
8248 %}
8249
8250 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{
8251 match(Set dst (MoveL2D src));
8252 effect(DEF dst, USE src);
8253 ins_cost(MEMORY_REF_COST);
8254
8255 format %{ "LDDF $src,$dst\t! MoveL2D" %}
8256 opcode(Assembler::lddf_op3);
8257 ins_encode(simple_form3_mem_reg(src, dst));
8258 ins_pipe(floadD_stk);
8259 %}
8260
8261 instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{
8262 match(Set dst (MoveF2I src));
8263 effect(DEF dst, USE src);
8264 ins_cost(MEMORY_REF_COST);
8265
8266 format %{ "STF $src,$dst\t! MoveF2I" %}
8267 opcode(Assembler::stf_op3);
8268 ins_encode(simple_form3_mem_reg(dst, src));
8269 ins_pipe(fstoreF_stk_reg);
8270 %}
8271
8272 instruct MoveI2F_reg_stack(stackSlotF dst, iRegI src) %{
8273 match(Set dst (MoveI2F src));
8274 effect(DEF dst, USE src);
8275 ins_cost(MEMORY_REF_COST);
8276
8277 format %{ "STW $src,$dst\t! MoveI2F" %}
8278 opcode(Assembler::stw_op3);
8279 ins_encode(simple_form3_mem_reg( dst, src ) );
8280 ins_pipe(istore_mem_reg);
8281 %}
8282
8283 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{
8284 match(Set dst (MoveD2L src));
8285 effect(DEF dst, USE src);
8286 ins_cost(MEMORY_REF_COST);
8287
8288 format %{ "STDF $src,$dst\t! MoveD2L" %}
8289 opcode(Assembler::stdf_op3);
8290 ins_encode(simple_form3_mem_reg(dst, src));
8291 ins_pipe(fstoreD_stk_reg);
8292 %}
8293
8294 instruct MoveL2D_reg_stack(stackSlotD dst, iRegL src) %{
8295 match(Set dst (MoveL2D src));
8296 effect(DEF dst, USE src);
8297 ins_cost(MEMORY_REF_COST);
8298
8299 format %{ "STX $src,$dst\t! MoveL2D" %}
8300 opcode(Assembler::stx_op3);
8301 ins_encode(simple_form3_mem_reg( dst, src ) );
8302 ins_pipe(istore_mem_reg);
8303 %}
8304
8305
8306 //----------Arithmetic Conversion Instructions---------------------------------
8307 // The conversions operations are all Alpha sorted. Please keep it that way!
8308
8309 instruct convD2F_reg(regF dst, regD src) %{
8310 match(Set dst (ConvD2F src));
8311 size(4);
8312 format %{ "FDTOS $src,$dst" %}
8313 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdtos_opf);
8314 ins_encode(form3_opf_rs2D_rdF(src, dst));
8315 ins_pipe(fcvtD2F);
8316 %}
8317
8318
8319 // Convert a double to an int in a float register.
8320 // If the double is a NAN, stuff a zero in instead.
8321 instruct convD2I_helper(regF dst, regD src, flagsRegF0 fcc0) %{
8322 effect(DEF dst, USE src, KILL fcc0);
8323 format %{ "FCMPd fcc0,$src,$src\t! check for NAN\n\t"
8324 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
8325 "FDTOI $src,$dst\t! convert in delay slot\n\t"
8326 "FITOS $dst,$dst\t! change NaN/max-int to valid float\n\t"
8327 "FSUBs $dst,$dst,$dst\t! cleared only if nan\n"
8328 "skip:" %}
8329 ins_encode(form_d2i_helper(src,dst));
8330 ins_pipe(fcvtD2I);
8331 %}
8332
8333 instruct convD2I_stk(stackSlotI dst, regD src) %{
8334 match(Set dst (ConvD2I src));
8335 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
8336 expand %{
8337 regF tmp;
8338 convD2I_helper(tmp, src);
8339 regF_to_stkI(dst, tmp);
8340 %}
8341 %}
8342
8343 instruct convD2I_reg(iRegI dst, regD src) %{
8344 predicate(UseVIS >= 3);
8345 match(Set dst (ConvD2I src));
8346 ins_cost(DEFAULT_COST*2 + BRANCH_COST);
8347 expand %{
8348 regF tmp;
8349 convD2I_helper(tmp, src);
8350 MoveF2I_reg_reg(dst, tmp);
8351 %}
8352 %}
8353
8354
8355 // Convert a double to a long in a double register.
8356 // If the double is a NAN, stuff a zero in instead.
8357 instruct convD2L_helper(regD dst, regD src, flagsRegF0 fcc0) %{
8358 effect(DEF dst, USE src, KILL fcc0);
8359 format %{ "FCMPd fcc0,$src,$src\t! check for NAN\n\t"
8360 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
8361 "FDTOX $src,$dst\t! convert in delay slot\n\t"
8362 "FXTOD $dst,$dst\t! change NaN/max-long to valid double\n\t"
8363 "FSUBd $dst,$dst,$dst\t! cleared only if nan\n"
8364 "skip:" %}
8365 ins_encode(form_d2l_helper(src,dst));
8366 ins_pipe(fcvtD2L);
8367 %}
8368
8369 instruct convD2L_stk(stackSlotL dst, regD src) %{
8370 match(Set dst (ConvD2L src));
8371 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
8372 expand %{
8373 regD tmp;
8374 convD2L_helper(tmp, src);
8375 regD_to_stkL(dst, tmp);
8376 %}
8377 %}
8378
8379 instruct convD2L_reg(iRegL dst, regD src) %{
8380 predicate(UseVIS >= 3);
8381 match(Set dst (ConvD2L src));
8382 ins_cost(DEFAULT_COST*2 + BRANCH_COST);
8383 expand %{
8384 regD tmp;
8385 convD2L_helper(tmp, src);
8386 MoveD2L_reg_reg(dst, tmp);
8387 %}
8388 %}
8389
8390
8391 instruct convF2D_reg(regD dst, regF src) %{
8392 match(Set dst (ConvF2D src));
8393 format %{ "FSTOD $src,$dst" %}
8394 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fstod_opf);
8395 ins_encode(form3_opf_rs2F_rdD(src, dst));
8396 ins_pipe(fcvtF2D);
8397 %}
8398
8399
8400 // Convert a float to an int in a float register.
8401 // If the float is a NAN, stuff a zero in instead.
8402 instruct convF2I_helper(regF dst, regF src, flagsRegF0 fcc0) %{
8403 effect(DEF dst, USE src, KILL fcc0);
8404 format %{ "FCMPs fcc0,$src,$src\t! check for NAN\n\t"
8405 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
8406 "FSTOI $src,$dst\t! convert in delay slot\n\t"
8407 "FITOS $dst,$dst\t! change NaN/max-int to valid float\n\t"
8408 "FSUBs $dst,$dst,$dst\t! cleared only if nan\n"
8409 "skip:" %}
8410 ins_encode(form_f2i_helper(src,dst));
8411 ins_pipe(fcvtF2I);
8412 %}
8413
8414 instruct convF2I_stk(stackSlotI dst, regF src) %{
8415 match(Set dst (ConvF2I src));
8416 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
8417 expand %{
8418 regF tmp;
8419 convF2I_helper(tmp, src);
8420 regF_to_stkI(dst, tmp);
8421 %}
8422 %}
8423
8424 instruct convF2I_reg(iRegI dst, regF src) %{
8425 predicate(UseVIS >= 3);
8426 match(Set dst (ConvF2I src));
8427 ins_cost(DEFAULT_COST*2 + BRANCH_COST);
8428 expand %{
8429 regF tmp;
8430 convF2I_helper(tmp, src);
8431 MoveF2I_reg_reg(dst, tmp);
8432 %}
8433 %}
8434
8435
8436 // Convert a float to a long in a float register.
8437 // If the float is a NAN, stuff a zero in instead.
8438 instruct convF2L_helper(regD dst, regF src, flagsRegF0 fcc0) %{
8439 effect(DEF dst, USE src, KILL fcc0);
8440 format %{ "FCMPs fcc0,$src,$src\t! check for NAN\n\t"
8441 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
8442 "FSTOX $src,$dst\t! convert in delay slot\n\t"
8443 "FXTOD $dst,$dst\t! change NaN/max-long to valid double\n\t"
8444 "FSUBd $dst,$dst,$dst\t! cleared only if nan\n"
8445 "skip:" %}
8446 ins_encode(form_f2l_helper(src,dst));
8447 ins_pipe(fcvtF2L);
8448 %}
8449
8450 instruct convF2L_stk(stackSlotL dst, regF src) %{
8451 match(Set dst (ConvF2L src));
8452 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
8453 expand %{
8454 regD tmp;
8455 convF2L_helper(tmp, src);
8456 regD_to_stkL(dst, tmp);
8457 %}
8458 %}
8459
8460 instruct convF2L_reg(iRegL dst, regF src) %{
8461 predicate(UseVIS >= 3);
8462 match(Set dst (ConvF2L src));
8463 ins_cost(DEFAULT_COST*2 + BRANCH_COST);
8464 expand %{
8465 regD tmp;
8466 convF2L_helper(tmp, src);
8467 MoveD2L_reg_reg(dst, tmp);
8468 %}
8469 %}
8470
8471
8472 instruct convI2D_helper(regD dst, regF tmp) %{
8473 effect(USE tmp, DEF dst);
8474 format %{ "FITOD $tmp,$dst" %}
8475 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf);
8476 ins_encode(form3_opf_rs2F_rdD(tmp, dst));
8477 ins_pipe(fcvtI2D);
8478 %}
8479
8480 instruct convI2D_stk(stackSlotI src, regD dst) %{
8481 match(Set dst (ConvI2D src));
8482 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8483 expand %{
8484 regF tmp;
8485 stkI_to_regF(tmp, src);
8486 convI2D_helper(dst, tmp);
8487 %}
8488 %}
8489
8490 instruct convI2D_reg(regD_low dst, iRegI src) %{
8491 predicate(UseVIS >= 3);
8492 match(Set dst (ConvI2D src));
8493 expand %{
8494 regF tmp;
8495 MoveI2F_reg_reg(tmp, src);
8496 convI2D_helper(dst, tmp);
8497 %}
8498 %}
8499
8500 instruct convI2D_mem(regD_low dst, memory mem) %{
8501 match(Set dst (ConvI2D (LoadI mem)));
8502 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8503 format %{ "LDF $mem,$dst\n\t"
8504 "FITOD $dst,$dst" %}
8505 opcode(Assembler::ldf_op3, Assembler::fitod_opf);
8506 ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst));
8507 ins_pipe(floadF_mem);
8508 %}
8509
8510
8511 instruct convI2F_helper(regF dst, regF tmp) %{
8512 effect(DEF dst, USE tmp);
8513 format %{ "FITOS $tmp,$dst" %}
8514 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitos_opf);
8515 ins_encode(form3_opf_rs2F_rdF(tmp, dst));
8516 ins_pipe(fcvtI2F);
8517 %}
8518
8519 instruct convI2F_stk(regF dst, stackSlotI src) %{
8520 match(Set dst (ConvI2F src));
8521 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8522 expand %{
8523 regF tmp;
8524 stkI_to_regF(tmp,src);
8525 convI2F_helper(dst, tmp);
8526 %}
8527 %}
8528
8529 instruct convI2F_reg(regF dst, iRegI src) %{
8530 predicate(UseVIS >= 3);
8531 match(Set dst (ConvI2F src));
8532 ins_cost(DEFAULT_COST);
8533 expand %{
8534 regF tmp;
8535 MoveI2F_reg_reg(tmp, src);
8536 convI2F_helper(dst, tmp);
8537 %}
8538 %}
8539
8540 instruct convI2F_mem( regF dst, memory mem ) %{
8541 match(Set dst (ConvI2F (LoadI mem)));
8542 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8543 format %{ "LDF $mem,$dst\n\t"
8544 "FITOS $dst,$dst" %}
8545 opcode(Assembler::ldf_op3, Assembler::fitos_opf);
8546 ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst));
8547 ins_pipe(floadF_mem);
8548 %}
8549
8550
8551 instruct convI2L_reg(iRegL dst, iRegI src) %{
8552 match(Set dst (ConvI2L src));
8553 size(4);
8554 format %{ "SRA $src,0,$dst\t! int->long" %}
8555 opcode(Assembler::sra_op3, Assembler::arith_op);
8556 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) );
8557 ins_pipe(ialu_reg_reg);
8558 %}
8559
8560 // Zero-extend convert int to long
8561 instruct convI2L_reg_zex(iRegL dst, iRegI src, immL_32bits mask ) %{
8562 match(Set dst (AndL (ConvI2L src) mask) );
8563 size(4);
8564 format %{ "SRL $src,0,$dst\t! zero-extend int to long" %}
8565 opcode(Assembler::srl_op3, Assembler::arith_op);
8566 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) );
8567 ins_pipe(ialu_reg_reg);
8568 %}
8569
8570 // Zero-extend long
8571 instruct zerox_long(iRegL dst, iRegL src, immL_32bits mask ) %{
8572 match(Set dst (AndL src mask) );
8573 size(4);
8574 format %{ "SRL $src,0,$dst\t! zero-extend long" %}
8575 opcode(Assembler::srl_op3, Assembler::arith_op);
8576 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) );
8577 ins_pipe(ialu_reg_reg);
8578 %}
8579
8580
8581 //-----------
8582 // Long to Double conversion using V8 opcodes.
8583 // Still useful because cheetah traps and becomes
8584 // amazingly slow for some common numbers.
8585
8586 // Magic constant, 0x43300000
8587 instruct loadConI_x43300000(iRegI dst) %{
8588 effect(DEF dst);
8589 size(4);
8590 format %{ "SETHI HI(0x43300000),$dst\t! 2^52" %}
8591 ins_encode(SetHi22(0x43300000, dst));
8592 ins_pipe(ialu_none);
8593 %}
8594
8595 // Magic constant, 0x41f00000
8596 instruct loadConI_x41f00000(iRegI dst) %{
8597 effect(DEF dst);
8598 size(4);
8599 format %{ "SETHI HI(0x41f00000),$dst\t! 2^32" %}
8600 ins_encode(SetHi22(0x41f00000, dst));
8601 ins_pipe(ialu_none);
8602 %}
8603
8604 // Construct a double from two float halves
8605 instruct regDHi_regDLo_to_regD(regD_low dst, regD_low src1, regD_low src2) %{
8606 effect(DEF dst, USE src1, USE src2);
8607 size(8);
8608 format %{ "FMOVS $src1.hi,$dst.hi\n\t"
8609 "FMOVS $src2.lo,$dst.lo" %}
8610 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmovs_opf);
8611 ins_encode(form3_opf_rs2D_hi_rdD_hi(src1, dst), form3_opf_rs2D_lo_rdD_lo(src2, dst));
8612 ins_pipe(faddD_reg_reg);
8613 %}
8614
8615 // Convert integer in high half of a double register (in the lower half of
8616 // the double register file) to double
8617 instruct convI2D_regDHi_regD(regD dst, regD_low src) %{
8618 effect(DEF dst, USE src);
8619 size(4);
8620 format %{ "FITOD $src,$dst" %}
8621 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf);
8622 ins_encode(form3_opf_rs2D_rdD(src, dst));
8623 ins_pipe(fcvtLHi2D);
8624 %}
8625
8626 // Add float double precision
8627 instruct addD_regD_regD(regD dst, regD src1, regD src2) %{
8628 effect(DEF dst, USE src1, USE src2);
8629 size(4);
8630 format %{ "FADDD $src1,$src2,$dst" %}
8631 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::faddd_opf);
8632 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
8633 ins_pipe(faddD_reg_reg);
8634 %}
8635
8636 // Sub float double precision
8637 instruct subD_regD_regD(regD dst, regD src1, regD src2) %{
8638 effect(DEF dst, USE src1, USE src2);
8639 size(4);
8640 format %{ "FSUBD $src1,$src2,$dst" %}
8641 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubd_opf);
8642 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
8643 ins_pipe(faddD_reg_reg);
8644 %}
8645
8646 // Mul float double precision
8647 instruct mulD_regD_regD(regD dst, regD src1, regD src2) %{
8648 effect(DEF dst, USE src1, USE src2);
8649 size(4);
8650 format %{ "FMULD $src1,$src2,$dst" %}
8651 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuld_opf);
8652 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
8653 ins_pipe(fmulD_reg_reg);
8654 %}
8655
8656 instruct convL2D_reg_slow_fxtof(regD dst, stackSlotL src) %{
8657 match(Set dst (ConvL2D src));
8658 ins_cost(DEFAULT_COST*8 + MEMORY_REF_COST*6);
8659
8660 expand %{
8661 regD_low tmpsrc;
8662 iRegI ix43300000;
8663 iRegI ix41f00000;
8664 stackSlotL lx43300000;
8665 stackSlotL lx41f00000;
8666 regD_low dx43300000;
8667 regD dx41f00000;
8668 regD tmp1;
8669 regD_low tmp2;
8670 regD tmp3;
8671 regD tmp4;
8672
8673 stkL_to_regD(tmpsrc, src);
8674
8675 loadConI_x43300000(ix43300000);
8676 loadConI_x41f00000(ix41f00000);
8677 regI_to_stkLHi(lx43300000, ix43300000);
8678 regI_to_stkLHi(lx41f00000, ix41f00000);
8679 stkL_to_regD(dx43300000, lx43300000);
8680 stkL_to_regD(dx41f00000, lx41f00000);
8681
8682 convI2D_regDHi_regD(tmp1, tmpsrc);
8683 regDHi_regDLo_to_regD(tmp2, dx43300000, tmpsrc);
8684 subD_regD_regD(tmp3, tmp2, dx43300000);
8685 mulD_regD_regD(tmp4, tmp1, dx41f00000);
8686 addD_regD_regD(dst, tmp3, tmp4);
8687 %}
8688 %}
8689
8690 // Long to Double conversion using fast fxtof
8691 instruct convL2D_helper(regD dst, regD tmp) %{
8692 effect(DEF dst, USE tmp);
8693 size(4);
8694 format %{ "FXTOD $tmp,$dst" %}
8695 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtod_opf);
8696 ins_encode(form3_opf_rs2D_rdD(tmp, dst));
8697 ins_pipe(fcvtL2D);
8698 %}
8699
8700 instruct convL2D_stk_fast_fxtof(regD dst, stackSlotL src) %{
8701 predicate(VM_Version::has_fast_fxtof());
8702 match(Set dst (ConvL2D src));
8703 ins_cost(DEFAULT_COST + 3 * MEMORY_REF_COST);
8704 expand %{
8705 regD tmp;
8706 stkL_to_regD(tmp, src);
8707 convL2D_helper(dst, tmp);
8708 %}
8709 %}
8710
8711 instruct convL2D_reg(regD dst, iRegL src) %{
8712 predicate(UseVIS >= 3);
8713 match(Set dst (ConvL2D src));
8714 expand %{
8715 regD tmp;
8716 MoveL2D_reg_reg(tmp, src);
8717 convL2D_helper(dst, tmp);
8718 %}
8719 %}
8720
8721 // Long to Float conversion using fast fxtof
8722 instruct convL2F_helper(regF dst, regD tmp) %{
8723 effect(DEF dst, USE tmp);
8724 size(4);
8725 format %{ "FXTOS $tmp,$dst" %}
8726 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtos_opf);
8727 ins_encode(form3_opf_rs2D_rdF(tmp, dst));
8728 ins_pipe(fcvtL2F);
8729 %}
8730
8731 instruct convL2F_stk_fast_fxtof(regF dst, stackSlotL src) %{
8732 match(Set dst (ConvL2F src));
8733 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8734 expand %{
8735 regD tmp;
8736 stkL_to_regD(tmp, src);
8737 convL2F_helper(dst, tmp);
8738 %}
8739 %}
8740
8741 instruct convL2F_reg(regF dst, iRegL src) %{
8742 predicate(UseVIS >= 3);
8743 match(Set dst (ConvL2F src));
8744 ins_cost(DEFAULT_COST);
8745 expand %{
8746 regD tmp;
8747 MoveL2D_reg_reg(tmp, src);
8748 convL2F_helper(dst, tmp);
8749 %}
8750 %}
8751
8752 //-----------
8753
8754 instruct convL2I_reg(iRegI dst, iRegL src) %{
8755 match(Set dst (ConvL2I src));
8756 #ifndef _LP64
8757 format %{ "MOV $src.lo,$dst\t! long->int" %}
8758 ins_encode( form3_g0_rs2_rd_move_lo2( src, dst ) );
8759 ins_pipe(ialu_move_reg_I_to_L);
8760 #else
8761 size(4);
8762 format %{ "SRA $src,R_G0,$dst\t! long->int" %}
8763 ins_encode( form3_rs1_rd_signextend_lo1( src, dst ) );
8764 ins_pipe(ialu_reg);
8765 #endif
8766 %}
8767
8768 // Register Shift Right Immediate
8769 instruct shrL_reg_imm6_L2I(iRegI dst, iRegL src, immI_32_63 cnt) %{
8770 match(Set dst (ConvL2I (RShiftL src cnt)));
8771
8772 size(4);
8773 format %{ "SRAX $src,$cnt,$dst" %}
8774 opcode(Assembler::srax_op3, Assembler::arith_op);
8775 ins_encode( form3_sd_rs1_imm6_rd( src, cnt, dst ) );
8776 ins_pipe(ialu_reg_imm);
8777 %}
8778
8779 //----------Control Flow Instructions------------------------------------------
8780 // Compare Instructions
8781 // Compare Integers
8782 instruct compI_iReg(flagsReg icc, iRegI op1, iRegI op2) %{
8783 match(Set icc (CmpI op1 op2));
8784 effect( DEF icc, USE op1, USE op2 );
8785
8786 size(4);
8787 format %{ "CMP $op1,$op2" %}
8788 opcode(Assembler::subcc_op3, Assembler::arith_op);
8789 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8790 ins_pipe(ialu_cconly_reg_reg);
8791 %}
8792
8793 instruct compU_iReg(flagsRegU icc, iRegI op1, iRegI op2) %{
8794 match(Set icc (CmpU op1 op2));
8795
8796 size(4);
8797 format %{ "CMP $op1,$op2\t! unsigned" %}
8798 opcode(Assembler::subcc_op3, Assembler::arith_op);
8799 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8800 ins_pipe(ialu_cconly_reg_reg);
8801 %}
8802
8803 instruct compI_iReg_imm13(flagsReg icc, iRegI op1, immI13 op2) %{
8804 match(Set icc (CmpI op1 op2));
8805 effect( DEF icc, USE op1 );
8806
8807 size(4);
8808 format %{ "CMP $op1,$op2" %}
8809 opcode(Assembler::subcc_op3, Assembler::arith_op);
8810 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8811 ins_pipe(ialu_cconly_reg_imm);
8812 %}
8813
8814 instruct testI_reg_reg( flagsReg icc, iRegI op1, iRegI op2, immI0 zero ) %{
8815 match(Set icc (CmpI (AndI op1 op2) zero));
8816
8817 size(4);
8818 format %{ "BTST $op2,$op1" %}
8819 opcode(Assembler::andcc_op3, Assembler::arith_op);
8820 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8821 ins_pipe(ialu_cconly_reg_reg_zero);
8822 %}
8823
8824 instruct testI_reg_imm( flagsReg icc, iRegI op1, immI13 op2, immI0 zero ) %{
8825 match(Set icc (CmpI (AndI op1 op2) zero));
8826
8827 size(4);
8828 format %{ "BTST $op2,$op1" %}
8829 opcode(Assembler::andcc_op3, Assembler::arith_op);
8830 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8831 ins_pipe(ialu_cconly_reg_imm_zero);
8832 %}
8833
8834 instruct compL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2 ) %{
8835 match(Set xcc (CmpL op1 op2));
8836 effect( DEF xcc, USE op1, USE op2 );
8837
8838 size(4);
8839 format %{ "CMP $op1,$op2\t\t! long" %}
8840 opcode(Assembler::subcc_op3, Assembler::arith_op);
8841 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8842 ins_pipe(ialu_cconly_reg_reg);
8843 %}
8844
8845 instruct compL_reg_con(flagsRegL xcc, iRegL op1, immL13 con) %{
8846 match(Set xcc (CmpL op1 con));
8847 effect( DEF xcc, USE op1, USE con );
8848
8849 size(4);
8850 format %{ "CMP $op1,$con\t\t! long" %}
8851 opcode(Assembler::subcc_op3, Assembler::arith_op);
8852 ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) );
8853 ins_pipe(ialu_cconly_reg_reg);
8854 %}
8855
8856 instruct testL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2, immL0 zero) %{
8857 match(Set xcc (CmpL (AndL op1 op2) zero));
8858 effect( DEF xcc, USE op1, USE op2 );
8859
8860 size(4);
8861 format %{ "BTST $op1,$op2\t\t! long" %}
8862 opcode(Assembler::andcc_op3, Assembler::arith_op);
8863 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8864 ins_pipe(ialu_cconly_reg_reg);
8865 %}
8866
8867 // useful for checking the alignment of a pointer:
8868 instruct testL_reg_con(flagsRegL xcc, iRegL op1, immL13 con, immL0 zero) %{
8869 match(Set xcc (CmpL (AndL op1 con) zero));
8870 effect( DEF xcc, USE op1, USE con );
8871
8872 size(4);
8873 format %{ "BTST $op1,$con\t\t! long" %}
8874 opcode(Assembler::andcc_op3, Assembler::arith_op);
8875 ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) );
8876 ins_pipe(ialu_cconly_reg_reg);
8877 %}
8878
8879 instruct compU_iReg_imm13(flagsRegU icc, iRegI op1, immU12 op2 ) %{
8880 match(Set icc (CmpU op1 op2));
8881
8882 size(4);
8883 format %{ "CMP $op1,$op2\t! unsigned" %}
8884 opcode(Assembler::subcc_op3, Assembler::arith_op);
8885 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8886 ins_pipe(ialu_cconly_reg_imm);
8887 %}
8888
8889 // Compare Pointers
8890 instruct compP_iRegP(flagsRegP pcc, iRegP op1, iRegP op2 ) %{
8891 match(Set pcc (CmpP op1 op2));
8892
8893 size(4);
8894 format %{ "CMP $op1,$op2\t! ptr" %}
8895 opcode(Assembler::subcc_op3, Assembler::arith_op);
8896 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8897 ins_pipe(ialu_cconly_reg_reg);
8898 %}
8899
8900 instruct compP_iRegP_imm13(flagsRegP pcc, iRegP op1, immP13 op2 ) %{
8901 match(Set pcc (CmpP op1 op2));
8902
8903 size(4);
8904 format %{ "CMP $op1,$op2\t! ptr" %}
8905 opcode(Assembler::subcc_op3, Assembler::arith_op);
8906 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8907 ins_pipe(ialu_cconly_reg_imm);
8908 %}
8909
8910 // Compare Narrow oops
8911 instruct compN_iRegN(flagsReg icc, iRegN op1, iRegN op2 ) %{
8912 match(Set icc (CmpN op1 op2));
8913
8914 size(4);
8915 format %{ "CMP $op1,$op2\t! compressed ptr" %}
8916 opcode(Assembler::subcc_op3, Assembler::arith_op);
8917 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8918 ins_pipe(ialu_cconly_reg_reg);
8919 %}
8920
8921 instruct compN_iRegN_immN0(flagsReg icc, iRegN op1, immN0 op2 ) %{
8922 match(Set icc (CmpN op1 op2));
8923
8924 size(4);
8925 format %{ "CMP $op1,$op2\t! compressed ptr" %}
8926 opcode(Assembler::subcc_op3, Assembler::arith_op);
8927 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8928 ins_pipe(ialu_cconly_reg_imm);
8929 %}
8930
8931 //----------Max and Min--------------------------------------------------------
8932 // Min Instructions
8933 // Conditional move for min
8934 instruct cmovI_reg_lt( iRegI op2, iRegI op1, flagsReg icc ) %{
8935 effect( USE_DEF op2, USE op1, USE icc );
8936
8937 size(4);
8938 format %{ "MOVlt icc,$op1,$op2\t! min" %}
8939 opcode(Assembler::less);
8940 ins_encode( enc_cmov_reg_minmax(op2,op1) );
8941 ins_pipe(ialu_reg_flags);
8942 %}
8943
8944 // Min Register with Register.
8945 instruct minI_eReg(iRegI op1, iRegI op2) %{
8946 match(Set op2 (MinI op1 op2));
8947 ins_cost(DEFAULT_COST*2);
8948 expand %{
8949 flagsReg icc;
8950 compI_iReg(icc,op1,op2);
8951 cmovI_reg_lt(op2,op1,icc);
8952 %}
8953 %}
8954
8955 // Max Instructions
8956 // Conditional move for max
8957 instruct cmovI_reg_gt( iRegI op2, iRegI op1, flagsReg icc ) %{
8958 effect( USE_DEF op2, USE op1, USE icc );
8959 format %{ "MOVgt icc,$op1,$op2\t! max" %}
8960 opcode(Assembler::greater);
8961 ins_encode( enc_cmov_reg_minmax(op2,op1) );
8962 ins_pipe(ialu_reg_flags);
8963 %}
8964
8965 // Max Register with Register
8966 instruct maxI_eReg(iRegI op1, iRegI op2) %{
8967 match(Set op2 (MaxI op1 op2));
8968 ins_cost(DEFAULT_COST*2);
8969 expand %{
8970 flagsReg icc;
8971 compI_iReg(icc,op1,op2);
8972 cmovI_reg_gt(op2,op1,icc);
8973 %}
8974 %}
8975
8976
8977 //----------Float Compares----------------------------------------------------
8978 // Compare floating, generate condition code
8979 instruct cmpF_cc(flagsRegF fcc, regF src1, regF src2) %{
8980 match(Set fcc (CmpF src1 src2));
8981
8982 size(4);
8983 format %{ "FCMPs $fcc,$src1,$src2" %}
8984 opcode(Assembler::fpop2_op3, Assembler::arith_op, Assembler::fcmps_opf);
8985 ins_encode( form3_opf_rs1F_rs2F_fcc( src1, src2, fcc ) );
8986 ins_pipe(faddF_fcc_reg_reg_zero);
8987 %}
8988
8989 instruct cmpD_cc(flagsRegF fcc, regD src1, regD src2) %{
8990 match(Set fcc (CmpD src1 src2));
8991
8992 size(4);
8993 format %{ "FCMPd $fcc,$src1,$src2" %}
8994 opcode(Assembler::fpop2_op3, Assembler::arith_op, Assembler::fcmpd_opf);
8995 ins_encode( form3_opf_rs1D_rs2D_fcc( src1, src2, fcc ) );
8996 ins_pipe(faddD_fcc_reg_reg_zero);
8997 %}
8998
8999
9000 // Compare floating, generate -1,0,1
9001 instruct cmpF_reg(iRegI dst, regF src1, regF src2, flagsRegF0 fcc0) %{
9002 match(Set dst (CmpF3 src1 src2));
9003 effect(KILL fcc0);
9004 ins_cost(DEFAULT_COST*3+BRANCH_COST*3);
9005 format %{ "fcmpl $dst,$src1,$src2" %}
9006 // Primary = float
9007 opcode( true );
9008 ins_encode( floating_cmp( dst, src1, src2 ) );
9009 ins_pipe( floating_cmp );
9010 %}
9011
9012 instruct cmpD_reg(iRegI dst, regD src1, regD src2, flagsRegF0 fcc0) %{
9013 match(Set dst (CmpD3 src1 src2));
9014 effect(KILL fcc0);
9015 ins_cost(DEFAULT_COST*3+BRANCH_COST*3);
9016 format %{ "dcmpl $dst,$src1,$src2" %}
9017 // Primary = double (not float)
9018 opcode( false );
9019 ins_encode( floating_cmp( dst, src1, src2 ) );
9020 ins_pipe( floating_cmp );
9021 %}
9022
9023 //----------Branches---------------------------------------------------------
9024 // Jump
9025 // (compare 'operand indIndex' and 'instruct addP_reg_reg' above)
9026 instruct jumpXtnd(iRegX switch_val, o7RegI table) %{
9027 match(Jump switch_val);
9028 effect(TEMP table);
9029
9030 ins_cost(350);
9031
9032 format %{ "ADD $constanttablebase, $constantoffset, O7\n\t"
9033 "LD [O7 + $switch_val], O7\n\t"
9034 "JUMP O7" %}
9035 ins_encode %{
9036 // Calculate table address into a register.
9037 Register table_reg;
9038 Register label_reg = O7;
9039 // If we are calculating the size of this instruction don't trust
9040 // zero offsets because they might change when
9041 // MachConstantBaseNode decides to optimize the constant table
9042 // base.
9043 if ((constant_offset() == 0) && !Compile::current()->in_scratch_emit_size()) {
9044 table_reg = $constanttablebase;
9045 } else {
9046 table_reg = O7;
9047 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset, O7);
9048 __ add($constanttablebase, con_offset, table_reg);
9049 }
9050
9051 // Jump to base address + switch value
9052 __ ld_ptr(table_reg, $switch_val$$Register, label_reg);
9053 __ jmp(label_reg, G0);
9054 __ delayed()->nop();
9055 %}
9056 ins_pipe(ialu_reg_reg);
9057 %}
9058
9059 // Direct Branch. Use V8 version with longer range.
9060 instruct branch(label labl) %{
9061 match(Goto);
9062 effect(USE labl);
9063
9064 size(8);
9065 ins_cost(BRANCH_COST);
9066 format %{ "BA $labl" %}
9067 ins_encode %{
9068 Label* L = $labl$$label;
9069 __ ba(*L);
9070 __ delayed()->nop();
9071 %}
9072 ins_avoid_back_to_back(AVOID_BEFORE);
9073 ins_pipe(br);
9074 %}
9075
9076 // Direct Branch, short with no delay slot
9077 instruct branch_short(label labl) %{
9078 match(Goto);
9079 predicate(UseCBCond);
9080 effect(USE labl);
9081
9082 size(4);
9083 ins_cost(BRANCH_COST);
9084 format %{ "BA $labl\t! short branch" %}
9085 ins_encode %{
9086 Label* L = $labl$$label;
9087 assert(__ use_cbcond(*L), "back to back cbcond");
9088 __ ba_short(*L);
9089 %}
9090 ins_short_branch(1);
9091 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9092 ins_pipe(cbcond_reg_imm);
9093 %}
9094
9095 // Conditional Direct Branch
9096 instruct branchCon(cmpOp cmp, flagsReg icc, label labl) %{
9097 match(If cmp icc);
9098 effect(USE labl);
9099
9100 size(8);
9101 ins_cost(BRANCH_COST);
9102 format %{ "BP$cmp $icc,$labl" %}
9103 // Prim = bits 24-22, Secnd = bits 31-30
9104 ins_encode( enc_bp( labl, cmp, icc ) );
9105 ins_avoid_back_to_back(AVOID_BEFORE);
9106 ins_pipe(br_cc);
9107 %}
9108
9109 instruct branchConU(cmpOpU cmp, flagsRegU icc, label labl) %{
9110 match(If cmp icc);
9111 effect(USE labl);
9112
9113 ins_cost(BRANCH_COST);
9114 format %{ "BP$cmp $icc,$labl" %}
9115 // Prim = bits 24-22, Secnd = bits 31-30
9116 ins_encode( enc_bp( labl, cmp, icc ) );
9117 ins_avoid_back_to_back(AVOID_BEFORE);
9118 ins_pipe(br_cc);
9119 %}
9120
9121 instruct branchConP(cmpOpP cmp, flagsRegP pcc, label labl) %{
9122 match(If cmp pcc);
9123 effect(USE labl);
9124
9125 size(8);
9126 ins_cost(BRANCH_COST);
9127 format %{ "BP$cmp $pcc,$labl" %}
9128 ins_encode %{
9129 Label* L = $labl$$label;
9130 Assembler::Predict predict_taken =
9131 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9132
9133 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, *L);
9134 __ delayed()->nop();
9135 %}
9136 ins_avoid_back_to_back(AVOID_BEFORE);
9137 ins_pipe(br_cc);
9138 %}
9139
9140 instruct branchConF(cmpOpF cmp, flagsRegF fcc, label labl) %{
9141 match(If cmp fcc);
9142 effect(USE labl);
9143
9144 size(8);
9145 ins_cost(BRANCH_COST);
9146 format %{ "FBP$cmp $fcc,$labl" %}
9147 ins_encode %{
9148 Label* L = $labl$$label;
9149 Assembler::Predict predict_taken =
9150 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9151
9152 __ fbp( (Assembler::Condition)($cmp$$cmpcode), false, (Assembler::CC)($fcc$$reg), predict_taken, *L);
9153 __ delayed()->nop();
9154 %}
9155 ins_avoid_back_to_back(AVOID_BEFORE);
9156 ins_pipe(br_fcc);
9157 %}
9158
9159 instruct branchLoopEnd(cmpOp cmp, flagsReg icc, label labl) %{
9160 match(CountedLoopEnd cmp icc);
9161 effect(USE labl);
9162
9163 size(8);
9164 ins_cost(BRANCH_COST);
9165 format %{ "BP$cmp $icc,$labl\t! Loop end" %}
9166 // Prim = bits 24-22, Secnd = bits 31-30
9167 ins_encode( enc_bp( labl, cmp, icc ) );
9168 ins_avoid_back_to_back(AVOID_BEFORE);
9169 ins_pipe(br_cc);
9170 %}
9171
9172 instruct branchLoopEndU(cmpOpU cmp, flagsRegU icc, label labl) %{
9173 match(CountedLoopEnd cmp icc);
9174 effect(USE labl);
9175
9176 size(8);
9177 ins_cost(BRANCH_COST);
9178 format %{ "BP$cmp $icc,$labl\t! Loop end" %}
9179 // Prim = bits 24-22, Secnd = bits 31-30
9180 ins_encode( enc_bp( labl, cmp, icc ) );
9181 ins_avoid_back_to_back(AVOID_BEFORE);
9182 ins_pipe(br_cc);
9183 %}
9184
9185 // Compare and branch instructions
9186 instruct cmpI_reg_branch(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{
9187 match(If cmp (CmpI op1 op2));
9188 effect(USE labl, KILL icc);
9189
9190 size(12);
9191 ins_cost(BRANCH_COST);
9192 format %{ "CMP $op1,$op2\t! int\n\t"
9193 "BP$cmp $labl" %}
9194 ins_encode %{
9195 Label* L = $labl$$label;
9196 Assembler::Predict predict_taken =
9197 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9198 __ cmp($op1$$Register, $op2$$Register);
9199 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9200 __ delayed()->nop();
9201 %}
9202 ins_pipe(cmp_br_reg_reg);
9203 %}
9204
9205 instruct cmpI_imm_branch(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{
9206 match(If cmp (CmpI op1 op2));
9207 effect(USE labl, KILL icc);
9208
9209 size(12);
9210 ins_cost(BRANCH_COST);
9211 format %{ "CMP $op1,$op2\t! int\n\t"
9212 "BP$cmp $labl" %}
9213 ins_encode %{
9214 Label* L = $labl$$label;
9215 Assembler::Predict predict_taken =
9216 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9217 __ cmp($op1$$Register, $op2$$constant);
9218 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9219 __ delayed()->nop();
9220 %}
9221 ins_pipe(cmp_br_reg_imm);
9222 %}
9223
9224 instruct cmpU_reg_branch(cmpOpU cmp, iRegI op1, iRegI op2, label labl, flagsRegU icc) %{
9225 match(If cmp (CmpU op1 op2));
9226 effect(USE labl, KILL icc);
9227
9228 size(12);
9229 ins_cost(BRANCH_COST);
9230 format %{ "CMP $op1,$op2\t! unsigned\n\t"
9231 "BP$cmp $labl" %}
9232 ins_encode %{
9233 Label* L = $labl$$label;
9234 Assembler::Predict predict_taken =
9235 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9236 __ cmp($op1$$Register, $op2$$Register);
9237 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9238 __ delayed()->nop();
9239 %}
9240 ins_pipe(cmp_br_reg_reg);
9241 %}
9242
9243 instruct cmpU_imm_branch(cmpOpU cmp, iRegI op1, immI5 op2, label labl, flagsRegU icc) %{
9244 match(If cmp (CmpU op1 op2));
9245 effect(USE labl, KILL icc);
9246
9247 size(12);
9248 ins_cost(BRANCH_COST);
9249 format %{ "CMP $op1,$op2\t! unsigned\n\t"
9250 "BP$cmp $labl" %}
9251 ins_encode %{
9252 Label* L = $labl$$label;
9253 Assembler::Predict predict_taken =
9254 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9255 __ cmp($op1$$Register, $op2$$constant);
9256 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9257 __ delayed()->nop();
9258 %}
9259 ins_pipe(cmp_br_reg_imm);
9260 %}
9261
9262 instruct cmpL_reg_branch(cmpOp cmp, iRegL op1, iRegL op2, label labl, flagsRegL xcc) %{
9263 match(If cmp (CmpL op1 op2));
9264 effect(USE labl, KILL xcc);
9265
9266 size(12);
9267 ins_cost(BRANCH_COST);
9268 format %{ "CMP $op1,$op2\t! long\n\t"
9269 "BP$cmp $labl" %}
9270 ins_encode %{
9271 Label* L = $labl$$label;
9272 Assembler::Predict predict_taken =
9273 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9274 __ cmp($op1$$Register, $op2$$Register);
9275 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L);
9276 __ delayed()->nop();
9277 %}
9278 ins_pipe(cmp_br_reg_reg);
9279 %}
9280
9281 instruct cmpL_imm_branch(cmpOp cmp, iRegL op1, immL5 op2, label labl, flagsRegL xcc) %{
9282 match(If cmp (CmpL op1 op2));
9283 effect(USE labl, KILL xcc);
9284
9285 size(12);
9286 ins_cost(BRANCH_COST);
9287 format %{ "CMP $op1,$op2\t! long\n\t"
9288 "BP$cmp $labl" %}
9289 ins_encode %{
9290 Label* L = $labl$$label;
9291 Assembler::Predict predict_taken =
9292 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9293 __ cmp($op1$$Register, $op2$$constant);
9294 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L);
9295 __ delayed()->nop();
9296 %}
9297 ins_pipe(cmp_br_reg_imm);
9298 %}
9299
9300 // Compare Pointers and branch
9301 instruct cmpP_reg_branch(cmpOpP cmp, iRegP op1, iRegP op2, label labl, flagsRegP pcc) %{
9302 match(If cmp (CmpP op1 op2));
9303 effect(USE labl, KILL pcc);
9304
9305 size(12);
9306 ins_cost(BRANCH_COST);
9307 format %{ "CMP $op1,$op2\t! ptr\n\t"
9308 "B$cmp $labl" %}
9309 ins_encode %{
9310 Label* L = $labl$$label;
9311 Assembler::Predict predict_taken =
9312 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9313 __ cmp($op1$$Register, $op2$$Register);
9314 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, *L);
9315 __ delayed()->nop();
9316 %}
9317 ins_pipe(cmp_br_reg_reg);
9318 %}
9319
9320 instruct cmpP_null_branch(cmpOpP cmp, iRegP op1, immP0 null, label labl, flagsRegP pcc) %{
9321 match(If cmp (CmpP op1 null));
9322 effect(USE labl, KILL pcc);
9323
9324 size(12);
9325 ins_cost(BRANCH_COST);
9326 format %{ "CMP $op1,0\t! ptr\n\t"
9327 "B$cmp $labl" %}
9328 ins_encode %{
9329 Label* L = $labl$$label;
9330 Assembler::Predict predict_taken =
9331 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9332 __ cmp($op1$$Register, G0);
9333 // bpr() is not used here since it has shorter distance.
9334 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, *L);
9335 __ delayed()->nop();
9336 %}
9337 ins_pipe(cmp_br_reg_reg);
9338 %}
9339
9340 instruct cmpN_reg_branch(cmpOp cmp, iRegN op1, iRegN op2, label labl, flagsReg icc) %{
9341 match(If cmp (CmpN op1 op2));
9342 effect(USE labl, KILL icc);
9343
9344 size(12);
9345 ins_cost(BRANCH_COST);
9346 format %{ "CMP $op1,$op2\t! compressed ptr\n\t"
9347 "BP$cmp $labl" %}
9348 ins_encode %{
9349 Label* L = $labl$$label;
9350 Assembler::Predict predict_taken =
9351 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9352 __ cmp($op1$$Register, $op2$$Register);
9353 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9354 __ delayed()->nop();
9355 %}
9356 ins_pipe(cmp_br_reg_reg);
9357 %}
9358
9359 instruct cmpN_null_branch(cmpOp cmp, iRegN op1, immN0 null, label labl, flagsReg icc) %{
9360 match(If cmp (CmpN op1 null));
9361 effect(USE labl, KILL icc);
9362
9363 size(12);
9364 ins_cost(BRANCH_COST);
9365 format %{ "CMP $op1,0\t! compressed ptr\n\t"
9366 "BP$cmp $labl" %}
9367 ins_encode %{
9368 Label* L = $labl$$label;
9369 Assembler::Predict predict_taken =
9370 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9371 __ cmp($op1$$Register, G0);
9372 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9373 __ delayed()->nop();
9374 %}
9375 ins_pipe(cmp_br_reg_reg);
9376 %}
9377
9378 // Loop back branch
9379 instruct cmpI_reg_branchLoopEnd(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{
9380 match(CountedLoopEnd cmp (CmpI op1 op2));
9381 effect(USE labl, KILL icc);
9382
9383 size(12);
9384 ins_cost(BRANCH_COST);
9385 format %{ "CMP $op1,$op2\t! int\n\t"
9386 "BP$cmp $labl\t! Loop end" %}
9387 ins_encode %{
9388 Label* L = $labl$$label;
9389 Assembler::Predict predict_taken =
9390 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9391 __ cmp($op1$$Register, $op2$$Register);
9392 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9393 __ delayed()->nop();
9394 %}
9395 ins_pipe(cmp_br_reg_reg);
9396 %}
9397
9398 instruct cmpI_imm_branchLoopEnd(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{
9399 match(CountedLoopEnd cmp (CmpI op1 op2));
9400 effect(USE labl, KILL icc);
9401
9402 size(12);
9403 ins_cost(BRANCH_COST);
9404 format %{ "CMP $op1,$op2\t! int\n\t"
9405 "BP$cmp $labl\t! Loop end" %}
9406 ins_encode %{
9407 Label* L = $labl$$label;
9408 Assembler::Predict predict_taken =
9409 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9410 __ cmp($op1$$Register, $op2$$constant);
9411 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9412 __ delayed()->nop();
9413 %}
9414 ins_pipe(cmp_br_reg_imm);
9415 %}
9416
9417 // Short compare and branch instructions
9418 instruct cmpI_reg_branch_short(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{
9419 match(If cmp (CmpI op1 op2));
9420 predicate(UseCBCond);
9421 effect(USE labl, KILL icc);
9422
9423 size(4);
9424 ins_cost(BRANCH_COST);
9425 format %{ "CWB$cmp $op1,$op2,$labl\t! int" %}
9426 ins_encode %{
9427 Label* L = $labl$$label;
9428 assert(__ use_cbcond(*L), "back to back cbcond");
9429 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L);
9430 %}
9431 ins_short_branch(1);
9432 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9433 ins_pipe(cbcond_reg_reg);
9434 %}
9435
9436 instruct cmpI_imm_branch_short(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{
9437 match(If cmp (CmpI op1 op2));
9438 predicate(UseCBCond);
9439 effect(USE labl, KILL icc);
9440
9441 size(4);
9442 ins_cost(BRANCH_COST);
9443 format %{ "CWB$cmp $op1,$op2,$labl\t! int" %}
9444 ins_encode %{
9445 Label* L = $labl$$label;
9446 assert(__ use_cbcond(*L), "back to back cbcond");
9447 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$constant, *L);
9448 %}
9449 ins_short_branch(1);
9450 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9451 ins_pipe(cbcond_reg_imm);
9452 %}
9453
9454 instruct cmpU_reg_branch_short(cmpOpU cmp, iRegI op1, iRegI op2, label labl, flagsRegU icc) %{
9455 match(If cmp (CmpU op1 op2));
9456 predicate(UseCBCond);
9457 effect(USE labl, KILL icc);
9458
9459 size(4);
9460 ins_cost(BRANCH_COST);
9461 format %{ "CWB$cmp $op1,$op2,$labl\t! unsigned" %}
9462 ins_encode %{
9463 Label* L = $labl$$label;
9464 assert(__ use_cbcond(*L), "back to back cbcond");
9465 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L);
9466 %}
9467 ins_short_branch(1);
9468 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9469 ins_pipe(cbcond_reg_reg);
9470 %}
9471
9472 instruct cmpU_imm_branch_short(cmpOpU cmp, iRegI op1, immI5 op2, label labl, flagsRegU icc) %{
9473 match(If cmp (CmpU op1 op2));
9474 predicate(UseCBCond);
9475 effect(USE labl, KILL icc);
9476
9477 size(4);
9478 ins_cost(BRANCH_COST);
9479 format %{ "CWB$cmp $op1,$op2,$labl\t! unsigned" %}
9480 ins_encode %{
9481 Label* L = $labl$$label;
9482 assert(__ use_cbcond(*L), "back to back cbcond");
9483 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$constant, *L);
9484 %}
9485 ins_short_branch(1);
9486 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9487 ins_pipe(cbcond_reg_imm);
9488 %}
9489
9490 instruct cmpL_reg_branch_short(cmpOp cmp, iRegL op1, iRegL op2, label labl, flagsRegL xcc) %{
9491 match(If cmp (CmpL op1 op2));
9492 predicate(UseCBCond);
9493 effect(USE labl, KILL xcc);
9494
9495 size(4);
9496 ins_cost(BRANCH_COST);
9497 format %{ "CXB$cmp $op1,$op2,$labl\t! long" %}
9498 ins_encode %{
9499 Label* L = $labl$$label;
9500 assert(__ use_cbcond(*L), "back to back cbcond");
9501 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::xcc, $op1$$Register, $op2$$Register, *L);
9502 %}
9503 ins_short_branch(1);
9504 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9505 ins_pipe(cbcond_reg_reg);
9506 %}
9507
9508 instruct cmpL_imm_branch_short(cmpOp cmp, iRegL op1, immL5 op2, label labl, flagsRegL xcc) %{
9509 match(If cmp (CmpL op1 op2));
9510 predicate(UseCBCond);
9511 effect(USE labl, KILL xcc);
9512
9513 size(4);
9514 ins_cost(BRANCH_COST);
9515 format %{ "CXB$cmp $op1,$op2,$labl\t! long" %}
9516 ins_encode %{
9517 Label* L = $labl$$label;
9518 assert(__ use_cbcond(*L), "back to back cbcond");
9519 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::xcc, $op1$$Register, $op2$$constant, *L);
9520 %}
9521 ins_short_branch(1);
9522 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9523 ins_pipe(cbcond_reg_imm);
9524 %}
9525
9526 // Compare Pointers and branch
9527 instruct cmpP_reg_branch_short(cmpOpP cmp, iRegP op1, iRegP op2, label labl, flagsRegP pcc) %{
9528 match(If cmp (CmpP op1 op2));
9529 predicate(UseCBCond);
9530 effect(USE labl, KILL pcc);
9531
9532 size(4);
9533 ins_cost(BRANCH_COST);
9534 #ifdef _LP64
9535 format %{ "CXB$cmp $op1,$op2,$labl\t! ptr" %}
9536 #else
9537 format %{ "CWB$cmp $op1,$op2,$labl\t! ptr" %}
9538 #endif
9539 ins_encode %{
9540 Label* L = $labl$$label;
9541 assert(__ use_cbcond(*L), "back to back cbcond");
9542 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::ptr_cc, $op1$$Register, $op2$$Register, *L);
9543 %}
9544 ins_short_branch(1);
9545 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9546 ins_pipe(cbcond_reg_reg);
9547 %}
9548
9549 instruct cmpP_null_branch_short(cmpOpP cmp, iRegP op1, immP0 null, label labl, flagsRegP pcc) %{
9550 match(If cmp (CmpP op1 null));
9551 predicate(UseCBCond);
9552 effect(USE labl, KILL pcc);
9553
9554 size(4);
9555 ins_cost(BRANCH_COST);
9556 #ifdef _LP64
9557 format %{ "CXB$cmp $op1,0,$labl\t! ptr" %}
9558 #else
9559 format %{ "CWB$cmp $op1,0,$labl\t! ptr" %}
9560 #endif
9561 ins_encode %{
9562 Label* L = $labl$$label;
9563 assert(__ use_cbcond(*L), "back to back cbcond");
9564 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::ptr_cc, $op1$$Register, G0, *L);
9565 %}
9566 ins_short_branch(1);
9567 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9568 ins_pipe(cbcond_reg_reg);
9569 %}
9570
9571 instruct cmpN_reg_branch_short(cmpOp cmp, iRegN op1, iRegN op2, label labl, flagsReg icc) %{
9572 match(If cmp (CmpN op1 op2));
9573 predicate(UseCBCond);
9574 effect(USE labl, KILL icc);
9575
9576 size(4);
9577 ins_cost(BRANCH_COST);
9578 format %{ "CWB$cmp $op1,$op2,$labl\t! compressed ptr" %}
9579 ins_encode %{
9580 Label* L = $labl$$label;
9581 assert(__ use_cbcond(*L), "back to back cbcond");
9582 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L);
9583 %}
9584 ins_short_branch(1);
9585 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9586 ins_pipe(cbcond_reg_reg);
9587 %}
9588
9589 instruct cmpN_null_branch_short(cmpOp cmp, iRegN op1, immN0 null, label labl, flagsReg icc) %{
9590 match(If cmp (CmpN op1 null));
9591 predicate(UseCBCond);
9592 effect(USE labl, KILL icc);
9593
9594 size(4);
9595 ins_cost(BRANCH_COST);
9596 format %{ "CWB$cmp $op1,0,$labl\t! compressed ptr" %}
9597 ins_encode %{
9598 Label* L = $labl$$label;
9599 assert(__ use_cbcond(*L), "back to back cbcond");
9600 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, G0, *L);
9601 %}
9602 ins_short_branch(1);
9603 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9604 ins_pipe(cbcond_reg_reg);
9605 %}
9606
9607 // Loop back branch
9608 instruct cmpI_reg_branchLoopEnd_short(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{
9609 match(CountedLoopEnd cmp (CmpI op1 op2));
9610 predicate(UseCBCond);
9611 effect(USE labl, KILL icc);
9612
9613 size(4);
9614 ins_cost(BRANCH_COST);
9615 format %{ "CWB$cmp $op1,$op2,$labl\t! Loop end" %}
9616 ins_encode %{
9617 Label* L = $labl$$label;
9618 assert(__ use_cbcond(*L), "back to back cbcond");
9619 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L);
9620 %}
9621 ins_short_branch(1);
9622 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9623 ins_pipe(cbcond_reg_reg);
9624 %}
9625
9626 instruct cmpI_imm_branchLoopEnd_short(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{
9627 match(CountedLoopEnd cmp (CmpI op1 op2));
9628 predicate(UseCBCond);
9629 effect(USE labl, KILL icc);
9630
9631 size(4);
9632 ins_cost(BRANCH_COST);
9633 format %{ "CWB$cmp $op1,$op2,$labl\t! Loop end" %}
9634 ins_encode %{
9635 Label* L = $labl$$label;
9636 assert(__ use_cbcond(*L), "back to back cbcond");
9637 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$constant, *L);
9638 %}
9639 ins_short_branch(1);
9640 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9641 ins_pipe(cbcond_reg_imm);
9642 %}
9643
9644 // Branch-on-register tests all 64 bits. We assume that values
9645 // in 64-bit registers always remains zero or sign extended
9646 // unless our code munges the high bits. Interrupts can chop
9647 // the high order bits to zero or sign at any time.
9648 instruct branchCon_regI(cmpOp_reg cmp, iRegI op1, immI0 zero, label labl) %{
9649 match(If cmp (CmpI op1 zero));
9650 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf));
9651 effect(USE labl);
9652
9653 size(8);
9654 ins_cost(BRANCH_COST);
9655 format %{ "BR$cmp $op1,$labl" %}
9656 ins_encode( enc_bpr( labl, cmp, op1 ) );
9657 ins_avoid_back_to_back(AVOID_BEFORE);
9658 ins_pipe(br_reg);
9659 %}
9660
9661 instruct branchCon_regP(cmpOp_reg cmp, iRegP op1, immP0 null, label labl) %{
9662 match(If cmp (CmpP op1 null));
9663 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf));
9664 effect(USE labl);
9665
9666 size(8);
9667 ins_cost(BRANCH_COST);
9668 format %{ "BR$cmp $op1,$labl" %}
9669 ins_encode( enc_bpr( labl, cmp, op1 ) );
9670 ins_avoid_back_to_back(AVOID_BEFORE);
9671 ins_pipe(br_reg);
9672 %}
9673
9674 instruct branchCon_regL(cmpOp_reg cmp, iRegL op1, immL0 zero, label labl) %{
9675 match(If cmp (CmpL op1 zero));
9676 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf));
9677 effect(USE labl);
9678
9679 size(8);
9680 ins_cost(BRANCH_COST);
9681 format %{ "BR$cmp $op1,$labl" %}
9682 ins_encode( enc_bpr( labl, cmp, op1 ) );
9683 ins_avoid_back_to_back(AVOID_BEFORE);
9684 ins_pipe(br_reg);
9685 %}
9686
9687
9688 // ============================================================================
9689 // Long Compare
9690 //
9691 // Currently we hold longs in 2 registers. Comparing such values efficiently
9692 // is tricky. The flavor of compare used depends on whether we are testing
9693 // for LT, LE, or EQ. For a simple LT test we can check just the sign bit.
9694 // The GE test is the negated LT test. The LE test can be had by commuting
9695 // the operands (yielding a GE test) and then negating; negate again for the
9696 // GT test. The EQ test is done by ORcc'ing the high and low halves, and the
9697 // NE test is negated from that.
9698
9699 // Due to a shortcoming in the ADLC, it mixes up expressions like:
9700 // (foo (CmpI (CmpL X Y) 0)) and (bar (CmpI (CmpL X 0L) 0)). Note the
9701 // difference between 'Y' and '0L'. The tree-matches for the CmpI sections
9702 // are collapsed internally in the ADLC's dfa-gen code. The match for
9703 // (CmpI (CmpL X Y) 0) is silently replaced with (CmpI (CmpL X 0L) 0) and the
9704 // foo match ends up with the wrong leaf. One fix is to not match both
9705 // reg-reg and reg-zero forms of long-compare. This is unfortunate because
9706 // both forms beat the trinary form of long-compare and both are very useful
9707 // on Intel which has so few registers.
9708
9709 instruct branchCon_long(cmpOp cmp, flagsRegL xcc, label labl) %{
9710 match(If cmp xcc);
9711 effect(USE labl);
9712
9713 size(8);
9714 ins_cost(BRANCH_COST);
9715 format %{ "BP$cmp $xcc,$labl" %}
9716 ins_encode %{
9717 Label* L = $labl$$label;
9718 Assembler::Predict predict_taken =
9719 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9720
9721 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L);
9722 __ delayed()->nop();
9723 %}
9724 ins_avoid_back_to_back(AVOID_BEFORE);
9725 ins_pipe(br_cc);
9726 %}
9727
9728 // Manifest a CmpL3 result in an integer register. Very painful.
9729 // This is the test to avoid.
9730 instruct cmpL3_reg_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg ccr ) %{
9731 match(Set dst (CmpL3 src1 src2) );
9732 effect( KILL ccr );
9733 ins_cost(6*DEFAULT_COST);
9734 size(24);
9735 format %{ "CMP $src1,$src2\t\t! long\n"
9736 "\tBLT,a,pn done\n"
9737 "\tMOV -1,$dst\t! delay slot\n"
9738 "\tBGT,a,pn done\n"
9739 "\tMOV 1,$dst\t! delay slot\n"
9740 "\tCLR $dst\n"
9741 "done:" %}
9742 ins_encode( cmpl_flag(src1,src2,dst) );
9743 ins_pipe(cmpL_reg);
9744 %}
9745
9746 // Conditional move
9747 instruct cmovLL_reg(cmpOp cmp, flagsRegL xcc, iRegL dst, iRegL src) %{
9748 match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src)));
9749 ins_cost(150);
9750 format %{ "MOV$cmp $xcc,$src,$dst\t! long" %}
9751 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
9752 ins_pipe(ialu_reg);
9753 %}
9754
9755 instruct cmovLL_imm(cmpOp cmp, flagsRegL xcc, iRegL dst, immL0 src) %{
9756 match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src)));
9757 ins_cost(140);
9758 format %{ "MOV$cmp $xcc,$src,$dst\t! long" %}
9759 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) );
9760 ins_pipe(ialu_imm);
9761 %}
9762
9763 instruct cmovIL_reg(cmpOp cmp, flagsRegL xcc, iRegI dst, iRegI src) %{
9764 match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src)));
9765 ins_cost(150);
9766 format %{ "MOV$cmp $xcc,$src,$dst" %}
9767 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
9768 ins_pipe(ialu_reg);
9769 %}
9770
9771 instruct cmovIL_imm(cmpOp cmp, flagsRegL xcc, iRegI dst, immI11 src) %{
9772 match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src)));
9773 ins_cost(140);
9774 format %{ "MOV$cmp $xcc,$src,$dst" %}
9775 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) );
9776 ins_pipe(ialu_imm);
9777 %}
9778
9779 instruct cmovNL_reg(cmpOp cmp, flagsRegL xcc, iRegN dst, iRegN src) %{
9780 match(Set dst (CMoveN (Binary cmp xcc) (Binary dst src)));
9781 ins_cost(150);
9782 format %{ "MOV$cmp $xcc,$src,$dst" %}
9783 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
9784 ins_pipe(ialu_reg);
9785 %}
9786
9787 instruct cmovPL_reg(cmpOp cmp, flagsRegL xcc, iRegP dst, iRegP src) %{
9788 match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src)));
9789 ins_cost(150);
9790 format %{ "MOV$cmp $xcc,$src,$dst" %}
9791 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
9792 ins_pipe(ialu_reg);
9793 %}
9794
9795 instruct cmovPL_imm(cmpOp cmp, flagsRegL xcc, iRegP dst, immP0 src) %{
9796 match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src)));
9797 ins_cost(140);
9798 format %{ "MOV$cmp $xcc,$src,$dst" %}
9799 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) );
9800 ins_pipe(ialu_imm);
9801 %}
9802
9803 instruct cmovFL_reg(cmpOp cmp, flagsRegL xcc, regF dst, regF src) %{
9804 match(Set dst (CMoveF (Binary cmp xcc) (Binary dst src)));
9805 ins_cost(150);
9806 opcode(0x101);
9807 format %{ "FMOVS$cmp $xcc,$src,$dst" %}
9808 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::xcc)) );
9809 ins_pipe(int_conditional_float_move);
9810 %}
9811
9812 instruct cmovDL_reg(cmpOp cmp, flagsRegL xcc, regD dst, regD src) %{
9813 match(Set dst (CMoveD (Binary cmp xcc) (Binary dst src)));
9814 ins_cost(150);
9815 opcode(0x102);
9816 format %{ "FMOVD$cmp $xcc,$src,$dst" %}
9817 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::xcc)) );
9818 ins_pipe(int_conditional_float_move);
9819 %}
9820
9821 // ============================================================================
9822 // Safepoint Instruction
9823 instruct safePoint_poll(iRegP poll) %{
9824 match(SafePoint poll);
9825 effect(USE poll);
9826
9827 size(4);
9828 #ifdef _LP64
9829 format %{ "LDX [$poll],R_G0\t! Safepoint: poll for GC" %}
9830 #else
9831 format %{ "LDUW [$poll],R_G0\t! Safepoint: poll for GC" %}
9832 #endif
9833 ins_encode %{
9834 __ relocate(relocInfo::poll_type);
9835 __ ld_ptr($poll$$Register, 0, G0);
9836 %}
9837 ins_pipe(loadPollP);
9838 %}
9839
9840 // ============================================================================
9841 // Call Instructions
9842 // Call Java Static Instruction
9843 instruct CallStaticJavaDirect( method meth ) %{
9844 match(CallStaticJava);
9845 predicate(! ((CallStaticJavaNode*)n)->is_method_handle_invoke());
9846 effect(USE meth);
9847
9848 size(8);
9849 ins_cost(CALL_COST);
9850 format %{ "CALL,static ; NOP ==> " %}
9851 ins_encode( Java_Static_Call( meth ), call_epilog );
9852 ins_avoid_back_to_back(AVOID_BEFORE);
9853 ins_pipe(simple_call);
9854 %}
9855
9856 // Call Java Static Instruction (method handle version)
9857 instruct CallStaticJavaHandle(method meth, l7RegP l7_mh_SP_save) %{
9858 match(CallStaticJava);
9859 predicate(((CallStaticJavaNode*)n)->is_method_handle_invoke());
9860 effect(USE meth, KILL l7_mh_SP_save);
9861
9862 size(16);
9863 ins_cost(CALL_COST);
9864 format %{ "CALL,static/MethodHandle" %}
9865 ins_encode(preserve_SP, Java_Static_Call(meth), restore_SP, call_epilog);
9866 ins_pipe(simple_call);
9867 %}
9868
9869 // Call Java Dynamic Instruction
9870 instruct CallDynamicJavaDirect( method meth ) %{
9871 match(CallDynamicJava);
9872 effect(USE meth);
9873
9874 ins_cost(CALL_COST);
9875 format %{ "SET (empty),R_G5\n\t"
9876 "CALL,dynamic ; NOP ==> " %}
9877 ins_encode( Java_Dynamic_Call( meth ), call_epilog );
9878 ins_pipe(call);
9879 %}
9880
9881 // Call Runtime Instruction
9882 instruct CallRuntimeDirect(method meth, l7RegP l7) %{
9883 match(CallRuntime);
9884 effect(USE meth, KILL l7);
9885 ins_cost(CALL_COST);
9886 format %{ "CALL,runtime" %}
9887 ins_encode( Java_To_Runtime( meth ),
9888 call_epilog, adjust_long_from_native_call );
9889 ins_avoid_back_to_back(AVOID_BEFORE);
9890 ins_pipe(simple_call);
9891 %}
9892
9893 // Call runtime without safepoint - same as CallRuntime
9894 instruct CallLeafDirect(method meth, l7RegP l7) %{
9895 match(CallLeaf);
9896 effect(USE meth, KILL l7);
9897 ins_cost(CALL_COST);
9898 format %{ "CALL,runtime leaf" %}
9899 ins_encode( Java_To_Runtime( meth ),
9900 call_epilog,
9901 adjust_long_from_native_call );
9902 ins_avoid_back_to_back(AVOID_BEFORE);
9903 ins_pipe(simple_call);
9904 %}
9905
9906 // Call runtime without safepoint - same as CallLeaf
9907 instruct CallLeafNoFPDirect(method meth, l7RegP l7) %{
9908 match(CallLeafNoFP);
9909 effect(USE meth, KILL l7);
9910 ins_cost(CALL_COST);
9911 format %{ "CALL,runtime leaf nofp" %}
9912 ins_encode( Java_To_Runtime( meth ),
9913 call_epilog,
9914 adjust_long_from_native_call );
9915 ins_avoid_back_to_back(AVOID_BEFORE);
9916 ins_pipe(simple_call);
9917 %}
9918
9919 // Tail Call; Jump from runtime stub to Java code.
9920 // Also known as an 'interprocedural jump'.
9921 // Target of jump will eventually return to caller.
9922 // TailJump below removes the return address.
9923 instruct TailCalljmpInd(g3RegP jump_target, inline_cache_regP method_oop) %{
9924 match(TailCall jump_target method_oop );
9925
9926 ins_cost(CALL_COST);
9927 format %{ "Jmp $jump_target ; NOP \t! $method_oop holds method oop" %}
9928 ins_encode(form_jmpl(jump_target));
9929 ins_avoid_back_to_back(AVOID_BEFORE);
9930 ins_pipe(tail_call);
9931 %}
9932
9933
9934 // Return Instruction
9935 instruct Ret() %{
9936 match(Return);
9937
9938 // The epilogue node did the ret already.
9939 size(0);
9940 format %{ "! return" %}
9941 ins_encode();
9942 ins_pipe(empty);
9943 %}
9944
9945
9946 // Tail Jump; remove the return address; jump to target.
9947 // TailCall above leaves the return address around.
9948 // TailJump is used in only one place, the rethrow_Java stub (fancy_jump=2).
9949 // ex_oop (Exception Oop) is needed in %o0 at the jump. As there would be a
9950 // "restore" before this instruction (in Epilogue), we need to materialize it
9951 // in %i0.
9952 instruct tailjmpInd(g1RegP jump_target, i0RegP ex_oop) %{
9953 match( TailJump jump_target ex_oop );
9954 ins_cost(CALL_COST);
9955 format %{ "! discard R_O7\n\t"
9956 "Jmp $jump_target ; ADD O7,8,O1 \t! $ex_oop holds exc. oop" %}
9957 ins_encode(form_jmpl_set_exception_pc(jump_target));
9958 // opcode(Assembler::jmpl_op3, Assembler::arith_op);
9959 // The hack duplicates the exception oop into G3, so that CreateEx can use it there.
9960 // ins_encode( form3_rs1_simm13_rd( jump_target, 0x00, R_G0 ), move_return_pc_to_o1() );
9961 ins_avoid_back_to_back(AVOID_BEFORE);
9962 ins_pipe(tail_call);
9963 %}
9964
9965 // Create exception oop: created by stack-crawling runtime code.
9966 // Created exception is now available to this handler, and is setup
9967 // just prior to jumping to this handler. No code emitted.
9968 instruct CreateException( o0RegP ex_oop )
9969 %{
9970 match(Set ex_oop (CreateEx));
9971 ins_cost(0);
9972
9973 size(0);
9974 // use the following format syntax
9975 format %{ "! exception oop is in R_O0; no code emitted" %}
9976 ins_encode();
9977 ins_pipe(empty);
9978 %}
9979
9980
9981 // Rethrow exception:
9982 // The exception oop will come in the first argument position.
9983 // Then JUMP (not call) to the rethrow stub code.
9984 instruct RethrowException()
9985 %{
9986 match(Rethrow);
9987 ins_cost(CALL_COST);
9988
9989 // use the following format syntax
9990 format %{ "Jmp rethrow_stub" %}
9991 ins_encode(enc_rethrow);
9992 ins_avoid_back_to_back(AVOID_BEFORE);
9993 ins_pipe(tail_call);
9994 %}
9995
9996
9997 // Die now
9998 instruct ShouldNotReachHere( )
9999 %{
10000 match(Halt);
10001 ins_cost(CALL_COST);
10002
10003 size(4);
10004 // Use the following format syntax
10005 format %{ "ILLTRAP ; ShouldNotReachHere" %}
10006 ins_encode( form2_illtrap() );
10007 ins_pipe(tail_call);
10008 %}
10009
10010 // ============================================================================
10011 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass
10012 // array for an instance of the superklass. Set a hidden internal cache on a
10013 // hit (cache is checked with exposed code in gen_subtype_check()). Return
10014 // not zero for a miss or zero for a hit. The encoding ALSO sets flags.
10015 instruct partialSubtypeCheck( o0RegP index, o1RegP sub, o2RegP super, flagsRegP pcc, o7RegP o7 ) %{
10016 match(Set index (PartialSubtypeCheck sub super));
10017 effect( KILL pcc, KILL o7 );
10018 ins_cost(DEFAULT_COST*10);
10019 format %{ "CALL PartialSubtypeCheck\n\tNOP" %}
10020 ins_encode( enc_PartialSubtypeCheck() );
10021 ins_avoid_back_to_back(AVOID_BEFORE);
10022 ins_pipe(partial_subtype_check_pipe);
10023 %}
10024
10025 instruct partialSubtypeCheck_vs_zero( flagsRegP pcc, o1RegP sub, o2RegP super, immP0 zero, o0RegP idx, o7RegP o7 ) %{
10026 match(Set pcc (CmpP (PartialSubtypeCheck sub super) zero));
10027 effect( KILL idx, KILL o7 );
10028 ins_cost(DEFAULT_COST*10);
10029 format %{ "CALL PartialSubtypeCheck\n\tNOP\t# (sets condition codes)" %}
10030 ins_encode( enc_PartialSubtypeCheck() );
10031 ins_avoid_back_to_back(AVOID_BEFORE);
10032 ins_pipe(partial_subtype_check_pipe);
10033 %}
10034
10035
10036 // ============================================================================
10037 // inlined locking and unlocking
10038
10039 instruct cmpFastLock(flagsRegP pcc, iRegP object, o1RegP box, iRegP scratch2, o7RegP scratch ) %{
10040 match(Set pcc (FastLock object box));
10041
10042 effect(TEMP scratch2, USE_KILL box, KILL scratch);
10043 ins_cost(100);
10044
10045 format %{ "FASTLOCK $object,$box\t! kills $box,$scratch,$scratch2" %}
10046 ins_encode( Fast_Lock(object, box, scratch, scratch2) );
10047 ins_pipe(long_memory_op);
10048 %}
10049
10050
10051 instruct cmpFastUnlock(flagsRegP pcc, iRegP object, o1RegP box, iRegP scratch2, o7RegP scratch ) %{
10052 match(Set pcc (FastUnlock object box));
10053 effect(TEMP scratch2, USE_KILL box, KILL scratch);
10054 ins_cost(100);
10055
10056 format %{ "FASTUNLOCK $object,$box\t! kills $box,$scratch,$scratch2" %}
10057 ins_encode( Fast_Unlock(object, box, scratch, scratch2) );
10058 ins_pipe(long_memory_op);
10059 %}
10060
10061 // The encodings are generic.
10062 instruct clear_array(iRegX cnt, iRegP base, iRegX temp, Universe dummy, flagsReg ccr) %{
10063 predicate(!use_block_zeroing(n->in(2)) );
10064 match(Set dummy (ClearArray cnt base));
10065 effect(TEMP temp, KILL ccr);
10066 ins_cost(300);
10067 format %{ "MOV $cnt,$temp\n"
10068 "loop: SUBcc $temp,8,$temp\t! Count down a dword of bytes\n"
10069 " BRge loop\t\t! Clearing loop\n"
10070 " STX G0,[$base+$temp]\t! delay slot" %}
10071
10072 ins_encode %{
10073 // Compiler ensures base is doubleword aligned and cnt is count of doublewords
10074 Register nof_bytes_arg = $cnt$$Register;
10075 Register nof_bytes_tmp = $temp$$Register;
10076 Register base_pointer_arg = $base$$Register;
10077
10078 Label loop;
10079 __ mov(nof_bytes_arg, nof_bytes_tmp);
10080
10081 // Loop and clear, walking backwards through the array.
10082 // nof_bytes_tmp (if >0) is always the number of bytes to zero
10083 __ bind(loop);
10084 __ deccc(nof_bytes_tmp, 8);
10085 __ br(Assembler::greaterEqual, true, Assembler::pt, loop);
10086 __ delayed()-> stx(G0, base_pointer_arg, nof_bytes_tmp);
10087 // %%%% this mini-loop must not cross a cache boundary!
10088 %}
10089 ins_pipe(long_memory_op);
10090 %}
10091
10092 instruct clear_array_bis(g1RegX cnt, o0RegP base, Universe dummy, flagsReg ccr) %{
10093 predicate(use_block_zeroing(n->in(2)));
10094 match(Set dummy (ClearArray cnt base));
10095 effect(USE_KILL cnt, USE_KILL base, KILL ccr);
10096 ins_cost(300);
10097 format %{ "CLEAR [$base, $cnt]\t! ClearArray" %}
10098
10099 ins_encode %{
10100
10101 assert(MinObjAlignmentInBytes >= BytesPerLong, "need alternate implementation");
10102 Register to = $base$$Register;
10103 Register count = $cnt$$Register;
10104
10105 Label Ldone;
10106 __ nop(); // Separate short branches
10107 // Use BIS for zeroing (temp is not used).
10108 __ bis_zeroing(to, count, G0, Ldone);
10109 __ bind(Ldone);
10110
10111 %}
10112 ins_pipe(long_memory_op);
10113 %}
10114
10115 instruct clear_array_bis_2(g1RegX cnt, o0RegP base, iRegX tmp, Universe dummy, flagsReg ccr) %{
10116 predicate(use_block_zeroing(n->in(2)) && !Assembler::is_simm13((int)BlockZeroingLowLimit));
10117 match(Set dummy (ClearArray cnt base));
10118 effect(TEMP tmp, USE_KILL cnt, USE_KILL base, KILL ccr);
10119 ins_cost(300);
10120 format %{ "CLEAR [$base, $cnt]\t! ClearArray" %}
10121
10122 ins_encode %{
10123
10124 assert(MinObjAlignmentInBytes >= BytesPerLong, "need alternate implementation");
10125 Register to = $base$$Register;
10126 Register count = $cnt$$Register;
10127 Register temp = $tmp$$Register;
10128
10129 Label Ldone;
10130 __ nop(); // Separate short branches
10131 // Use BIS for zeroing
10132 __ bis_zeroing(to, count, temp, Ldone);
10133 __ bind(Ldone);
10134
10135 %}
10136 ins_pipe(long_memory_op);
10137 %}
10138
10139 instruct string_compareL(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result,
10140 o7RegI tmp, flagsReg ccr) %{
10141 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::LL);
10142 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10143 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL ccr, KILL tmp);
10144 ins_cost(300);
10145 format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp" %}
10146 ins_encode %{
10147 __ string_compare($str1$$Register, $str2$$Register,
10148 $cnt1$$Register, $cnt2$$Register,
10149 $tmp$$Register, $tmp$$Register,
10150 $result$$Register, StrIntrinsicNode::LL);
10151 %}
10152 ins_pipe(long_memory_op);
10153 %}
10154
10155 instruct string_compareU(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result,
10156 o7RegI tmp, flagsReg ccr) %{
10157 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::UU);
10158 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10159 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL ccr, KILL tmp);
10160 ins_cost(300);
10161 format %{ "String Compare char[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp" %}
10162 ins_encode %{
10163 __ string_compare($str1$$Register, $str2$$Register,
10164 $cnt1$$Register, $cnt2$$Register,
10165 $tmp$$Register, $tmp$$Register,
10166 $result$$Register, StrIntrinsicNode::UU);
10167 %}
10168 ins_pipe(long_memory_op);
10169 %}
10170
10171 instruct string_compareLU(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result,
10172 o7RegI tmp1, g1RegI tmp2, flagsReg ccr) %{
10173 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::LU);
10174 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10175 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL ccr, KILL tmp1, KILL tmp2);
10176 ins_cost(300);
10177 format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1,$tmp2" %}
10178 ins_encode %{
10179 __ string_compare($str1$$Register, $str2$$Register,
10180 $cnt1$$Register, $cnt2$$Register,
10181 $tmp1$$Register, $tmp2$$Register,
10182 $result$$Register, StrIntrinsicNode::LU);
10183 %}
10184 ins_pipe(long_memory_op);
10185 %}
10186
10187 instruct string_compareUL(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result,
10188 o7RegI tmp1, g1RegI tmp2, flagsReg ccr) %{
10189 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::UL);
10190 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10191 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL ccr, KILL tmp1, KILL tmp2);
10192 ins_cost(300);
10193 format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1,$tmp2" %}
10194 ins_encode %{
10195 __ string_compare($str2$$Register, $str1$$Register,
10196 $cnt2$$Register, $cnt1$$Register,
10197 $tmp1$$Register, $tmp2$$Register,
10198 $result$$Register, StrIntrinsicNode::UL);
10199 %}
10200 ins_pipe(long_memory_op);
10201 %}
10202
10203 instruct string_equalsL(o0RegP str1, o1RegP str2, g3RegI cnt, notemp_iRegI result,
10204 o7RegI tmp, flagsReg ccr) %{
10205 predicate(((StrEqualsNode*)n)->encoding() == StrIntrinsicNode::LL);
10206 match(Set result (StrEquals (Binary str1 str2) cnt));
10207 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp, KILL ccr);
10208 ins_cost(300);
10209 format %{ "String Equals byte[] $str1,$str2,$cnt -> $result // KILL $tmp" %}
10210 ins_encode %{
10211 __ array_equals(false, $str1$$Register, $str2$$Register,
10212 $cnt$$Register, $tmp$$Register,
10213 $result$$Register, true /* byte */);
10214 %}
10215 ins_pipe(long_memory_op);
10216 %}
10217
10218 instruct string_equalsU(o0RegP str1, o1RegP str2, g3RegI cnt, notemp_iRegI result,
10219 o7RegI tmp, flagsReg ccr) %{
10220 predicate(((StrEqualsNode*)n)->encoding() == StrIntrinsicNode::UU);
10221 match(Set result (StrEquals (Binary str1 str2) cnt));
10222 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp, KILL ccr);
10223 ins_cost(300);
10224 format %{ "String Equals char[] $str1,$str2,$cnt -> $result // KILL $tmp" %}
10225 ins_encode %{
10226 __ array_equals(false, $str1$$Register, $str2$$Register,
10227 $cnt$$Register, $tmp$$Register,
10228 $result$$Register, false /* byte */);
10229 %}
10230 ins_pipe(long_memory_op);
10231 %}
10232
10233 instruct array_equalsB(o0RegP ary1, o1RegP ary2, g3RegI tmp1, notemp_iRegI result,
10234 o7RegI tmp2, flagsReg ccr) %{
10235 predicate(((AryEqNode*)n)->encoding() == StrIntrinsicNode::LL);
10236 match(Set result (AryEq ary1 ary2));
10237 effect(USE_KILL ary1, USE_KILL ary2, KILL tmp1, KILL tmp2, KILL ccr);
10238 ins_cost(300);
10239 format %{ "Array Equals $ary1,$ary2 -> $result // KILL $tmp1,$tmp2" %}
10240 ins_encode %{
10241 __ array_equals(true, $ary1$$Register, $ary2$$Register,
10242 $tmp1$$Register, $tmp2$$Register,
10243 $result$$Register, true /* byte */);
10244 %}
10245 ins_pipe(long_memory_op);
10246 %}
10247
10248 instruct array_equalsC(o0RegP ary1, o1RegP ary2, g3RegI tmp1, notemp_iRegI result,
10249 o7RegI tmp2, flagsReg ccr) %{
10250 predicate(((AryEqNode*)n)->encoding() == StrIntrinsicNode::UU);
10251 match(Set result (AryEq ary1 ary2));
10252 effect(USE_KILL ary1, USE_KILL ary2, KILL tmp1, KILL tmp2, KILL ccr);
10253 ins_cost(300);
10254 format %{ "Array Equals $ary1,$ary2 -> $result // KILL $tmp1,$tmp2" %}
10255 ins_encode %{
10256 __ array_equals(true, $ary1$$Register, $ary2$$Register,
10257 $tmp1$$Register, $tmp2$$Register,
10258 $result$$Register, false /* byte */);
10259 %}
10260 ins_pipe(long_memory_op);
10261 %}
10262
10263 instruct has_negatives(o0RegP pAryR, g3RegI iSizeR, notemp_iRegI resultR,
10264 iRegL tmp1L, iRegL tmp2L, iRegL tmp3L, iRegL tmp4L,
10265 flagsReg ccr)
10266 %{
10267 match(Set resultR (HasNegatives pAryR iSizeR));
10268 effect(TEMP resultR, TEMP tmp1L, TEMP tmp2L, TEMP tmp3L, TEMP tmp4L, USE pAryR, USE iSizeR, KILL ccr);
10269 format %{ "has negatives byte[] $pAryR,$iSizeR -> $resultR // KILL $tmp1L,$tmp2L,$tmp3L,$tmp4L" %}
10270 ins_encode %{
10271 __ has_negatives($pAryR$$Register, $iSizeR$$Register,
10272 $resultR$$Register,
10273 $tmp1L$$Register, $tmp2L$$Register,
10274 $tmp3L$$Register, $tmp4L$$Register);
10275 %}
10276 ins_pipe(long_memory_op);
10277 %}
10278
10279 // char[] to byte[] compression
10280 instruct string_compress(o0RegP src, o1RegP dst, g3RegI len, notemp_iRegI result, iRegL tmp, flagsReg ccr) %{
10281 predicate(UseVIS < 3);
10282 match(Set result (StrCompressedCopy src (Binary dst len)));
10283 effect(TEMP result, TEMP tmp, USE_KILL src, USE_KILL dst, USE_KILL len, KILL ccr);
10284 ins_cost(300);
10285 format %{ "String Compress $src,$dst,$len -> $result // KILL $tmp" %}
10286 ins_encode %{
10287 Label Ldone;
10288 __ signx($len$$Register);
10289 __ cmp_zero_and_br(Assembler::zero, $len$$Register, Ldone, false, Assembler::pn);
10290 __ delayed()->mov($len$$Register, $result$$Register); // copy count
10291 __ string_compress($src$$Register, $dst$$Register, $len$$Register, $result$$Register, $tmp$$Register, Ldone);
10292 __ bind(Ldone);
10293 %}
10294 ins_pipe(long_memory_op);
10295 %}
10296
10297 // fast char[] to byte[] compression using VIS instructions
10298 instruct string_compress_fast(o0RegP src, o1RegP dst, g3RegI len, notemp_iRegI result,
10299 iRegL tmp1, iRegL tmp2, iRegL tmp3, iRegL tmp4,
10300 regD ftmp1, regD ftmp2, regD ftmp3, flagsReg ccr) %{
10301 predicate(UseVIS >= 3);
10302 match(Set result (StrCompressedCopy src (Binary dst len)));
10303 effect(TEMP result, TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP ftmp1, TEMP ftmp2, TEMP ftmp3, USE_KILL src, USE_KILL dst, USE_KILL len, KILL ccr);
10304 ins_cost(300);
10305 format %{ "String Compress Fast $src,$dst,$len -> $result // KILL $tmp1,$tmp2,$tmp3,$tmp4,$ftmp1,$ftmp2,$ftmp3" %}
10306 ins_encode %{
10307 Label Ldone;
10308 __ signx($len$$Register);
10309 __ string_compress_16($src$$Register, $dst$$Register, $len$$Register, $result$$Register,
10310 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register,
10311 $ftmp1$$FloatRegister, $ftmp2$$FloatRegister, $ftmp3$$FloatRegister, Ldone);
10312 __ cmp_and_brx_short($len$$Register, 0, Assembler::equal, Assembler::pn, Ldone);
10313 __ string_compress($src$$Register, $dst$$Register, $len$$Register, $result$$Register, $tmp1$$Register, Ldone);
10314 __ bind(Ldone);
10315 %}
10316 ins_pipe(long_memory_op);
10317 %}
10318
10319 // byte[] to char[] inflation
10320 instruct string_inflate(Universe dummy, o0RegP src, o1RegP dst, g3RegI len,
10321 iRegL tmp, flagsReg ccr) %{
10322 match(Set dummy (StrInflatedCopy src (Binary dst len)));
10323 effect(TEMP tmp, USE_KILL src, USE_KILL dst, USE_KILL len, KILL ccr);
10324 ins_cost(300);
10325 format %{ "String Inflate $src,$dst,$len // KILL $tmp" %}
10326 ins_encode %{
10327 Label Ldone;
10328 __ signx($len$$Register);
10329 __ cmp_and_brx_short($len$$Register, 0, Assembler::equal, Assembler::pn, Ldone);
10330 __ string_inflate($src$$Register, $dst$$Register, $len$$Register, $tmp$$Register, Ldone);
10331 __ bind(Ldone);
10332 %}
10333 ins_pipe(long_memory_op);
10334 %}
10335
10336 // fast byte[] to char[] inflation using VIS instructions
10337 instruct string_inflate_fast(Universe dummy, o0RegP src, o1RegP dst, g3RegI len,
10338 iRegL tmp, regD ftmp1, regD ftmp2, regD ftmp3, regD ftmp4, flagsReg ccr) %{
10339 predicate(UseVIS >= 3);
10340 match(Set dummy (StrInflatedCopy src (Binary dst len)));
10341 effect(TEMP tmp, TEMP ftmp1, TEMP ftmp2, TEMP ftmp3, TEMP ftmp4, USE_KILL src, USE_KILL dst, USE_KILL len, KILL ccr);
10342 ins_cost(300);
10343 format %{ "String Inflate Fast $src,$dst,$len // KILL $tmp,$ftmp1,$ftmp2,$ftmp3,$ftmp4" %}
10344 ins_encode %{
10345 Label Ldone;
10346 __ signx($len$$Register);
10347 __ string_inflate_16($src$$Register, $dst$$Register, $len$$Register, $tmp$$Register,
10348 $ftmp1$$FloatRegister, $ftmp2$$FloatRegister, $ftmp3$$FloatRegister, $ftmp4$$FloatRegister, Ldone);
10349 __ cmp_and_brx_short($len$$Register, 0, Assembler::equal, Assembler::pn, Ldone);
10350 __ string_inflate($src$$Register, $dst$$Register, $len$$Register, $tmp$$Register, Ldone);
10351 __ bind(Ldone);
10352 %}
10353 ins_pipe(long_memory_op);
10354 %}
10355
10356
10357 //---------- Zeros Count Instructions ------------------------------------------
10358
10359 instruct countLeadingZerosI(iRegIsafe dst, iRegI src, iRegI tmp, flagsReg cr) %{
10360 predicate(UsePopCountInstruction && !UseCountLeadingZerosInstruction); // See Matcher::match_rule_supported
10361 match(Set dst (CountLeadingZerosI src));
10362 effect(TEMP dst, TEMP tmp, KILL cr);
10363
10364 // x |= (x >> 1);
10365 // x |= (x >> 2);
10366 // x |= (x >> 4);
10367 // x |= (x >> 8);
10368 // x |= (x >> 16);
10369 // return (WORDBITS - popc(x));
10370 format %{ "SRL $src,1,$tmp\t! count leading zeros (int)\n\t"
10371 "SRL $src,0,$dst\t! 32-bit zero extend\n\t"
10372 "OR $dst,$tmp,$dst\n\t"
10373 "SRL $dst,2,$tmp\n\t"
10374 "OR $dst,$tmp,$dst\n\t"
10375 "SRL $dst,4,$tmp\n\t"
10376 "OR $dst,$tmp,$dst\n\t"
10377 "SRL $dst,8,$tmp\n\t"
10378 "OR $dst,$tmp,$dst\n\t"
10379 "SRL $dst,16,$tmp\n\t"
10380 "OR $dst,$tmp,$dst\n\t"
10381 "POPC $dst,$dst\n\t"
10382 "MOV 32,$tmp\n\t"
10383 "SUB $tmp,$dst,$dst" %}
10384 ins_encode %{
10385 Register Rdst = $dst$$Register;
10386 Register Rsrc = $src$$Register;
10387 Register Rtmp = $tmp$$Register;
10388 __ srl(Rsrc, 1, Rtmp);
10389 __ srl(Rsrc, 0, Rdst);
10390 __ or3(Rdst, Rtmp, Rdst);
10391 __ srl(Rdst, 2, Rtmp);
10392 __ or3(Rdst, Rtmp, Rdst);
10393 __ srl(Rdst, 4, Rtmp);
10394 __ or3(Rdst, Rtmp, Rdst);
10395 __ srl(Rdst, 8, Rtmp);
10396 __ or3(Rdst, Rtmp, Rdst);
10397 __ srl(Rdst, 16, Rtmp);
10398 __ or3(Rdst, Rtmp, Rdst);
10399 __ popc(Rdst, Rdst);
10400 __ mov(BitsPerInt, Rtmp);
10401 __ sub(Rtmp, Rdst, Rdst);
10402 %}
10403 ins_pipe(ialu_reg);
10404 %}
10405
10406 instruct countLeadingZerosL(iRegIsafe dst, iRegL src, iRegL tmp, flagsReg cr) %{
10407 predicate(UsePopCountInstruction && !UseCountLeadingZerosInstruction);
10408 match(Set dst (CountLeadingZerosL src));
10409 effect(TEMP dst, TEMP tmp, KILL cr);
10410
10411 // x |= (x >> 1);
10412 // x |= (x >> 2);
10413 // x |= (x >> 4);
10414 // x |= (x >> 8);
10415 // x |= (x >> 16);
10416 // x |= (x >> 32);
10417 // return (WORDBITS - popc(x));
10418 format %{ "SRLX $src,1,$tmp\t! count leading zeros (long)\n\t"
10419 "OR $src,$tmp,$dst\n\t"
10420 "SRLX $dst,2,$tmp\n\t"
10421 "OR $dst,$tmp,$dst\n\t"
10422 "SRLX $dst,4,$tmp\n\t"
10423 "OR $dst,$tmp,$dst\n\t"
10424 "SRLX $dst,8,$tmp\n\t"
10425 "OR $dst,$tmp,$dst\n\t"
10426 "SRLX $dst,16,$tmp\n\t"
10427 "OR $dst,$tmp,$dst\n\t"
10428 "SRLX $dst,32,$tmp\n\t"
10429 "OR $dst,$tmp,$dst\n\t"
10430 "POPC $dst,$dst\n\t"
10431 "MOV 64,$tmp\n\t"
10432 "SUB $tmp,$dst,$dst" %}
10433 ins_encode %{
10434 Register Rdst = $dst$$Register;
10435 Register Rsrc = $src$$Register;
10436 Register Rtmp = $tmp$$Register;
10437 __ srlx(Rsrc, 1, Rtmp);
10438 __ or3( Rsrc, Rtmp, Rdst);
10439 __ srlx(Rdst, 2, Rtmp);
10440 __ or3( Rdst, Rtmp, Rdst);
10441 __ srlx(Rdst, 4, Rtmp);
10442 __ or3( Rdst, Rtmp, Rdst);
10443 __ srlx(Rdst, 8, Rtmp);
10444 __ or3( Rdst, Rtmp, Rdst);
10445 __ srlx(Rdst, 16, Rtmp);
10446 __ or3( Rdst, Rtmp, Rdst);
10447 __ srlx(Rdst, 32, Rtmp);
10448 __ or3( Rdst, Rtmp, Rdst);
10449 __ popc(Rdst, Rdst);
10450 __ mov(BitsPerLong, Rtmp);
10451 __ sub(Rtmp, Rdst, Rdst);
10452 %}
10453 ins_pipe(ialu_reg);
10454 %}
10455
10456 instruct countLeadingZerosIvis(iRegIsafe dst, iRegI src) %{
10457 predicate(UseCountLeadingZerosInstruction);
10458 match(Set dst (CountLeadingZerosI src));
10459 effect(TEMP dst);
10460
10461 format %{ "SRL $src,0,$dst\t! count leading zeros (int)\n\t"
10462 "LZCNT $dst,$dst\n\t"
10463 "SUB $dst,32,$dst" %}
10464 ins_encode %{
10465 Register Rdst = $dst$$Register;
10466 Register Rsrc = $src$$Register;
10467 __ srl(Rsrc, 0, Rdst);
10468 __ lzcnt(Rdst, Rdst);
10469 __ sub(Rdst, BitsPerInt, Rdst);
10470 %}
10471 ins_pipe(ialu_reg);
10472 %}
10473
10474 instruct countLeadingZerosLvis(iRegIsafe dst, iRegL src) %{
10475 predicate(UseCountLeadingZerosInstruction);
10476 match(Set dst (CountLeadingZerosL src));
10477 effect(TEMP dst);
10478
10479 format %{ "LZCNT $src,$dst\t! count leading zeros (long)" %}
10480 ins_encode %{
10481 Register Rdst = $dst$$Register;
10482 Register Rsrc = $src$$Register;
10483 __ lzcnt(Rsrc, Rdst);
10484 %}
10485 ins_pipe(ialu_reg);
10486 %}
10487
10488 instruct countTrailingZerosI(iRegIsafe dst, iRegI src, flagsReg cr) %{
10489 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported
10490 match(Set dst (CountTrailingZerosI src));
10491 effect(TEMP dst, KILL cr);
10492
10493 // return popc(~x & (x - 1));
10494 format %{ "SUB $src,1,$dst\t! count trailing zeros (int)\n\t"
10495 "ANDN $dst,$src,$dst\n\t"
10496 "SRL $dst,R_G0,$dst\n\t"
10497 "POPC $dst,$dst" %}
10498 ins_encode %{
10499 Register Rdst = $dst$$Register;
10500 Register Rsrc = $src$$Register;
10501 __ sub(Rsrc, 1, Rdst);
10502 __ andn(Rdst, Rsrc, Rdst);
10503 __ srl(Rdst, G0, Rdst);
10504 __ popc(Rdst, Rdst);
10505 %}
10506 ins_pipe(ialu_reg);
10507 %}
10508
10509 instruct countTrailingZerosL(iRegIsafe dst, iRegL src, flagsReg cr) %{
10510 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported
10511 match(Set dst (CountTrailingZerosL src));
10512 effect(TEMP dst, KILL cr);
10513
10514 // return popc(~x & (x - 1));
10515 format %{ "SUB $src,1,$dst\t! count trailing zeros (long)\n\t"
10516 "ANDN $dst,$src,$dst\n\t"
10517 "POPC $dst,$dst" %}
10518 ins_encode %{
10519 Register Rdst = $dst$$Register;
10520 Register Rsrc = $src$$Register;
10521 __ sub(Rsrc, 1, Rdst);
10522 __ andn(Rdst, Rsrc, Rdst);
10523 __ popc(Rdst, Rdst);
10524 %}
10525 ins_pipe(ialu_reg);
10526 %}
10527
10528
10529 //---------- Population Count Instructions -------------------------------------
10530
10531 instruct popCountI(iRegIsafe dst, iRegI src) %{
10532 predicate(UsePopCountInstruction);
10533 match(Set dst (PopCountI src));
10534
10535 format %{ "SRL $src, G0, $dst\t! clear upper word for 64 bit POPC\n\t"
10536 "POPC $dst, $dst" %}
10537 ins_encode %{
10538 __ srl($src$$Register, G0, $dst$$Register);
10539 __ popc($dst$$Register, $dst$$Register);
10540 %}
10541 ins_pipe(ialu_reg);
10542 %}
10543
10544 // Note: Long.bitCount(long) returns an int.
10545 instruct popCountL(iRegIsafe dst, iRegL src) %{
10546 predicate(UsePopCountInstruction);
10547 match(Set dst (PopCountL src));
10548
10549 format %{ "POPC $src, $dst" %}
10550 ins_encode %{
10551 __ popc($src$$Register, $dst$$Register);
10552 %}
10553 ins_pipe(ialu_reg);
10554 %}
10555
10556
10557 // ============================================================================
10558 //------------Bytes reverse--------------------------------------------------
10559
10560 instruct bytes_reverse_int(iRegI dst, stackSlotI src) %{
10561 match(Set dst (ReverseBytesI src));
10562
10563 // Op cost is artificially doubled to make sure that load or store
10564 // instructions are preferred over this one which requires a spill
10565 // onto a stack slot.
10566 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
10567 format %{ "LDUWA $src, $dst\t!asi=primary_little" %}
10568
10569 ins_encode %{
10570 __ set($src$$disp + STACK_BIAS, O7);
10571 __ lduwa($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10572 %}
10573 ins_pipe( iload_mem );
10574 %}
10575
10576 instruct bytes_reverse_long(iRegL dst, stackSlotL src) %{
10577 match(Set dst (ReverseBytesL src));
10578
10579 // Op cost is artificially doubled to make sure that load or store
10580 // instructions are preferred over this one which requires a spill
10581 // onto a stack slot.
10582 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
10583 format %{ "LDXA $src, $dst\t!asi=primary_little" %}
10584
10585 ins_encode %{
10586 __ set($src$$disp + STACK_BIAS, O7);
10587 __ ldxa($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10588 %}
10589 ins_pipe( iload_mem );
10590 %}
10591
10592 instruct bytes_reverse_unsigned_short(iRegI dst, stackSlotI src) %{
10593 match(Set dst (ReverseBytesUS src));
10594
10595 // Op cost is artificially doubled to make sure that load or store
10596 // instructions are preferred over this one which requires a spill
10597 // onto a stack slot.
10598 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
10599 format %{ "LDUHA $src, $dst\t!asi=primary_little\n\t" %}
10600
10601 ins_encode %{
10602 // the value was spilled as an int so bias the load
10603 __ set($src$$disp + STACK_BIAS + 2, O7);
10604 __ lduha($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10605 %}
10606 ins_pipe( iload_mem );
10607 %}
10608
10609 instruct bytes_reverse_short(iRegI dst, stackSlotI src) %{
10610 match(Set dst (ReverseBytesS src));
10611
10612 // Op cost is artificially doubled to make sure that load or store
10613 // instructions are preferred over this one which requires a spill
10614 // onto a stack slot.
10615 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
10616 format %{ "LDSHA $src, $dst\t!asi=primary_little\n\t" %}
10617
10618 ins_encode %{
10619 // the value was spilled as an int so bias the load
10620 __ set($src$$disp + STACK_BIAS + 2, O7);
10621 __ ldsha($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10622 %}
10623 ins_pipe( iload_mem );
10624 %}
10625
10626 // Load Integer reversed byte order
10627 instruct loadI_reversed(iRegI dst, indIndexMemory src) %{
10628 match(Set dst (ReverseBytesI (LoadI src)));
10629
10630 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
10631 size(4);
10632 format %{ "LDUWA $src, $dst\t!asi=primary_little" %}
10633
10634 ins_encode %{
10635 __ lduwa($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10636 %}
10637 ins_pipe(iload_mem);
10638 %}
10639
10640 // Load Long - aligned and reversed
10641 instruct loadL_reversed(iRegL dst, indIndexMemory src) %{
10642 match(Set dst (ReverseBytesL (LoadL src)));
10643
10644 ins_cost(MEMORY_REF_COST);
10645 size(4);
10646 format %{ "LDXA $src, $dst\t!asi=primary_little" %}
10647
10648 ins_encode %{
10649 __ ldxa($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10650 %}
10651 ins_pipe(iload_mem);
10652 %}
10653
10654 // Load unsigned short / char reversed byte order
10655 instruct loadUS_reversed(iRegI dst, indIndexMemory src) %{
10656 match(Set dst (ReverseBytesUS (LoadUS src)));
10657
10658 ins_cost(MEMORY_REF_COST);
10659 size(4);
10660 format %{ "LDUHA $src, $dst\t!asi=primary_little" %}
10661
10662 ins_encode %{
10663 __ lduha($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10664 %}
10665 ins_pipe(iload_mem);
10666 %}
10667
10668 // Load short reversed byte order
10669 instruct loadS_reversed(iRegI dst, indIndexMemory src) %{
10670 match(Set dst (ReverseBytesS (LoadS src)));
10671
10672 ins_cost(MEMORY_REF_COST);
10673 size(4);
10674 format %{ "LDSHA $src, $dst\t!asi=primary_little" %}
10675
10676 ins_encode %{
10677 __ ldsha($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10678 %}
10679 ins_pipe(iload_mem);
10680 %}
10681
10682 // Store Integer reversed byte order
10683 instruct storeI_reversed(indIndexMemory dst, iRegI src) %{
10684 match(Set dst (StoreI dst (ReverseBytesI src)));
10685
10686 ins_cost(MEMORY_REF_COST);
10687 size(4);
10688 format %{ "STWA $src, $dst\t!asi=primary_little" %}
10689
10690 ins_encode %{
10691 __ stwa($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE);
10692 %}
10693 ins_pipe(istore_mem_reg);
10694 %}
10695
10696 // Store Long reversed byte order
10697 instruct storeL_reversed(indIndexMemory dst, iRegL src) %{
10698 match(Set dst (StoreL dst (ReverseBytesL src)));
10699
10700 ins_cost(MEMORY_REF_COST);
10701 size(4);
10702 format %{ "STXA $src, $dst\t!asi=primary_little" %}
10703
10704 ins_encode %{
10705 __ stxa($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE);
10706 %}
10707 ins_pipe(istore_mem_reg);
10708 %}
10709
10710 // Store unsighed short/char reversed byte order
10711 instruct storeUS_reversed(indIndexMemory dst, iRegI src) %{
10712 match(Set dst (StoreC dst (ReverseBytesUS src)));
10713
10714 ins_cost(MEMORY_REF_COST);
10715 size(4);
10716 format %{ "STHA $src, $dst\t!asi=primary_little" %}
10717
10718 ins_encode %{
10719 __ stha($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE);
10720 %}
10721 ins_pipe(istore_mem_reg);
10722 %}
10723
10724 // Store short reversed byte order
10725 instruct storeS_reversed(indIndexMemory dst, iRegI src) %{
10726 match(Set dst (StoreC dst (ReverseBytesS src)));
10727
10728 ins_cost(MEMORY_REF_COST);
10729 size(4);
10730 format %{ "STHA $src, $dst\t!asi=primary_little" %}
10731
10732 ins_encode %{
10733 __ stha($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE);
10734 %}
10735 ins_pipe(istore_mem_reg);
10736 %}
10737
10738 // ====================VECTOR INSTRUCTIONS=====================================
10739
10740 // Load Aligned Packed values into a Double Register
10741 instruct loadV8(regD dst, memory mem) %{
10742 predicate(n->as_LoadVector()->memory_size() == 8);
10743 match(Set dst (LoadVector mem));
10744 ins_cost(MEMORY_REF_COST);
10745 size(4);
10746 format %{ "LDDF $mem,$dst\t! load vector (8 bytes)" %}
10747 ins_encode %{
10748 __ ldf(FloatRegisterImpl::D, $mem$$Address, as_DoubleFloatRegister($dst$$reg));
10749 %}
10750 ins_pipe(floadD_mem);
10751 %}
10752
10753 // Store Vector in Double register to memory
10754 instruct storeV8(memory mem, regD src) %{
10755 predicate(n->as_StoreVector()->memory_size() == 8);
10756 match(Set mem (StoreVector mem src));
10757 ins_cost(MEMORY_REF_COST);
10758 size(4);
10759 format %{ "STDF $src,$mem\t! store vector (8 bytes)" %}
10760 ins_encode %{
10761 __ stf(FloatRegisterImpl::D, as_DoubleFloatRegister($src$$reg), $mem$$Address);
10762 %}
10763 ins_pipe(fstoreD_mem_reg);
10764 %}
10765
10766 // Store Zero into vector in memory
10767 instruct storeV8B_zero(memory mem, immI0 zero) %{
10768 predicate(n->as_StoreVector()->memory_size() == 8);
10769 match(Set mem (StoreVector mem (ReplicateB zero)));
10770 ins_cost(MEMORY_REF_COST);
10771 size(4);
10772 format %{ "STX $zero,$mem\t! store zero vector (8 bytes)" %}
10773 ins_encode %{
10774 __ stx(G0, $mem$$Address);
10775 %}
10776 ins_pipe(fstoreD_mem_zero);
10777 %}
10778
10779 instruct storeV4S_zero(memory mem, immI0 zero) %{
10780 predicate(n->as_StoreVector()->memory_size() == 8);
10781 match(Set mem (StoreVector mem (ReplicateS zero)));
10782 ins_cost(MEMORY_REF_COST);
10783 size(4);
10784 format %{ "STX $zero,$mem\t! store zero vector (4 shorts)" %}
10785 ins_encode %{
10786 __ stx(G0, $mem$$Address);
10787 %}
10788 ins_pipe(fstoreD_mem_zero);
10789 %}
10790
10791 instruct storeV2I_zero(memory mem, immI0 zero) %{
10792 predicate(n->as_StoreVector()->memory_size() == 8);
10793 match(Set mem (StoreVector mem (ReplicateI zero)));
10794 ins_cost(MEMORY_REF_COST);
10795 size(4);
10796 format %{ "STX $zero,$mem\t! store zero vector (2 ints)" %}
10797 ins_encode %{
10798 __ stx(G0, $mem$$Address);
10799 %}
10800 ins_pipe(fstoreD_mem_zero);
10801 %}
10802
10803 instruct storeV2F_zero(memory mem, immF0 zero) %{
10804 predicate(n->as_StoreVector()->memory_size() == 8);
10805 match(Set mem (StoreVector mem (ReplicateF zero)));
10806 ins_cost(MEMORY_REF_COST);
10807 size(4);
10808 format %{ "STX $zero,$mem\t! store zero vector (2 floats)" %}
10809 ins_encode %{
10810 __ stx(G0, $mem$$Address);
10811 %}
10812 ins_pipe(fstoreD_mem_zero);
10813 %}
10814
10815 // Replicate scalar to packed byte values into Double register
10816 instruct Repl8B_reg(regD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
10817 predicate(n->as_Vector()->length() == 8 && UseVIS >= 3);
10818 match(Set dst (ReplicateB src));
10819 effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
10820 format %{ "SLLX $src,56,$tmp\n\t"
10821 "SRLX $tmp, 8,$tmp2\n\t"
10822 "OR $tmp,$tmp2,$tmp\n\t"
10823 "SRLX $tmp,16,$tmp2\n\t"
10824 "OR $tmp,$tmp2,$tmp\n\t"
10825 "SRLX $tmp,32,$tmp2\n\t"
10826 "OR $tmp,$tmp2,$tmp\t! replicate8B\n\t"
10827 "MOVXTOD $tmp,$dst\t! MoveL2D" %}
10828 ins_encode %{
10829 Register Rsrc = $src$$Register;
10830 Register Rtmp = $tmp$$Register;
10831 Register Rtmp2 = $tmp2$$Register;
10832 __ sllx(Rsrc, 56, Rtmp);
10833 __ srlx(Rtmp, 8, Rtmp2);
10834 __ or3 (Rtmp, Rtmp2, Rtmp);
10835 __ srlx(Rtmp, 16, Rtmp2);
10836 __ or3 (Rtmp, Rtmp2, Rtmp);
10837 __ srlx(Rtmp, 32, Rtmp2);
10838 __ or3 (Rtmp, Rtmp2, Rtmp);
10839 __ movxtod(Rtmp, as_DoubleFloatRegister($dst$$reg));
10840 %}
10841 ins_pipe(ialu_reg);
10842 %}
10843
10844 // Replicate scalar to packed byte values into Double stack
10845 instruct Repl8B_stk(stackSlotD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
10846 predicate(n->as_Vector()->length() == 8 && UseVIS < 3);
10847 match(Set dst (ReplicateB src));
10848 effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
10849 format %{ "SLLX $src,56,$tmp\n\t"
10850 "SRLX $tmp, 8,$tmp2\n\t"
10851 "OR $tmp,$tmp2,$tmp\n\t"
10852 "SRLX $tmp,16,$tmp2\n\t"
10853 "OR $tmp,$tmp2,$tmp\n\t"
10854 "SRLX $tmp,32,$tmp2\n\t"
10855 "OR $tmp,$tmp2,$tmp\t! replicate8B\n\t"
10856 "STX $tmp,$dst\t! regL to stkD" %}
10857 ins_encode %{
10858 Register Rsrc = $src$$Register;
10859 Register Rtmp = $tmp$$Register;
10860 Register Rtmp2 = $tmp2$$Register;
10861 __ sllx(Rsrc, 56, Rtmp);
10862 __ srlx(Rtmp, 8, Rtmp2);
10863 __ or3 (Rtmp, Rtmp2, Rtmp);
10864 __ srlx(Rtmp, 16, Rtmp2);
10865 __ or3 (Rtmp, Rtmp2, Rtmp);
10866 __ srlx(Rtmp, 32, Rtmp2);
10867 __ or3 (Rtmp, Rtmp2, Rtmp);
10868 __ set ($dst$$disp + STACK_BIAS, Rtmp2);
10869 __ stx (Rtmp, Rtmp2, $dst$$base$$Register);
10870 %}
10871 ins_pipe(ialu_reg);
10872 %}
10873
10874 // Replicate scalar constant to packed byte values in Double register
10875 instruct Repl8B_immI(regD dst, immI13 con, o7RegI tmp) %{
10876 predicate(n->as_Vector()->length() == 8);
10877 match(Set dst (ReplicateB con));
10878 effect(KILL tmp);
10879 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl8B($con)" %}
10880 ins_encode %{
10881 // XXX This is a quick fix for 6833573.
10882 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 8, 1)), $dst$$FloatRegister);
10883 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 8, 1)), $tmp$$Register);
10884 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
10885 %}
10886 ins_pipe(loadConFD);
10887 %}
10888
10889 // Replicate scalar to packed char/short values into Double register
10890 instruct Repl4S_reg(regD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
10891 predicate(n->as_Vector()->length() == 4 && UseVIS >= 3);
10892 match(Set dst (ReplicateS src));
10893 effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
10894 format %{ "SLLX $src,48,$tmp\n\t"
10895 "SRLX $tmp,16,$tmp2\n\t"
10896 "OR $tmp,$tmp2,$tmp\n\t"
10897 "SRLX $tmp,32,$tmp2\n\t"
10898 "OR $tmp,$tmp2,$tmp\t! replicate4S\n\t"
10899 "MOVXTOD $tmp,$dst\t! MoveL2D" %}
10900 ins_encode %{
10901 Register Rsrc = $src$$Register;
10902 Register Rtmp = $tmp$$Register;
10903 Register Rtmp2 = $tmp2$$Register;
10904 __ sllx(Rsrc, 48, Rtmp);
10905 __ srlx(Rtmp, 16, Rtmp2);
10906 __ or3 (Rtmp, Rtmp2, Rtmp);
10907 __ srlx(Rtmp, 32, Rtmp2);
10908 __ or3 (Rtmp, Rtmp2, Rtmp);
10909 __ movxtod(Rtmp, as_DoubleFloatRegister($dst$$reg));
10910 %}
10911 ins_pipe(ialu_reg);
10912 %}
10913
10914 // Replicate scalar to packed char/short values into Double stack
10915 instruct Repl4S_stk(stackSlotD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
10916 predicate(n->as_Vector()->length() == 4 && UseVIS < 3);
10917 match(Set dst (ReplicateS src));
10918 effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
10919 format %{ "SLLX $src,48,$tmp\n\t"
10920 "SRLX $tmp,16,$tmp2\n\t"
10921 "OR $tmp,$tmp2,$tmp\n\t"
10922 "SRLX $tmp,32,$tmp2\n\t"
10923 "OR $tmp,$tmp2,$tmp\t! replicate4S\n\t"
10924 "STX $tmp,$dst\t! regL to stkD" %}
10925 ins_encode %{
10926 Register Rsrc = $src$$Register;
10927 Register Rtmp = $tmp$$Register;
10928 Register Rtmp2 = $tmp2$$Register;
10929 __ sllx(Rsrc, 48, Rtmp);
10930 __ srlx(Rtmp, 16, Rtmp2);
10931 __ or3 (Rtmp, Rtmp2, Rtmp);
10932 __ srlx(Rtmp, 32, Rtmp2);
10933 __ or3 (Rtmp, Rtmp2, Rtmp);
10934 __ set ($dst$$disp + STACK_BIAS, Rtmp2);
10935 __ stx (Rtmp, Rtmp2, $dst$$base$$Register);
10936 %}
10937 ins_pipe(ialu_reg);
10938 %}
10939
10940 // Replicate scalar constant to packed char/short values in Double register
10941 instruct Repl4S_immI(regD dst, immI con, o7RegI tmp) %{
10942 predicate(n->as_Vector()->length() == 4);
10943 match(Set dst (ReplicateS con));
10944 effect(KILL tmp);
10945 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl4S($con)" %}
10946 ins_encode %{
10947 // XXX This is a quick fix for 6833573.
10948 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 4, 2)), $dst$$FloatRegister);
10949 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 4, 2)), $tmp$$Register);
10950 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
10951 %}
10952 ins_pipe(loadConFD);
10953 %}
10954
10955 // Replicate scalar to packed int values into Double register
10956 instruct Repl2I_reg(regD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
10957 predicate(n->as_Vector()->length() == 2 && UseVIS >= 3);
10958 match(Set dst (ReplicateI src));
10959 effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
10960 format %{ "SLLX $src,32,$tmp\n\t"
10961 "SRLX $tmp,32,$tmp2\n\t"
10962 "OR $tmp,$tmp2,$tmp\t! replicate2I\n\t"
10963 "MOVXTOD $tmp,$dst\t! MoveL2D" %}
10964 ins_encode %{
10965 Register Rsrc = $src$$Register;
10966 Register Rtmp = $tmp$$Register;
10967 Register Rtmp2 = $tmp2$$Register;
10968 __ sllx(Rsrc, 32, Rtmp);
10969 __ srlx(Rtmp, 32, Rtmp2);
10970 __ or3 (Rtmp, Rtmp2, Rtmp);
10971 __ movxtod(Rtmp, as_DoubleFloatRegister($dst$$reg));
10972 %}
10973 ins_pipe(ialu_reg);
10974 %}
10975
10976 // Replicate scalar to packed int values into Double stack
10977 instruct Repl2I_stk(stackSlotD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
10978 predicate(n->as_Vector()->length() == 2 && UseVIS < 3);
10979 match(Set dst (ReplicateI src));
10980 effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
10981 format %{ "SLLX $src,32,$tmp\n\t"
10982 "SRLX $tmp,32,$tmp2\n\t"
10983 "OR $tmp,$tmp2,$tmp\t! replicate2I\n\t"
10984 "STX $tmp,$dst\t! regL to stkD" %}
10985 ins_encode %{
10986 Register Rsrc = $src$$Register;
10987 Register Rtmp = $tmp$$Register;
10988 Register Rtmp2 = $tmp2$$Register;
10989 __ sllx(Rsrc, 32, Rtmp);
10990 __ srlx(Rtmp, 32, Rtmp2);
10991 __ or3 (Rtmp, Rtmp2, Rtmp);
10992 __ set ($dst$$disp + STACK_BIAS, Rtmp2);
10993 __ stx (Rtmp, Rtmp2, $dst$$base$$Register);
10994 %}
10995 ins_pipe(ialu_reg);
10996 %}
10997
10998 // Replicate scalar zero constant to packed int values in Double register
10999 instruct Repl2I_immI(regD dst, immI con, o7RegI tmp) %{
11000 predicate(n->as_Vector()->length() == 2);
11001 match(Set dst (ReplicateI con));
11002 effect(KILL tmp);
11003 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl2I($con)" %}
11004 ins_encode %{
11005 // XXX This is a quick fix for 6833573.
11006 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 2, 4)), $dst$$FloatRegister);
11007 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 2, 4)), $tmp$$Register);
11008 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
11009 %}
11010 ins_pipe(loadConFD);
11011 %}
11012
11013 // Replicate scalar to packed float values into Double stack
11014 instruct Repl2F_stk(stackSlotD dst, regF src) %{
11015 predicate(n->as_Vector()->length() == 2);
11016 match(Set dst (ReplicateF src));
11017 ins_cost(MEMORY_REF_COST*2);
11018 format %{ "STF $src,$dst.hi\t! packed2F\n\t"
11019 "STF $src,$dst.lo" %}
11020 opcode(Assembler::stf_op3);
11021 ins_encode(simple_form3_mem_reg(dst, src), form3_mem_plus_4_reg(dst, src));
11022 ins_pipe(fstoreF_stk_reg);
11023 %}
11024
11025 // Replicate scalar zero constant to packed float values in Double register
11026 instruct Repl2F_immF(regD dst, immF con, o7RegI tmp) %{
11027 predicate(n->as_Vector()->length() == 2);
11028 match(Set dst (ReplicateF con));
11029 effect(KILL tmp);
11030 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl2F($con)" %}
11031 ins_encode %{
11032 // XXX This is a quick fix for 6833573.
11033 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immF($con$$constant)), $dst$$FloatRegister);
11034 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immF($con$$constant)), $tmp$$Register);
11035 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
11036 %}
11037 ins_pipe(loadConFD);
11038 %}
11039
11040 //----------PEEPHOLE RULES-----------------------------------------------------
11041 // These must follow all instruction definitions as they use the names
11042 // defined in the instructions definitions.
11043 //
11044 // peepmatch ( root_instr_name [preceding_instruction]* );
11045 //
11046 // peepconstraint %{
11047 // (instruction_number.operand_name relational_op instruction_number.operand_name
11048 // [, ...] );
11049 // // instruction numbers are zero-based using left to right order in peepmatch
11050 //
11051 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
11052 // // provide an instruction_number.operand_name for each operand that appears
11053 // // in the replacement instruction's match rule
11054 //
11055 // ---------VM FLAGS---------------------------------------------------------
11056 //
11057 // All peephole optimizations can be turned off using -XX:-OptoPeephole
11058 //
11059 // Each peephole rule is given an identifying number starting with zero and
11060 // increasing by one in the order seen by the parser. An individual peephole
11061 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
11062 // on the command-line.
11063 //
11064 // ---------CURRENT LIMITATIONS----------------------------------------------
11065 //
11066 // Only match adjacent instructions in same basic block
11067 // Only equality constraints
11068 // Only constraints between operands, not (0.dest_reg == EAX_enc)
11069 // Only one replacement instruction
11070 //
11071 // ---------EXAMPLE----------------------------------------------------------
11072 //
11073 // // pertinent parts of existing instructions in architecture description
11074 // instruct movI(eRegI dst, eRegI src) %{
11075 // match(Set dst (CopyI src));
11076 // %}
11077 //
11078 // instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{
11079 // match(Set dst (AddI dst src));
11080 // effect(KILL cr);
11081 // %}
11082 //
11083 // // Change (inc mov) to lea
11084 // peephole %{
11085 // // increment preceeded by register-register move
11086 // peepmatch ( incI_eReg movI );
11087 // // require that the destination register of the increment
11088 // // match the destination register of the move
11089 // peepconstraint ( 0.dst == 1.dst );
11090 // // construct a replacement instruction that sets
11091 // // the destination to ( move's source register + one )
11092 // peepreplace ( incI_eReg_immI1( 0.dst 1.src 0.src ) );
11093 // %}
11094 //
11095
11096 // // Change load of spilled value to only a spill
11097 // instruct storeI(memory mem, eRegI src) %{
11098 // match(Set mem (StoreI mem src));
11099 // %}
11100 //
11101 // instruct loadI(eRegI dst, memory mem) %{
11102 // match(Set dst (LoadI mem));
11103 // %}
11104 //
11105 // peephole %{
11106 // peepmatch ( loadI storeI );
11107 // peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem );
11108 // peepreplace ( storeI( 1.mem 1.mem 1.src ) );
11109 // %}
11110
11111 //----------SMARTSPILL RULES---------------------------------------------------
11112 // These must follow all instruction definitions as they use the names
11113 // defined in the instructions definitions.
11114 //
11115 // SPARC will probably not have any of these rules due to RISC instruction set.
11116
11117 //----------PIPELINE-----------------------------------------------------------
11118 // Rules which define the behavior of the target architectures pipeline.