1 // 2 // Copyright (c) 2011, 2014, Oracle and/or its affiliates. All rights reserved. 3 // Copyright 2012, 2014 SAP AG. All rights reserved. 4 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 5 // 6 // This code is free software; you can redistribute it and/or modify it 7 // under the terms of the GNU General Public License version 2 only, as 8 // published by the Free Software Foundation. 9 // 10 // This code is distributed in the hope that it will be useful, but WITHOUT 11 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 13 // version 2 for more details (a copy is included in the LICENSE file that 14 // accompanied this code). 15 // 16 // You should have received a copy of the GNU General Public License version 17 // 2 along with this work; if not, write to the Free Software Foundation, 18 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 19 // 20 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 21 // or visit www.oracle.com if you need additional information or have any 22 // questions. 23 // 24 // 25 26 // 27 // PPC64 Architecture Description File 28 // 29 30 //----------REGISTER DEFINITION BLOCK------------------------------------------ 31 // This information is used by the matcher and the register allocator to 32 // describe individual registers and classes of registers within the target 33 // architecture. 34 register %{ 35 //----------Architecture Description Register Definitions---------------------- 36 // General Registers 37 // "reg_def" name (register save type, C convention save type, 38 // ideal register type, encoding); 39 // 40 // Register Save Types: 41 // 42 // NS = No-Save: The register allocator assumes that these registers 43 // can be used without saving upon entry to the method, & 44 // that they do not need to be saved at call sites. 45 // 46 // SOC = Save-On-Call: The register allocator assumes that these registers 47 // can be used without saving upon entry to the method, 48 // but that they must be saved at call sites. 49 // These are called "volatiles" on ppc. 50 // 51 // SOE = Save-On-Entry: The register allocator assumes that these registers 52 // must be saved before using them upon entry to the 53 // method, but they do not need to be saved at call 54 // sites. 55 // These are called "nonvolatiles" on ppc. 56 // 57 // AS = Always-Save: The register allocator assumes that these registers 58 // must be saved before using them upon entry to the 59 // method, & that they must be saved at call sites. 60 // 61 // Ideal Register Type is used to determine how to save & restore a 62 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get 63 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI. 64 // 65 // The encoding number is the actual bit-pattern placed into the opcodes. 66 // 67 // PPC64 register definitions, based on the 64-bit PowerPC ELF ABI 68 // Supplement Version 1.7 as of 2003-10-29. 69 // 70 // For each 64-bit register we must define two registers: the register 71 // itself, e.g. R3, and a corresponding virtual other (32-bit-)'half', 72 // e.g. R3_H, which is needed by the allocator, but is not used 73 // for stores, loads, etc. 74 75 // ---------------------------- 76 // Integer/Long Registers 77 // ---------------------------- 78 79 // PPC64 has 32 64-bit integer registers. 80 81 // types: v = volatile, nv = non-volatile, s = system 82 reg_def R0 ( SOC, SOC, Op_RegI, 0, R0->as_VMReg() ); // v used in prologs 83 reg_def R0_H ( SOC, SOC, Op_RegI, 99, R0->as_VMReg()->next() ); 84 reg_def R1 ( NS, NS, Op_RegI, 1, R1->as_VMReg() ); // s SP 85 reg_def R1_H ( NS, NS, Op_RegI, 99, R1->as_VMReg()->next() ); 86 reg_def R2 ( SOC, SOC, Op_RegI, 2, R2->as_VMReg() ); // v TOC 87 reg_def R2_H ( SOC, SOC, Op_RegI, 99, R2->as_VMReg()->next() ); 88 reg_def R3 ( SOC, SOC, Op_RegI, 3, R3->as_VMReg() ); // v iarg1 & iret 89 reg_def R3_H ( SOC, SOC, Op_RegI, 99, R3->as_VMReg()->next() ); 90 reg_def R4 ( SOC, SOC, Op_RegI, 4, R4->as_VMReg() ); // iarg2 91 reg_def R4_H ( SOC, SOC, Op_RegI, 99, R4->as_VMReg()->next() ); 92 reg_def R5 ( SOC, SOC, Op_RegI, 5, R5->as_VMReg() ); // v iarg3 93 reg_def R5_H ( SOC, SOC, Op_RegI, 99, R5->as_VMReg()->next() ); 94 reg_def R6 ( SOC, SOC, Op_RegI, 6, R6->as_VMReg() ); // v iarg4 95 reg_def R6_H ( SOC, SOC, Op_RegI, 99, R6->as_VMReg()->next() ); 96 reg_def R7 ( SOC, SOC, Op_RegI, 7, R7->as_VMReg() ); // v iarg5 97 reg_def R7_H ( SOC, SOC, Op_RegI, 99, R7->as_VMReg()->next() ); 98 reg_def R8 ( SOC, SOC, Op_RegI, 8, R8->as_VMReg() ); // v iarg6 99 reg_def R8_H ( SOC, SOC, Op_RegI, 99, R8->as_VMReg()->next() ); 100 reg_def R9 ( SOC, SOC, Op_RegI, 9, R9->as_VMReg() ); // v iarg7 101 reg_def R9_H ( SOC, SOC, Op_RegI, 99, R9->as_VMReg()->next() ); 102 reg_def R10 ( SOC, SOC, Op_RegI, 10, R10->as_VMReg() ); // v iarg8 103 reg_def R10_H( SOC, SOC, Op_RegI, 99, R10->as_VMReg()->next()); 104 reg_def R11 ( SOC, SOC, Op_RegI, 11, R11->as_VMReg() ); // v ENV / scratch 105 reg_def R11_H( SOC, SOC, Op_RegI, 99, R11->as_VMReg()->next()); 106 reg_def R12 ( SOC, SOC, Op_RegI, 12, R12->as_VMReg() ); // v scratch 107 reg_def R12_H( SOC, SOC, Op_RegI, 99, R12->as_VMReg()->next()); 108 reg_def R13 ( NS, NS, Op_RegI, 13, R13->as_VMReg() ); // s system thread id 109 reg_def R13_H( NS, NS, Op_RegI, 99, R13->as_VMReg()->next()); 110 reg_def R14 ( SOC, SOE, Op_RegI, 14, R14->as_VMReg() ); // nv 111 reg_def R14_H( SOC, SOE, Op_RegI, 99, R14->as_VMReg()->next()); 112 reg_def R15 ( SOC, SOE, Op_RegI, 15, R15->as_VMReg() ); // nv 113 reg_def R15_H( SOC, SOE, Op_RegI, 99, R15->as_VMReg()->next()); 114 reg_def R16 ( SOC, SOE, Op_RegI, 16, R16->as_VMReg() ); // nv 115 reg_def R16_H( SOC, SOE, Op_RegI, 99, R16->as_VMReg()->next()); 116 reg_def R17 ( SOC, SOE, Op_RegI, 17, R17->as_VMReg() ); // nv 117 reg_def R17_H( SOC, SOE, Op_RegI, 99, R17->as_VMReg()->next()); 118 reg_def R18 ( SOC, SOE, Op_RegI, 18, R18->as_VMReg() ); // nv 119 reg_def R18_H( SOC, SOE, Op_RegI, 99, R18->as_VMReg()->next()); 120 reg_def R19 ( SOC, SOE, Op_RegI, 19, R19->as_VMReg() ); // nv 121 reg_def R19_H( SOC, SOE, Op_RegI, 99, R19->as_VMReg()->next()); 122 reg_def R20 ( SOC, SOE, Op_RegI, 20, R20->as_VMReg() ); // nv 123 reg_def R20_H( SOC, SOE, Op_RegI, 99, R20->as_VMReg()->next()); 124 reg_def R21 ( SOC, SOE, Op_RegI, 21, R21->as_VMReg() ); // nv 125 reg_def R21_H( SOC, SOE, Op_RegI, 99, R21->as_VMReg()->next()); 126 reg_def R22 ( SOC, SOE, Op_RegI, 22, R22->as_VMReg() ); // nv 127 reg_def R22_H( SOC, SOE, Op_RegI, 99, R22->as_VMReg()->next()); 128 reg_def R23 ( SOC, SOE, Op_RegI, 23, R23->as_VMReg() ); // nv 129 reg_def R23_H( SOC, SOE, Op_RegI, 99, R23->as_VMReg()->next()); 130 reg_def R24 ( SOC, SOE, Op_RegI, 24, R24->as_VMReg() ); // nv 131 reg_def R24_H( SOC, SOE, Op_RegI, 99, R24->as_VMReg()->next()); 132 reg_def R25 ( SOC, SOE, Op_RegI, 25, R25->as_VMReg() ); // nv 133 reg_def R25_H( SOC, SOE, Op_RegI, 99, R25->as_VMReg()->next()); 134 reg_def R26 ( SOC, SOE, Op_RegI, 26, R26->as_VMReg() ); // nv 135 reg_def R26_H( SOC, SOE, Op_RegI, 99, R26->as_VMReg()->next()); 136 reg_def R27 ( SOC, SOE, Op_RegI, 27, R27->as_VMReg() ); // nv 137 reg_def R27_H( SOC, SOE, Op_RegI, 99, R27->as_VMReg()->next()); 138 reg_def R28 ( SOC, SOE, Op_RegI, 28, R28->as_VMReg() ); // nv 139 reg_def R28_H( SOC, SOE, Op_RegI, 99, R28->as_VMReg()->next()); 140 reg_def R29 ( SOC, SOE, Op_RegI, 29, R29->as_VMReg() ); // nv 141 reg_def R29_H( SOC, SOE, Op_RegI, 99, R29->as_VMReg()->next()); 142 reg_def R30 ( SOC, SOE, Op_RegI, 30, R30->as_VMReg() ); // nv 143 reg_def R30_H( SOC, SOE, Op_RegI, 99, R30->as_VMReg()->next()); 144 reg_def R31 ( SOC, SOE, Op_RegI, 31, R31->as_VMReg() ); // nv 145 reg_def R31_H( SOC, SOE, Op_RegI, 99, R31->as_VMReg()->next()); 146 147 148 // ---------------------------- 149 // Float/Double Registers 150 // ---------------------------- 151 152 // Double Registers 153 // The rules of ADL require that double registers be defined in pairs. 154 // Each pair must be two 32-bit values, but not necessarily a pair of 155 // single float registers. In each pair, ADLC-assigned register numbers 156 // must be adjacent, with the lower number even. Finally, when the 157 // CPU stores such a register pair to memory, the word associated with 158 // the lower ADLC-assigned number must be stored to the lower address. 159 160 // PPC64 has 32 64-bit floating-point registers. Each can store a single 161 // or double precision floating-point value. 162 163 // types: v = volatile, nv = non-volatile, s = system 164 reg_def F0 ( SOC, SOC, Op_RegF, 0, F0->as_VMReg() ); // v scratch 165 reg_def F0_H ( SOC, SOC, Op_RegF, 99, F0->as_VMReg()->next() ); 166 reg_def F1 ( SOC, SOC, Op_RegF, 1, F1->as_VMReg() ); // v farg1 & fret 167 reg_def F1_H ( SOC, SOC, Op_RegF, 99, F1->as_VMReg()->next() ); 168 reg_def F2 ( SOC, SOC, Op_RegF, 2, F2->as_VMReg() ); // v farg2 169 reg_def F2_H ( SOC, SOC, Op_RegF, 99, F2->as_VMReg()->next() ); 170 reg_def F3 ( SOC, SOC, Op_RegF, 3, F3->as_VMReg() ); // v farg3 171 reg_def F3_H ( SOC, SOC, Op_RegF, 99, F3->as_VMReg()->next() ); 172 reg_def F4 ( SOC, SOC, Op_RegF, 4, F4->as_VMReg() ); // v farg4 173 reg_def F4_H ( SOC, SOC, Op_RegF, 99, F4->as_VMReg()->next() ); 174 reg_def F5 ( SOC, SOC, Op_RegF, 5, F5->as_VMReg() ); // v farg5 175 reg_def F5_H ( SOC, SOC, Op_RegF, 99, F5->as_VMReg()->next() ); 176 reg_def F6 ( SOC, SOC, Op_RegF, 6, F6->as_VMReg() ); // v farg6 177 reg_def F6_H ( SOC, SOC, Op_RegF, 99, F6->as_VMReg()->next() ); 178 reg_def F7 ( SOC, SOC, Op_RegF, 7, F7->as_VMReg() ); // v farg7 179 reg_def F7_H ( SOC, SOC, Op_RegF, 99, F7->as_VMReg()->next() ); 180 reg_def F8 ( SOC, SOC, Op_RegF, 8, F8->as_VMReg() ); // v farg8 181 reg_def F8_H ( SOC, SOC, Op_RegF, 99, F8->as_VMReg()->next() ); 182 reg_def F9 ( SOC, SOC, Op_RegF, 9, F9->as_VMReg() ); // v farg9 183 reg_def F9_H ( SOC, SOC, Op_RegF, 99, F9->as_VMReg()->next() ); 184 reg_def F10 ( SOC, SOC, Op_RegF, 10, F10->as_VMReg() ); // v farg10 185 reg_def F10_H( SOC, SOC, Op_RegF, 99, F10->as_VMReg()->next()); 186 reg_def F11 ( SOC, SOC, Op_RegF, 11, F11->as_VMReg() ); // v farg11 187 reg_def F11_H( SOC, SOC, Op_RegF, 99, F11->as_VMReg()->next()); 188 reg_def F12 ( SOC, SOC, Op_RegF, 12, F12->as_VMReg() ); // v farg12 189 reg_def F12_H( SOC, SOC, Op_RegF, 99, F12->as_VMReg()->next()); 190 reg_def F13 ( SOC, SOC, Op_RegF, 13, F13->as_VMReg() ); // v farg13 191 reg_def F13_H( SOC, SOC, Op_RegF, 99, F13->as_VMReg()->next()); 192 reg_def F14 ( SOC, SOE, Op_RegF, 14, F14->as_VMReg() ); // nv 193 reg_def F14_H( SOC, SOE, Op_RegF, 99, F14->as_VMReg()->next()); 194 reg_def F15 ( SOC, SOE, Op_RegF, 15, F15->as_VMReg() ); // nv 195 reg_def F15_H( SOC, SOE, Op_RegF, 99, F15->as_VMReg()->next()); 196 reg_def F16 ( SOC, SOE, Op_RegF, 16, F16->as_VMReg() ); // nv 197 reg_def F16_H( SOC, SOE, Op_RegF, 99, F16->as_VMReg()->next()); 198 reg_def F17 ( SOC, SOE, Op_RegF, 17, F17->as_VMReg() ); // nv 199 reg_def F17_H( SOC, SOE, Op_RegF, 99, F17->as_VMReg()->next()); 200 reg_def F18 ( SOC, SOE, Op_RegF, 18, F18->as_VMReg() ); // nv 201 reg_def F18_H( SOC, SOE, Op_RegF, 99, F18->as_VMReg()->next()); 202 reg_def F19 ( SOC, SOE, Op_RegF, 19, F19->as_VMReg() ); // nv 203 reg_def F19_H( SOC, SOE, Op_RegF, 99, F19->as_VMReg()->next()); 204 reg_def F20 ( SOC, SOE, Op_RegF, 20, F20->as_VMReg() ); // nv 205 reg_def F20_H( SOC, SOE, Op_RegF, 99, F20->as_VMReg()->next()); 206 reg_def F21 ( SOC, SOE, Op_RegF, 21, F21->as_VMReg() ); // nv 207 reg_def F21_H( SOC, SOE, Op_RegF, 99, F21->as_VMReg()->next()); 208 reg_def F22 ( SOC, SOE, Op_RegF, 22, F22->as_VMReg() ); // nv 209 reg_def F22_H( SOC, SOE, Op_RegF, 99, F22->as_VMReg()->next()); 210 reg_def F23 ( SOC, SOE, Op_RegF, 23, F23->as_VMReg() ); // nv 211 reg_def F23_H( SOC, SOE, Op_RegF, 99, F23->as_VMReg()->next()); 212 reg_def F24 ( SOC, SOE, Op_RegF, 24, F24->as_VMReg() ); // nv 213 reg_def F24_H( SOC, SOE, Op_RegF, 99, F24->as_VMReg()->next()); 214 reg_def F25 ( SOC, SOE, Op_RegF, 25, F25->as_VMReg() ); // nv 215 reg_def F25_H( SOC, SOE, Op_RegF, 99, F25->as_VMReg()->next()); 216 reg_def F26 ( SOC, SOE, Op_RegF, 26, F26->as_VMReg() ); // nv 217 reg_def F26_H( SOC, SOE, Op_RegF, 99, F26->as_VMReg()->next()); 218 reg_def F27 ( SOC, SOE, Op_RegF, 27, F27->as_VMReg() ); // nv 219 reg_def F27_H( SOC, SOE, Op_RegF, 99, F27->as_VMReg()->next()); 220 reg_def F28 ( SOC, SOE, Op_RegF, 28, F28->as_VMReg() ); // nv 221 reg_def F28_H( SOC, SOE, Op_RegF, 99, F28->as_VMReg()->next()); 222 reg_def F29 ( SOC, SOE, Op_RegF, 29, F29->as_VMReg() ); // nv 223 reg_def F29_H( SOC, SOE, Op_RegF, 99, F29->as_VMReg()->next()); 224 reg_def F30 ( SOC, SOE, Op_RegF, 30, F30->as_VMReg() ); // nv 225 reg_def F30_H( SOC, SOE, Op_RegF, 99, F30->as_VMReg()->next()); 226 reg_def F31 ( SOC, SOE, Op_RegF, 31, F31->as_VMReg() ); // nv 227 reg_def F31_H( SOC, SOE, Op_RegF, 99, F31->as_VMReg()->next()); 228 229 // ---------------------------- 230 // Special Registers 231 // ---------------------------- 232 233 // Condition Codes Flag Registers 234 235 // PPC64 has 8 condition code "registers" which are all contained 236 // in the CR register. 237 238 // types: v = volatile, nv = non-volatile, s = system 239 reg_def CCR0(SOC, SOC, Op_RegFlags, 0, CCR0->as_VMReg()); // v 240 reg_def CCR1(SOC, SOC, Op_RegFlags, 1, CCR1->as_VMReg()); // v 241 reg_def CCR2(SOC, SOC, Op_RegFlags, 2, CCR2->as_VMReg()); // nv 242 reg_def CCR3(SOC, SOC, Op_RegFlags, 3, CCR3->as_VMReg()); // nv 243 reg_def CCR4(SOC, SOC, Op_RegFlags, 4, CCR4->as_VMReg()); // nv 244 reg_def CCR5(SOC, SOC, Op_RegFlags, 5, CCR5->as_VMReg()); // v 245 reg_def CCR6(SOC, SOC, Op_RegFlags, 6, CCR6->as_VMReg()); // v 246 reg_def CCR7(SOC, SOC, Op_RegFlags, 7, CCR7->as_VMReg()); // v 247 248 // Special registers of PPC64 249 250 reg_def SR_XER( SOC, SOC, Op_RegP, 0, SR_XER->as_VMReg()); // v 251 reg_def SR_LR( SOC, SOC, Op_RegP, 1, SR_LR->as_VMReg()); // v 252 reg_def SR_CTR( SOC, SOC, Op_RegP, 2, SR_CTR->as_VMReg()); // v 253 reg_def SR_VRSAVE( SOC, SOC, Op_RegP, 3, SR_VRSAVE->as_VMReg()); // v 254 reg_def SR_SPEFSCR(SOC, SOC, Op_RegP, 4, SR_SPEFSCR->as_VMReg()); // v 255 reg_def SR_PPR( SOC, SOC, Op_RegP, 5, SR_PPR->as_VMReg()); // v 256 257 258 // ---------------------------- 259 // Specify priority of register selection within phases of register 260 // allocation. Highest priority is first. A useful heuristic is to 261 // give registers a low priority when they are required by machine 262 // instructions, like EAX and EDX on I486, and choose no-save registers 263 // before save-on-call, & save-on-call before save-on-entry. Registers 264 // which participate in fixed calling sequences should come last. 265 // Registers which are used as pairs must fall on an even boundary. 266 267 // It's worth about 1% on SPEC geomean to get this right. 268 269 // Chunk0, chunk1, and chunk2 form the MachRegisterNumbers enumeration 270 // in adGlobals_ppc64.hpp which defines the <register>_num values, e.g. 271 // R3_num. Therefore, R3_num may not be (and in reality is not) 272 // the same as R3->encoding()! Furthermore, we cannot make any 273 // assumptions on ordering, e.g. R3_num may be less than R2_num. 274 // Additionally, the function 275 // static enum RC rc_class(OptoReg::Name reg ) 276 // maps a given <register>_num value to its chunk type (except for flags) 277 // and its current implementation relies on chunk0 and chunk1 having a 278 // size of 64 each. 279 280 // If you change this allocation class, please have a look at the 281 // default values for the parameters RoundRobinIntegerRegIntervalStart 282 // and RoundRobinFloatRegIntervalStart 283 284 alloc_class chunk0 ( 285 // Chunk0 contains *all* 64 integer registers halves. 286 287 // "non-volatile" registers 288 R14, R14_H, 289 R15, R15_H, 290 R17, R17_H, 291 R18, R18_H, 292 R19, R19_H, 293 R20, R20_H, 294 R21, R21_H, 295 R22, R22_H, 296 R23, R23_H, 297 R24, R24_H, 298 R25, R25_H, 299 R26, R26_H, 300 R27, R27_H, 301 R28, R28_H, 302 R29, R29_H, 303 R30, R30_H, 304 R31, R31_H, 305 306 // scratch/special registers 307 R11, R11_H, 308 R12, R12_H, 309 310 // argument registers 311 R10, R10_H, 312 R9, R9_H, 313 R8, R8_H, 314 R7, R7_H, 315 R6, R6_H, 316 R5, R5_H, 317 R4, R4_H, 318 R3, R3_H, 319 320 // special registers, not available for allocation 321 R16, R16_H, // R16_thread 322 R13, R13_H, // system thread id 323 R2, R2_H, // may be used for TOC 324 R1, R1_H, // SP 325 R0, R0_H // R0 (scratch) 326 ); 327 328 // If you change this allocation class, please have a look at the 329 // default values for the parameters RoundRobinIntegerRegIntervalStart 330 // and RoundRobinFloatRegIntervalStart 331 332 alloc_class chunk1 ( 333 // Chunk1 contains *all* 64 floating-point registers halves. 334 335 // scratch register 336 F0, F0_H, 337 338 // argument registers 339 F13, F13_H, 340 F12, F12_H, 341 F11, F11_H, 342 F10, F10_H, 343 F9, F9_H, 344 F8, F8_H, 345 F7, F7_H, 346 F6, F6_H, 347 F5, F5_H, 348 F4, F4_H, 349 F3, F3_H, 350 F2, F2_H, 351 F1, F1_H, 352 353 // non-volatile registers 354 F14, F14_H, 355 F15, F15_H, 356 F16, F16_H, 357 F17, F17_H, 358 F18, F18_H, 359 F19, F19_H, 360 F20, F20_H, 361 F21, F21_H, 362 F22, F22_H, 363 F23, F23_H, 364 F24, F24_H, 365 F25, F25_H, 366 F26, F26_H, 367 F27, F27_H, 368 F28, F28_H, 369 F29, F29_H, 370 F30, F30_H, 371 F31, F31_H 372 ); 373 374 alloc_class chunk2 ( 375 // Chunk2 contains *all* 8 condition code registers. 376 377 CCR0, 378 CCR1, 379 CCR2, 380 CCR3, 381 CCR4, 382 CCR5, 383 CCR6, 384 CCR7 385 ); 386 387 alloc_class chunk3 ( 388 // special registers 389 // These registers are not allocated, but used for nodes generated by postalloc expand. 390 SR_XER, 391 SR_LR, 392 SR_CTR, 393 SR_VRSAVE, 394 SR_SPEFSCR, 395 SR_PPR 396 ); 397 398 //-------Architecture Description Register Classes----------------------- 399 400 // Several register classes are automatically defined based upon 401 // information in this architecture description. 402 403 // 1) reg_class inline_cache_reg ( as defined in frame section ) 404 // 2) reg_class compiler_method_oop_reg ( as defined in frame section ) 405 // 2) reg_class interpreter_method_oop_reg ( as defined in frame section ) 406 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ ) 407 // 408 409 // ---------------------------- 410 // 32 Bit Register Classes 411 // ---------------------------- 412 413 // We specify registers twice, once as read/write, and once read-only. 414 // We use the read-only registers for source operands. With this, we 415 // can include preset read only registers in this class, as a hard-coded 416 // '0'-register. (We used to simulate this on ppc.) 417 418 // 32 bit registers that can be read and written i.e. these registers 419 // can be dest (or src) of normal instructions. 420 reg_class bits32_reg_rw( 421 /*R0*/ // R0 422 /*R1*/ // SP 423 R2, // TOC 424 R3, 425 R4, 426 R5, 427 R6, 428 R7, 429 R8, 430 R9, 431 R10, 432 R11, 433 R12, 434 /*R13*/ // system thread id 435 R14, 436 R15, 437 /*R16*/ // R16_thread 438 R17, 439 R18, 440 R19, 441 R20, 442 R21, 443 R22, 444 R23, 445 R24, 446 R25, 447 R26, 448 R27, 449 R28, 450 /*R29*/ // global TOC 451 /*R30*/ // Narrow Oop Base 452 R31 453 ); 454 455 // 32 bit registers that can only be read i.e. these registers can 456 // only be src of all instructions. 457 reg_class bits32_reg_ro( 458 /*R0*/ // R0 459 /*R1*/ // SP 460 R2 // TOC 461 R3, 462 R4, 463 R5, 464 R6, 465 R7, 466 R8, 467 R9, 468 R10, 469 R11, 470 R12, 471 /*R13*/ // system thread id 472 R14, 473 R15, 474 /*R16*/ // R16_thread 475 R17, 476 R18, 477 R19, 478 R20, 479 R21, 480 R22, 481 R23, 482 R24, 483 R25, 484 R26, 485 R27, 486 R28, 487 /*R29*/ 488 /*R30*/ // Narrow Oop Base 489 R31 490 ); 491 492 // Complement-required-in-pipeline operands for narrow oops. 493 reg_class bits32_reg_ro_not_complement ( 494 /*R0*/ // R0 495 R1, // SP 496 R2, // TOC 497 R3, 498 R4, 499 R5, 500 R6, 501 R7, 502 R8, 503 R9, 504 R10, 505 R11, 506 R12, 507 /*R13,*/ // system thread id 508 R14, 509 R15, 510 R16, // R16_thread 511 R17, 512 R18, 513 R19, 514 R20, 515 R21, 516 R22, 517 /*R23, 518 R24, 519 R25, 520 R26, 521 R27, 522 R28,*/ 523 /*R29,*/ // TODO: let allocator handle TOC!! 524 /*R30,*/ 525 R31 526 ); 527 528 // Complement-required-in-pipeline operands for narrow oops. 529 // See 64-bit declaration. 530 reg_class bits32_reg_ro_complement ( 531 R23, 532 R24, 533 R25, 534 R26, 535 R27, 536 R28 537 ); 538 539 reg_class rscratch1_bits32_reg(R11); 540 reg_class rscratch2_bits32_reg(R12); 541 reg_class rarg1_bits32_reg(R3); 542 reg_class rarg2_bits32_reg(R4); 543 reg_class rarg3_bits32_reg(R5); 544 reg_class rarg4_bits32_reg(R6); 545 546 // ---------------------------- 547 // 64 Bit Register Classes 548 // ---------------------------- 549 // 64-bit build means 64-bit pointers means hi/lo pairs 550 551 reg_class rscratch1_bits64_reg(R11_H, R11); 552 reg_class rscratch2_bits64_reg(R12_H, R12); 553 reg_class rarg1_bits64_reg(R3_H, R3); 554 reg_class rarg2_bits64_reg(R4_H, R4); 555 reg_class rarg3_bits64_reg(R5_H, R5); 556 reg_class rarg4_bits64_reg(R6_H, R6); 557 // Thread register, 'written' by tlsLoadP, see there. 558 reg_class thread_bits64_reg(R16_H, R16); 559 560 reg_class r19_bits64_reg(R19_H, R19); 561 562 // 64 bit registers that can be read and written i.e. these registers 563 // can be dest (or src) of normal instructions. 564 reg_class bits64_reg_rw( 565 /*R0_H, R0*/ // R0 566 /*R1_H, R1*/ // SP 567 R2_H, R2, // TOC 568 R3_H, R3, 569 R4_H, R4, 570 R5_H, R5, 571 R6_H, R6, 572 R7_H, R7, 573 R8_H, R8, 574 R9_H, R9, 575 R10_H, R10, 576 R11_H, R11, 577 R12_H, R12, 578 /*R13_H, R13*/ // system thread id 579 R14_H, R14, 580 R15_H, R15, 581 /*R16_H, R16*/ // R16_thread 582 R17_H, R17, 583 R18_H, R18, 584 R19_H, R19, 585 R20_H, R20, 586 R21_H, R21, 587 R22_H, R22, 588 R23_H, R23, 589 R24_H, R24, 590 R25_H, R25, 591 R26_H, R26, 592 R27_H, R27, 593 R28_H, R28, 594 /*R29_H, R29*/ 595 /*R30_H, R30*/ 596 R31_H, R31 597 ); 598 599 // 64 bit registers used excluding r2, r11 and r12 600 // Used to hold the TOC to avoid collisions with expanded LeafCall which uses 601 // r2, r11 and r12 internally. 602 reg_class bits64_reg_leaf_call( 603 /*R0_H, R0*/ // R0 604 /*R1_H, R1*/ // SP 605 /*R2_H, R2*/ // TOC 606 R3_H, R3, 607 R4_H, R4, 608 R5_H, R5, 609 R6_H, R6, 610 R7_H, R7, 611 R8_H, R8, 612 R9_H, R9, 613 R10_H, R10, 614 /*R11_H, R11*/ 615 /*R12_H, R12*/ 616 /*R13_H, R13*/ // system thread id 617 R14_H, R14, 618 R15_H, R15, 619 /*R16_H, R16*/ // R16_thread 620 R17_H, R17, 621 R18_H, R18, 622 R19_H, R19, 623 R20_H, R20, 624 R21_H, R21, 625 R22_H, R22, 626 R23_H, R23, 627 R24_H, R24, 628 R25_H, R25, 629 R26_H, R26, 630 R27_H, R27, 631 R28_H, R28, 632 /*R29_H, R29*/ 633 /*R30_H, R30*/ 634 R31_H, R31 635 ); 636 637 // Used to hold the TOC to avoid collisions with expanded DynamicCall 638 // which uses r19 as inline cache internally and expanded LeafCall which uses 639 // r2, r11 and r12 internally. 640 reg_class bits64_constant_table_base( 641 /*R0_H, R0*/ // R0 642 /*R1_H, R1*/ // SP 643 /*R2_H, R2*/ // TOC 644 R3_H, R3, 645 R4_H, R4, 646 R5_H, R5, 647 R6_H, R6, 648 R7_H, R7, 649 R8_H, R8, 650 R9_H, R9, 651 R10_H, R10, 652 /*R11_H, R11*/ 653 /*R12_H, R12*/ 654 /*R13_H, R13*/ // system thread id 655 R14_H, R14, 656 R15_H, R15, 657 /*R16_H, R16*/ // R16_thread 658 R17_H, R17, 659 R18_H, R18, 660 /*R19_H, R19*/ 661 R20_H, R20, 662 R21_H, R21, 663 R22_H, R22, 664 R23_H, R23, 665 R24_H, R24, 666 R25_H, R25, 667 R26_H, R26, 668 R27_H, R27, 669 R28_H, R28, 670 /*R29_H, R29*/ 671 /*R30_H, R30*/ 672 R31_H, R31 673 ); 674 675 // 64 bit registers that can only be read i.e. these registers can 676 // only be src of all instructions. 677 reg_class bits64_reg_ro( 678 /*R0_H, R0*/ // R0 679 R1_H, R1, 680 R2_H, R2, // TOC 681 R3_H, R3, 682 R4_H, R4, 683 R5_H, R5, 684 R6_H, R6, 685 R7_H, R7, 686 R8_H, R8, 687 R9_H, R9, 688 R10_H, R10, 689 R11_H, R11, 690 R12_H, R12, 691 /*R13_H, R13*/ // system thread id 692 R14_H, R14, 693 R15_H, R15, 694 R16_H, R16, // R16_thread 695 R17_H, R17, 696 R18_H, R18, 697 R19_H, R19, 698 R20_H, R20, 699 R21_H, R21, 700 R22_H, R22, 701 R23_H, R23, 702 R24_H, R24, 703 R25_H, R25, 704 R26_H, R26, 705 R27_H, R27, 706 R28_H, R28, 707 /*R29_H, R29*/ // TODO: let allocator handle TOC!! 708 /*R30_H, R30,*/ 709 R31_H, R31 710 ); 711 712 // Complement-required-in-pipeline operands. 713 reg_class bits64_reg_ro_not_complement ( 714 /*R0_H, R0*/ // R0 715 R1_H, R1, // SP 716 R2_H, R2, // TOC 717 R3_H, R3, 718 R4_H, R4, 719 R5_H, R5, 720 R6_H, R6, 721 R7_H, R7, 722 R8_H, R8, 723 R9_H, R9, 724 R10_H, R10, 725 R11_H, R11, 726 R12_H, R12, 727 /*R13_H, R13*/ // system thread id 728 R14_H, R14, 729 R15_H, R15, 730 R16_H, R16, // R16_thread 731 R17_H, R17, 732 R18_H, R18, 733 R19_H, R19, 734 R20_H, R20, 735 R21_H, R21, 736 R22_H, R22, 737 /*R23_H, R23, 738 R24_H, R24, 739 R25_H, R25, 740 R26_H, R26, 741 R27_H, R27, 742 R28_H, R28,*/ 743 /*R29_H, R29*/ // TODO: let allocator handle TOC!! 744 /*R30_H, R30,*/ 745 R31_H, R31 746 ); 747 748 // Complement-required-in-pipeline operands. 749 // This register mask is used for the trap instructions that implement 750 // the null checks on AIX. The trap instruction first computes the 751 // complement of the value it shall trap on. Because of this, the 752 // instruction can not be scheduled in the same cycle as an other 753 // instruction reading the normal value of the same register. So we 754 // force the value to check into 'bits64_reg_ro_not_complement' 755 // and then copy it to 'bits64_reg_ro_complement' for the trap. 756 reg_class bits64_reg_ro_complement ( 757 R23_H, R23, 758 R24_H, R24, 759 R25_H, R25, 760 R26_H, R26, 761 R27_H, R27, 762 R28_H, R28 763 ); 764 765 766 // ---------------------------- 767 // Special Class for Condition Code Flags Register 768 769 reg_class int_flags( 770 /*CCR0*/ // scratch 771 /*CCR1*/ // scratch 772 /*CCR2*/ // nv! 773 /*CCR3*/ // nv! 774 /*CCR4*/ // nv! 775 CCR5, 776 CCR6, 777 CCR7 778 ); 779 780 reg_class int_flags_CR0(CCR0); 781 reg_class int_flags_CR1(CCR1); 782 reg_class int_flags_CR6(CCR6); 783 reg_class ctr_reg(SR_CTR); 784 785 // ---------------------------- 786 // Float Register Classes 787 // ---------------------------- 788 789 reg_class flt_reg( 790 /*F0*/ // scratch 791 F1, 792 F2, 793 F3, 794 F4, 795 F5, 796 F6, 797 F7, 798 F8, 799 F9, 800 F10, 801 F11, 802 F12, 803 F13, 804 F14, // nv! 805 F15, // nv! 806 F16, // nv! 807 F17, // nv! 808 F18, // nv! 809 F19, // nv! 810 F20, // nv! 811 F21, // nv! 812 F22, // nv! 813 F23, // nv! 814 F24, // nv! 815 F25, // nv! 816 F26, // nv! 817 F27, // nv! 818 F28, // nv! 819 F29, // nv! 820 F30, // nv! 821 F31 // nv! 822 ); 823 824 // Double precision float registers have virtual `high halves' that 825 // are needed by the allocator. 826 reg_class dbl_reg( 827 /*F0, F0_H*/ // scratch 828 F1, F1_H, 829 F2, F2_H, 830 F3, F3_H, 831 F4, F4_H, 832 F5, F5_H, 833 F6, F6_H, 834 F7, F7_H, 835 F8, F8_H, 836 F9, F9_H, 837 F10, F10_H, 838 F11, F11_H, 839 F12, F12_H, 840 F13, F13_H, 841 F14, F14_H, // nv! 842 F15, F15_H, // nv! 843 F16, F16_H, // nv! 844 F17, F17_H, // nv! 845 F18, F18_H, // nv! 846 F19, F19_H, // nv! 847 F20, F20_H, // nv! 848 F21, F21_H, // nv! 849 F22, F22_H, // nv! 850 F23, F23_H, // nv! 851 F24, F24_H, // nv! 852 F25, F25_H, // nv! 853 F26, F26_H, // nv! 854 F27, F27_H, // nv! 855 F28, F28_H, // nv! 856 F29, F29_H, // nv! 857 F30, F30_H, // nv! 858 F31, F31_H // nv! 859 ); 860 861 %} 862 863 //----------DEFINITION BLOCK--------------------------------------------------- 864 // Define name --> value mappings to inform the ADLC of an integer valued name 865 // Current support includes integer values in the range [0, 0x7FFFFFFF] 866 // Format: 867 // int_def <name> ( <int_value>, <expression>); 868 // Generated Code in ad_<arch>.hpp 869 // #define <name> (<expression>) 870 // // value == <int_value> 871 // Generated code in ad_<arch>.cpp adlc_verification() 872 // assert( <name> == <int_value>, "Expect (<expression>) to equal <int_value>"); 873 // 874 definitions %{ 875 // The default cost (of an ALU instruction). 876 int_def DEFAULT_COST_LOW ( 30, 30); 877 int_def DEFAULT_COST ( 100, 100); 878 int_def HUGE_COST (1000000, 1000000); 879 880 // Memory refs 881 int_def MEMORY_REF_COST_LOW ( 200, DEFAULT_COST * 2); 882 int_def MEMORY_REF_COST ( 300, DEFAULT_COST * 3); 883 884 // Branches are even more expensive. 885 int_def BRANCH_COST ( 900, DEFAULT_COST * 9); 886 int_def CALL_COST ( 1300, DEFAULT_COST * 13); 887 %} 888 889 890 //----------SOURCE BLOCK------------------------------------------------------- 891 // This is a block of C++ code which provides values, functions, and 892 // definitions necessary in the rest of the architecture description. 893 source_hpp %{ 894 // Header information of the source block. 895 // Method declarations/definitions which are used outside 896 // the ad-scope can conveniently be defined here. 897 // 898 // To keep related declarations/definitions/uses close together, 899 // we switch between source %{ }% and source_hpp %{ }% freely as needed. 900 901 // Returns true if Node n is followed by a MemBar node that 902 // will do an acquire. If so, this node must not do the acquire 903 // operation. 904 bool followed_by_acquire(const Node *n); 905 %} 906 907 source %{ 908 909 // Optimize load-acquire. 910 // 911 // Check if acquire is unnecessary due to following operation that does 912 // acquire anyways. 913 // Walk the pattern: 914 // 915 // n: Load.acq 916 // | 917 // MemBarAcquire 918 // | | 919 // Proj(ctrl) Proj(mem) 920 // | | 921 // MemBarRelease/Volatile 922 // 923 bool followed_by_acquire(const Node *load) { 924 assert(load->is_Load(), "So far implemented only for loads."); 925 926 // Find MemBarAcquire. 927 const Node *mba = NULL; 928 for (DUIterator_Fast imax, i = load->fast_outs(imax); i < imax; i++) { 929 const Node *out = load->fast_out(i); 930 if (out->Opcode() == Op_MemBarAcquire) { 931 if (out->in(0) == load) continue; // Skip control edge, membar should be found via precedence edge. 932 mba = out; 933 break; 934 } 935 } 936 if (!mba) return false; 937 938 // Find following MemBar node. 939 // 940 // The following node must be reachable by control AND memory 941 // edge to assure no other operations are in between the two nodes. 942 // 943 // So first get the Proj node, mem_proj, to use it to iterate forward. 944 Node *mem_proj = NULL; 945 for (DUIterator_Fast imax, i = mba->fast_outs(imax); i < imax; i++) { 946 mem_proj = mba->fast_out(i); // Throw out-of-bounds if proj not found 947 assert(mem_proj->is_Proj(), "only projections here"); 948 ProjNode *proj = mem_proj->as_Proj(); 949 if (proj->_con == TypeFunc::Memory && 950 !Compile::current()->node_arena()->contains(mem_proj)) // Unmatched old-space only 951 break; 952 } 953 assert(mem_proj->as_Proj()->_con == TypeFunc::Memory, "Graph broken"); 954 955 // Search MemBar behind Proj. If there are other memory operations 956 // behind the Proj we lost. 957 for (DUIterator_Fast jmax, j = mem_proj->fast_outs(jmax); j < jmax; j++) { 958 Node *x = mem_proj->fast_out(j); 959 // Proj might have an edge to a store or load node which precedes the membar. 960 if (x->is_Mem()) return false; 961 962 // On PPC64 release and volatile are implemented by an instruction 963 // that also has acquire semantics. I.e. there is no need for an 964 // acquire before these. 965 int xop = x->Opcode(); 966 if (xop == Op_MemBarRelease || xop == Op_MemBarVolatile) { 967 // Make sure we're not missing Call/Phi/MergeMem by checking 968 // control edges. The control edge must directly lead back 969 // to the MemBarAcquire 970 Node *ctrl_proj = x->in(0); 971 if (ctrl_proj->is_Proj() && ctrl_proj->in(0) == mba) { 972 return true; 973 } 974 } 975 } 976 977 return false; 978 } 979 980 #define __ _masm. 981 982 // Tertiary op of a LoadP or StoreP encoding. 983 #define REGP_OP true 984 985 // **************************************************************************** 986 987 // REQUIRED FUNCTIONALITY 988 989 // !!!!! Special hack to get all type of calls to specify the byte offset 990 // from the start of the call to the point where the return address 991 // will point. 992 993 // PPC port: Removed use of lazy constant construct. 994 995 int MachCallStaticJavaNode::ret_addr_offset() { 996 // It's only a single branch-and-link instruction. 997 return 4; 998 } 999 1000 int MachCallDynamicJavaNode::ret_addr_offset() { 1001 // Offset is 4 with postalloc expanded calls (bl is one instruction). We use 1002 // postalloc expanded calls if we use inline caches and do not update method data. 1003 if (UseInlineCaches) 1004 return 4; 1005 1006 int vtable_index = this->_vtable_index; 1007 if (vtable_index < 0) { 1008 // Must be invalid_vtable_index, not nonvirtual_vtable_index. 1009 assert(vtable_index == Method::invalid_vtable_index, "correct sentinel value"); 1010 return 12; 1011 } else { 1012 assert(!UseInlineCaches, "expect vtable calls only if not using ICs"); 1013 return 24; 1014 } 1015 } 1016 1017 int MachCallRuntimeNode::ret_addr_offset() { 1018 #if defined(ABI_ELFv2) 1019 return 28; 1020 #else 1021 return 40; 1022 #endif 1023 } 1024 1025 //============================================================================= 1026 1027 // condition code conversions 1028 1029 static int cc_to_boint(int cc) { 1030 return Assembler::bcondCRbiIs0 | (cc & 8); 1031 } 1032 1033 static int cc_to_inverse_boint(int cc) { 1034 return Assembler::bcondCRbiIs0 | (8-(cc & 8)); 1035 } 1036 1037 static int cc_to_biint(int cc, int flags_reg) { 1038 return (flags_reg << 2) | (cc & 3); 1039 } 1040 1041 //============================================================================= 1042 1043 // Compute padding required for nodes which need alignment. The padding 1044 // is the number of bytes (not instructions) which will be inserted before 1045 // the instruction. The padding must match the size of a NOP instruction. 1046 1047 int string_indexOf_imm1_charNode::compute_padding(int current_offset) const { 1048 return (3*4-current_offset)&31; 1049 } 1050 1051 int string_indexOf_imm1Node::compute_padding(int current_offset) const { 1052 return (2*4-current_offset)&31; 1053 } 1054 1055 int string_indexOf_immNode::compute_padding(int current_offset) const { 1056 return (3*4-current_offset)&31; 1057 } 1058 1059 int string_indexOfNode::compute_padding(int current_offset) const { 1060 return (1*4-current_offset)&31; 1061 } 1062 1063 int string_compareNode::compute_padding(int current_offset) const { 1064 return (4*4-current_offset)&31; 1065 } 1066 1067 int string_equals_immNode::compute_padding(int current_offset) const { 1068 if (opnd_array(3)->constant() < 16) return 0; // Don't insert nops for short version (loop completely unrolled). 1069 return (2*4-current_offset)&31; 1070 } 1071 1072 int string_equalsNode::compute_padding(int current_offset) const { 1073 return (7*4-current_offset)&31; 1074 } 1075 1076 int inlineCallClearArrayNode::compute_padding(int current_offset) const { 1077 return (2*4-current_offset)&31; 1078 } 1079 1080 //============================================================================= 1081 1082 // Indicate if the safepoint node needs the polling page as an input. 1083 bool SafePointNode::needs_polling_address_input() { 1084 // The address is loaded from thread by a seperate node. 1085 return true; 1086 } 1087 1088 //============================================================================= 1089 1090 // Emit an interrupt that is caught by the debugger (for debugging compiler). 1091 void emit_break(CodeBuffer &cbuf) { 1092 MacroAssembler _masm(&cbuf); 1093 __ illtrap(); 1094 } 1095 1096 #ifndef PRODUCT 1097 void MachBreakpointNode::format(PhaseRegAlloc *ra_, outputStream *st) const { 1098 st->print("BREAKPOINT"); 1099 } 1100 #endif 1101 1102 void MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 1103 emit_break(cbuf); 1104 } 1105 1106 uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const { 1107 return MachNode::size(ra_); 1108 } 1109 1110 //============================================================================= 1111 1112 void emit_nop(CodeBuffer &cbuf) { 1113 MacroAssembler _masm(&cbuf); 1114 __ nop(); 1115 } 1116 1117 static inline void emit_long(CodeBuffer &cbuf, int value) { 1118 *((int*)(cbuf.insts_end())) = value; 1119 cbuf.set_insts_end(cbuf.insts_end() + BytesPerInstWord); 1120 } 1121 1122 //============================================================================= 1123 1124 %} // interrupt source 1125 1126 source_hpp %{ // Header information of the source block. 1127 1128 //-------------------------------------------------------------- 1129 //---< Used for optimization in Compile::Shorten_branches >--- 1130 //-------------------------------------------------------------- 1131 1132 const uint trampoline_stub_size = 6 * BytesPerInstWord; 1133 1134 class CallStubImpl { 1135 1136 public: 1137 1138 // Emit call stub, compiled java to interpreter. 1139 static void emit_trampoline_stub(MacroAssembler &_masm, int destination_toc_offset, int insts_call_instruction_offset); 1140 1141 // Size of call trampoline stub. 1142 // This doesn't need to be accurate to the byte, but it 1143 // must be larger than or equal to the real size of the stub. 1144 static uint size_call_trampoline() { 1145 return trampoline_stub_size; 1146 } 1147 1148 // number of relocations needed by a call trampoline stub 1149 static uint reloc_call_trampoline() { 1150 return 5; 1151 } 1152 1153 }; 1154 1155 %} // end source_hpp 1156 1157 source %{ 1158 1159 // Emit a trampoline stub for a call to a target which is too far away. 1160 // 1161 // code sequences: 1162 // 1163 // call-site: 1164 // branch-and-link to <destination> or <trampoline stub> 1165 // 1166 // Related trampoline stub for this call-site in the stub section: 1167 // load the call target from the constant pool 1168 // branch via CTR (LR/link still points to the call-site above) 1169 1170 void CallStubImpl::emit_trampoline_stub(MacroAssembler &_masm, int destination_toc_offset, int insts_call_instruction_offset) { 1171 // Start the stub. 1172 address stub = __ start_a_stub(Compile::MAX_stubs_size/2); 1173 if (stub == NULL) { 1174 Compile::current()->env()->record_out_of_memory_failure(); 1175 return; 1176 } 1177 1178 // For java_to_interp stubs we use R11_scratch1 as scratch register 1179 // and in call trampoline stubs we use R12_scratch2. This way we 1180 // can distinguish them (see is_NativeCallTrampolineStub_at()). 1181 Register reg_scratch = R12_scratch2; 1182 1183 // Create a trampoline stub relocation which relates this trampoline stub 1184 // with the call instruction at insts_call_instruction_offset in the 1185 // instructions code-section. 1186 __ relocate(trampoline_stub_Relocation::spec(__ code()->insts()->start() + insts_call_instruction_offset)); 1187 const int stub_start_offset = __ offset(); 1188 1189 // Now, create the trampoline stub's code: 1190 // - load the TOC 1191 // - load the call target from the constant pool 1192 // - call 1193 __ calculate_address_from_global_toc(reg_scratch, __ method_toc()); 1194 __ ld_largeoffset_unchecked(reg_scratch, destination_toc_offset, reg_scratch, false); 1195 __ mtctr(reg_scratch); 1196 __ bctr(); 1197 1198 const address stub_start_addr = __ addr_at(stub_start_offset); 1199 1200 // FIXME: Assert that the trampoline stub can be identified and patched. 1201 1202 // Assert that the encoded destination_toc_offset can be identified and that it is correct. 1203 assert(destination_toc_offset == NativeCallTrampolineStub_at(stub_start_addr)->destination_toc_offset(), 1204 "encoded offset into the constant pool must match"); 1205 // Trampoline_stub_size should be good. 1206 assert((uint)(__ offset() - stub_start_offset) <= trampoline_stub_size, "should be good size"); 1207 assert(is_NativeCallTrampolineStub_at(stub_start_addr), "doesn't look like a trampoline"); 1208 1209 // End the stub. 1210 __ end_a_stub(); 1211 } 1212 1213 //============================================================================= 1214 1215 // Emit an inline branch-and-link call and a related trampoline stub. 1216 // 1217 // code sequences: 1218 // 1219 // call-site: 1220 // branch-and-link to <destination> or <trampoline stub> 1221 // 1222 // Related trampoline stub for this call-site in the stub section: 1223 // load the call target from the constant pool 1224 // branch via CTR (LR/link still points to the call-site above) 1225 // 1226 1227 typedef struct { 1228 int insts_call_instruction_offset; 1229 int ret_addr_offset; 1230 } EmitCallOffsets; 1231 1232 // Emit a branch-and-link instruction that branches to a trampoline. 1233 // - Remember the offset of the branch-and-link instruction. 1234 // - Add a relocation at the branch-and-link instruction. 1235 // - Emit a branch-and-link. 1236 // - Remember the return pc offset. 1237 EmitCallOffsets emit_call_with_trampoline_stub(MacroAssembler &_masm, address entry_point, relocInfo::relocType rtype) { 1238 EmitCallOffsets offsets = { -1, -1 }; 1239 const int start_offset = __ offset(); 1240 offsets.insts_call_instruction_offset = __ offset(); 1241 1242 // No entry point given, use the current pc. 1243 if (entry_point == NULL) entry_point = __ pc(); 1244 1245 if (!Compile::current()->in_scratch_emit_size()) { 1246 // Put the entry point as a constant into the constant pool. 1247 const address entry_point_toc_addr = __ address_constant(entry_point, RelocationHolder::none); 1248 const int entry_point_toc_offset = __ offset_to_method_toc(entry_point_toc_addr); 1249 1250 // Emit the trampoline stub which will be related to the branch-and-link below. 1251 CallStubImpl::emit_trampoline_stub(_masm, entry_point_toc_offset, offsets.insts_call_instruction_offset); 1252 if (Compile::current()->env()->failing()) { return offsets; } // Code cache may be full. 1253 __ relocate(rtype); 1254 } 1255 1256 // Note: At this point we do not have the address of the trampoline 1257 // stub, and the entry point might be too far away for bl, so __ pc() 1258 // serves as dummy and the bl will be patched later. 1259 __ bl((address) __ pc()); 1260 1261 offsets.ret_addr_offset = __ offset() - start_offset; 1262 1263 return offsets; 1264 } 1265 1266 //============================================================================= 1267 1268 // Factory for creating loadConL* nodes for large/small constant pool. 1269 1270 static inline jlong replicate_immF(float con) { 1271 // Replicate float con 2 times and pack into vector. 1272 int val = *((int*)&con); 1273 jlong lval = val; 1274 lval = (lval << 32) | (lval & 0xFFFFFFFFl); 1275 return lval; 1276 } 1277 1278 //============================================================================= 1279 1280 const RegMask& MachConstantBaseNode::_out_RegMask = BITS64_CONSTANT_TABLE_BASE_mask(); 1281 int Compile::ConstantTable::calculate_table_base_offset() const { 1282 return 0; // absolute addressing, no offset 1283 } 1284 1285 bool MachConstantBaseNode::requires_postalloc_expand() const { return true; } 1286 void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) { 1287 Compile *C = ra_->C; 1288 1289 iRegPdstOper *op_dst = new (C) iRegPdstOper(); 1290 MachNode *m1 = new (C) loadToc_hiNode(); 1291 MachNode *m2 = new (C) loadToc_loNode(); 1292 1293 m1->add_req(NULL); 1294 m2->add_req(NULL, m1); 1295 m1->_opnds[0] = op_dst; 1296 m2->_opnds[0] = op_dst; 1297 m2->_opnds[1] = op_dst; 1298 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 1299 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 1300 nodes->push(m1); 1301 nodes->push(m2); 1302 } 1303 1304 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const { 1305 // Is postalloc expanded. 1306 ShouldNotReachHere(); 1307 } 1308 1309 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const { 1310 return 0; 1311 } 1312 1313 #ifndef PRODUCT 1314 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const { 1315 st->print("-- \t// MachConstantBaseNode (empty encoding)"); 1316 } 1317 #endif 1318 1319 //============================================================================= 1320 1321 #ifndef PRODUCT 1322 void MachPrologNode::format(PhaseRegAlloc *ra_, outputStream *st) const { 1323 Compile* C = ra_->C; 1324 const long framesize = C->frame_slots() << LogBytesPerInt; 1325 1326 st->print("PROLOG\n\t"); 1327 if (C->need_stack_bang(framesize)) { 1328 st->print("stack_overflow_check\n\t"); 1329 } 1330 1331 if (!false /* TODO: PPC port C->is_frameless_method()*/) { 1332 st->print("save return pc\n\t"); 1333 st->print("push frame %ld\n\t", -framesize); 1334 } 1335 } 1336 #endif 1337 1338 // Macro used instead of the common __ to emulate the pipes of PPC. 1339 // Instead of e.g. __ ld(...) one hase to write ___(ld) ld(...) This enables the 1340 // micro scheduler to cope with "hand written" assembler like in the prolog. Though 1341 // still no scheduling of this code is possible, the micro scheduler is aware of the 1342 // code and can update its internal data. The following mechanism is used to achieve this: 1343 // The micro scheduler calls size() of each compound node during scheduling. size() does a 1344 // dummy emit and only during this dummy emit C->hb_scheduling() is not NULL. 1345 #if 0 // TODO: PPC port 1346 #define ___(op) if (UsePower6SchedulerPPC64 && C->hb_scheduling()) \ 1347 C->hb_scheduling()->_pdScheduling->PdEmulatePipe(ppc64Opcode_##op); \ 1348 _masm. 1349 #define ___stop if (UsePower6SchedulerPPC64 && C->hb_scheduling()) \ 1350 C->hb_scheduling()->_pdScheduling->PdEmulatePipe(archOpcode_none) 1351 #define ___advance if (UsePower6SchedulerPPC64 && C->hb_scheduling()) \ 1352 C->hb_scheduling()->_pdScheduling->advance_offset 1353 #else 1354 #define ___(op) if (UsePower6SchedulerPPC64) \ 1355 Unimplemented(); \ 1356 _masm. 1357 #define ___stop if (UsePower6SchedulerPPC64) \ 1358 Unimplemented() 1359 #define ___advance if (UsePower6SchedulerPPC64) \ 1360 Unimplemented() 1361 #endif 1362 1363 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 1364 Compile* C = ra_->C; 1365 MacroAssembler _masm(&cbuf); 1366 1367 const long framesize = C->frame_size_in_bytes(); 1368 assert(framesize % (2 * wordSize) == 0, "must preserve 2*wordSize alignment"); 1369 1370 const bool method_is_frameless = false /* TODO: PPC port C->is_frameless_method()*/; 1371 1372 const Register return_pc = R20; // Must match return_addr() in frame section. 1373 const Register callers_sp = R21; 1374 const Register push_frame_temp = R22; 1375 const Register toc_temp = R23; 1376 assert_different_registers(R11, return_pc, callers_sp, push_frame_temp, toc_temp); 1377 1378 if (method_is_frameless) { 1379 // Add nop at beginning of all frameless methods to prevent any 1380 // oop instructions from getting overwritten by make_not_entrant 1381 // (patching attempt would fail). 1382 ___(nop) nop(); 1383 } else { 1384 // Get return pc. 1385 ___(mflr) mflr(return_pc); 1386 } 1387 1388 // Calls to C2R adapters often do not accept exceptional returns. 1389 // We require that their callers must bang for them. But be 1390 // careful, because some VM calls (such as call site linkage) can 1391 // use several kilobytes of stack. But the stack safety zone should 1392 // account for that. See bugs 4446381, 4468289, 4497237. 1393 1394 int bangsize = C->bang_size_in_bytes(); 1395 assert(bangsize >= framesize || bangsize <= 0, "stack bang size incorrect"); 1396 if (C->need_stack_bang(bangsize) && UseStackBanging) { 1397 // Unfortunately we cannot use the function provided in 1398 // assembler.cpp as we have to emulate the pipes. So I had to 1399 // insert the code of generate_stack_overflow_check(), see 1400 // assembler.cpp for some illuminative comments. 1401 const int page_size = os::vm_page_size(); 1402 int bang_end = StackShadowPages * page_size; 1403 1404 // This is how far the previous frame's stack banging extended. 1405 const int bang_end_safe = bang_end; 1406 1407 if (bangsize > page_size) { 1408 bang_end += bangsize; 1409 } 1410 1411 int bang_offset = bang_end_safe; 1412 1413 while (bang_offset <= bang_end) { 1414 // Need at least one stack bang at end of shadow zone. 1415 1416 // Again I had to copy code, this time from assembler_ppc.cpp, 1417 // bang_stack_with_offset - see there for comments. 1418 1419 // Stack grows down, caller passes positive offset. 1420 assert(bang_offset > 0, "must bang with positive offset"); 1421 1422 long stdoffset = -bang_offset; 1423 1424 if (Assembler::is_simm(stdoffset, 16)) { 1425 // Signed 16 bit offset, a simple std is ok. 1426 if (UseLoadInstructionsForStackBangingPPC64) { 1427 ___(ld) ld(R0, (int)(signed short)stdoffset, R1_SP); 1428 } else { 1429 ___(std) std(R0, (int)(signed short)stdoffset, R1_SP); 1430 } 1431 } else if (Assembler::is_simm(stdoffset, 31)) { 1432 // Use largeoffset calculations for addis & ld/std. 1433 const int hi = MacroAssembler::largeoffset_si16_si16_hi(stdoffset); 1434 const int lo = MacroAssembler::largeoffset_si16_si16_lo(stdoffset); 1435 1436 Register tmp = R11; 1437 ___(addis) addis(tmp, R1_SP, hi); 1438 if (UseLoadInstructionsForStackBangingPPC64) { 1439 ___(ld) ld(R0, lo, tmp); 1440 } else { 1441 ___(std) std(R0, lo, tmp); 1442 } 1443 } else { 1444 ShouldNotReachHere(); 1445 } 1446 1447 bang_offset += page_size; 1448 } 1449 // R11 trashed 1450 } // C->need_stack_bang(framesize) && UseStackBanging 1451 1452 unsigned int bytes = (unsigned int)framesize; 1453 long offset = Assembler::align_addr(bytes, frame::alignment_in_bytes); 1454 ciMethod *currMethod = C->method(); 1455 1456 // Optimized version for most common case. 1457 if (UsePower6SchedulerPPC64 && 1458 !method_is_frameless && Assembler::is_simm((int)(-offset), 16) && 1459 !(false /* ConstantsALot TODO: PPC port*/)) { 1460 ___(or) mr(callers_sp, R1_SP); 1461 ___(std) std(return_pc, _abi(lr), R1_SP); 1462 ___(stdu) stdu(R1_SP, -offset, R1_SP); 1463 return; 1464 } 1465 1466 if (!method_is_frameless) { 1467 // Get callers sp. 1468 ___(or) mr(callers_sp, R1_SP); 1469 1470 // Push method's frame, modifies SP. 1471 assert(Assembler::is_uimm(framesize, 32U), "wrong type"); 1472 // The ABI is already accounted for in 'framesize' via the 1473 // 'out_preserve' area. 1474 Register tmp = push_frame_temp; 1475 // Had to insert code of push_frame((unsigned int)framesize, push_frame_temp). 1476 if (Assembler::is_simm(-offset, 16)) { 1477 ___(stdu) stdu(R1_SP, -offset, R1_SP); 1478 } else { 1479 long x = -offset; 1480 // Had to insert load_const(tmp, -offset). 1481 ___(addis) lis( tmp, (int)((signed short)(((x >> 32) & 0xffff0000) >> 16))); 1482 ___(ori) ori( tmp, tmp, ((x >> 32) & 0x0000ffff)); 1483 ___(rldicr) sldi(tmp, tmp, 32); 1484 ___(oris) oris(tmp, tmp, (x & 0xffff0000) >> 16); 1485 ___(ori) ori( tmp, tmp, (x & 0x0000ffff)); 1486 1487 ___(stdux) stdux(R1_SP, R1_SP, tmp); 1488 } 1489 } 1490 #if 0 // TODO: PPC port 1491 // For testing large constant pools, emit a lot of constants to constant pool. 1492 // "Randomize" const_size. 1493 if (ConstantsALot) { 1494 const int num_consts = const_size(); 1495 for (int i = 0; i < num_consts; i++) { 1496 __ long_constant(0xB0B5B00BBABE); 1497 } 1498 } 1499 #endif 1500 if (!method_is_frameless) { 1501 // Save return pc. 1502 ___(std) std(return_pc, _abi(lr), callers_sp); 1503 } 1504 } 1505 #undef ___ 1506 #undef ___stop 1507 #undef ___advance 1508 1509 uint MachPrologNode::size(PhaseRegAlloc *ra_) const { 1510 // Variable size. determine dynamically. 1511 return MachNode::size(ra_); 1512 } 1513 1514 int MachPrologNode::reloc() const { 1515 // Return number of relocatable values contained in this instruction. 1516 return 1; // 1 reloc entry for load_const(toc). 1517 } 1518 1519 //============================================================================= 1520 1521 #ifndef PRODUCT 1522 void MachEpilogNode::format(PhaseRegAlloc *ra_, outputStream *st) const { 1523 Compile* C = ra_->C; 1524 1525 st->print("EPILOG\n\t"); 1526 st->print("restore return pc\n\t"); 1527 st->print("pop frame\n\t"); 1528 1529 if (do_polling() && C->is_method_compilation()) { 1530 st->print("touch polling page\n\t"); 1531 } 1532 } 1533 #endif 1534 1535 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 1536 Compile* C = ra_->C; 1537 MacroAssembler _masm(&cbuf); 1538 1539 const long framesize = ((long)C->frame_slots()) << LogBytesPerInt; 1540 assert(framesize >= 0, "negative frame-size?"); 1541 1542 const bool method_needs_polling = do_polling() && C->is_method_compilation(); 1543 const bool method_is_frameless = false /* TODO: PPC port C->is_frameless_method()*/; 1544 const Register return_pc = R11; 1545 const Register polling_page = R12; 1546 1547 if (!method_is_frameless) { 1548 // Restore return pc relative to callers' sp. 1549 __ ld(return_pc, ((int)framesize) + _abi(lr), R1_SP); 1550 } 1551 1552 if (method_needs_polling) { 1553 if (LoadPollAddressFromThread) { 1554 // TODO: PPC port __ ld(polling_page, in_bytes(JavaThread::poll_address_offset()), R16_thread); 1555 Unimplemented(); 1556 } else { 1557 __ load_const_optimized(polling_page, (long)(address) os::get_polling_page()); // TODO: PPC port: get_standard_polling_page() 1558 } 1559 } 1560 1561 if (!method_is_frameless) { 1562 // Move return pc to LR. 1563 __ mtlr(return_pc); 1564 // Pop frame (fixed frame-size). 1565 __ addi(R1_SP, R1_SP, (int)framesize); 1566 } 1567 1568 if (method_needs_polling) { 1569 // We need to mark the code position where the load from the safepoint 1570 // polling page was emitted as relocInfo::poll_return_type here. 1571 __ relocate(relocInfo::poll_return_type); 1572 __ load_from_polling_page(polling_page); 1573 } 1574 } 1575 1576 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const { 1577 // Variable size. Determine dynamically. 1578 return MachNode::size(ra_); 1579 } 1580 1581 int MachEpilogNode::reloc() const { 1582 // Return number of relocatable values contained in this instruction. 1583 return 1; // 1 for load_from_polling_page. 1584 } 1585 1586 const Pipeline * MachEpilogNode::pipeline() const { 1587 return MachNode::pipeline_class(); 1588 } 1589 1590 // This method seems to be obsolete. It is declared in machnode.hpp 1591 // and defined in all *.ad files, but it is never called. Should we 1592 // get rid of it? 1593 int MachEpilogNode::safepoint_offset() const { 1594 assert(do_polling(), "no return for this epilog node"); 1595 return 0; 1596 } 1597 1598 #if 0 // TODO: PPC port 1599 void MachLoadPollAddrLateNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const { 1600 MacroAssembler _masm(&cbuf); 1601 if (LoadPollAddressFromThread) { 1602 _masm.ld(R11, in_bytes(JavaThread::poll_address_offset()), R16_thread); 1603 } else { 1604 _masm.nop(); 1605 } 1606 } 1607 1608 uint MachLoadPollAddrLateNode::size(PhaseRegAlloc* ra_) const { 1609 if (LoadPollAddressFromThread) { 1610 return 4; 1611 } else { 1612 return 4; 1613 } 1614 } 1615 1616 #ifndef PRODUCT 1617 void MachLoadPollAddrLateNode::format(PhaseRegAlloc* ra_, outputStream* st) const { 1618 st->print_cr(" LD R11, PollAddressOffset, R16_thread \t// LoadPollAddressFromThread"); 1619 } 1620 #endif 1621 1622 const RegMask &MachLoadPollAddrLateNode::out_RegMask() const { 1623 return RSCRATCH1_BITS64_REG_mask(); 1624 } 1625 #endif // PPC port 1626 1627 // ============================================================================= 1628 1629 // Figure out which register class each belongs in: rc_int, rc_float or 1630 // rc_stack. 1631 enum RC { rc_bad, rc_int, rc_float, rc_stack }; 1632 1633 static enum RC rc_class(OptoReg::Name reg) { 1634 // Return the register class for the given register. The given register 1635 // reg is a <register>_num value, which is an index into the MachRegisterNumbers 1636 // enumeration in adGlobals_ppc64.hpp. 1637 1638 if (reg == OptoReg::Bad) return rc_bad; 1639 1640 // We have 64 integer register halves, starting at index 0. 1641 if (reg < 64) return rc_int; 1642 1643 // We have 64 floating-point register halves, starting at index 64. 1644 if (reg < 64+64) return rc_float; 1645 1646 // Between float regs & stack are the flags regs. 1647 assert(OptoReg::is_stack(reg), "blow up if spilling flags"); 1648 1649 return rc_stack; 1650 } 1651 1652 static int ld_st_helper(CodeBuffer *cbuf, const char *op_str, uint opcode, int reg, int offset, 1653 bool do_print, Compile* C, outputStream *st) { 1654 1655 assert(opcode == Assembler::LD_OPCODE || 1656 opcode == Assembler::STD_OPCODE || 1657 opcode == Assembler::LWZ_OPCODE || 1658 opcode == Assembler::STW_OPCODE || 1659 opcode == Assembler::LFD_OPCODE || 1660 opcode == Assembler::STFD_OPCODE || 1661 opcode == Assembler::LFS_OPCODE || 1662 opcode == Assembler::STFS_OPCODE, 1663 "opcode not supported"); 1664 1665 if (cbuf) { 1666 int d = 1667 (Assembler::LD_OPCODE == opcode || Assembler::STD_OPCODE == opcode) ? 1668 Assembler::ds(offset+0 /* TODO: PPC port C->frame_slots_sp_bias_in_bytes()*/) 1669 : Assembler::d1(offset+0 /* TODO: PPC port C->frame_slots_sp_bias_in_bytes()*/); // Makes no difference in opt build. 1670 emit_long(*cbuf, opcode | Assembler::rt(Matcher::_regEncode[reg]) | d | Assembler::ra(R1_SP)); 1671 } 1672 #ifndef PRODUCT 1673 else if (do_print) { 1674 st->print("%-7s %s, [R1_SP + #%d+%d] \t// spill copy", 1675 op_str, 1676 Matcher::regName[reg], 1677 offset, 0 /* TODO: PPC port C->frame_slots_sp_bias_in_bytes()*/); 1678 } 1679 #endif 1680 return 4; // size 1681 } 1682 1683 uint MachSpillCopyNode::implementation(CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, outputStream *st) const { 1684 Compile* C = ra_->C; 1685 1686 // Get registers to move. 1687 OptoReg::Name src_hi = ra_->get_reg_second(in(1)); 1688 OptoReg::Name src_lo = ra_->get_reg_first(in(1)); 1689 OptoReg::Name dst_hi = ra_->get_reg_second(this); 1690 OptoReg::Name dst_lo = ra_->get_reg_first(this); 1691 1692 enum RC src_hi_rc = rc_class(src_hi); 1693 enum RC src_lo_rc = rc_class(src_lo); 1694 enum RC dst_hi_rc = rc_class(dst_hi); 1695 enum RC dst_lo_rc = rc_class(dst_lo); 1696 1697 assert(src_lo != OptoReg::Bad && dst_lo != OptoReg::Bad, "must move at least 1 register"); 1698 if (src_hi != OptoReg::Bad) 1699 assert((src_lo&1)==0 && src_lo+1==src_hi && 1700 (dst_lo&1)==0 && dst_lo+1==dst_hi, 1701 "expected aligned-adjacent pairs"); 1702 // Generate spill code! 1703 int size = 0; 1704 1705 if (src_lo == dst_lo && src_hi == dst_hi) 1706 return size; // Self copy, no move. 1707 1708 // -------------------------------------- 1709 // Memory->Memory Spill. Use R0 to hold the value. 1710 if (src_lo_rc == rc_stack && dst_lo_rc == rc_stack) { 1711 int src_offset = ra_->reg2offset(src_lo); 1712 int dst_offset = ra_->reg2offset(dst_lo); 1713 if (src_hi != OptoReg::Bad) { 1714 assert(src_hi_rc==rc_stack && dst_hi_rc==rc_stack, 1715 "expected same type of move for high parts"); 1716 size += ld_st_helper(cbuf, "LD ", Assembler::LD_OPCODE, R0_num, src_offset, !do_size, C, st); 1717 if (!cbuf && !do_size) st->print("\n\t"); 1718 size += ld_st_helper(cbuf, "STD ", Assembler::STD_OPCODE, R0_num, dst_offset, !do_size, C, st); 1719 } else { 1720 size += ld_st_helper(cbuf, "LWZ ", Assembler::LWZ_OPCODE, R0_num, src_offset, !do_size, C, st); 1721 if (!cbuf && !do_size) st->print("\n\t"); 1722 size += ld_st_helper(cbuf, "STW ", Assembler::STW_OPCODE, R0_num, dst_offset, !do_size, C, st); 1723 } 1724 return size; 1725 } 1726 1727 // -------------------------------------- 1728 // Check for float->int copy; requires a trip through memory. 1729 if (src_lo_rc == rc_float && dst_lo_rc == rc_int) { 1730 Unimplemented(); 1731 } 1732 1733 // -------------------------------------- 1734 // Check for integer reg-reg copy. 1735 if (src_lo_rc == rc_int && dst_lo_rc == rc_int) { 1736 Register Rsrc = as_Register(Matcher::_regEncode[src_lo]); 1737 Register Rdst = as_Register(Matcher::_regEncode[dst_lo]); 1738 size = (Rsrc != Rdst) ? 4 : 0; 1739 1740 if (cbuf) { 1741 MacroAssembler _masm(cbuf); 1742 if (size) { 1743 __ mr(Rdst, Rsrc); 1744 } 1745 } 1746 #ifndef PRODUCT 1747 else if (!do_size) { 1748 if (size) { 1749 st->print("%-7s %s, %s \t// spill copy", "MR", Matcher::regName[dst_lo], Matcher::regName[src_lo]); 1750 } else { 1751 st->print("%-7s %s, %s \t// spill copy", "MR-NOP", Matcher::regName[dst_lo], Matcher::regName[src_lo]); 1752 } 1753 } 1754 #endif 1755 return size; 1756 } 1757 1758 // Check for integer store. 1759 if (src_lo_rc == rc_int && dst_lo_rc == rc_stack) { 1760 int dst_offset = ra_->reg2offset(dst_lo); 1761 if (src_hi != OptoReg::Bad) { 1762 assert(src_hi_rc==rc_int && dst_hi_rc==rc_stack, 1763 "expected same type of move for high parts"); 1764 size += ld_st_helper(cbuf, "STD ", Assembler::STD_OPCODE, src_lo, dst_offset, !do_size, C, st); 1765 } else { 1766 size += ld_st_helper(cbuf, "STW ", Assembler::STW_OPCODE, src_lo, dst_offset, !do_size, C, st); 1767 } 1768 return size; 1769 } 1770 1771 // Check for integer load. 1772 if (dst_lo_rc == rc_int && src_lo_rc == rc_stack) { 1773 int src_offset = ra_->reg2offset(src_lo); 1774 if (src_hi != OptoReg::Bad) { 1775 assert(dst_hi_rc==rc_int && src_hi_rc==rc_stack, 1776 "expected same type of move for high parts"); 1777 size += ld_st_helper(cbuf, "LD ", Assembler::LD_OPCODE, dst_lo, src_offset, !do_size, C, st); 1778 } else { 1779 size += ld_st_helper(cbuf, "LWZ ", Assembler::LWZ_OPCODE, dst_lo, src_offset, !do_size, C, st); 1780 } 1781 return size; 1782 } 1783 1784 // Check for float reg-reg copy. 1785 if (src_lo_rc == rc_float && dst_lo_rc == rc_float) { 1786 if (cbuf) { 1787 MacroAssembler _masm(cbuf); 1788 FloatRegister Rsrc = as_FloatRegister(Matcher::_regEncode[src_lo]); 1789 FloatRegister Rdst = as_FloatRegister(Matcher::_regEncode[dst_lo]); 1790 __ fmr(Rdst, Rsrc); 1791 } 1792 #ifndef PRODUCT 1793 else if (!do_size) { 1794 st->print("%-7s %s, %s \t// spill copy", "FMR", Matcher::regName[dst_lo], Matcher::regName[src_lo]); 1795 } 1796 #endif 1797 return 4; 1798 } 1799 1800 // Check for float store. 1801 if (src_lo_rc == rc_float && dst_lo_rc == rc_stack) { 1802 int dst_offset = ra_->reg2offset(dst_lo); 1803 if (src_hi != OptoReg::Bad) { 1804 assert(src_hi_rc==rc_float && dst_hi_rc==rc_stack, 1805 "expected same type of move for high parts"); 1806 size += ld_st_helper(cbuf, "STFD", Assembler::STFD_OPCODE, src_lo, dst_offset, !do_size, C, st); 1807 } else { 1808 size += ld_st_helper(cbuf, "STFS", Assembler::STFS_OPCODE, src_lo, dst_offset, !do_size, C, st); 1809 } 1810 return size; 1811 } 1812 1813 // Check for float load. 1814 if (dst_lo_rc == rc_float && src_lo_rc == rc_stack) { 1815 int src_offset = ra_->reg2offset(src_lo); 1816 if (src_hi != OptoReg::Bad) { 1817 assert(dst_hi_rc==rc_float && src_hi_rc==rc_stack, 1818 "expected same type of move for high parts"); 1819 size += ld_st_helper(cbuf, "LFD ", Assembler::LFD_OPCODE, dst_lo, src_offset, !do_size, C, st); 1820 } else { 1821 size += ld_st_helper(cbuf, "LFS ", Assembler::LFS_OPCODE, dst_lo, src_offset, !do_size, C, st); 1822 } 1823 return size; 1824 } 1825 1826 // -------------------------------------------------------------------- 1827 // Check for hi bits still needing moving. Only happens for misaligned 1828 // arguments to native calls. 1829 if (src_hi == dst_hi) 1830 return size; // Self copy; no move. 1831 1832 assert(src_hi_rc != rc_bad && dst_hi_rc != rc_bad, "src_hi & dst_hi cannot be Bad"); 1833 ShouldNotReachHere(); // Unimplemented 1834 return 0; 1835 } 1836 1837 #ifndef PRODUCT 1838 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream *st) const { 1839 if (!ra_) 1840 st->print("N%d = SpillCopy(N%d)", _idx, in(1)->_idx); 1841 else 1842 implementation(NULL, ra_, false, st); 1843 } 1844 #endif 1845 1846 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 1847 implementation(&cbuf, ra_, false, NULL); 1848 } 1849 1850 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const { 1851 return implementation(NULL, ra_, true, NULL); 1852 } 1853 1854 #if 0 // TODO: PPC port 1855 ArchOpcode MachSpillCopyNode_archOpcode(MachSpillCopyNode *n, PhaseRegAlloc *ra_) { 1856 #ifndef PRODUCT 1857 if (ra_->node_regs_max_index() == 0) return archOpcode_undefined; 1858 #endif 1859 assert(ra_->node_regs_max_index() != 0, ""); 1860 1861 // Get registers to move. 1862 OptoReg::Name src_hi = ra_->get_reg_second(n->in(1)); 1863 OptoReg::Name src_lo = ra_->get_reg_first(n->in(1)); 1864 OptoReg::Name dst_hi = ra_->get_reg_second(n); 1865 OptoReg::Name dst_lo = ra_->get_reg_first(n); 1866 1867 enum RC src_lo_rc = rc_class(src_lo); 1868 enum RC dst_lo_rc = rc_class(dst_lo); 1869 1870 if (src_lo == dst_lo && src_hi == dst_hi) 1871 return ppc64Opcode_none; // Self copy, no move. 1872 1873 // -------------------------------------- 1874 // Memory->Memory Spill. Use R0 to hold the value. 1875 if (src_lo_rc == rc_stack && dst_lo_rc == rc_stack) { 1876 return ppc64Opcode_compound; 1877 } 1878 1879 // -------------------------------------- 1880 // Check for float->int copy; requires a trip through memory. 1881 if (src_lo_rc == rc_float && dst_lo_rc == rc_int) { 1882 Unimplemented(); 1883 } 1884 1885 // -------------------------------------- 1886 // Check for integer reg-reg copy. 1887 if (src_lo_rc == rc_int && dst_lo_rc == rc_int) { 1888 Register Rsrc = as_Register(Matcher::_regEncode[src_lo]); 1889 Register Rdst = as_Register(Matcher::_regEncode[dst_lo]); 1890 if (Rsrc == Rdst) { 1891 return ppc64Opcode_none; 1892 } else { 1893 return ppc64Opcode_or; 1894 } 1895 } 1896 1897 // Check for integer store. 1898 if (src_lo_rc == rc_int && dst_lo_rc == rc_stack) { 1899 if (src_hi != OptoReg::Bad) { 1900 return ppc64Opcode_std; 1901 } else { 1902 return ppc64Opcode_stw; 1903 } 1904 } 1905 1906 // Check for integer load. 1907 if (dst_lo_rc == rc_int && src_lo_rc == rc_stack) { 1908 if (src_hi != OptoReg::Bad) { 1909 return ppc64Opcode_ld; 1910 } else { 1911 return ppc64Opcode_lwz; 1912 } 1913 } 1914 1915 // Check for float reg-reg copy. 1916 if (src_lo_rc == rc_float && dst_lo_rc == rc_float) { 1917 return ppc64Opcode_fmr; 1918 } 1919 1920 // Check for float store. 1921 if (src_lo_rc == rc_float && dst_lo_rc == rc_stack) { 1922 if (src_hi != OptoReg::Bad) { 1923 return ppc64Opcode_stfd; 1924 } else { 1925 return ppc64Opcode_stfs; 1926 } 1927 } 1928 1929 // Check for float load. 1930 if (dst_lo_rc == rc_float && src_lo_rc == rc_stack) { 1931 if (src_hi != OptoReg::Bad) { 1932 return ppc64Opcode_lfd; 1933 } else { 1934 return ppc64Opcode_lfs; 1935 } 1936 } 1937 1938 // -------------------------------------------------------------------- 1939 // Check for hi bits still needing moving. Only happens for misaligned 1940 // arguments to native calls. 1941 if (src_hi == dst_hi) 1942 return ppc64Opcode_none; // Self copy; no move. 1943 1944 ShouldNotReachHere(); 1945 return ppc64Opcode_undefined; 1946 } 1947 #endif // PPC port 1948 1949 #ifndef PRODUCT 1950 void MachNopNode::format(PhaseRegAlloc *ra_, outputStream *st) const { 1951 st->print("NOP \t// %d nops to pad for loops.", _count); 1952 } 1953 #endif 1954 1955 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *) const { 1956 MacroAssembler _masm(&cbuf); 1957 // _count contains the number of nops needed for padding. 1958 for (int i = 0; i < _count; i++) { 1959 __ nop(); 1960 } 1961 } 1962 1963 uint MachNopNode::size(PhaseRegAlloc *ra_) const { 1964 return _count * 4; 1965 } 1966 1967 #ifndef PRODUCT 1968 void BoxLockNode::format(PhaseRegAlloc *ra_, outputStream *st) const { 1969 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()); 1970 int reg = ra_->get_reg_first(this); 1971 st->print("ADDI %s, SP, %d \t// box node", Matcher::regName[reg], offset); 1972 } 1973 #endif 1974 1975 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 1976 MacroAssembler _masm(&cbuf); 1977 1978 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()); 1979 int reg = ra_->get_encode(this); 1980 1981 if (Assembler::is_simm(offset, 16)) { 1982 __ addi(as_Register(reg), R1, offset); 1983 } else { 1984 ShouldNotReachHere(); 1985 } 1986 } 1987 1988 uint BoxLockNode::size(PhaseRegAlloc *ra_) const { 1989 // BoxLockNode is not a MachNode, so we can't just call MachNode::size(ra_). 1990 return 4; 1991 } 1992 1993 #ifndef PRODUCT 1994 void MachUEPNode::format(PhaseRegAlloc *ra_, outputStream *st) const { 1995 st->print_cr("---- MachUEPNode ----"); 1996 st->print_cr("..."); 1997 } 1998 #endif 1999 2000 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 2001 // This is the unverified entry point. 2002 MacroAssembler _masm(&cbuf); 2003 2004 // Inline_cache contains a klass. 2005 Register ic_klass = as_Register(Matcher::inline_cache_reg_encode()); 2006 Register receiver_klass = R12_scratch2; // tmp 2007 2008 assert_different_registers(ic_klass, receiver_klass, R11_scratch1, R3_ARG1); 2009 assert(R11_scratch1 == R11, "need prologue scratch register"); 2010 2011 // Check for NULL argument if we don't have implicit null checks. 2012 if (!ImplicitNullChecks || !os::zero_page_read_protected()) { 2013 if (TrapBasedNullChecks) { 2014 __ trap_null_check(R3_ARG1); 2015 } else { 2016 Label valid; 2017 __ cmpdi(CCR0, R3_ARG1, 0); 2018 __ bne_predict_taken(CCR0, valid); 2019 // We have a null argument, branch to ic_miss_stub. 2020 __ b64_patchable((address)SharedRuntime::get_ic_miss_stub(), 2021 relocInfo::runtime_call_type); 2022 __ bind(valid); 2023 } 2024 } 2025 // Assume argument is not NULL, load klass from receiver. 2026 __ load_klass(receiver_klass, R3_ARG1); 2027 2028 if (TrapBasedICMissChecks) { 2029 __ trap_ic_miss_check(receiver_klass, ic_klass); 2030 } else { 2031 Label valid; 2032 __ cmpd(CCR0, receiver_klass, ic_klass); 2033 __ beq_predict_taken(CCR0, valid); 2034 // We have an unexpected klass, branch to ic_miss_stub. 2035 __ b64_patchable((address)SharedRuntime::get_ic_miss_stub(), 2036 relocInfo::runtime_call_type); 2037 __ bind(valid); 2038 } 2039 2040 // Argument is valid and klass is as expected, continue. 2041 } 2042 2043 #if 0 // TODO: PPC port 2044 // Optimize UEP code on z (save a load_const() call in main path). 2045 int MachUEPNode::ep_offset() { 2046 return 0; 2047 } 2048 #endif 2049 2050 uint MachUEPNode::size(PhaseRegAlloc *ra_) const { 2051 // Variable size. Determine dynamically. 2052 return MachNode::size(ra_); 2053 } 2054 2055 //============================================================================= 2056 2057 %} // interrupt source 2058 2059 source_hpp %{ // Header information of the source block. 2060 2061 class HandlerImpl { 2062 2063 public: 2064 2065 static int emit_exception_handler(CodeBuffer &cbuf); 2066 static int emit_deopt_handler(CodeBuffer& cbuf); 2067 2068 static uint size_exception_handler() { 2069 // The exception_handler is a b64_patchable. 2070 return MacroAssembler::b64_patchable_size; 2071 } 2072 2073 static uint size_deopt_handler() { 2074 // The deopt_handler is a bl64_patchable. 2075 return MacroAssembler::bl64_patchable_size; 2076 } 2077 2078 }; 2079 2080 %} // end source_hpp 2081 2082 source %{ 2083 2084 int HandlerImpl::emit_exception_handler(CodeBuffer &cbuf) { 2085 MacroAssembler _masm(&cbuf); 2086 2087 address base = __ start_a_stub(size_exception_handler()); 2088 if (base == NULL) return 0; // CodeBuffer::expand failed 2089 2090 int offset = __ offset(); 2091 __ b64_patchable((address)OptoRuntime::exception_blob()->content_begin(), 2092 relocInfo::runtime_call_type); 2093 assert(__ offset() - offset == (int)size_exception_handler(), "must be fixed size"); 2094 __ end_a_stub(); 2095 2096 return offset; 2097 } 2098 2099 // The deopt_handler is like the exception handler, but it calls to 2100 // the deoptimization blob instead of jumping to the exception blob. 2101 int HandlerImpl::emit_deopt_handler(CodeBuffer& cbuf) { 2102 MacroAssembler _masm(&cbuf); 2103 2104 address base = __ start_a_stub(size_deopt_handler()); 2105 if (base == NULL) return 0; // CodeBuffer::expand failed 2106 2107 int offset = __ offset(); 2108 __ bl64_patchable((address)SharedRuntime::deopt_blob()->unpack(), 2109 relocInfo::runtime_call_type); 2110 assert(__ offset() - offset == (int) size_deopt_handler(), "must be fixed size"); 2111 __ end_a_stub(); 2112 2113 return offset; 2114 } 2115 2116 //============================================================================= 2117 2118 // Use a frame slots bias for frameless methods if accessing the stack. 2119 static int frame_slots_bias(int reg_enc, PhaseRegAlloc* ra_) { 2120 if (as_Register(reg_enc) == R1_SP) { 2121 return 0; // TODO: PPC port ra_->C->frame_slots_sp_bias_in_bytes(); 2122 } 2123 return 0; 2124 } 2125 2126 const bool Matcher::match_rule_supported(int opcode) { 2127 if (!has_match_rule(opcode)) 2128 return false; 2129 2130 switch (opcode) { 2131 case Op_SqrtD: 2132 return VM_Version::has_fsqrt(); 2133 case Op_CountLeadingZerosI: 2134 case Op_CountLeadingZerosL: 2135 case Op_CountTrailingZerosI: 2136 case Op_CountTrailingZerosL: 2137 if (!UseCountLeadingZerosInstructionsPPC64) 2138 return false; 2139 break; 2140 2141 case Op_PopCountI: 2142 case Op_PopCountL: 2143 return (UsePopCountInstruction && VM_Version::has_popcntw()); 2144 2145 case Op_StrComp: 2146 return SpecialStringCompareTo; 2147 case Op_StrEquals: 2148 return SpecialStringEquals; 2149 case Op_StrIndexOf: 2150 return SpecialStringIndexOf; 2151 } 2152 2153 return true; // Per default match rules are supported. 2154 } 2155 2156 int Matcher::regnum_to_fpu_offset(int regnum) { 2157 // No user for this method? 2158 Unimplemented(); 2159 return 999; 2160 } 2161 2162 const bool Matcher::convL2FSupported(void) { 2163 // fcfids can do the conversion (>= Power7). 2164 // fcfid + frsp showed rounding problem when result should be 0x3f800001. 2165 return VM_Version::has_fcfids(); // False means that conversion is done by runtime call. 2166 } 2167 2168 // Vector width in bytes. 2169 const int Matcher::vector_width_in_bytes(BasicType bt) { 2170 assert(MaxVectorSize == 8, ""); 2171 return 8; 2172 } 2173 2174 // Vector ideal reg. 2175 const int Matcher::vector_ideal_reg(int size) { 2176 assert(MaxVectorSize == 8 && size == 8, ""); 2177 return Op_RegL; 2178 } 2179 2180 const int Matcher::vector_shift_count_ideal_reg(int size) { 2181 fatal("vector shift is not supported"); 2182 return Node::NotAMachineReg; 2183 } 2184 2185 // Limits on vector size (number of elements) loaded into vector. 2186 const int Matcher::max_vector_size(const BasicType bt) { 2187 assert(is_java_primitive(bt), "only primitive type vectors"); 2188 return vector_width_in_bytes(bt)/type2aelembytes(bt); 2189 } 2190 2191 const int Matcher::min_vector_size(const BasicType bt) { 2192 return max_vector_size(bt); // Same as max. 2193 } 2194 2195 // PPC doesn't support misaligned vectors store/load. 2196 const bool Matcher::misaligned_vectors_ok() { 2197 return false; 2198 } 2199 2200 // PPC AES support not yet implemented 2201 const bool Matcher::pass_original_key_for_aes() { 2202 return false; 2203 } 2204 2205 // RETURNS: whether this branch offset is short enough that a short 2206 // branch can be used. 2207 // 2208 // If the platform does not provide any short branch variants, then 2209 // this method should return `false' for offset 0. 2210 // 2211 // `Compile::Fill_buffer' will decide on basis of this information 2212 // whether to do the pass `Compile::Shorten_branches' at all. 2213 // 2214 // And `Compile::Shorten_branches' will decide on basis of this 2215 // information whether to replace particular branch sites by short 2216 // ones. 2217 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) { 2218 // Is the offset within the range of a ppc64 pc relative branch? 2219 bool b; 2220 2221 const int safety_zone = 3 * BytesPerInstWord; 2222 b = Assembler::is_simm((offset<0 ? offset-safety_zone : offset+safety_zone), 2223 29 - 16 + 1 + 2); 2224 return b; 2225 } 2226 2227 const bool Matcher::isSimpleConstant64(jlong value) { 2228 // Probably always true, even if a temp register is required. 2229 return true; 2230 } 2231 /* TODO: PPC port 2232 // Make a new machine dependent decode node (with its operands). 2233 MachTypeNode *Matcher::make_decode_node(Compile *C) { 2234 assert(Universe::narrow_oop_base() == NULL && Universe::narrow_oop_shift() == 0, 2235 "This method is only implemented for unscaled cOops mode so far"); 2236 MachTypeNode *decode = new (C) decodeN_unscaledNode(); 2237 decode->set_opnd_array(0, new (C) iRegPdstOper()); 2238 decode->set_opnd_array(1, new (C) iRegNsrcOper()); 2239 return decode; 2240 } 2241 */ 2242 // Threshold size for cleararray. 2243 const int Matcher::init_array_short_size = 8 * BytesPerLong; 2244 2245 // false => size gets scaled to BytesPerLong, ok. 2246 const bool Matcher::init_array_count_is_in_bytes = false; 2247 2248 // Use conditional move (CMOVL) on Power7. 2249 const int Matcher::long_cmove_cost() { return 0; } // this only makes long cmoves more expensive than int cmoves 2250 2251 // Suppress CMOVF. Conditional move available (sort of) on PPC64 only from P7 onwards. Not exploited yet. 2252 // fsel doesn't accept a condition register as input, so this would be slightly different. 2253 const int Matcher::float_cmove_cost() { return ConditionalMoveLimit; } 2254 2255 // Power6 requires postalloc expand (see block.cpp for description of postalloc expand). 2256 const bool Matcher::require_postalloc_expand = true; 2257 2258 // Should the Matcher clone shifts on addressing modes, expecting them to 2259 // be subsumed into complex addressing expressions or compute them into 2260 // registers? True for Intel but false for most RISCs. 2261 const bool Matcher::clone_shift_expressions = false; 2262 2263 // Do we need to mask the count passed to shift instructions or does 2264 // the cpu only look at the lower 5/6 bits anyway? 2265 // Off, as masks are generated in expand rules where required. 2266 // Constant shift counts are handled in Ideal phase. 2267 const bool Matcher::need_masked_shift_count = false; 2268 2269 // This affects two different things: 2270 // - how Decode nodes are matched 2271 // - how ImplicitNullCheck opportunities are recognized 2272 // If true, the matcher will try to remove all Decodes and match them 2273 // (as operands) into nodes. NullChecks are not prepared to deal with 2274 // Decodes by final_graph_reshaping(). 2275 // If false, final_graph_reshaping() forces the decode behind the Cmp 2276 // for a NullCheck. The matcher matches the Decode node into a register. 2277 // Implicit_null_check optimization moves the Decode along with the 2278 // memory operation back up before the NullCheck. 2279 bool Matcher::narrow_oop_use_complex_address() { 2280 // TODO: PPC port if (MatchDecodeNodes) return true; 2281 return false; 2282 } 2283 2284 bool Matcher::narrow_klass_use_complex_address() { 2285 NOT_LP64(ShouldNotCallThis()); 2286 assert(UseCompressedClassPointers, "only for compressed klass code"); 2287 // TODO: PPC port if (MatchDecodeNodes) return true; 2288 return false; 2289 } 2290 2291 // Is it better to copy float constants, or load them directly from memory? 2292 // Intel can load a float constant from a direct address, requiring no 2293 // extra registers. Most RISCs will have to materialize an address into a 2294 // register first, so they would do better to copy the constant from stack. 2295 const bool Matcher::rematerialize_float_constants = false; 2296 2297 // If CPU can load and store mis-aligned doubles directly then no fixup is 2298 // needed. Else we split the double into 2 integer pieces and move it 2299 // piece-by-piece. Only happens when passing doubles into C code as the 2300 // Java calling convention forces doubles to be aligned. 2301 const bool Matcher::misaligned_doubles_ok = true; 2302 2303 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) { 2304 Unimplemented(); 2305 } 2306 2307 // Advertise here if the CPU requires explicit rounding operations 2308 // to implement the UseStrictFP mode. 2309 const bool Matcher::strict_fp_requires_explicit_rounding = false; 2310 2311 // Do floats take an entire double register or just half? 2312 // 2313 // A float occupies a ppc64 double register. For the allocator, a 2314 // ppc64 double register appears as a pair of float registers. 2315 bool Matcher::float_in_double() { return true; } 2316 2317 // Do ints take an entire long register or just half? 2318 // The relevant question is how the int is callee-saved: 2319 // the whole long is written but de-opt'ing will have to extract 2320 // the relevant 32 bits. 2321 const bool Matcher::int_in_long = true; 2322 2323 // Constants for c2c and c calling conventions. 2324 2325 const MachRegisterNumbers iarg_reg[8] = { 2326 R3_num, R4_num, R5_num, R6_num, 2327 R7_num, R8_num, R9_num, R10_num 2328 }; 2329 2330 const MachRegisterNumbers farg_reg[13] = { 2331 F1_num, F2_num, F3_num, F4_num, 2332 F5_num, F6_num, F7_num, F8_num, 2333 F9_num, F10_num, F11_num, F12_num, 2334 F13_num 2335 }; 2336 2337 const int num_iarg_registers = sizeof(iarg_reg) / sizeof(iarg_reg[0]); 2338 2339 const int num_farg_registers = sizeof(farg_reg) / sizeof(farg_reg[0]); 2340 2341 // Return whether or not this register is ever used as an argument. This 2342 // function is used on startup to build the trampoline stubs in generateOptoStub. 2343 // Registers not mentioned will be killed by the VM call in the trampoline, and 2344 // arguments in those registers not be available to the callee. 2345 bool Matcher::can_be_java_arg(int reg) { 2346 // We return true for all registers contained in iarg_reg[] and 2347 // farg_reg[] and their virtual halves. 2348 // We must include the virtual halves in order to get STDs and LDs 2349 // instead of STWs and LWs in the trampoline stubs. 2350 2351 if ( reg == R3_num || reg == R3_H_num 2352 || reg == R4_num || reg == R4_H_num 2353 || reg == R5_num || reg == R5_H_num 2354 || reg == R6_num || reg == R6_H_num 2355 || reg == R7_num || reg == R7_H_num 2356 || reg == R8_num || reg == R8_H_num 2357 || reg == R9_num || reg == R9_H_num 2358 || reg == R10_num || reg == R10_H_num) 2359 return true; 2360 2361 if ( reg == F1_num || reg == F1_H_num 2362 || reg == F2_num || reg == F2_H_num 2363 || reg == F3_num || reg == F3_H_num 2364 || reg == F4_num || reg == F4_H_num 2365 || reg == F5_num || reg == F5_H_num 2366 || reg == F6_num || reg == F6_H_num 2367 || reg == F7_num || reg == F7_H_num 2368 || reg == F8_num || reg == F8_H_num 2369 || reg == F9_num || reg == F9_H_num 2370 || reg == F10_num || reg == F10_H_num 2371 || reg == F11_num || reg == F11_H_num 2372 || reg == F12_num || reg == F12_H_num 2373 || reg == F13_num || reg == F13_H_num) 2374 return true; 2375 2376 return false; 2377 } 2378 2379 bool Matcher::is_spillable_arg(int reg) { 2380 return can_be_java_arg(reg); 2381 } 2382 2383 bool Matcher::use_asm_for_ldiv_by_con(jlong divisor) { 2384 return false; 2385 } 2386 2387 // Register for DIVI projection of divmodI. 2388 RegMask Matcher::divI_proj_mask() { 2389 ShouldNotReachHere(); 2390 return RegMask(); 2391 } 2392 2393 // Register for MODI projection of divmodI. 2394 RegMask Matcher::modI_proj_mask() { 2395 ShouldNotReachHere(); 2396 return RegMask(); 2397 } 2398 2399 // Register for DIVL projection of divmodL. 2400 RegMask Matcher::divL_proj_mask() { 2401 ShouldNotReachHere(); 2402 return RegMask(); 2403 } 2404 2405 // Register for MODL projection of divmodL. 2406 RegMask Matcher::modL_proj_mask() { 2407 ShouldNotReachHere(); 2408 return RegMask(); 2409 } 2410 2411 const RegMask Matcher::method_handle_invoke_SP_save_mask() { 2412 return RegMask(); 2413 } 2414 2415 %} 2416 2417 //----------ENCODING BLOCK----------------------------------------------------- 2418 // This block specifies the encoding classes used by the compiler to output 2419 // byte streams. Encoding classes are parameterized macros used by 2420 // Machine Instruction Nodes in order to generate the bit encoding of the 2421 // instruction. Operands specify their base encoding interface with the 2422 // interface keyword. There are currently supported four interfaces, 2423 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an 2424 // operand to generate a function which returns its register number when 2425 // queried. CONST_INTER causes an operand to generate a function which 2426 // returns the value of the constant when queried. MEMORY_INTER causes an 2427 // operand to generate four functions which return the Base Register, the 2428 // Index Register, the Scale Value, and the Offset Value of the operand when 2429 // queried. COND_INTER causes an operand to generate six functions which 2430 // return the encoding code (ie - encoding bits for the instruction) 2431 // associated with each basic boolean condition for a conditional instruction. 2432 // 2433 // Instructions specify two basic values for encoding. Again, a function 2434 // is available to check if the constant displacement is an oop. They use the 2435 // ins_encode keyword to specify their encoding classes (which must be 2436 // a sequence of enc_class names, and their parameters, specified in 2437 // the encoding block), and they use the 2438 // opcode keyword to specify, in order, their primary, secondary, and 2439 // tertiary opcode. Only the opcode sections which a particular instruction 2440 // needs for encoding need to be specified. 2441 encode %{ 2442 enc_class enc_unimplemented %{ 2443 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 2444 MacroAssembler _masm(&cbuf); 2445 __ unimplemented("Unimplemented mach node encoding in AD file.", 13); 2446 %} 2447 2448 enc_class enc_untested %{ 2449 #ifdef ASSERT 2450 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 2451 MacroAssembler _masm(&cbuf); 2452 __ untested("Untested mach node encoding in AD file."); 2453 #else 2454 // TODO: PPC port $archOpcode(ppc64Opcode_none); 2455 #endif 2456 %} 2457 2458 enc_class enc_lbz(iRegIdst dst, memory mem) %{ 2459 // TODO: PPC port $archOpcode(ppc64Opcode_lbz); 2460 MacroAssembler _masm(&cbuf); 2461 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); 2462 __ lbz($dst$$Register, Idisp, $mem$$base$$Register); 2463 %} 2464 2465 // Load acquire. 2466 enc_class enc_lbz_ac(iRegIdst dst, memory mem) %{ 2467 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 2468 MacroAssembler _masm(&cbuf); 2469 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); 2470 __ lbz($dst$$Register, Idisp, $mem$$base$$Register); 2471 __ twi_0($dst$$Register); 2472 __ isync(); 2473 %} 2474 2475 enc_class enc_lhz(iRegIdst dst, memory mem) %{ 2476 // TODO: PPC port $archOpcode(ppc64Opcode_lhz); 2477 2478 MacroAssembler _masm(&cbuf); 2479 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); 2480 __ lhz($dst$$Register, Idisp, $mem$$base$$Register); 2481 %} 2482 2483 // Load acquire. 2484 enc_class enc_lhz_ac(iRegIdst dst, memory mem) %{ 2485 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 2486 2487 MacroAssembler _masm(&cbuf); 2488 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); 2489 __ lhz($dst$$Register, Idisp, $mem$$base$$Register); 2490 __ twi_0($dst$$Register); 2491 __ isync(); 2492 %} 2493 2494 enc_class enc_lwz(iRegIdst dst, memory mem) %{ 2495 // TODO: PPC port $archOpcode(ppc64Opcode_lwz); 2496 2497 MacroAssembler _masm(&cbuf); 2498 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); 2499 __ lwz($dst$$Register, Idisp, $mem$$base$$Register); 2500 %} 2501 2502 // Load acquire. 2503 enc_class enc_lwz_ac(iRegIdst dst, memory mem) %{ 2504 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 2505 2506 MacroAssembler _masm(&cbuf); 2507 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); 2508 __ lwz($dst$$Register, Idisp, $mem$$base$$Register); 2509 __ twi_0($dst$$Register); 2510 __ isync(); 2511 %} 2512 2513 enc_class enc_ld(iRegLdst dst, memoryAlg4 mem) %{ 2514 // TODO: PPC port $archOpcode(ppc64Opcode_ld); 2515 MacroAssembler _masm(&cbuf); 2516 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); 2517 // Operand 'ds' requires 4-alignment. 2518 assert((Idisp & 0x3) == 0, "unaligned offset"); 2519 __ ld($dst$$Register, Idisp, $mem$$base$$Register); 2520 %} 2521 2522 // Load acquire. 2523 enc_class enc_ld_ac(iRegLdst dst, memoryAlg4 mem) %{ 2524 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 2525 MacroAssembler _masm(&cbuf); 2526 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); 2527 // Operand 'ds' requires 4-alignment. 2528 assert((Idisp & 0x3) == 0, "unaligned offset"); 2529 __ ld($dst$$Register, Idisp, $mem$$base$$Register); 2530 __ twi_0($dst$$Register); 2531 __ isync(); 2532 %} 2533 2534 enc_class enc_lfd(RegF dst, memory mem) %{ 2535 // TODO: PPC port $archOpcode(ppc64Opcode_lfd); 2536 MacroAssembler _masm(&cbuf); 2537 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); 2538 __ lfd($dst$$FloatRegister, Idisp, $mem$$base$$Register); 2539 %} 2540 2541 enc_class enc_load_long_constL(iRegLdst dst, immL src, iRegLdst toc) %{ 2542 // TODO: PPC port $archOpcode(ppc64Opcode_ld); 2543 2544 MacroAssembler _masm(&cbuf); 2545 int toc_offset = 0; 2546 2547 if (!ra_->C->in_scratch_emit_size()) { 2548 address const_toc_addr; 2549 // Create a non-oop constant, no relocation needed. 2550 // If it is an IC, it has a virtual_call_Relocation. 2551 const_toc_addr = __ long_constant((jlong)$src$$constant); 2552 2553 // Get the constant's TOC offset. 2554 toc_offset = __ offset_to_method_toc(const_toc_addr); 2555 2556 // Keep the current instruction offset in mind. 2557 ((loadConLNode*)this)->_cbuf_insts_offset = __ offset(); 2558 } 2559 2560 __ ld($dst$$Register, toc_offset, $toc$$Register); 2561 %} 2562 2563 enc_class enc_load_long_constL_hi(iRegLdst dst, iRegLdst toc, immL src) %{ 2564 // TODO: PPC port $archOpcode(ppc64Opcode_addis); 2565 2566 MacroAssembler _masm(&cbuf); 2567 2568 if (!ra_->C->in_scratch_emit_size()) { 2569 address const_toc_addr; 2570 // Create a non-oop constant, no relocation needed. 2571 // If it is an IC, it has a virtual_call_Relocation. 2572 const_toc_addr = __ long_constant((jlong)$src$$constant); 2573 2574 // Get the constant's TOC offset. 2575 const int toc_offset = __ offset_to_method_toc(const_toc_addr); 2576 // Store the toc offset of the constant. 2577 ((loadConL_hiNode*)this)->_const_toc_offset = toc_offset; 2578 2579 // Also keep the current instruction offset in mind. 2580 ((loadConL_hiNode*)this)->_cbuf_insts_offset = __ offset(); 2581 } 2582 2583 __ addis($dst$$Register, $toc$$Register, MacroAssembler::largeoffset_si16_si16_hi(_const_toc_offset)); 2584 %} 2585 2586 %} // encode 2587 2588 source %{ 2589 2590 typedef struct { 2591 loadConL_hiNode *_large_hi; 2592 loadConL_loNode *_large_lo; 2593 loadConLNode *_small; 2594 MachNode *_last; 2595 } loadConLNodesTuple; 2596 2597 loadConLNodesTuple loadConLNodesTuple_create(Compile *C, PhaseRegAlloc *ra_, Node *toc, immLOper *immSrc, 2598 OptoReg::Name reg_second, OptoReg::Name reg_first) { 2599 loadConLNodesTuple nodes; 2600 2601 const bool large_constant_pool = true; // TODO: PPC port C->cfg()->_consts_size > 4000; 2602 if (large_constant_pool) { 2603 // Create new nodes. 2604 loadConL_hiNode *m1 = new (C) loadConL_hiNode(); 2605 loadConL_loNode *m2 = new (C) loadConL_loNode(); 2606 2607 // inputs for new nodes 2608 m1->add_req(NULL, toc); 2609 m2->add_req(NULL, m1); 2610 2611 // operands for new nodes 2612 m1->_opnds[0] = new (C) iRegLdstOper(); // dst 2613 m1->_opnds[1] = immSrc; // src 2614 m1->_opnds[2] = new (C) iRegPdstOper(); // toc 2615 m2->_opnds[0] = new (C) iRegLdstOper(); // dst 2616 m2->_opnds[1] = immSrc; // src 2617 m2->_opnds[2] = new (C) iRegLdstOper(); // base 2618 2619 // Initialize ins_attrib TOC fields. 2620 m1->_const_toc_offset = -1; 2621 m2->_const_toc_offset_hi_node = m1; 2622 2623 // Initialize ins_attrib instruction offset. 2624 m1->_cbuf_insts_offset = -1; 2625 2626 // register allocation for new nodes 2627 ra_->set_pair(m1->_idx, reg_second, reg_first); 2628 ra_->set_pair(m2->_idx, reg_second, reg_first); 2629 2630 // Create result. 2631 nodes._large_hi = m1; 2632 nodes._large_lo = m2; 2633 nodes._small = NULL; 2634 nodes._last = nodes._large_lo; 2635 assert(m2->bottom_type()->isa_long(), "must be long"); 2636 } else { 2637 loadConLNode *m2 = new (C) loadConLNode(); 2638 2639 // inputs for new nodes 2640 m2->add_req(NULL, toc); 2641 2642 // operands for new nodes 2643 m2->_opnds[0] = new (C) iRegLdstOper(); // dst 2644 m2->_opnds[1] = immSrc; // src 2645 m2->_opnds[2] = new (C) iRegPdstOper(); // toc 2646 2647 // Initialize ins_attrib instruction offset. 2648 m2->_cbuf_insts_offset = -1; 2649 2650 // register allocation for new nodes 2651 ra_->set_pair(m2->_idx, reg_second, reg_first); 2652 2653 // Create result. 2654 nodes._large_hi = NULL; 2655 nodes._large_lo = NULL; 2656 nodes._small = m2; 2657 nodes._last = nodes._small; 2658 assert(m2->bottom_type()->isa_long(), "must be long"); 2659 } 2660 2661 return nodes; 2662 } 2663 2664 %} // source 2665 2666 encode %{ 2667 // Postalloc expand emitter for loading a long constant from the method's TOC. 2668 // Enc_class needed as consttanttablebase is not supported by postalloc 2669 // expand. 2670 enc_class postalloc_expand_load_long_constant(iRegLdst dst, immL src, iRegLdst toc) %{ 2671 // Create new nodes. 2672 loadConLNodesTuple loadConLNodes = 2673 loadConLNodesTuple_create(C, ra_, n_toc, op_src, 2674 ra_->get_reg_second(this), ra_->get_reg_first(this)); 2675 2676 // Push new nodes. 2677 if (loadConLNodes._large_hi) nodes->push(loadConLNodes._large_hi); 2678 if (loadConLNodes._last) nodes->push(loadConLNodes._last); 2679 2680 // some asserts 2681 assert(nodes->length() >= 1, "must have created at least 1 node"); 2682 assert(loadConLNodes._last->bottom_type()->isa_long(), "must be long"); 2683 %} 2684 2685 enc_class enc_load_long_constP(iRegLdst dst, immP src, iRegLdst toc) %{ 2686 // TODO: PPC port $archOpcode(ppc64Opcode_ld); 2687 2688 MacroAssembler _masm(&cbuf); 2689 int toc_offset = 0; 2690 2691 if (!ra_->C->in_scratch_emit_size()) { 2692 intptr_t val = $src$$constant; 2693 relocInfo::relocType constant_reloc = $src->constant_reloc(); // src 2694 address const_toc_addr; 2695 if (constant_reloc == relocInfo::oop_type) { 2696 // Create an oop constant and a corresponding relocation. 2697 AddressLiteral a = __ allocate_oop_address((jobject)val); 2698 const_toc_addr = __ address_constant((address)a.value(), RelocationHolder::none); 2699 __ relocate(a.rspec()); 2700 } else if (constant_reloc == relocInfo::metadata_type) { 2701 AddressLiteral a = __ allocate_metadata_address((Metadata *)val); 2702 const_toc_addr = __ address_constant((address)a.value(), RelocationHolder::none); 2703 __ relocate(a.rspec()); 2704 } else { 2705 // Create a non-oop constant, no relocation needed. 2706 const_toc_addr = __ long_constant((jlong)$src$$constant); 2707 } 2708 2709 // Get the constant's TOC offset. 2710 toc_offset = __ offset_to_method_toc(const_toc_addr); 2711 } 2712 2713 __ ld($dst$$Register, toc_offset, $toc$$Register); 2714 %} 2715 2716 enc_class enc_load_long_constP_hi(iRegLdst dst, immP src, iRegLdst toc) %{ 2717 // TODO: PPC port $archOpcode(ppc64Opcode_addis); 2718 2719 MacroAssembler _masm(&cbuf); 2720 if (!ra_->C->in_scratch_emit_size()) { 2721 intptr_t val = $src$$constant; 2722 relocInfo::relocType constant_reloc = $src->constant_reloc(); // src 2723 address const_toc_addr; 2724 if (constant_reloc == relocInfo::oop_type) { 2725 // Create an oop constant and a corresponding relocation. 2726 AddressLiteral a = __ allocate_oop_address((jobject)val); 2727 const_toc_addr = __ address_constant((address)a.value(), RelocationHolder::none); 2728 __ relocate(a.rspec()); 2729 } else if (constant_reloc == relocInfo::metadata_type) { 2730 AddressLiteral a = __ allocate_metadata_address((Metadata *)val); 2731 const_toc_addr = __ address_constant((address)a.value(), RelocationHolder::none); 2732 __ relocate(a.rspec()); 2733 } else { // non-oop pointers, e.g. card mark base, heap top 2734 // Create a non-oop constant, no relocation needed. 2735 const_toc_addr = __ long_constant((jlong)$src$$constant); 2736 } 2737 2738 // Get the constant's TOC offset. 2739 const int toc_offset = __ offset_to_method_toc(const_toc_addr); 2740 // Store the toc offset of the constant. 2741 ((loadConP_hiNode*)this)->_const_toc_offset = toc_offset; 2742 } 2743 2744 __ addis($dst$$Register, $toc$$Register, MacroAssembler::largeoffset_si16_si16_hi(_const_toc_offset)); 2745 %} 2746 2747 // Postalloc expand emitter for loading a ptr constant from the method's TOC. 2748 // Enc_class needed as consttanttablebase is not supported by postalloc 2749 // expand. 2750 enc_class postalloc_expand_load_ptr_constant(iRegPdst dst, immP src, iRegLdst toc) %{ 2751 const bool large_constant_pool = true; // TODO: PPC port C->cfg()->_consts_size > 4000; 2752 if (large_constant_pool) { 2753 // Create new nodes. 2754 loadConP_hiNode *m1 = new (C) loadConP_hiNode(); 2755 loadConP_loNode *m2 = new (C) loadConP_loNode(); 2756 2757 // inputs for new nodes 2758 m1->add_req(NULL, n_toc); 2759 m2->add_req(NULL, m1); 2760 2761 // operands for new nodes 2762 m1->_opnds[0] = new (C) iRegPdstOper(); // dst 2763 m1->_opnds[1] = op_src; // src 2764 m1->_opnds[2] = new (C) iRegPdstOper(); // toc 2765 m2->_opnds[0] = new (C) iRegPdstOper(); // dst 2766 m2->_opnds[1] = op_src; // src 2767 m2->_opnds[2] = new (C) iRegLdstOper(); // base 2768 2769 // Initialize ins_attrib TOC fields. 2770 m1->_const_toc_offset = -1; 2771 m2->_const_toc_offset_hi_node = m1; 2772 2773 // Register allocation for new nodes. 2774 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 2775 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 2776 2777 nodes->push(m1); 2778 nodes->push(m2); 2779 assert(m2->bottom_type()->isa_ptr(), "must be ptr"); 2780 } else { 2781 loadConPNode *m2 = new (C) loadConPNode(); 2782 2783 // inputs for new nodes 2784 m2->add_req(NULL, n_toc); 2785 2786 // operands for new nodes 2787 m2->_opnds[0] = new (C) iRegPdstOper(); // dst 2788 m2->_opnds[1] = op_src; // src 2789 m2->_opnds[2] = new (C) iRegPdstOper(); // toc 2790 2791 // Register allocation for new nodes. 2792 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 2793 2794 nodes->push(m2); 2795 assert(m2->bottom_type()->isa_ptr(), "must be ptr"); 2796 } 2797 %} 2798 2799 // Enc_class needed as consttanttablebase is not supported by postalloc 2800 // expand. 2801 enc_class postalloc_expand_load_float_constant(regF dst, immF src, iRegLdst toc) %{ 2802 bool large_constant_pool = true; // TODO: PPC port C->cfg()->_consts_size > 4000; 2803 2804 MachNode *m2; 2805 if (large_constant_pool) { 2806 m2 = new (C) loadConFCompNode(); 2807 } else { 2808 m2 = new (C) loadConFNode(); 2809 } 2810 // inputs for new nodes 2811 m2->add_req(NULL, n_toc); 2812 2813 // operands for new nodes 2814 m2->_opnds[0] = op_dst; 2815 m2->_opnds[1] = op_src; 2816 m2->_opnds[2] = new (C) iRegPdstOper(); // constanttablebase 2817 2818 // register allocation for new nodes 2819 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 2820 nodes->push(m2); 2821 %} 2822 2823 // Enc_class needed as consttanttablebase is not supported by postalloc 2824 // expand. 2825 enc_class postalloc_expand_load_double_constant(regD dst, immD src, iRegLdst toc) %{ 2826 bool large_constant_pool = true; // TODO: PPC port C->cfg()->_consts_size > 4000; 2827 2828 MachNode *m2; 2829 if (large_constant_pool) { 2830 m2 = new (C) loadConDCompNode(); 2831 } else { 2832 m2 = new (C) loadConDNode(); 2833 } 2834 // inputs for new nodes 2835 m2->add_req(NULL, n_toc); 2836 2837 // operands for new nodes 2838 m2->_opnds[0] = op_dst; 2839 m2->_opnds[1] = op_src; 2840 m2->_opnds[2] = new (C) iRegPdstOper(); // constanttablebase 2841 2842 // register allocation for new nodes 2843 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 2844 nodes->push(m2); 2845 %} 2846 2847 enc_class enc_stw(iRegIsrc src, memory mem) %{ 2848 // TODO: PPC port $archOpcode(ppc64Opcode_stw); 2849 MacroAssembler _masm(&cbuf); 2850 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); 2851 __ stw($src$$Register, Idisp, $mem$$base$$Register); 2852 %} 2853 2854 enc_class enc_std(iRegIsrc src, memoryAlg4 mem) %{ 2855 // TODO: PPC port $archOpcode(ppc64Opcode_std); 2856 MacroAssembler _masm(&cbuf); 2857 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); 2858 // Operand 'ds' requires 4-alignment. 2859 assert((Idisp & 0x3) == 0, "unaligned offset"); 2860 __ std($src$$Register, Idisp, $mem$$base$$Register); 2861 %} 2862 2863 enc_class enc_stfs(RegF src, memory mem) %{ 2864 // TODO: PPC port $archOpcode(ppc64Opcode_stfs); 2865 MacroAssembler _masm(&cbuf); 2866 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); 2867 __ stfs($src$$FloatRegister, Idisp, $mem$$base$$Register); 2868 %} 2869 2870 enc_class enc_stfd(RegF src, memory mem) %{ 2871 // TODO: PPC port $archOpcode(ppc64Opcode_stfd); 2872 MacroAssembler _masm(&cbuf); 2873 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); 2874 __ stfd($src$$FloatRegister, Idisp, $mem$$base$$Register); 2875 %} 2876 2877 // Use release_store for card-marking to ensure that previous 2878 // oop-stores are visible before the card-mark change. 2879 enc_class enc_cms_card_mark(memory mem, iRegLdst releaseFieldAddr) %{ 2880 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 2881 // FIXME: Implement this as a cmove and use a fixed condition code 2882 // register which is written on every transition to compiled code, 2883 // e.g. in call-stub and when returning from runtime stubs. 2884 // 2885 // Proposed code sequence for the cmove implementation: 2886 // 2887 // Label skip_release; 2888 // __ beq(CCRfixed, skip_release); 2889 // __ release(); 2890 // __ bind(skip_release); 2891 // __ stb(card mark); 2892 2893 MacroAssembler _masm(&cbuf); 2894 Label skip_storestore; 2895 2896 #if 0 // TODO: PPC port 2897 // Check CMSCollectorCardTableModRefBSExt::_requires_release and do the 2898 // StoreStore barrier conditionally. 2899 __ lwz(R0, 0, $releaseFieldAddr$$Register); 2900 __ cmpwi(CCR0, R0, 0); 2901 __ beq_predict_taken(CCR0, skip_storestore); 2902 #endif 2903 __ li(R0, 0); 2904 __ membar(Assembler::StoreStore); 2905 #if 0 // TODO: PPC port 2906 __ bind(skip_storestore); 2907 #endif 2908 2909 // Do the store. 2910 if ($mem$$index == 0) { 2911 __ stb(R0, $mem$$disp, $mem$$base$$Register); 2912 } else { 2913 assert(0 == $mem$$disp, "no displacement possible with indexed load/stores on ppc"); 2914 __ stbx(R0, $mem$$base$$Register, $mem$$index$$Register); 2915 } 2916 %} 2917 2918 enc_class postalloc_expand_encode_oop(iRegNdst dst, iRegPdst src, flagsReg crx) %{ 2919 2920 if (VM_Version::has_isel()) { 2921 // use isel instruction with Power 7 2922 cmpP_reg_imm16Node *n_compare = new (C) cmpP_reg_imm16Node(); 2923 encodeP_subNode *n_sub_base = new (C) encodeP_subNode(); 2924 encodeP_shiftNode *n_shift = new (C) encodeP_shiftNode(); 2925 cond_set_0_oopNode *n_cond_set = new (C) cond_set_0_oopNode(); 2926 2927 n_compare->add_req(n_region, n_src); 2928 n_compare->_opnds[0] = op_crx; 2929 n_compare->_opnds[1] = op_src; 2930 n_compare->_opnds[2] = new (C) immL16Oper(0); 2931 2932 n_sub_base->add_req(n_region, n_src); 2933 n_sub_base->_opnds[0] = op_dst; 2934 n_sub_base->_opnds[1] = op_src; 2935 n_sub_base->_bottom_type = _bottom_type; 2936 2937 n_shift->add_req(n_region, n_sub_base); 2938 n_shift->_opnds[0] = op_dst; 2939 n_shift->_opnds[1] = op_dst; 2940 n_shift->_bottom_type = _bottom_type; 2941 2942 n_cond_set->add_req(n_region, n_compare, n_shift); 2943 n_cond_set->_opnds[0] = op_dst; 2944 n_cond_set->_opnds[1] = op_crx; 2945 n_cond_set->_opnds[2] = op_dst; 2946 n_cond_set->_bottom_type = _bottom_type; 2947 2948 ra_->set_pair(n_compare->_idx, ra_->get_reg_second(n_crx), ra_->get_reg_first(n_crx)); 2949 ra_->set_pair(n_sub_base->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 2950 ra_->set_pair(n_shift->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 2951 ra_->set_pair(n_cond_set->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 2952 2953 nodes->push(n_compare); 2954 nodes->push(n_sub_base); 2955 nodes->push(n_shift); 2956 nodes->push(n_cond_set); 2957 2958 } else { 2959 // before Power 7 2960 moveRegNode *n_move = new (C) moveRegNode(); 2961 cmpP_reg_imm16Node *n_compare = new (C) cmpP_reg_imm16Node(); 2962 encodeP_shiftNode *n_shift = new (C) encodeP_shiftNode(); 2963 cond_sub_baseNode *n_sub_base = new (C) cond_sub_baseNode(); 2964 2965 n_move->add_req(n_region, n_src); 2966 n_move->_opnds[0] = op_dst; 2967 n_move->_opnds[1] = op_src; 2968 ra_->set_oop(n_move, true); // Until here, 'n_move' still produces an oop. 2969 2970 n_compare->add_req(n_region, n_src); 2971 n_compare->add_prec(n_move); 2972 2973 n_compare->_opnds[0] = op_crx; 2974 n_compare->_opnds[1] = op_src; 2975 n_compare->_opnds[2] = new (C) immL16Oper(0); 2976 2977 n_sub_base->add_req(n_region, n_compare, n_src); 2978 n_sub_base->_opnds[0] = op_dst; 2979 n_sub_base->_opnds[1] = op_crx; 2980 n_sub_base->_opnds[2] = op_src; 2981 n_sub_base->_bottom_type = _bottom_type; 2982 2983 n_shift->add_req(n_region, n_sub_base); 2984 n_shift->_opnds[0] = op_dst; 2985 n_shift->_opnds[1] = op_dst; 2986 n_shift->_bottom_type = _bottom_type; 2987 2988 ra_->set_pair(n_shift->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 2989 ra_->set_pair(n_compare->_idx, ra_->get_reg_second(n_crx), ra_->get_reg_first(n_crx)); 2990 ra_->set_pair(n_sub_base->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 2991 ra_->set_pair(n_move->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 2992 2993 nodes->push(n_move); 2994 nodes->push(n_compare); 2995 nodes->push(n_sub_base); 2996 nodes->push(n_shift); 2997 } 2998 2999 assert(!(ra_->is_oop(this)), "sanity"); // This is not supposed to be GC'ed. 3000 %} 3001 3002 enc_class postalloc_expand_encode_oop_not_null(iRegNdst dst, iRegPdst src) %{ 3003 3004 encodeP_subNode *n1 = new (C) encodeP_subNode(); 3005 n1->add_req(n_region, n_src); 3006 n1->_opnds[0] = op_dst; 3007 n1->_opnds[1] = op_src; 3008 n1->_bottom_type = _bottom_type; 3009 3010 encodeP_shiftNode *n2 = new (C) encodeP_shiftNode(); 3011 n2->add_req(n_region, n1); 3012 n2->_opnds[0] = op_dst; 3013 n2->_opnds[1] = op_dst; 3014 n2->_bottom_type = _bottom_type; 3015 ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 3016 ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 3017 3018 nodes->push(n1); 3019 nodes->push(n2); 3020 assert(!(ra_->is_oop(this)), "sanity"); // This is not supposed to be GC'ed. 3021 %} 3022 3023 enc_class postalloc_expand_decode_oop(iRegPdst dst, iRegNsrc src, flagsReg crx) %{ 3024 decodeN_shiftNode *n_shift = new (C) decodeN_shiftNode(); 3025 cmpN_reg_imm0Node *n_compare = new (C) cmpN_reg_imm0Node(); 3026 3027 n_compare->add_req(n_region, n_src); 3028 n_compare->_opnds[0] = op_crx; 3029 n_compare->_opnds[1] = op_src; 3030 n_compare->_opnds[2] = new (C) immN_0Oper(TypeNarrowOop::NULL_PTR); 3031 3032 n_shift->add_req(n_region, n_src); 3033 n_shift->_opnds[0] = op_dst; 3034 n_shift->_opnds[1] = op_src; 3035 n_shift->_bottom_type = _bottom_type; 3036 3037 if (VM_Version::has_isel()) { 3038 // use isel instruction with Power 7 3039 3040 decodeN_addNode *n_add_base = new (C) decodeN_addNode(); 3041 n_add_base->add_req(n_region, n_shift); 3042 n_add_base->_opnds[0] = op_dst; 3043 n_add_base->_opnds[1] = op_dst; 3044 n_add_base->_bottom_type = _bottom_type; 3045 3046 cond_set_0_ptrNode *n_cond_set = new (C) cond_set_0_ptrNode(); 3047 n_cond_set->add_req(n_region, n_compare, n_add_base); 3048 n_cond_set->_opnds[0] = op_dst; 3049 n_cond_set->_opnds[1] = op_crx; 3050 n_cond_set->_opnds[2] = op_dst; 3051 n_cond_set->_bottom_type = _bottom_type; 3052 3053 assert(ra_->is_oop(this) == true, "A decodeN node must produce an oop!"); 3054 ra_->set_oop(n_cond_set, true); 3055 3056 ra_->set_pair(n_shift->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 3057 ra_->set_pair(n_compare->_idx, ra_->get_reg_second(n_crx), ra_->get_reg_first(n_crx)); 3058 ra_->set_pair(n_add_base->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 3059 ra_->set_pair(n_cond_set->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 3060 3061 nodes->push(n_compare); 3062 nodes->push(n_shift); 3063 nodes->push(n_add_base); 3064 nodes->push(n_cond_set); 3065 3066 } else { 3067 // before Power 7 3068 cond_add_baseNode *n_add_base = new (C) cond_add_baseNode(); 3069 3070 n_add_base->add_req(n_region, n_compare, n_shift); 3071 n_add_base->_opnds[0] = op_dst; 3072 n_add_base->_opnds[1] = op_crx; 3073 n_add_base->_opnds[2] = op_dst; 3074 n_add_base->_bottom_type = _bottom_type; 3075 3076 assert(ra_->is_oop(this) == true, "A decodeN node must produce an oop!"); 3077 ra_->set_oop(n_add_base, true); 3078 3079 ra_->set_pair(n_shift->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 3080 ra_->set_pair(n_compare->_idx, ra_->get_reg_second(n_crx), ra_->get_reg_first(n_crx)); 3081 ra_->set_pair(n_add_base->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 3082 3083 nodes->push(n_compare); 3084 nodes->push(n_shift); 3085 nodes->push(n_add_base); 3086 } 3087 %} 3088 3089 enc_class postalloc_expand_decode_oop_not_null(iRegPdst dst, iRegNsrc src) %{ 3090 decodeN_shiftNode *n1 = new (C) decodeN_shiftNode(); 3091 n1->add_req(n_region, n_src); 3092 n1->_opnds[0] = op_dst; 3093 n1->_opnds[1] = op_src; 3094 n1->_bottom_type = _bottom_type; 3095 3096 decodeN_addNode *n2 = new (C) decodeN_addNode(); 3097 n2->add_req(n_region, n1); 3098 n2->_opnds[0] = op_dst; 3099 n2->_opnds[1] = op_dst; 3100 n2->_bottom_type = _bottom_type; 3101 ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 3102 ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 3103 3104 assert(ra_->is_oop(this) == true, "A decodeN node must produce an oop!"); 3105 ra_->set_oop(n2, true); 3106 3107 nodes->push(n1); 3108 nodes->push(n2); 3109 %} 3110 3111 enc_class enc_cmove_reg(iRegIdst dst, flagsReg crx, iRegIsrc src, cmpOp cmp) %{ 3112 // TODO: PPC port $archOpcode(ppc64Opcode_cmove); 3113 3114 MacroAssembler _masm(&cbuf); 3115 int cc = $cmp$$cmpcode; 3116 int flags_reg = $crx$$reg; 3117 Label done; 3118 assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding"); 3119 // Branch if not (cmp crx). 3120 __ bc(cc_to_inverse_boint(cc), cc_to_biint(cc, flags_reg), done); 3121 __ mr($dst$$Register, $src$$Register); 3122 // TODO PPC port __ endgroup_if_needed(_size == 12); 3123 __ bind(done); 3124 %} 3125 3126 enc_class enc_cmove_imm(iRegIdst dst, flagsReg crx, immI16 src, cmpOp cmp) %{ 3127 // TODO: PPC port $archOpcode(ppc64Opcode_cmove); 3128 3129 MacroAssembler _masm(&cbuf); 3130 Label done; 3131 assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding"); 3132 // Branch if not (cmp crx). 3133 __ bc(cc_to_inverse_boint($cmp$$cmpcode), cc_to_biint($cmp$$cmpcode, $crx$$reg), done); 3134 __ li($dst$$Register, $src$$constant); 3135 // TODO PPC port __ endgroup_if_needed(_size == 12); 3136 __ bind(done); 3137 %} 3138 3139 // New atomics. 3140 enc_class enc_GetAndAddI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src) %{ 3141 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 3142 3143 MacroAssembler _masm(&cbuf); 3144 Register Rtmp = R0; 3145 Register Rres = $res$$Register; 3146 Register Rsrc = $src$$Register; 3147 Register Rptr = $mem_ptr$$Register; 3148 bool RegCollision = (Rres == Rsrc) || (Rres == Rptr); 3149 Register Rold = RegCollision ? Rtmp : Rres; 3150 3151 Label Lretry; 3152 __ bind(Lretry); 3153 __ lwarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update()); 3154 __ add(Rtmp, Rsrc, Rold); 3155 __ stwcx_(Rtmp, Rptr); 3156 if (UseStaticBranchPredictionInCompareAndSwapPPC64) { 3157 __ bne_predict_not_taken(CCR0, Lretry); 3158 } else { 3159 __ bne( CCR0, Lretry); 3160 } 3161 if (RegCollision) __ subf(Rres, Rsrc, Rtmp); 3162 __ fence(); 3163 %} 3164 3165 enc_class enc_GetAndAddL(iRegLdst res, iRegPdst mem_ptr, iRegLsrc src) %{ 3166 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 3167 3168 MacroAssembler _masm(&cbuf); 3169 Register Rtmp = R0; 3170 Register Rres = $res$$Register; 3171 Register Rsrc = $src$$Register; 3172 Register Rptr = $mem_ptr$$Register; 3173 bool RegCollision = (Rres == Rsrc) || (Rres == Rptr); 3174 Register Rold = RegCollision ? Rtmp : Rres; 3175 3176 Label Lretry; 3177 __ bind(Lretry); 3178 __ ldarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update()); 3179 __ add(Rtmp, Rsrc, Rold); 3180 __ stdcx_(Rtmp, Rptr); 3181 if (UseStaticBranchPredictionInCompareAndSwapPPC64) { 3182 __ bne_predict_not_taken(CCR0, Lretry); 3183 } else { 3184 __ bne( CCR0, Lretry); 3185 } 3186 if (RegCollision) __ subf(Rres, Rsrc, Rtmp); 3187 __ fence(); 3188 %} 3189 3190 enc_class enc_GetAndSetI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src) %{ 3191 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 3192 3193 MacroAssembler _masm(&cbuf); 3194 Register Rtmp = R0; 3195 Register Rres = $res$$Register; 3196 Register Rsrc = $src$$Register; 3197 Register Rptr = $mem_ptr$$Register; 3198 bool RegCollision = (Rres == Rsrc) || (Rres == Rptr); 3199 Register Rold = RegCollision ? Rtmp : Rres; 3200 3201 Label Lretry; 3202 __ bind(Lretry); 3203 __ lwarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update()); 3204 __ stwcx_(Rsrc, Rptr); 3205 if (UseStaticBranchPredictionInCompareAndSwapPPC64) { 3206 __ bne_predict_not_taken(CCR0, Lretry); 3207 } else { 3208 __ bne( CCR0, Lretry); 3209 } 3210 if (RegCollision) __ mr(Rres, Rtmp); 3211 __ fence(); 3212 %} 3213 3214 enc_class enc_GetAndSetL(iRegLdst res, iRegPdst mem_ptr, iRegLsrc src) %{ 3215 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 3216 3217 MacroAssembler _masm(&cbuf); 3218 Register Rtmp = R0; 3219 Register Rres = $res$$Register; 3220 Register Rsrc = $src$$Register; 3221 Register Rptr = $mem_ptr$$Register; 3222 bool RegCollision = (Rres == Rsrc) || (Rres == Rptr); 3223 Register Rold = RegCollision ? Rtmp : Rres; 3224 3225 Label Lretry; 3226 __ bind(Lretry); 3227 __ ldarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update()); 3228 __ stdcx_(Rsrc, Rptr); 3229 if (UseStaticBranchPredictionInCompareAndSwapPPC64) { 3230 __ bne_predict_not_taken(CCR0, Lretry); 3231 } else { 3232 __ bne( CCR0, Lretry); 3233 } 3234 if (RegCollision) __ mr(Rres, Rtmp); 3235 __ fence(); 3236 %} 3237 3238 // This enc_class is needed so that scheduler gets proper 3239 // input mapping for latency computation. 3240 enc_class enc_andc(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ 3241 // TODO: PPC port $archOpcode(ppc64Opcode_andc); 3242 MacroAssembler _masm(&cbuf); 3243 __ andc($dst$$Register, $src1$$Register, $src2$$Register); 3244 %} 3245 3246 enc_class enc_convI2B_regI__cmove(iRegIdst dst, iRegIsrc src, flagsReg crx, immI16 zero, immI16 notzero) %{ 3247 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 3248 3249 MacroAssembler _masm(&cbuf); 3250 3251 Label done; 3252 __ cmpwi($crx$$CondRegister, $src$$Register, 0); 3253 __ li($dst$$Register, $zero$$constant); 3254 __ beq($crx$$CondRegister, done); 3255 __ li($dst$$Register, $notzero$$constant); 3256 __ bind(done); 3257 %} 3258 3259 enc_class enc_convP2B_regP__cmove(iRegIdst dst, iRegPsrc src, flagsReg crx, immI16 zero, immI16 notzero) %{ 3260 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 3261 3262 MacroAssembler _masm(&cbuf); 3263 3264 Label done; 3265 __ cmpdi($crx$$CondRegister, $src$$Register, 0); 3266 __ li($dst$$Register, $zero$$constant); 3267 __ beq($crx$$CondRegister, done); 3268 __ li($dst$$Register, $notzero$$constant); 3269 __ bind(done); 3270 %} 3271 3272 enc_class enc_cmove_bso_stackSlotL(iRegLdst dst, flagsReg crx, stackSlotL mem ) %{ 3273 // TODO: PPC port $archOpcode(ppc64Opcode_cmove); 3274 3275 MacroAssembler _masm(&cbuf); 3276 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); 3277 Label done; 3278 __ bso($crx$$CondRegister, done); 3279 __ ld($dst$$Register, Idisp, $mem$$base$$Register); 3280 // TODO PPC port __ endgroup_if_needed(_size == 12); 3281 __ bind(done); 3282 %} 3283 3284 enc_class enc_bc(flagsReg crx, cmpOp cmp, Label lbl) %{ 3285 // TODO: PPC port $archOpcode(ppc64Opcode_bc); 3286 3287 MacroAssembler _masm(&cbuf); 3288 Label d; // dummy 3289 __ bind(d); 3290 Label* p = ($lbl$$label); 3291 // `p' is `NULL' when this encoding class is used only to 3292 // determine the size of the encoded instruction. 3293 Label& l = (NULL == p)? d : *(p); 3294 int cc = $cmp$$cmpcode; 3295 int flags_reg = $crx$$reg; 3296 assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding"); 3297 int bhint = Assembler::bhintNoHint; 3298 3299 if (UseStaticBranchPredictionForUncommonPathsPPC64) { 3300 if (_prob <= PROB_NEVER) { 3301 bhint = Assembler::bhintIsNotTaken; 3302 } else if (_prob >= PROB_ALWAYS) { 3303 bhint = Assembler::bhintIsTaken; 3304 } 3305 } 3306 3307 __ bc(Assembler::add_bhint_to_boint(bhint, cc_to_boint(cc)), 3308 cc_to_biint(cc, flags_reg), 3309 l); 3310 %} 3311 3312 enc_class enc_bc_far(flagsReg crx, cmpOp cmp, Label lbl) %{ 3313 // The scheduler doesn't know about branch shortening, so we set the opcode 3314 // to ppc64Opcode_bc in order to hide this detail from the scheduler. 3315 // TODO: PPC port $archOpcode(ppc64Opcode_bc); 3316 3317 MacroAssembler _masm(&cbuf); 3318 Label d; // dummy 3319 __ bind(d); 3320 Label* p = ($lbl$$label); 3321 // `p' is `NULL' when this encoding class is used only to 3322 // determine the size of the encoded instruction. 3323 Label& l = (NULL == p)? d : *(p); 3324 int cc = $cmp$$cmpcode; 3325 int flags_reg = $crx$$reg; 3326 int bhint = Assembler::bhintNoHint; 3327 3328 if (UseStaticBranchPredictionForUncommonPathsPPC64) { 3329 if (_prob <= PROB_NEVER) { 3330 bhint = Assembler::bhintIsNotTaken; 3331 } else if (_prob >= PROB_ALWAYS) { 3332 bhint = Assembler::bhintIsTaken; 3333 } 3334 } 3335 3336 // Tell the conditional far branch to optimize itself when being relocated. 3337 __ bc_far(Assembler::add_bhint_to_boint(bhint, cc_to_boint(cc)), 3338 cc_to_biint(cc, flags_reg), 3339 l, 3340 MacroAssembler::bc_far_optimize_on_relocate); 3341 %} 3342 3343 // Branch used with Power6 scheduling (can be shortened without changing the node). 3344 enc_class enc_bc_short_far(flagsReg crx, cmpOp cmp, Label lbl) %{ 3345 // The scheduler doesn't know about branch shortening, so we set the opcode 3346 // to ppc64Opcode_bc in order to hide this detail from the scheduler. 3347 // TODO: PPC port $archOpcode(ppc64Opcode_bc); 3348 3349 MacroAssembler _masm(&cbuf); 3350 Label d; // dummy 3351 __ bind(d); 3352 Label* p = ($lbl$$label); 3353 // `p' is `NULL' when this encoding class is used only to 3354 // determine the size of the encoded instruction. 3355 Label& l = (NULL == p)? d : *(p); 3356 int cc = $cmp$$cmpcode; 3357 int flags_reg = $crx$$reg; 3358 int bhint = Assembler::bhintNoHint; 3359 3360 if (UseStaticBranchPredictionForUncommonPathsPPC64) { 3361 if (_prob <= PROB_NEVER) { 3362 bhint = Assembler::bhintIsNotTaken; 3363 } else if (_prob >= PROB_ALWAYS) { 3364 bhint = Assembler::bhintIsTaken; 3365 } 3366 } 3367 3368 #if 0 // TODO: PPC port 3369 if (_size == 8) { 3370 // Tell the conditional far branch to optimize itself when being relocated. 3371 __ bc_far(Assembler::add_bhint_to_boint(bhint, cc_to_boint(cc)), 3372 cc_to_biint(cc, flags_reg), 3373 l, 3374 MacroAssembler::bc_far_optimize_on_relocate); 3375 } else { 3376 __ bc (Assembler::add_bhint_to_boint(bhint, cc_to_boint(cc)), 3377 cc_to_biint(cc, flags_reg), 3378 l); 3379 } 3380 #endif 3381 Unimplemented(); 3382 %} 3383 3384 // Postalloc expand emitter for loading a replicatef float constant from 3385 // the method's TOC. 3386 // Enc_class needed as consttanttablebase is not supported by postalloc 3387 // expand. 3388 enc_class postalloc_expand_load_replF_constant(iRegLdst dst, immF src, iRegLdst toc) %{ 3389 // Create new nodes. 3390 3391 // Make an operand with the bit pattern to load as float. 3392 immLOper *op_repl = new (C) immLOper((jlong)replicate_immF(op_src->constantF())); 3393 3394 loadConLNodesTuple loadConLNodes = 3395 loadConLNodesTuple_create(C, ra_, n_toc, op_repl, 3396 ra_->get_reg_second(this), ra_->get_reg_first(this)); 3397 3398 // Push new nodes. 3399 if (loadConLNodes._large_hi) nodes->push(loadConLNodes._large_hi); 3400 if (loadConLNodes._last) nodes->push(loadConLNodes._last); 3401 3402 assert(nodes->length() >= 1, "must have created at least 1 node"); 3403 assert(loadConLNodes._last->bottom_type()->isa_long(), "must be long"); 3404 %} 3405 3406 // This enc_class is needed so that scheduler gets proper 3407 // input mapping for latency computation. 3408 enc_class enc_poll(immI dst, iRegLdst poll) %{ 3409 // TODO: PPC port $archOpcode(ppc64Opcode_ld); 3410 // Fake operand dst needed for PPC scheduler. 3411 assert($dst$$constant == 0x0, "dst must be 0x0"); 3412 3413 MacroAssembler _masm(&cbuf); 3414 // Mark the code position where the load from the safepoint 3415 // polling page was emitted as relocInfo::poll_type. 3416 __ relocate(relocInfo::poll_type); 3417 __ load_from_polling_page($poll$$Register); 3418 %} 3419 3420 // A Java static call or a runtime call. 3421 // 3422 // Branch-and-link relative to a trampoline. 3423 // The trampoline loads the target address and does a long branch to there. 3424 // In case we call java, the trampoline branches to a interpreter_stub 3425 // which loads the inline cache and the real call target from the constant pool. 3426 // 3427 // This basically looks like this: 3428 // 3429 // >>>> consts -+ -+ 3430 // | |- offset1 3431 // [call target1] | <-+ 3432 // [IC cache] |- offset2 3433 // [call target2] <--+ 3434 // 3435 // <<<< consts 3436 // >>>> insts 3437 // 3438 // bl offset16 -+ -+ ??? // How many bits available? 3439 // | | 3440 // <<<< insts | | 3441 // >>>> stubs | | 3442 // | |- trampoline_stub_Reloc 3443 // trampoline stub: | <-+ 3444 // r2 = toc | 3445 // r2 = [r2 + offset1] | // Load call target1 from const section 3446 // mtctr r2 | 3447 // bctr |- static_stub_Reloc 3448 // comp_to_interp_stub: <---+ 3449 // r1 = toc 3450 // ICreg = [r1 + IC_offset] // Load IC from const section 3451 // r1 = [r1 + offset2] // Load call target2 from const section 3452 // mtctr r1 3453 // bctr 3454 // 3455 // <<<< stubs 3456 // 3457 // The call instruction in the code either 3458 // - Branches directly to a compiled method if the offset is encodable in instruction. 3459 // - Branches to the trampoline stub if the offset to the compiled method is not encodable. 3460 // - Branches to the compiled_to_interp stub if the target is interpreted. 3461 // 3462 // Further there are three relocations from the loads to the constants in 3463 // the constant section. 3464 // 3465 // Usage of r1 and r2 in the stubs allows to distinguish them. 3466 enc_class enc_java_static_call(method meth) %{ 3467 // TODO: PPC port $archOpcode(ppc64Opcode_bl); 3468 3469 MacroAssembler _masm(&cbuf); 3470 address entry_point = (address)$meth$$method; 3471 3472 if (!_method) { 3473 // A call to a runtime wrapper, e.g. new, new_typeArray_Java, uncommon_trap. 3474 emit_call_with_trampoline_stub(_masm, entry_point, relocInfo::runtime_call_type); 3475 } else { 3476 // Remember the offset not the address. 3477 const int start_offset = __ offset(); 3478 // The trampoline stub. 3479 if (!Compile::current()->in_scratch_emit_size()) { 3480 // No entry point given, use the current pc. 3481 // Make sure branch fits into 3482 if (entry_point == 0) entry_point = __ pc(); 3483 3484 // Put the entry point as a constant into the constant pool. 3485 const address entry_point_toc_addr = __ address_constant(entry_point, RelocationHolder::none); 3486 const int entry_point_toc_offset = __ offset_to_method_toc(entry_point_toc_addr); 3487 3488 // Emit the trampoline stub which will be related to the branch-and-link below. 3489 CallStubImpl::emit_trampoline_stub(_masm, entry_point_toc_offset, start_offset); 3490 if (Compile::current()->env()->failing()) { return; } // Code cache may be full. 3491 __ relocate(_optimized_virtual ? 3492 relocInfo::opt_virtual_call_type : relocInfo::static_call_type); 3493 } 3494 3495 // The real call. 3496 // Note: At this point we do not have the address of the trampoline 3497 // stub, and the entry point might be too far away for bl, so __ pc() 3498 // serves as dummy and the bl will be patched later. 3499 cbuf.set_insts_mark(); 3500 __ bl(__ pc()); // Emits a relocation. 3501 3502 // The stub for call to interpreter. 3503 CompiledStaticCall::emit_to_interp_stub(cbuf); 3504 } 3505 %} 3506 3507 // Emit a method handle call. 3508 // 3509 // Method handle calls from compiled to compiled are going thru a 3510 // c2i -> i2c adapter, extending the frame for their arguments. The 3511 // caller however, returns directly to the compiled callee, that has 3512 // to cope with the extended frame. We restore the original frame by 3513 // loading the callers sp and adding the calculated framesize. 3514 enc_class enc_java_handle_call(method meth) %{ 3515 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 3516 3517 MacroAssembler _masm(&cbuf); 3518 address entry_point = (address)$meth$$method; 3519 3520 // Remember the offset not the address. 3521 const int start_offset = __ offset(); 3522 // The trampoline stub. 3523 if (!ra_->C->in_scratch_emit_size()) { 3524 // No entry point given, use the current pc. 3525 // Make sure branch fits into 3526 if (entry_point == 0) entry_point = __ pc(); 3527 3528 // Put the entry point as a constant into the constant pool. 3529 const address entry_point_toc_addr = __ address_constant(entry_point, RelocationHolder::none); 3530 const int entry_point_toc_offset = __ offset_to_method_toc(entry_point_toc_addr); 3531 3532 // Emit the trampoline stub which will be related to the branch-and-link below. 3533 CallStubImpl::emit_trampoline_stub(_masm, entry_point_toc_offset, start_offset); 3534 if (ra_->C->env()->failing()) { return; } // Code cache may be full. 3535 assert(_optimized_virtual, "methodHandle call should be a virtual call"); 3536 __ relocate(relocInfo::opt_virtual_call_type); 3537 } 3538 3539 // The real call. 3540 // Note: At this point we do not have the address of the trampoline 3541 // stub, and the entry point might be too far away for bl, so __ pc() 3542 // serves as dummy and the bl will be patched later. 3543 cbuf.set_insts_mark(); 3544 __ bl(__ pc()); // Emits a relocation. 3545 3546 assert(_method, "execute next statement conditionally"); 3547 // The stub for call to interpreter. 3548 CompiledStaticCall::emit_to_interp_stub(cbuf); 3549 3550 // Restore original sp. 3551 __ ld(R11_scratch1, 0, R1_SP); // Load caller sp. 3552 const long framesize = ra_->C->frame_slots() << LogBytesPerInt; 3553 unsigned int bytes = (unsigned int)framesize; 3554 long offset = Assembler::align_addr(bytes, frame::alignment_in_bytes); 3555 if (Assembler::is_simm(-offset, 16)) { 3556 __ addi(R1_SP, R11_scratch1, -offset); 3557 } else { 3558 __ load_const_optimized(R12_scratch2, -offset); 3559 __ add(R1_SP, R11_scratch1, R12_scratch2); 3560 } 3561 #ifdef ASSERT 3562 __ ld(R12_scratch2, 0, R1_SP); // Load from unextended_sp. 3563 __ cmpd(CCR0, R11_scratch1, R12_scratch2); 3564 __ asm_assert_eq("backlink changed", 0x8000); 3565 #endif 3566 // If fails should store backlink before unextending. 3567 3568 if (ra_->C->env()->failing()) { 3569 return; 3570 } 3571 %} 3572 3573 // Second node of expanded dynamic call - the call. 3574 enc_class enc_java_dynamic_call_sched(method meth) %{ 3575 // TODO: PPC port $archOpcode(ppc64Opcode_bl); 3576 3577 MacroAssembler _masm(&cbuf); 3578 3579 if (!ra_->C->in_scratch_emit_size()) { 3580 // Create a call trampoline stub for the given method. 3581 const address entry_point = !($meth$$method) ? 0 : (address)$meth$$method; 3582 const address entry_point_const = __ address_constant(entry_point, RelocationHolder::none); 3583 const int entry_point_const_toc_offset = __ offset_to_method_toc(entry_point_const); 3584 CallStubImpl::emit_trampoline_stub(_masm, entry_point_const_toc_offset, __ offset()); 3585 if (ra_->C->env()->failing()) { return; } // Code cache may be full. 3586 3587 // Build relocation at call site with ic position as data. 3588 assert((_load_ic_hi_node != NULL && _load_ic_node == NULL) || 3589 (_load_ic_hi_node == NULL && _load_ic_node != NULL), 3590 "must have one, but can't have both"); 3591 assert((_load_ic_hi_node != NULL && _load_ic_hi_node->_cbuf_insts_offset != -1) || 3592 (_load_ic_node != NULL && _load_ic_node->_cbuf_insts_offset != -1), 3593 "must contain instruction offset"); 3594 const int virtual_call_oop_addr_offset = _load_ic_hi_node != NULL 3595 ? _load_ic_hi_node->_cbuf_insts_offset 3596 : _load_ic_node->_cbuf_insts_offset; 3597 const address virtual_call_oop_addr = __ addr_at(virtual_call_oop_addr_offset); 3598 assert(MacroAssembler::is_load_const_from_method_toc_at(virtual_call_oop_addr), 3599 "should be load from TOC"); 3600 3601 __ relocate(virtual_call_Relocation::spec(virtual_call_oop_addr)); 3602 } 3603 3604 // At this point I do not have the address of the trampoline stub, 3605 // and the entry point might be too far away for bl. Pc() serves 3606 // as dummy and bl will be patched later. 3607 __ bl((address) __ pc()); 3608 %} 3609 3610 // postalloc expand emitter for virtual calls. 3611 enc_class postalloc_expand_java_dynamic_call_sched(method meth, iRegLdst toc) %{ 3612 3613 // Create the nodes for loading the IC from the TOC. 3614 loadConLNodesTuple loadConLNodes_IC = 3615 loadConLNodesTuple_create(C, ra_, n_toc, new (C) immLOper((jlong)Universe::non_oop_word()), 3616 OptoReg::Name(R19_H_num), OptoReg::Name(R19_num)); 3617 3618 // Create the call node. 3619 CallDynamicJavaDirectSchedNode *call = new (C) CallDynamicJavaDirectSchedNode(); 3620 call->_method_handle_invoke = _method_handle_invoke; 3621 call->_vtable_index = _vtable_index; 3622 call->_method = _method; 3623 call->_bci = _bci; 3624 call->_optimized_virtual = _optimized_virtual; 3625 call->_tf = _tf; 3626 call->_entry_point = _entry_point; 3627 call->_cnt = _cnt; 3628 call->_argsize = _argsize; 3629 call->_oop_map = _oop_map; 3630 call->_jvms = _jvms; 3631 call->_jvmadj = _jvmadj; 3632 call->_in_rms = _in_rms; 3633 call->_nesting = _nesting; 3634 3635 // New call needs all inputs of old call. 3636 // Req... 3637 for (uint i = 0; i < req(); ++i) { 3638 // The expanded node does not need toc any more. 3639 // Add the inline cache constant here instead. This expresses the 3640 // register of the inline cache must be live at the call. 3641 // Else we would have to adapt JVMState by -1. 3642 if (i == mach_constant_base_node_input()) { 3643 call->add_req(loadConLNodes_IC._last); 3644 } else { 3645 call->add_req(in(i)); 3646 } 3647 } 3648 // ...as well as prec 3649 for (uint i = req(); i < len(); ++i) { 3650 call->add_prec(in(i)); 3651 } 3652 3653 // Remember nodes loading the inline cache into r19. 3654 call->_load_ic_hi_node = loadConLNodes_IC._large_hi; 3655 call->_load_ic_node = loadConLNodes_IC._small; 3656 3657 // Operands for new nodes. 3658 call->_opnds[0] = _opnds[0]; 3659 call->_opnds[1] = _opnds[1]; 3660 3661 // Only the inline cache is associated with a register. 3662 assert(Matcher::inline_cache_reg() == OptoReg::Name(R19_num), "ic reg should be R19"); 3663 3664 // Push new nodes. 3665 if (loadConLNodes_IC._large_hi) nodes->push(loadConLNodes_IC._large_hi); 3666 if (loadConLNodes_IC._last) nodes->push(loadConLNodes_IC._last); 3667 nodes->push(call); 3668 %} 3669 3670 // Compound version of call dynamic 3671 // Toc is only passed so that it can be used in ins_encode statement. 3672 // In the code we have to use $constanttablebase. 3673 enc_class enc_java_dynamic_call(method meth, iRegLdst toc) %{ 3674 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 3675 MacroAssembler _masm(&cbuf); 3676 int start_offset = __ offset(); 3677 3678 Register Rtoc = (ra_) ? $constanttablebase : R2_TOC; 3679 #if 0 3680 int vtable_index = this->_vtable_index; 3681 if (_vtable_index < 0) { 3682 // Must be invalid_vtable_index, not nonvirtual_vtable_index. 3683 assert(_vtable_index == Method::invalid_vtable_index, "correct sentinel value"); 3684 Register ic_reg = as_Register(Matcher::inline_cache_reg_encode()); 3685 3686 // Virtual call relocation will point to ic load. 3687 address virtual_call_meta_addr = __ pc(); 3688 // Load a clear inline cache. 3689 AddressLiteral empty_ic((address) Universe::non_oop_word()); 3690 __ load_const_from_method_toc(ic_reg, empty_ic, Rtoc); 3691 // CALL to fixup routine. Fixup routine uses ScopeDesc info 3692 // to determine who we intended to call. 3693 __ relocate(virtual_call_Relocation::spec(virtual_call_meta_addr)); 3694 emit_call_with_trampoline_stub(_masm, (address)$meth$$method, relocInfo::none); 3695 assert(((MachCallDynamicJavaNode*)this)->ret_addr_offset() == __ offset() - start_offset, 3696 "Fix constant in ret_addr_offset()"); 3697 } else { 3698 assert(!UseInlineCaches, "expect vtable calls only if not using ICs"); 3699 // Go thru the vtable. Get receiver klass. Receiver already 3700 // checked for non-null. If we'll go thru a C2I adapter, the 3701 // interpreter expects method in R19_method. 3702 3703 __ load_klass(R11_scratch1, R3); 3704 3705 int entry_offset = InstanceKlass::vtable_start_offset() + _vtable_index * vtableEntry::size(); 3706 int v_off = entry_offset * wordSize + vtableEntry::method_offset_in_bytes(); 3707 __ li(R19_method, v_off); 3708 __ ldx(R19_method/*method oop*/, R19_method/*method offset*/, R11_scratch1/*class*/); 3709 // NOTE: for vtable dispatches, the vtable entry will never be 3710 // null. However it may very well end up in handle_wrong_method 3711 // if the method is abstract for the particular class. 3712 __ ld(R11_scratch1, in_bytes(Method::from_compiled_offset()), R19_method); 3713 // Call target. Either compiled code or C2I adapter. 3714 __ mtctr(R11_scratch1); 3715 __ bctrl(); 3716 if (((MachCallDynamicJavaNode*)this)->ret_addr_offset() != __ offset() - start_offset) { 3717 tty->print(" %d, %d\n", ((MachCallDynamicJavaNode*)this)->ret_addr_offset(),__ offset() - start_offset); 3718 } 3719 assert(((MachCallDynamicJavaNode*)this)->ret_addr_offset() == __ offset() - start_offset, 3720 "Fix constant in ret_addr_offset()"); 3721 } 3722 #endif 3723 Unimplemented(); // ret_addr_offset not yet fixed. Depends on compressed oops (load klass!). 3724 %} 3725 3726 // a runtime call 3727 enc_class enc_java_to_runtime_call (method meth) %{ 3728 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 3729 3730 MacroAssembler _masm(&cbuf); 3731 const address start_pc = __ pc(); 3732 3733 #if defined(ABI_ELFv2) 3734 address entry= !($meth$$method) ? NULL : (address)$meth$$method; 3735 __ call_c(entry, relocInfo::runtime_call_type); 3736 #else 3737 // The function we're going to call. 3738 FunctionDescriptor fdtemp; 3739 const FunctionDescriptor* fd = !($meth$$method) ? &fdtemp : (FunctionDescriptor*)$meth$$method; 3740 3741 Register Rtoc = R12_scratch2; 3742 // Calculate the method's TOC. 3743 __ calculate_address_from_global_toc(Rtoc, __ method_toc()); 3744 // Put entry, env, toc into the constant pool, this needs up to 3 constant 3745 // pool entries; call_c_using_toc will optimize the call. 3746 __ call_c_using_toc(fd, relocInfo::runtime_call_type, Rtoc); 3747 #endif 3748 3749 // Check the ret_addr_offset. 3750 assert(((MachCallRuntimeNode*)this)->ret_addr_offset() == __ last_calls_return_pc() - start_pc, 3751 "Fix constant in ret_addr_offset()"); 3752 %} 3753 3754 // Move to ctr for leaf call. 3755 // This enc_class is needed so that scheduler gets proper 3756 // input mapping for latency computation. 3757 enc_class enc_leaf_call_mtctr(iRegLsrc src) %{ 3758 // TODO: PPC port $archOpcode(ppc64Opcode_mtctr); 3759 MacroAssembler _masm(&cbuf); 3760 __ mtctr($src$$Register); 3761 %} 3762 3763 // Postalloc expand emitter for runtime leaf calls. 3764 enc_class postalloc_expand_java_to_runtime_call(method meth, iRegLdst toc) %{ 3765 loadConLNodesTuple loadConLNodes_Entry; 3766 #if defined(ABI_ELFv2) 3767 jlong entry_address = (jlong) this->entry_point(); 3768 assert(entry_address, "need address here"); 3769 loadConLNodes_Entry = loadConLNodesTuple_create(C, ra_, n_toc, new (C) immLOper(entry_address), 3770 OptoReg::Name(R12_H_num), OptoReg::Name(R12_num)); 3771 #else 3772 // Get the struct that describes the function we are about to call. 3773 FunctionDescriptor* fd = (FunctionDescriptor*) this->entry_point(); 3774 assert(fd, "need fd here"); 3775 jlong entry_address = (jlong) fd->entry(); 3776 // new nodes 3777 loadConLNodesTuple loadConLNodes_Env; 3778 loadConLNodesTuple loadConLNodes_Toc; 3779 3780 // Create nodes and operands for loading the entry point. 3781 loadConLNodes_Entry = loadConLNodesTuple_create(C, ra_, n_toc, new (C) immLOper(entry_address), 3782 OptoReg::Name(R12_H_num), OptoReg::Name(R12_num)); 3783 3784 3785 // Create nodes and operands for loading the env pointer. 3786 if (fd->env() != NULL) { 3787 loadConLNodes_Env = loadConLNodesTuple_create(C, ra_, n_toc, new (C) immLOper((jlong) fd->env()), 3788 OptoReg::Name(R11_H_num), OptoReg::Name(R11_num)); 3789 } else { 3790 loadConLNodes_Env._large_hi = NULL; 3791 loadConLNodes_Env._large_lo = NULL; 3792 loadConLNodes_Env._small = NULL; 3793 loadConLNodes_Env._last = new (C) loadConL16Node(); 3794 loadConLNodes_Env._last->_opnds[0] = new (C) iRegLdstOper(); 3795 loadConLNodes_Env._last->_opnds[1] = new (C) immL16Oper(0); 3796 ra_->set_pair(loadConLNodes_Env._last->_idx, OptoReg::Name(R11_H_num), OptoReg::Name(R11_num)); 3797 } 3798 3799 // Create nodes and operands for loading the Toc point. 3800 loadConLNodes_Toc = loadConLNodesTuple_create(C, ra_, n_toc, new (C) immLOper((jlong) fd->toc()), 3801 OptoReg::Name(R2_H_num), OptoReg::Name(R2_num)); 3802 #endif // ABI_ELFv2 3803 // mtctr node 3804 MachNode *mtctr = new (C) CallLeafDirect_mtctrNode(); 3805 3806 assert(loadConLNodes_Entry._last != NULL, "entry must exist"); 3807 mtctr->add_req(0, loadConLNodes_Entry._last); 3808 3809 mtctr->_opnds[0] = new (C) iRegLdstOper(); 3810 mtctr->_opnds[1] = new (C) iRegLdstOper(); 3811 3812 // call node 3813 MachCallLeafNode *call = new (C) CallLeafDirectNode(); 3814 3815 call->_opnds[0] = _opnds[0]; 3816 call->_opnds[1] = new (C) methodOper((intptr_t) entry_address); // May get set later. 3817 3818 // Make the new call node look like the old one. 3819 call->_name = _name; 3820 call->_tf = _tf; 3821 call->_entry_point = _entry_point; 3822 call->_cnt = _cnt; 3823 call->_argsize = _argsize; 3824 call->_oop_map = _oop_map; 3825 guarantee(!_jvms, "You must clone the jvms and adapt the offsets by fix_jvms()."); 3826 call->_jvms = NULL; 3827 call->_jvmadj = _jvmadj; 3828 call->_in_rms = _in_rms; 3829 call->_nesting = _nesting; 3830 3831 3832 // New call needs all inputs of old call. 3833 // Req... 3834 for (uint i = 0; i < req(); ++i) { 3835 if (i != mach_constant_base_node_input()) { 3836 call->add_req(in(i)); 3837 } 3838 } 3839 3840 // These must be reqired edges, as the registers are live up to 3841 // the call. Else the constants are handled as kills. 3842 call->add_req(mtctr); 3843 #if !defined(ABI_ELFv2) 3844 call->add_req(loadConLNodes_Env._last); 3845 call->add_req(loadConLNodes_Toc._last); 3846 #endif 3847 3848 // ...as well as prec 3849 for (uint i = req(); i < len(); ++i) { 3850 call->add_prec(in(i)); 3851 } 3852 3853 // registers 3854 ra_->set1(mtctr->_idx, OptoReg::Name(SR_CTR_num)); 3855 3856 // Insert the new nodes. 3857 if (loadConLNodes_Entry._large_hi) nodes->push(loadConLNodes_Entry._large_hi); 3858 if (loadConLNodes_Entry._last) nodes->push(loadConLNodes_Entry._last); 3859 #if !defined(ABI_ELFv2) 3860 if (loadConLNodes_Env._large_hi) nodes->push(loadConLNodes_Env._large_hi); 3861 if (loadConLNodes_Env._last) nodes->push(loadConLNodes_Env._last); 3862 if (loadConLNodes_Toc._large_hi) nodes->push(loadConLNodes_Toc._large_hi); 3863 if (loadConLNodes_Toc._last) nodes->push(loadConLNodes_Toc._last); 3864 #endif 3865 nodes->push(mtctr); 3866 nodes->push(call); 3867 %} 3868 %} 3869 3870 //----------FRAME-------------------------------------------------------------- 3871 // Definition of frame structure and management information. 3872 3873 frame %{ 3874 // What direction does stack grow in (assumed to be same for native & Java). 3875 stack_direction(TOWARDS_LOW); 3876 3877 // These two registers define part of the calling convention between 3878 // compiled code and the interpreter. 3879 3880 // Inline Cache Register or method for I2C. 3881 inline_cache_reg(R19); // R19_method 3882 3883 // Method Oop Register when calling interpreter. 3884 interpreter_method_oop_reg(R19); // R19_method 3885 3886 // Optional: name the operand used by cisc-spilling to access 3887 // [stack_pointer + offset]. 3888 cisc_spilling_operand_name(indOffset); 3889 3890 // Number of stack slots consumed by a Monitor enter. 3891 sync_stack_slots((frame::jit_monitor_size / VMRegImpl::stack_slot_size)); 3892 3893 // Compiled code's Frame Pointer. 3894 frame_pointer(R1); // R1_SP 3895 3896 // Interpreter stores its frame pointer in a register which is 3897 // stored to the stack by I2CAdaptors. I2CAdaptors convert from 3898 // interpreted java to compiled java. 3899 // 3900 // R14_state holds pointer to caller's cInterpreter. 3901 interpreter_frame_pointer(R14); // R14_state 3902 3903 stack_alignment(frame::alignment_in_bytes); 3904 3905 in_preserve_stack_slots((frame::jit_in_preserve_size / VMRegImpl::stack_slot_size)); 3906 3907 // Number of outgoing stack slots killed above the 3908 // out_preserve_stack_slots for calls to C. Supports the var-args 3909 // backing area for register parms. 3910 // 3911 varargs_C_out_slots_killed(((frame::abi_reg_args_size - frame::jit_out_preserve_size) / VMRegImpl::stack_slot_size)); 3912 3913 // The after-PROLOG location of the return address. Location of 3914 // return address specifies a type (REG or STACK) and a number 3915 // representing the register number (i.e. - use a register name) or 3916 // stack slot. 3917 // 3918 // A: Link register is stored in stack slot ... 3919 // M: ... but it's in the caller's frame according to PPC-64 ABI. 3920 // J: Therefore, we make sure that the link register is also in R11_scratch1 3921 // at the end of the prolog. 3922 // B: We use R20, now. 3923 //return_addr(REG R20); 3924 3925 // G: After reading the comments made by all the luminaries on their 3926 // failure to tell the compiler where the return address really is, 3927 // I hardly dare to try myself. However, I'm convinced it's in slot 3928 // 4 what apparently works and saves us some spills. 3929 return_addr(STACK 4); 3930 3931 // This is the body of the function 3932 // 3933 // void Matcher::calling_convention(OptoRegPair* sig, // array of ideal regs 3934 // uint length, // length of array 3935 // bool is_outgoing) 3936 // 3937 // The `sig' array is to be updated. sig[j] represents the location 3938 // of the j-th argument, either a register or a stack slot. 3939 3940 // Comment taken from i486.ad: 3941 // Body of function which returns an integer array locating 3942 // arguments either in registers or in stack slots. Passed an array 3943 // of ideal registers called "sig" and a "length" count. Stack-slot 3944 // offsets are based on outgoing arguments, i.e. a CALLER setting up 3945 // arguments for a CALLEE. Incoming stack arguments are 3946 // automatically biased by the preserve_stack_slots field above. 3947 calling_convention %{ 3948 // No difference between ingoing/outgoing. Just pass false. 3949 SharedRuntime::java_calling_convention(sig_bt, regs, length, false); 3950 %} 3951 3952 // Comment taken from i486.ad: 3953 // Body of function which returns an integer array locating 3954 // arguments either in registers or in stack slots. Passed an array 3955 // of ideal registers called "sig" and a "length" count. Stack-slot 3956 // offsets are based on outgoing arguments, i.e. a CALLER setting up 3957 // arguments for a CALLEE. Incoming stack arguments are 3958 // automatically biased by the preserve_stack_slots field above. 3959 c_calling_convention %{ 3960 // This is obviously always outgoing. 3961 // C argument in register AND stack slot. 3962 (void) SharedRuntime::c_calling_convention(sig_bt, regs, /*regs2=*/NULL, length); 3963 %} 3964 3965 // Location of native (C/C++) and interpreter return values. This 3966 // is specified to be the same as Java. In the 32-bit VM, long 3967 // values are actually returned from native calls in O0:O1 and 3968 // returned to the interpreter in I0:I1. The copying to and from 3969 // the register pairs is done by the appropriate call and epilog 3970 // opcodes. This simplifies the register allocator. 3971 c_return_value %{ 3972 assert((ideal_reg >= Op_RegI && ideal_reg <= Op_RegL) || 3973 (ideal_reg == Op_RegN && Universe::narrow_oop_base() == NULL && Universe::narrow_oop_shift() == 0), 3974 "only return normal values"); 3975 // enum names from opcodes.hpp: Op_Node Op_Set Op_RegN Op_RegI Op_RegP Op_RegF Op_RegD Op_RegL 3976 static int typeToRegLo[Op_RegL+1] = { 0, 0, R3_num, R3_num, R3_num, F1_num, F1_num, R3_num }; 3977 static int typeToRegHi[Op_RegL+1] = { 0, 0, OptoReg::Bad, R3_H_num, R3_H_num, OptoReg::Bad, F1_H_num, R3_H_num }; 3978 return OptoRegPair(typeToRegHi[ideal_reg], typeToRegLo[ideal_reg]); 3979 %} 3980 3981 // Location of compiled Java return values. Same as C 3982 return_value %{ 3983 assert((ideal_reg >= Op_RegI && ideal_reg <= Op_RegL) || 3984 (ideal_reg == Op_RegN && Universe::narrow_oop_base() == NULL && Universe::narrow_oop_shift() == 0), 3985 "only return normal values"); 3986 // enum names from opcodes.hpp: Op_Node Op_Set Op_RegN Op_RegI Op_RegP Op_RegF Op_RegD Op_RegL 3987 static int typeToRegLo[Op_RegL+1] = { 0, 0, R3_num, R3_num, R3_num, F1_num, F1_num, R3_num }; 3988 static int typeToRegHi[Op_RegL+1] = { 0, 0, OptoReg::Bad, R3_H_num, R3_H_num, OptoReg::Bad, F1_H_num, R3_H_num }; 3989 return OptoRegPair(typeToRegHi[ideal_reg], typeToRegLo[ideal_reg]); 3990 %} 3991 %} 3992 3993 3994 //----------ATTRIBUTES--------------------------------------------------------- 3995 3996 //----------Operand Attributes------------------------------------------------- 3997 op_attrib op_cost(1); // Required cost attribute. 3998 3999 //----------Instruction Attributes--------------------------------------------- 4000 4001 // Cost attribute. required. 4002 ins_attrib ins_cost(DEFAULT_COST); 4003 4004 // Is this instruction a non-matching short branch variant of some 4005 // long branch? Not required. 4006 ins_attrib ins_short_branch(0); 4007 4008 ins_attrib ins_is_TrapBasedCheckNode(true); 4009 4010 // Number of constants. 4011 // This instruction uses the given number of constants 4012 // (optional attribute). 4013 // This is needed to determine in time whether the constant pool will 4014 // exceed 4000 entries. Before postalloc_expand the overall number of constants 4015 // is determined. It's also used to compute the constant pool size 4016 // in Output(). 4017 ins_attrib ins_num_consts(0); 4018 4019 // Required alignment attribute (must be a power of 2) specifies the 4020 // alignment that some part of the instruction (not necessarily the 4021 // start) requires. If > 1, a compute_padding() function must be 4022 // provided for the instruction. 4023 ins_attrib ins_alignment(1); 4024 4025 // Enforce/prohibit rematerializations. 4026 // - If an instruction is attributed with 'ins_cannot_rematerialize(true)' 4027 // then rematerialization of that instruction is prohibited and the 4028 // instruction's value will be spilled if necessary. 4029 // Causes that MachNode::rematerialize() returns false. 4030 // - If an instruction is attributed with 'ins_should_rematerialize(true)' 4031 // then rematerialization should be enforced and a copy of the instruction 4032 // should be inserted if possible; rematerialization is not guaranteed. 4033 // Note: this may result in rematerializations in front of every use. 4034 // Causes that MachNode::rematerialize() can return true. 4035 // (optional attribute) 4036 ins_attrib ins_cannot_rematerialize(false); 4037 ins_attrib ins_should_rematerialize(false); 4038 4039 // Instruction has variable size depending on alignment. 4040 ins_attrib ins_variable_size_depending_on_alignment(false); 4041 4042 // Instruction is a nop. 4043 ins_attrib ins_is_nop(false); 4044 4045 // Instruction is mapped to a MachIfFastLock node (instead of MachFastLock). 4046 ins_attrib ins_use_mach_if_fast_lock_node(false); 4047 4048 // Field for the toc offset of a constant. 4049 // 4050 // This is needed if the toc offset is not encodable as an immediate in 4051 // the PPC load instruction. If so, the upper (hi) bits of the offset are 4052 // added to the toc, and from this a load with immediate is performed. 4053 // With postalloc expand, we get two nodes that require the same offset 4054 // but which don't know about each other. The offset is only known 4055 // when the constant is added to the constant pool during emitting. 4056 // It is generated in the 'hi'-node adding the upper bits, and saved 4057 // in this node. The 'lo'-node has a link to the 'hi'-node and reads 4058 // the offset from there when it gets encoded. 4059 ins_attrib ins_field_const_toc_offset(0); 4060 ins_attrib ins_field_const_toc_offset_hi_node(0); 4061 4062 // A field that can hold the instructions offset in the code buffer. 4063 // Set in the nodes emitter. 4064 ins_attrib ins_field_cbuf_insts_offset(-1); 4065 4066 // Fields for referencing a call's load-IC-node. 4067 // If the toc offset can not be encoded as an immediate in a load, we 4068 // use two nodes. 4069 ins_attrib ins_field_load_ic_hi_node(0); 4070 ins_attrib ins_field_load_ic_node(0); 4071 4072 //----------OPERANDS----------------------------------------------------------- 4073 // Operand definitions must precede instruction definitions for correct 4074 // parsing in the ADLC because operands constitute user defined types 4075 // which are used in instruction definitions. 4076 // 4077 // Formats are generated automatically for constants and base registers. 4078 4079 //----------Simple Operands---------------------------------------------------- 4080 // Immediate Operands 4081 4082 // Integer Immediate: 32-bit 4083 operand immI() %{ 4084 match(ConI); 4085 op_cost(40); 4086 format %{ %} 4087 interface(CONST_INTER); 4088 %} 4089 4090 operand immI8() %{ 4091 predicate(Assembler::is_simm(n->get_int(), 8)); 4092 op_cost(0); 4093 match(ConI); 4094 format %{ %} 4095 interface(CONST_INTER); 4096 %} 4097 4098 // Integer Immediate: 16-bit 4099 operand immI16() %{ 4100 predicate(Assembler::is_simm(n->get_int(), 16)); 4101 op_cost(0); 4102 match(ConI); 4103 format %{ %} 4104 interface(CONST_INTER); 4105 %} 4106 4107 // Integer Immediate: 32-bit, where lowest 16 bits are 0x0000. 4108 operand immIhi16() %{ 4109 predicate(((n->get_int() & 0xffff0000) != 0) && ((n->get_int() & 0xffff) == 0)); 4110 match(ConI); 4111 op_cost(0); 4112 format %{ %} 4113 interface(CONST_INTER); 4114 %} 4115 4116 operand immInegpow2() %{ 4117 predicate(is_power_of_2_long((jlong) (julong) (juint) (-(n->get_int())))); 4118 match(ConI); 4119 op_cost(0); 4120 format %{ %} 4121 interface(CONST_INTER); 4122 %} 4123 4124 operand immIpow2minus1() %{ 4125 predicate(is_power_of_2_long((((jlong) (n->get_int()))+1))); 4126 match(ConI); 4127 op_cost(0); 4128 format %{ %} 4129 interface(CONST_INTER); 4130 %} 4131 4132 operand immIpowerOf2() %{ 4133 predicate(is_power_of_2_long((((jlong) (julong) (juint) (n->get_int()))))); 4134 match(ConI); 4135 op_cost(0); 4136 format %{ %} 4137 interface(CONST_INTER); 4138 %} 4139 4140 // Unsigned Integer Immediate: the values 0-31 4141 operand uimmI5() %{ 4142 predicate(Assembler::is_uimm(n->get_int(), 5)); 4143 match(ConI); 4144 op_cost(0); 4145 format %{ %} 4146 interface(CONST_INTER); 4147 %} 4148 4149 // Unsigned Integer Immediate: 6-bit 4150 operand uimmI6() %{ 4151 predicate(Assembler::is_uimm(n->get_int(), 6)); 4152 match(ConI); 4153 op_cost(0); 4154 format %{ %} 4155 interface(CONST_INTER); 4156 %} 4157 4158 // Unsigned Integer Immediate: 6-bit int, greater than 32 4159 operand uimmI6_ge32() %{ 4160 predicate(Assembler::is_uimm(n->get_int(), 6) && n->get_int() >= 32); 4161 match(ConI); 4162 op_cost(0); 4163 format %{ %} 4164 interface(CONST_INTER); 4165 %} 4166 4167 // Unsigned Integer Immediate: 15-bit 4168 operand uimmI15() %{ 4169 predicate(Assembler::is_uimm(n->get_int(), 15)); 4170 match(ConI); 4171 op_cost(0); 4172 format %{ %} 4173 interface(CONST_INTER); 4174 %} 4175 4176 // Unsigned Integer Immediate: 16-bit 4177 operand uimmI16() %{ 4178 predicate(Assembler::is_uimm(n->get_int(), 16)); 4179 match(ConI); 4180 op_cost(0); 4181 format %{ %} 4182 interface(CONST_INTER); 4183 %} 4184 4185 // constant 'int 0'. 4186 operand immI_0() %{ 4187 predicate(n->get_int() == 0); 4188 match(ConI); 4189 op_cost(0); 4190 format %{ %} 4191 interface(CONST_INTER); 4192 %} 4193 4194 // constant 'int 1'. 4195 operand immI_1() %{ 4196 predicate(n->get_int() == 1); 4197 match(ConI); 4198 op_cost(0); 4199 format %{ %} 4200 interface(CONST_INTER); 4201 %} 4202 4203 // constant 'int -1'. 4204 operand immI_minus1() %{ 4205 predicate(n->get_int() == -1); 4206 match(ConI); 4207 op_cost(0); 4208 format %{ %} 4209 interface(CONST_INTER); 4210 %} 4211 4212 // int value 16. 4213 operand immI_16() %{ 4214 predicate(n->get_int() == 16); 4215 match(ConI); 4216 op_cost(0); 4217 format %{ %} 4218 interface(CONST_INTER); 4219 %} 4220 4221 // int value 24. 4222 operand immI_24() %{ 4223 predicate(n->get_int() == 24); 4224 match(ConI); 4225 op_cost(0); 4226 format %{ %} 4227 interface(CONST_INTER); 4228 %} 4229 4230 // Compressed oops constants 4231 // Pointer Immediate 4232 operand immN() %{ 4233 match(ConN); 4234 4235 op_cost(10); 4236 format %{ %} 4237 interface(CONST_INTER); 4238 %} 4239 4240 // NULL Pointer Immediate 4241 operand immN_0() %{ 4242 predicate(n->get_narrowcon() == 0); 4243 match(ConN); 4244 4245 op_cost(0); 4246 format %{ %} 4247 interface(CONST_INTER); 4248 %} 4249 4250 // Compressed klass constants 4251 operand immNKlass() %{ 4252 match(ConNKlass); 4253 4254 op_cost(0); 4255 format %{ %} 4256 interface(CONST_INTER); 4257 %} 4258 4259 // This operand can be used to avoid matching of an instruct 4260 // with chain rule. 4261 operand immNKlass_NM() %{ 4262 match(ConNKlass); 4263 predicate(false); 4264 op_cost(0); 4265 format %{ %} 4266 interface(CONST_INTER); 4267 %} 4268 4269 // Pointer Immediate: 64-bit 4270 operand immP() %{ 4271 match(ConP); 4272 op_cost(0); 4273 format %{ %} 4274 interface(CONST_INTER); 4275 %} 4276 4277 // Operand to avoid match of loadConP. 4278 // This operand can be used to avoid matching of an instruct 4279 // with chain rule. 4280 operand immP_NM() %{ 4281 match(ConP); 4282 predicate(false); 4283 op_cost(0); 4284 format %{ %} 4285 interface(CONST_INTER); 4286 %} 4287 4288 // costant 'pointer 0'. 4289 operand immP_0() %{ 4290 predicate(n->get_ptr() == 0); 4291 match(ConP); 4292 op_cost(0); 4293 format %{ %} 4294 interface(CONST_INTER); 4295 %} 4296 4297 // pointer 0x0 or 0x1 4298 operand immP_0or1() %{ 4299 predicate((n->get_ptr() == 0) || (n->get_ptr() == 1)); 4300 match(ConP); 4301 op_cost(0); 4302 format %{ %} 4303 interface(CONST_INTER); 4304 %} 4305 4306 operand immL() %{ 4307 match(ConL); 4308 op_cost(40); 4309 format %{ %} 4310 interface(CONST_INTER); 4311 %} 4312 4313 // Long Immediate: 16-bit 4314 operand immL16() %{ 4315 predicate(Assembler::is_simm(n->get_long(), 16)); 4316 match(ConL); 4317 op_cost(0); 4318 format %{ %} 4319 interface(CONST_INTER); 4320 %} 4321 4322 // Long Immediate: 16-bit, 4-aligned 4323 operand immL16Alg4() %{ 4324 predicate(Assembler::is_simm(n->get_long(), 16) && ((n->get_long() & 0x3) == 0)); 4325 match(ConL); 4326 op_cost(0); 4327 format %{ %} 4328 interface(CONST_INTER); 4329 %} 4330 4331 // Long Immediate: 32-bit, where lowest 16 bits are 0x0000. 4332 operand immL32hi16() %{ 4333 predicate(Assembler::is_simm(n->get_long(), 32) && ((n->get_long() & 0xffffL) == 0L)); 4334 match(ConL); 4335 op_cost(0); 4336 format %{ %} 4337 interface(CONST_INTER); 4338 %} 4339 4340 // Long Immediate: 32-bit 4341 operand immL32() %{ 4342 predicate(Assembler::is_simm(n->get_long(), 32)); 4343 match(ConL); 4344 op_cost(0); 4345 format %{ %} 4346 interface(CONST_INTER); 4347 %} 4348 4349 // Long Immediate: 64-bit, where highest 16 bits are not 0x0000. 4350 operand immLhighest16() %{ 4351 predicate((n->get_long() & 0xffff000000000000L) != 0L && (n->get_long() & 0x0000ffffffffffffL) == 0L); 4352 match(ConL); 4353 op_cost(0); 4354 format %{ %} 4355 interface(CONST_INTER); 4356 %} 4357 4358 operand immLnegpow2() %{ 4359 predicate(is_power_of_2_long((jlong)-(n->get_long()))); 4360 match(ConL); 4361 op_cost(0); 4362 format %{ %} 4363 interface(CONST_INTER); 4364 %} 4365 4366 operand immLpow2minus1() %{ 4367 predicate(is_power_of_2_long((((jlong) (n->get_long()))+1)) && 4368 (n->get_long() != (jlong)0xffffffffffffffffL)); 4369 match(ConL); 4370 op_cost(0); 4371 format %{ %} 4372 interface(CONST_INTER); 4373 %} 4374 4375 // constant 'long 0'. 4376 operand immL_0() %{ 4377 predicate(n->get_long() == 0L); 4378 match(ConL); 4379 op_cost(0); 4380 format %{ %} 4381 interface(CONST_INTER); 4382 %} 4383 4384 // constat ' long -1'. 4385 operand immL_minus1() %{ 4386 predicate(n->get_long() == -1L); 4387 match(ConL); 4388 op_cost(0); 4389 format %{ %} 4390 interface(CONST_INTER); 4391 %} 4392 4393 // Long Immediate: low 32-bit mask 4394 operand immL_32bits() %{ 4395 predicate(n->get_long() == 0xFFFFFFFFL); 4396 match(ConL); 4397 op_cost(0); 4398 format %{ %} 4399 interface(CONST_INTER); 4400 %} 4401 4402 // Unsigned Long Immediate: 16-bit 4403 operand uimmL16() %{ 4404 predicate(Assembler::is_uimm(n->get_long(), 16)); 4405 match(ConL); 4406 op_cost(0); 4407 format %{ %} 4408 interface(CONST_INTER); 4409 %} 4410 4411 // Float Immediate 4412 operand immF() %{ 4413 match(ConF); 4414 op_cost(40); 4415 format %{ %} 4416 interface(CONST_INTER); 4417 %} 4418 4419 // constant 'float +0.0'. 4420 operand immF_0() %{ 4421 predicate((n->getf() == 0) && 4422 (fpclassify(n->getf()) == FP_ZERO) && (signbit(n->getf()) == 0)); 4423 match(ConF); 4424 op_cost(0); 4425 format %{ %} 4426 interface(CONST_INTER); 4427 %} 4428 4429 // Double Immediate 4430 operand immD() %{ 4431 match(ConD); 4432 op_cost(40); 4433 format %{ %} 4434 interface(CONST_INTER); 4435 %} 4436 4437 // Integer Register Operands 4438 // Integer Destination Register 4439 // See definition of reg_class bits32_reg_rw. 4440 operand iRegIdst() %{ 4441 constraint(ALLOC_IN_RC(bits32_reg_rw)); 4442 match(RegI); 4443 match(rscratch1RegI); 4444 match(rscratch2RegI); 4445 match(rarg1RegI); 4446 match(rarg2RegI); 4447 match(rarg3RegI); 4448 match(rarg4RegI); 4449 format %{ %} 4450 interface(REG_INTER); 4451 %} 4452 4453 // Integer Source Register 4454 // See definition of reg_class bits32_reg_ro. 4455 operand iRegIsrc() %{ 4456 constraint(ALLOC_IN_RC(bits32_reg_ro)); 4457 match(RegI); 4458 match(rscratch1RegI); 4459 match(rscratch2RegI); 4460 match(rarg1RegI); 4461 match(rarg2RegI); 4462 match(rarg3RegI); 4463 match(rarg4RegI); 4464 format %{ %} 4465 interface(REG_INTER); 4466 %} 4467 4468 operand rscratch1RegI() %{ 4469 constraint(ALLOC_IN_RC(rscratch1_bits32_reg)); 4470 match(iRegIdst); 4471 format %{ %} 4472 interface(REG_INTER); 4473 %} 4474 4475 operand rscratch2RegI() %{ 4476 constraint(ALLOC_IN_RC(rscratch2_bits32_reg)); 4477 match(iRegIdst); 4478 format %{ %} 4479 interface(REG_INTER); 4480 %} 4481 4482 operand rarg1RegI() %{ 4483 constraint(ALLOC_IN_RC(rarg1_bits32_reg)); 4484 match(iRegIdst); 4485 format %{ %} 4486 interface(REG_INTER); 4487 %} 4488 4489 operand rarg2RegI() %{ 4490 constraint(ALLOC_IN_RC(rarg2_bits32_reg)); 4491 match(iRegIdst); 4492 format %{ %} 4493 interface(REG_INTER); 4494 %} 4495 4496 operand rarg3RegI() %{ 4497 constraint(ALLOC_IN_RC(rarg3_bits32_reg)); 4498 match(iRegIdst); 4499 format %{ %} 4500 interface(REG_INTER); 4501 %} 4502 4503 operand rarg4RegI() %{ 4504 constraint(ALLOC_IN_RC(rarg4_bits32_reg)); 4505 match(iRegIdst); 4506 format %{ %} 4507 interface(REG_INTER); 4508 %} 4509 4510 operand rarg1RegL() %{ 4511 constraint(ALLOC_IN_RC(rarg1_bits64_reg)); 4512 match(iRegLdst); 4513 format %{ %} 4514 interface(REG_INTER); 4515 %} 4516 4517 operand rarg2RegL() %{ 4518 constraint(ALLOC_IN_RC(rarg2_bits64_reg)); 4519 match(iRegLdst); 4520 format %{ %} 4521 interface(REG_INTER); 4522 %} 4523 4524 operand rarg3RegL() %{ 4525 constraint(ALLOC_IN_RC(rarg3_bits64_reg)); 4526 match(iRegLdst); 4527 format %{ %} 4528 interface(REG_INTER); 4529 %} 4530 4531 operand rarg4RegL() %{ 4532 constraint(ALLOC_IN_RC(rarg4_bits64_reg)); 4533 match(iRegLdst); 4534 format %{ %} 4535 interface(REG_INTER); 4536 %} 4537 4538 // Pointer Destination Register 4539 // See definition of reg_class bits64_reg_rw. 4540 operand iRegPdst() %{ 4541 constraint(ALLOC_IN_RC(bits64_reg_rw)); 4542 match(RegP); 4543 match(rscratch1RegP); 4544 match(rscratch2RegP); 4545 match(rarg1RegP); 4546 match(rarg2RegP); 4547 match(rarg3RegP); 4548 match(rarg4RegP); 4549 format %{ %} 4550 interface(REG_INTER); 4551 %} 4552 4553 // Pointer Destination Register 4554 // Operand not using r11 and r12 (killed in epilog). 4555 operand iRegPdstNoScratch() %{ 4556 constraint(ALLOC_IN_RC(bits64_reg_leaf_call)); 4557 match(RegP); 4558 match(rarg1RegP); 4559 match(rarg2RegP); 4560 match(rarg3RegP); 4561 match(rarg4RegP); 4562 format %{ %} 4563 interface(REG_INTER); 4564 %} 4565 4566 // Pointer Source Register 4567 // See definition of reg_class bits64_reg_ro. 4568 operand iRegPsrc() %{ 4569 constraint(ALLOC_IN_RC(bits64_reg_ro)); 4570 match(RegP); 4571 match(iRegPdst); 4572 match(rscratch1RegP); 4573 match(rscratch2RegP); 4574 match(rarg1RegP); 4575 match(rarg2RegP); 4576 match(rarg3RegP); 4577 match(rarg4RegP); 4578 match(threadRegP); 4579 format %{ %} 4580 interface(REG_INTER); 4581 %} 4582 4583 // Thread operand. 4584 operand threadRegP() %{ 4585 constraint(ALLOC_IN_RC(thread_bits64_reg)); 4586 match(iRegPdst); 4587 format %{ "R16" %} 4588 interface(REG_INTER); 4589 %} 4590 4591 operand rscratch1RegP() %{ 4592 constraint(ALLOC_IN_RC(rscratch1_bits64_reg)); 4593 match(iRegPdst); 4594 format %{ "R11" %} 4595 interface(REG_INTER); 4596 %} 4597 4598 operand rscratch2RegP() %{ 4599 constraint(ALLOC_IN_RC(rscratch2_bits64_reg)); 4600 match(iRegPdst); 4601 format %{ %} 4602 interface(REG_INTER); 4603 %} 4604 4605 operand rarg1RegP() %{ 4606 constraint(ALLOC_IN_RC(rarg1_bits64_reg)); 4607 match(iRegPdst); 4608 format %{ %} 4609 interface(REG_INTER); 4610 %} 4611 4612 operand rarg2RegP() %{ 4613 constraint(ALLOC_IN_RC(rarg2_bits64_reg)); 4614 match(iRegPdst); 4615 format %{ %} 4616 interface(REG_INTER); 4617 %} 4618 4619 operand rarg3RegP() %{ 4620 constraint(ALLOC_IN_RC(rarg3_bits64_reg)); 4621 match(iRegPdst); 4622 format %{ %} 4623 interface(REG_INTER); 4624 %} 4625 4626 operand rarg4RegP() %{ 4627 constraint(ALLOC_IN_RC(rarg4_bits64_reg)); 4628 match(iRegPdst); 4629 format %{ %} 4630 interface(REG_INTER); 4631 %} 4632 4633 operand iRegNsrc() %{ 4634 constraint(ALLOC_IN_RC(bits32_reg_ro)); 4635 match(RegN); 4636 match(iRegNdst); 4637 4638 format %{ %} 4639 interface(REG_INTER); 4640 %} 4641 4642 operand iRegNdst() %{ 4643 constraint(ALLOC_IN_RC(bits32_reg_rw)); 4644 match(RegN); 4645 4646 format %{ %} 4647 interface(REG_INTER); 4648 %} 4649 4650 // Long Destination Register 4651 // See definition of reg_class bits64_reg_rw. 4652 operand iRegLdst() %{ 4653 constraint(ALLOC_IN_RC(bits64_reg_rw)); 4654 match(RegL); 4655 match(rscratch1RegL); 4656 match(rscratch2RegL); 4657 format %{ %} 4658 interface(REG_INTER); 4659 %} 4660 4661 // Long Source Register 4662 // See definition of reg_class bits64_reg_ro. 4663 operand iRegLsrc() %{ 4664 constraint(ALLOC_IN_RC(bits64_reg_ro)); 4665 match(RegL); 4666 match(iRegLdst); 4667 match(rscratch1RegL); 4668 match(rscratch2RegL); 4669 format %{ %} 4670 interface(REG_INTER); 4671 %} 4672 4673 // Special operand for ConvL2I. 4674 operand iRegL2Isrc(iRegLsrc reg) %{ 4675 constraint(ALLOC_IN_RC(bits64_reg_ro)); 4676 match(ConvL2I reg); 4677 format %{ "ConvL2I($reg)" %} 4678 interface(REG_INTER) 4679 %} 4680 4681 operand rscratch1RegL() %{ 4682 constraint(ALLOC_IN_RC(rscratch1_bits64_reg)); 4683 match(RegL); 4684 format %{ %} 4685 interface(REG_INTER); 4686 %} 4687 4688 operand rscratch2RegL() %{ 4689 constraint(ALLOC_IN_RC(rscratch2_bits64_reg)); 4690 match(RegL); 4691 format %{ %} 4692 interface(REG_INTER); 4693 %} 4694 4695 // Condition Code Flag Registers 4696 operand flagsReg() %{ 4697 constraint(ALLOC_IN_RC(int_flags)); 4698 match(RegFlags); 4699 format %{ %} 4700 interface(REG_INTER); 4701 %} 4702 4703 // Condition Code Flag Register CR0 4704 operand flagsRegCR0() %{ 4705 constraint(ALLOC_IN_RC(int_flags_CR0)); 4706 match(RegFlags); 4707 format %{ "CR0" %} 4708 interface(REG_INTER); 4709 %} 4710 4711 operand flagsRegCR1() %{ 4712 constraint(ALLOC_IN_RC(int_flags_CR1)); 4713 match(RegFlags); 4714 format %{ "CR1" %} 4715 interface(REG_INTER); 4716 %} 4717 4718 operand flagsRegCR6() %{ 4719 constraint(ALLOC_IN_RC(int_flags_CR6)); 4720 match(RegFlags); 4721 format %{ "CR6" %} 4722 interface(REG_INTER); 4723 %} 4724 4725 operand regCTR() %{ 4726 constraint(ALLOC_IN_RC(ctr_reg)); 4727 // RegFlags should work. Introducing a RegSpecial type would cause a 4728 // lot of changes. 4729 match(RegFlags); 4730 format %{"SR_CTR" %} 4731 interface(REG_INTER); 4732 %} 4733 4734 operand regD() %{ 4735 constraint(ALLOC_IN_RC(dbl_reg)); 4736 match(RegD); 4737 format %{ %} 4738 interface(REG_INTER); 4739 %} 4740 4741 operand regF() %{ 4742 constraint(ALLOC_IN_RC(flt_reg)); 4743 match(RegF); 4744 format %{ %} 4745 interface(REG_INTER); 4746 %} 4747 4748 // Special Registers 4749 4750 // Method Register 4751 operand inline_cache_regP(iRegPdst reg) %{ 4752 constraint(ALLOC_IN_RC(r19_bits64_reg)); // inline_cache_reg 4753 match(reg); 4754 format %{ %} 4755 interface(REG_INTER); 4756 %} 4757 4758 operand compiler_method_oop_regP(iRegPdst reg) %{ 4759 constraint(ALLOC_IN_RC(rscratch1_bits64_reg)); // compiler_method_oop_reg 4760 match(reg); 4761 format %{ %} 4762 interface(REG_INTER); 4763 %} 4764 4765 operand interpreter_method_oop_regP(iRegPdst reg) %{ 4766 constraint(ALLOC_IN_RC(r19_bits64_reg)); // interpreter_method_oop_reg 4767 match(reg); 4768 format %{ %} 4769 interface(REG_INTER); 4770 %} 4771 4772 // Operands to remove register moves in unscaled mode. 4773 // Match read/write registers with an EncodeP node if neither shift nor add are required. 4774 operand iRegP2N(iRegPsrc reg) %{ 4775 predicate(false /* TODO: PPC port MatchDecodeNodes*/&& Universe::narrow_oop_shift() == 0); 4776 constraint(ALLOC_IN_RC(bits64_reg_ro)); 4777 match(EncodeP reg); 4778 format %{ "$reg" %} 4779 interface(REG_INTER) 4780 %} 4781 4782 operand iRegN2P(iRegNsrc reg) %{ 4783 predicate(false /* TODO: PPC port MatchDecodeNodes*/); 4784 constraint(ALLOC_IN_RC(bits32_reg_ro)); 4785 match(DecodeN reg); 4786 match(DecodeNKlass reg); 4787 format %{ "$reg" %} 4788 interface(REG_INTER) 4789 %} 4790 4791 //----------Complex Operands--------------------------------------------------- 4792 // Indirect Memory Reference 4793 operand indirect(iRegPsrc reg) %{ 4794 constraint(ALLOC_IN_RC(bits64_reg_ro)); 4795 match(reg); 4796 op_cost(100); 4797 format %{ "[$reg]" %} 4798 interface(MEMORY_INTER) %{ 4799 base($reg); 4800 index(0x0); 4801 scale(0x0); 4802 disp(0x0); 4803 %} 4804 %} 4805 4806 // Indirect with Offset 4807 operand indOffset16(iRegPsrc reg, immL16 offset) %{ 4808 constraint(ALLOC_IN_RC(bits64_reg_ro)); 4809 match(AddP reg offset); 4810 op_cost(100); 4811 format %{ "[$reg + $offset]" %} 4812 interface(MEMORY_INTER) %{ 4813 base($reg); 4814 index(0x0); 4815 scale(0x0); 4816 disp($offset); 4817 %} 4818 %} 4819 4820 // Indirect with 4-aligned Offset 4821 operand indOffset16Alg4(iRegPsrc reg, immL16Alg4 offset) %{ 4822 constraint(ALLOC_IN_RC(bits64_reg_ro)); 4823 match(AddP reg offset); 4824 op_cost(100); 4825 format %{ "[$reg + $offset]" %} 4826 interface(MEMORY_INTER) %{ 4827 base($reg); 4828 index(0x0); 4829 scale(0x0); 4830 disp($offset); 4831 %} 4832 %} 4833 4834 //----------Complex Operands for Compressed OOPs------------------------------- 4835 // Compressed OOPs with narrow_oop_shift == 0. 4836 4837 // Indirect Memory Reference, compressed OOP 4838 operand indirectNarrow(iRegNsrc reg) %{ 4839 predicate(false /* TODO: PPC port MatchDecodeNodes*/); 4840 constraint(ALLOC_IN_RC(bits64_reg_ro)); 4841 match(DecodeN reg); 4842 match(DecodeNKlass reg); 4843 op_cost(100); 4844 format %{ "[$reg]" %} 4845 interface(MEMORY_INTER) %{ 4846 base($reg); 4847 index(0x0); 4848 scale(0x0); 4849 disp(0x0); 4850 %} 4851 %} 4852 4853 // Indirect with Offset, compressed OOP 4854 operand indOffset16Narrow(iRegNsrc reg, immL16 offset) %{ 4855 predicate(false /* TODO: PPC port MatchDecodeNodes*/); 4856 constraint(ALLOC_IN_RC(bits64_reg_ro)); 4857 match(AddP (DecodeN reg) offset); 4858 match(AddP (DecodeNKlass reg) offset); 4859 op_cost(100); 4860 format %{ "[$reg + $offset]" %} 4861 interface(MEMORY_INTER) %{ 4862 base($reg); 4863 index(0x0); 4864 scale(0x0); 4865 disp($offset); 4866 %} 4867 %} 4868 4869 // Indirect with 4-aligned Offset, compressed OOP 4870 operand indOffset16NarrowAlg4(iRegNsrc reg, immL16Alg4 offset) %{ 4871 predicate(false /* TODO: PPC port MatchDecodeNodes*/); 4872 constraint(ALLOC_IN_RC(bits64_reg_ro)); 4873 match(AddP (DecodeN reg) offset); 4874 match(AddP (DecodeNKlass reg) offset); 4875 op_cost(100); 4876 format %{ "[$reg + $offset]" %} 4877 interface(MEMORY_INTER) %{ 4878 base($reg); 4879 index(0x0); 4880 scale(0x0); 4881 disp($offset); 4882 %} 4883 %} 4884 4885 //----------Special Memory Operands-------------------------------------------- 4886 // Stack Slot Operand 4887 // 4888 // This operand is used for loading and storing temporary values on 4889 // the stack where a match requires a value to flow through memory. 4890 operand stackSlotI(sRegI reg) %{ 4891 constraint(ALLOC_IN_RC(stack_slots)); 4892 op_cost(100); 4893 //match(RegI); 4894 format %{ "[sp+$reg]" %} 4895 interface(MEMORY_INTER) %{ 4896 base(0x1); // R1_SP 4897 index(0x0); 4898 scale(0x0); 4899 disp($reg); // Stack Offset 4900 %} 4901 %} 4902 4903 operand stackSlotL(sRegL reg) %{ 4904 constraint(ALLOC_IN_RC(stack_slots)); 4905 op_cost(100); 4906 //match(RegL); 4907 format %{ "[sp+$reg]" %} 4908 interface(MEMORY_INTER) %{ 4909 base(0x1); // R1_SP 4910 index(0x0); 4911 scale(0x0); 4912 disp($reg); // Stack Offset 4913 %} 4914 %} 4915 4916 operand stackSlotP(sRegP reg) %{ 4917 constraint(ALLOC_IN_RC(stack_slots)); 4918 op_cost(100); 4919 //match(RegP); 4920 format %{ "[sp+$reg]" %} 4921 interface(MEMORY_INTER) %{ 4922 base(0x1); // R1_SP 4923 index(0x0); 4924 scale(0x0); 4925 disp($reg); // Stack Offset 4926 %} 4927 %} 4928 4929 operand stackSlotF(sRegF reg) %{ 4930 constraint(ALLOC_IN_RC(stack_slots)); 4931 op_cost(100); 4932 //match(RegF); 4933 format %{ "[sp+$reg]" %} 4934 interface(MEMORY_INTER) %{ 4935 base(0x1); // R1_SP 4936 index(0x0); 4937 scale(0x0); 4938 disp($reg); // Stack Offset 4939 %} 4940 %} 4941 4942 operand stackSlotD(sRegD reg) %{ 4943 constraint(ALLOC_IN_RC(stack_slots)); 4944 op_cost(100); 4945 //match(RegD); 4946 format %{ "[sp+$reg]" %} 4947 interface(MEMORY_INTER) %{ 4948 base(0x1); // R1_SP 4949 index(0x0); 4950 scale(0x0); 4951 disp($reg); // Stack Offset 4952 %} 4953 %} 4954 4955 // Operands for expressing Control Flow 4956 // NOTE: Label is a predefined operand which should not be redefined in 4957 // the AD file. It is generically handled within the ADLC. 4958 4959 //----------Conditional Branch Operands---------------------------------------- 4960 // Comparison Op 4961 // 4962 // This is the operation of the comparison, and is limited to the 4963 // following set of codes: L (<), LE (<=), G (>), GE (>=), E (==), NE 4964 // (!=). 4965 // 4966 // Other attributes of the comparison, such as unsignedness, are specified 4967 // by the comparison instruction that sets a condition code flags register. 4968 // That result is represented by a flags operand whose subtype is appropriate 4969 // to the unsignedness (etc.) of the comparison. 4970 // 4971 // Later, the instruction which matches both the Comparison Op (a Bool) and 4972 // the flags (produced by the Cmp) specifies the coding of the comparison op 4973 // by matching a specific subtype of Bool operand below. 4974 4975 // When used for floating point comparisons: unordered same as less. 4976 operand cmpOp() %{ 4977 match(Bool); 4978 format %{ "" %} 4979 interface(COND_INTER) %{ 4980 // BO only encodes bit 4 of bcondCRbiIsX, as bits 1-3 are always '100'. 4981 // BO & BI 4982 equal(0xA); // 10 10: bcondCRbiIs1 & Condition::equal 4983 not_equal(0x2); // 00 10: bcondCRbiIs0 & Condition::equal 4984 less(0x8); // 10 00: bcondCRbiIs1 & Condition::less 4985 greater_equal(0x0); // 00 00: bcondCRbiIs0 & Condition::less 4986 less_equal(0x1); // 00 01: bcondCRbiIs0 & Condition::greater 4987 greater(0x9); // 10 01: bcondCRbiIs1 & Condition::greater 4988 overflow(0xB); // 10 11: bcondCRbiIs1 & Condition::summary_overflow 4989 no_overflow(0x3); // 00 11: bcondCRbiIs0 & Condition::summary_overflow 4990 %} 4991 %} 4992 4993 //----------OPERAND CLASSES---------------------------------------------------- 4994 // Operand Classes are groups of operands that are used to simplify 4995 // instruction definitions by not requiring the AD writer to specify 4996 // seperate instructions for every form of operand when the 4997 // instruction accepts multiple operand types with the same basic 4998 // encoding and format. The classic case of this is memory operands. 4999 // Indirect is not included since its use is limited to Compare & Swap. 5000 5001 opclass memory(indirect, indOffset16 /*, indIndex, tlsReference*/, indirectNarrow, indOffset16Narrow); 5002 // Memory operand where offsets are 4-aligned. Required for ld, std. 5003 opclass memoryAlg4(indirect, indOffset16Alg4, indirectNarrow, indOffset16NarrowAlg4); 5004 opclass indirectMemory(indirect, indirectNarrow); 5005 5006 // Special opclass for I and ConvL2I. 5007 opclass iRegIsrc_iRegL2Isrc(iRegIsrc, iRegL2Isrc); 5008 5009 // Operand classes to match encode and decode. iRegN_P2N is only used 5010 // for storeN. I have never seen an encode node elsewhere. 5011 opclass iRegN_P2N(iRegNsrc, iRegP2N); 5012 opclass iRegP_N2P(iRegPsrc, iRegN2P); 5013 5014 //----------PIPELINE----------------------------------------------------------- 5015 5016 pipeline %{ 5017 5018 // See J.M.Tendler et al. "Power4 system microarchitecture", IBM 5019 // J. Res. & Dev., No. 1, Jan. 2002. 5020 5021 //----------ATTRIBUTES--------------------------------------------------------- 5022 attributes %{ 5023 5024 // Power4 instructions are of fixed length. 5025 fixed_size_instructions; 5026 5027 // TODO: if `bundle' means number of instructions fetched 5028 // per cycle, this is 8. If `bundle' means Power4 `group', that is 5029 // max instructions issued per cycle, this is 5. 5030 max_instructions_per_bundle = 8; 5031 5032 // A Power4 instruction is 4 bytes long. 5033 instruction_unit_size = 4; 5034 5035 // The Power4 processor fetches 64 bytes... 5036 instruction_fetch_unit_size = 64; 5037 5038 // ...in one line 5039 instruction_fetch_units = 1 5040 5041 // Unused, list one so that array generated by adlc is not empty. 5042 // Aix compiler chokes if _nop_count = 0. 5043 nops(fxNop); 5044 %} 5045 5046 //----------RESOURCES---------------------------------------------------------- 5047 // Resources are the functional units available to the machine 5048 resources( 5049 PPC_BR, // branch unit 5050 PPC_CR, // condition unit 5051 PPC_FX1, // integer arithmetic unit 1 5052 PPC_FX2, // integer arithmetic unit 2 5053 PPC_LDST1, // load/store unit 1 5054 PPC_LDST2, // load/store unit 2 5055 PPC_FP1, // float arithmetic unit 1 5056 PPC_FP2, // float arithmetic unit 2 5057 PPC_LDST = PPC_LDST1 | PPC_LDST2, 5058 PPC_FX = PPC_FX1 | PPC_FX2, 5059 PPC_FP = PPC_FP1 | PPC_FP2 5060 ); 5061 5062 //----------PIPELINE DESCRIPTION----------------------------------------------- 5063 // Pipeline Description specifies the stages in the machine's pipeline 5064 pipe_desc( 5065 // Power4 longest pipeline path 5066 PPC_IF, // instruction fetch 5067 PPC_IC, 5068 //PPC_BP, // branch prediction 5069 PPC_D0, // decode 5070 PPC_D1, // decode 5071 PPC_D2, // decode 5072 PPC_D3, // decode 5073 PPC_Xfer1, 5074 PPC_GD, // group definition 5075 PPC_MP, // map 5076 PPC_ISS, // issue 5077 PPC_RF, // resource fetch 5078 PPC_EX1, // execute (all units) 5079 PPC_EX2, // execute (FP, LDST) 5080 PPC_EX3, // execute (FP, LDST) 5081 PPC_EX4, // execute (FP) 5082 PPC_EX5, // execute (FP) 5083 PPC_EX6, // execute (FP) 5084 PPC_WB, // write back 5085 PPC_Xfer2, 5086 PPC_CP 5087 ); 5088 5089 //----------PIPELINE CLASSES--------------------------------------------------- 5090 // Pipeline Classes describe the stages in which input and output are 5091 // referenced by the hardware pipeline. 5092 5093 // Simple pipeline classes. 5094 5095 // Default pipeline class. 5096 pipe_class pipe_class_default() %{ 5097 single_instruction; 5098 fixed_latency(2); 5099 %} 5100 5101 // Pipeline class for empty instructions. 5102 pipe_class pipe_class_empty() %{ 5103 single_instruction; 5104 fixed_latency(0); 5105 %} 5106 5107 // Pipeline class for compares. 5108 pipe_class pipe_class_compare() %{ 5109 single_instruction; 5110 fixed_latency(16); 5111 %} 5112 5113 // Pipeline class for traps. 5114 pipe_class pipe_class_trap() %{ 5115 single_instruction; 5116 fixed_latency(100); 5117 %} 5118 5119 // Pipeline class for memory operations. 5120 pipe_class pipe_class_memory() %{ 5121 single_instruction; 5122 fixed_latency(16); 5123 %} 5124 5125 // Pipeline class for call. 5126 pipe_class pipe_class_call() %{ 5127 single_instruction; 5128 fixed_latency(100); 5129 %} 5130 5131 // Define the class for the Nop node. 5132 define %{ 5133 MachNop = pipe_class_default; 5134 %} 5135 5136 %} 5137 5138 //----------INSTRUCTIONS------------------------------------------------------- 5139 5140 // Naming of instructions: 5141 // opA_operB / opA_operB_operC: 5142 // Operation 'op' with one or two source operands 'oper'. Result 5143 // type is A, source operand types are B and C. 5144 // Iff A == B == C, B and C are left out. 5145 // 5146 // The instructions are ordered according to the following scheme: 5147 // - loads 5148 // - load constants 5149 // - prefetch 5150 // - store 5151 // - encode/decode 5152 // - membar 5153 // - conditional moves 5154 // - compare & swap 5155 // - arithmetic and logic operations 5156 // * int: Add, Sub, Mul, Div, Mod 5157 // * int: lShift, arShift, urShift, rot 5158 // * float: Add, Sub, Mul, Div 5159 // * and, or, xor ... 5160 // - register moves: float <-> int, reg <-> stack, repl 5161 // - cast (high level type cast, XtoP, castPP, castII, not_null etc. 5162 // - conv (low level type cast requiring bit changes (sign extend etc) 5163 // - compares, range & zero checks. 5164 // - branches 5165 // - complex operations, intrinsics, min, max, replicate 5166 // - lock 5167 // - Calls 5168 // 5169 // If there are similar instructions with different types they are sorted: 5170 // int before float 5171 // small before big 5172 // signed before unsigned 5173 // e.g., loadS before loadUS before loadI before loadF. 5174 5175 5176 //----------Load/Store Instructions-------------------------------------------- 5177 5178 //----------Load Instructions-------------------------------------------------- 5179 5180 // Converts byte to int. 5181 // As convB2I_reg, but without match rule. The match rule of convB2I_reg 5182 // reuses the 'amount' operand, but adlc expects that operand specification 5183 // and operands in match rule are equivalent. 5184 instruct convB2I_reg_2(iRegIdst dst, iRegIsrc src) %{ 5185 effect(DEF dst, USE src); 5186 format %{ "EXTSB $dst, $src \t// byte->int" %} 5187 size(4); 5188 ins_encode %{ 5189 // TODO: PPC port $archOpcode(ppc64Opcode_extsb); 5190 __ extsb($dst$$Register, $src$$Register); 5191 %} 5192 ins_pipe(pipe_class_default); 5193 %} 5194 5195 instruct loadUB_indirect(iRegIdst dst, indirectMemory mem) %{ 5196 // match-rule, false predicate 5197 match(Set dst (LoadB mem)); 5198 predicate(false); 5199 5200 format %{ "LBZ $dst, $mem" %} 5201 size(4); 5202 ins_encode( enc_lbz(dst, mem) ); 5203 ins_pipe(pipe_class_memory); 5204 %} 5205 5206 instruct loadUB_indirect_ac(iRegIdst dst, indirectMemory mem) %{ 5207 // match-rule, false predicate 5208 match(Set dst (LoadB mem)); 5209 predicate(false); 5210 5211 format %{ "LBZ $dst, $mem\n\t" 5212 "TWI $dst\n\t" 5213 "ISYNC" %} 5214 size(12); 5215 ins_encode( enc_lbz_ac(dst, mem) ); 5216 ins_pipe(pipe_class_memory); 5217 %} 5218 5219 // Load Byte (8bit signed). LoadB = LoadUB + ConvUB2B. 5220 instruct loadB_indirect_Ex(iRegIdst dst, indirectMemory mem) %{ 5221 match(Set dst (LoadB mem)); 5222 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n)); 5223 ins_cost(MEMORY_REF_COST + DEFAULT_COST); 5224 expand %{ 5225 iRegIdst tmp; 5226 loadUB_indirect(tmp, mem); 5227 convB2I_reg_2(dst, tmp); 5228 %} 5229 %} 5230 5231 instruct loadB_indirect_ac_Ex(iRegIdst dst, indirectMemory mem) %{ 5232 match(Set dst (LoadB mem)); 5233 ins_cost(3*MEMORY_REF_COST + DEFAULT_COST); 5234 expand %{ 5235 iRegIdst tmp; 5236 loadUB_indirect_ac(tmp, mem); 5237 convB2I_reg_2(dst, tmp); 5238 %} 5239 %} 5240 5241 instruct loadUB_indOffset16(iRegIdst dst, indOffset16 mem) %{ 5242 // match-rule, false predicate 5243 match(Set dst (LoadB mem)); 5244 predicate(false); 5245 5246 format %{ "LBZ $dst, $mem" %} 5247 size(4); 5248 ins_encode( enc_lbz(dst, mem) ); 5249 ins_pipe(pipe_class_memory); 5250 %} 5251 5252 instruct loadUB_indOffset16_ac(iRegIdst dst, indOffset16 mem) %{ 5253 // match-rule, false predicate 5254 match(Set dst (LoadB mem)); 5255 predicate(false); 5256 5257 format %{ "LBZ $dst, $mem\n\t" 5258 "TWI $dst\n\t" 5259 "ISYNC" %} 5260 size(12); 5261 ins_encode( enc_lbz_ac(dst, mem) ); 5262 ins_pipe(pipe_class_memory); 5263 %} 5264 5265 // Load Byte (8bit signed). LoadB = LoadUB + ConvUB2B. 5266 instruct loadB_indOffset16_Ex(iRegIdst dst, indOffset16 mem) %{ 5267 match(Set dst (LoadB mem)); 5268 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n)); 5269 ins_cost(MEMORY_REF_COST + DEFAULT_COST); 5270 5271 expand %{ 5272 iRegIdst tmp; 5273 loadUB_indOffset16(tmp, mem); 5274 convB2I_reg_2(dst, tmp); 5275 %} 5276 %} 5277 5278 instruct loadB_indOffset16_ac_Ex(iRegIdst dst, indOffset16 mem) %{ 5279 match(Set dst (LoadB mem)); 5280 ins_cost(3*MEMORY_REF_COST + DEFAULT_COST); 5281 5282 expand %{ 5283 iRegIdst tmp; 5284 loadUB_indOffset16_ac(tmp, mem); 5285 convB2I_reg_2(dst, tmp); 5286 %} 5287 %} 5288 5289 // Load Unsigned Byte (8bit UNsigned) into an int reg. 5290 instruct loadUB(iRegIdst dst, memory mem) %{ 5291 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n)); 5292 match(Set dst (LoadUB mem)); 5293 ins_cost(MEMORY_REF_COST); 5294 5295 format %{ "LBZ $dst, $mem \t// byte, zero-extend to int" %} 5296 size(4); 5297 ins_encode( enc_lbz(dst, mem) ); 5298 ins_pipe(pipe_class_memory); 5299 %} 5300 5301 // Load Unsigned Byte (8bit UNsigned) acquire. 5302 instruct loadUB_ac(iRegIdst dst, memory mem) %{ 5303 match(Set dst (LoadUB mem)); 5304 ins_cost(3*MEMORY_REF_COST); 5305 5306 format %{ "LBZ $dst, $mem \t// byte, zero-extend to int, acquire\n\t" 5307 "TWI $dst\n\t" 5308 "ISYNC" %} 5309 size(12); 5310 ins_encode( enc_lbz_ac(dst, mem) ); 5311 ins_pipe(pipe_class_memory); 5312 %} 5313 5314 // Load Unsigned Byte (8bit UNsigned) into a Long Register. 5315 instruct loadUB2L(iRegLdst dst, memory mem) %{ 5316 match(Set dst (ConvI2L (LoadUB mem))); 5317 predicate(_kids[0]->_leaf->as_Load()->is_unordered() || followed_by_acquire(_kids[0]->_leaf)); 5318 ins_cost(MEMORY_REF_COST); 5319 5320 format %{ "LBZ $dst, $mem \t// byte, zero-extend to long" %} 5321 size(4); 5322 ins_encode( enc_lbz(dst, mem) ); 5323 ins_pipe(pipe_class_memory); 5324 %} 5325 5326 instruct loadUB2L_ac(iRegLdst dst, memory mem) %{ 5327 match(Set dst (ConvI2L (LoadUB mem))); 5328 ins_cost(3*MEMORY_REF_COST); 5329 5330 format %{ "LBZ $dst, $mem \t// byte, zero-extend to long, acquire\n\t" 5331 "TWI $dst\n\t" 5332 "ISYNC" %} 5333 size(12); 5334 ins_encode( enc_lbz_ac(dst, mem) ); 5335 ins_pipe(pipe_class_memory); 5336 %} 5337 5338 // Load Short (16bit signed) 5339 instruct loadS(iRegIdst dst, memory mem) %{ 5340 match(Set dst (LoadS mem)); 5341 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n)); 5342 ins_cost(MEMORY_REF_COST); 5343 5344 format %{ "LHA $dst, $mem" %} 5345 size(4); 5346 ins_encode %{ 5347 // TODO: PPC port $archOpcode(ppc64Opcode_lha); 5348 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); 5349 __ lha($dst$$Register, Idisp, $mem$$base$$Register); 5350 %} 5351 ins_pipe(pipe_class_memory); 5352 %} 5353 5354 // Load Short (16bit signed) acquire. 5355 instruct loadS_ac(iRegIdst dst, memory mem) %{ 5356 match(Set dst (LoadS mem)); 5357 ins_cost(3*MEMORY_REF_COST); 5358 5359 format %{ "LHA $dst, $mem\t acquire\n\t" 5360 "TWI $dst\n\t" 5361 "ISYNC" %} 5362 size(12); 5363 ins_encode %{ 5364 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 5365 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); 5366 __ lha($dst$$Register, Idisp, $mem$$base$$Register); 5367 __ twi_0($dst$$Register); 5368 __ isync(); 5369 %} 5370 ins_pipe(pipe_class_memory); 5371 %} 5372 5373 // Load Char (16bit unsigned) 5374 instruct loadUS(iRegIdst dst, memory mem) %{ 5375 match(Set dst (LoadUS mem)); 5376 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n)); 5377 ins_cost(MEMORY_REF_COST); 5378 5379 format %{ "LHZ $dst, $mem" %} 5380 size(4); 5381 ins_encode( enc_lhz(dst, mem) ); 5382 ins_pipe(pipe_class_memory); 5383 %} 5384 5385 // Load Char (16bit unsigned) acquire. 5386 instruct loadUS_ac(iRegIdst dst, memory mem) %{ 5387 match(Set dst (LoadUS mem)); 5388 ins_cost(3*MEMORY_REF_COST); 5389 5390 format %{ "LHZ $dst, $mem \t// acquire\n\t" 5391 "TWI $dst\n\t" 5392 "ISYNC" %} 5393 size(12); 5394 ins_encode( enc_lhz_ac(dst, mem) ); 5395 ins_pipe(pipe_class_memory); 5396 %} 5397 5398 // Load Unsigned Short/Char (16bit UNsigned) into a Long Register. 5399 instruct loadUS2L(iRegLdst dst, memory mem) %{ 5400 match(Set dst (ConvI2L (LoadUS mem))); 5401 predicate(_kids[0]->_leaf->as_Load()->is_unordered() || followed_by_acquire(_kids[0]->_leaf)); 5402 ins_cost(MEMORY_REF_COST); 5403 5404 format %{ "LHZ $dst, $mem \t// short, zero-extend to long" %} 5405 size(4); 5406 ins_encode( enc_lhz(dst, mem) ); 5407 ins_pipe(pipe_class_memory); 5408 %} 5409 5410 // Load Unsigned Short/Char (16bit UNsigned) into a Long Register acquire. 5411 instruct loadUS2L_ac(iRegLdst dst, memory mem) %{ 5412 match(Set dst (ConvI2L (LoadUS mem))); 5413 ins_cost(3*MEMORY_REF_COST); 5414 5415 format %{ "LHZ $dst, $mem \t// short, zero-extend to long, acquire\n\t" 5416 "TWI $dst\n\t" 5417 "ISYNC" %} 5418 size(12); 5419 ins_encode( enc_lhz_ac(dst, mem) ); 5420 ins_pipe(pipe_class_memory); 5421 %} 5422 5423 // Load Integer. 5424 instruct loadI(iRegIdst dst, memory mem) %{ 5425 match(Set dst (LoadI mem)); 5426 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n)); 5427 ins_cost(MEMORY_REF_COST); 5428 5429 format %{ "LWZ $dst, $mem" %} 5430 size(4); 5431 ins_encode( enc_lwz(dst, mem) ); 5432 ins_pipe(pipe_class_memory); 5433 %} 5434 5435 // Load Integer acquire. 5436 instruct loadI_ac(iRegIdst dst, memory mem) %{ 5437 match(Set dst (LoadI mem)); 5438 ins_cost(3*MEMORY_REF_COST); 5439 5440 format %{ "LWZ $dst, $mem \t// load acquire\n\t" 5441 "TWI $dst\n\t" 5442 "ISYNC" %} 5443 size(12); 5444 ins_encode( enc_lwz_ac(dst, mem) ); 5445 ins_pipe(pipe_class_memory); 5446 %} 5447 5448 // Match loading integer and casting it to unsigned int in 5449 // long register. 5450 // LoadI + ConvI2L + AndL 0xffffffff. 5451 instruct loadUI2L(iRegLdst dst, memory mem, immL_32bits mask) %{ 5452 match(Set dst (AndL (ConvI2L (LoadI mem)) mask)); 5453 predicate(_kids[0]->_kids[0]->_leaf->as_Load()->is_unordered()); 5454 ins_cost(MEMORY_REF_COST); 5455 5456 format %{ "LWZ $dst, $mem \t// zero-extend to long" %} 5457 size(4); 5458 ins_encode( enc_lwz(dst, mem) ); 5459 ins_pipe(pipe_class_memory); 5460 %} 5461 5462 // Match loading integer and casting it to long. 5463 instruct loadI2L(iRegLdst dst, memory mem) %{ 5464 match(Set dst (ConvI2L (LoadI mem))); 5465 predicate(_kids[0]->_leaf->as_Load()->is_unordered()); 5466 ins_cost(MEMORY_REF_COST); 5467 5468 format %{ "LWA $dst, $mem \t// loadI2L" %} 5469 size(4); 5470 ins_encode %{ 5471 // TODO: PPC port $archOpcode(ppc64Opcode_lwa); 5472 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); 5473 __ lwa($dst$$Register, Idisp, $mem$$base$$Register); 5474 %} 5475 ins_pipe(pipe_class_memory); 5476 %} 5477 5478 // Match loading integer and casting it to long - acquire. 5479 instruct loadI2L_ac(iRegLdst dst, memory mem) %{ 5480 match(Set dst (ConvI2L (LoadI mem))); 5481 ins_cost(3*MEMORY_REF_COST); 5482 5483 format %{ "LWA $dst, $mem \t// loadI2L acquire" 5484 "TWI $dst\n\t" 5485 "ISYNC" %} 5486 size(12); 5487 ins_encode %{ 5488 // TODO: PPC port $archOpcode(ppc64Opcode_lwa); 5489 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); 5490 __ lwa($dst$$Register, Idisp, $mem$$base$$Register); 5491 __ twi_0($dst$$Register); 5492 __ isync(); 5493 %} 5494 ins_pipe(pipe_class_memory); 5495 %} 5496 5497 // Load Long - aligned 5498 instruct loadL(iRegLdst dst, memoryAlg4 mem) %{ 5499 match(Set dst (LoadL mem)); 5500 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n)); 5501 ins_cost(MEMORY_REF_COST); 5502 5503 format %{ "LD $dst, $mem \t// long" %} 5504 size(4); 5505 ins_encode( enc_ld(dst, mem) ); 5506 ins_pipe(pipe_class_memory); 5507 %} 5508 5509 // Load Long - aligned acquire. 5510 instruct loadL_ac(iRegLdst dst, memoryAlg4 mem) %{ 5511 match(Set dst (LoadL mem)); 5512 ins_cost(3*MEMORY_REF_COST); 5513 5514 format %{ "LD $dst, $mem \t// long acquire\n\t" 5515 "TWI $dst\n\t" 5516 "ISYNC" %} 5517 size(12); 5518 ins_encode( enc_ld_ac(dst, mem) ); 5519 ins_pipe(pipe_class_memory); 5520 %} 5521 5522 // Load Long - UNaligned 5523 instruct loadL_unaligned(iRegLdst dst, memoryAlg4 mem) %{ 5524 match(Set dst (LoadL_unaligned mem)); 5525 // predicate(...) // Unaligned_ac is not needed (and wouldn't make sense). 5526 ins_cost(MEMORY_REF_COST); 5527 5528 format %{ "LD $dst, $mem \t// unaligned long" %} 5529 size(4); 5530 ins_encode( enc_ld(dst, mem) ); 5531 ins_pipe(pipe_class_memory); 5532 %} 5533 5534 // Load nodes for superwords 5535 5536 // Load Aligned Packed Byte 5537 instruct loadV8(iRegLdst dst, memoryAlg4 mem) %{ 5538 predicate(n->as_LoadVector()->memory_size() == 8); 5539 match(Set dst (LoadVector mem)); 5540 ins_cost(MEMORY_REF_COST); 5541 5542 format %{ "LD $dst, $mem \t// load 8-byte Vector" %} 5543 size(4); 5544 ins_encode( enc_ld(dst, mem) ); 5545 ins_pipe(pipe_class_memory); 5546 %} 5547 5548 // Load Range, range = array length (=jint) 5549 instruct loadRange(iRegIdst dst, memory mem) %{ 5550 match(Set dst (LoadRange mem)); 5551 ins_cost(MEMORY_REF_COST); 5552 5553 format %{ "LWZ $dst, $mem \t// range" %} 5554 size(4); 5555 ins_encode( enc_lwz(dst, mem) ); 5556 ins_pipe(pipe_class_memory); 5557 %} 5558 5559 // Load Compressed Pointer 5560 instruct loadN(iRegNdst dst, memory mem) %{ 5561 match(Set dst (LoadN mem)); 5562 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n)); 5563 ins_cost(MEMORY_REF_COST); 5564 5565 format %{ "LWZ $dst, $mem \t// load compressed ptr" %} 5566 size(4); 5567 ins_encode( enc_lwz(dst, mem) ); 5568 ins_pipe(pipe_class_memory); 5569 %} 5570 5571 // Load Compressed Pointer acquire. 5572 instruct loadN_ac(iRegNdst dst, memory mem) %{ 5573 match(Set dst (LoadN mem)); 5574 ins_cost(3*MEMORY_REF_COST); 5575 5576 format %{ "LWZ $dst, $mem \t// load acquire compressed ptr\n\t" 5577 "TWI $dst\n\t" 5578 "ISYNC" %} 5579 size(12); 5580 ins_encode( enc_lwz_ac(dst, mem) ); 5581 ins_pipe(pipe_class_memory); 5582 %} 5583 5584 // Load Compressed Pointer and decode it if narrow_oop_shift == 0. 5585 instruct loadN2P_unscaled(iRegPdst dst, memory mem) %{ 5586 match(Set dst (DecodeN (LoadN mem))); 5587 predicate(_kids[0]->_leaf->as_Load()->is_unordered() && Universe::narrow_oop_shift() == 0); 5588 ins_cost(MEMORY_REF_COST); 5589 5590 format %{ "LWZ $dst, $mem \t// DecodeN (unscaled)" %} 5591 size(4); 5592 ins_encode( enc_lwz(dst, mem) ); 5593 ins_pipe(pipe_class_memory); 5594 %} 5595 5596 // Load Pointer 5597 instruct loadP(iRegPdst dst, memoryAlg4 mem) %{ 5598 match(Set dst (LoadP mem)); 5599 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n)); 5600 ins_cost(MEMORY_REF_COST); 5601 5602 format %{ "LD $dst, $mem \t// ptr" %} 5603 size(4); 5604 ins_encode( enc_ld(dst, mem) ); 5605 ins_pipe(pipe_class_memory); 5606 %} 5607 5608 // Load Pointer acquire. 5609 instruct loadP_ac(iRegPdst dst, memoryAlg4 mem) %{ 5610 match(Set dst (LoadP mem)); 5611 ins_cost(3*MEMORY_REF_COST); 5612 5613 format %{ "LD $dst, $mem \t// ptr acquire\n\t" 5614 "TWI $dst\n\t" 5615 "ISYNC" %} 5616 size(12); 5617 ins_encode( enc_ld_ac(dst, mem) ); 5618 ins_pipe(pipe_class_memory); 5619 %} 5620 5621 // LoadP + CastP2L 5622 instruct loadP2X(iRegLdst dst, memoryAlg4 mem) %{ 5623 match(Set dst (CastP2X (LoadP mem))); 5624 predicate(_kids[0]->_leaf->as_Load()->is_unordered()); 5625 ins_cost(MEMORY_REF_COST); 5626 5627 format %{ "LD $dst, $mem \t// ptr + p2x" %} 5628 size(4); 5629 ins_encode( enc_ld(dst, mem) ); 5630 ins_pipe(pipe_class_memory); 5631 %} 5632 5633 // Load compressed klass pointer. 5634 instruct loadNKlass(iRegNdst dst, memory mem) %{ 5635 match(Set dst (LoadNKlass mem)); 5636 ins_cost(MEMORY_REF_COST); 5637 5638 format %{ "LWZ $dst, $mem \t// compressed klass ptr" %} 5639 size(4); 5640 ins_encode( enc_lwz(dst, mem) ); 5641 ins_pipe(pipe_class_memory); 5642 %} 5643 5644 // Load Klass Pointer 5645 instruct loadKlass(iRegPdst dst, memoryAlg4 mem) %{ 5646 match(Set dst (LoadKlass mem)); 5647 ins_cost(MEMORY_REF_COST); 5648 5649 format %{ "LD $dst, $mem \t// klass ptr" %} 5650 size(4); 5651 ins_encode( enc_ld(dst, mem) ); 5652 ins_pipe(pipe_class_memory); 5653 %} 5654 5655 // Load Float 5656 instruct loadF(regF dst, memory mem) %{ 5657 match(Set dst (LoadF mem)); 5658 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n)); 5659 ins_cost(MEMORY_REF_COST); 5660 5661 format %{ "LFS $dst, $mem" %} 5662 size(4); 5663 ins_encode %{ 5664 // TODO: PPC port $archOpcode(ppc64Opcode_lfs); 5665 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); 5666 __ lfs($dst$$FloatRegister, Idisp, $mem$$base$$Register); 5667 %} 5668 ins_pipe(pipe_class_memory); 5669 %} 5670 5671 // Load Float acquire. 5672 instruct loadF_ac(regF dst, memory mem) %{ 5673 match(Set dst (LoadF mem)); 5674 ins_cost(3*MEMORY_REF_COST); 5675 5676 format %{ "LFS $dst, $mem \t// acquire\n\t" 5677 "FCMPU cr0, $dst, $dst\n\t" 5678 "BNE cr0, next\n" 5679 "next:\n\t" 5680 "ISYNC" %} 5681 size(16); 5682 ins_encode %{ 5683 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 5684 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); 5685 Label next; 5686 __ lfs($dst$$FloatRegister, Idisp, $mem$$base$$Register); 5687 __ fcmpu(CCR0, $dst$$FloatRegister, $dst$$FloatRegister); 5688 __ bne(CCR0, next); 5689 __ bind(next); 5690 __ isync(); 5691 %} 5692 ins_pipe(pipe_class_memory); 5693 %} 5694 5695 // Load Double - aligned 5696 instruct loadD(regD dst, memory mem) %{ 5697 match(Set dst (LoadD mem)); 5698 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n)); 5699 ins_cost(MEMORY_REF_COST); 5700 5701 format %{ "LFD $dst, $mem" %} 5702 size(4); 5703 ins_encode( enc_lfd(dst, mem) ); 5704 ins_pipe(pipe_class_memory); 5705 %} 5706 5707 // Load Double - aligned acquire. 5708 instruct loadD_ac(regD dst, memory mem) %{ 5709 match(Set dst (LoadD mem)); 5710 ins_cost(3*MEMORY_REF_COST); 5711 5712 format %{ "LFD $dst, $mem \t// acquire\n\t" 5713 "FCMPU cr0, $dst, $dst\n\t" 5714 "BNE cr0, next\n" 5715 "next:\n\t" 5716 "ISYNC" %} 5717 size(16); 5718 ins_encode %{ 5719 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 5720 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); 5721 Label next; 5722 __ lfd($dst$$FloatRegister, Idisp, $mem$$base$$Register); 5723 __ fcmpu(CCR0, $dst$$FloatRegister, $dst$$FloatRegister); 5724 __ bne(CCR0, next); 5725 __ bind(next); 5726 __ isync(); 5727 %} 5728 ins_pipe(pipe_class_memory); 5729 %} 5730 5731 // Load Double - UNaligned 5732 instruct loadD_unaligned(regD dst, memory mem) %{ 5733 match(Set dst (LoadD_unaligned mem)); 5734 // predicate(...) // Unaligned_ac is not needed (and wouldn't make sense). 5735 ins_cost(MEMORY_REF_COST); 5736 5737 format %{ "LFD $dst, $mem" %} 5738 size(4); 5739 ins_encode( enc_lfd(dst, mem) ); 5740 ins_pipe(pipe_class_memory); 5741 %} 5742 5743 //----------Constants-------------------------------------------------------- 5744 5745 // Load MachConstantTableBase: add hi offset to global toc. 5746 // TODO: Handle hidden register r29 in bundler! 5747 instruct loadToc_hi(iRegLdst dst) %{ 5748 effect(DEF dst); 5749 ins_cost(DEFAULT_COST); 5750 5751 format %{ "ADDIS $dst, R29, DISP.hi \t// load TOC hi" %} 5752 size(4); 5753 ins_encode %{ 5754 // TODO: PPC port $archOpcode(ppc64Opcode_addis); 5755 __ calculate_address_from_global_toc_hi16only($dst$$Register, __ method_toc()); 5756 %} 5757 ins_pipe(pipe_class_default); 5758 %} 5759 5760 // Load MachConstantTableBase: add lo offset to global toc. 5761 instruct loadToc_lo(iRegLdst dst, iRegLdst src) %{ 5762 effect(DEF dst, USE src); 5763 ins_cost(DEFAULT_COST); 5764 5765 format %{ "ADDI $dst, $src, DISP.lo \t// load TOC lo" %} 5766 size(4); 5767 ins_encode %{ 5768 // TODO: PPC port $archOpcode(ppc64Opcode_ori); 5769 __ calculate_address_from_global_toc_lo16only($dst$$Register, __ method_toc()); 5770 %} 5771 ins_pipe(pipe_class_default); 5772 %} 5773 5774 // Load 16-bit integer constant 0xssss???? 5775 instruct loadConI16(iRegIdst dst, immI16 src) %{ 5776 match(Set dst src); 5777 5778 format %{ "LI $dst, $src" %} 5779 size(4); 5780 ins_encode %{ 5781 // TODO: PPC port $archOpcode(ppc64Opcode_addi); 5782 __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF))); 5783 %} 5784 ins_pipe(pipe_class_default); 5785 %} 5786 5787 // Load integer constant 0x????0000 5788 instruct loadConIhi16(iRegIdst dst, immIhi16 src) %{ 5789 match(Set dst src); 5790 ins_cost(DEFAULT_COST); 5791 5792 format %{ "LIS $dst, $src.hi" %} 5793 size(4); 5794 ins_encode %{ 5795 // TODO: PPC port $archOpcode(ppc64Opcode_addis); 5796 // Lis sign extends 16-bit src then shifts it 16 bit to the left. 5797 __ lis($dst$$Register, (int)((short)(($src$$constant & 0xFFFF0000) >> 16))); 5798 %} 5799 ins_pipe(pipe_class_default); 5800 %} 5801 5802 // Part 2 of loading 32 bit constant: hi16 is is src1 (properly shifted 5803 // and sign extended), this adds the low 16 bits. 5804 instruct loadConI32_lo16(iRegIdst dst, iRegIsrc src1, immI16 src2) %{ 5805 // no match-rule, false predicate 5806 effect(DEF dst, USE src1, USE src2); 5807 predicate(false); 5808 5809 format %{ "ORI $dst, $src1.hi, $src2.lo" %} 5810 size(4); 5811 ins_encode %{ 5812 // TODO: PPC port $archOpcode(ppc64Opcode_ori); 5813 __ ori($dst$$Register, $src1$$Register, ($src2$$constant) & 0xFFFF); 5814 %} 5815 ins_pipe(pipe_class_default); 5816 %} 5817 5818 instruct loadConI_Ex(iRegIdst dst, immI src) %{ 5819 match(Set dst src); 5820 ins_cost(DEFAULT_COST*2); 5821 5822 expand %{ 5823 // Would like to use $src$$constant. 5824 immI16 srcLo %{ _opnds[1]->constant() %} 5825 // srcHi can be 0000 if srcLo sign-extends to a negative number. 5826 immIhi16 srcHi %{ _opnds[1]->constant() %} 5827 iRegIdst tmpI; 5828 loadConIhi16(tmpI, srcHi); 5829 loadConI32_lo16(dst, tmpI, srcLo); 5830 %} 5831 %} 5832 5833 // No constant pool entries required. 5834 instruct loadConL16(iRegLdst dst, immL16 src) %{ 5835 match(Set dst src); 5836 5837 format %{ "LI $dst, $src \t// long" %} 5838 size(4); 5839 ins_encode %{ 5840 // TODO: PPC port $archOpcode(ppc64Opcode_addi); 5841 __ li($dst$$Register, (int)((short) ($src$$constant & 0xFFFF))); 5842 %} 5843 ins_pipe(pipe_class_default); 5844 %} 5845 5846 // Load long constant 0xssssssss????0000 5847 instruct loadConL32hi16(iRegLdst dst, immL32hi16 src) %{ 5848 match(Set dst src); 5849 ins_cost(DEFAULT_COST); 5850 5851 format %{ "LIS $dst, $src.hi \t// long" %} 5852 size(4); 5853 ins_encode %{ 5854 // TODO: PPC port $archOpcode(ppc64Opcode_addis); 5855 __ lis($dst$$Register, (int)((short)(($src$$constant & 0xFFFF0000) >> 16))); 5856 %} 5857 ins_pipe(pipe_class_default); 5858 %} 5859 5860 // To load a 32 bit constant: merge lower 16 bits into already loaded 5861 // high 16 bits. 5862 instruct loadConL32_lo16(iRegLdst dst, iRegLsrc src1, immL16 src2) %{ 5863 // no match-rule, false predicate 5864 effect(DEF dst, USE src1, USE src2); 5865 predicate(false); 5866 5867 format %{ "ORI $dst, $src1, $src2.lo" %} 5868 size(4); 5869 ins_encode %{ 5870 // TODO: PPC port $archOpcode(ppc64Opcode_ori); 5871 __ ori($dst$$Register, $src1$$Register, ($src2$$constant) & 0xFFFF); 5872 %} 5873 ins_pipe(pipe_class_default); 5874 %} 5875 5876 // Load 32-bit long constant 5877 instruct loadConL32_Ex(iRegLdst dst, immL32 src) %{ 5878 match(Set dst src); 5879 ins_cost(DEFAULT_COST*2); 5880 5881 expand %{ 5882 // Would like to use $src$$constant. 5883 immL16 srcLo %{ _opnds[1]->constant() /*& 0x0000FFFFL */%} 5884 // srcHi can be 0000 if srcLo sign-extends to a negative number. 5885 immL32hi16 srcHi %{ _opnds[1]->constant() /*& 0xFFFF0000L */%} 5886 iRegLdst tmpL; 5887 loadConL32hi16(tmpL, srcHi); 5888 loadConL32_lo16(dst, tmpL, srcLo); 5889 %} 5890 %} 5891 5892 // Load long constant 0x????000000000000. 5893 instruct loadConLhighest16_Ex(iRegLdst dst, immLhighest16 src) %{ 5894 match(Set dst src); 5895 ins_cost(DEFAULT_COST); 5896 5897 expand %{ 5898 immL32hi16 srcHi %{ _opnds[1]->constant() >> 32 /*& 0xFFFF0000L */%} 5899 immI shift32 %{ 32 %} 5900 iRegLdst tmpL; 5901 loadConL32hi16(tmpL, srcHi); 5902 lshiftL_regL_immI(dst, tmpL, shift32); 5903 %} 5904 %} 5905 5906 // Expand node for constant pool load: small offset. 5907 instruct loadConL(iRegLdst dst, immL src, iRegLdst toc) %{ 5908 effect(DEF dst, USE src, USE toc); 5909 ins_cost(MEMORY_REF_COST); 5910 5911 ins_num_consts(1); 5912 // Needed so that CallDynamicJavaDirect can compute the address of this 5913 // instruction for relocation. 5914 ins_field_cbuf_insts_offset(int); 5915 5916 format %{ "LD $dst, offset, $toc \t// load long $src from TOC" %} 5917 size(4); 5918 ins_encode( enc_load_long_constL(dst, src, toc) ); 5919 ins_pipe(pipe_class_memory); 5920 %} 5921 5922 // Expand node for constant pool load: large offset. 5923 instruct loadConL_hi(iRegLdst dst, immL src, iRegLdst toc) %{ 5924 effect(DEF dst, USE src, USE toc); 5925 predicate(false); 5926 5927 ins_num_consts(1); 5928 ins_field_const_toc_offset(int); 5929 // Needed so that CallDynamicJavaDirect can compute the address of this 5930 // instruction for relocation. 5931 ins_field_cbuf_insts_offset(int); 5932 5933 format %{ "ADDIS $dst, $toc, offset \t// load long $src from TOC (hi)" %} 5934 size(4); 5935 ins_encode( enc_load_long_constL_hi(dst, toc, src) ); 5936 ins_pipe(pipe_class_default); 5937 %} 5938 5939 // Expand node for constant pool load: large offset. 5940 // No constant pool entries required. 5941 instruct loadConL_lo(iRegLdst dst, immL src, iRegLdst base) %{ 5942 effect(DEF dst, USE src, USE base); 5943 predicate(false); 5944 5945 ins_field_const_toc_offset_hi_node(loadConL_hiNode*); 5946 5947 format %{ "LD $dst, offset, $base \t// load long $src from TOC (lo)" %} 5948 size(4); 5949 ins_encode %{ 5950 // TODO: PPC port $archOpcode(ppc64Opcode_ld); 5951 int offset = ra_->C->in_scratch_emit_size() ? 0 : _const_toc_offset_hi_node->_const_toc_offset; 5952 __ ld($dst$$Register, MacroAssembler::largeoffset_si16_si16_lo(offset), $base$$Register); 5953 %} 5954 ins_pipe(pipe_class_memory); 5955 %} 5956 5957 // Load long constant from constant table. Expand in case of 5958 // offset > 16 bit is needed. 5959 // Adlc adds toc node MachConstantTableBase. 5960 instruct loadConL_Ex(iRegLdst dst, immL src) %{ 5961 match(Set dst src); 5962 ins_cost(MEMORY_REF_COST); 5963 5964 format %{ "LD $dst, offset, $constanttablebase\t// load long $src from table, postalloc expanded" %} 5965 // We can not inline the enc_class for the expand as that does not support constanttablebase. 5966 postalloc_expand( postalloc_expand_load_long_constant(dst, src, constanttablebase) ); 5967 %} 5968 5969 // Load NULL as compressed oop. 5970 instruct loadConN0(iRegNdst dst, immN_0 src) %{ 5971 match(Set dst src); 5972 ins_cost(DEFAULT_COST); 5973 5974 format %{ "LI $dst, $src \t// compressed ptr" %} 5975 size(4); 5976 ins_encode %{ 5977 // TODO: PPC port $archOpcode(ppc64Opcode_addi); 5978 __ li($dst$$Register, 0); 5979 %} 5980 ins_pipe(pipe_class_default); 5981 %} 5982 5983 // Load hi part of compressed oop constant. 5984 instruct loadConN_hi(iRegNdst dst, immN src) %{ 5985 effect(DEF dst, USE src); 5986 ins_cost(DEFAULT_COST); 5987 5988 format %{ "LIS $dst, $src \t// narrow oop hi" %} 5989 size(4); 5990 ins_encode %{ 5991 // TODO: PPC port $archOpcode(ppc64Opcode_addis); 5992 __ lis($dst$$Register, (int)(short)(($src$$constant >> 16) & 0xffff)); 5993 %} 5994 ins_pipe(pipe_class_default); 5995 %} 5996 5997 // Add lo part of compressed oop constant to already loaded hi part. 5998 instruct loadConN_lo(iRegNdst dst, iRegNsrc src1, immN src2) %{ 5999 effect(DEF dst, USE src1, USE src2); 6000 ins_cost(DEFAULT_COST); 6001 6002 format %{ "ORI $dst, $src1, $src2 \t// narrow oop lo" %} 6003 size(4); 6004 ins_encode %{ 6005 // TODO: PPC port $archOpcode(ppc64Opcode_addi); 6006 assert(__ oop_recorder() != NULL, "this assembler needs an OopRecorder"); 6007 int oop_index = __ oop_recorder()->find_index((jobject)$src2$$constant); 6008 RelocationHolder rspec = oop_Relocation::spec(oop_index); 6009 __ relocate(rspec, 1); 6010 __ ori($dst$$Register, $src1$$Register, $src2$$constant & 0xffff); 6011 %} 6012 ins_pipe(pipe_class_default); 6013 %} 6014 6015 // Needed to postalloc expand loadConN: ConN is loaded as ConI 6016 // leaving the upper 32 bits with sign-extension bits. 6017 // This clears these bits: dst = src & 0xFFFFFFFF. 6018 // TODO: Eventually call this maskN_regN_FFFFFFFF. 6019 instruct clearMs32b(iRegNdst dst, iRegNsrc src) %{ 6020 effect(DEF dst, USE src); 6021 predicate(false); 6022 6023 format %{ "MASK $dst, $src, 0xFFFFFFFF" %} // mask 6024 size(4); 6025 ins_encode %{ 6026 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl); 6027 __ clrldi($dst$$Register, $src$$Register, 0x20); 6028 %} 6029 ins_pipe(pipe_class_default); 6030 %} 6031 6032 // Loading ConN must be postalloc expanded so that edges between 6033 // the nodes are safe. They may not interfere with a safepoint. 6034 // GL TODO: This needs three instructions: better put this into the constant pool. 6035 instruct loadConN_Ex(iRegNdst dst, immN src) %{ 6036 match(Set dst src); 6037 ins_cost(DEFAULT_COST*2); 6038 6039 format %{ "LoadN $dst, $src \t// postalloc expanded" %} // mask 6040 postalloc_expand %{ 6041 MachNode *m1 = new (C) loadConN_hiNode(); 6042 MachNode *m2 = new (C) loadConN_loNode(); 6043 MachNode *m3 = new (C) clearMs32bNode(); 6044 m1->add_req(NULL); 6045 m2->add_req(NULL, m1); 6046 m3->add_req(NULL, m2); 6047 m1->_opnds[0] = op_dst; 6048 m1->_opnds[1] = op_src; 6049 m2->_opnds[0] = op_dst; 6050 m2->_opnds[1] = op_dst; 6051 m2->_opnds[2] = op_src; 6052 m3->_opnds[0] = op_dst; 6053 m3->_opnds[1] = op_dst; 6054 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 6055 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 6056 ra_->set_pair(m3->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 6057 nodes->push(m1); 6058 nodes->push(m2); 6059 nodes->push(m3); 6060 %} 6061 %} 6062 6063 // We have seen a safepoint between the hi and lo parts, and this node was handled 6064 // as an oop. Therefore this needs a match rule so that build_oop_map knows this is 6065 // not a narrow oop. 6066 instruct loadConNKlass_hi(iRegNdst dst, immNKlass_NM src) %{ 6067 match(Set dst src); 6068 effect(DEF dst, USE src); 6069 ins_cost(DEFAULT_COST); 6070 6071 format %{ "LIS $dst, $src \t// narrow klass hi" %} 6072 size(4); 6073 ins_encode %{ 6074 // TODO: PPC port $archOpcode(ppc64Opcode_addis); 6075 intptr_t Csrc = Klass::encode_klass((Klass *)$src$$constant); 6076 __ lis($dst$$Register, (int)(short)((Csrc >> 16) & 0xffff)); 6077 %} 6078 ins_pipe(pipe_class_default); 6079 %} 6080 6081 // As loadConNKlass_hi this must be recognized as narrow klass, not oop! 6082 instruct loadConNKlass_mask(iRegNdst dst, immNKlass_NM src1, iRegNsrc src2) %{ 6083 match(Set dst src1); 6084 effect(TEMP src2); 6085 ins_cost(DEFAULT_COST); 6086 6087 format %{ "MASK $dst, $src2, 0xFFFFFFFF" %} // mask 6088 size(4); 6089 ins_encode %{ 6090 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl); 6091 __ clrldi($dst$$Register, $src2$$Register, 0x20); 6092 %} 6093 ins_pipe(pipe_class_default); 6094 %} 6095 6096 // This needs a match rule so that build_oop_map knows this is 6097 // not a narrow oop. 6098 instruct loadConNKlass_lo(iRegNdst dst, immNKlass_NM src1, iRegNsrc src2) %{ 6099 match(Set dst src1); 6100 effect(TEMP src2); 6101 ins_cost(DEFAULT_COST); 6102 6103 format %{ "ORI $dst, $src1, $src2 \t// narrow klass lo" %} 6104 size(4); 6105 ins_encode %{ 6106 // TODO: PPC port $archOpcode(ppc64Opcode_ori); 6107 intptr_t Csrc = Klass::encode_klass((Klass *)$src1$$constant); 6108 assert(__ oop_recorder() != NULL, "this assembler needs an OopRecorder"); 6109 int klass_index = __ oop_recorder()->find_index((Klass *)$src1$$constant); 6110 RelocationHolder rspec = metadata_Relocation::spec(klass_index); 6111 6112 __ relocate(rspec, 1); 6113 __ ori($dst$$Register, $src2$$Register, Csrc & 0xffff); 6114 %} 6115 ins_pipe(pipe_class_default); 6116 %} 6117 6118 // Loading ConNKlass must be postalloc expanded so that edges between 6119 // the nodes are safe. They may not interfere with a safepoint. 6120 instruct loadConNKlass_Ex(iRegNdst dst, immNKlass src) %{ 6121 match(Set dst src); 6122 ins_cost(DEFAULT_COST*2); 6123 6124 format %{ "LoadN $dst, $src \t// postalloc expanded" %} // mask 6125 postalloc_expand %{ 6126 // Load high bits into register. Sign extended. 6127 MachNode *m1 = new (C) loadConNKlass_hiNode(); 6128 m1->add_req(NULL); 6129 m1->_opnds[0] = op_dst; 6130 m1->_opnds[1] = op_src; 6131 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 6132 nodes->push(m1); 6133 6134 MachNode *m2 = m1; 6135 if (!Assembler::is_uimm((jlong)Klass::encode_klass((Klass *)op_src->constant()), 31)) { 6136 // Value might be 1-extended. Mask out these bits. 6137 m2 = new (C) loadConNKlass_maskNode(); 6138 m2->add_req(NULL, m1); 6139 m2->_opnds[0] = op_dst; 6140 m2->_opnds[1] = op_src; 6141 m2->_opnds[2] = op_dst; 6142 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 6143 nodes->push(m2); 6144 } 6145 6146 MachNode *m3 = new (C) loadConNKlass_loNode(); 6147 m3->add_req(NULL, m2); 6148 m3->_opnds[0] = op_dst; 6149 m3->_opnds[1] = op_src; 6150 m3->_opnds[2] = op_dst; 6151 ra_->set_pair(m3->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 6152 nodes->push(m3); 6153 %} 6154 %} 6155 6156 // 0x1 is used in object initialization (initial object header). 6157 // No constant pool entries required. 6158 instruct loadConP0or1(iRegPdst dst, immP_0or1 src) %{ 6159 match(Set dst src); 6160 6161 format %{ "LI $dst, $src \t// ptr" %} 6162 size(4); 6163 ins_encode %{ 6164 // TODO: PPC port $archOpcode(ppc64Opcode_addi); 6165 __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF))); 6166 %} 6167 ins_pipe(pipe_class_default); 6168 %} 6169 6170 // Expand node for constant pool load: small offset. 6171 // The match rule is needed to generate the correct bottom_type(), 6172 // however this node should never match. The use of predicate is not 6173 // possible since ADLC forbids predicates for chain rules. The higher 6174 // costs do not prevent matching in this case. For that reason the 6175 // operand immP_NM with predicate(false) is used. 6176 instruct loadConP(iRegPdst dst, immP_NM src, iRegLdst toc) %{ 6177 match(Set dst src); 6178 effect(TEMP toc); 6179 6180 ins_num_consts(1); 6181 6182 format %{ "LD $dst, offset, $toc \t// load ptr $src from TOC" %} 6183 size(4); 6184 ins_encode( enc_load_long_constP(dst, src, toc) ); 6185 ins_pipe(pipe_class_memory); 6186 %} 6187 6188 // Expand node for constant pool load: large offset. 6189 instruct loadConP_hi(iRegPdst dst, immP_NM src, iRegLdst toc) %{ 6190 effect(DEF dst, USE src, USE toc); 6191 predicate(false); 6192 6193 ins_num_consts(1); 6194 ins_field_const_toc_offset(int); 6195 6196 format %{ "ADDIS $dst, $toc, offset \t// load ptr $src from TOC (hi)" %} 6197 size(4); 6198 ins_encode( enc_load_long_constP_hi(dst, src, toc) ); 6199 ins_pipe(pipe_class_default); 6200 %} 6201 6202 // Expand node for constant pool load: large offset. 6203 instruct loadConP_lo(iRegPdst dst, immP_NM src, iRegLdst base) %{ 6204 match(Set dst src); 6205 effect(TEMP base); 6206 6207 ins_field_const_toc_offset_hi_node(loadConP_hiNode*); 6208 6209 format %{ "LD $dst, offset, $base \t// load ptr $src from TOC (lo)" %} 6210 size(4); 6211 ins_encode %{ 6212 // TODO: PPC port $archOpcode(ppc64Opcode_ld); 6213 int offset = ra_->C->in_scratch_emit_size() ? 0 : _const_toc_offset_hi_node->_const_toc_offset; 6214 __ ld($dst$$Register, MacroAssembler::largeoffset_si16_si16_lo(offset), $base$$Register); 6215 %} 6216 ins_pipe(pipe_class_memory); 6217 %} 6218 6219 // Load pointer constant from constant table. Expand in case an 6220 // offset > 16 bit is needed. 6221 // Adlc adds toc node MachConstantTableBase. 6222 instruct loadConP_Ex(iRegPdst dst, immP src) %{ 6223 match(Set dst src); 6224 ins_cost(MEMORY_REF_COST); 6225 6226 // This rule does not use "expand" because then 6227 // the result type is not known to be an Oop. An ADLC 6228 // enhancement will be needed to make that work - not worth it! 6229 6230 // If this instruction rematerializes, it prolongs the live range 6231 // of the toc node, causing illegal graphs. 6232 // assert(edge_from_to(_reg_node[reg_lo],def)) fails in verify_good_schedule(). 6233 ins_cannot_rematerialize(true); 6234 6235 format %{ "LD $dst, offset, $constanttablebase \t// load ptr $src from table, postalloc expanded" %} 6236 postalloc_expand( postalloc_expand_load_ptr_constant(dst, src, constanttablebase) ); 6237 %} 6238 6239 // Expand node for constant pool load: small offset. 6240 instruct loadConF(regF dst, immF src, iRegLdst toc) %{ 6241 effect(DEF dst, USE src, USE toc); 6242 ins_cost(MEMORY_REF_COST); 6243 6244 ins_num_consts(1); 6245 6246 format %{ "LFS $dst, offset, $toc \t// load float $src from TOC" %} 6247 size(4); 6248 ins_encode %{ 6249 // TODO: PPC port $archOpcode(ppc64Opcode_lfs); 6250 address float_address = __ float_constant($src$$constant); 6251 __ lfs($dst$$FloatRegister, __ offset_to_method_toc(float_address), $toc$$Register); 6252 %} 6253 ins_pipe(pipe_class_memory); 6254 %} 6255 6256 // Expand node for constant pool load: large offset. 6257 instruct loadConFComp(regF dst, immF src, iRegLdst toc) %{ 6258 effect(DEF dst, USE src, USE toc); 6259 ins_cost(MEMORY_REF_COST); 6260 6261 ins_num_consts(1); 6262 6263 format %{ "ADDIS $toc, $toc, offset_hi\n\t" 6264 "LFS $dst, offset_lo, $toc \t// load float $src from TOC (hi/lo)\n\t" 6265 "ADDIS $toc, $toc, -offset_hi"%} 6266 size(12); 6267 ins_encode %{ 6268 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 6269 FloatRegister Rdst = $dst$$FloatRegister; 6270 Register Rtoc = $toc$$Register; 6271 address float_address = __ float_constant($src$$constant); 6272 int offset = __ offset_to_method_toc(float_address); 6273 int hi = (offset + (1<<15))>>16; 6274 int lo = offset - hi * (1<<16); 6275 6276 __ addis(Rtoc, Rtoc, hi); 6277 __ lfs(Rdst, lo, Rtoc); 6278 __ addis(Rtoc, Rtoc, -hi); 6279 %} 6280 ins_pipe(pipe_class_memory); 6281 %} 6282 6283 // Adlc adds toc node MachConstantTableBase. 6284 instruct loadConF_Ex(regF dst, immF src) %{ 6285 match(Set dst src); 6286 ins_cost(MEMORY_REF_COST); 6287 6288 // See loadConP. 6289 ins_cannot_rematerialize(true); 6290 6291 format %{ "LFS $dst, offset, $constanttablebase \t// load $src from table, postalloc expanded" %} 6292 postalloc_expand( postalloc_expand_load_float_constant(dst, src, constanttablebase) ); 6293 %} 6294 6295 // Expand node for constant pool load: small offset. 6296 instruct loadConD(regD dst, immD src, iRegLdst toc) %{ 6297 effect(DEF dst, USE src, USE toc); 6298 ins_cost(MEMORY_REF_COST); 6299 6300 ins_num_consts(1); 6301 6302 format %{ "LFD $dst, offset, $toc \t// load double $src from TOC" %} 6303 size(4); 6304 ins_encode %{ 6305 // TODO: PPC port $archOpcode(ppc64Opcode_lfd); 6306 int offset = __ offset_to_method_toc(__ double_constant($src$$constant)); 6307 __ lfd($dst$$FloatRegister, offset, $toc$$Register); 6308 %} 6309 ins_pipe(pipe_class_memory); 6310 %} 6311 6312 // Expand node for constant pool load: large offset. 6313 instruct loadConDComp(regD dst, immD src, iRegLdst toc) %{ 6314 effect(DEF dst, USE src, USE toc); 6315 ins_cost(MEMORY_REF_COST); 6316 6317 ins_num_consts(1); 6318 6319 format %{ "ADDIS $toc, $toc, offset_hi\n\t" 6320 "LFD $dst, offset_lo, $toc \t// load double $src from TOC (hi/lo)\n\t" 6321 "ADDIS $toc, $toc, -offset_hi" %} 6322 size(12); 6323 ins_encode %{ 6324 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 6325 FloatRegister Rdst = $dst$$FloatRegister; 6326 Register Rtoc = $toc$$Register; 6327 address float_address = __ double_constant($src$$constant); 6328 int offset = __ offset_to_method_toc(float_address); 6329 int hi = (offset + (1<<15))>>16; 6330 int lo = offset - hi * (1<<16); 6331 6332 __ addis(Rtoc, Rtoc, hi); 6333 __ lfd(Rdst, lo, Rtoc); 6334 __ addis(Rtoc, Rtoc, -hi); 6335 %} 6336 ins_pipe(pipe_class_memory); 6337 %} 6338 6339 // Adlc adds toc node MachConstantTableBase. 6340 instruct loadConD_Ex(regD dst, immD src) %{ 6341 match(Set dst src); 6342 ins_cost(MEMORY_REF_COST); 6343 6344 // See loadConP. 6345 ins_cannot_rematerialize(true); 6346 6347 format %{ "ConD $dst, offset, $constanttablebase \t// load $src from table, postalloc expanded" %} 6348 postalloc_expand( postalloc_expand_load_double_constant(dst, src, constanttablebase) ); 6349 %} 6350 6351 // Prefetch instructions. 6352 // Must be safe to execute with invalid address (cannot fault). 6353 6354 instruct prefetchr(indirectMemory mem, iRegLsrc src) %{ 6355 match(PrefetchRead (AddP mem src)); 6356 ins_cost(MEMORY_REF_COST); 6357 6358 format %{ "PREFETCH $mem, 0, $src \t// Prefetch read-many" %} 6359 size(4); 6360 ins_encode %{ 6361 // TODO: PPC port $archOpcode(ppc64Opcode_dcbt); 6362 __ dcbt($src$$Register, $mem$$base$$Register); 6363 %} 6364 ins_pipe(pipe_class_memory); 6365 %} 6366 6367 instruct prefetchr_no_offset(indirectMemory mem) %{ 6368 match(PrefetchRead mem); 6369 ins_cost(MEMORY_REF_COST); 6370 6371 format %{ "PREFETCH $mem" %} 6372 size(4); 6373 ins_encode %{ 6374 // TODO: PPC port $archOpcode(ppc64Opcode_dcbt); 6375 __ dcbt($mem$$base$$Register); 6376 %} 6377 ins_pipe(pipe_class_memory); 6378 %} 6379 6380 instruct prefetchw(indirectMemory mem, iRegLsrc src) %{ 6381 match(PrefetchWrite (AddP mem src)); 6382 ins_cost(MEMORY_REF_COST); 6383 6384 format %{ "PREFETCH $mem, 2, $src \t// Prefetch write-many (and read)" %} 6385 size(4); 6386 ins_encode %{ 6387 // TODO: PPC port $archOpcode(ppc64Opcode_dcbtst); 6388 __ dcbtst($src$$Register, $mem$$base$$Register); 6389 %} 6390 ins_pipe(pipe_class_memory); 6391 %} 6392 6393 instruct prefetchw_no_offset(indirectMemory mem) %{ 6394 match(PrefetchWrite mem); 6395 ins_cost(MEMORY_REF_COST); 6396 6397 format %{ "PREFETCH $mem" %} 6398 size(4); 6399 ins_encode %{ 6400 // TODO: PPC port $archOpcode(ppc64Opcode_dcbtst); 6401 __ dcbtst($mem$$base$$Register); 6402 %} 6403 ins_pipe(pipe_class_memory); 6404 %} 6405 6406 // Special prefetch versions which use the dcbz instruction. 6407 instruct prefetch_alloc_zero(indirectMemory mem, iRegLsrc src) %{ 6408 match(PrefetchAllocation (AddP mem src)); 6409 predicate(AllocatePrefetchStyle == 3); 6410 ins_cost(MEMORY_REF_COST); 6411 6412 format %{ "PREFETCH $mem, 2, $src \t// Prefetch write-many with zero" %} 6413 size(4); 6414 ins_encode %{ 6415 // TODO: PPC port $archOpcode(ppc64Opcode_dcbtst); 6416 __ dcbz($src$$Register, $mem$$base$$Register); 6417 %} 6418 ins_pipe(pipe_class_memory); 6419 %} 6420 6421 instruct prefetch_alloc_zero_no_offset(indirectMemory mem) %{ 6422 match(PrefetchAllocation mem); 6423 predicate(AllocatePrefetchStyle == 3); 6424 ins_cost(MEMORY_REF_COST); 6425 6426 format %{ "PREFETCH $mem, 2 \t// Prefetch write-many with zero" %} 6427 size(4); 6428 ins_encode %{ 6429 // TODO: PPC port $archOpcode(ppc64Opcode_dcbtst); 6430 __ dcbz($mem$$base$$Register); 6431 %} 6432 ins_pipe(pipe_class_memory); 6433 %} 6434 6435 instruct prefetch_alloc(indirectMemory mem, iRegLsrc src) %{ 6436 match(PrefetchAllocation (AddP mem src)); 6437 predicate(AllocatePrefetchStyle != 3); 6438 ins_cost(MEMORY_REF_COST); 6439 6440 format %{ "PREFETCH $mem, 2, $src \t// Prefetch write-many" %} 6441 size(4); 6442 ins_encode %{ 6443 // TODO: PPC port $archOpcode(ppc64Opcode_dcbtst); 6444 __ dcbtst($src$$Register, $mem$$base$$Register); 6445 %} 6446 ins_pipe(pipe_class_memory); 6447 %} 6448 6449 instruct prefetch_alloc_no_offset(indirectMemory mem) %{ 6450 match(PrefetchAllocation mem); 6451 predicate(AllocatePrefetchStyle != 3); 6452 ins_cost(MEMORY_REF_COST); 6453 6454 format %{ "PREFETCH $mem, 2 \t// Prefetch write-many" %} 6455 size(4); 6456 ins_encode %{ 6457 // TODO: PPC port $archOpcode(ppc64Opcode_dcbtst); 6458 __ dcbtst($mem$$base$$Register); 6459 %} 6460 ins_pipe(pipe_class_memory); 6461 %} 6462 6463 //----------Store Instructions------------------------------------------------- 6464 6465 // Store Byte 6466 instruct storeB(memory mem, iRegIsrc src) %{ 6467 match(Set mem (StoreB mem src)); 6468 ins_cost(MEMORY_REF_COST); 6469 6470 format %{ "STB $src, $mem \t// byte" %} 6471 size(4); 6472 ins_encode %{ 6473 // TODO: PPC port $archOpcode(ppc64Opcode_stb); 6474 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); 6475 __ stb($src$$Register, Idisp, $mem$$base$$Register); 6476 %} 6477 ins_pipe(pipe_class_memory); 6478 %} 6479 6480 // Store Char/Short 6481 instruct storeC(memory mem, iRegIsrc src) %{ 6482 match(Set mem (StoreC mem src)); 6483 ins_cost(MEMORY_REF_COST); 6484 6485 format %{ "STH $src, $mem \t// short" %} 6486 size(4); 6487 ins_encode %{ 6488 // TODO: PPC port $archOpcode(ppc64Opcode_sth); 6489 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); 6490 __ sth($src$$Register, Idisp, $mem$$base$$Register); 6491 %} 6492 ins_pipe(pipe_class_memory); 6493 %} 6494 6495 // Store Integer 6496 instruct storeI(memory mem, iRegIsrc src) %{ 6497 match(Set mem (StoreI mem src)); 6498 ins_cost(MEMORY_REF_COST); 6499 6500 format %{ "STW $src, $mem" %} 6501 size(4); 6502 ins_encode( enc_stw(src, mem) ); 6503 ins_pipe(pipe_class_memory); 6504 %} 6505 6506 // ConvL2I + StoreI. 6507 instruct storeI_convL2I(memory mem, iRegLsrc src) %{ 6508 match(Set mem (StoreI mem (ConvL2I src))); 6509 ins_cost(MEMORY_REF_COST); 6510 6511 format %{ "STW l2i($src), $mem" %} 6512 size(4); 6513 ins_encode( enc_stw(src, mem) ); 6514 ins_pipe(pipe_class_memory); 6515 %} 6516 6517 // Store Long 6518 instruct storeL(memoryAlg4 mem, iRegLsrc src) %{ 6519 match(Set mem (StoreL mem src)); 6520 ins_cost(MEMORY_REF_COST); 6521 6522 format %{ "STD $src, $mem \t// long" %} 6523 size(4); 6524 ins_encode( enc_std(src, mem) ); 6525 ins_pipe(pipe_class_memory); 6526 %} 6527 6528 // Store super word nodes. 6529 6530 // Store Aligned Packed Byte long register to memory 6531 instruct storeA8B(memoryAlg4 mem, iRegLsrc src) %{ 6532 predicate(n->as_StoreVector()->memory_size() == 8); 6533 match(Set mem (StoreVector mem src)); 6534 ins_cost(MEMORY_REF_COST); 6535 6536 format %{ "STD $mem, $src \t// packed8B" %} 6537 size(4); 6538 ins_encode( enc_std(src, mem) ); 6539 ins_pipe(pipe_class_memory); 6540 %} 6541 6542 // Store Compressed Oop 6543 instruct storeN(memory dst, iRegN_P2N src) %{ 6544 match(Set dst (StoreN dst src)); 6545 ins_cost(MEMORY_REF_COST); 6546 6547 format %{ "STW $src, $dst \t// compressed oop" %} 6548 size(4); 6549 ins_encode( enc_stw(src, dst) ); 6550 ins_pipe(pipe_class_memory); 6551 %} 6552 6553 // Store Compressed KLass 6554 instruct storeNKlass(memory dst, iRegN_P2N src) %{ 6555 match(Set dst (StoreNKlass dst src)); 6556 ins_cost(MEMORY_REF_COST); 6557 6558 format %{ "STW $src, $dst \t// compressed klass" %} 6559 size(4); 6560 ins_encode( enc_stw(src, dst) ); 6561 ins_pipe(pipe_class_memory); 6562 %} 6563 6564 // Store Pointer 6565 instruct storeP(memoryAlg4 dst, iRegPsrc src) %{ 6566 match(Set dst (StoreP dst src)); 6567 ins_cost(MEMORY_REF_COST); 6568 6569 format %{ "STD $src, $dst \t// ptr" %} 6570 size(4); 6571 ins_encode( enc_std(src, dst) ); 6572 ins_pipe(pipe_class_memory); 6573 %} 6574 6575 // Store Float 6576 instruct storeF(memory mem, regF src) %{ 6577 match(Set mem (StoreF mem src)); 6578 ins_cost(MEMORY_REF_COST); 6579 6580 format %{ "STFS $src, $mem" %} 6581 size(4); 6582 ins_encode( enc_stfs(src, mem) ); 6583 ins_pipe(pipe_class_memory); 6584 %} 6585 6586 // Store Double 6587 instruct storeD(memory mem, regD src) %{ 6588 match(Set mem (StoreD mem src)); 6589 ins_cost(MEMORY_REF_COST); 6590 6591 format %{ "STFD $src, $mem" %} 6592 size(4); 6593 ins_encode( enc_stfd(src, mem) ); 6594 ins_pipe(pipe_class_memory); 6595 %} 6596 6597 //----------Store Instructions With Zeros-------------------------------------- 6598 6599 // Card-mark for CMS garbage collection. 6600 // This cardmark does an optimization so that it must not always 6601 // do a releasing store. For this, it gets the address of 6602 // CMSCollectorCardTableModRefBSExt::_requires_release as input. 6603 // (Using releaseFieldAddr in the match rule is a hack.) 6604 instruct storeCM_CMS(memory mem, iRegLdst releaseFieldAddr) %{ 6605 match(Set mem (StoreCM mem releaseFieldAddr)); 6606 predicate(false); 6607 ins_cost(MEMORY_REF_COST); 6608 6609 // See loadConP. 6610 ins_cannot_rematerialize(true); 6611 6612 format %{ "STB #0, $mem \t// CMS card-mark byte (must be 0!), checking requires_release in [$releaseFieldAddr]" %} 6613 ins_encode( enc_cms_card_mark(mem, releaseFieldAddr) ); 6614 ins_pipe(pipe_class_memory); 6615 %} 6616 6617 // Card-mark for CMS garbage collection. 6618 // This cardmark does an optimization so that it must not always 6619 // do a releasing store. For this, it needs the constant address of 6620 // CMSCollectorCardTableModRefBSExt::_requires_release. 6621 // This constant address is split off here by expand so we can use 6622 // adlc / matcher functionality to load it from the constant section. 6623 instruct storeCM_CMS_ExEx(memory mem, immI_0 zero) %{ 6624 match(Set mem (StoreCM mem zero)); 6625 predicate(UseConcMarkSweepGC); 6626 6627 expand %{ 6628 immL baseImm %{ 0 /* TODO: PPC port (jlong)CMSCollectorCardTableModRefBSExt::requires_release_address() */ %} 6629 iRegLdst releaseFieldAddress; 6630 loadConL_Ex(releaseFieldAddress, baseImm); 6631 storeCM_CMS(mem, releaseFieldAddress); 6632 %} 6633 %} 6634 6635 instruct storeCM_G1(memory mem, immI_0 zero) %{ 6636 match(Set mem (StoreCM mem zero)); 6637 predicate(UseG1GC); 6638 ins_cost(MEMORY_REF_COST); 6639 6640 ins_cannot_rematerialize(true); 6641 6642 format %{ "STB #0, $mem \t// CMS card-mark byte store (G1)" %} 6643 size(8); 6644 ins_encode %{ 6645 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 6646 __ li(R0, 0); 6647 //__ release(); // G1: oops are allowed to get visible after dirty marking 6648 guarantee($mem$$base$$Register != R1_SP, "use frame_slots_bias"); 6649 __ stb(R0, $mem$$disp, $mem$$base$$Register); 6650 %} 6651 ins_pipe(pipe_class_memory); 6652 %} 6653 6654 // Convert oop pointer into compressed form. 6655 6656 // Nodes for postalloc expand. 6657 6658 // Shift node for expand. 6659 instruct encodeP_shift(iRegNdst dst, iRegNsrc src) %{ 6660 // The match rule is needed to make it a 'MachTypeNode'! 6661 match(Set dst (EncodeP src)); 6662 predicate(false); 6663 6664 format %{ "SRDI $dst, $src, 3 \t// encode" %} 6665 size(4); 6666 ins_encode %{ 6667 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl); 6668 __ srdi($dst$$Register, $src$$Register, Universe::narrow_oop_shift() & 0x3f); 6669 %} 6670 ins_pipe(pipe_class_default); 6671 %} 6672 6673 // Add node for expand. 6674 instruct encodeP_sub(iRegPdst dst, iRegPdst src) %{ 6675 // The match rule is needed to make it a 'MachTypeNode'! 6676 match(Set dst (EncodeP src)); 6677 predicate(false); 6678 6679 format %{ "SUB $dst, $src, oop_base \t// encode" %} 6680 size(4); 6681 ins_encode %{ 6682 // TODO: PPC port $archOpcode(ppc64Opcode_subf); 6683 __ subf($dst$$Register, R30, $src$$Register); 6684 %} 6685 ins_pipe(pipe_class_default); 6686 %} 6687 6688 // Conditional sub base. 6689 instruct cond_sub_base(iRegNdst dst, flagsReg crx, iRegPsrc src1) %{ 6690 // The match rule is needed to make it a 'MachTypeNode'! 6691 match(Set dst (EncodeP (Binary crx src1))); 6692 predicate(false); 6693 6694 ins_variable_size_depending_on_alignment(true); 6695 6696 format %{ "BEQ $crx, done\n\t" 6697 "SUB $dst, $src1, R30 \t// encode: subtract base if != NULL\n" 6698 "done:" %} 6699 size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8); 6700 ins_encode %{ 6701 // TODO: PPC port $archOpcode(ppc64Opcode_cmove); 6702 Label done; 6703 __ beq($crx$$CondRegister, done); 6704 __ subf($dst$$Register, R30, $src1$$Register); 6705 // TODO PPC port __ endgroup_if_needed(_size == 12); 6706 __ bind(done); 6707 %} 6708 ins_pipe(pipe_class_default); 6709 %} 6710 6711 // Power 7 can use isel instruction 6712 instruct cond_set_0_oop(iRegNdst dst, flagsReg crx, iRegPsrc src1) %{ 6713 // The match rule is needed to make it a 'MachTypeNode'! 6714 match(Set dst (EncodeP (Binary crx src1))); 6715 predicate(false); 6716 6717 format %{ "CMOVE $dst, $crx eq, 0, $src1 \t// encode: preserve 0" %} 6718 size(4); 6719 ins_encode %{ 6720 // This is a Power7 instruction for which no machine description exists. 6721 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 6722 __ isel_0($dst$$Register, $crx$$CondRegister, Assembler::equal, $src1$$Register); 6723 %} 6724 ins_pipe(pipe_class_default); 6725 %} 6726 6727 // base != 0 6728 // 32G aligned narrow oop base. 6729 instruct encodeP_32GAligned(iRegNdst dst, iRegPsrc src) %{ 6730 match(Set dst (EncodeP src)); 6731 predicate(false /* TODO: PPC port Universe::narrow_oop_base_disjoint()*/); 6732 6733 format %{ "EXTRDI $dst, $src, #32, #3 \t// encode with 32G aligned base" %} 6734 size(4); 6735 ins_encode %{ 6736 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl); 6737 __ rldicl($dst$$Register, $src$$Register, 64-Universe::narrow_oop_shift(), 32); 6738 %} 6739 ins_pipe(pipe_class_default); 6740 %} 6741 6742 // shift != 0, base != 0 6743 instruct encodeP_Ex(iRegNdst dst, flagsReg crx, iRegPsrc src) %{ 6744 match(Set dst (EncodeP src)); 6745 effect(TEMP crx); 6746 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull && 6747 Universe::narrow_oop_shift() != 0 && 6748 true /* TODO: PPC port Universe::narrow_oop_base_overlaps()*/); 6749 6750 format %{ "EncodeP $dst, $crx, $src \t// postalloc expanded" %} 6751 postalloc_expand( postalloc_expand_encode_oop(dst, src, crx)); 6752 %} 6753 6754 // shift != 0, base != 0 6755 instruct encodeP_not_null_Ex(iRegNdst dst, iRegPsrc src) %{ 6756 match(Set dst (EncodeP src)); 6757 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull && 6758 Universe::narrow_oop_shift() != 0 && 6759 true /* TODO: PPC port Universe::narrow_oop_base_overlaps()*/); 6760 6761 format %{ "EncodeP $dst, $src\t// $src != Null, postalloc expanded" %} 6762 postalloc_expand( postalloc_expand_encode_oop_not_null(dst, src) ); 6763 %} 6764 6765 // shift != 0, base == 0 6766 // TODO: This is the same as encodeP_shift. Merge! 6767 instruct encodeP_not_null_base_null(iRegNdst dst, iRegPsrc src) %{ 6768 match(Set dst (EncodeP src)); 6769 predicate(Universe::narrow_oop_shift() != 0 && 6770 Universe::narrow_oop_base() ==0); 6771 6772 format %{ "SRDI $dst, $src, #3 \t// encodeP, $src != NULL" %} 6773 size(4); 6774 ins_encode %{ 6775 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl); 6776 __ srdi($dst$$Register, $src$$Register, Universe::narrow_oop_shift() & 0x3f); 6777 %} 6778 ins_pipe(pipe_class_default); 6779 %} 6780 6781 // Compressed OOPs with narrow_oop_shift == 0. 6782 // shift == 0, base == 0 6783 instruct encodeP_narrow_oop_shift_0(iRegNdst dst, iRegPsrc src) %{ 6784 match(Set dst (EncodeP src)); 6785 predicate(Universe::narrow_oop_shift() == 0); 6786 6787 format %{ "MR $dst, $src \t// Ptr->Narrow" %} 6788 // variable size, 0 or 4. 6789 ins_encode %{ 6790 // TODO: PPC port $archOpcode(ppc64Opcode_or); 6791 __ mr_if_needed($dst$$Register, $src$$Register); 6792 %} 6793 ins_pipe(pipe_class_default); 6794 %} 6795 6796 // Decode nodes. 6797 6798 // Shift node for expand. 6799 instruct decodeN_shift(iRegPdst dst, iRegPsrc src) %{ 6800 // The match rule is needed to make it a 'MachTypeNode'! 6801 match(Set dst (DecodeN src)); 6802 predicate(false); 6803 6804 format %{ "SLDI $dst, $src, #3 \t// DecodeN" %} 6805 size(4); 6806 ins_encode %{ 6807 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr); 6808 __ sldi($dst$$Register, $src$$Register, Universe::narrow_oop_shift()); 6809 %} 6810 ins_pipe(pipe_class_default); 6811 %} 6812 6813 // Add node for expand. 6814 instruct decodeN_add(iRegPdst dst, iRegPdst src) %{ 6815 // The match rule is needed to make it a 'MachTypeNode'! 6816 match(Set dst (DecodeN src)); 6817 predicate(false); 6818 6819 format %{ "ADD $dst, $src, R30 \t// DecodeN, add oop base" %} 6820 size(4); 6821 ins_encode %{ 6822 // TODO: PPC port $archOpcode(ppc64Opcode_add); 6823 __ add($dst$$Register, $src$$Register, R30); 6824 %} 6825 ins_pipe(pipe_class_default); 6826 %} 6827 6828 // conditianal add base for expand 6829 instruct cond_add_base(iRegPdst dst, flagsReg crx, iRegPsrc src1) %{ 6830 // The match rule is needed to make it a 'MachTypeNode'! 6831 // NOTICE that the rule is nonsense - we just have to make sure that: 6832 // - _matrule->_rChild->_opType == "DecodeN" (see InstructForm::captures_bottom_type() in formssel.cpp) 6833 // - we have to match 'crx' to avoid an "illegal USE of non-input: flagsReg crx" error in ADLC. 6834 match(Set dst (DecodeN (Binary crx src1))); 6835 predicate(false); 6836 6837 ins_variable_size_depending_on_alignment(true); 6838 6839 format %{ "BEQ $crx, done\n\t" 6840 "ADD $dst, $src1, R30 \t// DecodeN: add oop base if $src1 != NULL\n" 6841 "done:" %} 6842 size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling()) */? 12 : 8); 6843 ins_encode %{ 6844 // TODO: PPC port $archOpcode(ppc64Opcode_cmove); 6845 Label done; 6846 __ beq($crx$$CondRegister, done); 6847 __ add($dst$$Register, $src1$$Register, R30); 6848 // TODO PPC port __ endgroup_if_needed(_size == 12); 6849 __ bind(done); 6850 %} 6851 ins_pipe(pipe_class_default); 6852 %} 6853 6854 instruct cond_set_0_ptr(iRegPdst dst, flagsReg crx, iRegPsrc src1) %{ 6855 // The match rule is needed to make it a 'MachTypeNode'! 6856 // NOTICE that the rule is nonsense - we just have to make sure that: 6857 // - _matrule->_rChild->_opType == "DecodeN" (see InstructForm::captures_bottom_type() in formssel.cpp) 6858 // - we have to match 'crx' to avoid an "illegal USE of non-input: flagsReg crx" error in ADLC. 6859 match(Set dst (DecodeN (Binary crx src1))); 6860 predicate(false); 6861 6862 format %{ "CMOVE $dst, $crx eq, 0, $src1 \t// decode: preserve 0" %} 6863 size(4); 6864 ins_encode %{ 6865 // This is a Power7 instruction for which no machine description exists. 6866 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 6867 __ isel_0($dst$$Register, $crx$$CondRegister, Assembler::equal, $src1$$Register); 6868 %} 6869 ins_pipe(pipe_class_default); 6870 %} 6871 6872 // shift != 0, base != 0 6873 instruct decodeN_Ex(iRegPdst dst, iRegNsrc src, flagsReg crx) %{ 6874 match(Set dst (DecodeN src)); 6875 predicate((n->bottom_type()->is_oopptr()->ptr() != TypePtr::NotNull && 6876 n->bottom_type()->is_oopptr()->ptr() != TypePtr::Constant) && 6877 Universe::narrow_oop_shift() != 0 && 6878 Universe::narrow_oop_base() != 0); 6879 effect(TEMP crx); 6880 6881 format %{ "DecodeN $dst, $src \t// Kills $crx, postalloc expanded" %} 6882 postalloc_expand( postalloc_expand_decode_oop(dst, src, crx) ); 6883 %} 6884 6885 // shift != 0, base == 0 6886 instruct decodeN_nullBase(iRegPdst dst, iRegNsrc src) %{ 6887 match(Set dst (DecodeN src)); 6888 predicate(Universe::narrow_oop_shift() != 0 && 6889 Universe::narrow_oop_base() == 0); 6890 6891 format %{ "SLDI $dst, $src, #3 \t// DecodeN (zerobased)" %} 6892 size(4); 6893 ins_encode %{ 6894 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr); 6895 __ sldi($dst$$Register, $src$$Register, Universe::narrow_oop_shift()); 6896 %} 6897 ins_pipe(pipe_class_default); 6898 %} 6899 6900 // src != 0, shift != 0, base != 0 6901 instruct decodeN_notNull_addBase_Ex(iRegPdst dst, iRegNsrc src) %{ 6902 match(Set dst (DecodeN src)); 6903 predicate((n->bottom_type()->is_oopptr()->ptr() == TypePtr::NotNull || 6904 n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant) && 6905 Universe::narrow_oop_shift() != 0 && 6906 Universe::narrow_oop_base() != 0); 6907 6908 format %{ "DecodeN $dst, $src \t// $src != NULL, postalloc expanded" %} 6909 postalloc_expand( postalloc_expand_decode_oop_not_null(dst, src)); 6910 %} 6911 6912 // Compressed OOPs with narrow_oop_shift == 0. 6913 instruct decodeN_unscaled(iRegPdst dst, iRegNsrc src) %{ 6914 match(Set dst (DecodeN src)); 6915 predicate(Universe::narrow_oop_shift() == 0); 6916 ins_cost(DEFAULT_COST); 6917 6918 format %{ "MR $dst, $src \t// DecodeN (unscaled)" %} 6919 // variable size, 0 or 4. 6920 ins_encode %{ 6921 // TODO: PPC port $archOpcode(ppc64Opcode_or); 6922 __ mr_if_needed($dst$$Register, $src$$Register); 6923 %} 6924 ins_pipe(pipe_class_default); 6925 %} 6926 6927 // Convert compressed oop into int for vectors alignment masking. 6928 instruct decodeN2I_unscaled(iRegIdst dst, iRegNsrc src) %{ 6929 match(Set dst (ConvL2I (CastP2X (DecodeN src)))); 6930 predicate(Universe::narrow_oop_shift() == 0); 6931 ins_cost(DEFAULT_COST); 6932 6933 format %{ "MR $dst, $src \t// (int)DecodeN (unscaled)" %} 6934 // variable size, 0 or 4. 6935 ins_encode %{ 6936 // TODO: PPC port $archOpcode(ppc64Opcode_or); 6937 __ mr_if_needed($dst$$Register, $src$$Register); 6938 %} 6939 ins_pipe(pipe_class_default); 6940 %} 6941 6942 // Convert klass pointer into compressed form. 6943 6944 // Nodes for postalloc expand. 6945 6946 // Shift node for expand. 6947 instruct encodePKlass_shift(iRegNdst dst, iRegNsrc src) %{ 6948 // The match rule is needed to make it a 'MachTypeNode'! 6949 match(Set dst (EncodePKlass src)); 6950 predicate(false); 6951 6952 format %{ "SRDI $dst, $src, 3 \t// encode" %} 6953 size(4); 6954 ins_encode %{ 6955 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl); 6956 __ srdi($dst$$Register, $src$$Register, Universe::narrow_klass_shift()); 6957 %} 6958 ins_pipe(pipe_class_default); 6959 %} 6960 6961 // Add node for expand. 6962 instruct encodePKlass_sub_base(iRegPdst dst, iRegLsrc base, iRegPdst src) %{ 6963 // The match rule is needed to make it a 'MachTypeNode'! 6964 match(Set dst (EncodePKlass (Binary base src))); 6965 predicate(false); 6966 6967 format %{ "SUB $dst, $base, $src \t// encode" %} 6968 size(4); 6969 ins_encode %{ 6970 // TODO: PPC port $archOpcode(ppc64Opcode_subf); 6971 __ subf($dst$$Register, $base$$Register, $src$$Register); 6972 %} 6973 ins_pipe(pipe_class_default); 6974 %} 6975 6976 // base != 0 6977 // 32G aligned narrow oop base. 6978 instruct encodePKlass_32GAligned(iRegNdst dst, iRegPsrc src) %{ 6979 match(Set dst (EncodePKlass src)); 6980 predicate(false /* TODO: PPC port Universe::narrow_klass_base_disjoint()*/); 6981 6982 format %{ "EXTRDI $dst, $src, #32, #3 \t// encode with 32G aligned base" %} 6983 size(4); 6984 ins_encode %{ 6985 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl); 6986 __ rldicl($dst$$Register, $src$$Register, 64-Universe::narrow_klass_shift(), 32); 6987 %} 6988 ins_pipe(pipe_class_default); 6989 %} 6990 6991 // shift != 0, base != 0 6992 instruct encodePKlass_not_null_Ex(iRegNdst dst, iRegLsrc base, iRegPsrc src) %{ 6993 match(Set dst (EncodePKlass (Binary base src))); 6994 predicate(false); 6995 6996 format %{ "EncodePKlass $dst, $src\t// $src != Null, postalloc expanded" %} 6997 postalloc_expand %{ 6998 encodePKlass_sub_baseNode *n1 = new (C) encodePKlass_sub_baseNode(); 6999 n1->add_req(n_region, n_base, n_src); 7000 n1->_opnds[0] = op_dst; 7001 n1->_opnds[1] = op_base; 7002 n1->_opnds[2] = op_src; 7003 n1->_bottom_type = _bottom_type; 7004 7005 encodePKlass_shiftNode *n2 = new (C) encodePKlass_shiftNode(); 7006 n2->add_req(n_region, n1); 7007 n2->_opnds[0] = op_dst; 7008 n2->_opnds[1] = op_dst; 7009 n2->_bottom_type = _bottom_type; 7010 ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 7011 ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 7012 7013 nodes->push(n1); 7014 nodes->push(n2); 7015 %} 7016 %} 7017 7018 // shift != 0, base != 0 7019 instruct encodePKlass_not_null_ExEx(iRegNdst dst, iRegPsrc src) %{ 7020 match(Set dst (EncodePKlass src)); 7021 //predicate(Universe::narrow_klass_shift() != 0 && 7022 // true /* TODO: PPC port Universe::narrow_klass_base_overlaps()*/); 7023 7024 //format %{ "EncodePKlass $dst, $src\t// $src != Null, postalloc expanded" %} 7025 ins_cost(DEFAULT_COST*2); // Don't count constant. 7026 expand %{ 7027 immL baseImm %{ (jlong)(intptr_t)Universe::narrow_klass_base() %} 7028 iRegLdst base; 7029 loadConL_Ex(base, baseImm); 7030 encodePKlass_not_null_Ex(dst, base, src); 7031 %} 7032 %} 7033 7034 // Decode nodes. 7035 7036 // Shift node for expand. 7037 instruct decodeNKlass_shift(iRegPdst dst, iRegPsrc src) %{ 7038 // The match rule is needed to make it a 'MachTypeNode'! 7039 match(Set dst (DecodeNKlass src)); 7040 predicate(false); 7041 7042 format %{ "SLDI $dst, $src, #3 \t// DecodeNKlass" %} 7043 size(4); 7044 ins_encode %{ 7045 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr); 7046 __ sldi($dst$$Register, $src$$Register, Universe::narrow_klass_shift()); 7047 %} 7048 ins_pipe(pipe_class_default); 7049 %} 7050 7051 // Add node for expand. 7052 7053 instruct decodeNKlass_add_base(iRegPdst dst, iRegLsrc base, iRegPdst src) %{ 7054 // The match rule is needed to make it a 'MachTypeNode'! 7055 match(Set dst (DecodeNKlass (Binary base src))); 7056 predicate(false); 7057 7058 format %{ "ADD $dst, $base, $src \t// DecodeNKlass, add klass base" %} 7059 size(4); 7060 ins_encode %{ 7061 // TODO: PPC port $archOpcode(ppc64Opcode_add); 7062 __ add($dst$$Register, $base$$Register, $src$$Register); 7063 %} 7064 ins_pipe(pipe_class_default); 7065 %} 7066 7067 // src != 0, shift != 0, base != 0 7068 instruct decodeNKlass_notNull_addBase_Ex(iRegPdst dst, iRegLsrc base, iRegNsrc src) %{ 7069 match(Set dst (DecodeNKlass (Binary base src))); 7070 //effect(kill src); // We need a register for the immediate result after shifting. 7071 predicate(false); 7072 7073 format %{ "DecodeNKlass $dst = $base + ($src << 3) \t// $src != NULL, postalloc expanded" %} 7074 postalloc_expand %{ 7075 decodeNKlass_add_baseNode *n1 = new (C) decodeNKlass_add_baseNode(); 7076 n1->add_req(n_region, n_base, n_src); 7077 n1->_opnds[0] = op_dst; 7078 n1->_opnds[1] = op_base; 7079 n1->_opnds[2] = op_src; 7080 n1->_bottom_type = _bottom_type; 7081 7082 decodeNKlass_shiftNode *n2 = new (C) decodeNKlass_shiftNode(); 7083 n2->add_req(n_region, n1); 7084 n2->_opnds[0] = op_dst; 7085 n2->_opnds[1] = op_dst; 7086 n2->_bottom_type = _bottom_type; 7087 7088 ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 7089 ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 7090 7091 nodes->push(n1); 7092 nodes->push(n2); 7093 %} 7094 %} 7095 7096 // src != 0, shift != 0, base != 0 7097 instruct decodeNKlass_notNull_addBase_ExEx(iRegPdst dst, iRegNsrc src) %{ 7098 match(Set dst (DecodeNKlass src)); 7099 // predicate(Universe::narrow_klass_shift() != 0 && 7100 // Universe::narrow_klass_base() != 0); 7101 7102 //format %{ "DecodeNKlass $dst, $src \t// $src != NULL, expanded" %} 7103 7104 ins_cost(DEFAULT_COST*2); // Don't count constant. 7105 expand %{ 7106 // We add first, then we shift. Like this, we can get along with one register less. 7107 // But we have to load the base pre-shifted. 7108 immL baseImm %{ (jlong)((intptr_t)Universe::narrow_klass_base() >> Universe::narrow_klass_shift()) %} 7109 iRegLdst base; 7110 loadConL_Ex(base, baseImm); 7111 decodeNKlass_notNull_addBase_Ex(dst, base, src); 7112 %} 7113 %} 7114 7115 //----------MemBar Instructions----------------------------------------------- 7116 // Memory barrier flavors 7117 7118 instruct membar_acquire() %{ 7119 match(LoadFence); 7120 ins_cost(4*MEMORY_REF_COST); 7121 7122 format %{ "MEMBAR-acquire" %} 7123 size(4); 7124 ins_encode %{ 7125 // TODO: PPC port $archOpcode(ppc64Opcode_lwsync); 7126 __ acquire(); 7127 %} 7128 ins_pipe(pipe_class_default); 7129 %} 7130 7131 instruct unnecessary_membar_acquire() %{ 7132 match(MemBarAcquire); 7133 ins_cost(0); 7134 7135 format %{ " -- \t// redundant MEMBAR-acquire - empty" %} 7136 size(0); 7137 ins_encode( /*empty*/ ); 7138 ins_pipe(pipe_class_default); 7139 %} 7140 7141 instruct membar_acquire_lock() %{ 7142 match(MemBarAcquireLock); 7143 ins_cost(0); 7144 7145 format %{ " -- \t// redundant MEMBAR-acquire - empty (acquire as part of CAS in prior FastLock)" %} 7146 size(0); 7147 ins_encode( /*empty*/ ); 7148 ins_pipe(pipe_class_default); 7149 %} 7150 7151 instruct membar_release() %{ 7152 match(MemBarRelease); 7153 match(StoreFence); 7154 ins_cost(4*MEMORY_REF_COST); 7155 7156 format %{ "MEMBAR-release" %} 7157 size(4); 7158 ins_encode %{ 7159 // TODO: PPC port $archOpcode(ppc64Opcode_lwsync); 7160 __ release(); 7161 %} 7162 ins_pipe(pipe_class_default); 7163 %} 7164 7165 instruct membar_storestore() %{ 7166 match(MemBarStoreStore); 7167 ins_cost(4*MEMORY_REF_COST); 7168 7169 format %{ "MEMBAR-store-store" %} 7170 size(4); 7171 ins_encode %{ 7172 // TODO: PPC port $archOpcode(ppc64Opcode_lwsync); 7173 __ membar(Assembler::StoreStore); 7174 %} 7175 ins_pipe(pipe_class_default); 7176 %} 7177 7178 instruct membar_release_lock() %{ 7179 match(MemBarReleaseLock); 7180 ins_cost(0); 7181 7182 format %{ " -- \t// redundant MEMBAR-release - empty (release in FastUnlock)" %} 7183 size(0); 7184 ins_encode( /*empty*/ ); 7185 ins_pipe(pipe_class_default); 7186 %} 7187 7188 instruct membar_volatile() %{ 7189 match(MemBarVolatile); 7190 ins_cost(4*MEMORY_REF_COST); 7191 7192 format %{ "MEMBAR-volatile" %} 7193 size(4); 7194 ins_encode %{ 7195 // TODO: PPC port $archOpcode(ppc64Opcode_sync); 7196 __ fence(); 7197 %} 7198 ins_pipe(pipe_class_default); 7199 %} 7200 7201 // This optimization is wrong on PPC. The following pattern is not supported: 7202 // MemBarVolatile 7203 // ^ ^ 7204 // | | 7205 // CtrlProj MemProj 7206 // ^ ^ 7207 // | | 7208 // | Load 7209 // | 7210 // MemBarVolatile 7211 // 7212 // The first MemBarVolatile could get optimized out! According to 7213 // Vladimir, this pattern can not occur on Oracle platforms. 7214 // However, it does occur on PPC64 (because of membars in 7215 // inline_unsafe_load_store). 7216 // 7217 // Add this node again if we found a good solution for inline_unsafe_load_store(). 7218 // Don't forget to look at the implementation of post_store_load_barrier again, 7219 // we did other fixes in that method. 7220 //instruct unnecessary_membar_volatile() %{ 7221 // match(MemBarVolatile); 7222 // predicate(Matcher::post_store_load_barrier(n)); 7223 // ins_cost(0); 7224 // 7225 // format %{ " -- \t// redundant MEMBAR-volatile - empty" %} 7226 // size(0); 7227 // ins_encode( /*empty*/ ); 7228 // ins_pipe(pipe_class_default); 7229 //%} 7230 7231 instruct membar_CPUOrder() %{ 7232 match(MemBarCPUOrder); 7233 ins_cost(0); 7234 7235 format %{ " -- \t// MEMBAR-CPUOrder - empty: PPC64 processors are self-consistent." %} 7236 size(0); 7237 ins_encode( /*empty*/ ); 7238 ins_pipe(pipe_class_default); 7239 %} 7240 7241 //----------Conditional Move--------------------------------------------------- 7242 7243 // Cmove using isel. 7244 instruct cmovI_reg_isel(cmpOp cmp, flagsReg crx, iRegIdst dst, iRegIsrc src) %{ 7245 match(Set dst (CMoveI (Binary cmp crx) (Binary dst src))); 7246 predicate(VM_Version::has_isel()); 7247 ins_cost(DEFAULT_COST); 7248 7249 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %} 7250 size(4); 7251 ins_encode %{ 7252 // This is a Power7 instruction for which no machine description 7253 // exists. Anyways, the scheduler should be off on Power7. 7254 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 7255 int cc = $cmp$$cmpcode; 7256 __ isel($dst$$Register, $crx$$CondRegister, 7257 (Assembler::Condition)(cc & 3), /*invert*/((~cc) & 8), $src$$Register); 7258 %} 7259 ins_pipe(pipe_class_default); 7260 %} 7261 7262 instruct cmovI_reg(cmpOp cmp, flagsReg crx, iRegIdst dst, iRegIsrc src) %{ 7263 match(Set dst (CMoveI (Binary cmp crx) (Binary dst src))); 7264 predicate(!VM_Version::has_isel()); 7265 ins_cost(DEFAULT_COST+BRANCH_COST); 7266 7267 ins_variable_size_depending_on_alignment(true); 7268 7269 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %} 7270 // Worst case is branch + move + stop, no stop without scheduler 7271 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8); 7272 ins_encode( enc_cmove_reg(dst, crx, src, cmp) ); 7273 ins_pipe(pipe_class_default); 7274 %} 7275 7276 instruct cmovI_imm(cmpOp cmp, flagsReg crx, iRegIdst dst, immI16 src) %{ 7277 match(Set dst (CMoveI (Binary cmp crx) (Binary dst src))); 7278 ins_cost(DEFAULT_COST+BRANCH_COST); 7279 7280 ins_variable_size_depending_on_alignment(true); 7281 7282 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %} 7283 // Worst case is branch + move + stop, no stop without scheduler 7284 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8); 7285 ins_encode( enc_cmove_imm(dst, crx, src, cmp) ); 7286 ins_pipe(pipe_class_default); 7287 %} 7288 7289 // Cmove using isel. 7290 instruct cmovL_reg_isel(cmpOp cmp, flagsReg crx, iRegLdst dst, iRegLsrc src) %{ 7291 match(Set dst (CMoveL (Binary cmp crx) (Binary dst src))); 7292 predicate(VM_Version::has_isel()); 7293 ins_cost(DEFAULT_COST); 7294 7295 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %} 7296 size(4); 7297 ins_encode %{ 7298 // This is a Power7 instruction for which no machine description 7299 // exists. Anyways, the scheduler should be off on Power7. 7300 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 7301 int cc = $cmp$$cmpcode; 7302 __ isel($dst$$Register, $crx$$CondRegister, 7303 (Assembler::Condition)(cc & 3), /*invert*/((~cc) & 8), $src$$Register); 7304 %} 7305 ins_pipe(pipe_class_default); 7306 %} 7307 7308 instruct cmovL_reg(cmpOp cmp, flagsReg crx, iRegLdst dst, iRegLsrc src) %{ 7309 match(Set dst (CMoveL (Binary cmp crx) (Binary dst src))); 7310 predicate(!VM_Version::has_isel()); 7311 ins_cost(DEFAULT_COST+BRANCH_COST); 7312 7313 ins_variable_size_depending_on_alignment(true); 7314 7315 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %} 7316 // Worst case is branch + move + stop, no stop without scheduler. 7317 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8); 7318 ins_encode( enc_cmove_reg(dst, crx, src, cmp) ); 7319 ins_pipe(pipe_class_default); 7320 %} 7321 7322 instruct cmovL_imm(cmpOp cmp, flagsReg crx, iRegLdst dst, immL16 src) %{ 7323 match(Set dst (CMoveL (Binary cmp crx) (Binary dst src))); 7324 ins_cost(DEFAULT_COST+BRANCH_COST); 7325 7326 ins_variable_size_depending_on_alignment(true); 7327 7328 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %} 7329 // Worst case is branch + move + stop, no stop without scheduler. 7330 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8); 7331 ins_encode( enc_cmove_imm(dst, crx, src, cmp) ); 7332 ins_pipe(pipe_class_default); 7333 %} 7334 7335 // Cmove using isel. 7336 instruct cmovN_reg_isel(cmpOp cmp, flagsReg crx, iRegNdst dst, iRegNsrc src) %{ 7337 match(Set dst (CMoveN (Binary cmp crx) (Binary dst src))); 7338 predicate(VM_Version::has_isel()); 7339 ins_cost(DEFAULT_COST); 7340 7341 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %} 7342 size(4); 7343 ins_encode %{ 7344 // This is a Power7 instruction for which no machine description 7345 // exists. Anyways, the scheduler should be off on Power7. 7346 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 7347 int cc = $cmp$$cmpcode; 7348 __ isel($dst$$Register, $crx$$CondRegister, 7349 (Assembler::Condition)(cc & 3), /*invert*/((~cc) & 8), $src$$Register); 7350 %} 7351 ins_pipe(pipe_class_default); 7352 %} 7353 7354 // Conditional move for RegN. Only cmov(reg, reg). 7355 instruct cmovN_reg(cmpOp cmp, flagsReg crx, iRegNdst dst, iRegNsrc src) %{ 7356 match(Set dst (CMoveN (Binary cmp crx) (Binary dst src))); 7357 predicate(!VM_Version::has_isel()); 7358 ins_cost(DEFAULT_COST+BRANCH_COST); 7359 7360 ins_variable_size_depending_on_alignment(true); 7361 7362 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %} 7363 // Worst case is branch + move + stop, no stop without scheduler. 7364 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8); 7365 ins_encode( enc_cmove_reg(dst, crx, src, cmp) ); 7366 ins_pipe(pipe_class_default); 7367 %} 7368 7369 instruct cmovN_imm(cmpOp cmp, flagsReg crx, iRegNdst dst, immN_0 src) %{ 7370 match(Set dst (CMoveN (Binary cmp crx) (Binary dst src))); 7371 ins_cost(DEFAULT_COST+BRANCH_COST); 7372 7373 ins_variable_size_depending_on_alignment(true); 7374 7375 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %} 7376 // Worst case is branch + move + stop, no stop without scheduler. 7377 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8); 7378 ins_encode( enc_cmove_imm(dst, crx, src, cmp) ); 7379 ins_pipe(pipe_class_default); 7380 %} 7381 7382 // Cmove using isel. 7383 instruct cmovP_reg_isel(cmpOp cmp, flagsReg crx, iRegPdst dst, iRegPsrc src) %{ 7384 match(Set dst (CMoveP (Binary cmp crx) (Binary dst src))); 7385 predicate(VM_Version::has_isel()); 7386 ins_cost(DEFAULT_COST); 7387 7388 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %} 7389 size(4); 7390 ins_encode %{ 7391 // This is a Power7 instruction for which no machine description 7392 // exists. Anyways, the scheduler should be off on Power7. 7393 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 7394 int cc = $cmp$$cmpcode; 7395 __ isel($dst$$Register, $crx$$CondRegister, 7396 (Assembler::Condition)(cc & 3), /*invert*/((~cc) & 8), $src$$Register); 7397 %} 7398 ins_pipe(pipe_class_default); 7399 %} 7400 7401 instruct cmovP_reg(cmpOp cmp, flagsReg crx, iRegPdst dst, iRegP_N2P src) %{ 7402 match(Set dst (CMoveP (Binary cmp crx) (Binary dst src))); 7403 predicate(!VM_Version::has_isel()); 7404 ins_cost(DEFAULT_COST+BRANCH_COST); 7405 7406 ins_variable_size_depending_on_alignment(true); 7407 7408 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %} 7409 // Worst case is branch + move + stop, no stop without scheduler. 7410 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8); 7411 ins_encode( enc_cmove_reg(dst, crx, src, cmp) ); 7412 ins_pipe(pipe_class_default); 7413 %} 7414 7415 instruct cmovP_imm(cmpOp cmp, flagsReg crx, iRegPdst dst, immP_0 src) %{ 7416 match(Set dst (CMoveP (Binary cmp crx) (Binary dst src))); 7417 ins_cost(DEFAULT_COST+BRANCH_COST); 7418 7419 ins_variable_size_depending_on_alignment(true); 7420 7421 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %} 7422 // Worst case is branch + move + stop, no stop without scheduler. 7423 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8); 7424 ins_encode( enc_cmove_imm(dst, crx, src, cmp) ); 7425 ins_pipe(pipe_class_default); 7426 %} 7427 7428 instruct cmovF_reg(cmpOp cmp, flagsReg crx, regF dst, regF src) %{ 7429 match(Set dst (CMoveF (Binary cmp crx) (Binary dst src))); 7430 ins_cost(DEFAULT_COST+BRANCH_COST); 7431 7432 ins_variable_size_depending_on_alignment(true); 7433 7434 format %{ "CMOVEF $cmp, $crx, $dst, $src\n\t" %} 7435 // Worst case is branch + move + stop, no stop without scheduler. 7436 size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8); 7437 ins_encode %{ 7438 // TODO: PPC port $archOpcode(ppc64Opcode_cmovef); 7439 Label done; 7440 assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding"); 7441 // Branch if not (cmp crx). 7442 __ bc(cc_to_inverse_boint($cmp$$cmpcode), cc_to_biint($cmp$$cmpcode, $crx$$reg), done); 7443 __ fmr($dst$$FloatRegister, $src$$FloatRegister); 7444 // TODO PPC port __ endgroup_if_needed(_size == 12); 7445 __ bind(done); 7446 %} 7447 ins_pipe(pipe_class_default); 7448 %} 7449 7450 instruct cmovD_reg(cmpOp cmp, flagsReg crx, regD dst, regD src) %{ 7451 match(Set dst (CMoveD (Binary cmp crx) (Binary dst src))); 7452 ins_cost(DEFAULT_COST+BRANCH_COST); 7453 7454 ins_variable_size_depending_on_alignment(true); 7455 7456 format %{ "CMOVEF $cmp, $crx, $dst, $src\n\t" %} 7457 // Worst case is branch + move + stop, no stop without scheduler. 7458 size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8); 7459 ins_encode %{ 7460 // TODO: PPC port $archOpcode(ppc64Opcode_cmovef); 7461 Label done; 7462 assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding"); 7463 // Branch if not (cmp crx). 7464 __ bc(cc_to_inverse_boint($cmp$$cmpcode), cc_to_biint($cmp$$cmpcode, $crx$$reg), done); 7465 __ fmr($dst$$FloatRegister, $src$$FloatRegister); 7466 // TODO PPC port __ endgroup_if_needed(_size == 12); 7467 __ bind(done); 7468 %} 7469 ins_pipe(pipe_class_default); 7470 %} 7471 7472 //----------Conditional_store-------------------------------------------------- 7473 // Conditional-store of the updated heap-top. 7474 // Used during allocation of the shared heap. 7475 // Sets flags (EQ) on success. Implemented with a CASA on Sparc. 7476 7477 // As compareAndSwapL, but return flag register instead of boolean value in 7478 // int register. 7479 // Used by sun/misc/AtomicLongCSImpl.java. 7480 // Mem_ptr must be a memory operand, else this node does not get 7481 // Flag_needs_anti_dependence_check set by adlc. If this is not set this node 7482 // can be rematerialized which leads to errors. 7483 instruct storeLConditional_regP_regL_regL(flagsReg crx, indirect mem_ptr, iRegLsrc oldVal, iRegLsrc newVal) %{ 7484 match(Set crx (StoreLConditional mem_ptr (Binary oldVal newVal))); 7485 format %{ "CMPXCHGD if ($crx = ($oldVal == *$mem_ptr)) *mem_ptr = $newVal; as bool" %} 7486 ins_encode %{ 7487 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 7488 __ cmpxchgd($crx$$CondRegister, R0, $oldVal$$Register, $newVal$$Register, $mem_ptr$$Register, 7489 MacroAssembler::MemBarNone, MacroAssembler::cmpxchgx_hint_atomic_update(), 7490 noreg, NULL, true); 7491 %} 7492 ins_pipe(pipe_class_default); 7493 %} 7494 7495 // As compareAndSwapP, but return flag register instead of boolean value in 7496 // int register. 7497 // This instruction is matched if UseTLAB is off. 7498 // Mem_ptr must be a memory operand, else this node does not get 7499 // Flag_needs_anti_dependence_check set by adlc. If this is not set this node 7500 // can be rematerialized which leads to errors. 7501 instruct storePConditional_regP_regP_regP(flagsReg crx, indirect mem_ptr, iRegPsrc oldVal, iRegPsrc newVal) %{ 7502 match(Set crx (StorePConditional mem_ptr (Binary oldVal newVal))); 7503 format %{ "CMPXCHGD if ($crx = ($oldVal == *$mem_ptr)) *mem_ptr = $newVal; as bool" %} 7504 ins_encode %{ 7505 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 7506 __ cmpxchgd($crx$$CondRegister, R0, $oldVal$$Register, $newVal$$Register, $mem_ptr$$Register, 7507 MacroAssembler::MemBarNone, MacroAssembler::cmpxchgx_hint_atomic_update(), 7508 noreg, NULL, true); 7509 %} 7510 ins_pipe(pipe_class_default); 7511 %} 7512 7513 // Implement LoadPLocked. Must be ordered against changes of the memory location 7514 // by storePConditional. 7515 // Don't know whether this is ever used. 7516 instruct loadPLocked(iRegPdst dst, memory mem) %{ 7517 match(Set dst (LoadPLocked mem)); 7518 ins_cost(MEMORY_REF_COST); 7519 7520 format %{ "LD $dst, $mem \t// loadPLocked\n\t" 7521 "TWI $dst\n\t" 7522 "ISYNC" %} 7523 size(12); 7524 ins_encode( enc_ld_ac(dst, mem) ); 7525 ins_pipe(pipe_class_memory); 7526 %} 7527 7528 //----------Compare-And-Swap--------------------------------------------------- 7529 7530 // CompareAndSwap{P,I,L} have more than one output, therefore "CmpI 7531 // (CompareAndSwap ...)" or "If (CmpI (CompareAndSwap ..))" cannot be 7532 // matched. 7533 7534 instruct compareAndSwapI_regP_regI_regI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src1, iRegIsrc src2) %{ 7535 match(Set res (CompareAndSwapI mem_ptr (Binary src1 src2))); 7536 format %{ "CMPXCHGW $res, $mem_ptr, $src1, $src2; as bool" %} 7537 // Variable size: instruction count smaller if regs are disjoint. 7538 ins_encode %{ 7539 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 7540 // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'. 7541 __ cmpxchgw(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register, 7542 MacroAssembler::MemBarFenceAfter, MacroAssembler::cmpxchgx_hint_atomic_update(), 7543 $res$$Register, true); 7544 %} 7545 ins_pipe(pipe_class_default); 7546 %} 7547 7548 instruct compareAndSwapN_regP_regN_regN(iRegIdst res, iRegPdst mem_ptr, iRegNsrc src1, iRegNsrc src2) %{ 7549 match(Set res (CompareAndSwapN mem_ptr (Binary src1 src2))); 7550 format %{ "CMPXCHGW $res, $mem_ptr, $src1, $src2; as bool" %} 7551 // Variable size: instruction count smaller if regs are disjoint. 7552 ins_encode %{ 7553 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 7554 // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'. 7555 __ cmpxchgw(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register, 7556 MacroAssembler::MemBarFenceAfter, MacroAssembler::cmpxchgx_hint_atomic_update(), 7557 $res$$Register, true); 7558 %} 7559 ins_pipe(pipe_class_default); 7560 %} 7561 7562 instruct compareAndSwapL_regP_regL_regL(iRegIdst res, iRegPdst mem_ptr, iRegLsrc src1, iRegLsrc src2) %{ 7563 match(Set res (CompareAndSwapL mem_ptr (Binary src1 src2))); 7564 format %{ "CMPXCHGD $res, $mem_ptr, $src1, $src2; as bool" %} 7565 // Variable size: instruction count smaller if regs are disjoint. 7566 ins_encode %{ 7567 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 7568 // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'. 7569 __ cmpxchgd(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register, 7570 MacroAssembler::MemBarFenceAfter, MacroAssembler::cmpxchgx_hint_atomic_update(), 7571 $res$$Register, NULL, true); 7572 %} 7573 ins_pipe(pipe_class_default); 7574 %} 7575 7576 instruct compareAndSwapP_regP_regP_regP(iRegIdst res, iRegPdst mem_ptr, iRegPsrc src1, iRegPsrc src2) %{ 7577 match(Set res (CompareAndSwapP mem_ptr (Binary src1 src2))); 7578 format %{ "CMPXCHGD $res, $mem_ptr, $src1, $src2; as bool; ptr" %} 7579 // Variable size: instruction count smaller if regs are disjoint. 7580 ins_encode %{ 7581 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 7582 // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'. 7583 __ cmpxchgd(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register, 7584 MacroAssembler::MemBarFenceAfter, MacroAssembler::cmpxchgx_hint_atomic_update(), 7585 $res$$Register, NULL, true); 7586 %} 7587 ins_pipe(pipe_class_default); 7588 %} 7589 7590 instruct getAndAddI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src) %{ 7591 match(Set res (GetAndAddI mem_ptr src)); 7592 format %{ "GetAndAddI $res, $mem_ptr, $src" %} 7593 // Variable size: instruction count smaller if regs are disjoint. 7594 ins_encode( enc_GetAndAddI(res, mem_ptr, src) ); 7595 ins_pipe(pipe_class_default); 7596 %} 7597 7598 instruct getAndAddL(iRegLdst res, iRegPdst mem_ptr, iRegLsrc src) %{ 7599 match(Set res (GetAndAddL mem_ptr src)); 7600 format %{ "GetAndAddL $res, $mem_ptr, $src" %} 7601 // Variable size: instruction count smaller if regs are disjoint. 7602 ins_encode( enc_GetAndAddL(res, mem_ptr, src) ); 7603 ins_pipe(pipe_class_default); 7604 %} 7605 7606 instruct getAndSetI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src) %{ 7607 match(Set res (GetAndSetI mem_ptr src)); 7608 format %{ "GetAndSetI $res, $mem_ptr, $src" %} 7609 // Variable size: instruction count smaller if regs are disjoint. 7610 ins_encode( enc_GetAndSetI(res, mem_ptr, src) ); 7611 ins_pipe(pipe_class_default); 7612 %} 7613 7614 instruct getAndSetL(iRegLdst res, iRegPdst mem_ptr, iRegLsrc src) %{ 7615 match(Set res (GetAndSetL mem_ptr src)); 7616 format %{ "GetAndSetL $res, $mem_ptr, $src" %} 7617 // Variable size: instruction count smaller if regs are disjoint. 7618 ins_encode( enc_GetAndSetL(res, mem_ptr, src) ); 7619 ins_pipe(pipe_class_default); 7620 %} 7621 7622 instruct getAndSetP(iRegPdst res, iRegPdst mem_ptr, iRegPsrc src) %{ 7623 match(Set res (GetAndSetP mem_ptr src)); 7624 format %{ "GetAndSetP $res, $mem_ptr, $src" %} 7625 // Variable size: instruction count smaller if regs are disjoint. 7626 ins_encode( enc_GetAndSetL(res, mem_ptr, src) ); 7627 ins_pipe(pipe_class_default); 7628 %} 7629 7630 instruct getAndSetN(iRegNdst res, iRegPdst mem_ptr, iRegNsrc src) %{ 7631 match(Set res (GetAndSetN mem_ptr src)); 7632 format %{ "GetAndSetN $res, $mem_ptr, $src" %} 7633 // Variable size: instruction count smaller if regs are disjoint. 7634 ins_encode( enc_GetAndSetI(res, mem_ptr, src) ); 7635 ins_pipe(pipe_class_default); 7636 %} 7637 7638 //----------Arithmetic Instructions-------------------------------------------- 7639 // Addition Instructions 7640 7641 // Register Addition 7642 instruct addI_reg_reg(iRegIdst dst, iRegIsrc_iRegL2Isrc src1, iRegIsrc_iRegL2Isrc src2) %{ 7643 match(Set dst (AddI src1 src2)); 7644 format %{ "ADD $dst, $src1, $src2" %} 7645 size(4); 7646 ins_encode %{ 7647 // TODO: PPC port $archOpcode(ppc64Opcode_add); 7648 __ add($dst$$Register, $src1$$Register, $src2$$Register); 7649 %} 7650 ins_pipe(pipe_class_default); 7651 %} 7652 7653 // Expand does not work with above instruct. (??) 7654 instruct addI_reg_reg_2(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ 7655 // no match-rule 7656 effect(DEF dst, USE src1, USE src2); 7657 format %{ "ADD $dst, $src1, $src2" %} 7658 size(4); 7659 ins_encode %{ 7660 // TODO: PPC port $archOpcode(ppc64Opcode_add); 7661 __ add($dst$$Register, $src1$$Register, $src2$$Register); 7662 %} 7663 ins_pipe(pipe_class_default); 7664 %} 7665 7666 instruct tree_addI_addI_addI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2, iRegIsrc src3, iRegIsrc src4) %{ 7667 match(Set dst (AddI (AddI (AddI src1 src2) src3) src4)); 7668 ins_cost(DEFAULT_COST*3); 7669 7670 expand %{ 7671 // FIXME: we should do this in the ideal world. 7672 iRegIdst tmp1; 7673 iRegIdst tmp2; 7674 addI_reg_reg(tmp1, src1, src2); 7675 addI_reg_reg_2(tmp2, src3, src4); // Adlc complains about addI_reg_reg. 7676 addI_reg_reg(dst, tmp1, tmp2); 7677 %} 7678 %} 7679 7680 // Immediate Addition 7681 instruct addI_reg_imm16(iRegIdst dst, iRegIsrc src1, immI16 src2) %{ 7682 match(Set dst (AddI src1 src2)); 7683 format %{ "ADDI $dst, $src1, $src2" %} 7684 size(4); 7685 ins_encode %{ 7686 // TODO: PPC port $archOpcode(ppc64Opcode_addi); 7687 __ addi($dst$$Register, $src1$$Register, $src2$$constant); 7688 %} 7689 ins_pipe(pipe_class_default); 7690 %} 7691 7692 // Immediate Addition with 16-bit shifted operand 7693 instruct addI_reg_immhi16(iRegIdst dst, iRegIsrc src1, immIhi16 src2) %{ 7694 match(Set dst (AddI src1 src2)); 7695 format %{ "ADDIS $dst, $src1, $src2" %} 7696 size(4); 7697 ins_encode %{ 7698 // TODO: PPC port $archOpcode(ppc64Opcode_addis); 7699 __ addis($dst$$Register, $src1$$Register, ($src2$$constant)>>16); 7700 %} 7701 ins_pipe(pipe_class_default); 7702 %} 7703 7704 // Long Addition 7705 instruct addL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{ 7706 match(Set dst (AddL src1 src2)); 7707 format %{ "ADD $dst, $src1, $src2 \t// long" %} 7708 size(4); 7709 ins_encode %{ 7710 // TODO: PPC port $archOpcode(ppc64Opcode_add); 7711 __ add($dst$$Register, $src1$$Register, $src2$$Register); 7712 %} 7713 ins_pipe(pipe_class_default); 7714 %} 7715 7716 // Expand does not work with above instruct. (??) 7717 instruct addL_reg_reg_2(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{ 7718 // no match-rule 7719 effect(DEF dst, USE src1, USE src2); 7720 format %{ "ADD $dst, $src1, $src2 \t// long" %} 7721 size(4); 7722 ins_encode %{ 7723 // TODO: PPC port $archOpcode(ppc64Opcode_add); 7724 __ add($dst$$Register, $src1$$Register, $src2$$Register); 7725 %} 7726 ins_pipe(pipe_class_default); 7727 %} 7728 7729 instruct tree_addL_addL_addL_reg_reg_Ex(iRegLdst dst, iRegLsrc src1, iRegLsrc src2, iRegLsrc src3, iRegLsrc src4) %{ 7730 match(Set dst (AddL (AddL (AddL src1 src2) src3) src4)); 7731 ins_cost(DEFAULT_COST*3); 7732 7733 expand %{ 7734 // FIXME: we should do this in the ideal world. 7735 iRegLdst tmp1; 7736 iRegLdst tmp2; 7737 addL_reg_reg(tmp1, src1, src2); 7738 addL_reg_reg_2(tmp2, src3, src4); // Adlc complains about orI_reg_reg. 7739 addL_reg_reg(dst, tmp1, tmp2); 7740 %} 7741 %} 7742 7743 // AddL + ConvL2I. 7744 instruct addI_regL_regL(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{ 7745 match(Set dst (ConvL2I (AddL src1 src2))); 7746 7747 format %{ "ADD $dst, $src1, $src2 \t// long + l2i" %} 7748 size(4); 7749 ins_encode %{ 7750 // TODO: PPC port $archOpcode(ppc64Opcode_add); 7751 __ add($dst$$Register, $src1$$Register, $src2$$Register); 7752 %} 7753 ins_pipe(pipe_class_default); 7754 %} 7755 7756 // No constant pool entries required. 7757 instruct addL_reg_imm16(iRegLdst dst, iRegLsrc src1, immL16 src2) %{ 7758 match(Set dst (AddL src1 src2)); 7759 7760 format %{ "ADDI $dst, $src1, $src2" %} 7761 size(4); 7762 ins_encode %{ 7763 // TODO: PPC port $archOpcode(ppc64Opcode_addi); 7764 __ addi($dst$$Register, $src1$$Register, $src2$$constant); 7765 %} 7766 ins_pipe(pipe_class_default); 7767 %} 7768 7769 // Long Immediate Addition with 16-bit shifted operand. 7770 // No constant pool entries required. 7771 instruct addL_reg_immhi16(iRegLdst dst, iRegLsrc src1, immL32hi16 src2) %{ 7772 match(Set dst (AddL src1 src2)); 7773 7774 format %{ "ADDIS $dst, $src1, $src2" %} 7775 size(4); 7776 ins_encode %{ 7777 // TODO: PPC port $archOpcode(ppc64Opcode_addis); 7778 __ addis($dst$$Register, $src1$$Register, ($src2$$constant)>>16); 7779 %} 7780 ins_pipe(pipe_class_default); 7781 %} 7782 7783 // Pointer Register Addition 7784 instruct addP_reg_reg(iRegPdst dst, iRegP_N2P src1, iRegLsrc src2) %{ 7785 match(Set dst (AddP src1 src2)); 7786 format %{ "ADD $dst, $src1, $src2" %} 7787 size(4); 7788 ins_encode %{ 7789 // TODO: PPC port $archOpcode(ppc64Opcode_add); 7790 __ add($dst$$Register, $src1$$Register, $src2$$Register); 7791 %} 7792 ins_pipe(pipe_class_default); 7793 %} 7794 7795 // Pointer Immediate Addition 7796 // No constant pool entries required. 7797 instruct addP_reg_imm16(iRegPdst dst, iRegP_N2P src1, immL16 src2) %{ 7798 match(Set dst (AddP src1 src2)); 7799 7800 format %{ "ADDI $dst, $src1, $src2" %} 7801 size(4); 7802 ins_encode %{ 7803 // TODO: PPC port $archOpcode(ppc64Opcode_addi); 7804 __ addi($dst$$Register, $src1$$Register, $src2$$constant); 7805 %} 7806 ins_pipe(pipe_class_default); 7807 %} 7808 7809 // Pointer Immediate Addition with 16-bit shifted operand. 7810 // No constant pool entries required. 7811 instruct addP_reg_immhi16(iRegPdst dst, iRegP_N2P src1, immL32hi16 src2) %{ 7812 match(Set dst (AddP src1 src2)); 7813 7814 format %{ "ADDIS $dst, $src1, $src2" %} 7815 size(4); 7816 ins_encode %{ 7817 // TODO: PPC port $archOpcode(ppc64Opcode_addis); 7818 __ addis($dst$$Register, $src1$$Register, ($src2$$constant)>>16); 7819 %} 7820 ins_pipe(pipe_class_default); 7821 %} 7822 7823 //--------------------- 7824 // Subtraction Instructions 7825 7826 // Register Subtraction 7827 instruct subI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ 7828 match(Set dst (SubI src1 src2)); 7829 format %{ "SUBF $dst, $src2, $src1" %} 7830 size(4); 7831 ins_encode %{ 7832 // TODO: PPC port $archOpcode(ppc64Opcode_subf); 7833 __ subf($dst$$Register, $src2$$Register, $src1$$Register); 7834 %} 7835 ins_pipe(pipe_class_default); 7836 %} 7837 7838 // Immediate Subtraction 7839 // The compiler converts "x-c0" into "x+ -c0" (see SubINode::Ideal), 7840 // so this rule seems to be unused. 7841 instruct subI_reg_imm16(iRegIdst dst, iRegIsrc src1, immI16 src2) %{ 7842 match(Set dst (SubI src1 src2)); 7843 format %{ "SUBI $dst, $src1, $src2" %} 7844 size(4); 7845 ins_encode %{ 7846 // TODO: PPC port $archOpcode(ppc64Opcode_addi); 7847 __ addi($dst$$Register, $src1$$Register, ($src2$$constant) * (-1)); 7848 %} 7849 ins_pipe(pipe_class_default); 7850 %} 7851 7852 // SubI from constant (using subfic). 7853 instruct subI_imm16_reg(iRegIdst dst, immI16 src1, iRegIsrc src2) %{ 7854 match(Set dst (SubI src1 src2)); 7855 format %{ "SUBI $dst, $src1, $src2" %} 7856 7857 size(4); 7858 ins_encode %{ 7859 // TODO: PPC port $archOpcode(ppc64Opcode_subfic); 7860 __ subfic($dst$$Register, $src2$$Register, $src1$$constant); 7861 %} 7862 ins_pipe(pipe_class_default); 7863 %} 7864 7865 // Turn the sign-bit of an integer into a 32-bit mask, 0x0...0 for 7866 // positive integers and 0xF...F for negative ones. 7867 instruct signmask32I_regI(iRegIdst dst, iRegIsrc src) %{ 7868 // no match-rule, false predicate 7869 effect(DEF dst, USE src); 7870 predicate(false); 7871 7872 format %{ "SRAWI $dst, $src, #31" %} 7873 size(4); 7874 ins_encode %{ 7875 // TODO: PPC port $archOpcode(ppc64Opcode_srawi); 7876 __ srawi($dst$$Register, $src$$Register, 0x1f); 7877 %} 7878 ins_pipe(pipe_class_default); 7879 %} 7880 7881 instruct absI_reg_Ex(iRegIdst dst, iRegIsrc src) %{ 7882 match(Set dst (AbsI src)); 7883 ins_cost(DEFAULT_COST*3); 7884 7885 expand %{ 7886 iRegIdst tmp1; 7887 iRegIdst tmp2; 7888 signmask32I_regI(tmp1, src); 7889 xorI_reg_reg(tmp2, tmp1, src); 7890 subI_reg_reg(dst, tmp2, tmp1); 7891 %} 7892 %} 7893 7894 instruct negI_regI(iRegIdst dst, immI_0 zero, iRegIsrc src2) %{ 7895 match(Set dst (SubI zero src2)); 7896 format %{ "NEG $dst, $src2" %} 7897 size(4); 7898 ins_encode %{ 7899 // TODO: PPC port $archOpcode(ppc64Opcode_neg); 7900 __ neg($dst$$Register, $src2$$Register); 7901 %} 7902 ins_pipe(pipe_class_default); 7903 %} 7904 7905 // Long subtraction 7906 instruct subL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{ 7907 match(Set dst (SubL src1 src2)); 7908 format %{ "SUBF $dst, $src2, $src1 \t// long" %} 7909 size(4); 7910 ins_encode %{ 7911 // TODO: PPC port $archOpcode(ppc64Opcode_subf); 7912 __ subf($dst$$Register, $src2$$Register, $src1$$Register); 7913 %} 7914 ins_pipe(pipe_class_default); 7915 %} 7916 7917 // SubL + convL2I. 7918 instruct subI_regL_regL(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{ 7919 match(Set dst (ConvL2I (SubL src1 src2))); 7920 7921 format %{ "SUBF $dst, $src2, $src1 \t// long + l2i" %} 7922 size(4); 7923 ins_encode %{ 7924 // TODO: PPC port $archOpcode(ppc64Opcode_subf); 7925 __ subf($dst$$Register, $src2$$Register, $src1$$Register); 7926 %} 7927 ins_pipe(pipe_class_default); 7928 %} 7929 7930 // Immediate Subtraction 7931 // The compiler converts "x-c0" into "x+ -c0" (see SubLNode::Ideal), 7932 // so this rule seems to be unused. 7933 // No constant pool entries required. 7934 instruct subL_reg_imm16(iRegLdst dst, iRegLsrc src1, immL16 src2) %{ 7935 match(Set dst (SubL src1 src2)); 7936 7937 format %{ "SUBI $dst, $src1, $src2 \t// long" %} 7938 size(4); 7939 ins_encode %{ 7940 // TODO: PPC port $archOpcode(ppc64Opcode_addi); 7941 __ addi($dst$$Register, $src1$$Register, ($src2$$constant) * (-1)); 7942 %} 7943 ins_pipe(pipe_class_default); 7944 %} 7945 7946 // Turn the sign-bit of a long into a 64-bit mask, 0x0...0 for 7947 // positive longs and 0xF...F for negative ones. 7948 instruct signmask64I_regL(iRegIdst dst, iRegLsrc src) %{ 7949 // no match-rule, false predicate 7950 effect(DEF dst, USE src); 7951 predicate(false); 7952 7953 format %{ "SRADI $dst, $src, #63" %} 7954 size(4); 7955 ins_encode %{ 7956 // TODO: PPC port $archOpcode(ppc64Opcode_sradi); 7957 __ sradi($dst$$Register, $src$$Register, 0x3f); 7958 %} 7959 ins_pipe(pipe_class_default); 7960 %} 7961 7962 // Turn the sign-bit of a long into a 64-bit mask, 0x0...0 for 7963 // positive longs and 0xF...F for negative ones. 7964 instruct signmask64L_regL(iRegLdst dst, iRegLsrc src) %{ 7965 // no match-rule, false predicate 7966 effect(DEF dst, USE src); 7967 predicate(false); 7968 7969 format %{ "SRADI $dst, $src, #63" %} 7970 size(4); 7971 ins_encode %{ 7972 // TODO: PPC port $archOpcode(ppc64Opcode_sradi); 7973 __ sradi($dst$$Register, $src$$Register, 0x3f); 7974 %} 7975 ins_pipe(pipe_class_default); 7976 %} 7977 7978 // Long negation 7979 instruct negL_reg_reg(iRegLdst dst, immL_0 zero, iRegLsrc src2) %{ 7980 match(Set dst (SubL zero src2)); 7981 format %{ "NEG $dst, $src2 \t// long" %} 7982 size(4); 7983 ins_encode %{ 7984 // TODO: PPC port $archOpcode(ppc64Opcode_neg); 7985 __ neg($dst$$Register, $src2$$Register); 7986 %} 7987 ins_pipe(pipe_class_default); 7988 %} 7989 7990 // NegL + ConvL2I. 7991 instruct negI_con0_regL(iRegIdst dst, immL_0 zero, iRegLsrc src2) %{ 7992 match(Set dst (ConvL2I (SubL zero src2))); 7993 7994 format %{ "NEG $dst, $src2 \t// long + l2i" %} 7995 size(4); 7996 ins_encode %{ 7997 // TODO: PPC port $archOpcode(ppc64Opcode_neg); 7998 __ neg($dst$$Register, $src2$$Register); 7999 %} 8000 ins_pipe(pipe_class_default); 8001 %} 8002 8003 // Multiplication Instructions 8004 // Integer Multiplication 8005 8006 // Register Multiplication 8007 instruct mulI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ 8008 match(Set dst (MulI src1 src2)); 8009 ins_cost(DEFAULT_COST); 8010 8011 format %{ "MULLW $dst, $src1, $src2" %} 8012 size(4); 8013 ins_encode %{ 8014 // TODO: PPC port $archOpcode(ppc64Opcode_mullw); 8015 __ mullw($dst$$Register, $src1$$Register, $src2$$Register); 8016 %} 8017 ins_pipe(pipe_class_default); 8018 %} 8019 8020 // Immediate Multiplication 8021 instruct mulI_reg_imm16(iRegIdst dst, iRegIsrc src1, immI16 src2) %{ 8022 match(Set dst (MulI src1 src2)); 8023 ins_cost(DEFAULT_COST); 8024 8025 format %{ "MULLI $dst, $src1, $src2" %} 8026 size(4); 8027 ins_encode %{ 8028 // TODO: PPC port $archOpcode(ppc64Opcode_mulli); 8029 __ mulli($dst$$Register, $src1$$Register, $src2$$constant); 8030 %} 8031 ins_pipe(pipe_class_default); 8032 %} 8033 8034 instruct mulL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{ 8035 match(Set dst (MulL src1 src2)); 8036 ins_cost(DEFAULT_COST); 8037 8038 format %{ "MULLD $dst $src1, $src2 \t// long" %} 8039 size(4); 8040 ins_encode %{ 8041 // TODO: PPC port $archOpcode(ppc64Opcode_mulld); 8042 __ mulld($dst$$Register, $src1$$Register, $src2$$Register); 8043 %} 8044 ins_pipe(pipe_class_default); 8045 %} 8046 8047 // Multiply high for optimized long division by constant. 8048 instruct mulHighL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{ 8049 match(Set dst (MulHiL src1 src2)); 8050 ins_cost(DEFAULT_COST); 8051 8052 format %{ "MULHD $dst $src1, $src2 \t// long" %} 8053 size(4); 8054 ins_encode %{ 8055 // TODO: PPC port $archOpcode(ppc64Opcode_mulhd); 8056 __ mulhd($dst$$Register, $src1$$Register, $src2$$Register); 8057 %} 8058 ins_pipe(pipe_class_default); 8059 %} 8060 8061 // Immediate Multiplication 8062 instruct mulL_reg_imm16(iRegLdst dst, iRegLsrc src1, immL16 src2) %{ 8063 match(Set dst (MulL src1 src2)); 8064 ins_cost(DEFAULT_COST); 8065 8066 format %{ "MULLI $dst, $src1, $src2" %} 8067 size(4); 8068 ins_encode %{ 8069 // TODO: PPC port $archOpcode(ppc64Opcode_mulli); 8070 __ mulli($dst$$Register, $src1$$Register, $src2$$constant); 8071 %} 8072 ins_pipe(pipe_class_default); 8073 %} 8074 8075 // Integer Division with Immediate -1: Negate. 8076 instruct divI_reg_immIvalueMinus1(iRegIdst dst, iRegIsrc src1, immI_minus1 src2) %{ 8077 match(Set dst (DivI src1 src2)); 8078 ins_cost(DEFAULT_COST); 8079 8080 format %{ "NEG $dst, $src1 \t// /-1" %} 8081 size(4); 8082 ins_encode %{ 8083 // TODO: PPC port $archOpcode(ppc64Opcode_neg); 8084 __ neg($dst$$Register, $src1$$Register); 8085 %} 8086 ins_pipe(pipe_class_default); 8087 %} 8088 8089 // Integer Division with constant, but not -1. 8090 // We should be able to improve this by checking the type of src2. 8091 // It might well be that src2 is known to be positive. 8092 instruct divI_reg_regnotMinus1(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ 8093 match(Set dst (DivI src1 src2)); 8094 predicate(n->in(2)->find_int_con(-1) != -1); // src2 is a constant, but not -1 8095 ins_cost(2*DEFAULT_COST); 8096 8097 format %{ "DIVW $dst, $src1, $src2 \t// /not-1" %} 8098 size(4); 8099 ins_encode %{ 8100 // TODO: PPC port $archOpcode(ppc64Opcode_divw); 8101 __ divw($dst$$Register, $src1$$Register, $src2$$Register); 8102 %} 8103 ins_pipe(pipe_class_default); 8104 %} 8105 8106 instruct cmovI_bne_negI_reg(iRegIdst dst, flagsReg crx, iRegIsrc src1) %{ 8107 effect(USE_DEF dst, USE src1, USE crx); 8108 predicate(false); 8109 8110 ins_variable_size_depending_on_alignment(true); 8111 8112 format %{ "CMOVE $dst, neg($src1), $crx" %} 8113 // Worst case is branch + move + stop, no stop without scheduler. 8114 size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8); 8115 ins_encode %{ 8116 // TODO: PPC port $archOpcode(ppc64Opcode_cmove); 8117 Label done; 8118 __ bne($crx$$CondRegister, done); 8119 __ neg($dst$$Register, $src1$$Register); 8120 // TODO PPC port __ endgroup_if_needed(_size == 12); 8121 __ bind(done); 8122 %} 8123 ins_pipe(pipe_class_default); 8124 %} 8125 8126 // Integer Division with Registers not containing constants. 8127 instruct divI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ 8128 match(Set dst (DivI src1 src2)); 8129 ins_cost(10*DEFAULT_COST); 8130 8131 expand %{ 8132 immI16 imm %{ (int)-1 %} 8133 flagsReg tmp1; 8134 cmpI_reg_imm16(tmp1, src2, imm); // check src2 == -1 8135 divI_reg_regnotMinus1(dst, src1, src2); // dst = src1 / src2 8136 cmovI_bne_negI_reg(dst, tmp1, src1); // cmove dst = neg(src1) if src2 == -1 8137 %} 8138 %} 8139 8140 // Long Division with Immediate -1: Negate. 8141 instruct divL_reg_immLvalueMinus1(iRegLdst dst, iRegLsrc src1, immL_minus1 src2) %{ 8142 match(Set dst (DivL src1 src2)); 8143 ins_cost(DEFAULT_COST); 8144 8145 format %{ "NEG $dst, $src1 \t// /-1, long" %} 8146 size(4); 8147 ins_encode %{ 8148 // TODO: PPC port $archOpcode(ppc64Opcode_neg); 8149 __ neg($dst$$Register, $src1$$Register); 8150 %} 8151 ins_pipe(pipe_class_default); 8152 %} 8153 8154 // Long Division with constant, but not -1. 8155 instruct divL_reg_regnotMinus1(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{ 8156 match(Set dst (DivL src1 src2)); 8157 predicate(n->in(2)->find_long_con(-1L) != -1L); // Src2 is a constant, but not -1. 8158 ins_cost(2*DEFAULT_COST); 8159 8160 format %{ "DIVD $dst, $src1, $src2 \t// /not-1, long" %} 8161 size(4); 8162 ins_encode %{ 8163 // TODO: PPC port $archOpcode(ppc64Opcode_divd); 8164 __ divd($dst$$Register, $src1$$Register, $src2$$Register); 8165 %} 8166 ins_pipe(pipe_class_default); 8167 %} 8168 8169 instruct cmovL_bne_negL_reg(iRegLdst dst, flagsReg crx, iRegLsrc src1) %{ 8170 effect(USE_DEF dst, USE src1, USE crx); 8171 predicate(false); 8172 8173 ins_variable_size_depending_on_alignment(true); 8174 8175 format %{ "CMOVE $dst, neg($src1), $crx" %} 8176 // Worst case is branch + move + stop, no stop without scheduler. 8177 size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8); 8178 ins_encode %{ 8179 // TODO: PPC port $archOpcode(ppc64Opcode_cmove); 8180 Label done; 8181 __ bne($crx$$CondRegister, done); 8182 __ neg($dst$$Register, $src1$$Register); 8183 // TODO PPC port __ endgroup_if_needed(_size == 12); 8184 __ bind(done); 8185 %} 8186 ins_pipe(pipe_class_default); 8187 %} 8188 8189 // Long Division with Registers not containing constants. 8190 instruct divL_reg_reg_Ex(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{ 8191 match(Set dst (DivL src1 src2)); 8192 ins_cost(10*DEFAULT_COST); 8193 8194 expand %{ 8195 immL16 imm %{ (int)-1 %} 8196 flagsReg tmp1; 8197 cmpL_reg_imm16(tmp1, src2, imm); // check src2 == -1 8198 divL_reg_regnotMinus1(dst, src1, src2); // dst = src1 / src2 8199 cmovL_bne_negL_reg(dst, tmp1, src1); // cmove dst = neg(src1) if src2 == -1 8200 %} 8201 %} 8202 8203 // Integer Remainder with registers. 8204 instruct modI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ 8205 match(Set dst (ModI src1 src2)); 8206 ins_cost(10*DEFAULT_COST); 8207 8208 expand %{ 8209 immI16 imm %{ (int)-1 %} 8210 flagsReg tmp1; 8211 iRegIdst tmp2; 8212 iRegIdst tmp3; 8213 cmpI_reg_imm16(tmp1, src2, imm); // check src2 == -1 8214 divI_reg_regnotMinus1(tmp2, src1, src2); // tmp2 = src1 / src2 8215 cmovI_bne_negI_reg(tmp2, tmp1, src1); // cmove tmp2 = neg(src1) if src2 == -1 8216 mulI_reg_reg(tmp3, src2, tmp2); // tmp3 = src2 * tmp2 8217 subI_reg_reg(dst, src1, tmp3); // dst = src1 - tmp3 8218 %} 8219 %} 8220 8221 // Long Remainder with registers 8222 instruct modL_reg_reg_Ex(iRegLdst dst, iRegLsrc src1, iRegLsrc src2, flagsRegCR0 cr0) %{ 8223 match(Set dst (ModL src1 src2)); 8224 ins_cost(10*DEFAULT_COST); 8225 8226 expand %{ 8227 immL16 imm %{ (int)-1 %} 8228 flagsReg tmp1; 8229 iRegLdst tmp2; 8230 iRegLdst tmp3; 8231 cmpL_reg_imm16(tmp1, src2, imm); // check src2 == -1 8232 divL_reg_regnotMinus1(tmp2, src1, src2); // tmp2 = src1 / src2 8233 cmovL_bne_negL_reg(tmp2, tmp1, src1); // cmove tmp2 = neg(src1) if src2 == -1 8234 mulL_reg_reg(tmp3, src2, tmp2); // tmp3 = src2 * tmp2 8235 subL_reg_reg(dst, src1, tmp3); // dst = src1 - tmp3 8236 %} 8237 %} 8238 8239 // Integer Shift Instructions 8240 8241 // Register Shift Left 8242 8243 // Clear all but the lowest #mask bits. 8244 // Used to normalize shift amounts in registers. 8245 instruct maskI_reg_imm(iRegIdst dst, iRegIsrc src, uimmI6 mask) %{ 8246 // no match-rule, false predicate 8247 effect(DEF dst, USE src, USE mask); 8248 predicate(false); 8249 8250 format %{ "MASK $dst, $src, $mask \t// clear $mask upper bits" %} 8251 size(4); 8252 ins_encode %{ 8253 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl); 8254 __ clrldi($dst$$Register, $src$$Register, $mask$$constant); 8255 %} 8256 ins_pipe(pipe_class_default); 8257 %} 8258 8259 instruct lShiftI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ 8260 // no match-rule, false predicate 8261 effect(DEF dst, USE src1, USE src2); 8262 predicate(false); 8263 8264 format %{ "SLW $dst, $src1, $src2" %} 8265 size(4); 8266 ins_encode %{ 8267 // TODO: PPC port $archOpcode(ppc64Opcode_slw); 8268 __ slw($dst$$Register, $src1$$Register, $src2$$Register); 8269 %} 8270 ins_pipe(pipe_class_default); 8271 %} 8272 8273 instruct lShiftI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ 8274 match(Set dst (LShiftI src1 src2)); 8275 ins_cost(DEFAULT_COST*2); 8276 expand %{ 8277 uimmI6 mask %{ 0x3b /* clear 59 bits, keep 5 */ %} 8278 iRegIdst tmpI; 8279 maskI_reg_imm(tmpI, src2, mask); 8280 lShiftI_reg_reg(dst, src1, tmpI); 8281 %} 8282 %} 8283 8284 // Register Shift Left Immediate 8285 instruct lShiftI_reg_imm(iRegIdst dst, iRegIsrc src1, immI src2) %{ 8286 match(Set dst (LShiftI src1 src2)); 8287 8288 format %{ "SLWI $dst, $src1, ($src2 & 0x1f)" %} 8289 size(4); 8290 ins_encode %{ 8291 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm); 8292 __ slwi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x1f); 8293 %} 8294 ins_pipe(pipe_class_default); 8295 %} 8296 8297 // AndI with negpow2-constant + LShiftI 8298 instruct lShiftI_andI_immInegpow2_imm5(iRegIdst dst, iRegIsrc src1, immInegpow2 src2, uimmI5 src3) %{ 8299 match(Set dst (LShiftI (AndI src1 src2) src3)); 8300 predicate(UseRotateAndMaskInstructionsPPC64); 8301 8302 format %{ "RLWINM $dst, lShiftI(AndI($src1, $src2), $src3)" %} 8303 size(4); 8304 ins_encode %{ 8305 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm); // FIXME: assert that rlwinm is equal to addi 8306 long src2 = $src2$$constant; 8307 long src3 = $src3$$constant; 8308 long maskbits = src3 + log2_long((jlong) (julong) (juint) -src2); 8309 if (maskbits >= 32) { 8310 __ li($dst$$Register, 0); // addi 8311 } else { 8312 __ rlwinm($dst$$Register, $src1$$Register, src3 & 0x1f, 0, (31-maskbits) & 0x1f); 8313 } 8314 %} 8315 ins_pipe(pipe_class_default); 8316 %} 8317 8318 // RShiftI + AndI with negpow2-constant + LShiftI 8319 instruct lShiftI_andI_immInegpow2_rShiftI_imm5(iRegIdst dst, iRegIsrc src1, immInegpow2 src2, uimmI5 src3) %{ 8320 match(Set dst (LShiftI (AndI (RShiftI src1 src3) src2) src3)); 8321 predicate(UseRotateAndMaskInstructionsPPC64); 8322 8323 format %{ "RLWINM $dst, lShiftI(AndI(RShiftI($src1, $src3), $src2), $src3)" %} 8324 size(4); 8325 ins_encode %{ 8326 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm); // FIXME: assert that rlwinm is equal to addi 8327 long src2 = $src2$$constant; 8328 long src3 = $src3$$constant; 8329 long maskbits = src3 + log2_long((jlong) (julong) (juint) -src2); 8330 if (maskbits >= 32) { 8331 __ li($dst$$Register, 0); // addi 8332 } else { 8333 __ rlwinm($dst$$Register, $src1$$Register, 0, 0, (31-maskbits) & 0x1f); 8334 } 8335 %} 8336 ins_pipe(pipe_class_default); 8337 %} 8338 8339 instruct lShiftL_regL_regI(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{ 8340 // no match-rule, false predicate 8341 effect(DEF dst, USE src1, USE src2); 8342 predicate(false); 8343 8344 format %{ "SLD $dst, $src1, $src2" %} 8345 size(4); 8346 ins_encode %{ 8347 // TODO: PPC port $archOpcode(ppc64Opcode_sld); 8348 __ sld($dst$$Register, $src1$$Register, $src2$$Register); 8349 %} 8350 ins_pipe(pipe_class_default); 8351 %} 8352 8353 // Register Shift Left 8354 instruct lShiftL_regL_regI_Ex(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{ 8355 match(Set dst (LShiftL src1 src2)); 8356 ins_cost(DEFAULT_COST*2); 8357 expand %{ 8358 uimmI6 mask %{ 0x3a /* clear 58 bits, keep 6 */ %} 8359 iRegIdst tmpI; 8360 maskI_reg_imm(tmpI, src2, mask); 8361 lShiftL_regL_regI(dst, src1, tmpI); 8362 %} 8363 %} 8364 8365 // Register Shift Left Immediate 8366 instruct lshiftL_regL_immI(iRegLdst dst, iRegLsrc src1, immI src2) %{ 8367 match(Set dst (LShiftL src1 src2)); 8368 format %{ "SLDI $dst, $src1, ($src2 & 0x3f)" %} 8369 size(4); 8370 ins_encode %{ 8371 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr); 8372 __ sldi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f); 8373 %} 8374 ins_pipe(pipe_class_default); 8375 %} 8376 8377 // If we shift more than 32 bits, we need not convert I2L. 8378 instruct lShiftL_regI_immGE32(iRegLdst dst, iRegIsrc src1, uimmI6_ge32 src2) %{ 8379 match(Set dst (LShiftL (ConvI2L src1) src2)); 8380 ins_cost(DEFAULT_COST); 8381 8382 size(4); 8383 format %{ "SLDI $dst, i2l($src1), $src2" %} 8384 ins_encode %{ 8385 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr); 8386 __ sldi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f); 8387 %} 8388 ins_pipe(pipe_class_default); 8389 %} 8390 8391 // Shift a postivie int to the left. 8392 // Clrlsldi clears the upper 32 bits and shifts. 8393 instruct scaledPositiveI2L_lShiftL_convI2L_reg_imm6(iRegLdst dst, iRegIsrc src1, uimmI6 src2) %{ 8394 match(Set dst (LShiftL (ConvI2L src1) src2)); 8395 predicate(((ConvI2LNode*)(_kids[0]->_leaf))->type()->is_long()->is_positive_int()); 8396 8397 format %{ "SLDI $dst, i2l(positive_int($src1)), $src2" %} 8398 size(4); 8399 ins_encode %{ 8400 // TODO: PPC port $archOpcode(ppc64Opcode_rldic); 8401 __ clrlsldi($dst$$Register, $src1$$Register, 0x20, $src2$$constant); 8402 %} 8403 ins_pipe(pipe_class_default); 8404 %} 8405 8406 instruct arShiftI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ 8407 // no match-rule, false predicate 8408 effect(DEF dst, USE src1, USE src2); 8409 predicate(false); 8410 8411 format %{ "SRAW $dst, $src1, $src2" %} 8412 size(4); 8413 ins_encode %{ 8414 // TODO: PPC port $archOpcode(ppc64Opcode_sraw); 8415 __ sraw($dst$$Register, $src1$$Register, $src2$$Register); 8416 %} 8417 ins_pipe(pipe_class_default); 8418 %} 8419 8420 // Register Arithmetic Shift Right 8421 instruct arShiftI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ 8422 match(Set dst (RShiftI src1 src2)); 8423 ins_cost(DEFAULT_COST*2); 8424 expand %{ 8425 uimmI6 mask %{ 0x3b /* clear 59 bits, keep 5 */ %} 8426 iRegIdst tmpI; 8427 maskI_reg_imm(tmpI, src2, mask); 8428 arShiftI_reg_reg(dst, src1, tmpI); 8429 %} 8430 %} 8431 8432 // Register Arithmetic Shift Right Immediate 8433 instruct arShiftI_reg_imm(iRegIdst dst, iRegIsrc src1, immI src2) %{ 8434 match(Set dst (RShiftI src1 src2)); 8435 8436 format %{ "SRAWI $dst, $src1, ($src2 & 0x1f)" %} 8437 size(4); 8438 ins_encode %{ 8439 // TODO: PPC port $archOpcode(ppc64Opcode_srawi); 8440 __ srawi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x1f); 8441 %} 8442 ins_pipe(pipe_class_default); 8443 %} 8444 8445 instruct arShiftL_regL_regI(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{ 8446 // no match-rule, false predicate 8447 effect(DEF dst, USE src1, USE src2); 8448 predicate(false); 8449 8450 format %{ "SRAD $dst, $src1, $src2" %} 8451 size(4); 8452 ins_encode %{ 8453 // TODO: PPC port $archOpcode(ppc64Opcode_srad); 8454 __ srad($dst$$Register, $src1$$Register, $src2$$Register); 8455 %} 8456 ins_pipe(pipe_class_default); 8457 %} 8458 8459 // Register Shift Right Arithmetic Long 8460 instruct arShiftL_regL_regI_Ex(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{ 8461 match(Set dst (RShiftL src1 src2)); 8462 ins_cost(DEFAULT_COST*2); 8463 8464 expand %{ 8465 uimmI6 mask %{ 0x3a /* clear 58 bits, keep 6 */ %} 8466 iRegIdst tmpI; 8467 maskI_reg_imm(tmpI, src2, mask); 8468 arShiftL_regL_regI(dst, src1, tmpI); 8469 %} 8470 %} 8471 8472 // Register Shift Right Immediate 8473 instruct arShiftL_regL_immI(iRegLdst dst, iRegLsrc src1, immI src2) %{ 8474 match(Set dst (RShiftL src1 src2)); 8475 8476 format %{ "SRADI $dst, $src1, ($src2 & 0x3f)" %} 8477 size(4); 8478 ins_encode %{ 8479 // TODO: PPC port $archOpcode(ppc64Opcode_sradi); 8480 __ sradi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f); 8481 %} 8482 ins_pipe(pipe_class_default); 8483 %} 8484 8485 // RShiftL + ConvL2I 8486 instruct convL2I_arShiftL_regL_immI(iRegIdst dst, iRegLsrc src1, immI src2) %{ 8487 match(Set dst (ConvL2I (RShiftL src1 src2))); 8488 8489 format %{ "SRADI $dst, $src1, ($src2 & 0x3f) \t// long + l2i" %} 8490 size(4); 8491 ins_encode %{ 8492 // TODO: PPC port $archOpcode(ppc64Opcode_sradi); 8493 __ sradi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f); 8494 %} 8495 ins_pipe(pipe_class_default); 8496 %} 8497 8498 instruct urShiftI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ 8499 // no match-rule, false predicate 8500 effect(DEF dst, USE src1, USE src2); 8501 predicate(false); 8502 8503 format %{ "SRW $dst, $src1, $src2" %} 8504 size(4); 8505 ins_encode %{ 8506 // TODO: PPC port $archOpcode(ppc64Opcode_srw); 8507 __ srw($dst$$Register, $src1$$Register, $src2$$Register); 8508 %} 8509 ins_pipe(pipe_class_default); 8510 %} 8511 8512 // Register Shift Right 8513 instruct urShiftI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ 8514 match(Set dst (URShiftI src1 src2)); 8515 ins_cost(DEFAULT_COST*2); 8516 8517 expand %{ 8518 uimmI6 mask %{ 0x3b /* clear 59 bits, keep 5 */ %} 8519 iRegIdst tmpI; 8520 maskI_reg_imm(tmpI, src2, mask); 8521 urShiftI_reg_reg(dst, src1, tmpI); 8522 %} 8523 %} 8524 8525 // Register Shift Right Immediate 8526 instruct urShiftI_reg_imm(iRegIdst dst, iRegIsrc src1, immI src2) %{ 8527 match(Set dst (URShiftI src1 src2)); 8528 8529 format %{ "SRWI $dst, $src1, ($src2 & 0x1f)" %} 8530 size(4); 8531 ins_encode %{ 8532 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm); 8533 __ srwi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x1f); 8534 %} 8535 ins_pipe(pipe_class_default); 8536 %} 8537 8538 instruct urShiftL_regL_regI(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{ 8539 // no match-rule, false predicate 8540 effect(DEF dst, USE src1, USE src2); 8541 predicate(false); 8542 8543 format %{ "SRD $dst, $src1, $src2" %} 8544 size(4); 8545 ins_encode %{ 8546 // TODO: PPC port $archOpcode(ppc64Opcode_srd); 8547 __ srd($dst$$Register, $src1$$Register, $src2$$Register); 8548 %} 8549 ins_pipe(pipe_class_default); 8550 %} 8551 8552 // Register Shift Right 8553 instruct urShiftL_regL_regI_Ex(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{ 8554 match(Set dst (URShiftL src1 src2)); 8555 ins_cost(DEFAULT_COST*2); 8556 8557 expand %{ 8558 uimmI6 mask %{ 0x3a /* clear 58 bits, keep 6 */ %} 8559 iRegIdst tmpI; 8560 maskI_reg_imm(tmpI, src2, mask); 8561 urShiftL_regL_regI(dst, src1, tmpI); 8562 %} 8563 %} 8564 8565 // Register Shift Right Immediate 8566 instruct urShiftL_regL_immI(iRegLdst dst, iRegLsrc src1, immI src2) %{ 8567 match(Set dst (URShiftL src1 src2)); 8568 8569 format %{ "SRDI $dst, $src1, ($src2 & 0x3f)" %} 8570 size(4); 8571 ins_encode %{ 8572 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl); 8573 __ srdi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f); 8574 %} 8575 ins_pipe(pipe_class_default); 8576 %} 8577 8578 // URShiftL + ConvL2I. 8579 instruct convL2I_urShiftL_regL_immI(iRegIdst dst, iRegLsrc src1, immI src2) %{ 8580 match(Set dst (ConvL2I (URShiftL src1 src2))); 8581 8582 format %{ "SRDI $dst, $src1, ($src2 & 0x3f) \t// long + l2i" %} 8583 size(4); 8584 ins_encode %{ 8585 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl); 8586 __ srdi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f); 8587 %} 8588 ins_pipe(pipe_class_default); 8589 %} 8590 8591 // Register Shift Right Immediate with a CastP2X 8592 instruct shrP_convP2X_reg_imm6(iRegLdst dst, iRegP_N2P src1, uimmI6 src2) %{ 8593 match(Set dst (URShiftL (CastP2X src1) src2)); 8594 8595 format %{ "SRDI $dst, $src1, $src2 \t// Cast ptr $src1 to long and shift" %} 8596 size(4); 8597 ins_encode %{ 8598 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl); 8599 __ srdi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f); 8600 %} 8601 ins_pipe(pipe_class_default); 8602 %} 8603 8604 instruct sxtI_reg(iRegIdst dst, iRegIsrc src) %{ 8605 match(Set dst (ConvL2I (ConvI2L src))); 8606 8607 format %{ "EXTSW $dst, $src \t// int->int" %} 8608 size(4); 8609 ins_encode %{ 8610 // TODO: PPC port $archOpcode(ppc64Opcode_extsw); 8611 __ extsw($dst$$Register, $src$$Register); 8612 %} 8613 ins_pipe(pipe_class_default); 8614 %} 8615 8616 //----------Rotate Instructions------------------------------------------------ 8617 8618 // Rotate Left by 8-bit immediate 8619 instruct rotlI_reg_immi8(iRegIdst dst, iRegIsrc src, immI8 lshift, immI8 rshift) %{ 8620 match(Set dst (OrI (LShiftI src lshift) (URShiftI src rshift))); 8621 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f)); 8622 8623 format %{ "ROTLWI $dst, $src, $lshift" %} 8624 size(4); 8625 ins_encode %{ 8626 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm); 8627 __ rotlwi($dst$$Register, $src$$Register, $lshift$$constant); 8628 %} 8629 ins_pipe(pipe_class_default); 8630 %} 8631 8632 // Rotate Right by 8-bit immediate 8633 instruct rotrI_reg_immi8(iRegIdst dst, iRegIsrc src, immI8 rshift, immI8 lshift) %{ 8634 match(Set dst (OrI (URShiftI src rshift) (LShiftI src lshift))); 8635 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f)); 8636 8637 format %{ "ROTRWI $dst, $rshift" %} 8638 size(4); 8639 ins_encode %{ 8640 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm); 8641 __ rotrwi($dst$$Register, $src$$Register, $rshift$$constant); 8642 %} 8643 ins_pipe(pipe_class_default); 8644 %} 8645 8646 //----------Floating Point Arithmetic Instructions----------------------------- 8647 8648 // Add float single precision 8649 instruct addF_reg_reg(regF dst, regF src1, regF src2) %{ 8650 match(Set dst (AddF src1 src2)); 8651 8652 format %{ "FADDS $dst, $src1, $src2" %} 8653 size(4); 8654 ins_encode %{ 8655 // TODO: PPC port $archOpcode(ppc64Opcode_fadds); 8656 __ fadds($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister); 8657 %} 8658 ins_pipe(pipe_class_default); 8659 %} 8660 8661 // Add float double precision 8662 instruct addD_reg_reg(regD dst, regD src1, regD src2) %{ 8663 match(Set dst (AddD src1 src2)); 8664 8665 format %{ "FADD $dst, $src1, $src2" %} 8666 size(4); 8667 ins_encode %{ 8668 // TODO: PPC port $archOpcode(ppc64Opcode_fadd); 8669 __ fadd($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister); 8670 %} 8671 ins_pipe(pipe_class_default); 8672 %} 8673 8674 // Sub float single precision 8675 instruct subF_reg_reg(regF dst, regF src1, regF src2) %{ 8676 match(Set dst (SubF src1 src2)); 8677 8678 format %{ "FSUBS $dst, $src1, $src2" %} 8679 size(4); 8680 ins_encode %{ 8681 // TODO: PPC port $archOpcode(ppc64Opcode_fsubs); 8682 __ fsubs($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister); 8683 %} 8684 ins_pipe(pipe_class_default); 8685 %} 8686 8687 // Sub float double precision 8688 instruct subD_reg_reg(regD dst, regD src1, regD src2) %{ 8689 match(Set dst (SubD src1 src2)); 8690 format %{ "FSUB $dst, $src1, $src2" %} 8691 size(4); 8692 ins_encode %{ 8693 // TODO: PPC port $archOpcode(ppc64Opcode_fsub); 8694 __ fsub($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister); 8695 %} 8696 ins_pipe(pipe_class_default); 8697 %} 8698 8699 // Mul float single precision 8700 instruct mulF_reg_reg(regF dst, regF src1, regF src2) %{ 8701 match(Set dst (MulF src1 src2)); 8702 format %{ "FMULS $dst, $src1, $src2" %} 8703 size(4); 8704 ins_encode %{ 8705 // TODO: PPC port $archOpcode(ppc64Opcode_fmuls); 8706 __ fmuls($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister); 8707 %} 8708 ins_pipe(pipe_class_default); 8709 %} 8710 8711 // Mul float double precision 8712 instruct mulD_reg_reg(regD dst, regD src1, regD src2) %{ 8713 match(Set dst (MulD src1 src2)); 8714 format %{ "FMUL $dst, $src1, $src2" %} 8715 size(4); 8716 ins_encode %{ 8717 // TODO: PPC port $archOpcode(ppc64Opcode_fmul); 8718 __ fmul($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister); 8719 %} 8720 ins_pipe(pipe_class_default); 8721 %} 8722 8723 // Div float single precision 8724 instruct divF_reg_reg(regF dst, regF src1, regF src2) %{ 8725 match(Set dst (DivF src1 src2)); 8726 format %{ "FDIVS $dst, $src1, $src2" %} 8727 size(4); 8728 ins_encode %{ 8729 // TODO: PPC port $archOpcode(ppc64Opcode_fdivs); 8730 __ fdivs($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister); 8731 %} 8732 ins_pipe(pipe_class_default); 8733 %} 8734 8735 // Div float double precision 8736 instruct divD_reg_reg(regD dst, regD src1, regD src2) %{ 8737 match(Set dst (DivD src1 src2)); 8738 format %{ "FDIV $dst, $src1, $src2" %} 8739 size(4); 8740 ins_encode %{ 8741 // TODO: PPC port $archOpcode(ppc64Opcode_fdiv); 8742 __ fdiv($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister); 8743 %} 8744 ins_pipe(pipe_class_default); 8745 %} 8746 8747 // Absolute float single precision 8748 instruct absF_reg(regF dst, regF src) %{ 8749 match(Set dst (AbsF src)); 8750 format %{ "FABS $dst, $src \t// float" %} 8751 size(4); 8752 ins_encode %{ 8753 // TODO: PPC port $archOpcode(ppc64Opcode_fabs); 8754 __ fabs($dst$$FloatRegister, $src$$FloatRegister); 8755 %} 8756 ins_pipe(pipe_class_default); 8757 %} 8758 8759 // Absolute float double precision 8760 instruct absD_reg(regD dst, regD src) %{ 8761 match(Set dst (AbsD src)); 8762 format %{ "FABS $dst, $src \t// double" %} 8763 size(4); 8764 ins_encode %{ 8765 // TODO: PPC port $archOpcode(ppc64Opcode_fabs); 8766 __ fabs($dst$$FloatRegister, $src$$FloatRegister); 8767 %} 8768 ins_pipe(pipe_class_default); 8769 %} 8770 8771 instruct negF_reg(regF dst, regF src) %{ 8772 match(Set dst (NegF src)); 8773 format %{ "FNEG $dst, $src \t// float" %} 8774 size(4); 8775 ins_encode %{ 8776 // TODO: PPC port $archOpcode(ppc64Opcode_fneg); 8777 __ fneg($dst$$FloatRegister, $src$$FloatRegister); 8778 %} 8779 ins_pipe(pipe_class_default); 8780 %} 8781 8782 instruct negD_reg(regD dst, regD src) %{ 8783 match(Set dst (NegD src)); 8784 format %{ "FNEG $dst, $src \t// double" %} 8785 size(4); 8786 ins_encode %{ 8787 // TODO: PPC port $archOpcode(ppc64Opcode_fneg); 8788 __ fneg($dst$$FloatRegister, $src$$FloatRegister); 8789 %} 8790 ins_pipe(pipe_class_default); 8791 %} 8792 8793 // AbsF + NegF. 8794 instruct negF_absF_reg(regF dst, regF src) %{ 8795 match(Set dst (NegF (AbsF src))); 8796 format %{ "FNABS $dst, $src \t// float" %} 8797 size(4); 8798 ins_encode %{ 8799 // TODO: PPC port $archOpcode(ppc64Opcode_fnabs); 8800 __ fnabs($dst$$FloatRegister, $src$$FloatRegister); 8801 %} 8802 ins_pipe(pipe_class_default); 8803 %} 8804 8805 // AbsD + NegD. 8806 instruct negD_absD_reg(regD dst, regD src) %{ 8807 match(Set dst (NegD (AbsD src))); 8808 format %{ "FNABS $dst, $src \t// double" %} 8809 size(4); 8810 ins_encode %{ 8811 // TODO: PPC port $archOpcode(ppc64Opcode_fnabs); 8812 __ fnabs($dst$$FloatRegister, $src$$FloatRegister); 8813 %} 8814 ins_pipe(pipe_class_default); 8815 %} 8816 8817 // VM_Version::has_fsqrt() decides if this node will be used. 8818 // Sqrt float double precision 8819 instruct sqrtD_reg(regD dst, regD src) %{ 8820 match(Set dst (SqrtD src)); 8821 format %{ "FSQRT $dst, $src" %} 8822 size(4); 8823 ins_encode %{ 8824 // TODO: PPC port $archOpcode(ppc64Opcode_fsqrt); 8825 __ fsqrt($dst$$FloatRegister, $src$$FloatRegister); 8826 %} 8827 ins_pipe(pipe_class_default); 8828 %} 8829 8830 // Single-precision sqrt. 8831 instruct sqrtF_reg(regF dst, regF src) %{ 8832 match(Set dst (ConvD2F (SqrtD (ConvF2D src)))); 8833 predicate(VM_Version::has_fsqrts()); 8834 ins_cost(DEFAULT_COST); 8835 8836 format %{ "FSQRTS $dst, $src" %} 8837 size(4); 8838 ins_encode %{ 8839 // TODO: PPC port $archOpcode(ppc64Opcode_fsqrts); 8840 __ fsqrts($dst$$FloatRegister, $src$$FloatRegister); 8841 %} 8842 ins_pipe(pipe_class_default); 8843 %} 8844 8845 instruct roundDouble_nop(regD dst) %{ 8846 match(Set dst (RoundDouble dst)); 8847 ins_cost(0); 8848 8849 format %{ " -- \t// RoundDouble not needed - empty" %} 8850 size(0); 8851 // PPC results are already "rounded" (i.e., normal-format IEEE). 8852 ins_encode( /*empty*/ ); 8853 ins_pipe(pipe_class_default); 8854 %} 8855 8856 instruct roundFloat_nop(regF dst) %{ 8857 match(Set dst (RoundFloat dst)); 8858 ins_cost(0); 8859 8860 format %{ " -- \t// RoundFloat not needed - empty" %} 8861 size(0); 8862 // PPC results are already "rounded" (i.e., normal-format IEEE). 8863 ins_encode( /*empty*/ ); 8864 ins_pipe(pipe_class_default); 8865 %} 8866 8867 //----------Logical Instructions----------------------------------------------- 8868 8869 // And Instructions 8870 8871 // Register And 8872 instruct andI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ 8873 match(Set dst (AndI src1 src2)); 8874 format %{ "AND $dst, $src1, $src2" %} 8875 size(4); 8876 ins_encode %{ 8877 // TODO: PPC port $archOpcode(ppc64Opcode_and); 8878 __ andr($dst$$Register, $src1$$Register, $src2$$Register); 8879 %} 8880 ins_pipe(pipe_class_default); 8881 %} 8882 8883 // Immediate And 8884 instruct andI_reg_uimm16(iRegIdst dst, iRegIsrc src1, uimmI16 src2, flagsRegCR0 cr0) %{ 8885 match(Set dst (AndI src1 src2)); 8886 effect(KILL cr0); 8887 8888 format %{ "ANDI $dst, $src1, $src2" %} 8889 size(4); 8890 ins_encode %{ 8891 // TODO: PPC port $archOpcode(ppc64Opcode_andi_); 8892 // FIXME: avoid andi_ ? 8893 __ andi_($dst$$Register, $src1$$Register, $src2$$constant); 8894 %} 8895 ins_pipe(pipe_class_default); 8896 %} 8897 8898 // Immediate And where the immediate is a negative power of 2. 8899 instruct andI_reg_immInegpow2(iRegIdst dst, iRegIsrc src1, immInegpow2 src2) %{ 8900 match(Set dst (AndI src1 src2)); 8901 format %{ "ANDWI $dst, $src1, $src2" %} 8902 size(4); 8903 ins_encode %{ 8904 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr); 8905 __ clrrdi($dst$$Register, $src1$$Register, log2_long((jlong)(julong)(juint)-($src2$$constant))); 8906 %} 8907 ins_pipe(pipe_class_default); 8908 %} 8909 8910 instruct andI_reg_immIpow2minus1(iRegIdst dst, iRegIsrc src1, immIpow2minus1 src2) %{ 8911 match(Set dst (AndI src1 src2)); 8912 format %{ "ANDWI $dst, $src1, $src2" %} 8913 size(4); 8914 ins_encode %{ 8915 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl); 8916 __ clrldi($dst$$Register, $src1$$Register, 64-log2_long((((jlong) $src2$$constant)+1))); 8917 %} 8918 ins_pipe(pipe_class_default); 8919 %} 8920 8921 instruct andI_reg_immIpowerOf2(iRegIdst dst, iRegIsrc src1, immIpowerOf2 src2) %{ 8922 match(Set dst (AndI src1 src2)); 8923 predicate(UseRotateAndMaskInstructionsPPC64); 8924 format %{ "ANDWI $dst, $src1, $src2" %} 8925 size(4); 8926 ins_encode %{ 8927 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm); 8928 __ rlwinm($dst$$Register, $src1$$Register, 0, 8929 (31-log2_long((jlong) $src2$$constant)) & 0x1f, (31-log2_long((jlong) $src2$$constant)) & 0x1f); 8930 %} 8931 ins_pipe(pipe_class_default); 8932 %} 8933 8934 // Register And Long 8935 instruct andL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{ 8936 match(Set dst (AndL src1 src2)); 8937 ins_cost(DEFAULT_COST); 8938 8939 format %{ "AND $dst, $src1, $src2 \t// long" %} 8940 size(4); 8941 ins_encode %{ 8942 // TODO: PPC port $archOpcode(ppc64Opcode_and); 8943 __ andr($dst$$Register, $src1$$Register, $src2$$Register); 8944 %} 8945 ins_pipe(pipe_class_default); 8946 %} 8947 8948 // Immediate And long 8949 instruct andL_reg_uimm16(iRegLdst dst, iRegLsrc src1, uimmL16 src2, flagsRegCR0 cr0) %{ 8950 match(Set dst (AndL src1 src2)); 8951 effect(KILL cr0); 8952 ins_cost(DEFAULT_COST); 8953 8954 format %{ "ANDI $dst, $src1, $src2 \t// long" %} 8955 size(4); 8956 ins_encode %{ 8957 // TODO: PPC port $archOpcode(ppc64Opcode_andi_); 8958 // FIXME: avoid andi_ ? 8959 __ andi_($dst$$Register, $src1$$Register, $src2$$constant); 8960 %} 8961 ins_pipe(pipe_class_default); 8962 %} 8963 8964 // Immediate And Long where the immediate is a negative power of 2. 8965 instruct andL_reg_immLnegpow2(iRegLdst dst, iRegLsrc src1, immLnegpow2 src2) %{ 8966 match(Set dst (AndL src1 src2)); 8967 format %{ "ANDDI $dst, $src1, $src2" %} 8968 size(4); 8969 ins_encode %{ 8970 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr); 8971 __ clrrdi($dst$$Register, $src1$$Register, log2_long((jlong)-$src2$$constant)); 8972 %} 8973 ins_pipe(pipe_class_default); 8974 %} 8975 8976 instruct andL_reg_immLpow2minus1(iRegLdst dst, iRegLsrc src1, immLpow2minus1 src2) %{ 8977 match(Set dst (AndL src1 src2)); 8978 format %{ "ANDDI $dst, $src1, $src2" %} 8979 size(4); 8980 ins_encode %{ 8981 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl); 8982 __ clrldi($dst$$Register, $src1$$Register, 64-log2_long((((jlong) $src2$$constant)+1))); 8983 %} 8984 ins_pipe(pipe_class_default); 8985 %} 8986 8987 // AndL + ConvL2I. 8988 instruct convL2I_andL_reg_immLpow2minus1(iRegIdst dst, iRegLsrc src1, immLpow2minus1 src2) %{ 8989 match(Set dst (ConvL2I (AndL src1 src2))); 8990 ins_cost(DEFAULT_COST); 8991 8992 format %{ "ANDDI $dst, $src1, $src2 \t// long + l2i" %} 8993 size(4); 8994 ins_encode %{ 8995 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl); 8996 __ clrldi($dst$$Register, $src1$$Register, 64-log2_long((((jlong) $src2$$constant)+1))); 8997 %} 8998 ins_pipe(pipe_class_default); 8999 %} 9000 9001 // Or Instructions 9002 9003 // Register Or 9004 instruct orI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ 9005 match(Set dst (OrI src1 src2)); 9006 format %{ "OR $dst, $src1, $src2" %} 9007 size(4); 9008 ins_encode %{ 9009 // TODO: PPC port $archOpcode(ppc64Opcode_or); 9010 __ or_unchecked($dst$$Register, $src1$$Register, $src2$$Register); 9011 %} 9012 ins_pipe(pipe_class_default); 9013 %} 9014 9015 // Expand does not work with above instruct. (??) 9016 instruct orI_reg_reg_2(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ 9017 // no match-rule 9018 effect(DEF dst, USE src1, USE src2); 9019 format %{ "OR $dst, $src1, $src2" %} 9020 size(4); 9021 ins_encode %{ 9022 // TODO: PPC port $archOpcode(ppc64Opcode_or); 9023 __ or_unchecked($dst$$Register, $src1$$Register, $src2$$Register); 9024 %} 9025 ins_pipe(pipe_class_default); 9026 %} 9027 9028 instruct tree_orI_orI_orI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2, iRegIsrc src3, iRegIsrc src4) %{ 9029 match(Set dst (OrI (OrI (OrI src1 src2) src3) src4)); 9030 ins_cost(DEFAULT_COST*3); 9031 9032 expand %{ 9033 // FIXME: we should do this in the ideal world. 9034 iRegIdst tmp1; 9035 iRegIdst tmp2; 9036 orI_reg_reg(tmp1, src1, src2); 9037 orI_reg_reg_2(tmp2, src3, src4); // Adlc complains about orI_reg_reg. 9038 orI_reg_reg(dst, tmp1, tmp2); 9039 %} 9040 %} 9041 9042 // Immediate Or 9043 instruct orI_reg_uimm16(iRegIdst dst, iRegIsrc src1, uimmI16 src2) %{ 9044 match(Set dst (OrI src1 src2)); 9045 format %{ "ORI $dst, $src1, $src2" %} 9046 size(4); 9047 ins_encode %{ 9048 // TODO: PPC port $archOpcode(ppc64Opcode_ori); 9049 __ ori($dst$$Register, $src1$$Register, ($src2$$constant) & 0xFFFF); 9050 %} 9051 ins_pipe(pipe_class_default); 9052 %} 9053 9054 // Register Or Long 9055 instruct orL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{ 9056 match(Set dst (OrL src1 src2)); 9057 ins_cost(DEFAULT_COST); 9058 9059 size(4); 9060 format %{ "OR $dst, $src1, $src2 \t// long" %} 9061 ins_encode %{ 9062 // TODO: PPC port $archOpcode(ppc64Opcode_or); 9063 __ or_unchecked($dst$$Register, $src1$$Register, $src2$$Register); 9064 %} 9065 ins_pipe(pipe_class_default); 9066 %} 9067 9068 // OrL + ConvL2I. 9069 instruct orI_regL_regL(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{ 9070 match(Set dst (ConvL2I (OrL src1 src2))); 9071 ins_cost(DEFAULT_COST); 9072 9073 format %{ "OR $dst, $src1, $src2 \t// long + l2i" %} 9074 size(4); 9075 ins_encode %{ 9076 // TODO: PPC port $archOpcode(ppc64Opcode_or); 9077 __ or_unchecked($dst$$Register, $src1$$Register, $src2$$Register); 9078 %} 9079 ins_pipe(pipe_class_default); 9080 %} 9081 9082 // Immediate Or long 9083 instruct orL_reg_uimm16(iRegLdst dst, iRegLsrc src1, uimmL16 con) %{ 9084 match(Set dst (OrL src1 con)); 9085 ins_cost(DEFAULT_COST); 9086 9087 format %{ "ORI $dst, $src1, $con \t// long" %} 9088 size(4); 9089 ins_encode %{ 9090 // TODO: PPC port $archOpcode(ppc64Opcode_ori); 9091 __ ori($dst$$Register, $src1$$Register, ($con$$constant) & 0xFFFF); 9092 %} 9093 ins_pipe(pipe_class_default); 9094 %} 9095 9096 // Xor Instructions 9097 9098 // Register Xor 9099 instruct xorI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ 9100 match(Set dst (XorI src1 src2)); 9101 format %{ "XOR $dst, $src1, $src2" %} 9102 size(4); 9103 ins_encode %{ 9104 // TODO: PPC port $archOpcode(ppc64Opcode_xor); 9105 __ xorr($dst$$Register, $src1$$Register, $src2$$Register); 9106 %} 9107 ins_pipe(pipe_class_default); 9108 %} 9109 9110 // Expand does not work with above instruct. (??) 9111 instruct xorI_reg_reg_2(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ 9112 // no match-rule 9113 effect(DEF dst, USE src1, USE src2); 9114 format %{ "XOR $dst, $src1, $src2" %} 9115 size(4); 9116 ins_encode %{ 9117 // TODO: PPC port $archOpcode(ppc64Opcode_xor); 9118 __ xorr($dst$$Register, $src1$$Register, $src2$$Register); 9119 %} 9120 ins_pipe(pipe_class_default); 9121 %} 9122 9123 instruct tree_xorI_xorI_xorI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2, iRegIsrc src3, iRegIsrc src4) %{ 9124 match(Set dst (XorI (XorI (XorI src1 src2) src3) src4)); 9125 ins_cost(DEFAULT_COST*3); 9126 9127 expand %{ 9128 // FIXME: we should do this in the ideal world. 9129 iRegIdst tmp1; 9130 iRegIdst tmp2; 9131 xorI_reg_reg(tmp1, src1, src2); 9132 xorI_reg_reg_2(tmp2, src3, src4); // Adlc complains about xorI_reg_reg. 9133 xorI_reg_reg(dst, tmp1, tmp2); 9134 %} 9135 %} 9136 9137 // Immediate Xor 9138 instruct xorI_reg_uimm16(iRegIdst dst, iRegIsrc src1, uimmI16 src2) %{ 9139 match(Set dst (XorI src1 src2)); 9140 format %{ "XORI $dst, $src1, $src2" %} 9141 size(4); 9142 ins_encode %{ 9143 // TODO: PPC port $archOpcode(ppc64Opcode_xori); 9144 __ xori($dst$$Register, $src1$$Register, $src2$$constant); 9145 %} 9146 ins_pipe(pipe_class_default); 9147 %} 9148 9149 // Register Xor Long 9150 instruct xorL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{ 9151 match(Set dst (XorL src1 src2)); 9152 ins_cost(DEFAULT_COST); 9153 9154 format %{ "XOR $dst, $src1, $src2 \t// long" %} 9155 size(4); 9156 ins_encode %{ 9157 // TODO: PPC port $archOpcode(ppc64Opcode_xor); 9158 __ xorr($dst$$Register, $src1$$Register, $src2$$Register); 9159 %} 9160 ins_pipe(pipe_class_default); 9161 %} 9162 9163 // XorL + ConvL2I. 9164 instruct xorI_regL_regL(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{ 9165 match(Set dst (ConvL2I (XorL src1 src2))); 9166 ins_cost(DEFAULT_COST); 9167 9168 format %{ "XOR $dst, $src1, $src2 \t// long + l2i" %} 9169 size(4); 9170 ins_encode %{ 9171 // TODO: PPC port $archOpcode(ppc64Opcode_xor); 9172 __ xorr($dst$$Register, $src1$$Register, $src2$$Register); 9173 %} 9174 ins_pipe(pipe_class_default); 9175 %} 9176 9177 // Immediate Xor Long 9178 instruct xorL_reg_uimm16(iRegLdst dst, iRegLsrc src1, uimmL16 src2) %{ 9179 match(Set dst (XorL src1 src2)); 9180 ins_cost(DEFAULT_COST); 9181 9182 format %{ "XORI $dst, $src1, $src2 \t// long" %} 9183 size(4); 9184 ins_encode %{ 9185 // TODO: PPC port $archOpcode(ppc64Opcode_xori); 9186 __ xori($dst$$Register, $src1$$Register, $src2$$constant); 9187 %} 9188 ins_pipe(pipe_class_default); 9189 %} 9190 9191 instruct notI_reg(iRegIdst dst, iRegIsrc src1, immI_minus1 src2) %{ 9192 match(Set dst (XorI src1 src2)); 9193 ins_cost(DEFAULT_COST); 9194 9195 format %{ "NOT $dst, $src1 ($src2)" %} 9196 size(4); 9197 ins_encode %{ 9198 // TODO: PPC port $archOpcode(ppc64Opcode_nor); 9199 __ nor($dst$$Register, $src1$$Register, $src1$$Register); 9200 %} 9201 ins_pipe(pipe_class_default); 9202 %} 9203 9204 instruct notL_reg(iRegLdst dst, iRegLsrc src1, immL_minus1 src2) %{ 9205 match(Set dst (XorL src1 src2)); 9206 ins_cost(DEFAULT_COST); 9207 9208 format %{ "NOT $dst, $src1 ($src2) \t// long" %} 9209 size(4); 9210 ins_encode %{ 9211 // TODO: PPC port $archOpcode(ppc64Opcode_nor); 9212 __ nor($dst$$Register, $src1$$Register, $src1$$Register); 9213 %} 9214 ins_pipe(pipe_class_default); 9215 %} 9216 9217 // And-complement 9218 instruct andcI_reg_reg(iRegIdst dst, iRegIsrc src1, immI_minus1 src2, iRegIsrc src3) %{ 9219 match(Set dst (AndI (XorI src1 src2) src3)); 9220 ins_cost(DEFAULT_COST); 9221 9222 format %{ "ANDW $dst, xori($src1, $src2), $src3" %} 9223 size(4); 9224 ins_encode( enc_andc(dst, src3, src1) ); 9225 ins_pipe(pipe_class_default); 9226 %} 9227 9228 // And-complement 9229 instruct andcL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{ 9230 // no match-rule, false predicate 9231 effect(DEF dst, USE src1, USE src2); 9232 predicate(false); 9233 9234 format %{ "ANDC $dst, $src1, $src2" %} 9235 size(4); 9236 ins_encode %{ 9237 // TODO: PPC port $archOpcode(ppc64Opcode_andc); 9238 __ andc($dst$$Register, $src1$$Register, $src2$$Register); 9239 %} 9240 ins_pipe(pipe_class_default); 9241 %} 9242 9243 //----------Moves between int/long and float/double---------------------------- 9244 // 9245 // The following rules move values from int/long registers/stack-locations 9246 // to float/double registers/stack-locations and vice versa, without doing any 9247 // conversions. These rules are used to implement the bit-conversion methods 9248 // of java.lang.Float etc., e.g. 9249 // int floatToIntBits(float value) 9250 // float intBitsToFloat(int bits) 9251 // 9252 // Notes on the implementation on ppc64: 9253 // We only provide rules which move between a register and a stack-location, 9254 // because we always have to go through memory when moving between a float 9255 // register and an integer register. 9256 9257 //---------- Chain stack slots between similar types -------- 9258 9259 // These are needed so that the rules below can match. 9260 9261 // Load integer from stack slot 9262 instruct stkI_to_regI(iRegIdst dst, stackSlotI src) %{ 9263 match(Set dst src); 9264 ins_cost(MEMORY_REF_COST); 9265 9266 format %{ "LWZ $dst, $src" %} 9267 size(4); 9268 ins_encode( enc_lwz(dst, src) ); 9269 ins_pipe(pipe_class_memory); 9270 %} 9271 9272 // Store integer to stack slot 9273 instruct regI_to_stkI(stackSlotI dst, iRegIsrc src) %{ 9274 match(Set dst src); 9275 ins_cost(MEMORY_REF_COST); 9276 9277 format %{ "STW $src, $dst \t// stk" %} 9278 size(4); 9279 ins_encode( enc_stw(src, dst) ); // rs=rt 9280 ins_pipe(pipe_class_memory); 9281 %} 9282 9283 // Load long from stack slot 9284 instruct stkL_to_regL(iRegLdst dst, stackSlotL src) %{ 9285 match(Set dst src); 9286 ins_cost(MEMORY_REF_COST); 9287 9288 format %{ "LD $dst, $src \t// long" %} 9289 size(4); 9290 ins_encode( enc_ld(dst, src) ); 9291 ins_pipe(pipe_class_memory); 9292 %} 9293 9294 // Store long to stack slot 9295 instruct regL_to_stkL(stackSlotL dst, iRegLsrc src) %{ 9296 match(Set dst src); 9297 ins_cost(MEMORY_REF_COST); 9298 9299 format %{ "STD $src, $dst \t// long" %} 9300 size(4); 9301 ins_encode( enc_std(src, dst) ); // rs=rt 9302 ins_pipe(pipe_class_memory); 9303 %} 9304 9305 //----------Moves between int and float 9306 9307 // Move float value from float stack-location to integer register. 9308 instruct moveF2I_stack_reg(iRegIdst dst, stackSlotF src) %{ 9309 match(Set dst (MoveF2I src)); 9310 ins_cost(MEMORY_REF_COST); 9311 9312 format %{ "LWZ $dst, $src \t// MoveF2I" %} 9313 size(4); 9314 ins_encode( enc_lwz(dst, src) ); 9315 ins_pipe(pipe_class_memory); 9316 %} 9317 9318 // Move float value from float register to integer stack-location. 9319 instruct moveF2I_reg_stack(stackSlotI dst, regF src) %{ 9320 match(Set dst (MoveF2I src)); 9321 ins_cost(MEMORY_REF_COST); 9322 9323 format %{ "STFS $src, $dst \t// MoveF2I" %} 9324 size(4); 9325 ins_encode( enc_stfs(src, dst) ); 9326 ins_pipe(pipe_class_memory); 9327 %} 9328 9329 // Move integer value from integer stack-location to float register. 9330 instruct moveI2F_stack_reg(regF dst, stackSlotI src) %{ 9331 match(Set dst (MoveI2F src)); 9332 ins_cost(MEMORY_REF_COST); 9333 9334 format %{ "LFS $dst, $src \t// MoveI2F" %} 9335 size(4); 9336 ins_encode %{ 9337 // TODO: PPC port $archOpcode(ppc64Opcode_lfs); 9338 int Idisp = $src$$disp + frame_slots_bias($src$$base, ra_); 9339 __ lfs($dst$$FloatRegister, Idisp, $src$$base$$Register); 9340 %} 9341 ins_pipe(pipe_class_memory); 9342 %} 9343 9344 // Move integer value from integer register to float stack-location. 9345 instruct moveI2F_reg_stack(stackSlotF dst, iRegIsrc src) %{ 9346 match(Set dst (MoveI2F src)); 9347 ins_cost(MEMORY_REF_COST); 9348 9349 format %{ "STW $src, $dst \t// MoveI2F" %} 9350 size(4); 9351 ins_encode( enc_stw(src, dst) ); 9352 ins_pipe(pipe_class_memory); 9353 %} 9354 9355 //----------Moves between long and float 9356 9357 instruct moveF2L_reg_stack(stackSlotL dst, regF src) %{ 9358 // no match-rule, false predicate 9359 effect(DEF dst, USE src); 9360 predicate(false); 9361 9362 format %{ "storeD $src, $dst \t// STACK" %} 9363 size(4); 9364 ins_encode( enc_stfd(src, dst) ); 9365 ins_pipe(pipe_class_default); 9366 %} 9367 9368 //----------Moves between long and double 9369 9370 // Move double value from double stack-location to long register. 9371 instruct moveD2L_stack_reg(iRegLdst dst, stackSlotD src) %{ 9372 match(Set dst (MoveD2L src)); 9373 ins_cost(MEMORY_REF_COST); 9374 size(4); 9375 format %{ "LD $dst, $src \t// MoveD2L" %} 9376 ins_encode( enc_ld(dst, src) ); 9377 ins_pipe(pipe_class_memory); 9378 %} 9379 9380 // Move double value from double register to long stack-location. 9381 instruct moveD2L_reg_stack(stackSlotL dst, regD src) %{ 9382 match(Set dst (MoveD2L src)); 9383 effect(DEF dst, USE src); 9384 ins_cost(MEMORY_REF_COST); 9385 9386 format %{ "STFD $src, $dst \t// MoveD2L" %} 9387 size(4); 9388 ins_encode( enc_stfd(src, dst) ); 9389 ins_pipe(pipe_class_memory); 9390 %} 9391 9392 // Move long value from long stack-location to double register. 9393 instruct moveL2D_stack_reg(regD dst, stackSlotL src) %{ 9394 match(Set dst (MoveL2D src)); 9395 ins_cost(MEMORY_REF_COST); 9396 9397 format %{ "LFD $dst, $src \t// MoveL2D" %} 9398 size(4); 9399 ins_encode( enc_lfd(dst, src) ); 9400 ins_pipe(pipe_class_memory); 9401 %} 9402 9403 // Move long value from long register to double stack-location. 9404 instruct moveL2D_reg_stack(stackSlotD dst, iRegLsrc src) %{ 9405 match(Set dst (MoveL2D src)); 9406 ins_cost(MEMORY_REF_COST); 9407 9408 format %{ "STD $src, $dst \t// MoveL2D" %} 9409 size(4); 9410 ins_encode( enc_std(src, dst) ); 9411 ins_pipe(pipe_class_memory); 9412 %} 9413 9414 //----------Register Move Instructions----------------------------------------- 9415 9416 // Replicate for Superword 9417 9418 instruct moveReg(iRegLdst dst, iRegIsrc src) %{ 9419 predicate(false); 9420 effect(DEF dst, USE src); 9421 9422 format %{ "MR $dst, $src \t// replicate " %} 9423 // variable size, 0 or 4. 9424 ins_encode %{ 9425 // TODO: PPC port $archOpcode(ppc64Opcode_or); 9426 __ mr_if_needed($dst$$Register, $src$$Register); 9427 %} 9428 ins_pipe(pipe_class_default); 9429 %} 9430 9431 //----------Cast instructions (Java-level type cast)--------------------------- 9432 9433 // Cast Long to Pointer for unsafe natives. 9434 instruct castX2P(iRegPdst dst, iRegLsrc src) %{ 9435 match(Set dst (CastX2P src)); 9436 9437 format %{ "MR $dst, $src \t// Long->Ptr" %} 9438 // variable size, 0 or 4. 9439 ins_encode %{ 9440 // TODO: PPC port $archOpcode(ppc64Opcode_or); 9441 __ mr_if_needed($dst$$Register, $src$$Register); 9442 %} 9443 ins_pipe(pipe_class_default); 9444 %} 9445 9446 // Cast Pointer to Long for unsafe natives. 9447 instruct castP2X(iRegLdst dst, iRegP_N2P src) %{ 9448 match(Set dst (CastP2X src)); 9449 9450 format %{ "MR $dst, $src \t// Ptr->Long" %} 9451 // variable size, 0 or 4. 9452 ins_encode %{ 9453 // TODO: PPC port $archOpcode(ppc64Opcode_or); 9454 __ mr_if_needed($dst$$Register, $src$$Register); 9455 %} 9456 ins_pipe(pipe_class_default); 9457 %} 9458 9459 instruct castPP(iRegPdst dst) %{ 9460 match(Set dst (CastPP dst)); 9461 format %{ " -- \t// castPP of $dst" %} 9462 size(0); 9463 ins_encode( /*empty*/ ); 9464 ins_pipe(pipe_class_default); 9465 %} 9466 9467 instruct castII(iRegIdst dst) %{ 9468 match(Set dst (CastII dst)); 9469 format %{ " -- \t// castII of $dst" %} 9470 size(0); 9471 ins_encode( /*empty*/ ); 9472 ins_pipe(pipe_class_default); 9473 %} 9474 9475 instruct checkCastPP(iRegPdst dst) %{ 9476 match(Set dst (CheckCastPP dst)); 9477 format %{ " -- \t// checkcastPP of $dst" %} 9478 size(0); 9479 ins_encode( /*empty*/ ); 9480 ins_pipe(pipe_class_default); 9481 %} 9482 9483 //----------Convert instructions----------------------------------------------- 9484 9485 // Convert to boolean. 9486 9487 // int_to_bool(src) : { 1 if src != 0 9488 // { 0 else 9489 // 9490 // strategy: 9491 // 1) Count leading zeros of 32 bit-value src, 9492 // this returns 32 (0b10.0000) iff src == 0 and <32 otherwise. 9493 // 2) Shift 5 bits to the right, result is 0b1 iff src == 0, 0b0 otherwise. 9494 // 3) Xori the result to get 0b1 if src != 0 and 0b0 if src == 0. 9495 9496 // convI2Bool 9497 instruct convI2Bool_reg__cntlz_Ex(iRegIdst dst, iRegIsrc src) %{ 9498 match(Set dst (Conv2B src)); 9499 predicate(UseCountLeadingZerosInstructionsPPC64); 9500 ins_cost(DEFAULT_COST); 9501 9502 expand %{ 9503 immI shiftAmount %{ 0x5 %} 9504 uimmI16 mask %{ 0x1 %} 9505 iRegIdst tmp1; 9506 iRegIdst tmp2; 9507 countLeadingZerosI(tmp1, src); 9508 urShiftI_reg_imm(tmp2, tmp1, shiftAmount); 9509 xorI_reg_uimm16(dst, tmp2, mask); 9510 %} 9511 %} 9512 9513 instruct convI2Bool_reg__cmove(iRegIdst dst, iRegIsrc src, flagsReg crx) %{ 9514 match(Set dst (Conv2B src)); 9515 effect(TEMP crx); 9516 predicate(!UseCountLeadingZerosInstructionsPPC64); 9517 ins_cost(DEFAULT_COST); 9518 9519 format %{ "CMPWI $crx, $src, #0 \t// convI2B" 9520 "LI $dst, #0\n\t" 9521 "BEQ $crx, done\n\t" 9522 "LI $dst, #1\n" 9523 "done:" %} 9524 size(16); 9525 ins_encode( enc_convI2B_regI__cmove(dst, src, crx, 0x0, 0x1) ); 9526 ins_pipe(pipe_class_compare); 9527 %} 9528 9529 // ConvI2B + XorI 9530 instruct xorI_convI2Bool_reg_immIvalue1__cntlz_Ex(iRegIdst dst, iRegIsrc src, immI_1 mask) %{ 9531 match(Set dst (XorI (Conv2B src) mask)); 9532 predicate(UseCountLeadingZerosInstructionsPPC64); 9533 ins_cost(DEFAULT_COST); 9534 9535 expand %{ 9536 immI shiftAmount %{ 0x5 %} 9537 iRegIdst tmp1; 9538 countLeadingZerosI(tmp1, src); 9539 urShiftI_reg_imm(dst, tmp1, shiftAmount); 9540 %} 9541 %} 9542 9543 instruct xorI_convI2Bool_reg_immIvalue1__cmove(iRegIdst dst, iRegIsrc src, flagsReg crx, immI_1 mask) %{ 9544 match(Set dst (XorI (Conv2B src) mask)); 9545 effect(TEMP crx); 9546 predicate(!UseCountLeadingZerosInstructionsPPC64); 9547 ins_cost(DEFAULT_COST); 9548 9549 format %{ "CMPWI $crx, $src, #0 \t// Xor(convI2B($src), $mask)" 9550 "LI $dst, #1\n\t" 9551 "BEQ $crx, done\n\t" 9552 "LI $dst, #0\n" 9553 "done:" %} 9554 size(16); 9555 ins_encode( enc_convI2B_regI__cmove(dst, src, crx, 0x1, 0x0) ); 9556 ins_pipe(pipe_class_compare); 9557 %} 9558 9559 // AndI 0b0..010..0 + ConvI2B 9560 instruct convI2Bool_andI_reg_immIpowerOf2(iRegIdst dst, iRegIsrc src, immIpowerOf2 mask) %{ 9561 match(Set dst (Conv2B (AndI src mask))); 9562 predicate(UseRotateAndMaskInstructionsPPC64); 9563 ins_cost(DEFAULT_COST); 9564 9565 format %{ "RLWINM $dst, $src, $mask \t// convI2B(AndI($src, $mask))" %} 9566 size(4); 9567 ins_encode %{ 9568 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm); 9569 __ rlwinm($dst$$Register, $src$$Register, (32-log2_long((jlong)$mask$$constant)) & 0x1f, 31, 31); 9570 %} 9571 ins_pipe(pipe_class_default); 9572 %} 9573 9574 // Convert pointer to boolean. 9575 // 9576 // ptr_to_bool(src) : { 1 if src != 0 9577 // { 0 else 9578 // 9579 // strategy: 9580 // 1) Count leading zeros of 64 bit-value src, 9581 // this returns 64 (0b100.0000) iff src == 0 and <64 otherwise. 9582 // 2) Shift 6 bits to the right, result is 0b1 iff src == 0, 0b0 otherwise. 9583 // 3) Xori the result to get 0b1 if src != 0 and 0b0 if src == 0. 9584 9585 // ConvP2B 9586 instruct convP2Bool_reg__cntlz_Ex(iRegIdst dst, iRegP_N2P src) %{ 9587 match(Set dst (Conv2B src)); 9588 predicate(UseCountLeadingZerosInstructionsPPC64); 9589 ins_cost(DEFAULT_COST); 9590 9591 expand %{ 9592 immI shiftAmount %{ 0x6 %} 9593 uimmI16 mask %{ 0x1 %} 9594 iRegIdst tmp1; 9595 iRegIdst tmp2; 9596 countLeadingZerosP(tmp1, src); 9597 urShiftI_reg_imm(tmp2, tmp1, shiftAmount); 9598 xorI_reg_uimm16(dst, tmp2, mask); 9599 %} 9600 %} 9601 9602 instruct convP2Bool_reg__cmove(iRegIdst dst, iRegP_N2P src, flagsReg crx) %{ 9603 match(Set dst (Conv2B src)); 9604 effect(TEMP crx); 9605 predicate(!UseCountLeadingZerosInstructionsPPC64); 9606 ins_cost(DEFAULT_COST); 9607 9608 format %{ "CMPDI $crx, $src, #0 \t// convP2B" 9609 "LI $dst, #0\n\t" 9610 "BEQ $crx, done\n\t" 9611 "LI $dst, #1\n" 9612 "done:" %} 9613 size(16); 9614 ins_encode( enc_convP2B_regP__cmove(dst, src, crx, 0x0, 0x1) ); 9615 ins_pipe(pipe_class_compare); 9616 %} 9617 9618 // ConvP2B + XorI 9619 instruct xorI_convP2Bool_reg__cntlz_Ex(iRegIdst dst, iRegP_N2P src, immI_1 mask) %{ 9620 match(Set dst (XorI (Conv2B src) mask)); 9621 predicate(UseCountLeadingZerosInstructionsPPC64); 9622 ins_cost(DEFAULT_COST); 9623 9624 expand %{ 9625 immI shiftAmount %{ 0x6 %} 9626 iRegIdst tmp1; 9627 countLeadingZerosP(tmp1, src); 9628 urShiftI_reg_imm(dst, tmp1, shiftAmount); 9629 %} 9630 %} 9631 9632 instruct xorI_convP2Bool_reg_immIvalue1__cmove(iRegIdst dst, iRegP_N2P src, flagsReg crx, immI_1 mask) %{ 9633 match(Set dst (XorI (Conv2B src) mask)); 9634 effect(TEMP crx); 9635 predicate(!UseCountLeadingZerosInstructionsPPC64); 9636 ins_cost(DEFAULT_COST); 9637 9638 format %{ "CMPDI $crx, $src, #0 \t// XorI(convP2B($src), $mask)" 9639 "LI $dst, #1\n\t" 9640 "BEQ $crx, done\n\t" 9641 "LI $dst, #0\n" 9642 "done:" %} 9643 size(16); 9644 ins_encode( enc_convP2B_regP__cmove(dst, src, crx, 0x1, 0x0) ); 9645 ins_pipe(pipe_class_compare); 9646 %} 9647 9648 // if src1 < src2, return -1 else return 0 9649 instruct cmpLTMask_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ 9650 match(Set dst (CmpLTMask src1 src2)); 9651 ins_cost(DEFAULT_COST*4); 9652 9653 expand %{ 9654 iRegLdst src1s; 9655 iRegLdst src2s; 9656 iRegLdst diff; 9657 convI2L_reg(src1s, src1); // Ensure proper sign extension. 9658 convI2L_reg(src2s, src2); // Ensure proper sign extension. 9659 subL_reg_reg(diff, src1s, src2s); 9660 // Need to consider >=33 bit result, therefore we need signmaskL. 9661 signmask64I_regL(dst, diff); 9662 %} 9663 %} 9664 9665 instruct cmpLTMask_reg_immI0(iRegIdst dst, iRegIsrc src1, immI_0 src2) %{ 9666 match(Set dst (CmpLTMask src1 src2)); // if src1 < src2, return -1 else return 0 9667 format %{ "SRAWI $dst, $src1, $src2 \t// CmpLTMask" %} 9668 size(4); 9669 ins_encode %{ 9670 // TODO: PPC port $archOpcode(ppc64Opcode_srawi); 9671 __ srawi($dst$$Register, $src1$$Register, 0x1f); 9672 %} 9673 ins_pipe(pipe_class_default); 9674 %} 9675 9676 //----------Arithmetic Conversion Instructions--------------------------------- 9677 9678 // Convert to Byte -- nop 9679 // Convert to Short -- nop 9680 9681 // Convert to Int 9682 9683 instruct convB2I_reg(iRegIdst dst, iRegIsrc src, immI_24 amount) %{ 9684 match(Set dst (RShiftI (LShiftI src amount) amount)); 9685 format %{ "EXTSB $dst, $src \t// byte->int" %} 9686 size(4); 9687 ins_encode %{ 9688 // TODO: PPC port $archOpcode(ppc64Opcode_extsb); 9689 __ extsb($dst$$Register, $src$$Register); 9690 %} 9691 ins_pipe(pipe_class_default); 9692 %} 9693 9694 // LShiftI 16 + RShiftI 16 converts short to int. 9695 instruct convS2I_reg(iRegIdst dst, iRegIsrc src, immI_16 amount) %{ 9696 match(Set dst (RShiftI (LShiftI src amount) amount)); 9697 format %{ "EXTSH $dst, $src \t// short->int" %} 9698 size(4); 9699 ins_encode %{ 9700 // TODO: PPC port $archOpcode(ppc64Opcode_extsh); 9701 __ extsh($dst$$Register, $src$$Register); 9702 %} 9703 ins_pipe(pipe_class_default); 9704 %} 9705 9706 // ConvL2I + ConvI2L: Sign extend int in long register. 9707 instruct sxtI_L2L_reg(iRegLdst dst, iRegLsrc src) %{ 9708 match(Set dst (ConvI2L (ConvL2I src))); 9709 9710 format %{ "EXTSW $dst, $src \t// long->long" %} 9711 size(4); 9712 ins_encode %{ 9713 // TODO: PPC port $archOpcode(ppc64Opcode_extsw); 9714 __ extsw($dst$$Register, $src$$Register); 9715 %} 9716 ins_pipe(pipe_class_default); 9717 %} 9718 9719 instruct convL2I_reg(iRegIdst dst, iRegLsrc src) %{ 9720 match(Set dst (ConvL2I src)); 9721 format %{ "MR $dst, $src \t// long->int" %} 9722 // variable size, 0 or 4 9723 ins_encode %{ 9724 // TODO: PPC port $archOpcode(ppc64Opcode_or); 9725 __ mr_if_needed($dst$$Register, $src$$Register); 9726 %} 9727 ins_pipe(pipe_class_default); 9728 %} 9729 9730 instruct convD2IRaw_regD(regD dst, regD src) %{ 9731 // no match-rule, false predicate 9732 effect(DEF dst, USE src); 9733 predicate(false); 9734 9735 format %{ "FCTIWZ $dst, $src \t// convD2I, $src != NaN" %} 9736 size(4); 9737 ins_encode %{ 9738 // TODO: PPC port $archOpcode(ppc64Opcode_fctiwz);; 9739 __ fctiwz($dst$$FloatRegister, $src$$FloatRegister); 9740 %} 9741 ins_pipe(pipe_class_default); 9742 %} 9743 9744 instruct cmovI_bso_stackSlotL(iRegIdst dst, flagsReg crx, stackSlotL src) %{ 9745 // no match-rule, false predicate 9746 effect(DEF dst, USE crx, USE src); 9747 predicate(false); 9748 9749 ins_variable_size_depending_on_alignment(true); 9750 9751 format %{ "cmovI $crx, $dst, $src" %} 9752 // Worst case is branch + move + stop, no stop without scheduler. 9753 size(false /* TODO: PPC PORT(InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8); 9754 ins_encode( enc_cmove_bso_stackSlotL(dst, crx, src) ); 9755 ins_pipe(pipe_class_default); 9756 %} 9757 9758 instruct cmovI_bso_stackSlotL_conLvalue0_Ex(iRegIdst dst, flagsReg crx, stackSlotL mem) %{ 9759 // no match-rule, false predicate 9760 effect(DEF dst, USE crx, USE mem); 9761 predicate(false); 9762 9763 format %{ "CmovI $dst, $crx, $mem \t// postalloc expanded" %} 9764 postalloc_expand %{ 9765 // 9766 // replaces 9767 // 9768 // region dst crx mem 9769 // \ | | / 9770 // dst=cmovI_bso_stackSlotL_conLvalue0 9771 // 9772 // with 9773 // 9774 // region dst 9775 // \ / 9776 // dst=loadConI16(0) 9777 // | 9778 // ^ region dst crx mem 9779 // | \ | | / 9780 // dst=cmovI_bso_stackSlotL 9781 // 9782 9783 // Create new nodes. 9784 MachNode *m1 = new (C) loadConI16Node(); 9785 MachNode *m2 = new (C) cmovI_bso_stackSlotLNode(); 9786 9787 // inputs for new nodes 9788 m1->add_req(n_region); 9789 m2->add_req(n_region, n_crx, n_mem); 9790 9791 // precedences for new nodes 9792 m2->add_prec(m1); 9793 9794 // operands for new nodes 9795 m1->_opnds[0] = op_dst; 9796 m1->_opnds[1] = new (C) immI16Oper(0); 9797 9798 m2->_opnds[0] = op_dst; 9799 m2->_opnds[1] = op_crx; 9800 m2->_opnds[2] = op_mem; 9801 9802 // registers for new nodes 9803 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst 9804 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst 9805 9806 // Insert new nodes. 9807 nodes->push(m1); 9808 nodes->push(m2); 9809 %} 9810 %} 9811 9812 // Double to Int conversion, NaN is mapped to 0. 9813 instruct convD2I_reg_ExEx(iRegIdst dst, regD src) %{ 9814 match(Set dst (ConvD2I src)); 9815 ins_cost(DEFAULT_COST); 9816 9817 expand %{ 9818 regD tmpD; 9819 stackSlotL tmpS; 9820 flagsReg crx; 9821 cmpDUnordered_reg_reg(crx, src, src); // Check whether src is NaN. 9822 convD2IRaw_regD(tmpD, src); // Convert float to int (speculated). 9823 moveD2L_reg_stack(tmpS, tmpD); // Store float to stack (speculated). 9824 cmovI_bso_stackSlotL_conLvalue0_Ex(dst, crx, tmpS); // Cmove based on NaN check. 9825 %} 9826 %} 9827 9828 instruct convF2IRaw_regF(regF dst, regF src) %{ 9829 // no match-rule, false predicate 9830 effect(DEF dst, USE src); 9831 predicate(false); 9832 9833 format %{ "FCTIWZ $dst, $src \t// convF2I, $src != NaN" %} 9834 size(4); 9835 ins_encode %{ 9836 // TODO: PPC port $archOpcode(ppc64Opcode_fctiwz); 9837 __ fctiwz($dst$$FloatRegister, $src$$FloatRegister); 9838 %} 9839 ins_pipe(pipe_class_default); 9840 %} 9841 9842 // Float to Int conversion, NaN is mapped to 0. 9843 instruct convF2I_regF_ExEx(iRegIdst dst, regF src) %{ 9844 match(Set dst (ConvF2I src)); 9845 ins_cost(DEFAULT_COST); 9846 9847 expand %{ 9848 regF tmpF; 9849 stackSlotL tmpS; 9850 flagsReg crx; 9851 cmpFUnordered_reg_reg(crx, src, src); // Check whether src is NaN. 9852 convF2IRaw_regF(tmpF, src); // Convert float to int (speculated). 9853 moveF2L_reg_stack(tmpS, tmpF); // Store float to stack (speculated). 9854 cmovI_bso_stackSlotL_conLvalue0_Ex(dst, crx, tmpS); // Cmove based on NaN check. 9855 %} 9856 %} 9857 9858 // Convert to Long 9859 9860 instruct convI2L_reg(iRegLdst dst, iRegIsrc src) %{ 9861 match(Set dst (ConvI2L src)); 9862 format %{ "EXTSW $dst, $src \t// int->long" %} 9863 size(4); 9864 ins_encode %{ 9865 // TODO: PPC port $archOpcode(ppc64Opcode_extsw); 9866 __ extsw($dst$$Register, $src$$Register); 9867 %} 9868 ins_pipe(pipe_class_default); 9869 %} 9870 9871 // Zero-extend: convert unsigned int to long (convUI2L). 9872 instruct zeroExtendL_regI(iRegLdst dst, iRegIsrc src, immL_32bits mask) %{ 9873 match(Set dst (AndL (ConvI2L src) mask)); 9874 ins_cost(DEFAULT_COST); 9875 9876 format %{ "CLRLDI $dst, $src, #32 \t// zero-extend int to long" %} 9877 size(4); 9878 ins_encode %{ 9879 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl); 9880 __ clrldi($dst$$Register, $src$$Register, 32); 9881 %} 9882 ins_pipe(pipe_class_default); 9883 %} 9884 9885 // Zero-extend: convert unsigned int to long in long register. 9886 instruct zeroExtendL_regL(iRegLdst dst, iRegLsrc src, immL_32bits mask) %{ 9887 match(Set dst (AndL src mask)); 9888 ins_cost(DEFAULT_COST); 9889 9890 format %{ "CLRLDI $dst, $src, #32 \t// zero-extend int to long" %} 9891 size(4); 9892 ins_encode %{ 9893 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl); 9894 __ clrldi($dst$$Register, $src$$Register, 32); 9895 %} 9896 ins_pipe(pipe_class_default); 9897 %} 9898 9899 instruct convF2LRaw_regF(regF dst, regF src) %{ 9900 // no match-rule, false predicate 9901 effect(DEF dst, USE src); 9902 predicate(false); 9903 9904 format %{ "FCTIDZ $dst, $src \t// convF2L, $src != NaN" %} 9905 size(4); 9906 ins_encode %{ 9907 // TODO: PPC port $archOpcode(ppc64Opcode_fctiwz); 9908 __ fctidz($dst$$FloatRegister, $src$$FloatRegister); 9909 %} 9910 ins_pipe(pipe_class_default); 9911 %} 9912 9913 instruct cmovL_bso_stackSlotL(iRegLdst dst, flagsReg crx, stackSlotL src) %{ 9914 // no match-rule, false predicate 9915 effect(DEF dst, USE crx, USE src); 9916 predicate(false); 9917 9918 ins_variable_size_depending_on_alignment(true); 9919 9920 format %{ "cmovL $crx, $dst, $src" %} 9921 // Worst case is branch + move + stop, no stop without scheduler. 9922 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8); 9923 ins_encode( enc_cmove_bso_stackSlotL(dst, crx, src) ); 9924 ins_pipe(pipe_class_default); 9925 %} 9926 9927 instruct cmovL_bso_stackSlotL_conLvalue0_Ex(iRegLdst dst, flagsReg crx, stackSlotL mem) %{ 9928 // no match-rule, false predicate 9929 effect(DEF dst, USE crx, USE mem); 9930 predicate(false); 9931 9932 format %{ "CmovL $dst, $crx, $mem \t// postalloc expanded" %} 9933 postalloc_expand %{ 9934 // 9935 // replaces 9936 // 9937 // region dst crx mem 9938 // \ | | / 9939 // dst=cmovL_bso_stackSlotL_conLvalue0 9940 // 9941 // with 9942 // 9943 // region dst 9944 // \ / 9945 // dst=loadConL16(0) 9946 // | 9947 // ^ region dst crx mem 9948 // | \ | | / 9949 // dst=cmovL_bso_stackSlotL 9950 // 9951 9952 // Create new nodes. 9953 MachNode *m1 = new (C) loadConL16Node(); 9954 MachNode *m2 = new (C) cmovL_bso_stackSlotLNode(); 9955 9956 // inputs for new nodes 9957 m1->add_req(n_region); 9958 m2->add_req(n_region, n_crx, n_mem); 9959 m2->add_prec(m1); 9960 9961 // operands for new nodes 9962 m1->_opnds[0] = op_dst; 9963 m1->_opnds[1] = new (C) immL16Oper(0); 9964 m2->_opnds[0] = op_dst; 9965 m2->_opnds[1] = op_crx; 9966 m2->_opnds[2] = op_mem; 9967 9968 // registers for new nodes 9969 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst 9970 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst 9971 9972 // Insert new nodes. 9973 nodes->push(m1); 9974 nodes->push(m2); 9975 %} 9976 %} 9977 9978 // Float to Long conversion, NaN is mapped to 0. 9979 instruct convF2L_reg_ExEx(iRegLdst dst, regF src) %{ 9980 match(Set dst (ConvF2L src)); 9981 ins_cost(DEFAULT_COST); 9982 9983 expand %{ 9984 regF tmpF; 9985 stackSlotL tmpS; 9986 flagsReg crx; 9987 cmpFUnordered_reg_reg(crx, src, src); // Check whether src is NaN. 9988 convF2LRaw_regF(tmpF, src); // Convert float to long (speculated). 9989 moveF2L_reg_stack(tmpS, tmpF); // Store float to stack (speculated). 9990 cmovL_bso_stackSlotL_conLvalue0_Ex(dst, crx, tmpS); // Cmove based on NaN check. 9991 %} 9992 %} 9993 9994 instruct convD2LRaw_regD(regD dst, regD src) %{ 9995 // no match-rule, false predicate 9996 effect(DEF dst, USE src); 9997 predicate(false); 9998 9999 format %{ "FCTIDZ $dst, $src \t// convD2L $src != NaN" %} 10000 size(4); 10001 ins_encode %{ 10002 // TODO: PPC port $archOpcode(ppc64Opcode_fctiwz); 10003 __ fctidz($dst$$FloatRegister, $src$$FloatRegister); 10004 %} 10005 ins_pipe(pipe_class_default); 10006 %} 10007 10008 // Double to Long conversion, NaN is mapped to 0. 10009 instruct convD2L_reg_ExEx(iRegLdst dst, regD src) %{ 10010 match(Set dst (ConvD2L src)); 10011 ins_cost(DEFAULT_COST); 10012 10013 expand %{ 10014 regD tmpD; 10015 stackSlotL tmpS; 10016 flagsReg crx; 10017 cmpDUnordered_reg_reg(crx, src, src); // Check whether src is NaN. 10018 convD2LRaw_regD(tmpD, src); // Convert float to long (speculated). 10019 moveD2L_reg_stack(tmpS, tmpD); // Store float to stack (speculated). 10020 cmovL_bso_stackSlotL_conLvalue0_Ex(dst, crx, tmpS); // Cmove based on NaN check. 10021 %} 10022 %} 10023 10024 // Convert to Float 10025 10026 // Placed here as needed in expand. 10027 instruct convL2DRaw_regD(regD dst, regD src) %{ 10028 // no match-rule, false predicate 10029 effect(DEF dst, USE src); 10030 predicate(false); 10031 10032 format %{ "FCFID $dst, $src \t// convL2D" %} 10033 size(4); 10034 ins_encode %{ 10035 // TODO: PPC port $archOpcode(ppc64Opcode_fcfid); 10036 __ fcfid($dst$$FloatRegister, $src$$FloatRegister); 10037 %} 10038 ins_pipe(pipe_class_default); 10039 %} 10040 10041 // Placed here as needed in expand. 10042 instruct convD2F_reg(regF dst, regD src) %{ 10043 match(Set dst (ConvD2F src)); 10044 format %{ "FRSP $dst, $src \t// convD2F" %} 10045 size(4); 10046 ins_encode %{ 10047 // TODO: PPC port $archOpcode(ppc64Opcode_frsp); 10048 __ frsp($dst$$FloatRegister, $src$$FloatRegister); 10049 %} 10050 ins_pipe(pipe_class_default); 10051 %} 10052 10053 // Integer to Float conversion. 10054 instruct convI2F_ireg_Ex(regF dst, iRegIsrc src) %{ 10055 match(Set dst (ConvI2F src)); 10056 predicate(!VM_Version::has_fcfids()); 10057 ins_cost(DEFAULT_COST); 10058 10059 expand %{ 10060 iRegLdst tmpL; 10061 stackSlotL tmpS; 10062 regD tmpD; 10063 regD tmpD2; 10064 convI2L_reg(tmpL, src); // Sign-extension int to long. 10065 regL_to_stkL(tmpS, tmpL); // Store long to stack. 10066 moveL2D_stack_reg(tmpD, tmpS); // Load long into double register. 10067 convL2DRaw_regD(tmpD2, tmpD); // Convert to double. 10068 convD2F_reg(dst, tmpD2); // Convert double to float. 10069 %} 10070 %} 10071 10072 instruct convL2FRaw_regF(regF dst, regD src) %{ 10073 // no match-rule, false predicate 10074 effect(DEF dst, USE src); 10075 predicate(false); 10076 10077 format %{ "FCFIDS $dst, $src \t// convL2F" %} 10078 size(4); 10079 ins_encode %{ 10080 // TODO: PPC port $archOpcode(ppc64Opcode_fcfid); 10081 __ fcfids($dst$$FloatRegister, $src$$FloatRegister); 10082 %} 10083 ins_pipe(pipe_class_default); 10084 %} 10085 10086 // Integer to Float conversion. Special version for Power7. 10087 instruct convI2F_ireg_fcfids_Ex(regF dst, iRegIsrc src) %{ 10088 match(Set dst (ConvI2F src)); 10089 predicate(VM_Version::has_fcfids()); 10090 ins_cost(DEFAULT_COST); 10091 10092 expand %{ 10093 iRegLdst tmpL; 10094 stackSlotL tmpS; 10095 regD tmpD; 10096 convI2L_reg(tmpL, src); // Sign-extension int to long. 10097 regL_to_stkL(tmpS, tmpL); // Store long to stack. 10098 moveL2D_stack_reg(tmpD, tmpS); // Load long into double register. 10099 convL2FRaw_regF(dst, tmpD); // Convert to float. 10100 %} 10101 %} 10102 10103 // L2F to avoid runtime call. 10104 instruct convL2F_ireg_fcfids_Ex(regF dst, iRegLsrc src) %{ 10105 match(Set dst (ConvL2F src)); 10106 predicate(VM_Version::has_fcfids()); 10107 ins_cost(DEFAULT_COST); 10108 10109 expand %{ 10110 stackSlotL tmpS; 10111 regD tmpD; 10112 regL_to_stkL(tmpS, src); // Store long to stack. 10113 moveL2D_stack_reg(tmpD, tmpS); // Load long into double register. 10114 convL2FRaw_regF(dst, tmpD); // Convert to float. 10115 %} 10116 %} 10117 10118 // Moved up as used in expand. 10119 //instruct convD2F_reg(regF dst, regD src) %{%} 10120 10121 // Convert to Double 10122 10123 // Integer to Double conversion. 10124 instruct convI2D_reg_Ex(regD dst, iRegIsrc src) %{ 10125 match(Set dst (ConvI2D src)); 10126 ins_cost(DEFAULT_COST); 10127 10128 expand %{ 10129 iRegLdst tmpL; 10130 stackSlotL tmpS; 10131 regD tmpD; 10132 convI2L_reg(tmpL, src); // Sign-extension int to long. 10133 regL_to_stkL(tmpS, tmpL); // Store long to stack. 10134 moveL2D_stack_reg(tmpD, tmpS); // Load long into double register. 10135 convL2DRaw_regD(dst, tmpD); // Convert to double. 10136 %} 10137 %} 10138 10139 // Long to Double conversion 10140 instruct convL2D_reg_Ex(regD dst, stackSlotL src) %{ 10141 match(Set dst (ConvL2D src)); 10142 ins_cost(DEFAULT_COST + MEMORY_REF_COST); 10143 10144 expand %{ 10145 regD tmpD; 10146 moveL2D_stack_reg(tmpD, src); 10147 convL2DRaw_regD(dst, tmpD); 10148 %} 10149 %} 10150 10151 instruct convF2D_reg(regD dst, regF src) %{ 10152 match(Set dst (ConvF2D src)); 10153 format %{ "FMR $dst, $src \t// float->double" %} 10154 // variable size, 0 or 4 10155 ins_encode %{ 10156 // TODO: PPC port $archOpcode(ppc64Opcode_fmr); 10157 __ fmr_if_needed($dst$$FloatRegister, $src$$FloatRegister); 10158 %} 10159 ins_pipe(pipe_class_default); 10160 %} 10161 10162 //----------Control Flow Instructions------------------------------------------ 10163 // Compare Instructions 10164 10165 // Compare Integers 10166 instruct cmpI_reg_reg(flagsReg crx, iRegIsrc src1, iRegIsrc src2) %{ 10167 match(Set crx (CmpI src1 src2)); 10168 size(4); 10169 format %{ "CMPW $crx, $src1, $src2" %} 10170 ins_encode %{ 10171 // TODO: PPC port $archOpcode(ppc64Opcode_cmp); 10172 __ cmpw($crx$$CondRegister, $src1$$Register, $src2$$Register); 10173 %} 10174 ins_pipe(pipe_class_compare); 10175 %} 10176 10177 instruct cmpI_reg_imm16(flagsReg crx, iRegIsrc src1, immI16 src2) %{ 10178 match(Set crx (CmpI src1 src2)); 10179 format %{ "CMPWI $crx, $src1, $src2" %} 10180 size(4); 10181 ins_encode %{ 10182 // TODO: PPC port $archOpcode(ppc64Opcode_cmpi); 10183 __ cmpwi($crx$$CondRegister, $src1$$Register, $src2$$constant); 10184 %} 10185 ins_pipe(pipe_class_compare); 10186 %} 10187 10188 // (src1 & src2) == 0? 10189 instruct testI_reg_imm(flagsRegCR0 cr0, iRegIsrc src1, uimmI16 src2, immI_0 zero) %{ 10190 match(Set cr0 (CmpI (AndI src1 src2) zero)); 10191 // r0 is killed 10192 format %{ "ANDI R0, $src1, $src2 \t// BTST int" %} 10193 size(4); 10194 ins_encode %{ 10195 // TODO: PPC port $archOpcode(ppc64Opcode_andi_); 10196 // FIXME: avoid andi_ ? 10197 __ andi_(R0, $src1$$Register, $src2$$constant); 10198 %} 10199 ins_pipe(pipe_class_compare); 10200 %} 10201 10202 instruct cmpL_reg_reg(flagsReg crx, iRegLsrc src1, iRegLsrc src2) %{ 10203 match(Set crx (CmpL src1 src2)); 10204 format %{ "CMPD $crx, $src1, $src2" %} 10205 size(4); 10206 ins_encode %{ 10207 // TODO: PPC port $archOpcode(ppc64Opcode_cmp); 10208 __ cmpd($crx$$CondRegister, $src1$$Register, $src2$$Register); 10209 %} 10210 ins_pipe(pipe_class_compare); 10211 %} 10212 10213 instruct cmpL_reg_imm16(flagsReg crx, iRegLsrc src1, immL16 src2) %{ 10214 match(Set crx (CmpL src1 src2)); 10215 format %{ "CMPDI $crx, $src1, $src2" %} 10216 size(4); 10217 ins_encode %{ 10218 // TODO: PPC port $archOpcode(ppc64Opcode_cmpi); 10219 __ cmpdi($crx$$CondRegister, $src1$$Register, $src2$$constant); 10220 %} 10221 ins_pipe(pipe_class_compare); 10222 %} 10223 10224 instruct testL_reg_reg(flagsRegCR0 cr0, iRegLsrc src1, iRegLsrc src2, immL_0 zero) %{ 10225 match(Set cr0 (CmpL (AndL src1 src2) zero)); 10226 // r0 is killed 10227 format %{ "AND R0, $src1, $src2 \t// BTST long" %} 10228 size(4); 10229 ins_encode %{ 10230 // TODO: PPC port $archOpcode(ppc64Opcode_and_); 10231 __ and_(R0, $src1$$Register, $src2$$Register); 10232 %} 10233 ins_pipe(pipe_class_compare); 10234 %} 10235 10236 instruct testL_reg_imm(flagsRegCR0 cr0, iRegLsrc src1, uimmL16 src2, immL_0 zero) %{ 10237 match(Set cr0 (CmpL (AndL src1 src2) zero)); 10238 // r0 is killed 10239 format %{ "ANDI R0, $src1, $src2 \t// BTST long" %} 10240 size(4); 10241 ins_encode %{ 10242 // TODO: PPC port $archOpcode(ppc64Opcode_andi_); 10243 // FIXME: avoid andi_ ? 10244 __ andi_(R0, $src1$$Register, $src2$$constant); 10245 %} 10246 ins_pipe(pipe_class_compare); 10247 %} 10248 10249 instruct cmovI_conIvalueMinus1_conIvalue1(iRegIdst dst, flagsReg crx) %{ 10250 // no match-rule, false predicate 10251 effect(DEF dst, USE crx); 10252 predicate(false); 10253 10254 ins_variable_size_depending_on_alignment(true); 10255 10256 format %{ "cmovI $crx, $dst, -1, 0, +1" %} 10257 // Worst case is branch + move + branch + move + stop, no stop without scheduler. 10258 size(false /* TODO: PPC PORTInsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 20 : 16); 10259 ins_encode %{ 10260 // TODO: PPC port $archOpcode(ppc64Opcode_cmove); 10261 Label done; 10262 // li(Rdst, 0); // equal -> 0 10263 __ beq($crx$$CondRegister, done); 10264 __ li($dst$$Register, 1); // greater -> +1 10265 __ bgt($crx$$CondRegister, done); 10266 __ li($dst$$Register, -1); // unordered or less -> -1 10267 // TODO: PPC port__ endgroup_if_needed(_size == 20); 10268 __ bind(done); 10269 %} 10270 ins_pipe(pipe_class_compare); 10271 %} 10272 10273 instruct cmovI_conIvalueMinus1_conIvalue0_conIvalue1_Ex(iRegIdst dst, flagsReg crx) %{ 10274 // no match-rule, false predicate 10275 effect(DEF dst, USE crx); 10276 predicate(false); 10277 10278 format %{ "CmovI $crx, $dst, -1, 0, +1 \t// postalloc expanded" %} 10279 postalloc_expand %{ 10280 // 10281 // replaces 10282 // 10283 // region crx 10284 // \ | 10285 // dst=cmovI_conIvalueMinus1_conIvalue0_conIvalue1 10286 // 10287 // with 10288 // 10289 // region 10290 // \ 10291 // dst=loadConI16(0) 10292 // | 10293 // ^ region crx 10294 // | \ | 10295 // dst=cmovI_conIvalueMinus1_conIvalue1 10296 // 10297 10298 // Create new nodes. 10299 MachNode *m1 = new (C) loadConI16Node(); 10300 MachNode *m2 = new (C) cmovI_conIvalueMinus1_conIvalue1Node(); 10301 10302 // inputs for new nodes 10303 m1->add_req(n_region); 10304 m2->add_req(n_region, n_crx); 10305 m2->add_prec(m1); 10306 10307 // operands for new nodes 10308 m1->_opnds[0] = op_dst; 10309 m1->_opnds[1] = new (C) immI16Oper(0); 10310 m2->_opnds[0] = op_dst; 10311 m2->_opnds[1] = op_crx; 10312 10313 // registers for new nodes 10314 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst 10315 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst 10316 10317 // Insert new nodes. 10318 nodes->push(m1); 10319 nodes->push(m2); 10320 %} 10321 %} 10322 10323 // Manifest a CmpL3 result in an integer register. Very painful. 10324 // This is the test to avoid. 10325 // (src1 < src2) ? -1 : ((src1 > src2) ? 1 : 0) 10326 instruct cmpL3_reg_reg_ExEx(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{ 10327 match(Set dst (CmpL3 src1 src2)); 10328 ins_cost(DEFAULT_COST*5+BRANCH_COST); 10329 10330 expand %{ 10331 flagsReg tmp1; 10332 cmpL_reg_reg(tmp1, src1, src2); 10333 cmovI_conIvalueMinus1_conIvalue0_conIvalue1_Ex(dst, tmp1); 10334 %} 10335 %} 10336 10337 // Implicit range checks. 10338 // A range check in the ideal world has one of the following shapes: 10339 // - (If le (CmpU length index)), (IfTrue throw exception) 10340 // - (If lt (CmpU index length)), (IfFalse throw exception) 10341 // 10342 // Match range check 'If le (CmpU length index)'. 10343 instruct rangeCheck_iReg_uimm15(cmpOp cmp, iRegIsrc src_length, uimmI15 index, label labl) %{ 10344 match(If cmp (CmpU src_length index)); 10345 effect(USE labl); 10346 predicate(TrapBasedRangeChecks && 10347 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le && 10348 PROB_UNLIKELY(_leaf->as_If()->_prob) >= PROB_ALWAYS && 10349 (Matcher::branches_to_uncommon_trap(_leaf))); 10350 10351 ins_is_TrapBasedCheckNode(true); 10352 10353 format %{ "TWI $index $cmp $src_length \t// RangeCheck => trap $labl" %} 10354 size(4); 10355 ins_encode %{ 10356 // TODO: PPC port $archOpcode(ppc64Opcode_twi); 10357 if ($cmp$$cmpcode == 0x1 /* less_equal */) { 10358 __ trap_range_check_le($src_length$$Register, $index$$constant); 10359 } else { 10360 // Both successors are uncommon traps, probability is 0. 10361 // Node got flipped during fixup flow. 10362 assert($cmp$$cmpcode == 0x9, "must be greater"); 10363 __ trap_range_check_g($src_length$$Register, $index$$constant); 10364 } 10365 %} 10366 ins_pipe(pipe_class_trap); 10367 %} 10368 10369 // Match range check 'If lt (CmpU index length)'. 10370 instruct rangeCheck_iReg_iReg(cmpOp cmp, iRegIsrc src_index, iRegIsrc src_length, label labl) %{ 10371 match(If cmp (CmpU src_index src_length)); 10372 effect(USE labl); 10373 predicate(TrapBasedRangeChecks && 10374 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt && 10375 _leaf->as_If()->_prob >= PROB_ALWAYS && 10376 (Matcher::branches_to_uncommon_trap(_leaf))); 10377 10378 ins_is_TrapBasedCheckNode(true); 10379 10380 format %{ "TW $src_index $cmp $src_length \t// RangeCheck => trap $labl" %} 10381 size(4); 10382 ins_encode %{ 10383 // TODO: PPC port $archOpcode(ppc64Opcode_tw); 10384 if ($cmp$$cmpcode == 0x0 /* greater_equal */) { 10385 __ trap_range_check_ge($src_index$$Register, $src_length$$Register); 10386 } else { 10387 // Both successors are uncommon traps, probability is 0. 10388 // Node got flipped during fixup flow. 10389 assert($cmp$$cmpcode == 0x8, "must be less"); 10390 __ trap_range_check_l($src_index$$Register, $src_length$$Register); 10391 } 10392 %} 10393 ins_pipe(pipe_class_trap); 10394 %} 10395 10396 // Match range check 'If lt (CmpU index length)'. 10397 instruct rangeCheck_uimm15_iReg(cmpOp cmp, iRegIsrc src_index, uimmI15 length, label labl) %{ 10398 match(If cmp (CmpU src_index length)); 10399 effect(USE labl); 10400 predicate(TrapBasedRangeChecks && 10401 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt && 10402 _leaf->as_If()->_prob >= PROB_ALWAYS && 10403 (Matcher::branches_to_uncommon_trap(_leaf))); 10404 10405 ins_is_TrapBasedCheckNode(true); 10406 10407 format %{ "TWI $src_index $cmp $length \t// RangeCheck => trap $labl" %} 10408 size(4); 10409 ins_encode %{ 10410 // TODO: PPC port $archOpcode(ppc64Opcode_twi); 10411 if ($cmp$$cmpcode == 0x0 /* greater_equal */) { 10412 __ trap_range_check_ge($src_index$$Register, $length$$constant); 10413 } else { 10414 // Both successors are uncommon traps, probability is 0. 10415 // Node got flipped during fixup flow. 10416 assert($cmp$$cmpcode == 0x8, "must be less"); 10417 __ trap_range_check_l($src_index$$Register, $length$$constant); 10418 } 10419 %} 10420 ins_pipe(pipe_class_trap); 10421 %} 10422 10423 instruct compU_reg_reg(flagsReg crx, iRegIsrc src1, iRegIsrc src2) %{ 10424 match(Set crx (CmpU src1 src2)); 10425 format %{ "CMPLW $crx, $src1, $src2 \t// unsigned" %} 10426 size(4); 10427 ins_encode %{ 10428 // TODO: PPC port $archOpcode(ppc64Opcode_cmpl); 10429 __ cmplw($crx$$CondRegister, $src1$$Register, $src2$$Register); 10430 %} 10431 ins_pipe(pipe_class_compare); 10432 %} 10433 10434 instruct compU_reg_uimm16(flagsReg crx, iRegIsrc src1, uimmI16 src2) %{ 10435 match(Set crx (CmpU src1 src2)); 10436 size(4); 10437 format %{ "CMPLWI $crx, $src1, $src2" %} 10438 ins_encode %{ 10439 // TODO: PPC port $archOpcode(ppc64Opcode_cmpli); 10440 __ cmplwi($crx$$CondRegister, $src1$$Register, $src2$$constant); 10441 %} 10442 ins_pipe(pipe_class_compare); 10443 %} 10444 10445 // Implicit zero checks (more implicit null checks). 10446 // No constant pool entries required. 10447 instruct zeroCheckN_iReg_imm0(cmpOp cmp, iRegNsrc value, immN_0 zero, label labl) %{ 10448 match(If cmp (CmpN value zero)); 10449 effect(USE labl); 10450 predicate(TrapBasedNullChecks && 10451 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne && 10452 _leaf->as_If()->_prob >= PROB_LIKELY_MAG(4) && 10453 Matcher::branches_to_uncommon_trap(_leaf)); 10454 ins_cost(1); 10455 10456 ins_is_TrapBasedCheckNode(true); 10457 10458 format %{ "TDI $value $cmp $zero \t// ZeroCheckN => trap $labl" %} 10459 size(4); 10460 ins_encode %{ 10461 // TODO: PPC port $archOpcode(ppc64Opcode_tdi); 10462 if ($cmp$$cmpcode == 0xA) { 10463 __ trap_null_check($value$$Register); 10464 } else { 10465 // Both successors are uncommon traps, probability is 0. 10466 // Node got flipped during fixup flow. 10467 assert($cmp$$cmpcode == 0x2 , "must be equal(0xA) or notEqual(0x2)"); 10468 __ trap_null_check($value$$Register, Assembler::traptoGreaterThanUnsigned); 10469 } 10470 %} 10471 ins_pipe(pipe_class_trap); 10472 %} 10473 10474 // Compare narrow oops. 10475 instruct cmpN_reg_reg(flagsReg crx, iRegNsrc src1, iRegNsrc src2) %{ 10476 match(Set crx (CmpN src1 src2)); 10477 10478 size(4); 10479 ins_cost(DEFAULT_COST); 10480 format %{ "CMPLW $crx, $src1, $src2 \t// compressed ptr" %} 10481 ins_encode %{ 10482 // TODO: PPC port $archOpcode(ppc64Opcode_cmpl); 10483 __ cmplw($crx$$CondRegister, $src1$$Register, $src2$$Register); 10484 %} 10485 ins_pipe(pipe_class_compare); 10486 %} 10487 10488 instruct cmpN_reg_imm0(flagsReg crx, iRegNsrc src1, immN_0 src2) %{ 10489 match(Set crx (CmpN src1 src2)); 10490 // Make this more expensive than zeroCheckN_iReg_imm0. 10491 ins_cost(DEFAULT_COST); 10492 10493 format %{ "CMPLWI $crx, $src1, $src2 \t// compressed ptr" %} 10494 size(4); 10495 ins_encode %{ 10496 // TODO: PPC port $archOpcode(ppc64Opcode_cmpli); 10497 __ cmplwi($crx$$CondRegister, $src1$$Register, $src2$$constant); 10498 %} 10499 ins_pipe(pipe_class_compare); 10500 %} 10501 10502 // Implicit zero checks (more implicit null checks). 10503 // No constant pool entries required. 10504 instruct zeroCheckP_reg_imm0(cmpOp cmp, iRegP_N2P value, immP_0 zero, label labl) %{ 10505 match(If cmp (CmpP value zero)); 10506 effect(USE labl); 10507 predicate(TrapBasedNullChecks && 10508 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne && 10509 _leaf->as_If()->_prob >= PROB_LIKELY_MAG(4) && 10510 Matcher::branches_to_uncommon_trap(_leaf)); 10511 10512 ins_is_TrapBasedCheckNode(true); 10513 10514 format %{ "TDI $value $cmp $zero \t// ZeroCheckP => trap $labl" %} 10515 size(4); 10516 ins_encode %{ 10517 // TODO: PPC port $archOpcode(ppc64Opcode_tdi); 10518 if ($cmp$$cmpcode == 0xA) { 10519 __ trap_null_check($value$$Register); 10520 } else { 10521 // Both successors are uncommon traps, probability is 0. 10522 // Node got flipped during fixup flow. 10523 assert($cmp$$cmpcode == 0x2 , "must be equal(0xA) or notEqual(0x2)"); 10524 __ trap_null_check($value$$Register, Assembler::traptoGreaterThanUnsigned); 10525 } 10526 %} 10527 ins_pipe(pipe_class_trap); 10528 %} 10529 10530 // Compare Pointers 10531 instruct cmpP_reg_reg(flagsReg crx, iRegP_N2P src1, iRegP_N2P src2) %{ 10532 match(Set crx (CmpP src1 src2)); 10533 format %{ "CMPLD $crx, $src1, $src2 \t// ptr" %} 10534 size(4); 10535 ins_encode %{ 10536 // TODO: PPC port $archOpcode(ppc64Opcode_cmpl); 10537 __ cmpld($crx$$CondRegister, $src1$$Register, $src2$$Register); 10538 %} 10539 ins_pipe(pipe_class_compare); 10540 %} 10541 10542 // Used in postalloc expand. 10543 instruct cmpP_reg_imm16(flagsReg crx, iRegPsrc src1, immL16 src2) %{ 10544 // This match rule prevents reordering of node before a safepoint. 10545 // This only makes sense if this instructions is used exclusively 10546 // for the expansion of EncodeP! 10547 match(Set crx (CmpP src1 src2)); 10548 predicate(false); 10549 10550 format %{ "CMPDI $crx, $src1, $src2" %} 10551 size(4); 10552 ins_encode %{ 10553 // TODO: PPC port $archOpcode(ppc64Opcode_cmpi); 10554 __ cmpdi($crx$$CondRegister, $src1$$Register, $src2$$constant); 10555 %} 10556 ins_pipe(pipe_class_compare); 10557 %} 10558 10559 //----------Float Compares---------------------------------------------------- 10560 10561 instruct cmpFUnordered_reg_reg(flagsReg crx, regF src1, regF src2) %{ 10562 // no match-rule, false predicate 10563 effect(DEF crx, USE src1, USE src2); 10564 predicate(false); 10565 10566 format %{ "cmpFUrd $crx, $src1, $src2" %} 10567 size(4); 10568 ins_encode %{ 10569 // TODO: PPC port $archOpcode(ppc64Opcode_fcmpu); 10570 __ fcmpu($crx$$CondRegister, $src1$$FloatRegister, $src2$$FloatRegister); 10571 %} 10572 ins_pipe(pipe_class_default); 10573 %} 10574 10575 instruct cmov_bns_less(flagsReg crx) %{ 10576 // no match-rule, false predicate 10577 effect(DEF crx); 10578 predicate(false); 10579 10580 ins_variable_size_depending_on_alignment(true); 10581 10582 format %{ "cmov $crx" %} 10583 // Worst case is branch + move + stop, no stop without scheduler. 10584 size(false /* TODO: PPC PORT(InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 16 : 12); 10585 ins_encode %{ 10586 // TODO: PPC port $archOpcode(ppc64Opcode_cmovecr); 10587 Label done; 10588 __ bns($crx$$CondRegister, done); // not unordered -> keep crx 10589 __ li(R0, 0); 10590 __ cmpwi($crx$$CondRegister, R0, 1); // unordered -> set crx to 'less' 10591 // TODO PPC port __ endgroup_if_needed(_size == 16); 10592 __ bind(done); 10593 %} 10594 ins_pipe(pipe_class_default); 10595 %} 10596 10597 // Compare floating, generate condition code. 10598 instruct cmpF_reg_reg_Ex(flagsReg crx, regF src1, regF src2) %{ 10599 // FIXME: should we match 'If cmp (CmpF src1 src2))' ?? 10600 // 10601 // The following code sequence occurs a lot in mpegaudio: 10602 // 10603 // block BXX: 10604 // 0: instruct cmpFUnordered_reg_reg (cmpF_reg_reg-0): 10605 // cmpFUrd CCR6, F11, F9 10606 // 4: instruct cmov_bns_less (cmpF_reg_reg-1): 10607 // cmov CCR6 10608 // 8: instruct branchConSched: 10609 // B_FARle CCR6, B56 P=0.500000 C=-1.000000 10610 match(Set crx (CmpF src1 src2)); 10611 ins_cost(DEFAULT_COST+BRANCH_COST); 10612 10613 format %{ "CmpF $crx, $src1, $src2 \t// postalloc expanded" %} 10614 postalloc_expand %{ 10615 // 10616 // replaces 10617 // 10618 // region src1 src2 10619 // \ | | 10620 // crx=cmpF_reg_reg 10621 // 10622 // with 10623 // 10624 // region src1 src2 10625 // \ | | 10626 // crx=cmpFUnordered_reg_reg 10627 // | 10628 // ^ region 10629 // | \ 10630 // crx=cmov_bns_less 10631 // 10632 10633 // Create new nodes. 10634 MachNode *m1 = new (C) cmpFUnordered_reg_regNode(); 10635 MachNode *m2 = new (C) cmov_bns_lessNode(); 10636 10637 // inputs for new nodes 10638 m1->add_req(n_region, n_src1, n_src2); 10639 m2->add_req(n_region); 10640 m2->add_prec(m1); 10641 10642 // operands for new nodes 10643 m1->_opnds[0] = op_crx; 10644 m1->_opnds[1] = op_src1; 10645 m1->_opnds[2] = op_src2; 10646 m2->_opnds[0] = op_crx; 10647 10648 // registers for new nodes 10649 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // crx 10650 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // crx 10651 10652 // Insert new nodes. 10653 nodes->push(m1); 10654 nodes->push(m2); 10655 %} 10656 %} 10657 10658 // Compare float, generate -1,0,1 10659 instruct cmpF3_reg_reg_ExEx(iRegIdst dst, regF src1, regF src2) %{ 10660 match(Set dst (CmpF3 src1 src2)); 10661 ins_cost(DEFAULT_COST*5+BRANCH_COST); 10662 10663 expand %{ 10664 flagsReg tmp1; 10665 cmpFUnordered_reg_reg(tmp1, src1, src2); 10666 cmovI_conIvalueMinus1_conIvalue0_conIvalue1_Ex(dst, tmp1); 10667 %} 10668 %} 10669 10670 instruct cmpDUnordered_reg_reg(flagsReg crx, regD src1, regD src2) %{ 10671 // no match-rule, false predicate 10672 effect(DEF crx, USE src1, USE src2); 10673 predicate(false); 10674 10675 format %{ "cmpFUrd $crx, $src1, $src2" %} 10676 size(4); 10677 ins_encode %{ 10678 // TODO: PPC port $archOpcode(ppc64Opcode_fcmpu); 10679 __ fcmpu($crx$$CondRegister, $src1$$FloatRegister, $src2$$FloatRegister); 10680 %} 10681 ins_pipe(pipe_class_default); 10682 %} 10683 10684 instruct cmpD_reg_reg_Ex(flagsReg crx, regD src1, regD src2) %{ 10685 match(Set crx (CmpD src1 src2)); 10686 ins_cost(DEFAULT_COST+BRANCH_COST); 10687 10688 format %{ "CmpD $crx, $src1, $src2 \t// postalloc expanded" %} 10689 postalloc_expand %{ 10690 // 10691 // replaces 10692 // 10693 // region src1 src2 10694 // \ | | 10695 // crx=cmpD_reg_reg 10696 // 10697 // with 10698 // 10699 // region src1 src2 10700 // \ | | 10701 // crx=cmpDUnordered_reg_reg 10702 // | 10703 // ^ region 10704 // | \ 10705 // crx=cmov_bns_less 10706 // 10707 10708 // create new nodes 10709 MachNode *m1 = new (C) cmpDUnordered_reg_regNode(); 10710 MachNode *m2 = new (C) cmov_bns_lessNode(); 10711 10712 // inputs for new nodes 10713 m1->add_req(n_region, n_src1, n_src2); 10714 m2->add_req(n_region); 10715 m2->add_prec(m1); 10716 10717 // operands for new nodes 10718 m1->_opnds[0] = op_crx; 10719 m1->_opnds[1] = op_src1; 10720 m1->_opnds[2] = op_src2; 10721 m2->_opnds[0] = op_crx; 10722 10723 // registers for new nodes 10724 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // crx 10725 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // crx 10726 10727 // Insert new nodes. 10728 nodes->push(m1); 10729 nodes->push(m2); 10730 %} 10731 %} 10732 10733 // Compare double, generate -1,0,1 10734 instruct cmpD3_reg_reg_ExEx(iRegIdst dst, regD src1, regD src2) %{ 10735 match(Set dst (CmpD3 src1 src2)); 10736 ins_cost(DEFAULT_COST*5+BRANCH_COST); 10737 10738 expand %{ 10739 flagsReg tmp1; 10740 cmpDUnordered_reg_reg(tmp1, src1, src2); 10741 cmovI_conIvalueMinus1_conIvalue0_conIvalue1_Ex(dst, tmp1); 10742 %} 10743 %} 10744 10745 //----------Branches--------------------------------------------------------- 10746 // Jump 10747 10748 // Direct Branch. 10749 instruct branch(label labl) %{ 10750 match(Goto); 10751 effect(USE labl); 10752 ins_cost(BRANCH_COST); 10753 10754 format %{ "B $labl" %} 10755 size(4); 10756 ins_encode %{ 10757 // TODO: PPC port $archOpcode(ppc64Opcode_b); 10758 Label d; // dummy 10759 __ bind(d); 10760 Label* p = $labl$$label; 10761 // `p' is `NULL' when this encoding class is used only to 10762 // determine the size of the encoded instruction. 10763 Label& l = (NULL == p)? d : *(p); 10764 __ b(l); 10765 %} 10766 ins_pipe(pipe_class_default); 10767 %} 10768 10769 // Conditional Near Branch 10770 instruct branchCon(cmpOp cmp, flagsReg crx, label lbl) %{ 10771 // Same match rule as `branchConFar'. 10772 match(If cmp crx); 10773 effect(USE lbl); 10774 ins_cost(BRANCH_COST); 10775 10776 // If set to 1 this indicates that the current instruction is a 10777 // short variant of a long branch. This avoids using this 10778 // instruction in first-pass matching. It will then only be used in 10779 // the `Shorten_branches' pass. 10780 ins_short_branch(1); 10781 10782 format %{ "B$cmp $crx, $lbl" %} 10783 size(4); 10784 ins_encode( enc_bc(crx, cmp, lbl) ); 10785 ins_pipe(pipe_class_default); 10786 %} 10787 10788 // This is for cases when the ppc64 `bc' instruction does not 10789 // reach far enough. So we emit a far branch here, which is more 10790 // expensive. 10791 // 10792 // Conditional Far Branch 10793 instruct branchConFar(cmpOp cmp, flagsReg crx, label lbl) %{ 10794 // Same match rule as `branchCon'. 10795 match(If cmp crx); 10796 effect(USE crx, USE lbl); 10797 predicate(!false /* TODO: PPC port HB_Schedule*/); 10798 // Higher cost than `branchCon'. 10799 ins_cost(5*BRANCH_COST); 10800 10801 // This is not a short variant of a branch, but the long variant. 10802 ins_short_branch(0); 10803 10804 format %{ "B_FAR$cmp $crx, $lbl" %} 10805 size(8); 10806 ins_encode( enc_bc_far(crx, cmp, lbl) ); 10807 ins_pipe(pipe_class_default); 10808 %} 10809 10810 // Conditional Branch used with Power6 scheduler (can be far or short). 10811 instruct branchConSched(cmpOp cmp, flagsReg crx, label lbl) %{ 10812 // Same match rule as `branchCon'. 10813 match(If cmp crx); 10814 effect(USE crx, USE lbl); 10815 predicate(false /* TODO: PPC port HB_Schedule*/); 10816 // Higher cost than `branchCon'. 10817 ins_cost(5*BRANCH_COST); 10818 10819 // Actually size doesn't depend on alignment but on shortening. 10820 ins_variable_size_depending_on_alignment(true); 10821 // long variant. 10822 ins_short_branch(0); 10823 10824 format %{ "B_FAR$cmp $crx, $lbl" %} 10825 size(8); // worst case 10826 ins_encode( enc_bc_short_far(crx, cmp, lbl) ); 10827 ins_pipe(pipe_class_default); 10828 %} 10829 10830 instruct branchLoopEnd(cmpOp cmp, flagsReg crx, label labl) %{ 10831 match(CountedLoopEnd cmp crx); 10832 effect(USE labl); 10833 ins_cost(BRANCH_COST); 10834 10835 // short variant. 10836 ins_short_branch(1); 10837 10838 format %{ "B$cmp $crx, $labl \t// counted loop end" %} 10839 size(4); 10840 ins_encode( enc_bc(crx, cmp, labl) ); 10841 ins_pipe(pipe_class_default); 10842 %} 10843 10844 instruct branchLoopEndFar(cmpOp cmp, flagsReg crx, label labl) %{ 10845 match(CountedLoopEnd cmp crx); 10846 effect(USE labl); 10847 predicate(!false /* TODO: PPC port HB_Schedule */); 10848 ins_cost(BRANCH_COST); 10849 10850 // Long variant. 10851 ins_short_branch(0); 10852 10853 format %{ "B_FAR$cmp $crx, $labl \t// counted loop end" %} 10854 size(8); 10855 ins_encode( enc_bc_far(crx, cmp, labl) ); 10856 ins_pipe(pipe_class_default); 10857 %} 10858 10859 // Conditional Branch used with Power6 scheduler (can be far or short). 10860 instruct branchLoopEndSched(cmpOp cmp, flagsReg crx, label labl) %{ 10861 match(CountedLoopEnd cmp crx); 10862 effect(USE labl); 10863 predicate(false /* TODO: PPC port HB_Schedule */); 10864 // Higher cost than `branchCon'. 10865 ins_cost(5*BRANCH_COST); 10866 10867 // Actually size doesn't depend on alignment but on shortening. 10868 ins_variable_size_depending_on_alignment(true); 10869 // Long variant. 10870 ins_short_branch(0); 10871 10872 format %{ "B_FAR$cmp $crx, $labl \t// counted loop end" %} 10873 size(8); // worst case 10874 ins_encode( enc_bc_short_far(crx, cmp, labl) ); 10875 ins_pipe(pipe_class_default); 10876 %} 10877 10878 // ============================================================================ 10879 // Java runtime operations, intrinsics and other complex operations. 10880 10881 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass 10882 // array for an instance of the superklass. Set a hidden internal cache on a 10883 // hit (cache is checked with exposed code in gen_subtype_check()). Return 10884 // not zero for a miss or zero for a hit. The encoding ALSO sets flags. 10885 // 10886 // GL TODO: Improve this. 10887 // - result should not be a TEMP 10888 // - Add match rule as on sparc avoiding additional Cmp. 10889 instruct partialSubtypeCheck(iRegPdst result, iRegP_N2P subklass, iRegP_N2P superklass, 10890 iRegPdst tmp_klass, iRegPdst tmp_arrayptr) %{ 10891 match(Set result (PartialSubtypeCheck subklass superklass)); 10892 effect(TEMP result, TEMP tmp_klass, TEMP tmp_arrayptr); 10893 ins_cost(DEFAULT_COST*10); 10894 10895 format %{ "PartialSubtypeCheck $result = ($subklass instanceOf $superklass) tmp: $tmp_klass, $tmp_arrayptr" %} 10896 ins_encode %{ 10897 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 10898 __ check_klass_subtype_slow_path($subklass$$Register, $superklass$$Register, $tmp_arrayptr$$Register, 10899 $tmp_klass$$Register, NULL, $result$$Register); 10900 %} 10901 ins_pipe(pipe_class_default); 10902 %} 10903 10904 // inlined locking and unlocking 10905 10906 instruct cmpFastLock(flagsReg crx, iRegPdst oop, iRegPdst box, iRegPdst tmp1, iRegPdst tmp2, iRegPdst tmp3) %{ 10907 match(Set crx (FastLock oop box)); 10908 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3); 10909 // TODO PPC port predicate(!UseNewFastLockPPC64 || UseBiasedLocking); 10910 10911 format %{ "FASTLOCK $oop, $box, $tmp1, $tmp2, $tmp3" %} 10912 ins_encode %{ 10913 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 10914 __ compiler_fast_lock_object($crx$$CondRegister, $oop$$Register, $box$$Register, 10915 $tmp3$$Register, $tmp1$$Register, $tmp2$$Register); 10916 // If locking was successfull, crx should indicate 'EQ'. 10917 // The compiler generates a branch to the runtime call to 10918 // _complete_monitor_locking_Java for the case where crx is 'NE'. 10919 %} 10920 ins_pipe(pipe_class_compare); 10921 %} 10922 10923 instruct cmpFastUnlock(flagsReg crx, iRegPdst oop, iRegPdst box, iRegPdst tmp1, iRegPdst tmp2, iRegPdst tmp3) %{ 10924 match(Set crx (FastUnlock oop box)); 10925 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3); 10926 10927 format %{ "FASTUNLOCK $oop, $box, $tmp1, $tmp2" %} 10928 ins_encode %{ 10929 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 10930 __ compiler_fast_unlock_object($crx$$CondRegister, $oop$$Register, $box$$Register, 10931 $tmp3$$Register, $tmp1$$Register, $tmp2$$Register); 10932 // If unlocking was successfull, crx should indicate 'EQ'. 10933 // The compiler generates a branch to the runtime call to 10934 // _complete_monitor_unlocking_Java for the case where crx is 'NE'. 10935 %} 10936 ins_pipe(pipe_class_compare); 10937 %} 10938 10939 // Align address. 10940 instruct align_addr(iRegPdst dst, iRegPsrc src, immLnegpow2 mask) %{ 10941 match(Set dst (CastX2P (AndL (CastP2X src) mask))); 10942 10943 format %{ "ANDDI $dst, $src, $mask \t// next aligned address" %} 10944 size(4); 10945 ins_encode %{ 10946 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr); 10947 __ clrrdi($dst$$Register, $src$$Register, log2_long((jlong)-$mask$$constant)); 10948 %} 10949 ins_pipe(pipe_class_default); 10950 %} 10951 10952 // Array size computation. 10953 instruct array_size(iRegLdst dst, iRegPsrc end, iRegPsrc start) %{ 10954 match(Set dst (SubL (CastP2X end) (CastP2X start))); 10955 10956 format %{ "SUB $dst, $end, $start \t// array size in bytes" %} 10957 size(4); 10958 ins_encode %{ 10959 // TODO: PPC port $archOpcode(ppc64Opcode_subf); 10960 __ subf($dst$$Register, $start$$Register, $end$$Register); 10961 %} 10962 ins_pipe(pipe_class_default); 10963 %} 10964 10965 // Clear-array with dynamic array-size. 10966 instruct inlineCallClearArray(rarg1RegL cnt, rarg2RegP base, Universe dummy, regCTR ctr) %{ 10967 match(Set dummy (ClearArray cnt base)); 10968 effect(USE_KILL cnt, USE_KILL base, KILL ctr); 10969 ins_cost(MEMORY_REF_COST); 10970 10971 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted. 10972 10973 format %{ "ClearArray $cnt, $base" %} 10974 ins_encode %{ 10975 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 10976 __ clear_memory_doubleword($base$$Register, $cnt$$Register); // kills cnt, base, R0 10977 %} 10978 ins_pipe(pipe_class_default); 10979 %} 10980 10981 // String_IndexOf for needle of length 1. 10982 // 10983 // Match needle into immediate operands: no loadConP node needed. Saves one 10984 // register and two instructions over string_indexOf_imm1Node. 10985 // 10986 // Assumes register result differs from all input registers. 10987 // 10988 // Preserves registers haystack, haycnt 10989 // Kills registers tmp1, tmp2 10990 // Defines registers result 10991 // 10992 // Use dst register classes if register gets killed, as it is the case for tmp registers! 10993 // 10994 // Unfortunately this does not match too often. In many situations the AddP is used 10995 // by several nodes, even several StrIndexOf nodes, breaking the match tree. 10996 instruct string_indexOf_imm1_char(iRegIdst result, iRegPsrc haystack, iRegIsrc haycnt, 10997 immP needleImm, immL offsetImm, immI_1 needlecntImm, 10998 iRegIdst tmp1, iRegIdst tmp2, 10999 flagsRegCR0 cr0, flagsRegCR1 cr1) %{ 11000 predicate(SpecialStringIndexOf); // type check implicit by parameter type, See Matcher::match_rule_supported 11001 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary (AddP needleImm offsetImm) needlecntImm))); 11002 11003 effect(TEMP result, TEMP tmp1, TEMP tmp2, KILL cr0, KILL cr1); 11004 11005 ins_cost(150); 11006 format %{ "String IndexOf CSCL1 $haystack[0..$haycnt], $needleImm+$offsetImm[0..$needlecntImm]" 11007 "-> $result \t// KILL $haycnt, $tmp1, $tmp2, $cr0, $cr1" %} 11008 11009 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted 11010 ins_encode %{ 11011 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 11012 immPOper *needleOper = (immPOper *)$needleImm; 11013 const TypeOopPtr *t = needleOper->type()->isa_oopptr(); 11014 ciTypeArray* needle_values = t->const_oop()->as_type_array(); // Pointer to live char * 11015 11016 __ string_indexof_1($result$$Register, 11017 $haystack$$Register, $haycnt$$Register, 11018 R0, needle_values->char_at(0), 11019 $tmp1$$Register, $tmp2$$Register); 11020 %} 11021 ins_pipe(pipe_class_compare); 11022 %} 11023 11024 // String_IndexOf for needle of length 1. 11025 // 11026 // Special case requires less registers and emits less instructions. 11027 // 11028 // Assumes register result differs from all input registers. 11029 // 11030 // Preserves registers haystack, haycnt 11031 // Kills registers tmp1, tmp2, needle 11032 // Defines registers result 11033 // 11034 // Use dst register classes if register gets killed, as it is the case for tmp registers! 11035 instruct string_indexOf_imm1(iRegIdst result, iRegPsrc haystack, iRegIsrc haycnt, 11036 rscratch2RegP needle, immI_1 needlecntImm, 11037 iRegIdst tmp1, iRegIdst tmp2, 11038 flagsRegCR0 cr0, flagsRegCR1 cr1) %{ 11039 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecntImm))); 11040 effect(USE_KILL needle, /* TDEF needle, */ TEMP result, 11041 TEMP tmp1, TEMP tmp2); 11042 // Required for EA: check if it is still a type_array. 11043 predicate(SpecialStringIndexOf && n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop() && 11044 n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop()->is_type_array()); 11045 ins_cost(180); 11046 11047 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted. 11048 11049 format %{ "String IndexOf SCL1 $haystack[0..$haycnt], $needle[0..$needlecntImm]" 11050 " -> $result \t// KILL $haycnt, $needle, $tmp1, $tmp2, $cr0, $cr1" %} 11051 ins_encode %{ 11052 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 11053 Node *ndl = in(operand_index($needle)); // The node that defines needle. 11054 ciTypeArray* needle_values = ndl->bottom_type()->is_aryptr()->const_oop()->as_type_array(); 11055 guarantee(needle_values, "sanity"); 11056 if (needle_values != NULL) { 11057 __ string_indexof_1($result$$Register, 11058 $haystack$$Register, $haycnt$$Register, 11059 R0, needle_values->char_at(0), 11060 $tmp1$$Register, $tmp2$$Register); 11061 } else { 11062 __ string_indexof_1($result$$Register, 11063 $haystack$$Register, $haycnt$$Register, 11064 $needle$$Register, 0, 11065 $tmp1$$Register, $tmp2$$Register); 11066 } 11067 %} 11068 ins_pipe(pipe_class_compare); 11069 %} 11070 11071 // String_IndexOf. 11072 // 11073 // Length of needle as immediate. This saves instruction loading constant needle 11074 // length. 11075 // @@@ TODO Specify rules for length < 8 or so, and roll out comparison of needle 11076 // completely or do it in vector instruction. This should save registers for 11077 // needlecnt and needle. 11078 // 11079 // Assumes register result differs from all input registers. 11080 // Overwrites haycnt, needlecnt. 11081 // Use dst register classes if register gets killed, as it is the case for tmp registers! 11082 instruct string_indexOf_imm(iRegIdst result, iRegPsrc haystack, rscratch1RegI haycnt, 11083 iRegPsrc needle, uimmI15 needlecntImm, 11084 iRegIdst tmp1, iRegIdst tmp2, iRegIdst tmp3, iRegIdst tmp4, iRegIdst tmp5, 11085 flagsRegCR0 cr0, flagsRegCR1 cr1, flagsRegCR6 cr6) %{ 11086 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecntImm))); 11087 effect(USE_KILL haycnt, /* better: TDEF haycnt, */ TEMP result, 11088 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5, KILL cr0, KILL cr1, KILL cr6); 11089 // Required for EA: check if it is still a type_array. 11090 predicate(SpecialStringIndexOf && n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop() && 11091 n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop()->is_type_array()); 11092 ins_cost(250); 11093 11094 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted. 11095 11096 format %{ "String IndexOf SCL $haystack[0..$haycnt], $needle[0..$needlecntImm]" 11097 " -> $result \t// KILL $haycnt, $tmp1, $tmp2, $tmp3, $tmp4, $tmp5, $cr0, $cr1" %} 11098 ins_encode %{ 11099 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 11100 Node *ndl = in(operand_index($needle)); // The node that defines needle. 11101 ciTypeArray* needle_values = ndl->bottom_type()->is_aryptr()->const_oop()->as_type_array(); 11102 11103 __ string_indexof($result$$Register, 11104 $haystack$$Register, $haycnt$$Register, 11105 $needle$$Register, needle_values, $tmp5$$Register, $needlecntImm$$constant, 11106 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register); 11107 %} 11108 ins_pipe(pipe_class_compare); 11109 %} 11110 11111 // StrIndexOf node. 11112 // 11113 // Assumes register result differs from all input registers. 11114 // Overwrites haycnt, needlecnt. 11115 // Use dst register classes if register gets killed, as it is the case for tmp registers! 11116 instruct string_indexOf(iRegIdst result, iRegPsrc haystack, rscratch1RegI haycnt, iRegPsrc needle, rscratch2RegI needlecnt, 11117 iRegLdst tmp1, iRegLdst tmp2, iRegLdst tmp3, iRegLdst tmp4, 11118 flagsRegCR0 cr0, flagsRegCR1 cr1, flagsRegCR6 cr6) %{ 11119 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecnt))); 11120 effect(USE_KILL haycnt, USE_KILL needlecnt, /*better: TDEF haycnt, TDEF needlecnt,*/ 11121 TEMP result, 11122 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL cr0, KILL cr1, KILL cr6); 11123 predicate(SpecialStringIndexOf); // See Matcher::match_rule_supported. 11124 ins_cost(300); 11125 11126 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted. 11127 11128 format %{ "String IndexOf $haystack[0..$haycnt], $needle[0..$needlecnt]" 11129 " -> $result \t// KILL $haycnt, $needlecnt, $tmp1, $tmp2, $tmp3, $tmp4, $cr0, $cr1" %} 11130 ins_encode %{ 11131 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 11132 __ string_indexof($result$$Register, 11133 $haystack$$Register, $haycnt$$Register, 11134 $needle$$Register, NULL, $needlecnt$$Register, 0, // needlecnt not constant. 11135 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register); 11136 %} 11137 ins_pipe(pipe_class_compare); 11138 %} 11139 11140 // String equals with immediate. 11141 instruct string_equals_imm(iRegPsrc str1, iRegPsrc str2, uimmI15 cntImm, iRegIdst result, 11142 iRegPdst tmp1, iRegPdst tmp2, 11143 flagsRegCR0 cr0, flagsRegCR6 cr6, regCTR ctr) %{ 11144 match(Set result (StrEquals (Binary str1 str2) cntImm)); 11145 effect(TEMP result, TEMP tmp1, TEMP tmp2, 11146 KILL cr0, KILL cr6, KILL ctr); 11147 predicate(SpecialStringEquals); // See Matcher::match_rule_supported. 11148 ins_cost(250); 11149 11150 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted. 11151 11152 format %{ "String Equals SCL [0..$cntImm]($str1),[0..$cntImm]($str2)" 11153 " -> $result \t// KILL $cr0, $cr6, $ctr, TEMP $result, $tmp1, $tmp2" %} 11154 ins_encode %{ 11155 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 11156 __ char_arrays_equalsImm($str1$$Register, $str2$$Register, $cntImm$$constant, 11157 $result$$Register, $tmp1$$Register, $tmp2$$Register); 11158 %} 11159 ins_pipe(pipe_class_compare); 11160 %} 11161 11162 // String equals. 11163 // Use dst register classes if register gets killed, as it is the case for TEMP operands! 11164 instruct string_equals(iRegPsrc str1, iRegPsrc str2, iRegIsrc cnt, iRegIdst result, 11165 iRegPdst tmp1, iRegPdst tmp2, iRegPdst tmp3, iRegPdst tmp4, iRegPdst tmp5, 11166 flagsRegCR0 cr0, flagsRegCR1 cr1, flagsRegCR6 cr6, regCTR ctr) %{ 11167 match(Set result (StrEquals (Binary str1 str2) cnt)); 11168 effect(TEMP result, TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5, 11169 KILL cr0, KILL cr1, KILL cr6, KILL ctr); 11170 predicate(SpecialStringEquals); // See Matcher::match_rule_supported. 11171 ins_cost(300); 11172 11173 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted. 11174 11175 format %{ "String Equals [0..$cnt]($str1),[0..$cnt]($str2) -> $result" 11176 " \t// KILL $cr0, $cr1, $cr6, $ctr, TEMP $result, $tmp1, $tmp2, $tmp3, $tmp4, $tmp5" %} 11177 ins_encode %{ 11178 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 11179 __ char_arrays_equals($str1$$Register, $str2$$Register, $cnt$$Register, $result$$Register, 11180 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register, $tmp5$$Register); 11181 %} 11182 ins_pipe(pipe_class_compare); 11183 %} 11184 11185 // String compare. 11186 // Char[] pointers are passed in. 11187 // Use dst register classes if register gets killed, as it is the case for TEMP operands! 11188 instruct string_compare(rarg1RegP str1, rarg2RegP str2, rarg3RegI cnt1, rarg4RegI cnt2, iRegIdst result, 11189 iRegPdst tmp, flagsRegCR0 cr0, regCTR ctr) %{ 11190 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2))); 11191 effect(USE_KILL cnt1, USE_KILL cnt2, USE_KILL str1, USE_KILL str2, TEMP result, TEMP tmp, KILL cr0, KILL ctr); 11192 ins_cost(300); 11193 11194 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted. 11195 11196 format %{ "String Compare $str1[0..$cnt1], $str2[0..$cnt2] -> $result" 11197 " \t// TEMP $tmp, $result KILLs $str1, $cnt1, $str2, $cnt2, $cr0, $ctr" %} 11198 ins_encode %{ 11199 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 11200 __ string_compare($str1$$Register, $str2$$Register, $cnt1$$Register, $cnt2$$Register, 11201 $result$$Register, $tmp$$Register); 11202 %} 11203 ins_pipe(pipe_class_compare); 11204 %} 11205 11206 //---------- Min/Max Instructions --------------------------------------------- 11207 11208 instruct minI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ 11209 match(Set dst (MinI src1 src2)); 11210 ins_cost(DEFAULT_COST*6); 11211 11212 expand %{ 11213 iRegLdst src1s; 11214 iRegLdst src2s; 11215 iRegLdst diff; 11216 iRegLdst sm; 11217 iRegLdst doz; // difference or zero 11218 convI2L_reg(src1s, src1); // Ensure proper sign extension. 11219 convI2L_reg(src2s, src2); // Ensure proper sign extension. 11220 subL_reg_reg(diff, src2s, src1s); 11221 // Need to consider >=33 bit result, therefore we need signmaskL. 11222 signmask64L_regL(sm, diff); 11223 andL_reg_reg(doz, diff, sm); // <=0 11224 addI_regL_regL(dst, doz, src1s); 11225 %} 11226 %} 11227 11228 instruct maxI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ 11229 match(Set dst (MaxI src1 src2)); 11230 ins_cost(DEFAULT_COST*6); 11231 11232 expand %{ 11233 iRegLdst src1s; 11234 iRegLdst src2s; 11235 iRegLdst diff; 11236 iRegLdst sm; 11237 iRegLdst doz; // difference or zero 11238 convI2L_reg(src1s, src1); // Ensure proper sign extension. 11239 convI2L_reg(src2s, src2); // Ensure proper sign extension. 11240 subL_reg_reg(diff, src2s, src1s); 11241 // Need to consider >=33 bit result, therefore we need signmaskL. 11242 signmask64L_regL(sm, diff); 11243 andcL_reg_reg(doz, diff, sm); // >=0 11244 addI_regL_regL(dst, doz, src1s); 11245 %} 11246 %} 11247 11248 //---------- Population Count Instructions ------------------------------------ 11249 11250 // Popcnt for Power7. 11251 instruct popCountI(iRegIdst dst, iRegIsrc src) %{ 11252 match(Set dst (PopCountI src)); 11253 predicate(UsePopCountInstruction && VM_Version::has_popcntw()); 11254 ins_cost(DEFAULT_COST); 11255 11256 format %{ "POPCNTW $dst, $src" %} 11257 size(4); 11258 ins_encode %{ 11259 // TODO: PPC port $archOpcode(ppc64Opcode_popcntb); 11260 __ popcntw($dst$$Register, $src$$Register); 11261 %} 11262 ins_pipe(pipe_class_default); 11263 %} 11264 11265 // Popcnt for Power7. 11266 instruct popCountL(iRegIdst dst, iRegLsrc src) %{ 11267 predicate(UsePopCountInstruction && VM_Version::has_popcntw()); 11268 match(Set dst (PopCountL src)); 11269 ins_cost(DEFAULT_COST); 11270 11271 format %{ "POPCNTD $dst, $src" %} 11272 size(4); 11273 ins_encode %{ 11274 // TODO: PPC port $archOpcode(ppc64Opcode_popcntb); 11275 __ popcntd($dst$$Register, $src$$Register); 11276 %} 11277 ins_pipe(pipe_class_default); 11278 %} 11279 11280 instruct countLeadingZerosI(iRegIdst dst, iRegIsrc src) %{ 11281 match(Set dst (CountLeadingZerosI src)); 11282 predicate(UseCountLeadingZerosInstructionsPPC64); // See Matcher::match_rule_supported. 11283 ins_cost(DEFAULT_COST); 11284 11285 format %{ "CNTLZW $dst, $src" %} 11286 size(4); 11287 ins_encode %{ 11288 // TODO: PPC port $archOpcode(ppc64Opcode_cntlzw); 11289 __ cntlzw($dst$$Register, $src$$Register); 11290 %} 11291 ins_pipe(pipe_class_default); 11292 %} 11293 11294 instruct countLeadingZerosL(iRegIdst dst, iRegLsrc src) %{ 11295 match(Set dst (CountLeadingZerosL src)); 11296 predicate(UseCountLeadingZerosInstructionsPPC64); // See Matcher::match_rule_supported. 11297 ins_cost(DEFAULT_COST); 11298 11299 format %{ "CNTLZD $dst, $src" %} 11300 size(4); 11301 ins_encode %{ 11302 // TODO: PPC port $archOpcode(ppc64Opcode_cntlzd); 11303 __ cntlzd($dst$$Register, $src$$Register); 11304 %} 11305 ins_pipe(pipe_class_default); 11306 %} 11307 11308 instruct countLeadingZerosP(iRegIdst dst, iRegPsrc src) %{ 11309 // no match-rule, false predicate 11310 effect(DEF dst, USE src); 11311 predicate(false); 11312 11313 format %{ "CNTLZD $dst, $src" %} 11314 size(4); 11315 ins_encode %{ 11316 // TODO: PPC port $archOpcode(ppc64Opcode_cntlzd); 11317 __ cntlzd($dst$$Register, $src$$Register); 11318 %} 11319 ins_pipe(pipe_class_default); 11320 %} 11321 11322 instruct countTrailingZerosI_Ex(iRegIdst dst, iRegIsrc src) %{ 11323 match(Set dst (CountTrailingZerosI src)); 11324 predicate(UseCountLeadingZerosInstructionsPPC64); 11325 ins_cost(DEFAULT_COST); 11326 11327 expand %{ 11328 immI16 imm1 %{ (int)-1 %} 11329 immI16 imm2 %{ (int)32 %} 11330 immI_minus1 m1 %{ -1 %} 11331 iRegIdst tmpI1; 11332 iRegIdst tmpI2; 11333 iRegIdst tmpI3; 11334 addI_reg_imm16(tmpI1, src, imm1); 11335 andcI_reg_reg(tmpI2, src, m1, tmpI1); 11336 countLeadingZerosI(tmpI3, tmpI2); 11337 subI_imm16_reg(dst, imm2, tmpI3); 11338 %} 11339 %} 11340 11341 instruct countTrailingZerosL_Ex(iRegIdst dst, iRegLsrc src) %{ 11342 match(Set dst (CountTrailingZerosL src)); 11343 predicate(UseCountLeadingZerosInstructionsPPC64); 11344 ins_cost(DEFAULT_COST); 11345 11346 expand %{ 11347 immL16 imm1 %{ (long)-1 %} 11348 immI16 imm2 %{ (int)64 %} 11349 iRegLdst tmpL1; 11350 iRegLdst tmpL2; 11351 iRegIdst tmpL3; 11352 addL_reg_imm16(tmpL1, src, imm1); 11353 andcL_reg_reg(tmpL2, tmpL1, src); 11354 countLeadingZerosL(tmpL3, tmpL2); 11355 subI_imm16_reg(dst, imm2, tmpL3); 11356 %} 11357 %} 11358 11359 // Expand nodes for byte_reverse_int. 11360 instruct insrwi_a(iRegIdst dst, iRegIsrc src, immI16 pos, immI16 shift) %{ 11361 effect(DEF dst, USE src, USE pos, USE shift); 11362 predicate(false); 11363 11364 format %{ "INSRWI $dst, $src, $pos, $shift" %} 11365 size(4); 11366 ins_encode %{ 11367 // TODO: PPC port $archOpcode(ppc64Opcode_rlwimi); 11368 __ insrwi($dst$$Register, $src$$Register, $shift$$constant, $pos$$constant); 11369 %} 11370 ins_pipe(pipe_class_default); 11371 %} 11372 11373 // As insrwi_a, but with USE_DEF. 11374 instruct insrwi(iRegIdst dst, iRegIsrc src, immI16 pos, immI16 shift) %{ 11375 effect(USE_DEF dst, USE src, USE pos, USE shift); 11376 predicate(false); 11377 11378 format %{ "INSRWI $dst, $src, $pos, $shift" %} 11379 size(4); 11380 ins_encode %{ 11381 // TODO: PPC port $archOpcode(ppc64Opcode_rlwimi); 11382 __ insrwi($dst$$Register, $src$$Register, $shift$$constant, $pos$$constant); 11383 %} 11384 ins_pipe(pipe_class_default); 11385 %} 11386 11387 // Just slightly faster than java implementation. 11388 instruct bytes_reverse_int_Ex(iRegIdst dst, iRegIsrc src) %{ 11389 match(Set dst (ReverseBytesI src)); 11390 predicate(UseCountLeadingZerosInstructionsPPC64); 11391 ins_cost(DEFAULT_COST); 11392 11393 expand %{ 11394 immI16 imm24 %{ (int) 24 %} 11395 immI16 imm16 %{ (int) 16 %} 11396 immI16 imm8 %{ (int) 8 %} 11397 immI16 imm4 %{ (int) 4 %} 11398 immI16 imm0 %{ (int) 0 %} 11399 iRegLdst tmpI1; 11400 iRegLdst tmpI2; 11401 iRegLdst tmpI3; 11402 11403 urShiftI_reg_imm(tmpI1, src, imm24); 11404 insrwi_a(dst, tmpI1, imm24, imm8); 11405 urShiftI_reg_imm(tmpI2, src, imm16); 11406 insrwi(dst, tmpI2, imm8, imm16); 11407 urShiftI_reg_imm(tmpI3, src, imm8); 11408 insrwi(dst, tmpI3, imm8, imm8); 11409 insrwi(dst, src, imm0, imm8); 11410 %} 11411 %} 11412 11413 //---------- Replicate Vector Instructions ------------------------------------ 11414 11415 // Insrdi does replicate if src == dst. 11416 instruct repl32(iRegLdst dst) %{ 11417 predicate(false); 11418 effect(USE_DEF dst); 11419 11420 format %{ "INSRDI $dst, #0, $dst, #32 \t// replicate" %} 11421 size(4); 11422 ins_encode %{ 11423 // TODO: PPC port $archOpcode(ppc64Opcode_rldimi); 11424 __ insrdi($dst$$Register, $dst$$Register, 32, 0); 11425 %} 11426 ins_pipe(pipe_class_default); 11427 %} 11428 11429 // Insrdi does replicate if src == dst. 11430 instruct repl48(iRegLdst dst) %{ 11431 predicate(false); 11432 effect(USE_DEF dst); 11433 11434 format %{ "INSRDI $dst, #0, $dst, #48 \t// replicate" %} 11435 size(4); 11436 ins_encode %{ 11437 // TODO: PPC port $archOpcode(ppc64Opcode_rldimi); 11438 __ insrdi($dst$$Register, $dst$$Register, 48, 0); 11439 %} 11440 ins_pipe(pipe_class_default); 11441 %} 11442 11443 // Insrdi does replicate if src == dst. 11444 instruct repl56(iRegLdst dst) %{ 11445 predicate(false); 11446 effect(USE_DEF dst); 11447 11448 format %{ "INSRDI $dst, #0, $dst, #56 \t// replicate" %} 11449 size(4); 11450 ins_encode %{ 11451 // TODO: PPC port $archOpcode(ppc64Opcode_rldimi); 11452 __ insrdi($dst$$Register, $dst$$Register, 56, 0); 11453 %} 11454 ins_pipe(pipe_class_default); 11455 %} 11456 11457 instruct repl8B_reg_Ex(iRegLdst dst, iRegIsrc src) %{ 11458 match(Set dst (ReplicateB src)); 11459 predicate(n->as_Vector()->length() == 8); 11460 expand %{ 11461 moveReg(dst, src); 11462 repl56(dst); 11463 repl48(dst); 11464 repl32(dst); 11465 %} 11466 %} 11467 11468 instruct repl8B_immI0(iRegLdst dst, immI_0 zero) %{ 11469 match(Set dst (ReplicateB zero)); 11470 predicate(n->as_Vector()->length() == 8); 11471 format %{ "LI $dst, #0 \t// replicate8B" %} 11472 size(4); 11473 ins_encode %{ 11474 // TODO: PPC port $archOpcode(ppc64Opcode_addi); 11475 __ li($dst$$Register, (int)((short)($zero$$constant & 0xFFFF))); 11476 %} 11477 ins_pipe(pipe_class_default); 11478 %} 11479 11480 instruct repl8B_immIminus1(iRegLdst dst, immI_minus1 src) %{ 11481 match(Set dst (ReplicateB src)); 11482 predicate(n->as_Vector()->length() == 8); 11483 format %{ "LI $dst, #-1 \t// replicate8B" %} 11484 size(4); 11485 ins_encode %{ 11486 // TODO: PPC port $archOpcode(ppc64Opcode_addi); 11487 __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF))); 11488 %} 11489 ins_pipe(pipe_class_default); 11490 %} 11491 11492 instruct repl4S_reg_Ex(iRegLdst dst, iRegIsrc src) %{ 11493 match(Set dst (ReplicateS src)); 11494 predicate(n->as_Vector()->length() == 4); 11495 expand %{ 11496 moveReg(dst, src); 11497 repl48(dst); 11498 repl32(dst); 11499 %} 11500 %} 11501 11502 instruct repl4S_immI0(iRegLdst dst, immI_0 zero) %{ 11503 match(Set dst (ReplicateS zero)); 11504 predicate(n->as_Vector()->length() == 4); 11505 format %{ "LI $dst, #0 \t// replicate4C" %} 11506 size(4); 11507 ins_encode %{ 11508 // TODO: PPC port $archOpcode(ppc64Opcode_addi); 11509 __ li($dst$$Register, (int)((short)($zero$$constant & 0xFFFF))); 11510 %} 11511 ins_pipe(pipe_class_default); 11512 %} 11513 11514 instruct repl4S_immIminus1(iRegLdst dst, immI_minus1 src) %{ 11515 match(Set dst (ReplicateS src)); 11516 predicate(n->as_Vector()->length() == 4); 11517 format %{ "LI $dst, -1 \t// replicate4C" %} 11518 size(4); 11519 ins_encode %{ 11520 // TODO: PPC port $archOpcode(ppc64Opcode_addi); 11521 __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF))); 11522 %} 11523 ins_pipe(pipe_class_default); 11524 %} 11525 11526 instruct repl2I_reg_Ex(iRegLdst dst, iRegIsrc src) %{ 11527 match(Set dst (ReplicateI src)); 11528 predicate(n->as_Vector()->length() == 2); 11529 ins_cost(2 * DEFAULT_COST); 11530 expand %{ 11531 moveReg(dst, src); 11532 repl32(dst); 11533 %} 11534 %} 11535 11536 instruct repl2I_immI0(iRegLdst dst, immI_0 zero) %{ 11537 match(Set dst (ReplicateI zero)); 11538 predicate(n->as_Vector()->length() == 2); 11539 format %{ "LI $dst, #0 \t// replicate4C" %} 11540 size(4); 11541 ins_encode %{ 11542 // TODO: PPC port $archOpcode(ppc64Opcode_addi); 11543 __ li($dst$$Register, (int)((short)($zero$$constant & 0xFFFF))); 11544 %} 11545 ins_pipe(pipe_class_default); 11546 %} 11547 11548 instruct repl2I_immIminus1(iRegLdst dst, immI_minus1 src) %{ 11549 match(Set dst (ReplicateI src)); 11550 predicate(n->as_Vector()->length() == 2); 11551 format %{ "LI $dst, -1 \t// replicate4C" %} 11552 size(4); 11553 ins_encode %{ 11554 // TODO: PPC port $archOpcode(ppc64Opcode_addi); 11555 __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF))); 11556 %} 11557 ins_pipe(pipe_class_default); 11558 %} 11559 11560 // Move float to int register via stack, replicate. 11561 instruct repl2F_reg_Ex(iRegLdst dst, regF src) %{ 11562 match(Set dst (ReplicateF src)); 11563 predicate(n->as_Vector()->length() == 2); 11564 ins_cost(2 * MEMORY_REF_COST + DEFAULT_COST); 11565 expand %{ 11566 stackSlotL tmpS; 11567 iRegIdst tmpI; 11568 moveF2I_reg_stack(tmpS, src); // Move float to stack. 11569 moveF2I_stack_reg(tmpI, tmpS); // Move stack to int reg. 11570 moveReg(dst, tmpI); // Move int to long reg. 11571 repl32(dst); // Replicate bitpattern. 11572 %} 11573 %} 11574 11575 // Replicate scalar constant to packed float values in Double register 11576 instruct repl2F_immF_Ex(iRegLdst dst, immF src) %{ 11577 match(Set dst (ReplicateF src)); 11578 predicate(n->as_Vector()->length() == 2); 11579 ins_cost(5 * DEFAULT_COST); 11580 11581 format %{ "LD $dst, offset, $constanttablebase\t// load replicated float $src $src from table, postalloc expanded" %} 11582 postalloc_expand( postalloc_expand_load_replF_constant(dst, src, constanttablebase) ); 11583 %} 11584 11585 // Replicate scalar zero constant to packed float values in Double register 11586 instruct repl2F_immF0(iRegLdst dst, immF_0 zero) %{ 11587 match(Set dst (ReplicateF zero)); 11588 predicate(n->as_Vector()->length() == 2); 11589 11590 format %{ "LI $dst, #0 \t// replicate2F" %} 11591 ins_encode %{ 11592 // TODO: PPC port $archOpcode(ppc64Opcode_addi); 11593 __ li($dst$$Register, 0x0); 11594 %} 11595 ins_pipe(pipe_class_default); 11596 %} 11597 11598 // ============================================================================ 11599 // Safepoint Instruction 11600 11601 instruct safePoint_poll(iRegPdst poll) %{ 11602 match(SafePoint poll); 11603 predicate(LoadPollAddressFromThread); 11604 11605 // It caused problems to add the effect that r0 is killed, but this 11606 // effect no longer needs to be mentioned, since r0 is not contained 11607 // in a reg_class. 11608 11609 format %{ "LD R0, #0, $poll \t// Safepoint poll for GC" %} 11610 size(4); 11611 ins_encode( enc_poll(0x0, poll) ); 11612 ins_pipe(pipe_class_default); 11613 %} 11614 11615 // Safepoint without per-thread support. Load address of page to poll 11616 // as constant. 11617 // Rscratch2RegP is R12. 11618 // LoadConPollAddr node is added in pd_post_matching_hook(). It must be 11619 // a seperate node so that the oop map is at the right location. 11620 instruct safePoint_poll_conPollAddr(rscratch2RegP poll) %{ 11621 match(SafePoint poll); 11622 predicate(!LoadPollAddressFromThread); 11623 11624 // It caused problems to add the effect that r0 is killed, but this 11625 // effect no longer needs to be mentioned, since r0 is not contained 11626 // in a reg_class. 11627 11628 format %{ "LD R0, #0, R12 \t// Safepoint poll for GC" %} 11629 ins_encode( enc_poll(0x0, poll) ); 11630 ins_pipe(pipe_class_default); 11631 %} 11632 11633 // ============================================================================ 11634 // Call Instructions 11635 11636 // Call Java Static Instruction 11637 11638 // Schedulable version of call static node. 11639 instruct CallStaticJavaDirect(method meth) %{ 11640 match(CallStaticJava); 11641 effect(USE meth); 11642 predicate(!((CallStaticJavaNode*)n)->is_method_handle_invoke()); 11643 ins_cost(CALL_COST); 11644 11645 ins_num_consts(3 /* up to 3 patchable constants: inline cache, 2 call targets. */); 11646 11647 format %{ "CALL,static $meth \t// ==> " %} 11648 size(4); 11649 ins_encode( enc_java_static_call(meth) ); 11650 ins_pipe(pipe_class_call); 11651 %} 11652 11653 // Schedulable version of call static node. 11654 instruct CallStaticJavaDirectHandle(method meth) %{ 11655 match(CallStaticJava); 11656 effect(USE meth); 11657 predicate(((CallStaticJavaNode*)n)->is_method_handle_invoke()); 11658 ins_cost(CALL_COST); 11659 11660 ins_num_consts(3 /* up to 3 patchable constants: inline cache, 2 call targets. */); 11661 11662 format %{ "CALL,static $meth \t// ==> " %} 11663 ins_encode( enc_java_handle_call(meth) ); 11664 ins_pipe(pipe_class_call); 11665 %} 11666 11667 // Call Java Dynamic Instruction 11668 11669 // Used by postalloc expand of CallDynamicJavaDirectSchedEx (actual call). 11670 // Loading of IC was postalloc expanded. The nodes loading the IC are reachable 11671 // via fields ins_field_load_ic_hi_node and ins_field_load_ic_node. 11672 // The call destination must still be placed in the constant pool. 11673 instruct CallDynamicJavaDirectSched(method meth) %{ 11674 match(CallDynamicJava); // To get all the data fields we need ... 11675 effect(USE meth); 11676 predicate(false); // ... but never match. 11677 11678 ins_field_load_ic_hi_node(loadConL_hiNode*); 11679 ins_field_load_ic_node(loadConLNode*); 11680 ins_num_consts(1 /* 1 patchable constant: call destination */); 11681 11682 format %{ "BL \t// dynamic $meth ==> " %} 11683 size(4); 11684 ins_encode( enc_java_dynamic_call_sched(meth) ); 11685 ins_pipe(pipe_class_call); 11686 %} 11687 11688 // Schedulable (i.e. postalloc expanded) version of call dynamic java. 11689 // We use postalloc expanded calls if we use inline caches 11690 // and do not update method data. 11691 // 11692 // This instruction has two constants: inline cache (IC) and call destination. 11693 // Loading the inline cache will be postalloc expanded, thus leaving a call with 11694 // one constant. 11695 instruct CallDynamicJavaDirectSched_Ex(method meth) %{ 11696 match(CallDynamicJava); 11697 effect(USE meth); 11698 predicate(UseInlineCaches); 11699 ins_cost(CALL_COST); 11700 11701 ins_num_consts(2 /* 2 patchable constants: inline cache, call destination. */); 11702 11703 format %{ "CALL,dynamic $meth \t// postalloc expanded" %} 11704 postalloc_expand( postalloc_expand_java_dynamic_call_sched(meth, constanttablebase) ); 11705 %} 11706 11707 // Compound version of call dynamic java 11708 // We use postalloc expanded calls if we use inline caches 11709 // and do not update method data. 11710 instruct CallDynamicJavaDirect(method meth) %{ 11711 match(CallDynamicJava); 11712 effect(USE meth); 11713 predicate(!UseInlineCaches); 11714 ins_cost(CALL_COST); 11715 11716 // Enc_java_to_runtime_call needs up to 4 constants (method data oop). 11717 ins_num_consts(4); 11718 11719 format %{ "CALL,dynamic $meth \t// ==> " %} 11720 ins_encode( enc_java_dynamic_call(meth, constanttablebase) ); 11721 ins_pipe(pipe_class_call); 11722 %} 11723 11724 // Call Runtime Instruction 11725 11726 instruct CallRuntimeDirect(method meth) %{ 11727 match(CallRuntime); 11728 effect(USE meth); 11729 ins_cost(CALL_COST); 11730 11731 // Enc_java_to_runtime_call needs up to 3 constants: call target, 11732 // env for callee, C-toc. 11733 ins_num_consts(3); 11734 11735 format %{ "CALL,runtime" %} 11736 ins_encode( enc_java_to_runtime_call(meth) ); 11737 ins_pipe(pipe_class_call); 11738 %} 11739 11740 // Call Leaf 11741 11742 // Used by postalloc expand of CallLeafDirect_Ex (mtctr). 11743 instruct CallLeafDirect_mtctr(iRegLdst dst, iRegLsrc src) %{ 11744 effect(DEF dst, USE src); 11745 11746 ins_num_consts(1); 11747 11748 format %{ "MTCTR $src" %} 11749 size(4); 11750 ins_encode( enc_leaf_call_mtctr(src) ); 11751 ins_pipe(pipe_class_default); 11752 %} 11753 11754 // Used by postalloc expand of CallLeafDirect_Ex (actual call). 11755 instruct CallLeafDirect(method meth) %{ 11756 match(CallLeaf); // To get the data all the data fields we need ... 11757 effect(USE meth); 11758 predicate(false); // but never match. 11759 11760 format %{ "BCTRL \t// leaf call $meth ==> " %} 11761 size(4); 11762 ins_encode %{ 11763 // TODO: PPC port $archOpcode(ppc64Opcode_bctrl); 11764 __ bctrl(); 11765 %} 11766 ins_pipe(pipe_class_call); 11767 %} 11768 11769 // postalloc expand of CallLeafDirect. 11770 // Load adress to call from TOC, then bl to it. 11771 instruct CallLeafDirect_Ex(method meth) %{ 11772 match(CallLeaf); 11773 effect(USE meth); 11774 ins_cost(CALL_COST); 11775 11776 // Postalloc_expand_java_to_runtime_call needs up to 3 constants: call target, 11777 // env for callee, C-toc. 11778 ins_num_consts(3); 11779 11780 format %{ "CALL,runtime leaf $meth \t// postalloc expanded" %} 11781 postalloc_expand( postalloc_expand_java_to_runtime_call(meth, constanttablebase) ); 11782 %} 11783 11784 // Call runtime without safepoint - same as CallLeaf. 11785 // postalloc expand of CallLeafNoFPDirect. 11786 // Load adress to call from TOC, then bl to it. 11787 instruct CallLeafNoFPDirect_Ex(method meth) %{ 11788 match(CallLeafNoFP); 11789 effect(USE meth); 11790 ins_cost(CALL_COST); 11791 11792 // Enc_java_to_runtime_call needs up to 3 constants: call target, 11793 // env for callee, C-toc. 11794 ins_num_consts(3); 11795 11796 format %{ "CALL,runtime leaf nofp $meth \t// postalloc expanded" %} 11797 postalloc_expand( postalloc_expand_java_to_runtime_call(meth, constanttablebase) ); 11798 %} 11799 11800 // Tail Call; Jump from runtime stub to Java code. 11801 // Also known as an 'interprocedural jump'. 11802 // Target of jump will eventually return to caller. 11803 // TailJump below removes the return address. 11804 instruct TailCalljmpInd(iRegPdstNoScratch jump_target, inline_cache_regP method_oop) %{ 11805 match(TailCall jump_target method_oop); 11806 ins_cost(CALL_COST); 11807 11808 format %{ "MTCTR $jump_target \t// $method_oop holds method oop\n\t" 11809 "BCTR \t// tail call" %} 11810 size(8); 11811 ins_encode %{ 11812 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 11813 __ mtctr($jump_target$$Register); 11814 __ bctr(); 11815 %} 11816 ins_pipe(pipe_class_call); 11817 %} 11818 11819 // Return Instruction 11820 instruct Ret() %{ 11821 match(Return); 11822 format %{ "BLR \t// branch to link register" %} 11823 size(4); 11824 ins_encode %{ 11825 // TODO: PPC port $archOpcode(ppc64Opcode_blr); 11826 // LR is restored in MachEpilogNode. Just do the RET here. 11827 __ blr(); 11828 %} 11829 ins_pipe(pipe_class_default); 11830 %} 11831 11832 // Tail Jump; remove the return address; jump to target. 11833 // TailCall above leaves the return address around. 11834 // TailJump is used in only one place, the rethrow_Java stub (fancy_jump=2). 11835 // ex_oop (Exception Oop) is needed in %o0 at the jump. As there would be a 11836 // "restore" before this instruction (in Epilogue), we need to materialize it 11837 // in %i0. 11838 instruct tailjmpInd(iRegPdstNoScratch jump_target, rarg1RegP ex_oop) %{ 11839 match(TailJump jump_target ex_oop); 11840 ins_cost(CALL_COST); 11841 11842 format %{ "LD R4_ARG2 = LR\n\t" 11843 "MTCTR $jump_target\n\t" 11844 "BCTR \t// TailJump, exception oop: $ex_oop" %} 11845 size(12); 11846 ins_encode %{ 11847 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 11848 __ ld(R4_ARG2/* issuing pc */, _abi(lr), R1_SP); 11849 __ mtctr($jump_target$$Register); 11850 __ bctr(); 11851 %} 11852 ins_pipe(pipe_class_call); 11853 %} 11854 11855 // Create exception oop: created by stack-crawling runtime code. 11856 // Created exception is now available to this handler, and is setup 11857 // just prior to jumping to this handler. No code emitted. 11858 instruct CreateException(rarg1RegP ex_oop) %{ 11859 match(Set ex_oop (CreateEx)); 11860 ins_cost(0); 11861 11862 format %{ " -- \t// exception oop; no code emitted" %} 11863 size(0); 11864 ins_encode( /*empty*/ ); 11865 ins_pipe(pipe_class_default); 11866 %} 11867 11868 // Rethrow exception: The exception oop will come in the first 11869 // argument position. Then JUMP (not call) to the rethrow stub code. 11870 instruct RethrowException() %{ 11871 match(Rethrow); 11872 ins_cost(CALL_COST); 11873 11874 format %{ "Jmp rethrow_stub" %} 11875 ins_encode %{ 11876 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 11877 cbuf.set_insts_mark(); 11878 __ b64_patchable((address)OptoRuntime::rethrow_stub(), relocInfo::runtime_call_type); 11879 %} 11880 ins_pipe(pipe_class_call); 11881 %} 11882 11883 // Die now. 11884 instruct ShouldNotReachHere() %{ 11885 match(Halt); 11886 ins_cost(CALL_COST); 11887 11888 format %{ "ShouldNotReachHere" %} 11889 size(4); 11890 ins_encode %{ 11891 // TODO: PPC port $archOpcode(ppc64Opcode_tdi); 11892 __ trap_should_not_reach_here(); 11893 %} 11894 ins_pipe(pipe_class_default); 11895 %} 11896 11897 // This name is KNOWN by the ADLC and cannot be changed. The ADLC 11898 // forces a 'TypeRawPtr::BOTTOM' output type for this guy. 11899 // Get a DEF on threadRegP, no costs, no encoding, use 11900 // 'ins_should_rematerialize(true)' to avoid spilling. 11901 instruct tlsLoadP(threadRegP dst) %{ 11902 match(Set dst (ThreadLocal)); 11903 ins_cost(0); 11904 11905 ins_should_rematerialize(true); 11906 11907 format %{ " -- \t// $dst=Thread::current(), empty" %} 11908 size(0); 11909 ins_encode( /*empty*/ ); 11910 ins_pipe(pipe_class_empty); 11911 %} 11912 11913 //---Some PPC specific nodes--------------------------------------------------- 11914 11915 // Stop a group. 11916 instruct endGroup() %{ 11917 ins_cost(0); 11918 11919 ins_is_nop(true); 11920 11921 format %{ "End Bundle (ori r1, r1, 0)" %} 11922 size(4); 11923 ins_encode %{ 11924 // TODO: PPC port $archOpcode(ppc64Opcode_endgroup); 11925 __ endgroup(); 11926 %} 11927 ins_pipe(pipe_class_default); 11928 %} 11929 11930 // Nop instructions 11931 11932 instruct fxNop() %{ 11933 ins_cost(0); 11934 11935 ins_is_nop(true); 11936 11937 format %{ "fxNop" %} 11938 size(4); 11939 ins_encode %{ 11940 // TODO: PPC port $archOpcode(ppc64Opcode_fmr); 11941 __ nop(); 11942 %} 11943 ins_pipe(pipe_class_default); 11944 %} 11945 11946 instruct fpNop0() %{ 11947 ins_cost(0); 11948 11949 ins_is_nop(true); 11950 11951 format %{ "fpNop0" %} 11952 size(4); 11953 ins_encode %{ 11954 // TODO: PPC port $archOpcode(ppc64Opcode_fmr); 11955 __ fpnop0(); 11956 %} 11957 ins_pipe(pipe_class_default); 11958 %} 11959 11960 instruct fpNop1() %{ 11961 ins_cost(0); 11962 11963 ins_is_nop(true); 11964 11965 format %{ "fpNop1" %} 11966 size(4); 11967 ins_encode %{ 11968 // TODO: PPC port $archOpcode(ppc64Opcode_fmr); 11969 __ fpnop1(); 11970 %} 11971 ins_pipe(pipe_class_default); 11972 %} 11973 11974 instruct brNop0() %{ 11975 ins_cost(0); 11976 size(4); 11977 format %{ "brNop0" %} 11978 ins_encode %{ 11979 // TODO: PPC port $archOpcode(ppc64Opcode_mcrf); 11980 __ brnop0(); 11981 %} 11982 ins_is_nop(true); 11983 ins_pipe(pipe_class_default); 11984 %} 11985 11986 instruct brNop1() %{ 11987 ins_cost(0); 11988 11989 ins_is_nop(true); 11990 11991 format %{ "brNop1" %} 11992 size(4); 11993 ins_encode %{ 11994 // TODO: PPC port $archOpcode(ppc64Opcode_mcrf); 11995 __ brnop1(); 11996 %} 11997 ins_pipe(pipe_class_default); 11998 %} 11999 12000 instruct brNop2() %{ 12001 ins_cost(0); 12002 12003 ins_is_nop(true); 12004 12005 format %{ "brNop2" %} 12006 size(4); 12007 ins_encode %{ 12008 // TODO: PPC port $archOpcode(ppc64Opcode_mcrf); 12009 __ brnop2(); 12010 %} 12011 ins_pipe(pipe_class_default); 12012 %} 12013 12014 //----------PEEPHOLE RULES----------------------------------------------------- 12015 // These must follow all instruction definitions as they use the names 12016 // defined in the instructions definitions. 12017 // 12018 // peepmatch ( root_instr_name [preceeding_instruction]* ); 12019 // 12020 // peepconstraint %{ 12021 // (instruction_number.operand_name relational_op instruction_number.operand_name 12022 // [, ...] ); 12023 // // instruction numbers are zero-based using left to right order in peepmatch 12024 // 12025 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) ); 12026 // // provide an instruction_number.operand_name for each operand that appears 12027 // // in the replacement instruction's match rule 12028 // 12029 // ---------VM FLAGS--------------------------------------------------------- 12030 // 12031 // All peephole optimizations can be turned off using -XX:-OptoPeephole 12032 // 12033 // Each peephole rule is given an identifying number starting with zero and 12034 // increasing by one in the order seen by the parser. An individual peephole 12035 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=# 12036 // on the command-line. 12037 // 12038 // ---------CURRENT LIMITATIONS---------------------------------------------- 12039 // 12040 // Only match adjacent instructions in same basic block 12041 // Only equality constraints 12042 // Only constraints between operands, not (0.dest_reg == EAX_enc) 12043 // Only one replacement instruction 12044 // 12045 // ---------EXAMPLE---------------------------------------------------------- 12046 // 12047 // // pertinent parts of existing instructions in architecture description 12048 // instruct movI(eRegI dst, eRegI src) %{ 12049 // match(Set dst (CopyI src)); 12050 // %} 12051 // 12052 // instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{ 12053 // match(Set dst (AddI dst src)); 12054 // effect(KILL cr); 12055 // %} 12056 // 12057 // // Change (inc mov) to lea 12058 // peephole %{ 12059 // // increment preceeded by register-register move 12060 // peepmatch ( incI_eReg movI ); 12061 // // require that the destination register of the increment 12062 // // match the destination register of the move 12063 // peepconstraint ( 0.dst == 1.dst ); 12064 // // construct a replacement instruction that sets 12065 // // the destination to ( move's source register + one ) 12066 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) ); 12067 // %} 12068 // 12069 // Implementation no longer uses movX instructions since 12070 // machine-independent system no longer uses CopyX nodes. 12071 // 12072 // peephole %{ 12073 // peepmatch ( incI_eReg movI ); 12074 // peepconstraint ( 0.dst == 1.dst ); 12075 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) ); 12076 // %} 12077 // 12078 // peephole %{ 12079 // peepmatch ( decI_eReg movI ); 12080 // peepconstraint ( 0.dst == 1.dst ); 12081 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) ); 12082 // %} 12083 // 12084 // peephole %{ 12085 // peepmatch ( addI_eReg_imm movI ); 12086 // peepconstraint ( 0.dst == 1.dst ); 12087 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) ); 12088 // %} 12089 // 12090 // peephole %{ 12091 // peepmatch ( addP_eReg_imm movP ); 12092 // peepconstraint ( 0.dst == 1.dst ); 12093 // peepreplace ( leaP_eReg_immI( 0.dst 1.src 0.src ) ); 12094 // %} 12095 12096 // // Change load of spilled value to only a spill 12097 // instruct storeI(memory mem, eRegI src) %{ 12098 // match(Set mem (StoreI mem src)); 12099 // %} 12100 // 12101 // instruct loadI(eRegI dst, memory mem) %{ 12102 // match(Set dst (LoadI mem)); 12103 // %} 12104 // 12105 peephole %{ 12106 peepmatch ( loadI storeI ); 12107 peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem ); 12108 peepreplace ( storeI( 1.mem 1.mem 1.src ) ); 12109 %} 12110 12111 peephole %{ 12112 peepmatch ( loadL storeL ); 12113 peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem ); 12114 peepreplace ( storeL( 1.mem 1.mem 1.src ) ); 12115 %} 12116 12117 peephole %{ 12118 peepmatch ( loadP storeP ); 12119 peepconstraint ( 1.src == 0.dst, 1.dst == 0.mem ); 12120 peepreplace ( storeP( 1.dst 1.dst 1.src ) ); 12121 %} 12122 12123 //----------SMARTSPILL RULES--------------------------------------------------- 12124 // These must follow all instruction definitions as they use the names 12125 // defined in the instructions definitions.