1 //
2 // Copyright (c) 2011, 2014, Oracle and/or its affiliates. All rights reserved.
3 // Copyright 2012, 2014 SAP AG. All rights reserved.
4 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 //
6 // This code is free software; you can redistribute it and/or modify it
7 // under the terms of the GNU General Public License version 2 only, as
8 // published by the Free Software Foundation.
9 //
10 // This code is distributed in the hope that it will be useful, but WITHOUT
11 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 // version 2 for more details (a copy is included in the LICENSE file that
14 // accompanied this code).
15 //
16 // You should have received a copy of the GNU General Public License version
17 // 2 along with this work; if not, write to the Free Software Foundation,
18 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 //
20 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 // or visit www.oracle.com if you need additional information or have any
22 // questions.
23 //
24 //
25
26 //
27 // PPC64 Architecture Description File
28 //
29
30 //----------REGISTER DEFINITION BLOCK------------------------------------------
31 // This information is used by the matcher and the register allocator to
32 // describe individual registers and classes of registers within the target
33 // architecture.
34 register %{
35 //----------Architecture Description Register Definitions----------------------
36 // General Registers
37 // "reg_def" name (register save type, C convention save type,
38 // ideal register type, encoding);
39 //
40 // Register Save Types:
41 //
42 // NS = No-Save: The register allocator assumes that these registers
43 // can be used without saving upon entry to the method, &
44 // that they do not need to be saved at call sites.
45 //
46 // SOC = Save-On-Call: The register allocator assumes that these registers
47 // can be used without saving upon entry to the method,
48 // but that they must be saved at call sites.
49 // These are called "volatiles" on ppc.
50 //
51 // SOE = Save-On-Entry: The register allocator assumes that these registers
52 // must be saved before using them upon entry to the
53 // method, but they do not need to be saved at call
54 // sites.
55 // These are called "nonvolatiles" on ppc.
56 //
57 // AS = Always-Save: The register allocator assumes that these registers
58 // must be saved before using them upon entry to the
59 // method, & that they must be saved at call sites.
60 //
61 // Ideal Register Type is used to determine how to save & restore a
62 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
63 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
64 //
65 // The encoding number is the actual bit-pattern placed into the opcodes.
66 //
67 // PPC64 register definitions, based on the 64-bit PowerPC ELF ABI
68 // Supplement Version 1.7 as of 2003-10-29.
69 //
70 // For each 64-bit register we must define two registers: the register
71 // itself, e.g. R3, and a corresponding virtual other (32-bit-)'half',
72 // e.g. R3_H, which is needed by the allocator, but is not used
73 // for stores, loads, etc.
74
75 // ----------------------------
76 // Integer/Long Registers
77 // ----------------------------
78
79 // PPC64 has 32 64-bit integer registers.
80
81 // types: v = volatile, nv = non-volatile, s = system
82 reg_def R0 ( SOC, SOC, Op_RegI, 0, R0->as_VMReg() ); // v used in prologs
83 reg_def R0_H ( SOC, SOC, Op_RegI, 99, R0->as_VMReg()->next() );
84 reg_def R1 ( NS, NS, Op_RegI, 1, R1->as_VMReg() ); // s SP
85 reg_def R1_H ( NS, NS, Op_RegI, 99, R1->as_VMReg()->next() );
86 reg_def R2 ( SOC, SOC, Op_RegI, 2, R2->as_VMReg() ); // v TOC
87 reg_def R2_H ( SOC, SOC, Op_RegI, 99, R2->as_VMReg()->next() );
88 reg_def R3 ( SOC, SOC, Op_RegI, 3, R3->as_VMReg() ); // v iarg1 & iret
89 reg_def R3_H ( SOC, SOC, Op_RegI, 99, R3->as_VMReg()->next() );
90 reg_def R4 ( SOC, SOC, Op_RegI, 4, R4->as_VMReg() ); // iarg2
91 reg_def R4_H ( SOC, SOC, Op_RegI, 99, R4->as_VMReg()->next() );
92 reg_def R5 ( SOC, SOC, Op_RegI, 5, R5->as_VMReg() ); // v iarg3
93 reg_def R5_H ( SOC, SOC, Op_RegI, 99, R5->as_VMReg()->next() );
94 reg_def R6 ( SOC, SOC, Op_RegI, 6, R6->as_VMReg() ); // v iarg4
95 reg_def R6_H ( SOC, SOC, Op_RegI, 99, R6->as_VMReg()->next() );
96 reg_def R7 ( SOC, SOC, Op_RegI, 7, R7->as_VMReg() ); // v iarg5
97 reg_def R7_H ( SOC, SOC, Op_RegI, 99, R7->as_VMReg()->next() );
98 reg_def R8 ( SOC, SOC, Op_RegI, 8, R8->as_VMReg() ); // v iarg6
99 reg_def R8_H ( SOC, SOC, Op_RegI, 99, R8->as_VMReg()->next() );
100 reg_def R9 ( SOC, SOC, Op_RegI, 9, R9->as_VMReg() ); // v iarg7
101 reg_def R9_H ( SOC, SOC, Op_RegI, 99, R9->as_VMReg()->next() );
102 reg_def R10 ( SOC, SOC, Op_RegI, 10, R10->as_VMReg() ); // v iarg8
103 reg_def R10_H( SOC, SOC, Op_RegI, 99, R10->as_VMReg()->next());
104 reg_def R11 ( SOC, SOC, Op_RegI, 11, R11->as_VMReg() ); // v ENV / scratch
105 reg_def R11_H( SOC, SOC, Op_RegI, 99, R11->as_VMReg()->next());
106 reg_def R12 ( SOC, SOC, Op_RegI, 12, R12->as_VMReg() ); // v scratch
107 reg_def R12_H( SOC, SOC, Op_RegI, 99, R12->as_VMReg()->next());
108 reg_def R13 ( NS, NS, Op_RegI, 13, R13->as_VMReg() ); // s system thread id
109 reg_def R13_H( NS, NS, Op_RegI, 99, R13->as_VMReg()->next());
110 reg_def R14 ( SOC, SOE, Op_RegI, 14, R14->as_VMReg() ); // nv
111 reg_def R14_H( SOC, SOE, Op_RegI, 99, R14->as_VMReg()->next());
112 reg_def R15 ( SOC, SOE, Op_RegI, 15, R15->as_VMReg() ); // nv
113 reg_def R15_H( SOC, SOE, Op_RegI, 99, R15->as_VMReg()->next());
114 reg_def R16 ( SOC, SOE, Op_RegI, 16, R16->as_VMReg() ); // nv
115 reg_def R16_H( SOC, SOE, Op_RegI, 99, R16->as_VMReg()->next());
116 reg_def R17 ( SOC, SOE, Op_RegI, 17, R17->as_VMReg() ); // nv
117 reg_def R17_H( SOC, SOE, Op_RegI, 99, R17->as_VMReg()->next());
118 reg_def R18 ( SOC, SOE, Op_RegI, 18, R18->as_VMReg() ); // nv
119 reg_def R18_H( SOC, SOE, Op_RegI, 99, R18->as_VMReg()->next());
120 reg_def R19 ( SOC, SOE, Op_RegI, 19, R19->as_VMReg() ); // nv
121 reg_def R19_H( SOC, SOE, Op_RegI, 99, R19->as_VMReg()->next());
122 reg_def R20 ( SOC, SOE, Op_RegI, 20, R20->as_VMReg() ); // nv
123 reg_def R20_H( SOC, SOE, Op_RegI, 99, R20->as_VMReg()->next());
124 reg_def R21 ( SOC, SOE, Op_RegI, 21, R21->as_VMReg() ); // nv
125 reg_def R21_H( SOC, SOE, Op_RegI, 99, R21->as_VMReg()->next());
126 reg_def R22 ( SOC, SOE, Op_RegI, 22, R22->as_VMReg() ); // nv
127 reg_def R22_H( SOC, SOE, Op_RegI, 99, R22->as_VMReg()->next());
128 reg_def R23 ( SOC, SOE, Op_RegI, 23, R23->as_VMReg() ); // nv
129 reg_def R23_H( SOC, SOE, Op_RegI, 99, R23->as_VMReg()->next());
130 reg_def R24 ( SOC, SOE, Op_RegI, 24, R24->as_VMReg() ); // nv
131 reg_def R24_H( SOC, SOE, Op_RegI, 99, R24->as_VMReg()->next());
132 reg_def R25 ( SOC, SOE, Op_RegI, 25, R25->as_VMReg() ); // nv
133 reg_def R25_H( SOC, SOE, Op_RegI, 99, R25->as_VMReg()->next());
134 reg_def R26 ( SOC, SOE, Op_RegI, 26, R26->as_VMReg() ); // nv
135 reg_def R26_H( SOC, SOE, Op_RegI, 99, R26->as_VMReg()->next());
136 reg_def R27 ( SOC, SOE, Op_RegI, 27, R27->as_VMReg() ); // nv
137 reg_def R27_H( SOC, SOE, Op_RegI, 99, R27->as_VMReg()->next());
138 reg_def R28 ( SOC, SOE, Op_RegI, 28, R28->as_VMReg() ); // nv
139 reg_def R28_H( SOC, SOE, Op_RegI, 99, R28->as_VMReg()->next());
140 reg_def R29 ( SOC, SOE, Op_RegI, 29, R29->as_VMReg() ); // nv
141 reg_def R29_H( SOC, SOE, Op_RegI, 99, R29->as_VMReg()->next());
142 reg_def R30 ( SOC, SOE, Op_RegI, 30, R30->as_VMReg() ); // nv
143 reg_def R30_H( SOC, SOE, Op_RegI, 99, R30->as_VMReg()->next());
144 reg_def R31 ( SOC, SOE, Op_RegI, 31, R31->as_VMReg() ); // nv
145 reg_def R31_H( SOC, SOE, Op_RegI, 99, R31->as_VMReg()->next());
146
147
148 // ----------------------------
149 // Float/Double Registers
150 // ----------------------------
151
152 // Double Registers
153 // The rules of ADL require that double registers be defined in pairs.
154 // Each pair must be two 32-bit values, but not necessarily a pair of
155 // single float registers. In each pair, ADLC-assigned register numbers
156 // must be adjacent, with the lower number even. Finally, when the
157 // CPU stores such a register pair to memory, the word associated with
158 // the lower ADLC-assigned number must be stored to the lower address.
159
160 // PPC64 has 32 64-bit floating-point registers. Each can store a single
161 // or double precision floating-point value.
162
163 // types: v = volatile, nv = non-volatile, s = system
164 reg_def F0 ( SOC, SOC, Op_RegF, 0, F0->as_VMReg() ); // v scratch
165 reg_def F0_H ( SOC, SOC, Op_RegF, 99, F0->as_VMReg()->next() );
166 reg_def F1 ( SOC, SOC, Op_RegF, 1, F1->as_VMReg() ); // v farg1 & fret
167 reg_def F1_H ( SOC, SOC, Op_RegF, 99, F1->as_VMReg()->next() );
168 reg_def F2 ( SOC, SOC, Op_RegF, 2, F2->as_VMReg() ); // v farg2
169 reg_def F2_H ( SOC, SOC, Op_RegF, 99, F2->as_VMReg()->next() );
170 reg_def F3 ( SOC, SOC, Op_RegF, 3, F3->as_VMReg() ); // v farg3
171 reg_def F3_H ( SOC, SOC, Op_RegF, 99, F3->as_VMReg()->next() );
172 reg_def F4 ( SOC, SOC, Op_RegF, 4, F4->as_VMReg() ); // v farg4
173 reg_def F4_H ( SOC, SOC, Op_RegF, 99, F4->as_VMReg()->next() );
174 reg_def F5 ( SOC, SOC, Op_RegF, 5, F5->as_VMReg() ); // v farg5
175 reg_def F5_H ( SOC, SOC, Op_RegF, 99, F5->as_VMReg()->next() );
176 reg_def F6 ( SOC, SOC, Op_RegF, 6, F6->as_VMReg() ); // v farg6
177 reg_def F6_H ( SOC, SOC, Op_RegF, 99, F6->as_VMReg()->next() );
178 reg_def F7 ( SOC, SOC, Op_RegF, 7, F7->as_VMReg() ); // v farg7
179 reg_def F7_H ( SOC, SOC, Op_RegF, 99, F7->as_VMReg()->next() );
180 reg_def F8 ( SOC, SOC, Op_RegF, 8, F8->as_VMReg() ); // v farg8
181 reg_def F8_H ( SOC, SOC, Op_RegF, 99, F8->as_VMReg()->next() );
182 reg_def F9 ( SOC, SOC, Op_RegF, 9, F9->as_VMReg() ); // v farg9
183 reg_def F9_H ( SOC, SOC, Op_RegF, 99, F9->as_VMReg()->next() );
184 reg_def F10 ( SOC, SOC, Op_RegF, 10, F10->as_VMReg() ); // v farg10
185 reg_def F10_H( SOC, SOC, Op_RegF, 99, F10->as_VMReg()->next());
186 reg_def F11 ( SOC, SOC, Op_RegF, 11, F11->as_VMReg() ); // v farg11
187 reg_def F11_H( SOC, SOC, Op_RegF, 99, F11->as_VMReg()->next());
188 reg_def F12 ( SOC, SOC, Op_RegF, 12, F12->as_VMReg() ); // v farg12
189 reg_def F12_H( SOC, SOC, Op_RegF, 99, F12->as_VMReg()->next());
190 reg_def F13 ( SOC, SOC, Op_RegF, 13, F13->as_VMReg() ); // v farg13
191 reg_def F13_H( SOC, SOC, Op_RegF, 99, F13->as_VMReg()->next());
192 reg_def F14 ( SOC, SOE, Op_RegF, 14, F14->as_VMReg() ); // nv
193 reg_def F14_H( SOC, SOE, Op_RegF, 99, F14->as_VMReg()->next());
194 reg_def F15 ( SOC, SOE, Op_RegF, 15, F15->as_VMReg() ); // nv
195 reg_def F15_H( SOC, SOE, Op_RegF, 99, F15->as_VMReg()->next());
196 reg_def F16 ( SOC, SOE, Op_RegF, 16, F16->as_VMReg() ); // nv
197 reg_def F16_H( SOC, SOE, Op_RegF, 99, F16->as_VMReg()->next());
198 reg_def F17 ( SOC, SOE, Op_RegF, 17, F17->as_VMReg() ); // nv
199 reg_def F17_H( SOC, SOE, Op_RegF, 99, F17->as_VMReg()->next());
200 reg_def F18 ( SOC, SOE, Op_RegF, 18, F18->as_VMReg() ); // nv
201 reg_def F18_H( SOC, SOE, Op_RegF, 99, F18->as_VMReg()->next());
202 reg_def F19 ( SOC, SOE, Op_RegF, 19, F19->as_VMReg() ); // nv
203 reg_def F19_H( SOC, SOE, Op_RegF, 99, F19->as_VMReg()->next());
204 reg_def F20 ( SOC, SOE, Op_RegF, 20, F20->as_VMReg() ); // nv
205 reg_def F20_H( SOC, SOE, Op_RegF, 99, F20->as_VMReg()->next());
206 reg_def F21 ( SOC, SOE, Op_RegF, 21, F21->as_VMReg() ); // nv
207 reg_def F21_H( SOC, SOE, Op_RegF, 99, F21->as_VMReg()->next());
208 reg_def F22 ( SOC, SOE, Op_RegF, 22, F22->as_VMReg() ); // nv
209 reg_def F22_H( SOC, SOE, Op_RegF, 99, F22->as_VMReg()->next());
210 reg_def F23 ( SOC, SOE, Op_RegF, 23, F23->as_VMReg() ); // nv
211 reg_def F23_H( SOC, SOE, Op_RegF, 99, F23->as_VMReg()->next());
212 reg_def F24 ( SOC, SOE, Op_RegF, 24, F24->as_VMReg() ); // nv
213 reg_def F24_H( SOC, SOE, Op_RegF, 99, F24->as_VMReg()->next());
214 reg_def F25 ( SOC, SOE, Op_RegF, 25, F25->as_VMReg() ); // nv
215 reg_def F25_H( SOC, SOE, Op_RegF, 99, F25->as_VMReg()->next());
216 reg_def F26 ( SOC, SOE, Op_RegF, 26, F26->as_VMReg() ); // nv
217 reg_def F26_H( SOC, SOE, Op_RegF, 99, F26->as_VMReg()->next());
218 reg_def F27 ( SOC, SOE, Op_RegF, 27, F27->as_VMReg() ); // nv
219 reg_def F27_H( SOC, SOE, Op_RegF, 99, F27->as_VMReg()->next());
220 reg_def F28 ( SOC, SOE, Op_RegF, 28, F28->as_VMReg() ); // nv
221 reg_def F28_H( SOC, SOE, Op_RegF, 99, F28->as_VMReg()->next());
222 reg_def F29 ( SOC, SOE, Op_RegF, 29, F29->as_VMReg() ); // nv
223 reg_def F29_H( SOC, SOE, Op_RegF, 99, F29->as_VMReg()->next());
224 reg_def F30 ( SOC, SOE, Op_RegF, 30, F30->as_VMReg() ); // nv
225 reg_def F30_H( SOC, SOE, Op_RegF, 99, F30->as_VMReg()->next());
226 reg_def F31 ( SOC, SOE, Op_RegF, 31, F31->as_VMReg() ); // nv
227 reg_def F31_H( SOC, SOE, Op_RegF, 99, F31->as_VMReg()->next());
228
229 // ----------------------------
230 // Special Registers
231 // ----------------------------
232
233 // Condition Codes Flag Registers
234
235 // PPC64 has 8 condition code "registers" which are all contained
236 // in the CR register.
237
238 // types: v = volatile, nv = non-volatile, s = system
239 reg_def CCR0(SOC, SOC, Op_RegFlags, 0, CCR0->as_VMReg()); // v
240 reg_def CCR1(SOC, SOC, Op_RegFlags, 1, CCR1->as_VMReg()); // v
241 reg_def CCR2(SOC, SOC, Op_RegFlags, 2, CCR2->as_VMReg()); // nv
242 reg_def CCR3(SOC, SOC, Op_RegFlags, 3, CCR3->as_VMReg()); // nv
243 reg_def CCR4(SOC, SOC, Op_RegFlags, 4, CCR4->as_VMReg()); // nv
244 reg_def CCR5(SOC, SOC, Op_RegFlags, 5, CCR5->as_VMReg()); // v
245 reg_def CCR6(SOC, SOC, Op_RegFlags, 6, CCR6->as_VMReg()); // v
246 reg_def CCR7(SOC, SOC, Op_RegFlags, 7, CCR7->as_VMReg()); // v
247
248 // Special registers of PPC64
249
250 reg_def SR_XER( SOC, SOC, Op_RegP, 0, SR_XER->as_VMReg()); // v
251 reg_def SR_LR( SOC, SOC, Op_RegP, 1, SR_LR->as_VMReg()); // v
252 reg_def SR_CTR( SOC, SOC, Op_RegP, 2, SR_CTR->as_VMReg()); // v
253 reg_def SR_VRSAVE( SOC, SOC, Op_RegP, 3, SR_VRSAVE->as_VMReg()); // v
254 reg_def SR_SPEFSCR(SOC, SOC, Op_RegP, 4, SR_SPEFSCR->as_VMReg()); // v
255 reg_def SR_PPR( SOC, SOC, Op_RegP, 5, SR_PPR->as_VMReg()); // v
256
257
258 // ----------------------------
259 // Specify priority of register selection within phases of register
260 // allocation. Highest priority is first. A useful heuristic is to
261 // give registers a low priority when they are required by machine
262 // instructions, like EAX and EDX on I486, and choose no-save registers
263 // before save-on-call, & save-on-call before save-on-entry. Registers
264 // which participate in fixed calling sequences should come last.
265 // Registers which are used as pairs must fall on an even boundary.
266
267 // It's worth about 1% on SPEC geomean to get this right.
268
269 // Chunk0, chunk1, and chunk2 form the MachRegisterNumbers enumeration
270 // in adGlobals_ppc64.hpp which defines the <register>_num values, e.g.
271 // R3_num. Therefore, R3_num may not be (and in reality is not)
272 // the same as R3->encoding()! Furthermore, we cannot make any
273 // assumptions on ordering, e.g. R3_num may be less than R2_num.
274 // Additionally, the function
275 // static enum RC rc_class(OptoReg::Name reg )
276 // maps a given <register>_num value to its chunk type (except for flags)
277 // and its current implementation relies on chunk0 and chunk1 having a
278 // size of 64 each.
279
280 // If you change this allocation class, please have a look at the
281 // default values for the parameters RoundRobinIntegerRegIntervalStart
282 // and RoundRobinFloatRegIntervalStart
283
284 alloc_class chunk0 (
285 // Chunk0 contains *all* 64 integer registers halves.
286
287 // "non-volatile" registers
288 R14, R14_H,
289 R15, R15_H,
290 R17, R17_H,
291 R18, R18_H,
292 R19, R19_H,
293 R20, R20_H,
294 R21, R21_H,
295 R22, R22_H,
296 R23, R23_H,
297 R24, R24_H,
298 R25, R25_H,
299 R26, R26_H,
300 R27, R27_H,
301 R28, R28_H,
302 R29, R29_H,
303 R30, R30_H,
304 R31, R31_H,
305
306 // scratch/special registers
307 R11, R11_H,
308 R12, R12_H,
309
310 // argument registers
311 R10, R10_H,
312 R9, R9_H,
313 R8, R8_H,
314 R7, R7_H,
315 R6, R6_H,
316 R5, R5_H,
317 R4, R4_H,
318 R3, R3_H,
319
320 // special registers, not available for allocation
321 R16, R16_H, // R16_thread
322 R13, R13_H, // system thread id
323 R2, R2_H, // may be used for TOC
324 R1, R1_H, // SP
325 R0, R0_H // R0 (scratch)
326 );
327
328 // If you change this allocation class, please have a look at the
329 // default values for the parameters RoundRobinIntegerRegIntervalStart
330 // and RoundRobinFloatRegIntervalStart
331
332 alloc_class chunk1 (
333 // Chunk1 contains *all* 64 floating-point registers halves.
334
335 // scratch register
336 F0, F0_H,
337
338 // argument registers
339 F13, F13_H,
340 F12, F12_H,
341 F11, F11_H,
342 F10, F10_H,
343 F9, F9_H,
344 F8, F8_H,
345 F7, F7_H,
346 F6, F6_H,
347 F5, F5_H,
348 F4, F4_H,
349 F3, F3_H,
350 F2, F2_H,
351 F1, F1_H,
352
353 // non-volatile registers
354 F14, F14_H,
355 F15, F15_H,
356 F16, F16_H,
357 F17, F17_H,
358 F18, F18_H,
359 F19, F19_H,
360 F20, F20_H,
361 F21, F21_H,
362 F22, F22_H,
363 F23, F23_H,
364 F24, F24_H,
365 F25, F25_H,
366 F26, F26_H,
367 F27, F27_H,
368 F28, F28_H,
369 F29, F29_H,
370 F30, F30_H,
371 F31, F31_H
372 );
373
374 alloc_class chunk2 (
375 // Chunk2 contains *all* 8 condition code registers.
376
377 CCR0,
378 CCR1,
379 CCR2,
380 CCR3,
381 CCR4,
382 CCR5,
383 CCR6,
384 CCR7
385 );
386
387 alloc_class chunk3 (
388 // special registers
389 // These registers are not allocated, but used for nodes generated by postalloc expand.
390 SR_XER,
391 SR_LR,
392 SR_CTR,
393 SR_VRSAVE,
394 SR_SPEFSCR,
395 SR_PPR
396 );
397
398 //-------Architecture Description Register Classes-----------------------
399
400 // Several register classes are automatically defined based upon
401 // information in this architecture description.
402
403 // 1) reg_class inline_cache_reg ( as defined in frame section )
404 // 2) reg_class compiler_method_oop_reg ( as defined in frame section )
405 // 2) reg_class interpreter_method_oop_reg ( as defined in frame section )
406 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
407 //
408
409 // ----------------------------
410 // 32 Bit Register Classes
411 // ----------------------------
412
413 // We specify registers twice, once as read/write, and once read-only.
414 // We use the read-only registers for source operands. With this, we
415 // can include preset read only registers in this class, as a hard-coded
416 // '0'-register. (We used to simulate this on ppc.)
417
418 // 32 bit registers that can be read and written i.e. these registers
419 // can be dest (or src) of normal instructions.
420 reg_class bits32_reg_rw(
421 /*R0*/ // R0
422 /*R1*/ // SP
423 R2, // TOC
424 R3,
425 R4,
426 R5,
427 R6,
428 R7,
429 R8,
430 R9,
431 R10,
432 R11,
433 R12,
434 /*R13*/ // system thread id
435 R14,
436 R15,
437 /*R16*/ // R16_thread
438 R17,
439 R18,
440 R19,
441 R20,
442 R21,
443 R22,
444 R23,
445 R24,
446 R25,
447 R26,
448 R27,
449 R28,
450 /*R29*/ // global TOC
451 /*R30*/ // Narrow Oop Base
452 R31
453 );
454
455 // 32 bit registers that can only be read i.e. these registers can
456 // only be src of all instructions.
457 reg_class bits32_reg_ro(
458 /*R0*/ // R0
459 /*R1*/ // SP
460 R2 // TOC
461 R3,
462 R4,
463 R5,
464 R6,
465 R7,
466 R8,
467 R9,
468 R10,
469 R11,
470 R12,
471 /*R13*/ // system thread id
472 R14,
473 R15,
474 /*R16*/ // R16_thread
475 R17,
476 R18,
477 R19,
478 R20,
479 R21,
480 R22,
481 R23,
482 R24,
483 R25,
484 R26,
485 R27,
486 R28,
487 /*R29*/
488 /*R30*/ // Narrow Oop Base
489 R31
490 );
491
492 // Complement-required-in-pipeline operands for narrow oops.
493 reg_class bits32_reg_ro_not_complement (
494 /*R0*/ // R0
495 R1, // SP
496 R2, // TOC
497 R3,
498 R4,
499 R5,
500 R6,
501 R7,
502 R8,
503 R9,
504 R10,
505 R11,
506 R12,
507 /*R13,*/ // system thread id
508 R14,
509 R15,
510 R16, // R16_thread
511 R17,
512 R18,
513 R19,
514 R20,
515 R21,
516 R22,
517 /*R23,
518 R24,
519 R25,
520 R26,
521 R27,
522 R28,*/
523 /*R29,*/ // TODO: let allocator handle TOC!!
524 /*R30,*/
525 R31
526 );
527
528 // Complement-required-in-pipeline operands for narrow oops.
529 // See 64-bit declaration.
530 reg_class bits32_reg_ro_complement (
531 R23,
532 R24,
533 R25,
534 R26,
535 R27,
536 R28
537 );
538
539 reg_class rscratch1_bits32_reg(R11);
540 reg_class rscratch2_bits32_reg(R12);
541 reg_class rarg1_bits32_reg(R3);
542 reg_class rarg2_bits32_reg(R4);
543 reg_class rarg3_bits32_reg(R5);
544 reg_class rarg4_bits32_reg(R6);
545
546 // ----------------------------
547 // 64 Bit Register Classes
548 // ----------------------------
549 // 64-bit build means 64-bit pointers means hi/lo pairs
550
551 reg_class rscratch1_bits64_reg(R11_H, R11);
552 reg_class rscratch2_bits64_reg(R12_H, R12);
553 reg_class rarg1_bits64_reg(R3_H, R3);
554 reg_class rarg2_bits64_reg(R4_H, R4);
555 reg_class rarg3_bits64_reg(R5_H, R5);
556 reg_class rarg4_bits64_reg(R6_H, R6);
557 // Thread register, 'written' by tlsLoadP, see there.
558 reg_class thread_bits64_reg(R16_H, R16);
559
560 reg_class r19_bits64_reg(R19_H, R19);
561
562 // 64 bit registers that can be read and written i.e. these registers
563 // can be dest (or src) of normal instructions.
564 reg_class bits64_reg_rw(
565 /*R0_H, R0*/ // R0
566 /*R1_H, R1*/ // SP
567 R2_H, R2, // TOC
568 R3_H, R3,
569 R4_H, R4,
570 R5_H, R5,
571 R6_H, R6,
572 R7_H, R7,
573 R8_H, R8,
574 R9_H, R9,
575 R10_H, R10,
576 R11_H, R11,
577 R12_H, R12,
578 /*R13_H, R13*/ // system thread id
579 R14_H, R14,
580 R15_H, R15,
581 /*R16_H, R16*/ // R16_thread
582 R17_H, R17,
583 R18_H, R18,
584 R19_H, R19,
585 R20_H, R20,
586 R21_H, R21,
587 R22_H, R22,
588 R23_H, R23,
589 R24_H, R24,
590 R25_H, R25,
591 R26_H, R26,
592 R27_H, R27,
593 R28_H, R28,
594 /*R29_H, R29*/
595 /*R30_H, R30*/
596 R31_H, R31
597 );
598
599 // 64 bit registers used excluding r2, r11 and r12
600 // Used to hold the TOC to avoid collisions with expanded LeafCall which uses
601 // r2, r11 and r12 internally.
602 reg_class bits64_reg_leaf_call(
603 /*R0_H, R0*/ // R0
604 /*R1_H, R1*/ // SP
605 /*R2_H, R2*/ // TOC
606 R3_H, R3,
607 R4_H, R4,
608 R5_H, R5,
609 R6_H, R6,
610 R7_H, R7,
611 R8_H, R8,
612 R9_H, R9,
613 R10_H, R10,
614 /*R11_H, R11*/
615 /*R12_H, R12*/
616 /*R13_H, R13*/ // system thread id
617 R14_H, R14,
618 R15_H, R15,
619 /*R16_H, R16*/ // R16_thread
620 R17_H, R17,
621 R18_H, R18,
622 R19_H, R19,
623 R20_H, R20,
624 R21_H, R21,
625 R22_H, R22,
626 R23_H, R23,
627 R24_H, R24,
628 R25_H, R25,
629 R26_H, R26,
630 R27_H, R27,
631 R28_H, R28,
632 /*R29_H, R29*/
633 /*R30_H, R30*/
634 R31_H, R31
635 );
636
637 // Used to hold the TOC to avoid collisions with expanded DynamicCall
638 // which uses r19 as inline cache internally and expanded LeafCall which uses
639 // r2, r11 and r12 internally.
640 reg_class bits64_constant_table_base(
641 /*R0_H, R0*/ // R0
642 /*R1_H, R1*/ // SP
643 /*R2_H, R2*/ // TOC
644 R3_H, R3,
645 R4_H, R4,
646 R5_H, R5,
647 R6_H, R6,
648 R7_H, R7,
649 R8_H, R8,
650 R9_H, R9,
651 R10_H, R10,
652 /*R11_H, R11*/
653 /*R12_H, R12*/
654 /*R13_H, R13*/ // system thread id
655 R14_H, R14,
656 R15_H, R15,
657 /*R16_H, R16*/ // R16_thread
658 R17_H, R17,
659 R18_H, R18,
660 /*R19_H, R19*/
661 R20_H, R20,
662 R21_H, R21,
663 R22_H, R22,
664 R23_H, R23,
665 R24_H, R24,
666 R25_H, R25,
667 R26_H, R26,
668 R27_H, R27,
669 R28_H, R28,
670 /*R29_H, R29*/
671 /*R30_H, R30*/
672 R31_H, R31
673 );
674
675 // 64 bit registers that can only be read i.e. these registers can
676 // only be src of all instructions.
677 reg_class bits64_reg_ro(
678 /*R0_H, R0*/ // R0
679 R1_H, R1,
680 R2_H, R2, // TOC
681 R3_H, R3,
682 R4_H, R4,
683 R5_H, R5,
684 R6_H, R6,
685 R7_H, R7,
686 R8_H, R8,
687 R9_H, R9,
688 R10_H, R10,
689 R11_H, R11,
690 R12_H, R12,
691 /*R13_H, R13*/ // system thread id
692 R14_H, R14,
693 R15_H, R15,
694 R16_H, R16, // R16_thread
695 R17_H, R17,
696 R18_H, R18,
697 R19_H, R19,
698 R20_H, R20,
699 R21_H, R21,
700 R22_H, R22,
701 R23_H, R23,
702 R24_H, R24,
703 R25_H, R25,
704 R26_H, R26,
705 R27_H, R27,
706 R28_H, R28,
707 /*R29_H, R29*/ // TODO: let allocator handle TOC!!
708 /*R30_H, R30,*/
709 R31_H, R31
710 );
711
712 // Complement-required-in-pipeline operands.
713 reg_class bits64_reg_ro_not_complement (
714 /*R0_H, R0*/ // R0
715 R1_H, R1, // SP
716 R2_H, R2, // TOC
717 R3_H, R3,
718 R4_H, R4,
719 R5_H, R5,
720 R6_H, R6,
721 R7_H, R7,
722 R8_H, R8,
723 R9_H, R9,
724 R10_H, R10,
725 R11_H, R11,
726 R12_H, R12,
727 /*R13_H, R13*/ // system thread id
728 R14_H, R14,
729 R15_H, R15,
730 R16_H, R16, // R16_thread
731 R17_H, R17,
732 R18_H, R18,
733 R19_H, R19,
734 R20_H, R20,
735 R21_H, R21,
736 R22_H, R22,
737 /*R23_H, R23,
738 R24_H, R24,
739 R25_H, R25,
740 R26_H, R26,
741 R27_H, R27,
742 R28_H, R28,*/
743 /*R29_H, R29*/ // TODO: let allocator handle TOC!!
744 /*R30_H, R30,*/
745 R31_H, R31
746 );
747
748 // Complement-required-in-pipeline operands.
749 // This register mask is used for the trap instructions that implement
750 // the null checks on AIX. The trap instruction first computes the
751 // complement of the value it shall trap on. Because of this, the
752 // instruction can not be scheduled in the same cycle as an other
753 // instruction reading the normal value of the same register. So we
754 // force the value to check into 'bits64_reg_ro_not_complement'
755 // and then copy it to 'bits64_reg_ro_complement' for the trap.
756 reg_class bits64_reg_ro_complement (
757 R23_H, R23,
758 R24_H, R24,
759 R25_H, R25,
760 R26_H, R26,
761 R27_H, R27,
762 R28_H, R28
763 );
764
765
766 // ----------------------------
767 // Special Class for Condition Code Flags Register
768
769 reg_class int_flags(
770 /*CCR0*/ // scratch
771 /*CCR1*/ // scratch
772 /*CCR2*/ // nv!
773 /*CCR3*/ // nv!
774 /*CCR4*/ // nv!
775 CCR5,
776 CCR6,
777 CCR7
778 );
779
780 reg_class int_flags_CR0(CCR0);
781 reg_class int_flags_CR1(CCR1);
782 reg_class int_flags_CR6(CCR6);
783 reg_class ctr_reg(SR_CTR);
784
785 // ----------------------------
786 // Float Register Classes
787 // ----------------------------
788
789 reg_class flt_reg(
790 /*F0*/ // scratch
791 F1,
792 F2,
793 F3,
794 F4,
795 F5,
796 F6,
797 F7,
798 F8,
799 F9,
800 F10,
801 F11,
802 F12,
803 F13,
804 F14, // nv!
805 F15, // nv!
806 F16, // nv!
807 F17, // nv!
808 F18, // nv!
809 F19, // nv!
810 F20, // nv!
811 F21, // nv!
812 F22, // nv!
813 F23, // nv!
814 F24, // nv!
815 F25, // nv!
816 F26, // nv!
817 F27, // nv!
818 F28, // nv!
819 F29, // nv!
820 F30, // nv!
821 F31 // nv!
822 );
823
824 // Double precision float registers have virtual `high halves' that
825 // are needed by the allocator.
826 reg_class dbl_reg(
827 /*F0, F0_H*/ // scratch
828 F1, F1_H,
829 F2, F2_H,
830 F3, F3_H,
831 F4, F4_H,
832 F5, F5_H,
833 F6, F6_H,
834 F7, F7_H,
835 F8, F8_H,
836 F9, F9_H,
837 F10, F10_H,
838 F11, F11_H,
839 F12, F12_H,
840 F13, F13_H,
841 F14, F14_H, // nv!
842 F15, F15_H, // nv!
843 F16, F16_H, // nv!
844 F17, F17_H, // nv!
845 F18, F18_H, // nv!
846 F19, F19_H, // nv!
847 F20, F20_H, // nv!
848 F21, F21_H, // nv!
849 F22, F22_H, // nv!
850 F23, F23_H, // nv!
851 F24, F24_H, // nv!
852 F25, F25_H, // nv!
853 F26, F26_H, // nv!
854 F27, F27_H, // nv!
855 F28, F28_H, // nv!
856 F29, F29_H, // nv!
857 F30, F30_H, // nv!
858 F31, F31_H // nv!
859 );
860
861 %}
862
863 //----------DEFINITION BLOCK---------------------------------------------------
864 // Define name --> value mappings to inform the ADLC of an integer valued name
865 // Current support includes integer values in the range [0, 0x7FFFFFFF]
866 // Format:
867 // int_def <name> ( <int_value>, <expression>);
868 // Generated Code in ad_<arch>.hpp
869 // #define <name> (<expression>)
870 // // value == <int_value>
871 // Generated code in ad_<arch>.cpp adlc_verification()
872 // assert( <name> == <int_value>, "Expect (<expression>) to equal <int_value>");
873 //
874 definitions %{
875 // The default cost (of an ALU instruction).
876 int_def DEFAULT_COST_LOW ( 30, 30);
877 int_def DEFAULT_COST ( 100, 100);
878 int_def HUGE_COST (1000000, 1000000);
879
880 // Memory refs
881 int_def MEMORY_REF_COST_LOW ( 200, DEFAULT_COST * 2);
882 int_def MEMORY_REF_COST ( 300, DEFAULT_COST * 3);
883
884 // Branches are even more expensive.
885 int_def BRANCH_COST ( 900, DEFAULT_COST * 9);
886 int_def CALL_COST ( 1300, DEFAULT_COST * 13);
887 %}
888
889
890 //----------SOURCE BLOCK-------------------------------------------------------
891 // This is a block of C++ code which provides values, functions, and
892 // definitions necessary in the rest of the architecture description.
893 source_hpp %{
894 // Header information of the source block.
895 // Method declarations/definitions which are used outside
896 // the ad-scope can conveniently be defined here.
897 //
898 // To keep related declarations/definitions/uses close together,
899 // we switch between source %{ }% and source_hpp %{ }% freely as needed.
900
901 // Returns true if Node n is followed by a MemBar node that
902 // will do an acquire. If so, this node must not do the acquire
903 // operation.
904 bool followed_by_acquire(const Node *n);
905 %}
906
907 source %{
908
909 // Optimize load-acquire.
910 //
911 // Check if acquire is unnecessary due to following operation that does
912 // acquire anyways.
913 // Walk the pattern:
914 //
915 // n: Load.acq
916 // |
917 // MemBarAcquire
918 // | |
919 // Proj(ctrl) Proj(mem)
920 // | |
921 // MemBarRelease/Volatile
922 //
923 bool followed_by_acquire(const Node *load) {
924 assert(load->is_Load(), "So far implemented only for loads.");
925
926 // Find MemBarAcquire.
927 const Node *mba = NULL;
928 for (DUIterator_Fast imax, i = load->fast_outs(imax); i < imax; i++) {
929 const Node *out = load->fast_out(i);
930 if (out->Opcode() == Op_MemBarAcquire) {
931 if (out->in(0) == load) continue; // Skip control edge, membar should be found via precedence edge.
932 mba = out;
933 break;
934 }
935 }
936 if (!mba) return false;
937
938 // Find following MemBar node.
939 //
940 // The following node must be reachable by control AND memory
941 // edge to assure no other operations are in between the two nodes.
942 //
943 // So first get the Proj node, mem_proj, to use it to iterate forward.
944 Node *mem_proj = NULL;
945 for (DUIterator_Fast imax, i = mba->fast_outs(imax); i < imax; i++) {
946 mem_proj = mba->fast_out(i); // Throw out-of-bounds if proj not found
947 assert(mem_proj->is_Proj(), "only projections here");
948 ProjNode *proj = mem_proj->as_Proj();
949 if (proj->_con == TypeFunc::Memory &&
950 !Compile::current()->node_arena()->contains(mem_proj)) // Unmatched old-space only
951 break;
952 }
953 assert(mem_proj->as_Proj()->_con == TypeFunc::Memory, "Graph broken");
954
955 // Search MemBar behind Proj. If there are other memory operations
956 // behind the Proj we lost.
957 for (DUIterator_Fast jmax, j = mem_proj->fast_outs(jmax); j < jmax; j++) {
958 Node *x = mem_proj->fast_out(j);
959 // Proj might have an edge to a store or load node which precedes the membar.
960 if (x->is_Mem()) return false;
961
962 // On PPC64 release and volatile are implemented by an instruction
963 // that also has acquire semantics. I.e. there is no need for an
964 // acquire before these.
965 int xop = x->Opcode();
966 if (xop == Op_MemBarRelease || xop == Op_MemBarVolatile) {
967 // Make sure we're not missing Call/Phi/MergeMem by checking
968 // control edges. The control edge must directly lead back
969 // to the MemBarAcquire
970 Node *ctrl_proj = x->in(0);
971 if (ctrl_proj->is_Proj() && ctrl_proj->in(0) == mba) {
972 return true;
973 }
974 }
975 }
976
977 return false;
978 }
979
980 #define __ _masm.
981
982 // Tertiary op of a LoadP or StoreP encoding.
983 #define REGP_OP true
984
985 // ****************************************************************************
986
987 // REQUIRED FUNCTIONALITY
988
989 // !!!!! Special hack to get all type of calls to specify the byte offset
990 // from the start of the call to the point where the return address
991 // will point.
992
993 // PPC port: Removed use of lazy constant construct.
994
995 int MachCallStaticJavaNode::ret_addr_offset() {
996 // It's only a single branch-and-link instruction.
997 return 4;
998 }
999
1000 int MachCallDynamicJavaNode::ret_addr_offset() {
1001 // Offset is 4 with postalloc expanded calls (bl is one instruction). We use
1002 // postalloc expanded calls if we use inline caches and do not update method data.
1003 if (UseInlineCaches)
1004 return 4;
1005
1006 int vtable_index = this->_vtable_index;
1007 if (vtable_index < 0) {
1008 // Must be invalid_vtable_index, not nonvirtual_vtable_index.
1009 assert(vtable_index == Method::invalid_vtable_index, "correct sentinel value");
1010 return 12;
1011 } else {
1012 assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
1013 return 24;
1014 }
1015 }
1016
1017 int MachCallRuntimeNode::ret_addr_offset() {
1018 #if defined(ABI_ELFv2)
1019 return 28;
1020 #else
1021 return 40;
1022 #endif
1023 }
1024
1025 //=============================================================================
1026
1027 // condition code conversions
1028
1029 static int cc_to_boint(int cc) {
1030 return Assembler::bcondCRbiIs0 | (cc & 8);
1031 }
1032
1033 static int cc_to_inverse_boint(int cc) {
1034 return Assembler::bcondCRbiIs0 | (8-(cc & 8));
1035 }
1036
1037 static int cc_to_biint(int cc, int flags_reg) {
1038 return (flags_reg << 2) | (cc & 3);
1039 }
1040
1041 //=============================================================================
1042
1043 // Compute padding required for nodes which need alignment. The padding
1044 // is the number of bytes (not instructions) which will be inserted before
1045 // the instruction. The padding must match the size of a NOP instruction.
1046
1047 int string_indexOf_imm1_charNode::compute_padding(int current_offset) const {
1048 return (3*4-current_offset)&31;
1049 }
1050
1051 int string_indexOf_imm1Node::compute_padding(int current_offset) const {
1052 return (2*4-current_offset)&31;
1053 }
1054
1055 int string_indexOf_immNode::compute_padding(int current_offset) const {
1056 return (3*4-current_offset)&31;
1057 }
1058
1059 int string_indexOfNode::compute_padding(int current_offset) const {
1060 return (1*4-current_offset)&31;
1061 }
1062
1063 int string_compareNode::compute_padding(int current_offset) const {
1064 return (4*4-current_offset)&31;
1065 }
1066
1067 int string_equals_immNode::compute_padding(int current_offset) const {
1068 if (opnd_array(3)->constant() < 16) return 0; // Don't insert nops for short version (loop completely unrolled).
1069 return (2*4-current_offset)&31;
1070 }
1071
1072 int string_equalsNode::compute_padding(int current_offset) const {
1073 return (7*4-current_offset)&31;
1074 }
1075
1076 int inlineCallClearArrayNode::compute_padding(int current_offset) const {
1077 return (2*4-current_offset)&31;
1078 }
1079
1080 //=============================================================================
1081
1082 // Indicate if the safepoint node needs the polling page as an input.
1083 bool SafePointNode::needs_polling_address_input() {
1084 // The address is loaded from thread by a seperate node.
1085 return true;
1086 }
1087
1088 //=============================================================================
1089
1090 // Emit an interrupt that is caught by the debugger (for debugging compiler).
1091 void emit_break(CodeBuffer &cbuf) {
1092 MacroAssembler _masm(&cbuf);
1093 __ illtrap();
1094 }
1095
1096 #ifndef PRODUCT
1097 void MachBreakpointNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1098 st->print("BREAKPOINT");
1099 }
1100 #endif
1101
1102 void MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1103 emit_break(cbuf);
1104 }
1105
1106 uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const {
1107 return MachNode::size(ra_);
1108 }
1109
1110 //=============================================================================
1111
1112 void emit_nop(CodeBuffer &cbuf) {
1113 MacroAssembler _masm(&cbuf);
1114 __ nop();
1115 }
1116
1117 static inline void emit_long(CodeBuffer &cbuf, int value) {
1118 *((int*)(cbuf.insts_end())) = value;
1119 cbuf.set_insts_end(cbuf.insts_end() + BytesPerInstWord);
1120 }
1121
1122 //=============================================================================
1123
1124 %} // interrupt source
1125
1126 source_hpp %{ // Header information of the source block.
1127
1128 //--------------------------------------------------------------
1129 //---< Used for optimization in Compile::Shorten_branches >---
1130 //--------------------------------------------------------------
1131
1132 const uint trampoline_stub_size = 6 * BytesPerInstWord;
1133
1134 class CallStubImpl {
1135
1136 public:
1137
1138 // Emit call stub, compiled java to interpreter.
1139 static void emit_trampoline_stub(MacroAssembler &_masm, int destination_toc_offset, int insts_call_instruction_offset);
1140
1141 // Size of call trampoline stub.
1142 // This doesn't need to be accurate to the byte, but it
1143 // must be larger than or equal to the real size of the stub.
1144 static uint size_call_trampoline() {
1145 return trampoline_stub_size;
1146 }
1147
1148 // number of relocations needed by a call trampoline stub
1149 static uint reloc_call_trampoline() {
1150 return 5;
1151 }
1152
1153 };
1154
1155 %} // end source_hpp
1156
1157 source %{
1158
1159 // Emit a trampoline stub for a call to a target which is too far away.
1160 //
1161 // code sequences:
1162 //
1163 // call-site:
1164 // branch-and-link to <destination> or <trampoline stub>
1165 //
1166 // Related trampoline stub for this call-site in the stub section:
1167 // load the call target from the constant pool
1168 // branch via CTR (LR/link still points to the call-site above)
1169
1170 void CallStubImpl::emit_trampoline_stub(MacroAssembler &_masm, int destination_toc_offset, int insts_call_instruction_offset) {
1171 // Start the stub.
1172 address stub = __ start_a_stub(Compile::MAX_stubs_size/2);
1173 if (stub == NULL) {
1174 Compile::current()->env()->record_out_of_memory_failure();
1175 return;
1176 }
1177
1178 // For java_to_interp stubs we use R11_scratch1 as scratch register
1179 // and in call trampoline stubs we use R12_scratch2. This way we
1180 // can distinguish them (see is_NativeCallTrampolineStub_at()).
1181 Register reg_scratch = R12_scratch2;
1182
1183 // Create a trampoline stub relocation which relates this trampoline stub
1184 // with the call instruction at insts_call_instruction_offset in the
1185 // instructions code-section.
1186 __ relocate(trampoline_stub_Relocation::spec(__ code()->insts()->start() + insts_call_instruction_offset));
1187 const int stub_start_offset = __ offset();
1188
1189 // Now, create the trampoline stub's code:
1190 // - load the TOC
1191 // - load the call target from the constant pool
1192 // - call
1193 __ calculate_address_from_global_toc(reg_scratch, __ method_toc());
1194 __ ld_largeoffset_unchecked(reg_scratch, destination_toc_offset, reg_scratch, false);
1195 __ mtctr(reg_scratch);
1196 __ bctr();
1197
1198 const address stub_start_addr = __ addr_at(stub_start_offset);
1199
1200 // FIXME: Assert that the trampoline stub can be identified and patched.
1201
1202 // Assert that the encoded destination_toc_offset can be identified and that it is correct.
1203 assert(destination_toc_offset == NativeCallTrampolineStub_at(stub_start_addr)->destination_toc_offset(),
1204 "encoded offset into the constant pool must match");
1205 // Trampoline_stub_size should be good.
1206 assert((uint)(__ offset() - stub_start_offset) <= trampoline_stub_size, "should be good size");
1207 assert(is_NativeCallTrampolineStub_at(stub_start_addr), "doesn't look like a trampoline");
1208
1209 // End the stub.
1210 __ end_a_stub();
1211 }
1212
1213 //=============================================================================
1214
1215 // Emit an inline branch-and-link call and a related trampoline stub.
1216 //
1217 // code sequences:
1218 //
1219 // call-site:
1220 // branch-and-link to <destination> or <trampoline stub>
1221 //
1222 // Related trampoline stub for this call-site in the stub section:
1223 // load the call target from the constant pool
1224 // branch via CTR (LR/link still points to the call-site above)
1225 //
1226
1227 typedef struct {
1228 int insts_call_instruction_offset;
1229 int ret_addr_offset;
1230 } EmitCallOffsets;
1231
1232 // Emit a branch-and-link instruction that branches to a trampoline.
1233 // - Remember the offset of the branch-and-link instruction.
1234 // - Add a relocation at the branch-and-link instruction.
1235 // - Emit a branch-and-link.
1236 // - Remember the return pc offset.
1237 EmitCallOffsets emit_call_with_trampoline_stub(MacroAssembler &_masm, address entry_point, relocInfo::relocType rtype) {
1238 EmitCallOffsets offsets = { -1, -1 };
1239 const int start_offset = __ offset();
1240 offsets.insts_call_instruction_offset = __ offset();
1241
1242 // No entry point given, use the current pc.
1243 if (entry_point == NULL) entry_point = __ pc();
1244
1245 if (!Compile::current()->in_scratch_emit_size()) {
1246 // Put the entry point as a constant into the constant pool.
1247 const address entry_point_toc_addr = __ address_constant(entry_point, RelocationHolder::none);
1248 const int entry_point_toc_offset = __ offset_to_method_toc(entry_point_toc_addr);
1249
1250 // Emit the trampoline stub which will be related to the branch-and-link below.
1251 CallStubImpl::emit_trampoline_stub(_masm, entry_point_toc_offset, offsets.insts_call_instruction_offset);
1252 if (Compile::current()->env()->failing()) { return offsets; } // Code cache may be full.
1253 __ relocate(rtype);
1254 }
1255
1256 // Note: At this point we do not have the address of the trampoline
1257 // stub, and the entry point might be too far away for bl, so __ pc()
1258 // serves as dummy and the bl will be patched later.
1259 __ bl((address) __ pc());
1260
1261 offsets.ret_addr_offset = __ offset() - start_offset;
1262
1263 return offsets;
1264 }
1265
1266 //=============================================================================
1267
1268 // Factory for creating loadConL* nodes for large/small constant pool.
1269
1270 static inline jlong replicate_immF(float con) {
1271 // Replicate float con 2 times and pack into vector.
1272 int val = *((int*)&con);
1273 jlong lval = val;
1274 lval = (lval << 32) | (lval & 0xFFFFFFFFl);
1275 return lval;
1276 }
1277
1278 //=============================================================================
1279
1280 const RegMask& MachConstantBaseNode::_out_RegMask = BITS64_CONSTANT_TABLE_BASE_mask();
1281 int Compile::ConstantTable::calculate_table_base_offset() const {
1282 return 0; // absolute addressing, no offset
1283 }
1284
1285 bool MachConstantBaseNode::requires_postalloc_expand() const { return true; }
1286 void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) {
1287 Compile *C = ra_->C;
1288
1289 iRegPdstOper *op_dst = new (C) iRegPdstOper();
1290 MachNode *m1 = new (C) loadToc_hiNode();
1291 MachNode *m2 = new (C) loadToc_loNode();
1292
1293 m1->add_req(NULL);
1294 m2->add_req(NULL, m1);
1295 m1->_opnds[0] = op_dst;
1296 m2->_opnds[0] = op_dst;
1297 m2->_opnds[1] = op_dst;
1298 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
1299 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
1300 nodes->push(m1);
1301 nodes->push(m2);
1302 }
1303
1304 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
1305 // Is postalloc expanded.
1306 ShouldNotReachHere();
1307 }
1308
1309 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const {
1310 return 0;
1311 }
1312
1313 #ifndef PRODUCT
1314 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
1315 st->print("-- \t// MachConstantBaseNode (empty encoding)");
1316 }
1317 #endif
1318
1319 //=============================================================================
1320
1321 #ifndef PRODUCT
1322 void MachPrologNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1323 Compile* C = ra_->C;
1324 const long framesize = C->frame_slots() << LogBytesPerInt;
1325
1326 st->print("PROLOG\n\t");
1327 if (C->need_stack_bang(framesize)) {
1328 st->print("stack_overflow_check\n\t");
1329 }
1330
1331 if (!false /* TODO: PPC port C->is_frameless_method()*/) {
1332 st->print("save return pc\n\t");
1333 st->print("push frame %ld\n\t", -framesize);
1334 }
1335 }
1336 #endif
1337
1338 // Macro used instead of the common __ to emulate the pipes of PPC.
1339 // Instead of e.g. __ ld(...) one hase to write ___(ld) ld(...) This enables the
1340 // micro scheduler to cope with "hand written" assembler like in the prolog. Though
1341 // still no scheduling of this code is possible, the micro scheduler is aware of the
1342 // code and can update its internal data. The following mechanism is used to achieve this:
1343 // The micro scheduler calls size() of each compound node during scheduling. size() does a
1344 // dummy emit and only during this dummy emit C->hb_scheduling() is not NULL.
1345 #if 0 // TODO: PPC port
1346 #define ___(op) if (UsePower6SchedulerPPC64 && C->hb_scheduling()) \
1347 C->hb_scheduling()->_pdScheduling->PdEmulatePipe(ppc64Opcode_##op); \
1348 _masm.
1349 #define ___stop if (UsePower6SchedulerPPC64 && C->hb_scheduling()) \
1350 C->hb_scheduling()->_pdScheduling->PdEmulatePipe(archOpcode_none)
1351 #define ___advance if (UsePower6SchedulerPPC64 && C->hb_scheduling()) \
1352 C->hb_scheduling()->_pdScheduling->advance_offset
1353 #else
1354 #define ___(op) if (UsePower6SchedulerPPC64) \
1355 Unimplemented(); \
1356 _masm.
1357 #define ___stop if (UsePower6SchedulerPPC64) \
1358 Unimplemented()
1359 #define ___advance if (UsePower6SchedulerPPC64) \
1360 Unimplemented()
1361 #endif
1362
1363 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1364 Compile* C = ra_->C;
1365 MacroAssembler _masm(&cbuf);
1366
1367 const long framesize = C->frame_size_in_bytes();
1368 assert(framesize % (2 * wordSize) == 0, "must preserve 2*wordSize alignment");
1369
1370 const bool method_is_frameless = false /* TODO: PPC port C->is_frameless_method()*/;
1371
1372 const Register return_pc = R20; // Must match return_addr() in frame section.
1373 const Register callers_sp = R21;
1374 const Register push_frame_temp = R22;
1375 const Register toc_temp = R23;
1376 assert_different_registers(R11, return_pc, callers_sp, push_frame_temp, toc_temp);
1377
1378 if (method_is_frameless) {
1379 // Add nop at beginning of all frameless methods to prevent any
1380 // oop instructions from getting overwritten by make_not_entrant
1381 // (patching attempt would fail).
1382 ___(nop) nop();
1383 } else {
1384 // Get return pc.
1385 ___(mflr) mflr(return_pc);
1386 }
1387
1388 // Calls to C2R adapters often do not accept exceptional returns.
1389 // We require that their callers must bang for them. But be
1390 // careful, because some VM calls (such as call site linkage) can
1391 // use several kilobytes of stack. But the stack safety zone should
1392 // account for that. See bugs 4446381, 4468289, 4497237.
1393
1394 int bangsize = C->bang_size_in_bytes();
1395 assert(bangsize >= framesize || bangsize <= 0, "stack bang size incorrect");
1396 if (C->need_stack_bang(bangsize) && UseStackBanging) {
1397 // Unfortunately we cannot use the function provided in
1398 // assembler.cpp as we have to emulate the pipes. So I had to
1399 // insert the code of generate_stack_overflow_check(), see
1400 // assembler.cpp for some illuminative comments.
1401 const int page_size = os::vm_page_size();
1402 int bang_end = StackShadowPages * page_size;
1403
1404 // This is how far the previous frame's stack banging extended.
1405 const int bang_end_safe = bang_end;
1406
1407 if (bangsize > page_size) {
1408 bang_end += bangsize;
1409 }
1410
1411 int bang_offset = bang_end_safe;
1412
1413 while (bang_offset <= bang_end) {
1414 // Need at least one stack bang at end of shadow zone.
1415
1416 // Again I had to copy code, this time from assembler_ppc.cpp,
1417 // bang_stack_with_offset - see there for comments.
1418
1419 // Stack grows down, caller passes positive offset.
1420 assert(bang_offset > 0, "must bang with positive offset");
1421
1422 long stdoffset = -bang_offset;
1423
1424 if (Assembler::is_simm(stdoffset, 16)) {
1425 // Signed 16 bit offset, a simple std is ok.
1426 if (UseLoadInstructionsForStackBangingPPC64) {
1427 ___(ld) ld(R0, (int)(signed short)stdoffset, R1_SP);
1428 } else {
1429 ___(std) std(R0, (int)(signed short)stdoffset, R1_SP);
1430 }
1431 } else if (Assembler::is_simm(stdoffset, 31)) {
1432 // Use largeoffset calculations for addis & ld/std.
1433 const int hi = MacroAssembler::largeoffset_si16_si16_hi(stdoffset);
1434 const int lo = MacroAssembler::largeoffset_si16_si16_lo(stdoffset);
1435
1436 Register tmp = R11;
1437 ___(addis) addis(tmp, R1_SP, hi);
1438 if (UseLoadInstructionsForStackBangingPPC64) {
1439 ___(ld) ld(R0, lo, tmp);
1440 } else {
1441 ___(std) std(R0, lo, tmp);
1442 }
1443 } else {
1444 ShouldNotReachHere();
1445 }
1446
1447 bang_offset += page_size;
1448 }
1449 // R11 trashed
1450 } // C->need_stack_bang(framesize) && UseStackBanging
1451
1452 unsigned int bytes = (unsigned int)framesize;
1453 long offset = Assembler::align_addr(bytes, frame::alignment_in_bytes);
1454 ciMethod *currMethod = C->method();
1455
1456 // Optimized version for most common case.
1457 if (UsePower6SchedulerPPC64 &&
1458 !method_is_frameless && Assembler::is_simm((int)(-offset), 16) &&
1459 !(false /* ConstantsALot TODO: PPC port*/)) {
1460 ___(or) mr(callers_sp, R1_SP);
1461 ___(std) std(return_pc, _abi(lr), R1_SP);
1462 ___(stdu) stdu(R1_SP, -offset, R1_SP);
1463 return;
1464 }
1465
1466 if (!method_is_frameless) {
1467 // Get callers sp.
1468 ___(or) mr(callers_sp, R1_SP);
1469
1470 // Push method's frame, modifies SP.
1471 assert(Assembler::is_uimm(framesize, 32U), "wrong type");
1472 // The ABI is already accounted for in 'framesize' via the
1473 // 'out_preserve' area.
1474 Register tmp = push_frame_temp;
1475 // Had to insert code of push_frame((unsigned int)framesize, push_frame_temp).
1476 if (Assembler::is_simm(-offset, 16)) {
1477 ___(stdu) stdu(R1_SP, -offset, R1_SP);
1478 } else {
1479 long x = -offset;
1480 // Had to insert load_const(tmp, -offset).
1481 ___(addis) lis( tmp, (int)((signed short)(((x >> 32) & 0xffff0000) >> 16)));
1482 ___(ori) ori( tmp, tmp, ((x >> 32) & 0x0000ffff));
1483 ___(rldicr) sldi(tmp, tmp, 32);
1484 ___(oris) oris(tmp, tmp, (x & 0xffff0000) >> 16);
1485 ___(ori) ori( tmp, tmp, (x & 0x0000ffff));
1486
1487 ___(stdux) stdux(R1_SP, R1_SP, tmp);
1488 }
1489 }
1490 #if 0 // TODO: PPC port
1491 // For testing large constant pools, emit a lot of constants to constant pool.
1492 // "Randomize" const_size.
1493 if (ConstantsALot) {
1494 const int num_consts = const_size();
1495 for (int i = 0; i < num_consts; i++) {
1496 __ long_constant(0xB0B5B00BBABE);
1497 }
1498 }
1499 #endif
1500 if (!method_is_frameless) {
1501 // Save return pc.
1502 ___(std) std(return_pc, _abi(lr), callers_sp);
1503 }
1504 }
1505 #undef ___
1506 #undef ___stop
1507 #undef ___advance
1508
1509 uint MachPrologNode::size(PhaseRegAlloc *ra_) const {
1510 // Variable size. determine dynamically.
1511 return MachNode::size(ra_);
1512 }
1513
1514 int MachPrologNode::reloc() const {
1515 // Return number of relocatable values contained in this instruction.
1516 return 1; // 1 reloc entry for load_const(toc).
1517 }
1518
1519 //=============================================================================
1520
1521 #ifndef PRODUCT
1522 void MachEpilogNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1523 Compile* C = ra_->C;
1524
1525 st->print("EPILOG\n\t");
1526 st->print("restore return pc\n\t");
1527 st->print("pop frame\n\t");
1528
1529 if (do_polling() && C->is_method_compilation()) {
1530 st->print("touch polling page\n\t");
1531 }
1532 }
1533 #endif
1534
1535 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1536 Compile* C = ra_->C;
1537 MacroAssembler _masm(&cbuf);
1538
1539 const long framesize = ((long)C->frame_slots()) << LogBytesPerInt;
1540 assert(framesize >= 0, "negative frame-size?");
1541
1542 const bool method_needs_polling = do_polling() && C->is_method_compilation();
1543 const bool method_is_frameless = false /* TODO: PPC port C->is_frameless_method()*/;
1544 const Register return_pc = R11;
1545 const Register polling_page = R12;
1546
1547 if (!method_is_frameless) {
1548 // Restore return pc relative to callers' sp.
1549 __ ld(return_pc, ((int)framesize) + _abi(lr), R1_SP);
1550 }
1551
1552 if (method_needs_polling) {
1553 if (LoadPollAddressFromThread) {
1554 // TODO: PPC port __ ld(polling_page, in_bytes(JavaThread::poll_address_offset()), R16_thread);
1555 Unimplemented();
1556 } else {
1557 __ load_const_optimized(polling_page, (long)(address) os::get_polling_page()); // TODO: PPC port: get_standard_polling_page()
1558 }
1559 }
1560
1561 if (!method_is_frameless) {
1562 // Move return pc to LR.
1563 __ mtlr(return_pc);
1564 // Pop frame (fixed frame-size).
1565 __ addi(R1_SP, R1_SP, (int)framesize);
1566 }
1567
1568 if (method_needs_polling) {
1569 // We need to mark the code position where the load from the safepoint
1570 // polling page was emitted as relocInfo::poll_return_type here.
1571 __ relocate(relocInfo::poll_return_type);
1572 __ load_from_polling_page(polling_page);
1573 }
1574 }
1575
1576 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const {
1577 // Variable size. Determine dynamically.
1578 return MachNode::size(ra_);
1579 }
1580
1581 int MachEpilogNode::reloc() const {
1582 // Return number of relocatable values contained in this instruction.
1583 return 1; // 1 for load_from_polling_page.
1584 }
1585
1586 const Pipeline * MachEpilogNode::pipeline() const {
1587 return MachNode::pipeline_class();
1588 }
1589
1590 // This method seems to be obsolete. It is declared in machnode.hpp
1591 // and defined in all *.ad files, but it is never called. Should we
1592 // get rid of it?
1593 int MachEpilogNode::safepoint_offset() const {
1594 assert(do_polling(), "no return for this epilog node");
1595 return 0;
1596 }
1597
1598 #if 0 // TODO: PPC port
1599 void MachLoadPollAddrLateNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
1600 MacroAssembler _masm(&cbuf);
1601 if (LoadPollAddressFromThread) {
1602 _masm.ld(R11, in_bytes(JavaThread::poll_address_offset()), R16_thread);
1603 } else {
1604 _masm.nop();
1605 }
1606 }
1607
1608 uint MachLoadPollAddrLateNode::size(PhaseRegAlloc* ra_) const {
1609 if (LoadPollAddressFromThread) {
1610 return 4;
1611 } else {
1612 return 4;
1613 }
1614 }
1615
1616 #ifndef PRODUCT
1617 void MachLoadPollAddrLateNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
1618 st->print_cr(" LD R11, PollAddressOffset, R16_thread \t// LoadPollAddressFromThread");
1619 }
1620 #endif
1621
1622 const RegMask &MachLoadPollAddrLateNode::out_RegMask() const {
1623 return RSCRATCH1_BITS64_REG_mask();
1624 }
1625 #endif // PPC port
1626
1627 // =============================================================================
1628
1629 // Figure out which register class each belongs in: rc_int, rc_float or
1630 // rc_stack.
1631 enum RC { rc_bad, rc_int, rc_float, rc_stack };
1632
1633 static enum RC rc_class(OptoReg::Name reg) {
1634 // Return the register class for the given register. The given register
1635 // reg is a <register>_num value, which is an index into the MachRegisterNumbers
1636 // enumeration in adGlobals_ppc64.hpp.
1637
1638 if (reg == OptoReg::Bad) return rc_bad;
1639
1640 // We have 64 integer register halves, starting at index 0.
1641 if (reg < 64) return rc_int;
1642
1643 // We have 64 floating-point register halves, starting at index 64.
1644 if (reg < 64+64) return rc_float;
1645
1646 // Between float regs & stack are the flags regs.
1647 assert(OptoReg::is_stack(reg), "blow up if spilling flags");
1648
1649 return rc_stack;
1650 }
1651
1652 static int ld_st_helper(CodeBuffer *cbuf, const char *op_str, uint opcode, int reg, int offset,
1653 bool do_print, Compile* C, outputStream *st) {
1654
1655 assert(opcode == Assembler::LD_OPCODE ||
1656 opcode == Assembler::STD_OPCODE ||
1657 opcode == Assembler::LWZ_OPCODE ||
1658 opcode == Assembler::STW_OPCODE ||
1659 opcode == Assembler::LFD_OPCODE ||
1660 opcode == Assembler::STFD_OPCODE ||
1661 opcode == Assembler::LFS_OPCODE ||
1662 opcode == Assembler::STFS_OPCODE,
1663 "opcode not supported");
1664
1665 if (cbuf) {
1666 int d =
1667 (Assembler::LD_OPCODE == opcode || Assembler::STD_OPCODE == opcode) ?
1668 Assembler::ds(offset+0 /* TODO: PPC port C->frame_slots_sp_bias_in_bytes()*/)
1669 : Assembler::d1(offset+0 /* TODO: PPC port C->frame_slots_sp_bias_in_bytes()*/); // Makes no difference in opt build.
1670 emit_long(*cbuf, opcode | Assembler::rt(Matcher::_regEncode[reg]) | d | Assembler::ra(R1_SP));
1671 }
1672 #ifndef PRODUCT
1673 else if (do_print) {
1674 st->print("%-7s %s, [R1_SP + #%d+%d] \t// spill copy",
1675 op_str,
1676 Matcher::regName[reg],
1677 offset, 0 /* TODO: PPC port C->frame_slots_sp_bias_in_bytes()*/);
1678 }
1679 #endif
1680 return 4; // size
1681 }
1682
1683 uint MachSpillCopyNode::implementation(CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, outputStream *st) const {
1684 Compile* C = ra_->C;
1685
1686 // Get registers to move.
1687 OptoReg::Name src_hi = ra_->get_reg_second(in(1));
1688 OptoReg::Name src_lo = ra_->get_reg_first(in(1));
1689 OptoReg::Name dst_hi = ra_->get_reg_second(this);
1690 OptoReg::Name dst_lo = ra_->get_reg_first(this);
1691
1692 enum RC src_hi_rc = rc_class(src_hi);
1693 enum RC src_lo_rc = rc_class(src_lo);
1694 enum RC dst_hi_rc = rc_class(dst_hi);
1695 enum RC dst_lo_rc = rc_class(dst_lo);
1696
1697 assert(src_lo != OptoReg::Bad && dst_lo != OptoReg::Bad, "must move at least 1 register");
1698 if (src_hi != OptoReg::Bad)
1699 assert((src_lo&1)==0 && src_lo+1==src_hi &&
1700 (dst_lo&1)==0 && dst_lo+1==dst_hi,
1701 "expected aligned-adjacent pairs");
1702 // Generate spill code!
1703 int size = 0;
1704
1705 if (src_lo == dst_lo && src_hi == dst_hi)
1706 return size; // Self copy, no move.
1707
1708 // --------------------------------------
1709 // Memory->Memory Spill. Use R0 to hold the value.
1710 if (src_lo_rc == rc_stack && dst_lo_rc == rc_stack) {
1711 int src_offset = ra_->reg2offset(src_lo);
1712 int dst_offset = ra_->reg2offset(dst_lo);
1713 if (src_hi != OptoReg::Bad) {
1714 assert(src_hi_rc==rc_stack && dst_hi_rc==rc_stack,
1715 "expected same type of move for high parts");
1716 size += ld_st_helper(cbuf, "LD ", Assembler::LD_OPCODE, R0_num, src_offset, !do_size, C, st);
1717 if (!cbuf && !do_size) st->print("\n\t");
1718 size += ld_st_helper(cbuf, "STD ", Assembler::STD_OPCODE, R0_num, dst_offset, !do_size, C, st);
1719 } else {
1720 size += ld_st_helper(cbuf, "LWZ ", Assembler::LWZ_OPCODE, R0_num, src_offset, !do_size, C, st);
1721 if (!cbuf && !do_size) st->print("\n\t");
1722 size += ld_st_helper(cbuf, "STW ", Assembler::STW_OPCODE, R0_num, dst_offset, !do_size, C, st);
1723 }
1724 return size;
1725 }
1726
1727 // --------------------------------------
1728 // Check for float->int copy; requires a trip through memory.
1729 if (src_lo_rc == rc_float && dst_lo_rc == rc_int) {
1730 Unimplemented();
1731 }
1732
1733 // --------------------------------------
1734 // Check for integer reg-reg copy.
1735 if (src_lo_rc == rc_int && dst_lo_rc == rc_int) {
1736 Register Rsrc = as_Register(Matcher::_regEncode[src_lo]);
1737 Register Rdst = as_Register(Matcher::_regEncode[dst_lo]);
1738 size = (Rsrc != Rdst) ? 4 : 0;
1739
1740 if (cbuf) {
1741 MacroAssembler _masm(cbuf);
1742 if (size) {
1743 __ mr(Rdst, Rsrc);
1744 }
1745 }
1746 #ifndef PRODUCT
1747 else if (!do_size) {
1748 if (size) {
1749 st->print("%-7s %s, %s \t// spill copy", "MR", Matcher::regName[dst_lo], Matcher::regName[src_lo]);
1750 } else {
1751 st->print("%-7s %s, %s \t// spill copy", "MR-NOP", Matcher::regName[dst_lo], Matcher::regName[src_lo]);
1752 }
1753 }
1754 #endif
1755 return size;
1756 }
1757
1758 // Check for integer store.
1759 if (src_lo_rc == rc_int && dst_lo_rc == rc_stack) {
1760 int dst_offset = ra_->reg2offset(dst_lo);
1761 if (src_hi != OptoReg::Bad) {
1762 assert(src_hi_rc==rc_int && dst_hi_rc==rc_stack,
1763 "expected same type of move for high parts");
1764 size += ld_st_helper(cbuf, "STD ", Assembler::STD_OPCODE, src_lo, dst_offset, !do_size, C, st);
1765 } else {
1766 size += ld_st_helper(cbuf, "STW ", Assembler::STW_OPCODE, src_lo, dst_offset, !do_size, C, st);
1767 }
1768 return size;
1769 }
1770
1771 // Check for integer load.
1772 if (dst_lo_rc == rc_int && src_lo_rc == rc_stack) {
1773 int src_offset = ra_->reg2offset(src_lo);
1774 if (src_hi != OptoReg::Bad) {
1775 assert(dst_hi_rc==rc_int && src_hi_rc==rc_stack,
1776 "expected same type of move for high parts");
1777 size += ld_st_helper(cbuf, "LD ", Assembler::LD_OPCODE, dst_lo, src_offset, !do_size, C, st);
1778 } else {
1779 size += ld_st_helper(cbuf, "LWZ ", Assembler::LWZ_OPCODE, dst_lo, src_offset, !do_size, C, st);
1780 }
1781 return size;
1782 }
1783
1784 // Check for float reg-reg copy.
1785 if (src_lo_rc == rc_float && dst_lo_rc == rc_float) {
1786 if (cbuf) {
1787 MacroAssembler _masm(cbuf);
1788 FloatRegister Rsrc = as_FloatRegister(Matcher::_regEncode[src_lo]);
1789 FloatRegister Rdst = as_FloatRegister(Matcher::_regEncode[dst_lo]);
1790 __ fmr(Rdst, Rsrc);
1791 }
1792 #ifndef PRODUCT
1793 else if (!do_size) {
1794 st->print("%-7s %s, %s \t// spill copy", "FMR", Matcher::regName[dst_lo], Matcher::regName[src_lo]);
1795 }
1796 #endif
1797 return 4;
1798 }
1799
1800 // Check for float store.
1801 if (src_lo_rc == rc_float && dst_lo_rc == rc_stack) {
1802 int dst_offset = ra_->reg2offset(dst_lo);
1803 if (src_hi != OptoReg::Bad) {
1804 assert(src_hi_rc==rc_float && dst_hi_rc==rc_stack,
1805 "expected same type of move for high parts");
1806 size += ld_st_helper(cbuf, "STFD", Assembler::STFD_OPCODE, src_lo, dst_offset, !do_size, C, st);
1807 } else {
1808 size += ld_st_helper(cbuf, "STFS", Assembler::STFS_OPCODE, src_lo, dst_offset, !do_size, C, st);
1809 }
1810 return size;
1811 }
1812
1813 // Check for float load.
1814 if (dst_lo_rc == rc_float && src_lo_rc == rc_stack) {
1815 int src_offset = ra_->reg2offset(src_lo);
1816 if (src_hi != OptoReg::Bad) {
1817 assert(dst_hi_rc==rc_float && src_hi_rc==rc_stack,
1818 "expected same type of move for high parts");
1819 size += ld_st_helper(cbuf, "LFD ", Assembler::LFD_OPCODE, dst_lo, src_offset, !do_size, C, st);
1820 } else {
1821 size += ld_st_helper(cbuf, "LFS ", Assembler::LFS_OPCODE, dst_lo, src_offset, !do_size, C, st);
1822 }
1823 return size;
1824 }
1825
1826 // --------------------------------------------------------------------
1827 // Check for hi bits still needing moving. Only happens for misaligned
1828 // arguments to native calls.
1829 if (src_hi == dst_hi)
1830 return size; // Self copy; no move.
1831
1832 assert(src_hi_rc != rc_bad && dst_hi_rc != rc_bad, "src_hi & dst_hi cannot be Bad");
1833 ShouldNotReachHere(); // Unimplemented
1834 return 0;
1835 }
1836
1837 #ifndef PRODUCT
1838 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1839 if (!ra_)
1840 st->print("N%d = SpillCopy(N%d)", _idx, in(1)->_idx);
1841 else
1842 implementation(NULL, ra_, false, st);
1843 }
1844 #endif
1845
1846 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1847 implementation(&cbuf, ra_, false, NULL);
1848 }
1849
1850 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1851 return implementation(NULL, ra_, true, NULL);
1852 }
1853
1854 #if 0 // TODO: PPC port
1855 ArchOpcode MachSpillCopyNode_archOpcode(MachSpillCopyNode *n, PhaseRegAlloc *ra_) {
1856 #ifndef PRODUCT
1857 if (ra_->node_regs_max_index() == 0) return archOpcode_undefined;
1858 #endif
1859 assert(ra_->node_regs_max_index() != 0, "");
1860
1861 // Get registers to move.
1862 OptoReg::Name src_hi = ra_->get_reg_second(n->in(1));
1863 OptoReg::Name src_lo = ra_->get_reg_first(n->in(1));
1864 OptoReg::Name dst_hi = ra_->get_reg_second(n);
1865 OptoReg::Name dst_lo = ra_->get_reg_first(n);
1866
1867 enum RC src_lo_rc = rc_class(src_lo);
1868 enum RC dst_lo_rc = rc_class(dst_lo);
1869
1870 if (src_lo == dst_lo && src_hi == dst_hi)
1871 return ppc64Opcode_none; // Self copy, no move.
1872
1873 // --------------------------------------
1874 // Memory->Memory Spill. Use R0 to hold the value.
1875 if (src_lo_rc == rc_stack && dst_lo_rc == rc_stack) {
1876 return ppc64Opcode_compound;
1877 }
1878
1879 // --------------------------------------
1880 // Check for float->int copy; requires a trip through memory.
1881 if (src_lo_rc == rc_float && dst_lo_rc == rc_int) {
1882 Unimplemented();
1883 }
1884
1885 // --------------------------------------
1886 // Check for integer reg-reg copy.
1887 if (src_lo_rc == rc_int && dst_lo_rc == rc_int) {
1888 Register Rsrc = as_Register(Matcher::_regEncode[src_lo]);
1889 Register Rdst = as_Register(Matcher::_regEncode[dst_lo]);
1890 if (Rsrc == Rdst) {
1891 return ppc64Opcode_none;
1892 } else {
1893 return ppc64Opcode_or;
1894 }
1895 }
1896
1897 // Check for integer store.
1898 if (src_lo_rc == rc_int && dst_lo_rc == rc_stack) {
1899 if (src_hi != OptoReg::Bad) {
1900 return ppc64Opcode_std;
1901 } else {
1902 return ppc64Opcode_stw;
1903 }
1904 }
1905
1906 // Check for integer load.
1907 if (dst_lo_rc == rc_int && src_lo_rc == rc_stack) {
1908 if (src_hi != OptoReg::Bad) {
1909 return ppc64Opcode_ld;
1910 } else {
1911 return ppc64Opcode_lwz;
1912 }
1913 }
1914
1915 // Check for float reg-reg copy.
1916 if (src_lo_rc == rc_float && dst_lo_rc == rc_float) {
1917 return ppc64Opcode_fmr;
1918 }
1919
1920 // Check for float store.
1921 if (src_lo_rc == rc_float && dst_lo_rc == rc_stack) {
1922 if (src_hi != OptoReg::Bad) {
1923 return ppc64Opcode_stfd;
1924 } else {
1925 return ppc64Opcode_stfs;
1926 }
1927 }
1928
1929 // Check for float load.
1930 if (dst_lo_rc == rc_float && src_lo_rc == rc_stack) {
1931 if (src_hi != OptoReg::Bad) {
1932 return ppc64Opcode_lfd;
1933 } else {
1934 return ppc64Opcode_lfs;
1935 }
1936 }
1937
1938 // --------------------------------------------------------------------
1939 // Check for hi bits still needing moving. Only happens for misaligned
1940 // arguments to native calls.
1941 if (src_hi == dst_hi) {
1942 return ppc64Opcode_none; // Self copy; no move.
1943 }
1944
1945 ShouldNotReachHere();
1946 return ppc64Opcode_undefined;
1947 }
1948 #endif // PPC port
1949
1950 #ifndef PRODUCT
1951 void MachNopNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1952 st->print("NOP \t// %d nops to pad for loops.", _count);
1953 }
1954 #endif
1955
1956 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *) const {
1957 MacroAssembler _masm(&cbuf);
1958 // _count contains the number of nops needed for padding.
1959 for (int i = 0; i < _count; i++) {
1960 __ nop();
1961 }
1962 }
1963
1964 uint MachNopNode::size(PhaseRegAlloc *ra_) const {
1965 return _count * 4;
1966 }
1967
1968 #ifndef PRODUCT
1969 void BoxLockNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1970 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1971 char reg_str[128];
1972 ra_->dump_register(this, reg_str);
1973 st->print("ADDI %s, SP, %d \t// box node", reg_str, offset);
1974 }
1975 #endif
1976
1977 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1978 MacroAssembler _masm(&cbuf);
1979
1980 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1981 int reg = ra_->get_encode(this);
1982
1983 if (Assembler::is_simm(offset, 16)) {
1984 __ addi(as_Register(reg), R1, offset);
1985 } else {
1986 ShouldNotReachHere();
1987 }
1988 }
1989
1990 uint BoxLockNode::size(PhaseRegAlloc *ra_) const {
1991 // BoxLockNode is not a MachNode, so we can't just call MachNode::size(ra_).
1992 return 4;
1993 }
1994
1995 #ifndef PRODUCT
1996 void MachUEPNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1997 st->print_cr("---- MachUEPNode ----");
1998 st->print_cr("...");
1999 }
2000 #endif
2001
2002 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
2003 // This is the unverified entry point.
2004 MacroAssembler _masm(&cbuf);
2005
2006 // Inline_cache contains a klass.
2007 Register ic_klass = as_Register(Matcher::inline_cache_reg_encode());
2008 Register receiver_klass = R12_scratch2; // tmp
2009
2010 assert_different_registers(ic_klass, receiver_klass, R11_scratch1, R3_ARG1);
2011 assert(R11_scratch1 == R11, "need prologue scratch register");
2012
2013 // Check for NULL argument if we don't have implicit null checks.
2014 if (!ImplicitNullChecks || !os::zero_page_read_protected()) {
2015 if (TrapBasedNullChecks) {
2016 __ trap_null_check(R3_ARG1);
2017 } else {
2018 Label valid;
2019 __ cmpdi(CCR0, R3_ARG1, 0);
2020 __ bne_predict_taken(CCR0, valid);
2021 // We have a null argument, branch to ic_miss_stub.
2022 __ b64_patchable((address)SharedRuntime::get_ic_miss_stub(),
2023 relocInfo::runtime_call_type);
2024 __ bind(valid);
2025 }
2026 }
2027 // Assume argument is not NULL, load klass from receiver.
2028 __ load_klass(receiver_klass, R3_ARG1);
2029
2030 if (TrapBasedICMissChecks) {
2031 __ trap_ic_miss_check(receiver_klass, ic_klass);
2032 } else {
2033 Label valid;
2034 __ cmpd(CCR0, receiver_klass, ic_klass);
2035 __ beq_predict_taken(CCR0, valid);
2036 // We have an unexpected klass, branch to ic_miss_stub.
2037 __ b64_patchable((address)SharedRuntime::get_ic_miss_stub(),
2038 relocInfo::runtime_call_type);
2039 __ bind(valid);
2040 }
2041
2042 // Argument is valid and klass is as expected, continue.
2043 }
2044
2045 #if 0 // TODO: PPC port
2046 // Optimize UEP code on z (save a load_const() call in main path).
2047 int MachUEPNode::ep_offset() {
2048 return 0;
2049 }
2050 #endif
2051
2052 uint MachUEPNode::size(PhaseRegAlloc *ra_) const {
2053 // Variable size. Determine dynamically.
2054 return MachNode::size(ra_);
2055 }
2056
2057 //=============================================================================
2058
2059 %} // interrupt source
2060
2061 source_hpp %{ // Header information of the source block.
2062
2063 class HandlerImpl {
2064
2065 public:
2066
2067 static int emit_exception_handler(CodeBuffer &cbuf);
2068 static int emit_deopt_handler(CodeBuffer& cbuf);
2069
2070 static uint size_exception_handler() {
2071 // The exception_handler is a b64_patchable.
2072 return MacroAssembler::b64_patchable_size;
2073 }
2074
2075 static uint size_deopt_handler() {
2076 // The deopt_handler is a bl64_patchable.
2077 return MacroAssembler::bl64_patchable_size;
2078 }
2079
2080 };
2081
2082 %} // end source_hpp
2083
2084 source %{
2085
2086 int HandlerImpl::emit_exception_handler(CodeBuffer &cbuf) {
2087 MacroAssembler _masm(&cbuf);
2088
2089 address base = __ start_a_stub(size_exception_handler());
2090 if (base == NULL) return 0; // CodeBuffer::expand failed
2091
2092 int offset = __ offset();
2093 __ b64_patchable((address)OptoRuntime::exception_blob()->content_begin(),
2094 relocInfo::runtime_call_type);
2095 assert(__ offset() - offset == (int)size_exception_handler(), "must be fixed size");
2096 __ end_a_stub();
2097
2098 return offset;
2099 }
2100
2101 // The deopt_handler is like the exception handler, but it calls to
2102 // the deoptimization blob instead of jumping to the exception blob.
2103 int HandlerImpl::emit_deopt_handler(CodeBuffer& cbuf) {
2104 MacroAssembler _masm(&cbuf);
2105
2106 address base = __ start_a_stub(size_deopt_handler());
2107 if (base == NULL) return 0; // CodeBuffer::expand failed
2108
2109 int offset = __ offset();
2110 __ bl64_patchable((address)SharedRuntime::deopt_blob()->unpack(),
2111 relocInfo::runtime_call_type);
2112 assert(__ offset() - offset == (int) size_deopt_handler(), "must be fixed size");
2113 __ end_a_stub();
2114
2115 return offset;
2116 }
2117
2118 //=============================================================================
2119
2120 // Use a frame slots bias for frameless methods if accessing the stack.
2121 static int frame_slots_bias(int reg_enc, PhaseRegAlloc* ra_) {
2122 if (as_Register(reg_enc) == R1_SP) {
2123 return 0; // TODO: PPC port ra_->C->frame_slots_sp_bias_in_bytes();
2124 }
2125 return 0;
2126 }
2127
2128 const bool Matcher::match_rule_supported(int opcode) {
2129 if (!has_match_rule(opcode))
2130 return false;
2131
2132 switch (opcode) {
2133 case Op_SqrtD:
2134 return VM_Version::has_fsqrt();
2135 case Op_CountLeadingZerosI:
2136 case Op_CountLeadingZerosL:
2137 case Op_CountTrailingZerosI:
2138 case Op_CountTrailingZerosL:
2139 if (!UseCountLeadingZerosInstructionsPPC64)
2140 return false;
2141 break;
2142
2143 case Op_PopCountI:
2144 case Op_PopCountL:
2145 return (UsePopCountInstruction && VM_Version::has_popcntw());
2146
2147 case Op_StrComp:
2148 return SpecialStringCompareTo;
2149 case Op_StrEquals:
2150 return SpecialStringEquals;
2151 case Op_StrIndexOf:
2152 return SpecialStringIndexOf;
2153 }
2154
2155 return true; // Per default match rules are supported.
2156 }
2157
2158 int Matcher::regnum_to_fpu_offset(int regnum) {
2159 // No user for this method?
2160 Unimplemented();
2161 return 999;
2162 }
2163
2164 const bool Matcher::convL2FSupported(void) {
2165 // fcfids can do the conversion (>= Power7).
2166 // fcfid + frsp showed rounding problem when result should be 0x3f800001.
2167 return VM_Version::has_fcfids(); // False means that conversion is done by runtime call.
2168 }
2169
2170 // Vector width in bytes.
2171 const int Matcher::vector_width_in_bytes(BasicType bt) {
2172 assert(MaxVectorSize == 8, "");
2173 return 8;
2174 }
2175
2176 // Vector ideal reg.
2177 const int Matcher::vector_ideal_reg(int size) {
2178 assert(MaxVectorSize == 8 && size == 8, "");
2179 return Op_RegL;
2180 }
2181
2182 const int Matcher::vector_shift_count_ideal_reg(int size) {
2183 fatal("vector shift is not supported");
2184 return Node::NotAMachineReg;
2185 }
2186
2187 // Limits on vector size (number of elements) loaded into vector.
2188 const int Matcher::max_vector_size(const BasicType bt) {
2189 assert(is_java_primitive(bt), "only primitive type vectors");
2190 return vector_width_in_bytes(bt)/type2aelembytes(bt);
2191 }
2192
2193 const int Matcher::min_vector_size(const BasicType bt) {
2194 return max_vector_size(bt); // Same as max.
2195 }
2196
2197 // PPC doesn't support misaligned vectors store/load.
2198 const bool Matcher::misaligned_vectors_ok() {
2199 return false;
2200 }
2201
2202 // PPC AES support not yet implemented
2203 const bool Matcher::pass_original_key_for_aes() {
2204 return false;
2205 }
2206
2207 // RETURNS: whether this branch offset is short enough that a short
2208 // branch can be used.
2209 //
2210 // If the platform does not provide any short branch variants, then
2211 // this method should return `false' for offset 0.
2212 //
2213 // `Compile::Fill_buffer' will decide on basis of this information
2214 // whether to do the pass `Compile::Shorten_branches' at all.
2215 //
2216 // And `Compile::Shorten_branches' will decide on basis of this
2217 // information whether to replace particular branch sites by short
2218 // ones.
2219 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
2220 // Is the offset within the range of a ppc64 pc relative branch?
2221 bool b;
2222
2223 const int safety_zone = 3 * BytesPerInstWord;
2224 b = Assembler::is_simm((offset<0 ? offset-safety_zone : offset+safety_zone),
2225 29 - 16 + 1 + 2);
2226 return b;
2227 }
2228
2229 const bool Matcher::isSimpleConstant64(jlong value) {
2230 // Probably always true, even if a temp register is required.
2231 return true;
2232 }
2233 /* TODO: PPC port
2234 // Make a new machine dependent decode node (with its operands).
2235 MachTypeNode *Matcher::make_decode_node(Compile *C) {
2236 assert(Universe::narrow_oop_base() == NULL && Universe::narrow_oop_shift() == 0,
2237 "This method is only implemented for unscaled cOops mode so far");
2238 MachTypeNode *decode = new (C) decodeN_unscaledNode();
2239 decode->set_opnd_array(0, new (C) iRegPdstOper());
2240 decode->set_opnd_array(1, new (C) iRegNsrcOper());
2241 return decode;
2242 }
2243 */
2244 // Threshold size for cleararray.
2245 const int Matcher::init_array_short_size = 8 * BytesPerLong;
2246
2247 // false => size gets scaled to BytesPerLong, ok.
2248 const bool Matcher::init_array_count_is_in_bytes = false;
2249
2250 // Use conditional move (CMOVL) on Power7.
2251 const int Matcher::long_cmove_cost() { return 0; } // this only makes long cmoves more expensive than int cmoves
2252
2253 // Suppress CMOVF. Conditional move available (sort of) on PPC64 only from P7 onwards. Not exploited yet.
2254 // fsel doesn't accept a condition register as input, so this would be slightly different.
2255 const int Matcher::float_cmove_cost() { return ConditionalMoveLimit; }
2256
2257 // Power6 requires postalloc expand (see block.cpp for description of postalloc expand).
2258 const bool Matcher::require_postalloc_expand = true;
2259
2260 // Should the Matcher clone shifts on addressing modes, expecting them to
2261 // be subsumed into complex addressing expressions or compute them into
2262 // registers? True for Intel but false for most RISCs.
2263 const bool Matcher::clone_shift_expressions = false;
2264
2265 // Do we need to mask the count passed to shift instructions or does
2266 // the cpu only look at the lower 5/6 bits anyway?
2267 // PowerPC requires masked shift counts.
2268 const bool Matcher::need_masked_shift_count = true;
2269
2270 // This affects two different things:
2271 // - how Decode nodes are matched
2272 // - how ImplicitNullCheck opportunities are recognized
2273 // If true, the matcher will try to remove all Decodes and match them
2274 // (as operands) into nodes. NullChecks are not prepared to deal with
2275 // Decodes by final_graph_reshaping().
2276 // If false, final_graph_reshaping() forces the decode behind the Cmp
2277 // for a NullCheck. The matcher matches the Decode node into a register.
2278 // Implicit_null_check optimization moves the Decode along with the
2279 // memory operation back up before the NullCheck.
2280 bool Matcher::narrow_oop_use_complex_address() {
2281 // TODO: PPC port if (MatchDecodeNodes) return true;
2282 return false;
2283 }
2284
2285 bool Matcher::narrow_klass_use_complex_address() {
2286 NOT_LP64(ShouldNotCallThis());
2287 assert(UseCompressedClassPointers, "only for compressed klass code");
2288 // TODO: PPC port if (MatchDecodeNodes) return true;
2289 return false;
2290 }
2291
2292 // Is it better to copy float constants, or load them directly from memory?
2293 // Intel can load a float constant from a direct address, requiring no
2294 // extra registers. Most RISCs will have to materialize an address into a
2295 // register first, so they would do better to copy the constant from stack.
2296 const bool Matcher::rematerialize_float_constants = false;
2297
2298 // If CPU can load and store mis-aligned doubles directly then no fixup is
2299 // needed. Else we split the double into 2 integer pieces and move it
2300 // piece-by-piece. Only happens when passing doubles into C code as the
2301 // Java calling convention forces doubles to be aligned.
2302 const bool Matcher::misaligned_doubles_ok = true;
2303
2304 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {
2305 Unimplemented();
2306 }
2307
2308 // Advertise here if the CPU requires explicit rounding operations
2309 // to implement the UseStrictFP mode.
2310 const bool Matcher::strict_fp_requires_explicit_rounding = false;
2311
2312 // Do floats take an entire double register or just half?
2313 //
2314 // A float occupies a ppc64 double register. For the allocator, a
2315 // ppc64 double register appears as a pair of float registers.
2316 bool Matcher::float_in_double() { return true; }
2317
2318 // Do ints take an entire long register or just half?
2319 // The relevant question is how the int is callee-saved:
2320 // the whole long is written but de-opt'ing will have to extract
2321 // the relevant 32 bits.
2322 const bool Matcher::int_in_long = true;
2323
2324 // Constants for c2c and c calling conventions.
2325
2326 const MachRegisterNumbers iarg_reg[8] = {
2327 R3_num, R4_num, R5_num, R6_num,
2328 R7_num, R8_num, R9_num, R10_num
2329 };
2330
2331 const MachRegisterNumbers farg_reg[13] = {
2332 F1_num, F2_num, F3_num, F4_num,
2333 F5_num, F6_num, F7_num, F8_num,
2334 F9_num, F10_num, F11_num, F12_num,
2335 F13_num
2336 };
2337
2338 const int num_iarg_registers = sizeof(iarg_reg) / sizeof(iarg_reg[0]);
2339
2340 const int num_farg_registers = sizeof(farg_reg) / sizeof(farg_reg[0]);
2341
2342 // Return whether or not this register is ever used as an argument. This
2343 // function is used on startup to build the trampoline stubs in generateOptoStub.
2344 // Registers not mentioned will be killed by the VM call in the trampoline, and
2345 // arguments in those registers not be available to the callee.
2346 bool Matcher::can_be_java_arg(int reg) {
2347 // We return true for all registers contained in iarg_reg[] and
2348 // farg_reg[] and their virtual halves.
2349 // We must include the virtual halves in order to get STDs and LDs
2350 // instead of STWs and LWs in the trampoline stubs.
2351
2352 if ( reg == R3_num || reg == R3_H_num
2353 || reg == R4_num || reg == R4_H_num
2354 || reg == R5_num || reg == R5_H_num
2355 || reg == R6_num || reg == R6_H_num
2356 || reg == R7_num || reg == R7_H_num
2357 || reg == R8_num || reg == R8_H_num
2358 || reg == R9_num || reg == R9_H_num
2359 || reg == R10_num || reg == R10_H_num)
2360 return true;
2361
2362 if ( reg == F1_num || reg == F1_H_num
2363 || reg == F2_num || reg == F2_H_num
2364 || reg == F3_num || reg == F3_H_num
2365 || reg == F4_num || reg == F4_H_num
2366 || reg == F5_num || reg == F5_H_num
2367 || reg == F6_num || reg == F6_H_num
2368 || reg == F7_num || reg == F7_H_num
2369 || reg == F8_num || reg == F8_H_num
2370 || reg == F9_num || reg == F9_H_num
2371 || reg == F10_num || reg == F10_H_num
2372 || reg == F11_num || reg == F11_H_num
2373 || reg == F12_num || reg == F12_H_num
2374 || reg == F13_num || reg == F13_H_num)
2375 return true;
2376
2377 return false;
2378 }
2379
2380 bool Matcher::is_spillable_arg(int reg) {
2381 return can_be_java_arg(reg);
2382 }
2383
2384 bool Matcher::use_asm_for_ldiv_by_con(jlong divisor) {
2385 return false;
2386 }
2387
2388 // Register for DIVI projection of divmodI.
2389 RegMask Matcher::divI_proj_mask() {
2390 ShouldNotReachHere();
2391 return RegMask();
2392 }
2393
2394 // Register for MODI projection of divmodI.
2395 RegMask Matcher::modI_proj_mask() {
2396 ShouldNotReachHere();
2397 return RegMask();
2398 }
2399
2400 // Register for DIVL projection of divmodL.
2401 RegMask Matcher::divL_proj_mask() {
2402 ShouldNotReachHere();
2403 return RegMask();
2404 }
2405
2406 // Register for MODL projection of divmodL.
2407 RegMask Matcher::modL_proj_mask() {
2408 ShouldNotReachHere();
2409 return RegMask();
2410 }
2411
2412 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
2413 return RegMask();
2414 }
2415
2416 %}
2417
2418 //----------ENCODING BLOCK-----------------------------------------------------
2419 // This block specifies the encoding classes used by the compiler to output
2420 // byte streams. Encoding classes are parameterized macros used by
2421 // Machine Instruction Nodes in order to generate the bit encoding of the
2422 // instruction. Operands specify their base encoding interface with the
2423 // interface keyword. There are currently supported four interfaces,
2424 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an
2425 // operand to generate a function which returns its register number when
2426 // queried. CONST_INTER causes an operand to generate a function which
2427 // returns the value of the constant when queried. MEMORY_INTER causes an
2428 // operand to generate four functions which return the Base Register, the
2429 // Index Register, the Scale Value, and the Offset Value of the operand when
2430 // queried. COND_INTER causes an operand to generate six functions which
2431 // return the encoding code (ie - encoding bits for the instruction)
2432 // associated with each basic boolean condition for a conditional instruction.
2433 //
2434 // Instructions specify two basic values for encoding. Again, a function
2435 // is available to check if the constant displacement is an oop. They use the
2436 // ins_encode keyword to specify their encoding classes (which must be
2437 // a sequence of enc_class names, and their parameters, specified in
2438 // the encoding block), and they use the
2439 // opcode keyword to specify, in order, their primary, secondary, and
2440 // tertiary opcode. Only the opcode sections which a particular instruction
2441 // needs for encoding need to be specified.
2442 encode %{
2443 enc_class enc_unimplemented %{
2444 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
2445 MacroAssembler _masm(&cbuf);
2446 __ unimplemented("Unimplemented mach node encoding in AD file.", 13);
2447 %}
2448
2449 enc_class enc_untested %{
2450 #ifdef ASSERT
2451 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
2452 MacroAssembler _masm(&cbuf);
2453 __ untested("Untested mach node encoding in AD file.");
2454 #else
2455 // TODO: PPC port $archOpcode(ppc64Opcode_none);
2456 #endif
2457 %}
2458
2459 enc_class enc_lbz(iRegIdst dst, memory mem) %{
2460 // TODO: PPC port $archOpcode(ppc64Opcode_lbz);
2461 MacroAssembler _masm(&cbuf);
2462 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2463 __ lbz($dst$$Register, Idisp, $mem$$base$$Register);
2464 %}
2465
2466 // Load acquire.
2467 enc_class enc_lbz_ac(iRegIdst dst, memory mem) %{
2468 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
2469 MacroAssembler _masm(&cbuf);
2470 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2471 __ lbz($dst$$Register, Idisp, $mem$$base$$Register);
2472 __ twi_0($dst$$Register);
2473 __ isync();
2474 %}
2475
2476 enc_class enc_lhz(iRegIdst dst, memory mem) %{
2477 // TODO: PPC port $archOpcode(ppc64Opcode_lhz);
2478
2479 MacroAssembler _masm(&cbuf);
2480 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2481 __ lhz($dst$$Register, Idisp, $mem$$base$$Register);
2482 %}
2483
2484 // Load acquire.
2485 enc_class enc_lhz_ac(iRegIdst dst, memory mem) %{
2486 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
2487
2488 MacroAssembler _masm(&cbuf);
2489 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2490 __ lhz($dst$$Register, Idisp, $mem$$base$$Register);
2491 __ twi_0($dst$$Register);
2492 __ isync();
2493 %}
2494
2495 enc_class enc_lwz(iRegIdst dst, memory mem) %{
2496 // TODO: PPC port $archOpcode(ppc64Opcode_lwz);
2497
2498 MacroAssembler _masm(&cbuf);
2499 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2500 __ lwz($dst$$Register, Idisp, $mem$$base$$Register);
2501 %}
2502
2503 // Load acquire.
2504 enc_class enc_lwz_ac(iRegIdst dst, memory mem) %{
2505 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
2506
2507 MacroAssembler _masm(&cbuf);
2508 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2509 __ lwz($dst$$Register, Idisp, $mem$$base$$Register);
2510 __ twi_0($dst$$Register);
2511 __ isync();
2512 %}
2513
2514 enc_class enc_ld(iRegLdst dst, memoryAlg4 mem) %{
2515 // TODO: PPC port $archOpcode(ppc64Opcode_ld);
2516 MacroAssembler _masm(&cbuf);
2517 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2518 // Operand 'ds' requires 4-alignment.
2519 assert((Idisp & 0x3) == 0, "unaligned offset");
2520 __ ld($dst$$Register, Idisp, $mem$$base$$Register);
2521 %}
2522
2523 // Load acquire.
2524 enc_class enc_ld_ac(iRegLdst dst, memoryAlg4 mem) %{
2525 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
2526 MacroAssembler _masm(&cbuf);
2527 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2528 // Operand 'ds' requires 4-alignment.
2529 assert((Idisp & 0x3) == 0, "unaligned offset");
2530 __ ld($dst$$Register, Idisp, $mem$$base$$Register);
2531 __ twi_0($dst$$Register);
2532 __ isync();
2533 %}
2534
2535 enc_class enc_lfd(RegF dst, memory mem) %{
2536 // TODO: PPC port $archOpcode(ppc64Opcode_lfd);
2537 MacroAssembler _masm(&cbuf);
2538 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2539 __ lfd($dst$$FloatRegister, Idisp, $mem$$base$$Register);
2540 %}
2541
2542 enc_class enc_load_long_constL(iRegLdst dst, immL src, iRegLdst toc) %{
2543 // TODO: PPC port $archOpcode(ppc64Opcode_ld);
2544
2545 MacroAssembler _masm(&cbuf);
2546 int toc_offset = 0;
2547
2548 if (!ra_->C->in_scratch_emit_size()) {
2549 address const_toc_addr;
2550 // Create a non-oop constant, no relocation needed.
2551 // If it is an IC, it has a virtual_call_Relocation.
2552 const_toc_addr = __ long_constant((jlong)$src$$constant);
2553
2554 // Get the constant's TOC offset.
2555 toc_offset = __ offset_to_method_toc(const_toc_addr);
2556
2557 // Keep the current instruction offset in mind.
2558 ((loadConLNode*)this)->_cbuf_insts_offset = __ offset();
2559 }
2560
2561 __ ld($dst$$Register, toc_offset, $toc$$Register);
2562 %}
2563
2564 enc_class enc_load_long_constL_hi(iRegLdst dst, iRegLdst toc, immL src) %{
2565 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
2566
2567 MacroAssembler _masm(&cbuf);
2568
2569 if (!ra_->C->in_scratch_emit_size()) {
2570 address const_toc_addr;
2571 // Create a non-oop constant, no relocation needed.
2572 // If it is an IC, it has a virtual_call_Relocation.
2573 const_toc_addr = __ long_constant((jlong)$src$$constant);
2574
2575 // Get the constant's TOC offset.
2576 const int toc_offset = __ offset_to_method_toc(const_toc_addr);
2577 // Store the toc offset of the constant.
2578 ((loadConL_hiNode*)this)->_const_toc_offset = toc_offset;
2579
2580 // Also keep the current instruction offset in mind.
2581 ((loadConL_hiNode*)this)->_cbuf_insts_offset = __ offset();
2582 }
2583
2584 __ addis($dst$$Register, $toc$$Register, MacroAssembler::largeoffset_si16_si16_hi(_const_toc_offset));
2585 %}
2586
2587 %} // encode
2588
2589 source %{
2590
2591 typedef struct {
2592 loadConL_hiNode *_large_hi;
2593 loadConL_loNode *_large_lo;
2594 loadConLNode *_small;
2595 MachNode *_last;
2596 } loadConLNodesTuple;
2597
2598 loadConLNodesTuple loadConLNodesTuple_create(Compile *C, PhaseRegAlloc *ra_, Node *toc, immLOper *immSrc,
2599 OptoReg::Name reg_second, OptoReg::Name reg_first) {
2600 loadConLNodesTuple nodes;
2601
2602 const bool large_constant_pool = true; // TODO: PPC port C->cfg()->_consts_size > 4000;
2603 if (large_constant_pool) {
2604 // Create new nodes.
2605 loadConL_hiNode *m1 = new (C) loadConL_hiNode();
2606 loadConL_loNode *m2 = new (C) loadConL_loNode();
2607
2608 // inputs for new nodes
2609 m1->add_req(NULL, toc);
2610 m2->add_req(NULL, m1);
2611
2612 // operands for new nodes
2613 m1->_opnds[0] = new (C) iRegLdstOper(); // dst
2614 m1->_opnds[1] = immSrc; // src
2615 m1->_opnds[2] = new (C) iRegPdstOper(); // toc
2616 m2->_opnds[0] = new (C) iRegLdstOper(); // dst
2617 m2->_opnds[1] = immSrc; // src
2618 m2->_opnds[2] = new (C) iRegLdstOper(); // base
2619
2620 // Initialize ins_attrib TOC fields.
2621 m1->_const_toc_offset = -1;
2622 m2->_const_toc_offset_hi_node = m1;
2623
2624 // Initialize ins_attrib instruction offset.
2625 m1->_cbuf_insts_offset = -1;
2626
2627 // register allocation for new nodes
2628 ra_->set_pair(m1->_idx, reg_second, reg_first);
2629 ra_->set_pair(m2->_idx, reg_second, reg_first);
2630
2631 // Create result.
2632 nodes._large_hi = m1;
2633 nodes._large_lo = m2;
2634 nodes._small = NULL;
2635 nodes._last = nodes._large_lo;
2636 assert(m2->bottom_type()->isa_long(), "must be long");
2637 } else {
2638 loadConLNode *m2 = new (C) loadConLNode();
2639
2640 // inputs for new nodes
2641 m2->add_req(NULL, toc);
2642
2643 // operands for new nodes
2644 m2->_opnds[0] = new (C) iRegLdstOper(); // dst
2645 m2->_opnds[1] = immSrc; // src
2646 m2->_opnds[2] = new (C) iRegPdstOper(); // toc
2647
2648 // Initialize ins_attrib instruction offset.
2649 m2->_cbuf_insts_offset = -1;
2650
2651 // register allocation for new nodes
2652 ra_->set_pair(m2->_idx, reg_second, reg_first);
2653
2654 // Create result.
2655 nodes._large_hi = NULL;
2656 nodes._large_lo = NULL;
2657 nodes._small = m2;
2658 nodes._last = nodes._small;
2659 assert(m2->bottom_type()->isa_long(), "must be long");
2660 }
2661
2662 return nodes;
2663 }
2664
2665 %} // source
2666
2667 encode %{
2668 // Postalloc expand emitter for loading a long constant from the method's TOC.
2669 // Enc_class needed as consttanttablebase is not supported by postalloc
2670 // expand.
2671 enc_class postalloc_expand_load_long_constant(iRegLdst dst, immL src, iRegLdst toc) %{
2672 // Create new nodes.
2673 loadConLNodesTuple loadConLNodes =
2674 loadConLNodesTuple_create(C, ra_, n_toc, op_src,
2675 ra_->get_reg_second(this), ra_->get_reg_first(this));
2676
2677 // Push new nodes.
2678 if (loadConLNodes._large_hi) nodes->push(loadConLNodes._large_hi);
2679 if (loadConLNodes._last) nodes->push(loadConLNodes._last);
2680
2681 // some asserts
2682 assert(nodes->length() >= 1, "must have created at least 1 node");
2683 assert(loadConLNodes._last->bottom_type()->isa_long(), "must be long");
2684 %}
2685
2686 enc_class enc_load_long_constP(iRegLdst dst, immP src, iRegLdst toc) %{
2687 // TODO: PPC port $archOpcode(ppc64Opcode_ld);
2688
2689 MacroAssembler _masm(&cbuf);
2690 int toc_offset = 0;
2691
2692 if (!ra_->C->in_scratch_emit_size()) {
2693 intptr_t val = $src$$constant;
2694 relocInfo::relocType constant_reloc = $src->constant_reloc(); // src
2695 address const_toc_addr;
2696 if (constant_reloc == relocInfo::oop_type) {
2697 // Create an oop constant and a corresponding relocation.
2698 AddressLiteral a = __ allocate_oop_address((jobject)val);
2699 const_toc_addr = __ address_constant((address)a.value(), RelocationHolder::none);
2700 __ relocate(a.rspec());
2701 } else if (constant_reloc == relocInfo::metadata_type) {
2702 AddressLiteral a = __ allocate_metadata_address((Metadata *)val);
2703 const_toc_addr = __ address_constant((address)a.value(), RelocationHolder::none);
2704 __ relocate(a.rspec());
2705 } else {
2706 // Create a non-oop constant, no relocation needed.
2707 const_toc_addr = __ long_constant((jlong)$src$$constant);
2708 }
2709
2710 // Get the constant's TOC offset.
2711 toc_offset = __ offset_to_method_toc(const_toc_addr);
2712 }
2713
2714 __ ld($dst$$Register, toc_offset, $toc$$Register);
2715 %}
2716
2717 enc_class enc_load_long_constP_hi(iRegLdst dst, immP src, iRegLdst toc) %{
2718 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
2719
2720 MacroAssembler _masm(&cbuf);
2721 if (!ra_->C->in_scratch_emit_size()) {
2722 intptr_t val = $src$$constant;
2723 relocInfo::relocType constant_reloc = $src->constant_reloc(); // src
2724 address const_toc_addr;
2725 if (constant_reloc == relocInfo::oop_type) {
2726 // Create an oop constant and a corresponding relocation.
2727 AddressLiteral a = __ allocate_oop_address((jobject)val);
2728 const_toc_addr = __ address_constant((address)a.value(), RelocationHolder::none);
2729 __ relocate(a.rspec());
2730 } else if (constant_reloc == relocInfo::metadata_type) {
2731 AddressLiteral a = __ allocate_metadata_address((Metadata *)val);
2732 const_toc_addr = __ address_constant((address)a.value(), RelocationHolder::none);
2733 __ relocate(a.rspec());
2734 } else { // non-oop pointers, e.g. card mark base, heap top
2735 // Create a non-oop constant, no relocation needed.
2736 const_toc_addr = __ long_constant((jlong)$src$$constant);
2737 }
2738
2739 // Get the constant's TOC offset.
2740 const int toc_offset = __ offset_to_method_toc(const_toc_addr);
2741 // Store the toc offset of the constant.
2742 ((loadConP_hiNode*)this)->_const_toc_offset = toc_offset;
2743 }
2744
2745 __ addis($dst$$Register, $toc$$Register, MacroAssembler::largeoffset_si16_si16_hi(_const_toc_offset));
2746 %}
2747
2748 // Postalloc expand emitter for loading a ptr constant from the method's TOC.
2749 // Enc_class needed as consttanttablebase is not supported by postalloc
2750 // expand.
2751 enc_class postalloc_expand_load_ptr_constant(iRegPdst dst, immP src, iRegLdst toc) %{
2752 const bool large_constant_pool = true; // TODO: PPC port C->cfg()->_consts_size > 4000;
2753 if (large_constant_pool) {
2754 // Create new nodes.
2755 loadConP_hiNode *m1 = new (C) loadConP_hiNode();
2756 loadConP_loNode *m2 = new (C) loadConP_loNode();
2757
2758 // inputs for new nodes
2759 m1->add_req(NULL, n_toc);
2760 m2->add_req(NULL, m1);
2761
2762 // operands for new nodes
2763 m1->_opnds[0] = new (C) iRegPdstOper(); // dst
2764 m1->_opnds[1] = op_src; // src
2765 m1->_opnds[2] = new (C) iRegPdstOper(); // toc
2766 m2->_opnds[0] = new (C) iRegPdstOper(); // dst
2767 m2->_opnds[1] = op_src; // src
2768 m2->_opnds[2] = new (C) iRegLdstOper(); // base
2769
2770 // Initialize ins_attrib TOC fields.
2771 m1->_const_toc_offset = -1;
2772 m2->_const_toc_offset_hi_node = m1;
2773
2774 // Register allocation for new nodes.
2775 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2776 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2777
2778 nodes->push(m1);
2779 nodes->push(m2);
2780 assert(m2->bottom_type()->isa_ptr(), "must be ptr");
2781 } else {
2782 loadConPNode *m2 = new (C) loadConPNode();
2783
2784 // inputs for new nodes
2785 m2->add_req(NULL, n_toc);
2786
2787 // operands for new nodes
2788 m2->_opnds[0] = new (C) iRegPdstOper(); // dst
2789 m2->_opnds[1] = op_src; // src
2790 m2->_opnds[2] = new (C) iRegPdstOper(); // toc
2791
2792 // Register allocation for new nodes.
2793 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2794
2795 nodes->push(m2);
2796 assert(m2->bottom_type()->isa_ptr(), "must be ptr");
2797 }
2798 %}
2799
2800 // Enc_class needed as consttanttablebase is not supported by postalloc
2801 // expand.
2802 enc_class postalloc_expand_load_float_constant(regF dst, immF src, iRegLdst toc) %{
2803 bool large_constant_pool = true; // TODO: PPC port C->cfg()->_consts_size > 4000;
2804
2805 MachNode *m2;
2806 if (large_constant_pool) {
2807 m2 = new (C) loadConFCompNode();
2808 } else {
2809 m2 = new (C) loadConFNode();
2810 }
2811 // inputs for new nodes
2812 m2->add_req(NULL, n_toc);
2813
2814 // operands for new nodes
2815 m2->_opnds[0] = op_dst;
2816 m2->_opnds[1] = op_src;
2817 m2->_opnds[2] = new (C) iRegPdstOper(); // constanttablebase
2818
2819 // register allocation for new nodes
2820 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2821 nodes->push(m2);
2822 %}
2823
2824 // Enc_class needed as consttanttablebase is not supported by postalloc
2825 // expand.
2826 enc_class postalloc_expand_load_double_constant(regD dst, immD src, iRegLdst toc) %{
2827 bool large_constant_pool = true; // TODO: PPC port C->cfg()->_consts_size > 4000;
2828
2829 MachNode *m2;
2830 if (large_constant_pool) {
2831 m2 = new (C) loadConDCompNode();
2832 } else {
2833 m2 = new (C) loadConDNode();
2834 }
2835 // inputs for new nodes
2836 m2->add_req(NULL, n_toc);
2837
2838 // operands for new nodes
2839 m2->_opnds[0] = op_dst;
2840 m2->_opnds[1] = op_src;
2841 m2->_opnds[2] = new (C) iRegPdstOper(); // constanttablebase
2842
2843 // register allocation for new nodes
2844 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2845 nodes->push(m2);
2846 %}
2847
2848 enc_class enc_stw(iRegIsrc src, memory mem) %{
2849 // TODO: PPC port $archOpcode(ppc64Opcode_stw);
2850 MacroAssembler _masm(&cbuf);
2851 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2852 __ stw($src$$Register, Idisp, $mem$$base$$Register);
2853 %}
2854
2855 enc_class enc_std(iRegIsrc src, memoryAlg4 mem) %{
2856 // TODO: PPC port $archOpcode(ppc64Opcode_std);
2857 MacroAssembler _masm(&cbuf);
2858 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2859 // Operand 'ds' requires 4-alignment.
2860 assert((Idisp & 0x3) == 0, "unaligned offset");
2861 __ std($src$$Register, Idisp, $mem$$base$$Register);
2862 %}
2863
2864 enc_class enc_stfs(RegF src, memory mem) %{
2865 // TODO: PPC port $archOpcode(ppc64Opcode_stfs);
2866 MacroAssembler _masm(&cbuf);
2867 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2868 __ stfs($src$$FloatRegister, Idisp, $mem$$base$$Register);
2869 %}
2870
2871 enc_class enc_stfd(RegF src, memory mem) %{
2872 // TODO: PPC port $archOpcode(ppc64Opcode_stfd);
2873 MacroAssembler _masm(&cbuf);
2874 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2875 __ stfd($src$$FloatRegister, Idisp, $mem$$base$$Register);
2876 %}
2877
2878 // Use release_store for card-marking to ensure that previous
2879 // oop-stores are visible before the card-mark change.
2880 enc_class enc_cms_card_mark(memory mem, iRegLdst releaseFieldAddr) %{
2881 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
2882 // FIXME: Implement this as a cmove and use a fixed condition code
2883 // register which is written on every transition to compiled code,
2884 // e.g. in call-stub and when returning from runtime stubs.
2885 //
2886 // Proposed code sequence for the cmove implementation:
2887 //
2888 // Label skip_release;
2889 // __ beq(CCRfixed, skip_release);
2890 // __ release();
2891 // __ bind(skip_release);
2892 // __ stb(card mark);
2893
2894 MacroAssembler _masm(&cbuf);
2895 Label skip_storestore;
2896
2897 #if 0 // TODO: PPC port
2898 // Check CMSCollectorCardTableModRefBSExt::_requires_release and do the
2899 // StoreStore barrier conditionally.
2900 __ lwz(R0, 0, $releaseFieldAddr$$Register);
2901 __ cmpwi(CCR0, R0, 0);
2902 __ beq_predict_taken(CCR0, skip_storestore);
2903 #endif
2904 __ li(R0, 0);
2905 __ membar(Assembler::StoreStore);
2906 #if 0 // TODO: PPC port
2907 __ bind(skip_storestore);
2908 #endif
2909
2910 // Do the store.
2911 if ($mem$$index == 0) {
2912 __ stb(R0, $mem$$disp, $mem$$base$$Register);
2913 } else {
2914 assert(0 == $mem$$disp, "no displacement possible with indexed load/stores on ppc");
2915 __ stbx(R0, $mem$$base$$Register, $mem$$index$$Register);
2916 }
2917 %}
2918
2919 enc_class postalloc_expand_encode_oop(iRegNdst dst, iRegPdst src, flagsReg crx) %{
2920
2921 if (VM_Version::has_isel()) {
2922 // use isel instruction with Power 7
2923 cmpP_reg_imm16Node *n_compare = new (C) cmpP_reg_imm16Node();
2924 encodeP_subNode *n_sub_base = new (C) encodeP_subNode();
2925 encodeP_shiftNode *n_shift = new (C) encodeP_shiftNode();
2926 cond_set_0_oopNode *n_cond_set = new (C) cond_set_0_oopNode();
2927
2928 n_compare->add_req(n_region, n_src);
2929 n_compare->_opnds[0] = op_crx;
2930 n_compare->_opnds[1] = op_src;
2931 n_compare->_opnds[2] = new (C) immL16Oper(0);
2932
2933 n_sub_base->add_req(n_region, n_src);
2934 n_sub_base->_opnds[0] = op_dst;
2935 n_sub_base->_opnds[1] = op_src;
2936 n_sub_base->_bottom_type = _bottom_type;
2937
2938 n_shift->add_req(n_region, n_sub_base);
2939 n_shift->_opnds[0] = op_dst;
2940 n_shift->_opnds[1] = op_dst;
2941 n_shift->_bottom_type = _bottom_type;
2942
2943 n_cond_set->add_req(n_region, n_compare, n_shift);
2944 n_cond_set->_opnds[0] = op_dst;
2945 n_cond_set->_opnds[1] = op_crx;
2946 n_cond_set->_opnds[2] = op_dst;
2947 n_cond_set->_bottom_type = _bottom_type;
2948
2949 ra_->set_pair(n_compare->_idx, ra_->get_reg_second(n_crx), ra_->get_reg_first(n_crx));
2950 ra_->set_pair(n_sub_base->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2951 ra_->set_pair(n_shift->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2952 ra_->set_pair(n_cond_set->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2953
2954 nodes->push(n_compare);
2955 nodes->push(n_sub_base);
2956 nodes->push(n_shift);
2957 nodes->push(n_cond_set);
2958
2959 } else {
2960 // before Power 7
2961 moveRegNode *n_move = new (C) moveRegNode();
2962 cmpP_reg_imm16Node *n_compare = new (C) cmpP_reg_imm16Node();
2963 encodeP_shiftNode *n_shift = new (C) encodeP_shiftNode();
2964 cond_sub_baseNode *n_sub_base = new (C) cond_sub_baseNode();
2965
2966 n_move->add_req(n_region, n_src);
2967 n_move->_opnds[0] = op_dst;
2968 n_move->_opnds[1] = op_src;
2969 ra_->set_oop(n_move, true); // Until here, 'n_move' still produces an oop.
2970
2971 n_compare->add_req(n_region, n_src);
2972 n_compare->add_prec(n_move);
2973
2974 n_compare->_opnds[0] = op_crx;
2975 n_compare->_opnds[1] = op_src;
2976 n_compare->_opnds[2] = new (C) immL16Oper(0);
2977
2978 n_sub_base->add_req(n_region, n_compare, n_src);
2979 n_sub_base->_opnds[0] = op_dst;
2980 n_sub_base->_opnds[1] = op_crx;
2981 n_sub_base->_opnds[2] = op_src;
2982 n_sub_base->_bottom_type = _bottom_type;
2983
2984 n_shift->add_req(n_region, n_sub_base);
2985 n_shift->_opnds[0] = op_dst;
2986 n_shift->_opnds[1] = op_dst;
2987 n_shift->_bottom_type = _bottom_type;
2988
2989 ra_->set_pair(n_shift->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2990 ra_->set_pair(n_compare->_idx, ra_->get_reg_second(n_crx), ra_->get_reg_first(n_crx));
2991 ra_->set_pair(n_sub_base->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2992 ra_->set_pair(n_move->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2993
2994 nodes->push(n_move);
2995 nodes->push(n_compare);
2996 nodes->push(n_sub_base);
2997 nodes->push(n_shift);
2998 }
2999
3000 assert(!(ra_->is_oop(this)), "sanity"); // This is not supposed to be GC'ed.
3001 %}
3002
3003 enc_class postalloc_expand_encode_oop_not_null(iRegNdst dst, iRegPdst src) %{
3004
3005 encodeP_subNode *n1 = new (C) encodeP_subNode();
3006 n1->add_req(n_region, n_src);
3007 n1->_opnds[0] = op_dst;
3008 n1->_opnds[1] = op_src;
3009 n1->_bottom_type = _bottom_type;
3010
3011 encodeP_shiftNode *n2 = new (C) encodeP_shiftNode();
3012 n2->add_req(n_region, n1);
3013 n2->_opnds[0] = op_dst;
3014 n2->_opnds[1] = op_dst;
3015 n2->_bottom_type = _bottom_type;
3016 ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
3017 ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
3018
3019 nodes->push(n1);
3020 nodes->push(n2);
3021 assert(!(ra_->is_oop(this)), "sanity"); // This is not supposed to be GC'ed.
3022 %}
3023
3024 enc_class postalloc_expand_decode_oop(iRegPdst dst, iRegNsrc src, flagsReg crx) %{
3025 decodeN_shiftNode *n_shift = new (C) decodeN_shiftNode();
3026 cmpN_reg_imm0Node *n_compare = new (C) cmpN_reg_imm0Node();
3027
3028 n_compare->add_req(n_region, n_src);
3029 n_compare->_opnds[0] = op_crx;
3030 n_compare->_opnds[1] = op_src;
3031 n_compare->_opnds[2] = new (C) immN_0Oper(TypeNarrowOop::NULL_PTR);
3032
3033 n_shift->add_req(n_region, n_src);
3034 n_shift->_opnds[0] = op_dst;
3035 n_shift->_opnds[1] = op_src;
3036 n_shift->_bottom_type = _bottom_type;
3037
3038 if (VM_Version::has_isel()) {
3039 // use isel instruction with Power 7
3040
3041 decodeN_addNode *n_add_base = new (C) decodeN_addNode();
3042 n_add_base->add_req(n_region, n_shift);
3043 n_add_base->_opnds[0] = op_dst;
3044 n_add_base->_opnds[1] = op_dst;
3045 n_add_base->_bottom_type = _bottom_type;
3046
3047 cond_set_0_ptrNode *n_cond_set = new (C) cond_set_0_ptrNode();
3048 n_cond_set->add_req(n_region, n_compare, n_add_base);
3049 n_cond_set->_opnds[0] = op_dst;
3050 n_cond_set->_opnds[1] = op_crx;
3051 n_cond_set->_opnds[2] = op_dst;
3052 n_cond_set->_bottom_type = _bottom_type;
3053
3054 assert(ra_->is_oop(this) == true, "A decodeN node must produce an oop!");
3055 ra_->set_oop(n_cond_set, true);
3056
3057 ra_->set_pair(n_shift->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
3058 ra_->set_pair(n_compare->_idx, ra_->get_reg_second(n_crx), ra_->get_reg_first(n_crx));
3059 ra_->set_pair(n_add_base->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
3060 ra_->set_pair(n_cond_set->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
3061
3062 nodes->push(n_compare);
3063 nodes->push(n_shift);
3064 nodes->push(n_add_base);
3065 nodes->push(n_cond_set);
3066
3067 } else {
3068 // before Power 7
3069 cond_add_baseNode *n_add_base = new (C) cond_add_baseNode();
3070
3071 n_add_base->add_req(n_region, n_compare, n_shift);
3072 n_add_base->_opnds[0] = op_dst;
3073 n_add_base->_opnds[1] = op_crx;
3074 n_add_base->_opnds[2] = op_dst;
3075 n_add_base->_bottom_type = _bottom_type;
3076
3077 assert(ra_->is_oop(this) == true, "A decodeN node must produce an oop!");
3078 ra_->set_oop(n_add_base, true);
3079
3080 ra_->set_pair(n_shift->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
3081 ra_->set_pair(n_compare->_idx, ra_->get_reg_second(n_crx), ra_->get_reg_first(n_crx));
3082 ra_->set_pair(n_add_base->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
3083
3084 nodes->push(n_compare);
3085 nodes->push(n_shift);
3086 nodes->push(n_add_base);
3087 }
3088 %}
3089
3090 enc_class postalloc_expand_decode_oop_not_null(iRegPdst dst, iRegNsrc src) %{
3091 decodeN_shiftNode *n1 = new (C) decodeN_shiftNode();
3092 n1->add_req(n_region, n_src);
3093 n1->_opnds[0] = op_dst;
3094 n1->_opnds[1] = op_src;
3095 n1->_bottom_type = _bottom_type;
3096
3097 decodeN_addNode *n2 = new (C) decodeN_addNode();
3098 n2->add_req(n_region, n1);
3099 n2->_opnds[0] = op_dst;
3100 n2->_opnds[1] = op_dst;
3101 n2->_bottom_type = _bottom_type;
3102 ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
3103 ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
3104
3105 assert(ra_->is_oop(this) == true, "A decodeN node must produce an oop!");
3106 ra_->set_oop(n2, true);
3107
3108 nodes->push(n1);
3109 nodes->push(n2);
3110 %}
3111
3112 enc_class enc_cmove_reg(iRegIdst dst, flagsReg crx, iRegIsrc src, cmpOp cmp) %{
3113 // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
3114
3115 MacroAssembler _masm(&cbuf);
3116 int cc = $cmp$$cmpcode;
3117 int flags_reg = $crx$$reg;
3118 Label done;
3119 assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding");
3120 // Branch if not (cmp crx).
3121 __ bc(cc_to_inverse_boint(cc), cc_to_biint(cc, flags_reg), done);
3122 __ mr($dst$$Register, $src$$Register);
3123 // TODO PPC port __ endgroup_if_needed(_size == 12);
3124 __ bind(done);
3125 %}
3126
3127 enc_class enc_cmove_imm(iRegIdst dst, flagsReg crx, immI16 src, cmpOp cmp) %{
3128 // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
3129
3130 MacroAssembler _masm(&cbuf);
3131 Label done;
3132 assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding");
3133 // Branch if not (cmp crx).
3134 __ bc(cc_to_inverse_boint($cmp$$cmpcode), cc_to_biint($cmp$$cmpcode, $crx$$reg), done);
3135 __ li($dst$$Register, $src$$constant);
3136 // TODO PPC port __ endgroup_if_needed(_size == 12);
3137 __ bind(done);
3138 %}
3139
3140 // New atomics.
3141 enc_class enc_GetAndAddI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src) %{
3142 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3143
3144 MacroAssembler _masm(&cbuf);
3145 Register Rtmp = R0;
3146 Register Rres = $res$$Register;
3147 Register Rsrc = $src$$Register;
3148 Register Rptr = $mem_ptr$$Register;
3149 bool RegCollision = (Rres == Rsrc) || (Rres == Rptr);
3150 Register Rold = RegCollision ? Rtmp : Rres;
3151
3152 Label Lretry;
3153 __ bind(Lretry);
3154 __ lwarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update());
3155 __ add(Rtmp, Rsrc, Rold);
3156 __ stwcx_(Rtmp, Rptr);
3157 if (UseStaticBranchPredictionInCompareAndSwapPPC64) {
3158 __ bne_predict_not_taken(CCR0, Lretry);
3159 } else {
3160 __ bne( CCR0, Lretry);
3161 }
3162 if (RegCollision) __ subf(Rres, Rsrc, Rtmp);
3163 __ fence();
3164 %}
3165
3166 enc_class enc_GetAndAddL(iRegLdst res, iRegPdst mem_ptr, iRegLsrc src) %{
3167 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3168
3169 MacroAssembler _masm(&cbuf);
3170 Register Rtmp = R0;
3171 Register Rres = $res$$Register;
3172 Register Rsrc = $src$$Register;
3173 Register Rptr = $mem_ptr$$Register;
3174 bool RegCollision = (Rres == Rsrc) || (Rres == Rptr);
3175 Register Rold = RegCollision ? Rtmp : Rres;
3176
3177 Label Lretry;
3178 __ bind(Lretry);
3179 __ ldarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update());
3180 __ add(Rtmp, Rsrc, Rold);
3181 __ stdcx_(Rtmp, Rptr);
3182 if (UseStaticBranchPredictionInCompareAndSwapPPC64) {
3183 __ bne_predict_not_taken(CCR0, Lretry);
3184 } else {
3185 __ bne( CCR0, Lretry);
3186 }
3187 if (RegCollision) __ subf(Rres, Rsrc, Rtmp);
3188 __ fence();
3189 %}
3190
3191 enc_class enc_GetAndSetI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src) %{
3192 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3193
3194 MacroAssembler _masm(&cbuf);
3195 Register Rtmp = R0;
3196 Register Rres = $res$$Register;
3197 Register Rsrc = $src$$Register;
3198 Register Rptr = $mem_ptr$$Register;
3199 bool RegCollision = (Rres == Rsrc) || (Rres == Rptr);
3200 Register Rold = RegCollision ? Rtmp : Rres;
3201
3202 Label Lretry;
3203 __ bind(Lretry);
3204 __ lwarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update());
3205 __ stwcx_(Rsrc, Rptr);
3206 if (UseStaticBranchPredictionInCompareAndSwapPPC64) {
3207 __ bne_predict_not_taken(CCR0, Lretry);
3208 } else {
3209 __ bne( CCR0, Lretry);
3210 }
3211 if (RegCollision) __ mr(Rres, Rtmp);
3212 __ fence();
3213 %}
3214
3215 enc_class enc_GetAndSetL(iRegLdst res, iRegPdst mem_ptr, iRegLsrc src) %{
3216 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3217
3218 MacroAssembler _masm(&cbuf);
3219 Register Rtmp = R0;
3220 Register Rres = $res$$Register;
3221 Register Rsrc = $src$$Register;
3222 Register Rptr = $mem_ptr$$Register;
3223 bool RegCollision = (Rres == Rsrc) || (Rres == Rptr);
3224 Register Rold = RegCollision ? Rtmp : Rres;
3225
3226 Label Lretry;
3227 __ bind(Lretry);
3228 __ ldarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update());
3229 __ stdcx_(Rsrc, Rptr);
3230 if (UseStaticBranchPredictionInCompareAndSwapPPC64) {
3231 __ bne_predict_not_taken(CCR0, Lretry);
3232 } else {
3233 __ bne( CCR0, Lretry);
3234 }
3235 if (RegCollision) __ mr(Rres, Rtmp);
3236 __ fence();
3237 %}
3238
3239 // This enc_class is needed so that scheduler gets proper
3240 // input mapping for latency computation.
3241 enc_class enc_andc(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
3242 // TODO: PPC port $archOpcode(ppc64Opcode_andc);
3243 MacroAssembler _masm(&cbuf);
3244 __ andc($dst$$Register, $src1$$Register, $src2$$Register);
3245 %}
3246
3247 enc_class enc_convI2B_regI__cmove(iRegIdst dst, iRegIsrc src, flagsReg crx, immI16 zero, immI16 notzero) %{
3248 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3249
3250 MacroAssembler _masm(&cbuf);
3251
3252 Label done;
3253 __ cmpwi($crx$$CondRegister, $src$$Register, 0);
3254 __ li($dst$$Register, $zero$$constant);
3255 __ beq($crx$$CondRegister, done);
3256 __ li($dst$$Register, $notzero$$constant);
3257 __ bind(done);
3258 %}
3259
3260 enc_class enc_convP2B_regP__cmove(iRegIdst dst, iRegPsrc src, flagsReg crx, immI16 zero, immI16 notzero) %{
3261 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3262
3263 MacroAssembler _masm(&cbuf);
3264
3265 Label done;
3266 __ cmpdi($crx$$CondRegister, $src$$Register, 0);
3267 __ li($dst$$Register, $zero$$constant);
3268 __ beq($crx$$CondRegister, done);
3269 __ li($dst$$Register, $notzero$$constant);
3270 __ bind(done);
3271 %}
3272
3273 enc_class enc_cmove_bso_stackSlotL(iRegLdst dst, flagsReg crx, stackSlotL mem ) %{
3274 // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
3275
3276 MacroAssembler _masm(&cbuf);
3277 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
3278 Label done;
3279 __ bso($crx$$CondRegister, done);
3280 __ ld($dst$$Register, Idisp, $mem$$base$$Register);
3281 // TODO PPC port __ endgroup_if_needed(_size == 12);
3282 __ bind(done);
3283 %}
3284
3285 enc_class enc_bc(flagsReg crx, cmpOp cmp, Label lbl) %{
3286 // TODO: PPC port $archOpcode(ppc64Opcode_bc);
3287
3288 MacroAssembler _masm(&cbuf);
3289 Label d; // dummy
3290 __ bind(d);
3291 Label* p = ($lbl$$label);
3292 // `p' is `NULL' when this encoding class is used only to
3293 // determine the size of the encoded instruction.
3294 Label& l = (NULL == p)? d : *(p);
3295 int cc = $cmp$$cmpcode;
3296 int flags_reg = $crx$$reg;
3297 assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding");
3298 int bhint = Assembler::bhintNoHint;
3299
3300 if (UseStaticBranchPredictionForUncommonPathsPPC64) {
3301 if (_prob <= PROB_NEVER) {
3302 bhint = Assembler::bhintIsNotTaken;
3303 } else if (_prob >= PROB_ALWAYS) {
3304 bhint = Assembler::bhintIsTaken;
3305 }
3306 }
3307
3308 __ bc(Assembler::add_bhint_to_boint(bhint, cc_to_boint(cc)),
3309 cc_to_biint(cc, flags_reg),
3310 l);
3311 %}
3312
3313 enc_class enc_bc_far(flagsReg crx, cmpOp cmp, Label lbl) %{
3314 // The scheduler doesn't know about branch shortening, so we set the opcode
3315 // to ppc64Opcode_bc in order to hide this detail from the scheduler.
3316 // TODO: PPC port $archOpcode(ppc64Opcode_bc);
3317
3318 MacroAssembler _masm(&cbuf);
3319 Label d; // dummy
3320 __ bind(d);
3321 Label* p = ($lbl$$label);
3322 // `p' is `NULL' when this encoding class is used only to
3323 // determine the size of the encoded instruction.
3324 Label& l = (NULL == p)? d : *(p);
3325 int cc = $cmp$$cmpcode;
3326 int flags_reg = $crx$$reg;
3327 int bhint = Assembler::bhintNoHint;
3328
3329 if (UseStaticBranchPredictionForUncommonPathsPPC64) {
3330 if (_prob <= PROB_NEVER) {
3331 bhint = Assembler::bhintIsNotTaken;
3332 } else if (_prob >= PROB_ALWAYS) {
3333 bhint = Assembler::bhintIsTaken;
3334 }
3335 }
3336
3337 // Tell the conditional far branch to optimize itself when being relocated.
3338 __ bc_far(Assembler::add_bhint_to_boint(bhint, cc_to_boint(cc)),
3339 cc_to_biint(cc, flags_reg),
3340 l,
3341 MacroAssembler::bc_far_optimize_on_relocate);
3342 %}
3343
3344 // Branch used with Power6 scheduling (can be shortened without changing the node).
3345 enc_class enc_bc_short_far(flagsReg crx, cmpOp cmp, Label lbl) %{
3346 // The scheduler doesn't know about branch shortening, so we set the opcode
3347 // to ppc64Opcode_bc in order to hide this detail from the scheduler.
3348 // TODO: PPC port $archOpcode(ppc64Opcode_bc);
3349
3350 MacroAssembler _masm(&cbuf);
3351 Label d; // dummy
3352 __ bind(d);
3353 Label* p = ($lbl$$label);
3354 // `p' is `NULL' when this encoding class is used only to
3355 // determine the size of the encoded instruction.
3356 Label& l = (NULL == p)? d : *(p);
3357 int cc = $cmp$$cmpcode;
3358 int flags_reg = $crx$$reg;
3359 int bhint = Assembler::bhintNoHint;
3360
3361 if (UseStaticBranchPredictionForUncommonPathsPPC64) {
3362 if (_prob <= PROB_NEVER) {
3363 bhint = Assembler::bhintIsNotTaken;
3364 } else if (_prob >= PROB_ALWAYS) {
3365 bhint = Assembler::bhintIsTaken;
3366 }
3367 }
3368
3369 #if 0 // TODO: PPC port
3370 if (_size == 8) {
3371 // Tell the conditional far branch to optimize itself when being relocated.
3372 __ bc_far(Assembler::add_bhint_to_boint(bhint, cc_to_boint(cc)),
3373 cc_to_biint(cc, flags_reg),
3374 l,
3375 MacroAssembler::bc_far_optimize_on_relocate);
3376 } else {
3377 __ bc (Assembler::add_bhint_to_boint(bhint, cc_to_boint(cc)),
3378 cc_to_biint(cc, flags_reg),
3379 l);
3380 }
3381 #endif
3382 Unimplemented();
3383 %}
3384
3385 // Postalloc expand emitter for loading a replicatef float constant from
3386 // the method's TOC.
3387 // Enc_class needed as consttanttablebase is not supported by postalloc
3388 // expand.
3389 enc_class postalloc_expand_load_replF_constant(iRegLdst dst, immF src, iRegLdst toc) %{
3390 // Create new nodes.
3391
3392 // Make an operand with the bit pattern to load as float.
3393 immLOper *op_repl = new (C) immLOper((jlong)replicate_immF(op_src->constantF()));
3394
3395 loadConLNodesTuple loadConLNodes =
3396 loadConLNodesTuple_create(C, ra_, n_toc, op_repl,
3397 ra_->get_reg_second(this), ra_->get_reg_first(this));
3398
3399 // Push new nodes.
3400 if (loadConLNodes._large_hi) nodes->push(loadConLNodes._large_hi);
3401 if (loadConLNodes._last) nodes->push(loadConLNodes._last);
3402
3403 assert(nodes->length() >= 1, "must have created at least 1 node");
3404 assert(loadConLNodes._last->bottom_type()->isa_long(), "must be long");
3405 %}
3406
3407 // This enc_class is needed so that scheduler gets proper
3408 // input mapping for latency computation.
3409 enc_class enc_poll(immI dst, iRegLdst poll) %{
3410 // TODO: PPC port $archOpcode(ppc64Opcode_ld);
3411 // Fake operand dst needed for PPC scheduler.
3412 assert($dst$$constant == 0x0, "dst must be 0x0");
3413
3414 MacroAssembler _masm(&cbuf);
3415 // Mark the code position where the load from the safepoint
3416 // polling page was emitted as relocInfo::poll_type.
3417 __ relocate(relocInfo::poll_type);
3418 __ load_from_polling_page($poll$$Register);
3419 %}
3420
3421 // A Java static call or a runtime call.
3422 //
3423 // Branch-and-link relative to a trampoline.
3424 // The trampoline loads the target address and does a long branch to there.
3425 // In case we call java, the trampoline branches to a interpreter_stub
3426 // which loads the inline cache and the real call target from the constant pool.
3427 //
3428 // This basically looks like this:
3429 //
3430 // >>>> consts -+ -+
3431 // | |- offset1
3432 // [call target1] | <-+
3433 // [IC cache] |- offset2
3434 // [call target2] <--+
3435 //
3436 // <<<< consts
3437 // >>>> insts
3438 //
3439 // bl offset16 -+ -+ ??? // How many bits available?
3440 // | |
3441 // <<<< insts | |
3442 // >>>> stubs | |
3443 // | |- trampoline_stub_Reloc
3444 // trampoline stub: | <-+
3445 // r2 = toc |
3446 // r2 = [r2 + offset1] | // Load call target1 from const section
3447 // mtctr r2 |
3448 // bctr |- static_stub_Reloc
3449 // comp_to_interp_stub: <---+
3450 // r1 = toc
3451 // ICreg = [r1 + IC_offset] // Load IC from const section
3452 // r1 = [r1 + offset2] // Load call target2 from const section
3453 // mtctr r1
3454 // bctr
3455 //
3456 // <<<< stubs
3457 //
3458 // The call instruction in the code either
3459 // - Branches directly to a compiled method if the offset is encodable in instruction.
3460 // - Branches to the trampoline stub if the offset to the compiled method is not encodable.
3461 // - Branches to the compiled_to_interp stub if the target is interpreted.
3462 //
3463 // Further there are three relocations from the loads to the constants in
3464 // the constant section.
3465 //
3466 // Usage of r1 and r2 in the stubs allows to distinguish them.
3467 enc_class enc_java_static_call(method meth) %{
3468 // TODO: PPC port $archOpcode(ppc64Opcode_bl);
3469
3470 MacroAssembler _masm(&cbuf);
3471 address entry_point = (address)$meth$$method;
3472
3473 if (!_method) {
3474 // A call to a runtime wrapper, e.g. new, new_typeArray_Java, uncommon_trap.
3475 emit_call_with_trampoline_stub(_masm, entry_point, relocInfo::runtime_call_type);
3476 } else {
3477 // Remember the offset not the address.
3478 const int start_offset = __ offset();
3479 // The trampoline stub.
3480 if (!Compile::current()->in_scratch_emit_size()) {
3481 // No entry point given, use the current pc.
3482 // Make sure branch fits into
3483 if (entry_point == 0) entry_point = __ pc();
3484
3485 // Put the entry point as a constant into the constant pool.
3486 const address entry_point_toc_addr = __ address_constant(entry_point, RelocationHolder::none);
3487 const int entry_point_toc_offset = __ offset_to_method_toc(entry_point_toc_addr);
3488
3489 // Emit the trampoline stub which will be related to the branch-and-link below.
3490 CallStubImpl::emit_trampoline_stub(_masm, entry_point_toc_offset, start_offset);
3491 if (Compile::current()->env()->failing()) { return; } // Code cache may be full.
3492 __ relocate(_optimized_virtual ?
3493 relocInfo::opt_virtual_call_type : relocInfo::static_call_type);
3494 }
3495
3496 // The real call.
3497 // Note: At this point we do not have the address of the trampoline
3498 // stub, and the entry point might be too far away for bl, so __ pc()
3499 // serves as dummy and the bl will be patched later.
3500 cbuf.set_insts_mark();
3501 __ bl(__ pc()); // Emits a relocation.
3502
3503 // The stub for call to interpreter.
3504 CompiledStaticCall::emit_to_interp_stub(cbuf);
3505 }
3506 %}
3507
3508 // Emit a method handle call.
3509 //
3510 // Method handle calls from compiled to compiled are going thru a
3511 // c2i -> i2c adapter, extending the frame for their arguments. The
3512 // caller however, returns directly to the compiled callee, that has
3513 // to cope with the extended frame. We restore the original frame by
3514 // loading the callers sp and adding the calculated framesize.
3515 enc_class enc_java_handle_call(method meth) %{
3516 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3517
3518 MacroAssembler _masm(&cbuf);
3519 address entry_point = (address)$meth$$method;
3520
3521 // Remember the offset not the address.
3522 const int start_offset = __ offset();
3523 // The trampoline stub.
3524 if (!ra_->C->in_scratch_emit_size()) {
3525 // No entry point given, use the current pc.
3526 // Make sure branch fits into
3527 if (entry_point == 0) entry_point = __ pc();
3528
3529 // Put the entry point as a constant into the constant pool.
3530 const address entry_point_toc_addr = __ address_constant(entry_point, RelocationHolder::none);
3531 const int entry_point_toc_offset = __ offset_to_method_toc(entry_point_toc_addr);
3532
3533 // Emit the trampoline stub which will be related to the branch-and-link below.
3534 CallStubImpl::emit_trampoline_stub(_masm, entry_point_toc_offset, start_offset);
3535 if (ra_->C->env()->failing()) { return; } // Code cache may be full.
3536 assert(_optimized_virtual, "methodHandle call should be a virtual call");
3537 __ relocate(relocInfo::opt_virtual_call_type);
3538 }
3539
3540 // The real call.
3541 // Note: At this point we do not have the address of the trampoline
3542 // stub, and the entry point might be too far away for bl, so __ pc()
3543 // serves as dummy and the bl will be patched later.
3544 cbuf.set_insts_mark();
3545 __ bl(__ pc()); // Emits a relocation.
3546
3547 assert(_method, "execute next statement conditionally");
3548 // The stub for call to interpreter.
3549 CompiledStaticCall::emit_to_interp_stub(cbuf);
3550
3551 // Restore original sp.
3552 __ ld(R11_scratch1, 0, R1_SP); // Load caller sp.
3553 const long framesize = ra_->C->frame_slots() << LogBytesPerInt;
3554 unsigned int bytes = (unsigned int)framesize;
3555 long offset = Assembler::align_addr(bytes, frame::alignment_in_bytes);
3556 if (Assembler::is_simm(-offset, 16)) {
3557 __ addi(R1_SP, R11_scratch1, -offset);
3558 } else {
3559 __ load_const_optimized(R12_scratch2, -offset);
3560 __ add(R1_SP, R11_scratch1, R12_scratch2);
3561 }
3562 #ifdef ASSERT
3563 __ ld(R12_scratch2, 0, R1_SP); // Load from unextended_sp.
3564 __ cmpd(CCR0, R11_scratch1, R12_scratch2);
3565 __ asm_assert_eq("backlink changed", 0x8000);
3566 #endif
3567 // If fails should store backlink before unextending.
3568
3569 if (ra_->C->env()->failing()) {
3570 return;
3571 }
3572 %}
3573
3574 // Second node of expanded dynamic call - the call.
3575 enc_class enc_java_dynamic_call_sched(method meth) %{
3576 // TODO: PPC port $archOpcode(ppc64Opcode_bl);
3577
3578 MacroAssembler _masm(&cbuf);
3579
3580 if (!ra_->C->in_scratch_emit_size()) {
3581 // Create a call trampoline stub for the given method.
3582 const address entry_point = !($meth$$method) ? 0 : (address)$meth$$method;
3583 const address entry_point_const = __ address_constant(entry_point, RelocationHolder::none);
3584 const int entry_point_const_toc_offset = __ offset_to_method_toc(entry_point_const);
3585 CallStubImpl::emit_trampoline_stub(_masm, entry_point_const_toc_offset, __ offset());
3586 if (ra_->C->env()->failing()) { return; } // Code cache may be full.
3587
3588 // Build relocation at call site with ic position as data.
3589 assert((_load_ic_hi_node != NULL && _load_ic_node == NULL) ||
3590 (_load_ic_hi_node == NULL && _load_ic_node != NULL),
3591 "must have one, but can't have both");
3592 assert((_load_ic_hi_node != NULL && _load_ic_hi_node->_cbuf_insts_offset != -1) ||
3593 (_load_ic_node != NULL && _load_ic_node->_cbuf_insts_offset != -1),
3594 "must contain instruction offset");
3595 const int virtual_call_oop_addr_offset = _load_ic_hi_node != NULL
3596 ? _load_ic_hi_node->_cbuf_insts_offset
3597 : _load_ic_node->_cbuf_insts_offset;
3598 const address virtual_call_oop_addr = __ addr_at(virtual_call_oop_addr_offset);
3599 assert(MacroAssembler::is_load_const_from_method_toc_at(virtual_call_oop_addr),
3600 "should be load from TOC");
3601
3602 __ relocate(virtual_call_Relocation::spec(virtual_call_oop_addr));
3603 }
3604
3605 // At this point I do not have the address of the trampoline stub,
3606 // and the entry point might be too far away for bl. Pc() serves
3607 // as dummy and bl will be patched later.
3608 __ bl((address) __ pc());
3609 %}
3610
3611 // postalloc expand emitter for virtual calls.
3612 enc_class postalloc_expand_java_dynamic_call_sched(method meth, iRegLdst toc) %{
3613
3614 // Create the nodes for loading the IC from the TOC.
3615 loadConLNodesTuple loadConLNodes_IC =
3616 loadConLNodesTuple_create(C, ra_, n_toc, new (C) immLOper((jlong)Universe::non_oop_word()),
3617 OptoReg::Name(R19_H_num), OptoReg::Name(R19_num));
3618
3619 // Create the call node.
3620 CallDynamicJavaDirectSchedNode *call = new (C) CallDynamicJavaDirectSchedNode();
3621 call->_method_handle_invoke = _method_handle_invoke;
3622 call->_vtable_index = _vtable_index;
3623 call->_method = _method;
3624 call->_bci = _bci;
3625 call->_optimized_virtual = _optimized_virtual;
3626 call->_tf = _tf;
3627 call->_entry_point = _entry_point;
3628 call->_cnt = _cnt;
3629 call->_argsize = _argsize;
3630 call->_oop_map = _oop_map;
3631 call->_jvms = _jvms;
3632 call->_jvmadj = _jvmadj;
3633 call->_in_rms = _in_rms;
3634 call->_nesting = _nesting;
3635
3636 // New call needs all inputs of old call.
3637 // Req...
3638 for (uint i = 0; i < req(); ++i) {
3639 // The expanded node does not need toc any more.
3640 // Add the inline cache constant here instead. This expresses the
3641 // register of the inline cache must be live at the call.
3642 // Else we would have to adapt JVMState by -1.
3643 if (i == mach_constant_base_node_input()) {
3644 call->add_req(loadConLNodes_IC._last);
3645 } else {
3646 call->add_req(in(i));
3647 }
3648 }
3649 // ...as well as prec
3650 for (uint i = req(); i < len(); ++i) {
3651 call->add_prec(in(i));
3652 }
3653
3654 // Remember nodes loading the inline cache into r19.
3655 call->_load_ic_hi_node = loadConLNodes_IC._large_hi;
3656 call->_load_ic_node = loadConLNodes_IC._small;
3657
3658 // Operands for new nodes.
3659 call->_opnds[0] = _opnds[0];
3660 call->_opnds[1] = _opnds[1];
3661
3662 // Only the inline cache is associated with a register.
3663 assert(Matcher::inline_cache_reg() == OptoReg::Name(R19_num), "ic reg should be R19");
3664
3665 // Push new nodes.
3666 if (loadConLNodes_IC._large_hi) nodes->push(loadConLNodes_IC._large_hi);
3667 if (loadConLNodes_IC._last) nodes->push(loadConLNodes_IC._last);
3668 nodes->push(call);
3669 %}
3670
3671 // Compound version of call dynamic
3672 // Toc is only passed so that it can be used in ins_encode statement.
3673 // In the code we have to use $constanttablebase.
3674 enc_class enc_java_dynamic_call(method meth, iRegLdst toc) %{
3675 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3676 MacroAssembler _masm(&cbuf);
3677 int start_offset = __ offset();
3678
3679 Register Rtoc = (ra_) ? $constanttablebase : R2_TOC;
3680 #if 0
3681 int vtable_index = this->_vtable_index;
3682 if (_vtable_index < 0) {
3683 // Must be invalid_vtable_index, not nonvirtual_vtable_index.
3684 assert(_vtable_index == Method::invalid_vtable_index, "correct sentinel value");
3685 Register ic_reg = as_Register(Matcher::inline_cache_reg_encode());
3686
3687 // Virtual call relocation will point to ic load.
3688 address virtual_call_meta_addr = __ pc();
3689 // Load a clear inline cache.
3690 AddressLiteral empty_ic((address) Universe::non_oop_word());
3691 __ load_const_from_method_toc(ic_reg, empty_ic, Rtoc);
3692 // CALL to fixup routine. Fixup routine uses ScopeDesc info
3693 // to determine who we intended to call.
3694 __ relocate(virtual_call_Relocation::spec(virtual_call_meta_addr));
3695 emit_call_with_trampoline_stub(_masm, (address)$meth$$method, relocInfo::none);
3696 assert(((MachCallDynamicJavaNode*)this)->ret_addr_offset() == __ offset() - start_offset,
3697 "Fix constant in ret_addr_offset()");
3698 } else {
3699 assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
3700 // Go thru the vtable. Get receiver klass. Receiver already
3701 // checked for non-null. If we'll go thru a C2I adapter, the
3702 // interpreter expects method in R19_method.
3703
3704 __ load_klass(R11_scratch1, R3);
3705
3706 int entry_offset = InstanceKlass::vtable_start_offset() + _vtable_index * vtableEntry::size();
3707 int v_off = entry_offset * wordSize + vtableEntry::method_offset_in_bytes();
3708 __ li(R19_method, v_off);
3709 __ ldx(R19_method/*method oop*/, R19_method/*method offset*/, R11_scratch1/*class*/);
3710 // NOTE: for vtable dispatches, the vtable entry will never be
3711 // null. However it may very well end up in handle_wrong_method
3712 // if the method is abstract for the particular class.
3713 __ ld(R11_scratch1, in_bytes(Method::from_compiled_offset()), R19_method);
3714 // Call target. Either compiled code or C2I adapter.
3715 __ mtctr(R11_scratch1);
3716 __ bctrl();
3717 if (((MachCallDynamicJavaNode*)this)->ret_addr_offset() != __ offset() - start_offset) {
3718 tty->print(" %d, %d\n", ((MachCallDynamicJavaNode*)this)->ret_addr_offset(),__ offset() - start_offset);
3719 }
3720 assert(((MachCallDynamicJavaNode*)this)->ret_addr_offset() == __ offset() - start_offset,
3721 "Fix constant in ret_addr_offset()");
3722 }
3723 #endif
3724 Unimplemented(); // ret_addr_offset not yet fixed. Depends on compressed oops (load klass!).
3725 %}
3726
3727 // a runtime call
3728 enc_class enc_java_to_runtime_call (method meth) %{
3729 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3730
3731 MacroAssembler _masm(&cbuf);
3732 const address start_pc = __ pc();
3733
3734 #if defined(ABI_ELFv2)
3735 address entry= !($meth$$method) ? NULL : (address)$meth$$method;
3736 __ call_c(entry, relocInfo::runtime_call_type);
3737 #else
3738 // The function we're going to call.
3739 FunctionDescriptor fdtemp;
3740 const FunctionDescriptor* fd = !($meth$$method) ? &fdtemp : (FunctionDescriptor*)$meth$$method;
3741
3742 Register Rtoc = R12_scratch2;
3743 // Calculate the method's TOC.
3744 __ calculate_address_from_global_toc(Rtoc, __ method_toc());
3745 // Put entry, env, toc into the constant pool, this needs up to 3 constant
3746 // pool entries; call_c_using_toc will optimize the call.
3747 __ call_c_using_toc(fd, relocInfo::runtime_call_type, Rtoc);
3748 #endif
3749
3750 // Check the ret_addr_offset.
3751 assert(((MachCallRuntimeNode*)this)->ret_addr_offset() == __ last_calls_return_pc() - start_pc,
3752 "Fix constant in ret_addr_offset()");
3753 %}
3754
3755 // Move to ctr for leaf call.
3756 // This enc_class is needed so that scheduler gets proper
3757 // input mapping for latency computation.
3758 enc_class enc_leaf_call_mtctr(iRegLsrc src) %{
3759 // TODO: PPC port $archOpcode(ppc64Opcode_mtctr);
3760 MacroAssembler _masm(&cbuf);
3761 __ mtctr($src$$Register);
3762 %}
3763
3764 // Postalloc expand emitter for runtime leaf calls.
3765 enc_class postalloc_expand_java_to_runtime_call(method meth, iRegLdst toc) %{
3766 loadConLNodesTuple loadConLNodes_Entry;
3767 #if defined(ABI_ELFv2)
3768 jlong entry_address = (jlong) this->entry_point();
3769 assert(entry_address, "need address here");
3770 loadConLNodes_Entry = loadConLNodesTuple_create(C, ra_, n_toc, new (C) immLOper(entry_address),
3771 OptoReg::Name(R12_H_num), OptoReg::Name(R12_num));
3772 #else
3773 // Get the struct that describes the function we are about to call.
3774 FunctionDescriptor* fd = (FunctionDescriptor*) this->entry_point();
3775 assert(fd, "need fd here");
3776 jlong entry_address = (jlong) fd->entry();
3777 // new nodes
3778 loadConLNodesTuple loadConLNodes_Env;
3779 loadConLNodesTuple loadConLNodes_Toc;
3780
3781 // Create nodes and operands for loading the entry point.
3782 loadConLNodes_Entry = loadConLNodesTuple_create(C, ra_, n_toc, new (C) immLOper(entry_address),
3783 OptoReg::Name(R12_H_num), OptoReg::Name(R12_num));
3784
3785
3786 // Create nodes and operands for loading the env pointer.
3787 if (fd->env() != NULL) {
3788 loadConLNodes_Env = loadConLNodesTuple_create(C, ra_, n_toc, new (C) immLOper((jlong) fd->env()),
3789 OptoReg::Name(R11_H_num), OptoReg::Name(R11_num));
3790 } else {
3791 loadConLNodes_Env._large_hi = NULL;
3792 loadConLNodes_Env._large_lo = NULL;
3793 loadConLNodes_Env._small = NULL;
3794 loadConLNodes_Env._last = new (C) loadConL16Node();
3795 loadConLNodes_Env._last->_opnds[0] = new (C) iRegLdstOper();
3796 loadConLNodes_Env._last->_opnds[1] = new (C) immL16Oper(0);
3797 ra_->set_pair(loadConLNodes_Env._last->_idx, OptoReg::Name(R11_H_num), OptoReg::Name(R11_num));
3798 }
3799
3800 // Create nodes and operands for loading the Toc point.
3801 loadConLNodes_Toc = loadConLNodesTuple_create(C, ra_, n_toc, new (C) immLOper((jlong) fd->toc()),
3802 OptoReg::Name(R2_H_num), OptoReg::Name(R2_num));
3803 #endif // ABI_ELFv2
3804 // mtctr node
3805 MachNode *mtctr = new (C) CallLeafDirect_mtctrNode();
3806
3807 assert(loadConLNodes_Entry._last != NULL, "entry must exist");
3808 mtctr->add_req(0, loadConLNodes_Entry._last);
3809
3810 mtctr->_opnds[0] = new (C) iRegLdstOper();
3811 mtctr->_opnds[1] = new (C) iRegLdstOper();
3812
3813 // call node
3814 MachCallLeafNode *call = new (C) CallLeafDirectNode();
3815
3816 call->_opnds[0] = _opnds[0];
3817 call->_opnds[1] = new (C) methodOper((intptr_t) entry_address); // May get set later.
3818
3819 // Make the new call node look like the old one.
3820 call->_name = _name;
3821 call->_tf = _tf;
3822 call->_entry_point = _entry_point;
3823 call->_cnt = _cnt;
3824 call->_argsize = _argsize;
3825 call->_oop_map = _oop_map;
3826 guarantee(!_jvms, "You must clone the jvms and adapt the offsets by fix_jvms().");
3827 call->_jvms = NULL;
3828 call->_jvmadj = _jvmadj;
3829 call->_in_rms = _in_rms;
3830 call->_nesting = _nesting;
3831
3832
3833 // New call needs all inputs of old call.
3834 // Req...
3835 for (uint i = 0; i < req(); ++i) {
3836 if (i != mach_constant_base_node_input()) {
3837 call->add_req(in(i));
3838 }
3839 }
3840
3841 // These must be reqired edges, as the registers are live up to
3842 // the call. Else the constants are handled as kills.
3843 call->add_req(mtctr);
3844 #if !defined(ABI_ELFv2)
3845 call->add_req(loadConLNodes_Env._last);
3846 call->add_req(loadConLNodes_Toc._last);
3847 #endif
3848
3849 // ...as well as prec
3850 for (uint i = req(); i < len(); ++i) {
3851 call->add_prec(in(i));
3852 }
3853
3854 // registers
3855 ra_->set1(mtctr->_idx, OptoReg::Name(SR_CTR_num));
3856
3857 // Insert the new nodes.
3858 if (loadConLNodes_Entry._large_hi) nodes->push(loadConLNodes_Entry._large_hi);
3859 if (loadConLNodes_Entry._last) nodes->push(loadConLNodes_Entry._last);
3860 #if !defined(ABI_ELFv2)
3861 if (loadConLNodes_Env._large_hi) nodes->push(loadConLNodes_Env._large_hi);
3862 if (loadConLNodes_Env._last) nodes->push(loadConLNodes_Env._last);
3863 if (loadConLNodes_Toc._large_hi) nodes->push(loadConLNodes_Toc._large_hi);
3864 if (loadConLNodes_Toc._last) nodes->push(loadConLNodes_Toc._last);
3865 #endif
3866 nodes->push(mtctr);
3867 nodes->push(call);
3868 %}
3869 %}
3870
3871 //----------FRAME--------------------------------------------------------------
3872 // Definition of frame structure and management information.
3873
3874 frame %{
3875 // What direction does stack grow in (assumed to be same for native & Java).
3876 stack_direction(TOWARDS_LOW);
3877
3878 // These two registers define part of the calling convention between
3879 // compiled code and the interpreter.
3880
3881 // Inline Cache Register or method for I2C.
3882 inline_cache_reg(R19); // R19_method
3883
3884 // Method Oop Register when calling interpreter.
3885 interpreter_method_oop_reg(R19); // R19_method
3886
3887 // Optional: name the operand used by cisc-spilling to access
3888 // [stack_pointer + offset].
3889 cisc_spilling_operand_name(indOffset);
3890
3891 // Number of stack slots consumed by a Monitor enter.
3892 sync_stack_slots((frame::jit_monitor_size / VMRegImpl::stack_slot_size));
3893
3894 // Compiled code's Frame Pointer.
3895 frame_pointer(R1); // R1_SP
3896
3897 // Interpreter stores its frame pointer in a register which is
3898 // stored to the stack by I2CAdaptors. I2CAdaptors convert from
3899 // interpreted java to compiled java.
3900 //
3901 // R14_state holds pointer to caller's cInterpreter.
3902 interpreter_frame_pointer(R14); // R14_state
3903
3904 stack_alignment(frame::alignment_in_bytes);
3905
3906 in_preserve_stack_slots((frame::jit_in_preserve_size / VMRegImpl::stack_slot_size));
3907
3908 // Number of outgoing stack slots killed above the
3909 // out_preserve_stack_slots for calls to C. Supports the var-args
3910 // backing area for register parms.
3911 //
3912 varargs_C_out_slots_killed(((frame::abi_reg_args_size - frame::jit_out_preserve_size) / VMRegImpl::stack_slot_size));
3913
3914 // The after-PROLOG location of the return address. Location of
3915 // return address specifies a type (REG or STACK) and a number
3916 // representing the register number (i.e. - use a register name) or
3917 // stack slot.
3918 //
3919 // A: Link register is stored in stack slot ...
3920 // M: ... but it's in the caller's frame according to PPC-64 ABI.
3921 // J: Therefore, we make sure that the link register is also in R11_scratch1
3922 // at the end of the prolog.
3923 // B: We use R20, now.
3924 //return_addr(REG R20);
3925
3926 // G: After reading the comments made by all the luminaries on their
3927 // failure to tell the compiler where the return address really is,
3928 // I hardly dare to try myself. However, I'm convinced it's in slot
3929 // 4 what apparently works and saves us some spills.
3930 return_addr(STACK 4);
3931
3932 // This is the body of the function
3933 //
3934 // void Matcher::calling_convention(OptoRegPair* sig, // array of ideal regs
3935 // uint length, // length of array
3936 // bool is_outgoing)
3937 //
3938 // The `sig' array is to be updated. sig[j] represents the location
3939 // of the j-th argument, either a register or a stack slot.
3940
3941 // Comment taken from i486.ad:
3942 // Body of function which returns an integer array locating
3943 // arguments either in registers or in stack slots. Passed an array
3944 // of ideal registers called "sig" and a "length" count. Stack-slot
3945 // offsets are based on outgoing arguments, i.e. a CALLER setting up
3946 // arguments for a CALLEE. Incoming stack arguments are
3947 // automatically biased by the preserve_stack_slots field above.
3948 calling_convention %{
3949 // No difference between ingoing/outgoing. Just pass false.
3950 SharedRuntime::java_calling_convention(sig_bt, regs, length, false);
3951 %}
3952
3953 // Comment taken from i486.ad:
3954 // Body of function which returns an integer array locating
3955 // arguments either in registers or in stack slots. Passed an array
3956 // of ideal registers called "sig" and a "length" count. Stack-slot
3957 // offsets are based on outgoing arguments, i.e. a CALLER setting up
3958 // arguments for a CALLEE. Incoming stack arguments are
3959 // automatically biased by the preserve_stack_slots field above.
3960 c_calling_convention %{
3961 // This is obviously always outgoing.
3962 // C argument in register AND stack slot.
3963 (void) SharedRuntime::c_calling_convention(sig_bt, regs, /*regs2=*/NULL, length);
3964 %}
3965
3966 // Location of native (C/C++) and interpreter return values. This
3967 // is specified to be the same as Java. In the 32-bit VM, long
3968 // values are actually returned from native calls in O0:O1 and
3969 // returned to the interpreter in I0:I1. The copying to and from
3970 // the register pairs is done by the appropriate call and epilog
3971 // opcodes. This simplifies the register allocator.
3972 c_return_value %{
3973 assert((ideal_reg >= Op_RegI && ideal_reg <= Op_RegL) ||
3974 (ideal_reg == Op_RegN && Universe::narrow_oop_base() == NULL && Universe::narrow_oop_shift() == 0),
3975 "only return normal values");
3976 // enum names from opcodes.hpp: Op_Node Op_Set Op_RegN Op_RegI Op_RegP Op_RegF Op_RegD Op_RegL
3977 static int typeToRegLo[Op_RegL+1] = { 0, 0, R3_num, R3_num, R3_num, F1_num, F1_num, R3_num };
3978 static int typeToRegHi[Op_RegL+1] = { 0, 0, OptoReg::Bad, R3_H_num, R3_H_num, OptoReg::Bad, F1_H_num, R3_H_num };
3979 return OptoRegPair(typeToRegHi[ideal_reg], typeToRegLo[ideal_reg]);
3980 %}
3981
3982 // Location of compiled Java return values. Same as C
3983 return_value %{
3984 assert((ideal_reg >= Op_RegI && ideal_reg <= Op_RegL) ||
3985 (ideal_reg == Op_RegN && Universe::narrow_oop_base() == NULL && Universe::narrow_oop_shift() == 0),
3986 "only return normal values");
3987 // enum names from opcodes.hpp: Op_Node Op_Set Op_RegN Op_RegI Op_RegP Op_RegF Op_RegD Op_RegL
3988 static int typeToRegLo[Op_RegL+1] = { 0, 0, R3_num, R3_num, R3_num, F1_num, F1_num, R3_num };
3989 static int typeToRegHi[Op_RegL+1] = { 0, 0, OptoReg::Bad, R3_H_num, R3_H_num, OptoReg::Bad, F1_H_num, R3_H_num };
3990 return OptoRegPair(typeToRegHi[ideal_reg], typeToRegLo[ideal_reg]);
3991 %}
3992 %}
3993
3994
3995 //----------ATTRIBUTES---------------------------------------------------------
3996
3997 //----------Operand Attributes-------------------------------------------------
3998 op_attrib op_cost(1); // Required cost attribute.
3999
4000 //----------Instruction Attributes---------------------------------------------
4001
4002 // Cost attribute. required.
4003 ins_attrib ins_cost(DEFAULT_COST);
4004
4005 // Is this instruction a non-matching short branch variant of some
4006 // long branch? Not required.
4007 ins_attrib ins_short_branch(0);
4008
4009 ins_attrib ins_is_TrapBasedCheckNode(true);
4010
4011 // Number of constants.
4012 // This instruction uses the given number of constants
4013 // (optional attribute).
4014 // This is needed to determine in time whether the constant pool will
4015 // exceed 4000 entries. Before postalloc_expand the overall number of constants
4016 // is determined. It's also used to compute the constant pool size
4017 // in Output().
4018 ins_attrib ins_num_consts(0);
4019
4020 // Required alignment attribute (must be a power of 2) specifies the
4021 // alignment that some part of the instruction (not necessarily the
4022 // start) requires. If > 1, a compute_padding() function must be
4023 // provided for the instruction.
4024 ins_attrib ins_alignment(1);
4025
4026 // Enforce/prohibit rematerializations.
4027 // - If an instruction is attributed with 'ins_cannot_rematerialize(true)'
4028 // then rematerialization of that instruction is prohibited and the
4029 // instruction's value will be spilled if necessary.
4030 // Causes that MachNode::rematerialize() returns false.
4031 // - If an instruction is attributed with 'ins_should_rematerialize(true)'
4032 // then rematerialization should be enforced and a copy of the instruction
4033 // should be inserted if possible; rematerialization is not guaranteed.
4034 // Note: this may result in rematerializations in front of every use.
4035 // Causes that MachNode::rematerialize() can return true.
4036 // (optional attribute)
4037 ins_attrib ins_cannot_rematerialize(false);
4038 ins_attrib ins_should_rematerialize(false);
4039
4040 // Instruction has variable size depending on alignment.
4041 ins_attrib ins_variable_size_depending_on_alignment(false);
4042
4043 // Instruction is a nop.
4044 ins_attrib ins_is_nop(false);
4045
4046 // Instruction is mapped to a MachIfFastLock node (instead of MachFastLock).
4047 ins_attrib ins_use_mach_if_fast_lock_node(false);
4048
4049 // Field for the toc offset of a constant.
4050 //
4051 // This is needed if the toc offset is not encodable as an immediate in
4052 // the PPC load instruction. If so, the upper (hi) bits of the offset are
4053 // added to the toc, and from this a load with immediate is performed.
4054 // With postalloc expand, we get two nodes that require the same offset
4055 // but which don't know about each other. The offset is only known
4056 // when the constant is added to the constant pool during emitting.
4057 // It is generated in the 'hi'-node adding the upper bits, and saved
4058 // in this node. The 'lo'-node has a link to the 'hi'-node and reads
4059 // the offset from there when it gets encoded.
4060 ins_attrib ins_field_const_toc_offset(0);
4061 ins_attrib ins_field_const_toc_offset_hi_node(0);
4062
4063 // A field that can hold the instructions offset in the code buffer.
4064 // Set in the nodes emitter.
4065 ins_attrib ins_field_cbuf_insts_offset(-1);
4066
4067 // Fields for referencing a call's load-IC-node.
4068 // If the toc offset can not be encoded as an immediate in a load, we
4069 // use two nodes.
4070 ins_attrib ins_field_load_ic_hi_node(0);
4071 ins_attrib ins_field_load_ic_node(0);
4072
4073 //----------OPERANDS-----------------------------------------------------------
4074 // Operand definitions must precede instruction definitions for correct
4075 // parsing in the ADLC because operands constitute user defined types
4076 // which are used in instruction definitions.
4077 //
4078 // Formats are generated automatically for constants and base registers.
4079
4080 //----------Simple Operands----------------------------------------------------
4081 // Immediate Operands
4082
4083 // Integer Immediate: 32-bit
4084 operand immI() %{
4085 match(ConI);
4086 op_cost(40);
4087 format %{ %}
4088 interface(CONST_INTER);
4089 %}
4090
4091 operand immI8() %{
4092 predicate(Assembler::is_simm(n->get_int(), 8));
4093 op_cost(0);
4094 match(ConI);
4095 format %{ %}
4096 interface(CONST_INTER);
4097 %}
4098
4099 // Integer Immediate: 16-bit
4100 operand immI16() %{
4101 predicate(Assembler::is_simm(n->get_int(), 16));
4102 op_cost(0);
4103 match(ConI);
4104 format %{ %}
4105 interface(CONST_INTER);
4106 %}
4107
4108 // Integer Immediate: 32-bit, where lowest 16 bits are 0x0000.
4109 operand immIhi16() %{
4110 predicate(((n->get_int() & 0xffff0000) != 0) && ((n->get_int() & 0xffff) == 0));
4111 match(ConI);
4112 op_cost(0);
4113 format %{ %}
4114 interface(CONST_INTER);
4115 %}
4116
4117 operand immInegpow2() %{
4118 predicate(is_power_of_2_long((jlong) (julong) (juint) (-(n->get_int()))));
4119 match(ConI);
4120 op_cost(0);
4121 format %{ %}
4122 interface(CONST_INTER);
4123 %}
4124
4125 operand immIpow2minus1() %{
4126 predicate(is_power_of_2_long((((jlong) (n->get_int()))+1)));
4127 match(ConI);
4128 op_cost(0);
4129 format %{ %}
4130 interface(CONST_INTER);
4131 %}
4132
4133 operand immIpowerOf2() %{
4134 predicate(is_power_of_2_long((((jlong) (julong) (juint) (n->get_int())))));
4135 match(ConI);
4136 op_cost(0);
4137 format %{ %}
4138 interface(CONST_INTER);
4139 %}
4140
4141 // Unsigned Integer Immediate: the values 0-31
4142 operand uimmI5() %{
4143 predicate(Assembler::is_uimm(n->get_int(), 5));
4144 match(ConI);
4145 op_cost(0);
4146 format %{ %}
4147 interface(CONST_INTER);
4148 %}
4149
4150 // Unsigned Integer Immediate: 6-bit
4151 operand uimmI6() %{
4152 predicate(Assembler::is_uimm(n->get_int(), 6));
4153 match(ConI);
4154 op_cost(0);
4155 format %{ %}
4156 interface(CONST_INTER);
4157 %}
4158
4159 // Unsigned Integer Immediate: 6-bit int, greater than 32
4160 operand uimmI6_ge32() %{
4161 predicate(Assembler::is_uimm(n->get_int(), 6) && n->get_int() >= 32);
4162 match(ConI);
4163 op_cost(0);
4164 format %{ %}
4165 interface(CONST_INTER);
4166 %}
4167
4168 // Unsigned Integer Immediate: 15-bit
4169 operand uimmI15() %{
4170 predicate(Assembler::is_uimm(n->get_int(), 15));
4171 match(ConI);
4172 op_cost(0);
4173 format %{ %}
4174 interface(CONST_INTER);
4175 %}
4176
4177 // Unsigned Integer Immediate: 16-bit
4178 operand uimmI16() %{
4179 predicate(Assembler::is_uimm(n->get_int(), 16));
4180 match(ConI);
4181 op_cost(0);
4182 format %{ %}
4183 interface(CONST_INTER);
4184 %}
4185
4186 // constant 'int 0'.
4187 operand immI_0() %{
4188 predicate(n->get_int() == 0);
4189 match(ConI);
4190 op_cost(0);
4191 format %{ %}
4192 interface(CONST_INTER);
4193 %}
4194
4195 // constant 'int 1'.
4196 operand immI_1() %{
4197 predicate(n->get_int() == 1);
4198 match(ConI);
4199 op_cost(0);
4200 format %{ %}
4201 interface(CONST_INTER);
4202 %}
4203
4204 // constant 'int -1'.
4205 operand immI_minus1() %{
4206 predicate(n->get_int() == -1);
4207 match(ConI);
4208 op_cost(0);
4209 format %{ %}
4210 interface(CONST_INTER);
4211 %}
4212
4213 // int value 16.
4214 operand immI_16() %{
4215 predicate(n->get_int() == 16);
4216 match(ConI);
4217 op_cost(0);
4218 format %{ %}
4219 interface(CONST_INTER);
4220 %}
4221
4222 // int value 24.
4223 operand immI_24() %{
4224 predicate(n->get_int() == 24);
4225 match(ConI);
4226 op_cost(0);
4227 format %{ %}
4228 interface(CONST_INTER);
4229 %}
4230
4231 // Compressed oops constants
4232 // Pointer Immediate
4233 operand immN() %{
4234 match(ConN);
4235
4236 op_cost(10);
4237 format %{ %}
4238 interface(CONST_INTER);
4239 %}
4240
4241 // NULL Pointer Immediate
4242 operand immN_0() %{
4243 predicate(n->get_narrowcon() == 0);
4244 match(ConN);
4245
4246 op_cost(0);
4247 format %{ %}
4248 interface(CONST_INTER);
4249 %}
4250
4251 // Compressed klass constants
4252 operand immNKlass() %{
4253 match(ConNKlass);
4254
4255 op_cost(0);
4256 format %{ %}
4257 interface(CONST_INTER);
4258 %}
4259
4260 // This operand can be used to avoid matching of an instruct
4261 // with chain rule.
4262 operand immNKlass_NM() %{
4263 match(ConNKlass);
4264 predicate(false);
4265 op_cost(0);
4266 format %{ %}
4267 interface(CONST_INTER);
4268 %}
4269
4270 // Pointer Immediate: 64-bit
4271 operand immP() %{
4272 match(ConP);
4273 op_cost(0);
4274 format %{ %}
4275 interface(CONST_INTER);
4276 %}
4277
4278 // Operand to avoid match of loadConP.
4279 // This operand can be used to avoid matching of an instruct
4280 // with chain rule.
4281 operand immP_NM() %{
4282 match(ConP);
4283 predicate(false);
4284 op_cost(0);
4285 format %{ %}
4286 interface(CONST_INTER);
4287 %}
4288
4289 // costant 'pointer 0'.
4290 operand immP_0() %{
4291 predicate(n->get_ptr() == 0);
4292 match(ConP);
4293 op_cost(0);
4294 format %{ %}
4295 interface(CONST_INTER);
4296 %}
4297
4298 // pointer 0x0 or 0x1
4299 operand immP_0or1() %{
4300 predicate((n->get_ptr() == 0) || (n->get_ptr() == 1));
4301 match(ConP);
4302 op_cost(0);
4303 format %{ %}
4304 interface(CONST_INTER);
4305 %}
4306
4307 operand immL() %{
4308 match(ConL);
4309 op_cost(40);
4310 format %{ %}
4311 interface(CONST_INTER);
4312 %}
4313
4314 // Long Immediate: 16-bit
4315 operand immL16() %{
4316 predicate(Assembler::is_simm(n->get_long(), 16));
4317 match(ConL);
4318 op_cost(0);
4319 format %{ %}
4320 interface(CONST_INTER);
4321 %}
4322
4323 // Long Immediate: 16-bit, 4-aligned
4324 operand immL16Alg4() %{
4325 predicate(Assembler::is_simm(n->get_long(), 16) && ((n->get_long() & 0x3) == 0));
4326 match(ConL);
4327 op_cost(0);
4328 format %{ %}
4329 interface(CONST_INTER);
4330 %}
4331
4332 // Long Immediate: 32-bit, where lowest 16 bits are 0x0000.
4333 operand immL32hi16() %{
4334 predicate(Assembler::is_simm(n->get_long(), 32) && ((n->get_long() & 0xffffL) == 0L));
4335 match(ConL);
4336 op_cost(0);
4337 format %{ %}
4338 interface(CONST_INTER);
4339 %}
4340
4341 // Long Immediate: 32-bit
4342 operand immL32() %{
4343 predicate(Assembler::is_simm(n->get_long(), 32));
4344 match(ConL);
4345 op_cost(0);
4346 format %{ %}
4347 interface(CONST_INTER);
4348 %}
4349
4350 // Long Immediate: 64-bit, where highest 16 bits are not 0x0000.
4351 operand immLhighest16() %{
4352 predicate((n->get_long() & 0xffff000000000000L) != 0L && (n->get_long() & 0x0000ffffffffffffL) == 0L);
4353 match(ConL);
4354 op_cost(0);
4355 format %{ %}
4356 interface(CONST_INTER);
4357 %}
4358
4359 operand immLnegpow2() %{
4360 predicate(is_power_of_2_long((jlong)-(n->get_long())));
4361 match(ConL);
4362 op_cost(0);
4363 format %{ %}
4364 interface(CONST_INTER);
4365 %}
4366
4367 operand immLpow2minus1() %{
4368 predicate(is_power_of_2_long((((jlong) (n->get_long()))+1)) &&
4369 (n->get_long() != (jlong)0xffffffffffffffffL));
4370 match(ConL);
4371 op_cost(0);
4372 format %{ %}
4373 interface(CONST_INTER);
4374 %}
4375
4376 // constant 'long 0'.
4377 operand immL_0() %{
4378 predicate(n->get_long() == 0L);
4379 match(ConL);
4380 op_cost(0);
4381 format %{ %}
4382 interface(CONST_INTER);
4383 %}
4384
4385 // constat ' long -1'.
4386 operand immL_minus1() %{
4387 predicate(n->get_long() == -1L);
4388 match(ConL);
4389 op_cost(0);
4390 format %{ %}
4391 interface(CONST_INTER);
4392 %}
4393
4394 // Long Immediate: low 32-bit mask
4395 operand immL_32bits() %{
4396 predicate(n->get_long() == 0xFFFFFFFFL);
4397 match(ConL);
4398 op_cost(0);
4399 format %{ %}
4400 interface(CONST_INTER);
4401 %}
4402
4403 // Unsigned Long Immediate: 16-bit
4404 operand uimmL16() %{
4405 predicate(Assembler::is_uimm(n->get_long(), 16));
4406 match(ConL);
4407 op_cost(0);
4408 format %{ %}
4409 interface(CONST_INTER);
4410 %}
4411
4412 // Float Immediate
4413 operand immF() %{
4414 match(ConF);
4415 op_cost(40);
4416 format %{ %}
4417 interface(CONST_INTER);
4418 %}
4419
4420 // Float Immediate: +0.0f.
4421 operand immF_0() %{
4422 predicate(jint_cast(n->getf()) == 0);
4423 match(ConF);
4424
4425 op_cost(0);
4426 format %{ %}
4427 interface(CONST_INTER);
4428 %}
4429
4430 // Double Immediate
4431 operand immD() %{
4432 match(ConD);
4433 op_cost(40);
4434 format %{ %}
4435 interface(CONST_INTER);
4436 %}
4437
4438 // Integer Register Operands
4439 // Integer Destination Register
4440 // See definition of reg_class bits32_reg_rw.
4441 operand iRegIdst() %{
4442 constraint(ALLOC_IN_RC(bits32_reg_rw));
4443 match(RegI);
4444 match(rscratch1RegI);
4445 match(rscratch2RegI);
4446 match(rarg1RegI);
4447 match(rarg2RegI);
4448 match(rarg3RegI);
4449 match(rarg4RegI);
4450 format %{ %}
4451 interface(REG_INTER);
4452 %}
4453
4454 // Integer Source Register
4455 // See definition of reg_class bits32_reg_ro.
4456 operand iRegIsrc() %{
4457 constraint(ALLOC_IN_RC(bits32_reg_ro));
4458 match(RegI);
4459 match(rscratch1RegI);
4460 match(rscratch2RegI);
4461 match(rarg1RegI);
4462 match(rarg2RegI);
4463 match(rarg3RegI);
4464 match(rarg4RegI);
4465 format %{ %}
4466 interface(REG_INTER);
4467 %}
4468
4469 operand rscratch1RegI() %{
4470 constraint(ALLOC_IN_RC(rscratch1_bits32_reg));
4471 match(iRegIdst);
4472 format %{ %}
4473 interface(REG_INTER);
4474 %}
4475
4476 operand rscratch2RegI() %{
4477 constraint(ALLOC_IN_RC(rscratch2_bits32_reg));
4478 match(iRegIdst);
4479 format %{ %}
4480 interface(REG_INTER);
4481 %}
4482
4483 operand rarg1RegI() %{
4484 constraint(ALLOC_IN_RC(rarg1_bits32_reg));
4485 match(iRegIdst);
4486 format %{ %}
4487 interface(REG_INTER);
4488 %}
4489
4490 operand rarg2RegI() %{
4491 constraint(ALLOC_IN_RC(rarg2_bits32_reg));
4492 match(iRegIdst);
4493 format %{ %}
4494 interface(REG_INTER);
4495 %}
4496
4497 operand rarg3RegI() %{
4498 constraint(ALLOC_IN_RC(rarg3_bits32_reg));
4499 match(iRegIdst);
4500 format %{ %}
4501 interface(REG_INTER);
4502 %}
4503
4504 operand rarg4RegI() %{
4505 constraint(ALLOC_IN_RC(rarg4_bits32_reg));
4506 match(iRegIdst);
4507 format %{ %}
4508 interface(REG_INTER);
4509 %}
4510
4511 operand rarg1RegL() %{
4512 constraint(ALLOC_IN_RC(rarg1_bits64_reg));
4513 match(iRegLdst);
4514 format %{ %}
4515 interface(REG_INTER);
4516 %}
4517
4518 operand rarg2RegL() %{
4519 constraint(ALLOC_IN_RC(rarg2_bits64_reg));
4520 match(iRegLdst);
4521 format %{ %}
4522 interface(REG_INTER);
4523 %}
4524
4525 operand rarg3RegL() %{
4526 constraint(ALLOC_IN_RC(rarg3_bits64_reg));
4527 match(iRegLdst);
4528 format %{ %}
4529 interface(REG_INTER);
4530 %}
4531
4532 operand rarg4RegL() %{
4533 constraint(ALLOC_IN_RC(rarg4_bits64_reg));
4534 match(iRegLdst);
4535 format %{ %}
4536 interface(REG_INTER);
4537 %}
4538
4539 // Pointer Destination Register
4540 // See definition of reg_class bits64_reg_rw.
4541 operand iRegPdst() %{
4542 constraint(ALLOC_IN_RC(bits64_reg_rw));
4543 match(RegP);
4544 match(rscratch1RegP);
4545 match(rscratch2RegP);
4546 match(rarg1RegP);
4547 match(rarg2RegP);
4548 match(rarg3RegP);
4549 match(rarg4RegP);
4550 format %{ %}
4551 interface(REG_INTER);
4552 %}
4553
4554 // Pointer Destination Register
4555 // Operand not using r11 and r12 (killed in epilog).
4556 operand iRegPdstNoScratch() %{
4557 constraint(ALLOC_IN_RC(bits64_reg_leaf_call));
4558 match(RegP);
4559 match(rarg1RegP);
4560 match(rarg2RegP);
4561 match(rarg3RegP);
4562 match(rarg4RegP);
4563 format %{ %}
4564 interface(REG_INTER);
4565 %}
4566
4567 // Pointer Source Register
4568 // See definition of reg_class bits64_reg_ro.
4569 operand iRegPsrc() %{
4570 constraint(ALLOC_IN_RC(bits64_reg_ro));
4571 match(RegP);
4572 match(iRegPdst);
4573 match(rscratch1RegP);
4574 match(rscratch2RegP);
4575 match(rarg1RegP);
4576 match(rarg2RegP);
4577 match(rarg3RegP);
4578 match(rarg4RegP);
4579 match(threadRegP);
4580 format %{ %}
4581 interface(REG_INTER);
4582 %}
4583
4584 // Thread operand.
4585 operand threadRegP() %{
4586 constraint(ALLOC_IN_RC(thread_bits64_reg));
4587 match(iRegPdst);
4588 format %{ "R16" %}
4589 interface(REG_INTER);
4590 %}
4591
4592 operand rscratch1RegP() %{
4593 constraint(ALLOC_IN_RC(rscratch1_bits64_reg));
4594 match(iRegPdst);
4595 format %{ "R11" %}
4596 interface(REG_INTER);
4597 %}
4598
4599 operand rscratch2RegP() %{
4600 constraint(ALLOC_IN_RC(rscratch2_bits64_reg));
4601 match(iRegPdst);
4602 format %{ %}
4603 interface(REG_INTER);
4604 %}
4605
4606 operand rarg1RegP() %{
4607 constraint(ALLOC_IN_RC(rarg1_bits64_reg));
4608 match(iRegPdst);
4609 format %{ %}
4610 interface(REG_INTER);
4611 %}
4612
4613 operand rarg2RegP() %{
4614 constraint(ALLOC_IN_RC(rarg2_bits64_reg));
4615 match(iRegPdst);
4616 format %{ %}
4617 interface(REG_INTER);
4618 %}
4619
4620 operand rarg3RegP() %{
4621 constraint(ALLOC_IN_RC(rarg3_bits64_reg));
4622 match(iRegPdst);
4623 format %{ %}
4624 interface(REG_INTER);
4625 %}
4626
4627 operand rarg4RegP() %{
4628 constraint(ALLOC_IN_RC(rarg4_bits64_reg));
4629 match(iRegPdst);
4630 format %{ %}
4631 interface(REG_INTER);
4632 %}
4633
4634 operand iRegNsrc() %{
4635 constraint(ALLOC_IN_RC(bits32_reg_ro));
4636 match(RegN);
4637 match(iRegNdst);
4638
4639 format %{ %}
4640 interface(REG_INTER);
4641 %}
4642
4643 operand iRegNdst() %{
4644 constraint(ALLOC_IN_RC(bits32_reg_rw));
4645 match(RegN);
4646
4647 format %{ %}
4648 interface(REG_INTER);
4649 %}
4650
4651 // Long Destination Register
4652 // See definition of reg_class bits64_reg_rw.
4653 operand iRegLdst() %{
4654 constraint(ALLOC_IN_RC(bits64_reg_rw));
4655 match(RegL);
4656 match(rscratch1RegL);
4657 match(rscratch2RegL);
4658 format %{ %}
4659 interface(REG_INTER);
4660 %}
4661
4662 // Long Source Register
4663 // See definition of reg_class bits64_reg_ro.
4664 operand iRegLsrc() %{
4665 constraint(ALLOC_IN_RC(bits64_reg_ro));
4666 match(RegL);
4667 match(iRegLdst);
4668 match(rscratch1RegL);
4669 match(rscratch2RegL);
4670 format %{ %}
4671 interface(REG_INTER);
4672 %}
4673
4674 // Special operand for ConvL2I.
4675 operand iRegL2Isrc(iRegLsrc reg) %{
4676 constraint(ALLOC_IN_RC(bits64_reg_ro));
4677 match(ConvL2I reg);
4678 format %{ "ConvL2I($reg)" %}
4679 interface(REG_INTER)
4680 %}
4681
4682 operand rscratch1RegL() %{
4683 constraint(ALLOC_IN_RC(rscratch1_bits64_reg));
4684 match(RegL);
4685 format %{ %}
4686 interface(REG_INTER);
4687 %}
4688
4689 operand rscratch2RegL() %{
4690 constraint(ALLOC_IN_RC(rscratch2_bits64_reg));
4691 match(RegL);
4692 format %{ %}
4693 interface(REG_INTER);
4694 %}
4695
4696 // Condition Code Flag Registers
4697 operand flagsReg() %{
4698 constraint(ALLOC_IN_RC(int_flags));
4699 match(RegFlags);
4700 format %{ %}
4701 interface(REG_INTER);
4702 %}
4703
4704 // Condition Code Flag Register CR0
4705 operand flagsRegCR0() %{
4706 constraint(ALLOC_IN_RC(int_flags_CR0));
4707 match(RegFlags);
4708 format %{ "CR0" %}
4709 interface(REG_INTER);
4710 %}
4711
4712 operand flagsRegCR1() %{
4713 constraint(ALLOC_IN_RC(int_flags_CR1));
4714 match(RegFlags);
4715 format %{ "CR1" %}
4716 interface(REG_INTER);
4717 %}
4718
4719 operand flagsRegCR6() %{
4720 constraint(ALLOC_IN_RC(int_flags_CR6));
4721 match(RegFlags);
4722 format %{ "CR6" %}
4723 interface(REG_INTER);
4724 %}
4725
4726 operand regCTR() %{
4727 constraint(ALLOC_IN_RC(ctr_reg));
4728 // RegFlags should work. Introducing a RegSpecial type would cause a
4729 // lot of changes.
4730 match(RegFlags);
4731 format %{"SR_CTR" %}
4732 interface(REG_INTER);
4733 %}
4734
4735 operand regD() %{
4736 constraint(ALLOC_IN_RC(dbl_reg));
4737 match(RegD);
4738 format %{ %}
4739 interface(REG_INTER);
4740 %}
4741
4742 operand regF() %{
4743 constraint(ALLOC_IN_RC(flt_reg));
4744 match(RegF);
4745 format %{ %}
4746 interface(REG_INTER);
4747 %}
4748
4749 // Special Registers
4750
4751 // Method Register
4752 operand inline_cache_regP(iRegPdst reg) %{
4753 constraint(ALLOC_IN_RC(r19_bits64_reg)); // inline_cache_reg
4754 match(reg);
4755 format %{ %}
4756 interface(REG_INTER);
4757 %}
4758
4759 operand compiler_method_oop_regP(iRegPdst reg) %{
4760 constraint(ALLOC_IN_RC(rscratch1_bits64_reg)); // compiler_method_oop_reg
4761 match(reg);
4762 format %{ %}
4763 interface(REG_INTER);
4764 %}
4765
4766 operand interpreter_method_oop_regP(iRegPdst reg) %{
4767 constraint(ALLOC_IN_RC(r19_bits64_reg)); // interpreter_method_oop_reg
4768 match(reg);
4769 format %{ %}
4770 interface(REG_INTER);
4771 %}
4772
4773 // Operands to remove register moves in unscaled mode.
4774 // Match read/write registers with an EncodeP node if neither shift nor add are required.
4775 operand iRegP2N(iRegPsrc reg) %{
4776 predicate(false /* TODO: PPC port MatchDecodeNodes*/&& Universe::narrow_oop_shift() == 0);
4777 constraint(ALLOC_IN_RC(bits64_reg_ro));
4778 match(EncodeP reg);
4779 format %{ "$reg" %}
4780 interface(REG_INTER)
4781 %}
4782
4783 operand iRegN2P(iRegNsrc reg) %{
4784 predicate(false /* TODO: PPC port MatchDecodeNodes*/);
4785 constraint(ALLOC_IN_RC(bits32_reg_ro));
4786 match(DecodeN reg);
4787 match(DecodeNKlass reg);
4788 format %{ "$reg" %}
4789 interface(REG_INTER)
4790 %}
4791
4792 //----------Complex Operands---------------------------------------------------
4793 // Indirect Memory Reference
4794 operand indirect(iRegPsrc reg) %{
4795 constraint(ALLOC_IN_RC(bits64_reg_ro));
4796 match(reg);
4797 op_cost(100);
4798 format %{ "[$reg]" %}
4799 interface(MEMORY_INTER) %{
4800 base($reg);
4801 index(0x0);
4802 scale(0x0);
4803 disp(0x0);
4804 %}
4805 %}
4806
4807 // Indirect with Offset
4808 operand indOffset16(iRegPsrc reg, immL16 offset) %{
4809 constraint(ALLOC_IN_RC(bits64_reg_ro));
4810 match(AddP reg offset);
4811 op_cost(100);
4812 format %{ "[$reg + $offset]" %}
4813 interface(MEMORY_INTER) %{
4814 base($reg);
4815 index(0x0);
4816 scale(0x0);
4817 disp($offset);
4818 %}
4819 %}
4820
4821 // Indirect with 4-aligned Offset
4822 operand indOffset16Alg4(iRegPsrc reg, immL16Alg4 offset) %{
4823 constraint(ALLOC_IN_RC(bits64_reg_ro));
4824 match(AddP reg offset);
4825 op_cost(100);
4826 format %{ "[$reg + $offset]" %}
4827 interface(MEMORY_INTER) %{
4828 base($reg);
4829 index(0x0);
4830 scale(0x0);
4831 disp($offset);
4832 %}
4833 %}
4834
4835 //----------Complex Operands for Compressed OOPs-------------------------------
4836 // Compressed OOPs with narrow_oop_shift == 0.
4837
4838 // Indirect Memory Reference, compressed OOP
4839 operand indirectNarrow(iRegNsrc reg) %{
4840 predicate(false /* TODO: PPC port MatchDecodeNodes*/);
4841 constraint(ALLOC_IN_RC(bits64_reg_ro));
4842 match(DecodeN reg);
4843 match(DecodeNKlass reg);
4844 op_cost(100);
4845 format %{ "[$reg]" %}
4846 interface(MEMORY_INTER) %{
4847 base($reg);
4848 index(0x0);
4849 scale(0x0);
4850 disp(0x0);
4851 %}
4852 %}
4853
4854 // Indirect with Offset, compressed OOP
4855 operand indOffset16Narrow(iRegNsrc reg, immL16 offset) %{
4856 predicate(false /* TODO: PPC port MatchDecodeNodes*/);
4857 constraint(ALLOC_IN_RC(bits64_reg_ro));
4858 match(AddP (DecodeN reg) offset);
4859 match(AddP (DecodeNKlass reg) offset);
4860 op_cost(100);
4861 format %{ "[$reg + $offset]" %}
4862 interface(MEMORY_INTER) %{
4863 base($reg);
4864 index(0x0);
4865 scale(0x0);
4866 disp($offset);
4867 %}
4868 %}
4869
4870 // Indirect with 4-aligned Offset, compressed OOP
4871 operand indOffset16NarrowAlg4(iRegNsrc reg, immL16Alg4 offset) %{
4872 predicate(false /* TODO: PPC port MatchDecodeNodes*/);
4873 constraint(ALLOC_IN_RC(bits64_reg_ro));
4874 match(AddP (DecodeN reg) offset);
4875 match(AddP (DecodeNKlass reg) offset);
4876 op_cost(100);
4877 format %{ "[$reg + $offset]" %}
4878 interface(MEMORY_INTER) %{
4879 base($reg);
4880 index(0x0);
4881 scale(0x0);
4882 disp($offset);
4883 %}
4884 %}
4885
4886 //----------Special Memory Operands--------------------------------------------
4887 // Stack Slot Operand
4888 //
4889 // This operand is used for loading and storing temporary values on
4890 // the stack where a match requires a value to flow through memory.
4891 operand stackSlotI(sRegI reg) %{
4892 constraint(ALLOC_IN_RC(stack_slots));
4893 op_cost(100);
4894 //match(RegI);
4895 format %{ "[sp+$reg]" %}
4896 interface(MEMORY_INTER) %{
4897 base(0x1); // R1_SP
4898 index(0x0);
4899 scale(0x0);
4900 disp($reg); // Stack Offset
4901 %}
4902 %}
4903
4904 operand stackSlotL(sRegL reg) %{
4905 constraint(ALLOC_IN_RC(stack_slots));
4906 op_cost(100);
4907 //match(RegL);
4908 format %{ "[sp+$reg]" %}
4909 interface(MEMORY_INTER) %{
4910 base(0x1); // R1_SP
4911 index(0x0);
4912 scale(0x0);
4913 disp($reg); // Stack Offset
4914 %}
4915 %}
4916
4917 operand stackSlotP(sRegP reg) %{
4918 constraint(ALLOC_IN_RC(stack_slots));
4919 op_cost(100);
4920 //match(RegP);
4921 format %{ "[sp+$reg]" %}
4922 interface(MEMORY_INTER) %{
4923 base(0x1); // R1_SP
4924 index(0x0);
4925 scale(0x0);
4926 disp($reg); // Stack Offset
4927 %}
4928 %}
4929
4930 operand stackSlotF(sRegF reg) %{
4931 constraint(ALLOC_IN_RC(stack_slots));
4932 op_cost(100);
4933 //match(RegF);
4934 format %{ "[sp+$reg]" %}
4935 interface(MEMORY_INTER) %{
4936 base(0x1); // R1_SP
4937 index(0x0);
4938 scale(0x0);
4939 disp($reg); // Stack Offset
4940 %}
4941 %}
4942
4943 operand stackSlotD(sRegD reg) %{
4944 constraint(ALLOC_IN_RC(stack_slots));
4945 op_cost(100);
4946 //match(RegD);
4947 format %{ "[sp+$reg]" %}
4948 interface(MEMORY_INTER) %{
4949 base(0x1); // R1_SP
4950 index(0x0);
4951 scale(0x0);
4952 disp($reg); // Stack Offset
4953 %}
4954 %}
4955
4956 // Operands for expressing Control Flow
4957 // NOTE: Label is a predefined operand which should not be redefined in
4958 // the AD file. It is generically handled within the ADLC.
4959
4960 //----------Conditional Branch Operands----------------------------------------
4961 // Comparison Op
4962 //
4963 // This is the operation of the comparison, and is limited to the
4964 // following set of codes: L (<), LE (<=), G (>), GE (>=), E (==), NE
4965 // (!=).
4966 //
4967 // Other attributes of the comparison, such as unsignedness, are specified
4968 // by the comparison instruction that sets a condition code flags register.
4969 // That result is represented by a flags operand whose subtype is appropriate
4970 // to the unsignedness (etc.) of the comparison.
4971 //
4972 // Later, the instruction which matches both the Comparison Op (a Bool) and
4973 // the flags (produced by the Cmp) specifies the coding of the comparison op
4974 // by matching a specific subtype of Bool operand below.
4975
4976 // When used for floating point comparisons: unordered same as less.
4977 operand cmpOp() %{
4978 match(Bool);
4979 format %{ "" %}
4980 interface(COND_INTER) %{
4981 // BO only encodes bit 4 of bcondCRbiIsX, as bits 1-3 are always '100'.
4982 // BO & BI
4983 equal(0xA); // 10 10: bcondCRbiIs1 & Condition::equal
4984 not_equal(0x2); // 00 10: bcondCRbiIs0 & Condition::equal
4985 less(0x8); // 10 00: bcondCRbiIs1 & Condition::less
4986 greater_equal(0x0); // 00 00: bcondCRbiIs0 & Condition::less
4987 less_equal(0x1); // 00 01: bcondCRbiIs0 & Condition::greater
4988 greater(0x9); // 10 01: bcondCRbiIs1 & Condition::greater
4989 overflow(0xB); // 10 11: bcondCRbiIs1 & Condition::summary_overflow
4990 no_overflow(0x3); // 00 11: bcondCRbiIs0 & Condition::summary_overflow
4991 %}
4992 %}
4993
4994 //----------OPERAND CLASSES----------------------------------------------------
4995 // Operand Classes are groups of operands that are used to simplify
4996 // instruction definitions by not requiring the AD writer to specify
4997 // seperate instructions for every form of operand when the
4998 // instruction accepts multiple operand types with the same basic
4999 // encoding and format. The classic case of this is memory operands.
5000 // Indirect is not included since its use is limited to Compare & Swap.
5001
5002 opclass memory(indirect, indOffset16 /*, indIndex, tlsReference*/, indirectNarrow, indOffset16Narrow);
5003 // Memory operand where offsets are 4-aligned. Required for ld, std.
5004 opclass memoryAlg4(indirect, indOffset16Alg4, indirectNarrow, indOffset16NarrowAlg4);
5005 opclass indirectMemory(indirect, indirectNarrow);
5006
5007 // Special opclass for I and ConvL2I.
5008 opclass iRegIsrc_iRegL2Isrc(iRegIsrc, iRegL2Isrc);
5009
5010 // Operand classes to match encode and decode. iRegN_P2N is only used
5011 // for storeN. I have never seen an encode node elsewhere.
5012 opclass iRegN_P2N(iRegNsrc, iRegP2N);
5013 opclass iRegP_N2P(iRegPsrc, iRegN2P);
5014
5015 //----------PIPELINE-----------------------------------------------------------
5016
5017 pipeline %{
5018
5019 // See J.M.Tendler et al. "Power4 system microarchitecture", IBM
5020 // J. Res. & Dev., No. 1, Jan. 2002.
5021
5022 //----------ATTRIBUTES---------------------------------------------------------
5023 attributes %{
5024
5025 // Power4 instructions are of fixed length.
5026 fixed_size_instructions;
5027
5028 // TODO: if `bundle' means number of instructions fetched
5029 // per cycle, this is 8. If `bundle' means Power4 `group', that is
5030 // max instructions issued per cycle, this is 5.
5031 max_instructions_per_bundle = 8;
5032
5033 // A Power4 instruction is 4 bytes long.
5034 instruction_unit_size = 4;
5035
5036 // The Power4 processor fetches 64 bytes...
5037 instruction_fetch_unit_size = 64;
5038
5039 // ...in one line
5040 instruction_fetch_units = 1
5041
5042 // Unused, list one so that array generated by adlc is not empty.
5043 // Aix compiler chokes if _nop_count = 0.
5044 nops(fxNop);
5045 %}
5046
5047 //----------RESOURCES----------------------------------------------------------
5048 // Resources are the functional units available to the machine
5049 resources(
5050 PPC_BR, // branch unit
5051 PPC_CR, // condition unit
5052 PPC_FX1, // integer arithmetic unit 1
5053 PPC_FX2, // integer arithmetic unit 2
5054 PPC_LDST1, // load/store unit 1
5055 PPC_LDST2, // load/store unit 2
5056 PPC_FP1, // float arithmetic unit 1
5057 PPC_FP2, // float arithmetic unit 2
5058 PPC_LDST = PPC_LDST1 | PPC_LDST2,
5059 PPC_FX = PPC_FX1 | PPC_FX2,
5060 PPC_FP = PPC_FP1 | PPC_FP2
5061 );
5062
5063 //----------PIPELINE DESCRIPTION-----------------------------------------------
5064 // Pipeline Description specifies the stages in the machine's pipeline
5065 pipe_desc(
5066 // Power4 longest pipeline path
5067 PPC_IF, // instruction fetch
5068 PPC_IC,
5069 //PPC_BP, // branch prediction
5070 PPC_D0, // decode
5071 PPC_D1, // decode
5072 PPC_D2, // decode
5073 PPC_D3, // decode
5074 PPC_Xfer1,
5075 PPC_GD, // group definition
5076 PPC_MP, // map
5077 PPC_ISS, // issue
5078 PPC_RF, // resource fetch
5079 PPC_EX1, // execute (all units)
5080 PPC_EX2, // execute (FP, LDST)
5081 PPC_EX3, // execute (FP, LDST)
5082 PPC_EX4, // execute (FP)
5083 PPC_EX5, // execute (FP)
5084 PPC_EX6, // execute (FP)
5085 PPC_WB, // write back
5086 PPC_Xfer2,
5087 PPC_CP
5088 );
5089
5090 //----------PIPELINE CLASSES---------------------------------------------------
5091 // Pipeline Classes describe the stages in which input and output are
5092 // referenced by the hardware pipeline.
5093
5094 // Simple pipeline classes.
5095
5096 // Default pipeline class.
5097 pipe_class pipe_class_default() %{
5098 single_instruction;
5099 fixed_latency(2);
5100 %}
5101
5102 // Pipeline class for empty instructions.
5103 pipe_class pipe_class_empty() %{
5104 single_instruction;
5105 fixed_latency(0);
5106 %}
5107
5108 // Pipeline class for compares.
5109 pipe_class pipe_class_compare() %{
5110 single_instruction;
5111 fixed_latency(16);
5112 %}
5113
5114 // Pipeline class for traps.
5115 pipe_class pipe_class_trap() %{
5116 single_instruction;
5117 fixed_latency(100);
5118 %}
5119
5120 // Pipeline class for memory operations.
5121 pipe_class pipe_class_memory() %{
5122 single_instruction;
5123 fixed_latency(16);
5124 %}
5125
5126 // Pipeline class for call.
5127 pipe_class pipe_class_call() %{
5128 single_instruction;
5129 fixed_latency(100);
5130 %}
5131
5132 // Define the class for the Nop node.
5133 define %{
5134 MachNop = pipe_class_default;
5135 %}
5136
5137 %}
5138
5139 //----------INSTRUCTIONS-------------------------------------------------------
5140
5141 // Naming of instructions:
5142 // opA_operB / opA_operB_operC:
5143 // Operation 'op' with one or two source operands 'oper'. Result
5144 // type is A, source operand types are B and C.
5145 // Iff A == B == C, B and C are left out.
5146 //
5147 // The instructions are ordered according to the following scheme:
5148 // - loads
5149 // - load constants
5150 // - prefetch
5151 // - store
5152 // - encode/decode
5153 // - membar
5154 // - conditional moves
5155 // - compare & swap
5156 // - arithmetic and logic operations
5157 // * int: Add, Sub, Mul, Div, Mod
5158 // * int: lShift, arShift, urShift, rot
5159 // * float: Add, Sub, Mul, Div
5160 // * and, or, xor ...
5161 // - register moves: float <-> int, reg <-> stack, repl
5162 // - cast (high level type cast, XtoP, castPP, castII, not_null etc.
5163 // - conv (low level type cast requiring bit changes (sign extend etc)
5164 // - compares, range & zero checks.
5165 // - branches
5166 // - complex operations, intrinsics, min, max, replicate
5167 // - lock
5168 // - Calls
5169 //
5170 // If there are similar instructions with different types they are sorted:
5171 // int before float
5172 // small before big
5173 // signed before unsigned
5174 // e.g., loadS before loadUS before loadI before loadF.
5175
5176
5177 //----------Load/Store Instructions--------------------------------------------
5178
5179 //----------Load Instructions--------------------------------------------------
5180
5181 // Converts byte to int.
5182 // As convB2I_reg, but without match rule. The match rule of convB2I_reg
5183 // reuses the 'amount' operand, but adlc expects that operand specification
5184 // and operands in match rule are equivalent.
5185 instruct convB2I_reg_2(iRegIdst dst, iRegIsrc src) %{
5186 effect(DEF dst, USE src);
5187 format %{ "EXTSB $dst, $src \t// byte->int" %}
5188 size(4);
5189 ins_encode %{
5190 // TODO: PPC port $archOpcode(ppc64Opcode_extsb);
5191 __ extsb($dst$$Register, $src$$Register);
5192 %}
5193 ins_pipe(pipe_class_default);
5194 %}
5195
5196 instruct loadUB_indirect(iRegIdst dst, indirectMemory mem) %{
5197 // match-rule, false predicate
5198 match(Set dst (LoadB mem));
5199 predicate(false);
5200
5201 format %{ "LBZ $dst, $mem" %}
5202 size(4);
5203 ins_encode( enc_lbz(dst, mem) );
5204 ins_pipe(pipe_class_memory);
5205 %}
5206
5207 instruct loadUB_indirect_ac(iRegIdst dst, indirectMemory mem) %{
5208 // match-rule, false predicate
5209 match(Set dst (LoadB mem));
5210 predicate(false);
5211
5212 format %{ "LBZ $dst, $mem\n\t"
5213 "TWI $dst\n\t"
5214 "ISYNC" %}
5215 size(12);
5216 ins_encode( enc_lbz_ac(dst, mem) );
5217 ins_pipe(pipe_class_memory);
5218 %}
5219
5220 // Load Byte (8bit signed). LoadB = LoadUB + ConvUB2B.
5221 instruct loadB_indirect_Ex(iRegIdst dst, indirectMemory mem) %{
5222 match(Set dst (LoadB mem));
5223 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5224 ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5225 expand %{
5226 iRegIdst tmp;
5227 loadUB_indirect(tmp, mem);
5228 convB2I_reg_2(dst, tmp);
5229 %}
5230 %}
5231
5232 instruct loadB_indirect_ac_Ex(iRegIdst dst, indirectMemory mem) %{
5233 match(Set dst (LoadB mem));
5234 ins_cost(3*MEMORY_REF_COST + DEFAULT_COST);
5235 expand %{
5236 iRegIdst tmp;
5237 loadUB_indirect_ac(tmp, mem);
5238 convB2I_reg_2(dst, tmp);
5239 %}
5240 %}
5241
5242 instruct loadUB_indOffset16(iRegIdst dst, indOffset16 mem) %{
5243 // match-rule, false predicate
5244 match(Set dst (LoadB mem));
5245 predicate(false);
5246
5247 format %{ "LBZ $dst, $mem" %}
5248 size(4);
5249 ins_encode( enc_lbz(dst, mem) );
5250 ins_pipe(pipe_class_memory);
5251 %}
5252
5253 instruct loadUB_indOffset16_ac(iRegIdst dst, indOffset16 mem) %{
5254 // match-rule, false predicate
5255 match(Set dst (LoadB mem));
5256 predicate(false);
5257
5258 format %{ "LBZ $dst, $mem\n\t"
5259 "TWI $dst\n\t"
5260 "ISYNC" %}
5261 size(12);
5262 ins_encode( enc_lbz_ac(dst, mem) );
5263 ins_pipe(pipe_class_memory);
5264 %}
5265
5266 // Load Byte (8bit signed). LoadB = LoadUB + ConvUB2B.
5267 instruct loadB_indOffset16_Ex(iRegIdst dst, indOffset16 mem) %{
5268 match(Set dst (LoadB mem));
5269 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5270 ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5271
5272 expand %{
5273 iRegIdst tmp;
5274 loadUB_indOffset16(tmp, mem);
5275 convB2I_reg_2(dst, tmp);
5276 %}
5277 %}
5278
5279 instruct loadB_indOffset16_ac_Ex(iRegIdst dst, indOffset16 mem) %{
5280 match(Set dst (LoadB mem));
5281 ins_cost(3*MEMORY_REF_COST + DEFAULT_COST);
5282
5283 expand %{
5284 iRegIdst tmp;
5285 loadUB_indOffset16_ac(tmp, mem);
5286 convB2I_reg_2(dst, tmp);
5287 %}
5288 %}
5289
5290 // Load Unsigned Byte (8bit UNsigned) into an int reg.
5291 instruct loadUB(iRegIdst dst, memory mem) %{
5292 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5293 match(Set dst (LoadUB mem));
5294 ins_cost(MEMORY_REF_COST);
5295
5296 format %{ "LBZ $dst, $mem \t// byte, zero-extend to int" %}
5297 size(4);
5298 ins_encode( enc_lbz(dst, mem) );
5299 ins_pipe(pipe_class_memory);
5300 %}
5301
5302 // Load Unsigned Byte (8bit UNsigned) acquire.
5303 instruct loadUB_ac(iRegIdst dst, memory mem) %{
5304 match(Set dst (LoadUB mem));
5305 ins_cost(3*MEMORY_REF_COST);
5306
5307 format %{ "LBZ $dst, $mem \t// byte, zero-extend to int, acquire\n\t"
5308 "TWI $dst\n\t"
5309 "ISYNC" %}
5310 size(12);
5311 ins_encode( enc_lbz_ac(dst, mem) );
5312 ins_pipe(pipe_class_memory);
5313 %}
5314
5315 // Load Unsigned Byte (8bit UNsigned) into a Long Register.
5316 instruct loadUB2L(iRegLdst dst, memory mem) %{
5317 match(Set dst (ConvI2L (LoadUB mem)));
5318 predicate(_kids[0]->_leaf->as_Load()->is_unordered() || followed_by_acquire(_kids[0]->_leaf));
5319 ins_cost(MEMORY_REF_COST);
5320
5321 format %{ "LBZ $dst, $mem \t// byte, zero-extend to long" %}
5322 size(4);
5323 ins_encode( enc_lbz(dst, mem) );
5324 ins_pipe(pipe_class_memory);
5325 %}
5326
5327 instruct loadUB2L_ac(iRegLdst dst, memory mem) %{
5328 match(Set dst (ConvI2L (LoadUB mem)));
5329 ins_cost(3*MEMORY_REF_COST);
5330
5331 format %{ "LBZ $dst, $mem \t// byte, zero-extend to long, acquire\n\t"
5332 "TWI $dst\n\t"
5333 "ISYNC" %}
5334 size(12);
5335 ins_encode( enc_lbz_ac(dst, mem) );
5336 ins_pipe(pipe_class_memory);
5337 %}
5338
5339 // Load Short (16bit signed)
5340 instruct loadS(iRegIdst dst, memory mem) %{
5341 match(Set dst (LoadS mem));
5342 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5343 ins_cost(MEMORY_REF_COST);
5344
5345 format %{ "LHA $dst, $mem" %}
5346 size(4);
5347 ins_encode %{
5348 // TODO: PPC port $archOpcode(ppc64Opcode_lha);
5349 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5350 __ lha($dst$$Register, Idisp, $mem$$base$$Register);
5351 %}
5352 ins_pipe(pipe_class_memory);
5353 %}
5354
5355 // Load Short (16bit signed) acquire.
5356 instruct loadS_ac(iRegIdst dst, memory mem) %{
5357 match(Set dst (LoadS mem));
5358 ins_cost(3*MEMORY_REF_COST);
5359
5360 format %{ "LHA $dst, $mem\t acquire\n\t"
5361 "TWI $dst\n\t"
5362 "ISYNC" %}
5363 size(12);
5364 ins_encode %{
5365 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
5366 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5367 __ lha($dst$$Register, Idisp, $mem$$base$$Register);
5368 __ twi_0($dst$$Register);
5369 __ isync();
5370 %}
5371 ins_pipe(pipe_class_memory);
5372 %}
5373
5374 // Load Char (16bit unsigned)
5375 instruct loadUS(iRegIdst dst, memory mem) %{
5376 match(Set dst (LoadUS mem));
5377 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5378 ins_cost(MEMORY_REF_COST);
5379
5380 format %{ "LHZ $dst, $mem" %}
5381 size(4);
5382 ins_encode( enc_lhz(dst, mem) );
5383 ins_pipe(pipe_class_memory);
5384 %}
5385
5386 // Load Char (16bit unsigned) acquire.
5387 instruct loadUS_ac(iRegIdst dst, memory mem) %{
5388 match(Set dst (LoadUS mem));
5389 ins_cost(3*MEMORY_REF_COST);
5390
5391 format %{ "LHZ $dst, $mem \t// acquire\n\t"
5392 "TWI $dst\n\t"
5393 "ISYNC" %}
5394 size(12);
5395 ins_encode( enc_lhz_ac(dst, mem) );
5396 ins_pipe(pipe_class_memory);
5397 %}
5398
5399 // Load Unsigned Short/Char (16bit UNsigned) into a Long Register.
5400 instruct loadUS2L(iRegLdst dst, memory mem) %{
5401 match(Set dst (ConvI2L (LoadUS mem)));
5402 predicate(_kids[0]->_leaf->as_Load()->is_unordered() || followed_by_acquire(_kids[0]->_leaf));
5403 ins_cost(MEMORY_REF_COST);
5404
5405 format %{ "LHZ $dst, $mem \t// short, zero-extend to long" %}
5406 size(4);
5407 ins_encode( enc_lhz(dst, mem) );
5408 ins_pipe(pipe_class_memory);
5409 %}
5410
5411 // Load Unsigned Short/Char (16bit UNsigned) into a Long Register acquire.
5412 instruct loadUS2L_ac(iRegLdst dst, memory mem) %{
5413 match(Set dst (ConvI2L (LoadUS mem)));
5414 ins_cost(3*MEMORY_REF_COST);
5415
5416 format %{ "LHZ $dst, $mem \t// short, zero-extend to long, acquire\n\t"
5417 "TWI $dst\n\t"
5418 "ISYNC" %}
5419 size(12);
5420 ins_encode( enc_lhz_ac(dst, mem) );
5421 ins_pipe(pipe_class_memory);
5422 %}
5423
5424 // Load Integer.
5425 instruct loadI(iRegIdst dst, memory mem) %{
5426 match(Set dst (LoadI mem));
5427 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5428 ins_cost(MEMORY_REF_COST);
5429
5430 format %{ "LWZ $dst, $mem" %}
5431 size(4);
5432 ins_encode( enc_lwz(dst, mem) );
5433 ins_pipe(pipe_class_memory);
5434 %}
5435
5436 // Load Integer acquire.
5437 instruct loadI_ac(iRegIdst dst, memory mem) %{
5438 match(Set dst (LoadI mem));
5439 ins_cost(3*MEMORY_REF_COST);
5440
5441 format %{ "LWZ $dst, $mem \t// load acquire\n\t"
5442 "TWI $dst\n\t"
5443 "ISYNC" %}
5444 size(12);
5445 ins_encode( enc_lwz_ac(dst, mem) );
5446 ins_pipe(pipe_class_memory);
5447 %}
5448
5449 // Match loading integer and casting it to unsigned int in
5450 // long register.
5451 // LoadI + ConvI2L + AndL 0xffffffff.
5452 instruct loadUI2L(iRegLdst dst, memory mem, immL_32bits mask) %{
5453 match(Set dst (AndL (ConvI2L (LoadI mem)) mask));
5454 predicate(_kids[0]->_kids[0]->_leaf->as_Load()->is_unordered());
5455 ins_cost(MEMORY_REF_COST);
5456
5457 format %{ "LWZ $dst, $mem \t// zero-extend to long" %}
5458 size(4);
5459 ins_encode( enc_lwz(dst, mem) );
5460 ins_pipe(pipe_class_memory);
5461 %}
5462
5463 // Match loading integer and casting it to long.
5464 instruct loadI2L(iRegLdst dst, memory mem) %{
5465 match(Set dst (ConvI2L (LoadI mem)));
5466 predicate(_kids[0]->_leaf->as_Load()->is_unordered());
5467 ins_cost(MEMORY_REF_COST);
5468
5469 format %{ "LWA $dst, $mem \t// loadI2L" %}
5470 size(4);
5471 ins_encode %{
5472 // TODO: PPC port $archOpcode(ppc64Opcode_lwa);
5473 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5474 __ lwa($dst$$Register, Idisp, $mem$$base$$Register);
5475 %}
5476 ins_pipe(pipe_class_memory);
5477 %}
5478
5479 // Match loading integer and casting it to long - acquire.
5480 instruct loadI2L_ac(iRegLdst dst, memory mem) %{
5481 match(Set dst (ConvI2L (LoadI mem)));
5482 ins_cost(3*MEMORY_REF_COST);
5483
5484 format %{ "LWA $dst, $mem \t// loadI2L acquire"
5485 "TWI $dst\n\t"
5486 "ISYNC" %}
5487 size(12);
5488 ins_encode %{
5489 // TODO: PPC port $archOpcode(ppc64Opcode_lwa);
5490 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5491 __ lwa($dst$$Register, Idisp, $mem$$base$$Register);
5492 __ twi_0($dst$$Register);
5493 __ isync();
5494 %}
5495 ins_pipe(pipe_class_memory);
5496 %}
5497
5498 // Load Long - aligned
5499 instruct loadL(iRegLdst dst, memoryAlg4 mem) %{
5500 match(Set dst (LoadL mem));
5501 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5502 ins_cost(MEMORY_REF_COST);
5503
5504 format %{ "LD $dst, $mem \t// long" %}
5505 size(4);
5506 ins_encode( enc_ld(dst, mem) );
5507 ins_pipe(pipe_class_memory);
5508 %}
5509
5510 // Load Long - aligned acquire.
5511 instruct loadL_ac(iRegLdst dst, memoryAlg4 mem) %{
5512 match(Set dst (LoadL mem));
5513 ins_cost(3*MEMORY_REF_COST);
5514
5515 format %{ "LD $dst, $mem \t// long acquire\n\t"
5516 "TWI $dst\n\t"
5517 "ISYNC" %}
5518 size(12);
5519 ins_encode( enc_ld_ac(dst, mem) );
5520 ins_pipe(pipe_class_memory);
5521 %}
5522
5523 // Load Long - UNaligned
5524 instruct loadL_unaligned(iRegLdst dst, memoryAlg4 mem) %{
5525 match(Set dst (LoadL_unaligned mem));
5526 // predicate(...) // Unaligned_ac is not needed (and wouldn't make sense).
5527 ins_cost(MEMORY_REF_COST);
5528
5529 format %{ "LD $dst, $mem \t// unaligned long" %}
5530 size(4);
5531 ins_encode( enc_ld(dst, mem) );
5532 ins_pipe(pipe_class_memory);
5533 %}
5534
5535 // Load nodes for superwords
5536
5537 // Load Aligned Packed Byte
5538 instruct loadV8(iRegLdst dst, memoryAlg4 mem) %{
5539 predicate(n->as_LoadVector()->memory_size() == 8);
5540 match(Set dst (LoadVector mem));
5541 ins_cost(MEMORY_REF_COST);
5542
5543 format %{ "LD $dst, $mem \t// load 8-byte Vector" %}
5544 size(4);
5545 ins_encode( enc_ld(dst, mem) );
5546 ins_pipe(pipe_class_memory);
5547 %}
5548
5549 // Load Range, range = array length (=jint)
5550 instruct loadRange(iRegIdst dst, memory mem) %{
5551 match(Set dst (LoadRange mem));
5552 ins_cost(MEMORY_REF_COST);
5553
5554 format %{ "LWZ $dst, $mem \t// range" %}
5555 size(4);
5556 ins_encode( enc_lwz(dst, mem) );
5557 ins_pipe(pipe_class_memory);
5558 %}
5559
5560 // Load Compressed Pointer
5561 instruct loadN(iRegNdst dst, memory mem) %{
5562 match(Set dst (LoadN mem));
5563 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5564 ins_cost(MEMORY_REF_COST);
5565
5566 format %{ "LWZ $dst, $mem \t// load compressed ptr" %}
5567 size(4);
5568 ins_encode( enc_lwz(dst, mem) );
5569 ins_pipe(pipe_class_memory);
5570 %}
5571
5572 // Load Compressed Pointer acquire.
5573 instruct loadN_ac(iRegNdst dst, memory mem) %{
5574 match(Set dst (LoadN mem));
5575 ins_cost(3*MEMORY_REF_COST);
5576
5577 format %{ "LWZ $dst, $mem \t// load acquire compressed ptr\n\t"
5578 "TWI $dst\n\t"
5579 "ISYNC" %}
5580 size(12);
5581 ins_encode( enc_lwz_ac(dst, mem) );
5582 ins_pipe(pipe_class_memory);
5583 %}
5584
5585 // Load Compressed Pointer and decode it if narrow_oop_shift == 0.
5586 instruct loadN2P_unscaled(iRegPdst dst, memory mem) %{
5587 match(Set dst (DecodeN (LoadN mem)));
5588 predicate(_kids[0]->_leaf->as_Load()->is_unordered() && Universe::narrow_oop_shift() == 0);
5589 ins_cost(MEMORY_REF_COST);
5590
5591 format %{ "LWZ $dst, $mem \t// DecodeN (unscaled)" %}
5592 size(4);
5593 ins_encode( enc_lwz(dst, mem) );
5594 ins_pipe(pipe_class_memory);
5595 %}
5596
5597 // Load Pointer
5598 instruct loadP(iRegPdst dst, memoryAlg4 mem) %{
5599 match(Set dst (LoadP mem));
5600 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5601 ins_cost(MEMORY_REF_COST);
5602
5603 format %{ "LD $dst, $mem \t// ptr" %}
5604 size(4);
5605 ins_encode( enc_ld(dst, mem) );
5606 ins_pipe(pipe_class_memory);
5607 %}
5608
5609 // Load Pointer acquire.
5610 instruct loadP_ac(iRegPdst dst, memoryAlg4 mem) %{
5611 match(Set dst (LoadP mem));
5612 ins_cost(3*MEMORY_REF_COST);
5613
5614 format %{ "LD $dst, $mem \t// ptr acquire\n\t"
5615 "TWI $dst\n\t"
5616 "ISYNC" %}
5617 size(12);
5618 ins_encode( enc_ld_ac(dst, mem) );
5619 ins_pipe(pipe_class_memory);
5620 %}
5621
5622 // LoadP + CastP2L
5623 instruct loadP2X(iRegLdst dst, memoryAlg4 mem) %{
5624 match(Set dst (CastP2X (LoadP mem)));
5625 predicate(_kids[0]->_leaf->as_Load()->is_unordered());
5626 ins_cost(MEMORY_REF_COST);
5627
5628 format %{ "LD $dst, $mem \t// ptr + p2x" %}
5629 size(4);
5630 ins_encode( enc_ld(dst, mem) );
5631 ins_pipe(pipe_class_memory);
5632 %}
5633
5634 // Load compressed klass pointer.
5635 instruct loadNKlass(iRegNdst dst, memory mem) %{
5636 match(Set dst (LoadNKlass mem));
5637 ins_cost(MEMORY_REF_COST);
5638
5639 format %{ "LWZ $dst, $mem \t// compressed klass ptr" %}
5640 size(4);
5641 ins_encode( enc_lwz(dst, mem) );
5642 ins_pipe(pipe_class_memory);
5643 %}
5644
5645 // Load Klass Pointer
5646 instruct loadKlass(iRegPdst dst, memoryAlg4 mem) %{
5647 match(Set dst (LoadKlass mem));
5648 ins_cost(MEMORY_REF_COST);
5649
5650 format %{ "LD $dst, $mem \t// klass ptr" %}
5651 size(4);
5652 ins_encode( enc_ld(dst, mem) );
5653 ins_pipe(pipe_class_memory);
5654 %}
5655
5656 // Load Float
5657 instruct loadF(regF dst, memory mem) %{
5658 match(Set dst (LoadF mem));
5659 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5660 ins_cost(MEMORY_REF_COST);
5661
5662 format %{ "LFS $dst, $mem" %}
5663 size(4);
5664 ins_encode %{
5665 // TODO: PPC port $archOpcode(ppc64Opcode_lfs);
5666 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5667 __ lfs($dst$$FloatRegister, Idisp, $mem$$base$$Register);
5668 %}
5669 ins_pipe(pipe_class_memory);
5670 %}
5671
5672 // Load Float acquire.
5673 instruct loadF_ac(regF dst, memory mem) %{
5674 match(Set dst (LoadF mem));
5675 ins_cost(3*MEMORY_REF_COST);
5676
5677 format %{ "LFS $dst, $mem \t// acquire\n\t"
5678 "FCMPU cr0, $dst, $dst\n\t"
5679 "BNE cr0, next\n"
5680 "next:\n\t"
5681 "ISYNC" %}
5682 size(16);
5683 ins_encode %{
5684 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
5685 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5686 Label next;
5687 __ lfs($dst$$FloatRegister, Idisp, $mem$$base$$Register);
5688 __ fcmpu(CCR0, $dst$$FloatRegister, $dst$$FloatRegister);
5689 __ bne(CCR0, next);
5690 __ bind(next);
5691 __ isync();
5692 %}
5693 ins_pipe(pipe_class_memory);
5694 %}
5695
5696 // Load Double - aligned
5697 instruct loadD(regD dst, memory mem) %{
5698 match(Set dst (LoadD mem));
5699 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5700 ins_cost(MEMORY_REF_COST);
5701
5702 format %{ "LFD $dst, $mem" %}
5703 size(4);
5704 ins_encode( enc_lfd(dst, mem) );
5705 ins_pipe(pipe_class_memory);
5706 %}
5707
5708 // Load Double - aligned acquire.
5709 instruct loadD_ac(regD dst, memory mem) %{
5710 match(Set dst (LoadD mem));
5711 ins_cost(3*MEMORY_REF_COST);
5712
5713 format %{ "LFD $dst, $mem \t// acquire\n\t"
5714 "FCMPU cr0, $dst, $dst\n\t"
5715 "BNE cr0, next\n"
5716 "next:\n\t"
5717 "ISYNC" %}
5718 size(16);
5719 ins_encode %{
5720 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
5721 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5722 Label next;
5723 __ lfd($dst$$FloatRegister, Idisp, $mem$$base$$Register);
5724 __ fcmpu(CCR0, $dst$$FloatRegister, $dst$$FloatRegister);
5725 __ bne(CCR0, next);
5726 __ bind(next);
5727 __ isync();
5728 %}
5729 ins_pipe(pipe_class_memory);
5730 %}
5731
5732 // Load Double - UNaligned
5733 instruct loadD_unaligned(regD dst, memory mem) %{
5734 match(Set dst (LoadD_unaligned mem));
5735 // predicate(...) // Unaligned_ac is not needed (and wouldn't make sense).
5736 ins_cost(MEMORY_REF_COST);
5737
5738 format %{ "LFD $dst, $mem" %}
5739 size(4);
5740 ins_encode( enc_lfd(dst, mem) );
5741 ins_pipe(pipe_class_memory);
5742 %}
5743
5744 //----------Constants--------------------------------------------------------
5745
5746 // Load MachConstantTableBase: add hi offset to global toc.
5747 // TODO: Handle hidden register r29 in bundler!
5748 instruct loadToc_hi(iRegLdst dst) %{
5749 effect(DEF dst);
5750 ins_cost(DEFAULT_COST);
5751
5752 format %{ "ADDIS $dst, R29, DISP.hi \t// load TOC hi" %}
5753 size(4);
5754 ins_encode %{
5755 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
5756 __ calculate_address_from_global_toc_hi16only($dst$$Register, __ method_toc());
5757 %}
5758 ins_pipe(pipe_class_default);
5759 %}
5760
5761 // Load MachConstantTableBase: add lo offset to global toc.
5762 instruct loadToc_lo(iRegLdst dst, iRegLdst src) %{
5763 effect(DEF dst, USE src);
5764 ins_cost(DEFAULT_COST);
5765
5766 format %{ "ADDI $dst, $src, DISP.lo \t// load TOC lo" %}
5767 size(4);
5768 ins_encode %{
5769 // TODO: PPC port $archOpcode(ppc64Opcode_ori);
5770 __ calculate_address_from_global_toc_lo16only($dst$$Register, __ method_toc());
5771 %}
5772 ins_pipe(pipe_class_default);
5773 %}
5774
5775 // Load 16-bit integer constant 0xssss????
5776 instruct loadConI16(iRegIdst dst, immI16 src) %{
5777 match(Set dst src);
5778
5779 format %{ "LI $dst, $src" %}
5780 size(4);
5781 ins_encode %{
5782 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
5783 __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF)));
5784 %}
5785 ins_pipe(pipe_class_default);
5786 %}
5787
5788 // Load integer constant 0x????0000
5789 instruct loadConIhi16(iRegIdst dst, immIhi16 src) %{
5790 match(Set dst src);
5791 ins_cost(DEFAULT_COST);
5792
5793 format %{ "LIS $dst, $src.hi" %}
5794 size(4);
5795 ins_encode %{
5796 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
5797 // Lis sign extends 16-bit src then shifts it 16 bit to the left.
5798 __ lis($dst$$Register, (int)((short)(($src$$constant & 0xFFFF0000) >> 16)));
5799 %}
5800 ins_pipe(pipe_class_default);
5801 %}
5802
5803 // Part 2 of loading 32 bit constant: hi16 is is src1 (properly shifted
5804 // and sign extended), this adds the low 16 bits.
5805 instruct loadConI32_lo16(iRegIdst dst, iRegIsrc src1, immI16 src2) %{
5806 // no match-rule, false predicate
5807 effect(DEF dst, USE src1, USE src2);
5808 predicate(false);
5809
5810 format %{ "ORI $dst, $src1.hi, $src2.lo" %}
5811 size(4);
5812 ins_encode %{
5813 // TODO: PPC port $archOpcode(ppc64Opcode_ori);
5814 __ ori($dst$$Register, $src1$$Register, ($src2$$constant) & 0xFFFF);
5815 %}
5816 ins_pipe(pipe_class_default);
5817 %}
5818
5819 instruct loadConI_Ex(iRegIdst dst, immI src) %{
5820 match(Set dst src);
5821 ins_cost(DEFAULT_COST*2);
5822
5823 expand %{
5824 // Would like to use $src$$constant.
5825 immI16 srcLo %{ _opnds[1]->constant() %}
5826 // srcHi can be 0000 if srcLo sign-extends to a negative number.
5827 immIhi16 srcHi %{ _opnds[1]->constant() %}
5828 iRegIdst tmpI;
5829 loadConIhi16(tmpI, srcHi);
5830 loadConI32_lo16(dst, tmpI, srcLo);
5831 %}
5832 %}
5833
5834 // No constant pool entries required.
5835 instruct loadConL16(iRegLdst dst, immL16 src) %{
5836 match(Set dst src);
5837
5838 format %{ "LI $dst, $src \t// long" %}
5839 size(4);
5840 ins_encode %{
5841 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
5842 __ li($dst$$Register, (int)((short) ($src$$constant & 0xFFFF)));
5843 %}
5844 ins_pipe(pipe_class_default);
5845 %}
5846
5847 // Load long constant 0xssssssss????0000
5848 instruct loadConL32hi16(iRegLdst dst, immL32hi16 src) %{
5849 match(Set dst src);
5850 ins_cost(DEFAULT_COST);
5851
5852 format %{ "LIS $dst, $src.hi \t// long" %}
5853 size(4);
5854 ins_encode %{
5855 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
5856 __ lis($dst$$Register, (int)((short)(($src$$constant & 0xFFFF0000) >> 16)));
5857 %}
5858 ins_pipe(pipe_class_default);
5859 %}
5860
5861 // To load a 32 bit constant: merge lower 16 bits into already loaded
5862 // high 16 bits.
5863 instruct loadConL32_lo16(iRegLdst dst, iRegLsrc src1, immL16 src2) %{
5864 // no match-rule, false predicate
5865 effect(DEF dst, USE src1, USE src2);
5866 predicate(false);
5867
5868 format %{ "ORI $dst, $src1, $src2.lo" %}
5869 size(4);
5870 ins_encode %{
5871 // TODO: PPC port $archOpcode(ppc64Opcode_ori);
5872 __ ori($dst$$Register, $src1$$Register, ($src2$$constant) & 0xFFFF);
5873 %}
5874 ins_pipe(pipe_class_default);
5875 %}
5876
5877 // Load 32-bit long constant
5878 instruct loadConL32_Ex(iRegLdst dst, immL32 src) %{
5879 match(Set dst src);
5880 ins_cost(DEFAULT_COST*2);
5881
5882 expand %{
5883 // Would like to use $src$$constant.
5884 immL16 srcLo %{ _opnds[1]->constant() /*& 0x0000FFFFL */%}
5885 // srcHi can be 0000 if srcLo sign-extends to a negative number.
5886 immL32hi16 srcHi %{ _opnds[1]->constant() /*& 0xFFFF0000L */%}
5887 iRegLdst tmpL;
5888 loadConL32hi16(tmpL, srcHi);
5889 loadConL32_lo16(dst, tmpL, srcLo);
5890 %}
5891 %}
5892
5893 // Load long constant 0x????000000000000.
5894 instruct loadConLhighest16_Ex(iRegLdst dst, immLhighest16 src) %{
5895 match(Set dst src);
5896 ins_cost(DEFAULT_COST);
5897
5898 expand %{
5899 immL32hi16 srcHi %{ _opnds[1]->constant() >> 32 /*& 0xFFFF0000L */%}
5900 immI shift32 %{ 32 %}
5901 iRegLdst tmpL;
5902 loadConL32hi16(tmpL, srcHi);
5903 lshiftL_regL_immI(dst, tmpL, shift32);
5904 %}
5905 %}
5906
5907 // Expand node for constant pool load: small offset.
5908 instruct loadConL(iRegLdst dst, immL src, iRegLdst toc) %{
5909 effect(DEF dst, USE src, USE toc);
5910 ins_cost(MEMORY_REF_COST);
5911
5912 ins_num_consts(1);
5913 // Needed so that CallDynamicJavaDirect can compute the address of this
5914 // instruction for relocation.
5915 ins_field_cbuf_insts_offset(int);
5916
5917 format %{ "LD $dst, offset, $toc \t// load long $src from TOC" %}
5918 size(4);
5919 ins_encode( enc_load_long_constL(dst, src, toc) );
5920 ins_pipe(pipe_class_memory);
5921 %}
5922
5923 // Expand node for constant pool load: large offset.
5924 instruct loadConL_hi(iRegLdst dst, immL src, iRegLdst toc) %{
5925 effect(DEF dst, USE src, USE toc);
5926 predicate(false);
5927
5928 ins_num_consts(1);
5929 ins_field_const_toc_offset(int);
5930 // Needed so that CallDynamicJavaDirect can compute the address of this
5931 // instruction for relocation.
5932 ins_field_cbuf_insts_offset(int);
5933
5934 format %{ "ADDIS $dst, $toc, offset \t// load long $src from TOC (hi)" %}
5935 size(4);
5936 ins_encode( enc_load_long_constL_hi(dst, toc, src) );
5937 ins_pipe(pipe_class_default);
5938 %}
5939
5940 // Expand node for constant pool load: large offset.
5941 // No constant pool entries required.
5942 instruct loadConL_lo(iRegLdst dst, immL src, iRegLdst base) %{
5943 effect(DEF dst, USE src, USE base);
5944 predicate(false);
5945
5946 ins_field_const_toc_offset_hi_node(loadConL_hiNode*);
5947
5948 format %{ "LD $dst, offset, $base \t// load long $src from TOC (lo)" %}
5949 size(4);
5950 ins_encode %{
5951 // TODO: PPC port $archOpcode(ppc64Opcode_ld);
5952 int offset = ra_->C->in_scratch_emit_size() ? 0 : _const_toc_offset_hi_node->_const_toc_offset;
5953 __ ld($dst$$Register, MacroAssembler::largeoffset_si16_si16_lo(offset), $base$$Register);
5954 %}
5955 ins_pipe(pipe_class_memory);
5956 %}
5957
5958 // Load long constant from constant table. Expand in case of
5959 // offset > 16 bit is needed.
5960 // Adlc adds toc node MachConstantTableBase.
5961 instruct loadConL_Ex(iRegLdst dst, immL src) %{
5962 match(Set dst src);
5963 ins_cost(MEMORY_REF_COST);
5964
5965 format %{ "LD $dst, offset, $constanttablebase\t// load long $src from table, postalloc expanded" %}
5966 // We can not inline the enc_class for the expand as that does not support constanttablebase.
5967 postalloc_expand( postalloc_expand_load_long_constant(dst, src, constanttablebase) );
5968 %}
5969
5970 // Load NULL as compressed oop.
5971 instruct loadConN0(iRegNdst dst, immN_0 src) %{
5972 match(Set dst src);
5973 ins_cost(DEFAULT_COST);
5974
5975 format %{ "LI $dst, $src \t// compressed ptr" %}
5976 size(4);
5977 ins_encode %{
5978 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
5979 __ li($dst$$Register, 0);
5980 %}
5981 ins_pipe(pipe_class_default);
5982 %}
5983
5984 // Load hi part of compressed oop constant.
5985 instruct loadConN_hi(iRegNdst dst, immN src) %{
5986 effect(DEF dst, USE src);
5987 ins_cost(DEFAULT_COST);
5988
5989 format %{ "LIS $dst, $src \t// narrow oop hi" %}
5990 size(4);
5991 ins_encode %{
5992 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
5993 __ lis($dst$$Register, (int)(short)(($src$$constant >> 16) & 0xffff));
5994 %}
5995 ins_pipe(pipe_class_default);
5996 %}
5997
5998 // Add lo part of compressed oop constant to already loaded hi part.
5999 instruct loadConN_lo(iRegNdst dst, iRegNsrc src1, immN src2) %{
6000 effect(DEF dst, USE src1, USE src2);
6001 ins_cost(DEFAULT_COST);
6002
6003 format %{ "ORI $dst, $src1, $src2 \t// narrow oop lo" %}
6004 size(4);
6005 ins_encode %{
6006 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
6007 assert(__ oop_recorder() != NULL, "this assembler needs an OopRecorder");
6008 int oop_index = __ oop_recorder()->find_index((jobject)$src2$$constant);
6009 RelocationHolder rspec = oop_Relocation::spec(oop_index);
6010 __ relocate(rspec, 1);
6011 __ ori($dst$$Register, $src1$$Register, $src2$$constant & 0xffff);
6012 %}
6013 ins_pipe(pipe_class_default);
6014 %}
6015
6016 // Needed to postalloc expand loadConN: ConN is loaded as ConI
6017 // leaving the upper 32 bits with sign-extension bits.
6018 // This clears these bits: dst = src & 0xFFFFFFFF.
6019 // TODO: Eventually call this maskN_regN_FFFFFFFF.
6020 instruct clearMs32b(iRegNdst dst, iRegNsrc src) %{
6021 effect(DEF dst, USE src);
6022 predicate(false);
6023
6024 format %{ "MASK $dst, $src, 0xFFFFFFFF" %} // mask
6025 size(4);
6026 ins_encode %{
6027 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
6028 __ clrldi($dst$$Register, $src$$Register, 0x20);
6029 %}
6030 ins_pipe(pipe_class_default);
6031 %}
6032
6033 // Loading ConN must be postalloc expanded so that edges between
6034 // the nodes are safe. They may not interfere with a safepoint.
6035 // GL TODO: This needs three instructions: better put this into the constant pool.
6036 instruct loadConN_Ex(iRegNdst dst, immN src) %{
6037 match(Set dst src);
6038 ins_cost(DEFAULT_COST*2);
6039
6040 format %{ "LoadN $dst, $src \t// postalloc expanded" %} // mask
6041 postalloc_expand %{
6042 MachNode *m1 = new (C) loadConN_hiNode();
6043 MachNode *m2 = new (C) loadConN_loNode();
6044 MachNode *m3 = new (C) clearMs32bNode();
6045 m1->add_req(NULL);
6046 m2->add_req(NULL, m1);
6047 m3->add_req(NULL, m2);
6048 m1->_opnds[0] = op_dst;
6049 m1->_opnds[1] = op_src;
6050 m2->_opnds[0] = op_dst;
6051 m2->_opnds[1] = op_dst;
6052 m2->_opnds[2] = op_src;
6053 m3->_opnds[0] = op_dst;
6054 m3->_opnds[1] = op_dst;
6055 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6056 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6057 ra_->set_pair(m3->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6058 nodes->push(m1);
6059 nodes->push(m2);
6060 nodes->push(m3);
6061 %}
6062 %}
6063
6064 // We have seen a safepoint between the hi and lo parts, and this node was handled
6065 // as an oop. Therefore this needs a match rule so that build_oop_map knows this is
6066 // not a narrow oop.
6067 instruct loadConNKlass_hi(iRegNdst dst, immNKlass_NM src) %{
6068 match(Set dst src);
6069 effect(DEF dst, USE src);
6070 ins_cost(DEFAULT_COST);
6071
6072 format %{ "LIS $dst, $src \t// narrow klass hi" %}
6073 size(4);
6074 ins_encode %{
6075 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
6076 intptr_t Csrc = Klass::encode_klass((Klass *)$src$$constant);
6077 __ lis($dst$$Register, (int)(short)((Csrc >> 16) & 0xffff));
6078 %}
6079 ins_pipe(pipe_class_default);
6080 %}
6081
6082 // As loadConNKlass_hi this must be recognized as narrow klass, not oop!
6083 instruct loadConNKlass_mask(iRegNdst dst, immNKlass_NM src1, iRegNsrc src2) %{
6084 match(Set dst src1);
6085 effect(TEMP src2);
6086 ins_cost(DEFAULT_COST);
6087
6088 format %{ "MASK $dst, $src2, 0xFFFFFFFF" %} // mask
6089 size(4);
6090 ins_encode %{
6091 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
6092 __ clrldi($dst$$Register, $src2$$Register, 0x20);
6093 %}
6094 ins_pipe(pipe_class_default);
6095 %}
6096
6097 // This needs a match rule so that build_oop_map knows this is
6098 // not a narrow oop.
6099 instruct loadConNKlass_lo(iRegNdst dst, immNKlass_NM src1, iRegNsrc src2) %{
6100 match(Set dst src1);
6101 effect(TEMP src2);
6102 ins_cost(DEFAULT_COST);
6103
6104 format %{ "ORI $dst, $src1, $src2 \t// narrow klass lo" %}
6105 size(4);
6106 ins_encode %{
6107 // TODO: PPC port $archOpcode(ppc64Opcode_ori);
6108 intptr_t Csrc = Klass::encode_klass((Klass *)$src1$$constant);
6109 assert(__ oop_recorder() != NULL, "this assembler needs an OopRecorder");
6110 int klass_index = __ oop_recorder()->find_index((Klass *)$src1$$constant);
6111 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
6112
6113 __ relocate(rspec, 1);
6114 __ ori($dst$$Register, $src2$$Register, Csrc & 0xffff);
6115 %}
6116 ins_pipe(pipe_class_default);
6117 %}
6118
6119 // Loading ConNKlass must be postalloc expanded so that edges between
6120 // the nodes are safe. They may not interfere with a safepoint.
6121 instruct loadConNKlass_Ex(iRegNdst dst, immNKlass src) %{
6122 match(Set dst src);
6123 ins_cost(DEFAULT_COST*2);
6124
6125 format %{ "LoadN $dst, $src \t// postalloc expanded" %} // mask
6126 postalloc_expand %{
6127 // Load high bits into register. Sign extended.
6128 MachNode *m1 = new (C) loadConNKlass_hiNode();
6129 m1->add_req(NULL);
6130 m1->_opnds[0] = op_dst;
6131 m1->_opnds[1] = op_src;
6132 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6133 nodes->push(m1);
6134
6135 MachNode *m2 = m1;
6136 if (!Assembler::is_uimm((jlong)Klass::encode_klass((Klass *)op_src->constant()), 31)) {
6137 // Value might be 1-extended. Mask out these bits.
6138 m2 = new (C) loadConNKlass_maskNode();
6139 m2->add_req(NULL, m1);
6140 m2->_opnds[0] = op_dst;
6141 m2->_opnds[1] = op_src;
6142 m2->_opnds[2] = op_dst;
6143 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6144 nodes->push(m2);
6145 }
6146
6147 MachNode *m3 = new (C) loadConNKlass_loNode();
6148 m3->add_req(NULL, m2);
6149 m3->_opnds[0] = op_dst;
6150 m3->_opnds[1] = op_src;
6151 m3->_opnds[2] = op_dst;
6152 ra_->set_pair(m3->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6153 nodes->push(m3);
6154 %}
6155 %}
6156
6157 // 0x1 is used in object initialization (initial object header).
6158 // No constant pool entries required.
6159 instruct loadConP0or1(iRegPdst dst, immP_0or1 src) %{
6160 match(Set dst src);
6161
6162 format %{ "LI $dst, $src \t// ptr" %}
6163 size(4);
6164 ins_encode %{
6165 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
6166 __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF)));
6167 %}
6168 ins_pipe(pipe_class_default);
6169 %}
6170
6171 // Expand node for constant pool load: small offset.
6172 // The match rule is needed to generate the correct bottom_type(),
6173 // however this node should never match. The use of predicate is not
6174 // possible since ADLC forbids predicates for chain rules. The higher
6175 // costs do not prevent matching in this case. For that reason the
6176 // operand immP_NM with predicate(false) is used.
6177 instruct loadConP(iRegPdst dst, immP_NM src, iRegLdst toc) %{
6178 match(Set dst src);
6179 effect(TEMP toc);
6180
6181 ins_num_consts(1);
6182
6183 format %{ "LD $dst, offset, $toc \t// load ptr $src from TOC" %}
6184 size(4);
6185 ins_encode( enc_load_long_constP(dst, src, toc) );
6186 ins_pipe(pipe_class_memory);
6187 %}
6188
6189 // Expand node for constant pool load: large offset.
6190 instruct loadConP_hi(iRegPdst dst, immP_NM src, iRegLdst toc) %{
6191 effect(DEF dst, USE src, USE toc);
6192 predicate(false);
6193
6194 ins_num_consts(1);
6195 ins_field_const_toc_offset(int);
6196
6197 format %{ "ADDIS $dst, $toc, offset \t// load ptr $src from TOC (hi)" %}
6198 size(4);
6199 ins_encode( enc_load_long_constP_hi(dst, src, toc) );
6200 ins_pipe(pipe_class_default);
6201 %}
6202
6203 // Expand node for constant pool load: large offset.
6204 instruct loadConP_lo(iRegPdst dst, immP_NM src, iRegLdst base) %{
6205 match(Set dst src);
6206 effect(TEMP base);
6207
6208 ins_field_const_toc_offset_hi_node(loadConP_hiNode*);
6209
6210 format %{ "LD $dst, offset, $base \t// load ptr $src from TOC (lo)" %}
6211 size(4);
6212 ins_encode %{
6213 // TODO: PPC port $archOpcode(ppc64Opcode_ld);
6214 int offset = ra_->C->in_scratch_emit_size() ? 0 : _const_toc_offset_hi_node->_const_toc_offset;
6215 __ ld($dst$$Register, MacroAssembler::largeoffset_si16_si16_lo(offset), $base$$Register);
6216 %}
6217 ins_pipe(pipe_class_memory);
6218 %}
6219
6220 // Load pointer constant from constant table. Expand in case an
6221 // offset > 16 bit is needed.
6222 // Adlc adds toc node MachConstantTableBase.
6223 instruct loadConP_Ex(iRegPdst dst, immP src) %{
6224 match(Set dst src);
6225 ins_cost(MEMORY_REF_COST);
6226
6227 // This rule does not use "expand" because then
6228 // the result type is not known to be an Oop. An ADLC
6229 // enhancement will be needed to make that work - not worth it!
6230
6231 // If this instruction rematerializes, it prolongs the live range
6232 // of the toc node, causing illegal graphs.
6233 // assert(edge_from_to(_reg_node[reg_lo],def)) fails in verify_good_schedule().
6234 ins_cannot_rematerialize(true);
6235
6236 format %{ "LD $dst, offset, $constanttablebase \t// load ptr $src from table, postalloc expanded" %}
6237 postalloc_expand( postalloc_expand_load_ptr_constant(dst, src, constanttablebase) );
6238 %}
6239
6240 // Expand node for constant pool load: small offset.
6241 instruct loadConF(regF dst, immF src, iRegLdst toc) %{
6242 effect(DEF dst, USE src, USE toc);
6243 ins_cost(MEMORY_REF_COST);
6244
6245 ins_num_consts(1);
6246
6247 format %{ "LFS $dst, offset, $toc \t// load float $src from TOC" %}
6248 size(4);
6249 ins_encode %{
6250 // TODO: PPC port $archOpcode(ppc64Opcode_lfs);
6251 address float_address = __ float_constant($src$$constant);
6252 __ lfs($dst$$FloatRegister, __ offset_to_method_toc(float_address), $toc$$Register);
6253 %}
6254 ins_pipe(pipe_class_memory);
6255 %}
6256
6257 // Expand node for constant pool load: large offset.
6258 instruct loadConFComp(regF dst, immF src, iRegLdst toc) %{
6259 effect(DEF dst, USE src, USE toc);
6260 ins_cost(MEMORY_REF_COST);
6261
6262 ins_num_consts(1);
6263
6264 format %{ "ADDIS $toc, $toc, offset_hi\n\t"
6265 "LFS $dst, offset_lo, $toc \t// load float $src from TOC (hi/lo)\n\t"
6266 "ADDIS $toc, $toc, -offset_hi"%}
6267 size(12);
6268 ins_encode %{
6269 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6270 FloatRegister Rdst = $dst$$FloatRegister;
6271 Register Rtoc = $toc$$Register;
6272 address float_address = __ float_constant($src$$constant);
6273 int offset = __ offset_to_method_toc(float_address);
6274 int hi = (offset + (1<<15))>>16;
6275 int lo = offset - hi * (1<<16);
6276
6277 __ addis(Rtoc, Rtoc, hi);
6278 __ lfs(Rdst, lo, Rtoc);
6279 __ addis(Rtoc, Rtoc, -hi);
6280 %}
6281 ins_pipe(pipe_class_memory);
6282 %}
6283
6284 // Adlc adds toc node MachConstantTableBase.
6285 instruct loadConF_Ex(regF dst, immF src) %{
6286 match(Set dst src);
6287 ins_cost(MEMORY_REF_COST);
6288
6289 // See loadConP.
6290 ins_cannot_rematerialize(true);
6291
6292 format %{ "LFS $dst, offset, $constanttablebase \t// load $src from table, postalloc expanded" %}
6293 postalloc_expand( postalloc_expand_load_float_constant(dst, src, constanttablebase) );
6294 %}
6295
6296 // Expand node for constant pool load: small offset.
6297 instruct loadConD(regD dst, immD src, iRegLdst toc) %{
6298 effect(DEF dst, USE src, USE toc);
6299 ins_cost(MEMORY_REF_COST);
6300
6301 ins_num_consts(1);
6302
6303 format %{ "LFD $dst, offset, $toc \t// load double $src from TOC" %}
6304 size(4);
6305 ins_encode %{
6306 // TODO: PPC port $archOpcode(ppc64Opcode_lfd);
6307 int offset = __ offset_to_method_toc(__ double_constant($src$$constant));
6308 __ lfd($dst$$FloatRegister, offset, $toc$$Register);
6309 %}
6310 ins_pipe(pipe_class_memory);
6311 %}
6312
6313 // Expand node for constant pool load: large offset.
6314 instruct loadConDComp(regD dst, immD src, iRegLdst toc) %{
6315 effect(DEF dst, USE src, USE toc);
6316 ins_cost(MEMORY_REF_COST);
6317
6318 ins_num_consts(1);
6319
6320 format %{ "ADDIS $toc, $toc, offset_hi\n\t"
6321 "LFD $dst, offset_lo, $toc \t// load double $src from TOC (hi/lo)\n\t"
6322 "ADDIS $toc, $toc, -offset_hi" %}
6323 size(12);
6324 ins_encode %{
6325 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6326 FloatRegister Rdst = $dst$$FloatRegister;
6327 Register Rtoc = $toc$$Register;
6328 address float_address = __ double_constant($src$$constant);
6329 int offset = __ offset_to_method_toc(float_address);
6330 int hi = (offset + (1<<15))>>16;
6331 int lo = offset - hi * (1<<16);
6332
6333 __ addis(Rtoc, Rtoc, hi);
6334 __ lfd(Rdst, lo, Rtoc);
6335 __ addis(Rtoc, Rtoc, -hi);
6336 %}
6337 ins_pipe(pipe_class_memory);
6338 %}
6339
6340 // Adlc adds toc node MachConstantTableBase.
6341 instruct loadConD_Ex(regD dst, immD src) %{
6342 match(Set dst src);
6343 ins_cost(MEMORY_REF_COST);
6344
6345 // See loadConP.
6346 ins_cannot_rematerialize(true);
6347
6348 format %{ "ConD $dst, offset, $constanttablebase \t// load $src from table, postalloc expanded" %}
6349 postalloc_expand( postalloc_expand_load_double_constant(dst, src, constanttablebase) );
6350 %}
6351
6352 // Prefetch instructions.
6353 // Must be safe to execute with invalid address (cannot fault).
6354
6355 instruct prefetchr(indirectMemory mem, iRegLsrc src) %{
6356 match(PrefetchRead (AddP mem src));
6357 ins_cost(MEMORY_REF_COST);
6358
6359 format %{ "PREFETCH $mem, 0, $src \t// Prefetch read-many" %}
6360 size(4);
6361 ins_encode %{
6362 // TODO: PPC port $archOpcode(ppc64Opcode_dcbt);
6363 __ dcbt($src$$Register, $mem$$base$$Register);
6364 %}
6365 ins_pipe(pipe_class_memory);
6366 %}
6367
6368 instruct prefetchr_no_offset(indirectMemory mem) %{
6369 match(PrefetchRead mem);
6370 ins_cost(MEMORY_REF_COST);
6371
6372 format %{ "PREFETCH $mem" %}
6373 size(4);
6374 ins_encode %{
6375 // TODO: PPC port $archOpcode(ppc64Opcode_dcbt);
6376 __ dcbt($mem$$base$$Register);
6377 %}
6378 ins_pipe(pipe_class_memory);
6379 %}
6380
6381 instruct prefetchw(indirectMemory mem, iRegLsrc src) %{
6382 match(PrefetchWrite (AddP mem src));
6383 ins_cost(MEMORY_REF_COST);
6384
6385 format %{ "PREFETCH $mem, 2, $src \t// Prefetch write-many (and read)" %}
6386 size(4);
6387 ins_encode %{
6388 // TODO: PPC port $archOpcode(ppc64Opcode_dcbtst);
6389 __ dcbtst($src$$Register, $mem$$base$$Register);
6390 %}
6391 ins_pipe(pipe_class_memory);
6392 %}
6393
6394 instruct prefetchw_no_offset(indirectMemory mem) %{
6395 match(PrefetchWrite mem);
6396 ins_cost(MEMORY_REF_COST);
6397
6398 format %{ "PREFETCH $mem" %}
6399 size(4);
6400 ins_encode %{
6401 // TODO: PPC port $archOpcode(ppc64Opcode_dcbtst);
6402 __ dcbtst($mem$$base$$Register);
6403 %}
6404 ins_pipe(pipe_class_memory);
6405 %}
6406
6407 // Special prefetch versions which use the dcbz instruction.
6408 instruct prefetch_alloc_zero(indirectMemory mem, iRegLsrc src) %{
6409 match(PrefetchAllocation (AddP mem src));
6410 predicate(AllocatePrefetchStyle == 3);
6411 ins_cost(MEMORY_REF_COST);
6412
6413 format %{ "PREFETCH $mem, 2, $src \t// Prefetch write-many with zero" %}
6414 size(4);
6415 ins_encode %{
6416 // TODO: PPC port $archOpcode(ppc64Opcode_dcbtst);
6417 __ dcbz($src$$Register, $mem$$base$$Register);
6418 %}
6419 ins_pipe(pipe_class_memory);
6420 %}
6421
6422 instruct prefetch_alloc_zero_no_offset(indirectMemory mem) %{
6423 match(PrefetchAllocation mem);
6424 predicate(AllocatePrefetchStyle == 3);
6425 ins_cost(MEMORY_REF_COST);
6426
6427 format %{ "PREFETCH $mem, 2 \t// Prefetch write-many with zero" %}
6428 size(4);
6429 ins_encode %{
6430 // TODO: PPC port $archOpcode(ppc64Opcode_dcbtst);
6431 __ dcbz($mem$$base$$Register);
6432 %}
6433 ins_pipe(pipe_class_memory);
6434 %}
6435
6436 instruct prefetch_alloc(indirectMemory mem, iRegLsrc src) %{
6437 match(PrefetchAllocation (AddP mem src));
6438 predicate(AllocatePrefetchStyle != 3);
6439 ins_cost(MEMORY_REF_COST);
6440
6441 format %{ "PREFETCH $mem, 2, $src \t// Prefetch write-many" %}
6442 size(4);
6443 ins_encode %{
6444 // TODO: PPC port $archOpcode(ppc64Opcode_dcbtst);
6445 __ dcbtst($src$$Register, $mem$$base$$Register);
6446 %}
6447 ins_pipe(pipe_class_memory);
6448 %}
6449
6450 instruct prefetch_alloc_no_offset(indirectMemory mem) %{
6451 match(PrefetchAllocation mem);
6452 predicate(AllocatePrefetchStyle != 3);
6453 ins_cost(MEMORY_REF_COST);
6454
6455 format %{ "PREFETCH $mem, 2 \t// Prefetch write-many" %}
6456 size(4);
6457 ins_encode %{
6458 // TODO: PPC port $archOpcode(ppc64Opcode_dcbtst);
6459 __ dcbtst($mem$$base$$Register);
6460 %}
6461 ins_pipe(pipe_class_memory);
6462 %}
6463
6464 //----------Store Instructions-------------------------------------------------
6465
6466 // Store Byte
6467 instruct storeB(memory mem, iRegIsrc src) %{
6468 match(Set mem (StoreB mem src));
6469 ins_cost(MEMORY_REF_COST);
6470
6471 format %{ "STB $src, $mem \t// byte" %}
6472 size(4);
6473 ins_encode %{
6474 // TODO: PPC port $archOpcode(ppc64Opcode_stb);
6475 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
6476 __ stb($src$$Register, Idisp, $mem$$base$$Register);
6477 %}
6478 ins_pipe(pipe_class_memory);
6479 %}
6480
6481 // Store Char/Short
6482 instruct storeC(memory mem, iRegIsrc src) %{
6483 match(Set mem (StoreC mem src));
6484 ins_cost(MEMORY_REF_COST);
6485
6486 format %{ "STH $src, $mem \t// short" %}
6487 size(4);
6488 ins_encode %{
6489 // TODO: PPC port $archOpcode(ppc64Opcode_sth);
6490 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
6491 __ sth($src$$Register, Idisp, $mem$$base$$Register);
6492 %}
6493 ins_pipe(pipe_class_memory);
6494 %}
6495
6496 // Store Integer
6497 instruct storeI(memory mem, iRegIsrc src) %{
6498 match(Set mem (StoreI mem src));
6499 ins_cost(MEMORY_REF_COST);
6500
6501 format %{ "STW $src, $mem" %}
6502 size(4);
6503 ins_encode( enc_stw(src, mem) );
6504 ins_pipe(pipe_class_memory);
6505 %}
6506
6507 // ConvL2I + StoreI.
6508 instruct storeI_convL2I(memory mem, iRegLsrc src) %{
6509 match(Set mem (StoreI mem (ConvL2I src)));
6510 ins_cost(MEMORY_REF_COST);
6511
6512 format %{ "STW l2i($src), $mem" %}
6513 size(4);
6514 ins_encode( enc_stw(src, mem) );
6515 ins_pipe(pipe_class_memory);
6516 %}
6517
6518 // Store Long
6519 instruct storeL(memoryAlg4 mem, iRegLsrc src) %{
6520 match(Set mem (StoreL mem src));
6521 ins_cost(MEMORY_REF_COST);
6522
6523 format %{ "STD $src, $mem \t// long" %}
6524 size(4);
6525 ins_encode( enc_std(src, mem) );
6526 ins_pipe(pipe_class_memory);
6527 %}
6528
6529 // Store super word nodes.
6530
6531 // Store Aligned Packed Byte long register to memory
6532 instruct storeA8B(memoryAlg4 mem, iRegLsrc src) %{
6533 predicate(n->as_StoreVector()->memory_size() == 8);
6534 match(Set mem (StoreVector mem src));
6535 ins_cost(MEMORY_REF_COST);
6536
6537 format %{ "STD $mem, $src \t// packed8B" %}
6538 size(4);
6539 ins_encode( enc_std(src, mem) );
6540 ins_pipe(pipe_class_memory);
6541 %}
6542
6543 // Store Compressed Oop
6544 instruct storeN(memory dst, iRegN_P2N src) %{
6545 match(Set dst (StoreN dst src));
6546 ins_cost(MEMORY_REF_COST);
6547
6548 format %{ "STW $src, $dst \t// compressed oop" %}
6549 size(4);
6550 ins_encode( enc_stw(src, dst) );
6551 ins_pipe(pipe_class_memory);
6552 %}
6553
6554 // Store Compressed KLass
6555 instruct storeNKlass(memory dst, iRegN_P2N src) %{
6556 match(Set dst (StoreNKlass dst src));
6557 ins_cost(MEMORY_REF_COST);
6558
6559 format %{ "STW $src, $dst \t// compressed klass" %}
6560 size(4);
6561 ins_encode( enc_stw(src, dst) );
6562 ins_pipe(pipe_class_memory);
6563 %}
6564
6565 // Store Pointer
6566 instruct storeP(memoryAlg4 dst, iRegPsrc src) %{
6567 match(Set dst (StoreP dst src));
6568 ins_cost(MEMORY_REF_COST);
6569
6570 format %{ "STD $src, $dst \t// ptr" %}
6571 size(4);
6572 ins_encode( enc_std(src, dst) );
6573 ins_pipe(pipe_class_memory);
6574 %}
6575
6576 // Store Float
6577 instruct storeF(memory mem, regF src) %{
6578 match(Set mem (StoreF mem src));
6579 ins_cost(MEMORY_REF_COST);
6580
6581 format %{ "STFS $src, $mem" %}
6582 size(4);
6583 ins_encode( enc_stfs(src, mem) );
6584 ins_pipe(pipe_class_memory);
6585 %}
6586
6587 // Store Double
6588 instruct storeD(memory mem, regD src) %{
6589 match(Set mem (StoreD mem src));
6590 ins_cost(MEMORY_REF_COST);
6591
6592 format %{ "STFD $src, $mem" %}
6593 size(4);
6594 ins_encode( enc_stfd(src, mem) );
6595 ins_pipe(pipe_class_memory);
6596 %}
6597
6598 //----------Store Instructions With Zeros--------------------------------------
6599
6600 // Card-mark for CMS garbage collection.
6601 // This cardmark does an optimization so that it must not always
6602 // do a releasing store. For this, it gets the address of
6603 // CMSCollectorCardTableModRefBSExt::_requires_release as input.
6604 // (Using releaseFieldAddr in the match rule is a hack.)
6605 instruct storeCM_CMS(memory mem, iRegLdst releaseFieldAddr) %{
6606 match(Set mem (StoreCM mem releaseFieldAddr));
6607 predicate(false);
6608 ins_cost(MEMORY_REF_COST);
6609
6610 // See loadConP.
6611 ins_cannot_rematerialize(true);
6612
6613 format %{ "STB #0, $mem \t// CMS card-mark byte (must be 0!), checking requires_release in [$releaseFieldAddr]" %}
6614 ins_encode( enc_cms_card_mark(mem, releaseFieldAddr) );
6615 ins_pipe(pipe_class_memory);
6616 %}
6617
6618 // Card-mark for CMS garbage collection.
6619 // This cardmark does an optimization so that it must not always
6620 // do a releasing store. For this, it needs the constant address of
6621 // CMSCollectorCardTableModRefBSExt::_requires_release.
6622 // This constant address is split off here by expand so we can use
6623 // adlc / matcher functionality to load it from the constant section.
6624 instruct storeCM_CMS_ExEx(memory mem, immI_0 zero) %{
6625 match(Set mem (StoreCM mem zero));
6626 predicate(UseConcMarkSweepGC);
6627
6628 expand %{
6629 immL baseImm %{ 0 /* TODO: PPC port (jlong)CMSCollectorCardTableModRefBSExt::requires_release_address() */ %}
6630 iRegLdst releaseFieldAddress;
6631 loadConL_Ex(releaseFieldAddress, baseImm);
6632 storeCM_CMS(mem, releaseFieldAddress);
6633 %}
6634 %}
6635
6636 instruct storeCM_G1(memory mem, immI_0 zero) %{
6637 match(Set mem (StoreCM mem zero));
6638 predicate(UseG1GC);
6639 ins_cost(MEMORY_REF_COST);
6640
6641 ins_cannot_rematerialize(true);
6642
6643 format %{ "STB #0, $mem \t// CMS card-mark byte store (G1)" %}
6644 size(8);
6645 ins_encode %{
6646 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6647 __ li(R0, 0);
6648 //__ release(); // G1: oops are allowed to get visible after dirty marking
6649 guarantee($mem$$base$$Register != R1_SP, "use frame_slots_bias");
6650 __ stb(R0, $mem$$disp, $mem$$base$$Register);
6651 %}
6652 ins_pipe(pipe_class_memory);
6653 %}
6654
6655 // Convert oop pointer into compressed form.
6656
6657 // Nodes for postalloc expand.
6658
6659 // Shift node for expand.
6660 instruct encodeP_shift(iRegNdst dst, iRegNsrc src) %{
6661 // The match rule is needed to make it a 'MachTypeNode'!
6662 match(Set dst (EncodeP src));
6663 predicate(false);
6664
6665 format %{ "SRDI $dst, $src, 3 \t// encode" %}
6666 size(4);
6667 ins_encode %{
6668 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
6669 __ srdi($dst$$Register, $src$$Register, Universe::narrow_oop_shift() & 0x3f);
6670 %}
6671 ins_pipe(pipe_class_default);
6672 %}
6673
6674 // Add node for expand.
6675 instruct encodeP_sub(iRegPdst dst, iRegPdst src) %{
6676 // The match rule is needed to make it a 'MachTypeNode'!
6677 match(Set dst (EncodeP src));
6678 predicate(false);
6679
6680 format %{ "SUB $dst, $src, oop_base \t// encode" %}
6681 size(4);
6682 ins_encode %{
6683 // TODO: PPC port $archOpcode(ppc64Opcode_subf);
6684 __ subf($dst$$Register, R30, $src$$Register);
6685 %}
6686 ins_pipe(pipe_class_default);
6687 %}
6688
6689 // Conditional sub base.
6690 instruct cond_sub_base(iRegNdst dst, flagsReg crx, iRegPsrc src1) %{
6691 // The match rule is needed to make it a 'MachTypeNode'!
6692 match(Set dst (EncodeP (Binary crx src1)));
6693 predicate(false);
6694
6695 ins_variable_size_depending_on_alignment(true);
6696
6697 format %{ "BEQ $crx, done\n\t"
6698 "SUB $dst, $src1, R30 \t// encode: subtract base if != NULL\n"
6699 "done:" %}
6700 size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8);
6701 ins_encode %{
6702 // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
6703 Label done;
6704 __ beq($crx$$CondRegister, done);
6705 __ subf($dst$$Register, R30, $src1$$Register);
6706 // TODO PPC port __ endgroup_if_needed(_size == 12);
6707 __ bind(done);
6708 %}
6709 ins_pipe(pipe_class_default);
6710 %}
6711
6712 // Power 7 can use isel instruction
6713 instruct cond_set_0_oop(iRegNdst dst, flagsReg crx, iRegPsrc src1) %{
6714 // The match rule is needed to make it a 'MachTypeNode'!
6715 match(Set dst (EncodeP (Binary crx src1)));
6716 predicate(false);
6717
6718 format %{ "CMOVE $dst, $crx eq, 0, $src1 \t// encode: preserve 0" %}
6719 size(4);
6720 ins_encode %{
6721 // This is a Power7 instruction for which no machine description exists.
6722 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6723 __ isel_0($dst$$Register, $crx$$CondRegister, Assembler::equal, $src1$$Register);
6724 %}
6725 ins_pipe(pipe_class_default);
6726 %}
6727
6728 // base != 0
6729 // 32G aligned narrow oop base.
6730 instruct encodeP_32GAligned(iRegNdst dst, iRegPsrc src) %{
6731 match(Set dst (EncodeP src));
6732 predicate(false /* TODO: PPC port Universe::narrow_oop_base_disjoint()*/);
6733
6734 format %{ "EXTRDI $dst, $src, #32, #3 \t// encode with 32G aligned base" %}
6735 size(4);
6736 ins_encode %{
6737 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
6738 __ rldicl($dst$$Register, $src$$Register, 64-Universe::narrow_oop_shift(), 32);
6739 %}
6740 ins_pipe(pipe_class_default);
6741 %}
6742
6743 // shift != 0, base != 0
6744 instruct encodeP_Ex(iRegNdst dst, flagsReg crx, iRegPsrc src) %{
6745 match(Set dst (EncodeP src));
6746 effect(TEMP crx);
6747 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull &&
6748 Universe::narrow_oop_shift() != 0 &&
6749 true /* TODO: PPC port Universe::narrow_oop_base_overlaps()*/);
6750
6751 format %{ "EncodeP $dst, $crx, $src \t// postalloc expanded" %}
6752 postalloc_expand( postalloc_expand_encode_oop(dst, src, crx));
6753 %}
6754
6755 // shift != 0, base != 0
6756 instruct encodeP_not_null_Ex(iRegNdst dst, iRegPsrc src) %{
6757 match(Set dst (EncodeP src));
6758 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull &&
6759 Universe::narrow_oop_shift() != 0 &&
6760 true /* TODO: PPC port Universe::narrow_oop_base_overlaps()*/);
6761
6762 format %{ "EncodeP $dst, $src\t// $src != Null, postalloc expanded" %}
6763 postalloc_expand( postalloc_expand_encode_oop_not_null(dst, src) );
6764 %}
6765
6766 // shift != 0, base == 0
6767 // TODO: This is the same as encodeP_shift. Merge!
6768 instruct encodeP_not_null_base_null(iRegNdst dst, iRegPsrc src) %{
6769 match(Set dst (EncodeP src));
6770 predicate(Universe::narrow_oop_shift() != 0 &&
6771 Universe::narrow_oop_base() ==0);
6772
6773 format %{ "SRDI $dst, $src, #3 \t// encodeP, $src != NULL" %}
6774 size(4);
6775 ins_encode %{
6776 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
6777 __ srdi($dst$$Register, $src$$Register, Universe::narrow_oop_shift() & 0x3f);
6778 %}
6779 ins_pipe(pipe_class_default);
6780 %}
6781
6782 // Compressed OOPs with narrow_oop_shift == 0.
6783 // shift == 0, base == 0
6784 instruct encodeP_narrow_oop_shift_0(iRegNdst dst, iRegPsrc src) %{
6785 match(Set dst (EncodeP src));
6786 predicate(Universe::narrow_oop_shift() == 0);
6787
6788 format %{ "MR $dst, $src \t// Ptr->Narrow" %}
6789 // variable size, 0 or 4.
6790 ins_encode %{
6791 // TODO: PPC port $archOpcode(ppc64Opcode_or);
6792 __ mr_if_needed($dst$$Register, $src$$Register);
6793 %}
6794 ins_pipe(pipe_class_default);
6795 %}
6796
6797 // Decode nodes.
6798
6799 // Shift node for expand.
6800 instruct decodeN_shift(iRegPdst dst, iRegPsrc src) %{
6801 // The match rule is needed to make it a 'MachTypeNode'!
6802 match(Set dst (DecodeN src));
6803 predicate(false);
6804
6805 format %{ "SLDI $dst, $src, #3 \t// DecodeN" %}
6806 size(4);
6807 ins_encode %{
6808 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
6809 __ sldi($dst$$Register, $src$$Register, Universe::narrow_oop_shift());
6810 %}
6811 ins_pipe(pipe_class_default);
6812 %}
6813
6814 // Add node for expand.
6815 instruct decodeN_add(iRegPdst dst, iRegPdst src) %{
6816 // The match rule is needed to make it a 'MachTypeNode'!
6817 match(Set dst (DecodeN src));
6818 predicate(false);
6819
6820 format %{ "ADD $dst, $src, R30 \t// DecodeN, add oop base" %}
6821 size(4);
6822 ins_encode %{
6823 // TODO: PPC port $archOpcode(ppc64Opcode_add);
6824 __ add($dst$$Register, $src$$Register, R30);
6825 %}
6826 ins_pipe(pipe_class_default);
6827 %}
6828
6829 // conditianal add base for expand
6830 instruct cond_add_base(iRegPdst dst, flagsReg crx, iRegPsrc src1) %{
6831 // The match rule is needed to make it a 'MachTypeNode'!
6832 // NOTICE that the rule is nonsense - we just have to make sure that:
6833 // - _matrule->_rChild->_opType == "DecodeN" (see InstructForm::captures_bottom_type() in formssel.cpp)
6834 // - we have to match 'crx' to avoid an "illegal USE of non-input: flagsReg crx" error in ADLC.
6835 match(Set dst (DecodeN (Binary crx src1)));
6836 predicate(false);
6837
6838 ins_variable_size_depending_on_alignment(true);
6839
6840 format %{ "BEQ $crx, done\n\t"
6841 "ADD $dst, $src1, R30 \t// DecodeN: add oop base if $src1 != NULL\n"
6842 "done:" %}
6843 size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling()) */? 12 : 8);
6844 ins_encode %{
6845 // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
6846 Label done;
6847 __ beq($crx$$CondRegister, done);
6848 __ add($dst$$Register, $src1$$Register, R30);
6849 // TODO PPC port __ endgroup_if_needed(_size == 12);
6850 __ bind(done);
6851 %}
6852 ins_pipe(pipe_class_default);
6853 %}
6854
6855 instruct cond_set_0_ptr(iRegPdst dst, flagsReg crx, iRegPsrc src1) %{
6856 // The match rule is needed to make it a 'MachTypeNode'!
6857 // NOTICE that the rule is nonsense - we just have to make sure that:
6858 // - _matrule->_rChild->_opType == "DecodeN" (see InstructForm::captures_bottom_type() in formssel.cpp)
6859 // - we have to match 'crx' to avoid an "illegal USE of non-input: flagsReg crx" error in ADLC.
6860 match(Set dst (DecodeN (Binary crx src1)));
6861 predicate(false);
6862
6863 format %{ "CMOVE $dst, $crx eq, 0, $src1 \t// decode: preserve 0" %}
6864 size(4);
6865 ins_encode %{
6866 // This is a Power7 instruction for which no machine description exists.
6867 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6868 __ isel_0($dst$$Register, $crx$$CondRegister, Assembler::equal, $src1$$Register);
6869 %}
6870 ins_pipe(pipe_class_default);
6871 %}
6872
6873 // shift != 0, base != 0
6874 instruct decodeN_Ex(iRegPdst dst, iRegNsrc src, flagsReg crx) %{
6875 match(Set dst (DecodeN src));
6876 predicate((n->bottom_type()->is_oopptr()->ptr() != TypePtr::NotNull &&
6877 n->bottom_type()->is_oopptr()->ptr() != TypePtr::Constant) &&
6878 Universe::narrow_oop_shift() != 0 &&
6879 Universe::narrow_oop_base() != 0);
6880 effect(TEMP crx);
6881
6882 format %{ "DecodeN $dst, $src \t// Kills $crx, postalloc expanded" %}
6883 postalloc_expand( postalloc_expand_decode_oop(dst, src, crx) );
6884 %}
6885
6886 // shift != 0, base == 0
6887 instruct decodeN_nullBase(iRegPdst dst, iRegNsrc src) %{
6888 match(Set dst (DecodeN src));
6889 predicate(Universe::narrow_oop_shift() != 0 &&
6890 Universe::narrow_oop_base() == 0);
6891
6892 format %{ "SLDI $dst, $src, #3 \t// DecodeN (zerobased)" %}
6893 size(4);
6894 ins_encode %{
6895 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
6896 __ sldi($dst$$Register, $src$$Register, Universe::narrow_oop_shift());
6897 %}
6898 ins_pipe(pipe_class_default);
6899 %}
6900
6901 // src != 0, shift != 0, base != 0
6902 instruct decodeN_notNull_addBase_Ex(iRegPdst dst, iRegNsrc src) %{
6903 match(Set dst (DecodeN src));
6904 predicate((n->bottom_type()->is_oopptr()->ptr() == TypePtr::NotNull ||
6905 n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant) &&
6906 Universe::narrow_oop_shift() != 0 &&
6907 Universe::narrow_oop_base() != 0);
6908
6909 format %{ "DecodeN $dst, $src \t// $src != NULL, postalloc expanded" %}
6910 postalloc_expand( postalloc_expand_decode_oop_not_null(dst, src));
6911 %}
6912
6913 // Compressed OOPs with narrow_oop_shift == 0.
6914 instruct decodeN_unscaled(iRegPdst dst, iRegNsrc src) %{
6915 match(Set dst (DecodeN src));
6916 predicate(Universe::narrow_oop_shift() == 0);
6917 ins_cost(DEFAULT_COST);
6918
6919 format %{ "MR $dst, $src \t// DecodeN (unscaled)" %}
6920 // variable size, 0 or 4.
6921 ins_encode %{
6922 // TODO: PPC port $archOpcode(ppc64Opcode_or);
6923 __ mr_if_needed($dst$$Register, $src$$Register);
6924 %}
6925 ins_pipe(pipe_class_default);
6926 %}
6927
6928 // Convert compressed oop into int for vectors alignment masking.
6929 instruct decodeN2I_unscaled(iRegIdst dst, iRegNsrc src) %{
6930 match(Set dst (ConvL2I (CastP2X (DecodeN src))));
6931 predicate(Universe::narrow_oop_shift() == 0);
6932 ins_cost(DEFAULT_COST);
6933
6934 format %{ "MR $dst, $src \t// (int)DecodeN (unscaled)" %}
6935 // variable size, 0 or 4.
6936 ins_encode %{
6937 // TODO: PPC port $archOpcode(ppc64Opcode_or);
6938 __ mr_if_needed($dst$$Register, $src$$Register);
6939 %}
6940 ins_pipe(pipe_class_default);
6941 %}
6942
6943 // Convert klass pointer into compressed form.
6944
6945 // Nodes for postalloc expand.
6946
6947 // Shift node for expand.
6948 instruct encodePKlass_shift(iRegNdst dst, iRegNsrc src) %{
6949 // The match rule is needed to make it a 'MachTypeNode'!
6950 match(Set dst (EncodePKlass src));
6951 predicate(false);
6952
6953 format %{ "SRDI $dst, $src, 3 \t// encode" %}
6954 size(4);
6955 ins_encode %{
6956 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
6957 __ srdi($dst$$Register, $src$$Register, Universe::narrow_klass_shift());
6958 %}
6959 ins_pipe(pipe_class_default);
6960 %}
6961
6962 // Add node for expand.
6963 instruct encodePKlass_sub_base(iRegPdst dst, iRegLsrc base, iRegPdst src) %{
6964 // The match rule is needed to make it a 'MachTypeNode'!
6965 match(Set dst (EncodePKlass (Binary base src)));
6966 predicate(false);
6967
6968 format %{ "SUB $dst, $base, $src \t// encode" %}
6969 size(4);
6970 ins_encode %{
6971 // TODO: PPC port $archOpcode(ppc64Opcode_subf);
6972 __ subf($dst$$Register, $base$$Register, $src$$Register);
6973 %}
6974 ins_pipe(pipe_class_default);
6975 %}
6976
6977 // base != 0
6978 // 32G aligned narrow oop base.
6979 instruct encodePKlass_32GAligned(iRegNdst dst, iRegPsrc src) %{
6980 match(Set dst (EncodePKlass src));
6981 predicate(false /* TODO: PPC port Universe::narrow_klass_base_disjoint()*/);
6982
6983 format %{ "EXTRDI $dst, $src, #32, #3 \t// encode with 32G aligned base" %}
6984 size(4);
6985 ins_encode %{
6986 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
6987 __ rldicl($dst$$Register, $src$$Register, 64-Universe::narrow_klass_shift(), 32);
6988 %}
6989 ins_pipe(pipe_class_default);
6990 %}
6991
6992 // shift != 0, base != 0
6993 instruct encodePKlass_not_null_Ex(iRegNdst dst, iRegLsrc base, iRegPsrc src) %{
6994 match(Set dst (EncodePKlass (Binary base src)));
6995 predicate(false);
6996
6997 format %{ "EncodePKlass $dst, $src\t// $src != Null, postalloc expanded" %}
6998 postalloc_expand %{
6999 encodePKlass_sub_baseNode *n1 = new (C) encodePKlass_sub_baseNode();
7000 n1->add_req(n_region, n_base, n_src);
7001 n1->_opnds[0] = op_dst;
7002 n1->_opnds[1] = op_base;
7003 n1->_opnds[2] = op_src;
7004 n1->_bottom_type = _bottom_type;
7005
7006 encodePKlass_shiftNode *n2 = new (C) encodePKlass_shiftNode();
7007 n2->add_req(n_region, n1);
7008 n2->_opnds[0] = op_dst;
7009 n2->_opnds[1] = op_dst;
7010 n2->_bottom_type = _bottom_type;
7011 ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
7012 ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
7013
7014 nodes->push(n1);
7015 nodes->push(n2);
7016 %}
7017 %}
7018
7019 // shift != 0, base != 0
7020 instruct encodePKlass_not_null_ExEx(iRegNdst dst, iRegPsrc src) %{
7021 match(Set dst (EncodePKlass src));
7022 //predicate(Universe::narrow_klass_shift() != 0 &&
7023 // true /* TODO: PPC port Universe::narrow_klass_base_overlaps()*/);
7024
7025 //format %{ "EncodePKlass $dst, $src\t// $src != Null, postalloc expanded" %}
7026 ins_cost(DEFAULT_COST*2); // Don't count constant.
7027 expand %{
7028 immL baseImm %{ (jlong)(intptr_t)Universe::narrow_klass_base() %}
7029 iRegLdst base;
7030 loadConL_Ex(base, baseImm);
7031 encodePKlass_not_null_Ex(dst, base, src);
7032 %}
7033 %}
7034
7035 // Decode nodes.
7036
7037 // Shift node for expand.
7038 instruct decodeNKlass_shift(iRegPdst dst, iRegPsrc src) %{
7039 // The match rule is needed to make it a 'MachTypeNode'!
7040 match(Set dst (DecodeNKlass src));
7041 predicate(false);
7042
7043 format %{ "SLDI $dst, $src, #3 \t// DecodeNKlass" %}
7044 size(4);
7045 ins_encode %{
7046 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
7047 __ sldi($dst$$Register, $src$$Register, Universe::narrow_klass_shift());
7048 %}
7049 ins_pipe(pipe_class_default);
7050 %}
7051
7052 // Add node for expand.
7053
7054 instruct decodeNKlass_add_base(iRegPdst dst, iRegLsrc base, iRegPdst src) %{
7055 // The match rule is needed to make it a 'MachTypeNode'!
7056 match(Set dst (DecodeNKlass (Binary base src)));
7057 predicate(false);
7058
7059 format %{ "ADD $dst, $base, $src \t// DecodeNKlass, add klass base" %}
7060 size(4);
7061 ins_encode %{
7062 // TODO: PPC port $archOpcode(ppc64Opcode_add);
7063 __ add($dst$$Register, $base$$Register, $src$$Register);
7064 %}
7065 ins_pipe(pipe_class_default);
7066 %}
7067
7068 // src != 0, shift != 0, base != 0
7069 instruct decodeNKlass_notNull_addBase_Ex(iRegPdst dst, iRegLsrc base, iRegNsrc src) %{
7070 match(Set dst (DecodeNKlass (Binary base src)));
7071 //effect(kill src); // We need a register for the immediate result after shifting.
7072 predicate(false);
7073
7074 format %{ "DecodeNKlass $dst = $base + ($src << 3) \t// $src != NULL, postalloc expanded" %}
7075 postalloc_expand %{
7076 decodeNKlass_add_baseNode *n1 = new (C) decodeNKlass_add_baseNode();
7077 n1->add_req(n_region, n_base, n_src);
7078 n1->_opnds[0] = op_dst;
7079 n1->_opnds[1] = op_base;
7080 n1->_opnds[2] = op_src;
7081 n1->_bottom_type = _bottom_type;
7082
7083 decodeNKlass_shiftNode *n2 = new (C) decodeNKlass_shiftNode();
7084 n2->add_req(n_region, n1);
7085 n2->_opnds[0] = op_dst;
7086 n2->_opnds[1] = op_dst;
7087 n2->_bottom_type = _bottom_type;
7088
7089 ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
7090 ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
7091
7092 nodes->push(n1);
7093 nodes->push(n2);
7094 %}
7095 %}
7096
7097 // src != 0, shift != 0, base != 0
7098 instruct decodeNKlass_notNull_addBase_ExEx(iRegPdst dst, iRegNsrc src) %{
7099 match(Set dst (DecodeNKlass src));
7100 // predicate(Universe::narrow_klass_shift() != 0 &&
7101 // Universe::narrow_klass_base() != 0);
7102
7103 //format %{ "DecodeNKlass $dst, $src \t// $src != NULL, expanded" %}
7104
7105 ins_cost(DEFAULT_COST*2); // Don't count constant.
7106 expand %{
7107 // We add first, then we shift. Like this, we can get along with one register less.
7108 // But we have to load the base pre-shifted.
7109 immL baseImm %{ (jlong)((intptr_t)Universe::narrow_klass_base() >> Universe::narrow_klass_shift()) %}
7110 iRegLdst base;
7111 loadConL_Ex(base, baseImm);
7112 decodeNKlass_notNull_addBase_Ex(dst, base, src);
7113 %}
7114 %}
7115
7116 //----------MemBar Instructions-----------------------------------------------
7117 // Memory barrier flavors
7118
7119 instruct membar_acquire() %{
7120 match(LoadFence);
7121 ins_cost(4*MEMORY_REF_COST);
7122
7123 format %{ "MEMBAR-acquire" %}
7124 size(4);
7125 ins_encode %{
7126 // TODO: PPC port $archOpcode(ppc64Opcode_lwsync);
7127 __ acquire();
7128 %}
7129 ins_pipe(pipe_class_default);
7130 %}
7131
7132 instruct unnecessary_membar_acquire() %{
7133 match(MemBarAcquire);
7134 ins_cost(0);
7135
7136 format %{ " -- \t// redundant MEMBAR-acquire - empty" %}
7137 size(0);
7138 ins_encode( /*empty*/ );
7139 ins_pipe(pipe_class_default);
7140 %}
7141
7142 instruct membar_acquire_lock() %{
7143 match(MemBarAcquireLock);
7144 ins_cost(0);
7145
7146 format %{ " -- \t// redundant MEMBAR-acquire - empty (acquire as part of CAS in prior FastLock)" %}
7147 size(0);
7148 ins_encode( /*empty*/ );
7149 ins_pipe(pipe_class_default);
7150 %}
7151
7152 instruct membar_release() %{
7153 match(MemBarRelease);
7154 match(StoreFence);
7155 ins_cost(4*MEMORY_REF_COST);
7156
7157 format %{ "MEMBAR-release" %}
7158 size(4);
7159 ins_encode %{
7160 // TODO: PPC port $archOpcode(ppc64Opcode_lwsync);
7161 __ release();
7162 %}
7163 ins_pipe(pipe_class_default);
7164 %}
7165
7166 instruct membar_storestore() %{
7167 match(MemBarStoreStore);
7168 ins_cost(4*MEMORY_REF_COST);
7169
7170 format %{ "MEMBAR-store-store" %}
7171 size(4);
7172 ins_encode %{
7173 // TODO: PPC port $archOpcode(ppc64Opcode_lwsync);
7174 __ membar(Assembler::StoreStore);
7175 %}
7176 ins_pipe(pipe_class_default);
7177 %}
7178
7179 instruct membar_release_lock() %{
7180 match(MemBarReleaseLock);
7181 ins_cost(0);
7182
7183 format %{ " -- \t// redundant MEMBAR-release - empty (release in FastUnlock)" %}
7184 size(0);
7185 ins_encode( /*empty*/ );
7186 ins_pipe(pipe_class_default);
7187 %}
7188
7189 instruct membar_volatile() %{
7190 match(MemBarVolatile);
7191 ins_cost(4*MEMORY_REF_COST);
7192
7193 format %{ "MEMBAR-volatile" %}
7194 size(4);
7195 ins_encode %{
7196 // TODO: PPC port $archOpcode(ppc64Opcode_sync);
7197 __ fence();
7198 %}
7199 ins_pipe(pipe_class_default);
7200 %}
7201
7202 // This optimization is wrong on PPC. The following pattern is not supported:
7203 // MemBarVolatile
7204 // ^ ^
7205 // | |
7206 // CtrlProj MemProj
7207 // ^ ^
7208 // | |
7209 // | Load
7210 // |
7211 // MemBarVolatile
7212 //
7213 // The first MemBarVolatile could get optimized out! According to
7214 // Vladimir, this pattern can not occur on Oracle platforms.
7215 // However, it does occur on PPC64 (because of membars in
7216 // inline_unsafe_load_store).
7217 //
7218 // Add this node again if we found a good solution for inline_unsafe_load_store().
7219 // Don't forget to look at the implementation of post_store_load_barrier again,
7220 // we did other fixes in that method.
7221 //instruct unnecessary_membar_volatile() %{
7222 // match(MemBarVolatile);
7223 // predicate(Matcher::post_store_load_barrier(n));
7224 // ins_cost(0);
7225 //
7226 // format %{ " -- \t// redundant MEMBAR-volatile - empty" %}
7227 // size(0);
7228 // ins_encode( /*empty*/ );
7229 // ins_pipe(pipe_class_default);
7230 //%}
7231
7232 instruct membar_CPUOrder() %{
7233 match(MemBarCPUOrder);
7234 ins_cost(0);
7235
7236 format %{ " -- \t// MEMBAR-CPUOrder - empty: PPC64 processors are self-consistent." %}
7237 size(0);
7238 ins_encode( /*empty*/ );
7239 ins_pipe(pipe_class_default);
7240 %}
7241
7242 //----------Conditional Move---------------------------------------------------
7243
7244 // Cmove using isel.
7245 instruct cmovI_reg_isel(cmpOp cmp, flagsReg crx, iRegIdst dst, iRegIsrc src) %{
7246 match(Set dst (CMoveI (Binary cmp crx) (Binary dst src)));
7247 predicate(VM_Version::has_isel());
7248 ins_cost(DEFAULT_COST);
7249
7250 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7251 size(4);
7252 ins_encode %{
7253 // This is a Power7 instruction for which no machine description
7254 // exists. Anyways, the scheduler should be off on Power7.
7255 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7256 int cc = $cmp$$cmpcode;
7257 __ isel($dst$$Register, $crx$$CondRegister,
7258 (Assembler::Condition)(cc & 3), /*invert*/((~cc) & 8), $src$$Register);
7259 %}
7260 ins_pipe(pipe_class_default);
7261 %}
7262
7263 instruct cmovI_reg(cmpOp cmp, flagsReg crx, iRegIdst dst, iRegIsrc src) %{
7264 match(Set dst (CMoveI (Binary cmp crx) (Binary dst src)));
7265 predicate(!VM_Version::has_isel());
7266 ins_cost(DEFAULT_COST+BRANCH_COST);
7267
7268 ins_variable_size_depending_on_alignment(true);
7269
7270 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7271 // Worst case is branch + move + stop, no stop without scheduler
7272 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7273 ins_encode( enc_cmove_reg(dst, crx, src, cmp) );
7274 ins_pipe(pipe_class_default);
7275 %}
7276
7277 instruct cmovI_imm(cmpOp cmp, flagsReg crx, iRegIdst dst, immI16 src) %{
7278 match(Set dst (CMoveI (Binary cmp crx) (Binary dst src)));
7279 ins_cost(DEFAULT_COST+BRANCH_COST);
7280
7281 ins_variable_size_depending_on_alignment(true);
7282
7283 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7284 // Worst case is branch + move + stop, no stop without scheduler
7285 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7286 ins_encode( enc_cmove_imm(dst, crx, src, cmp) );
7287 ins_pipe(pipe_class_default);
7288 %}
7289
7290 // Cmove using isel.
7291 instruct cmovL_reg_isel(cmpOp cmp, flagsReg crx, iRegLdst dst, iRegLsrc src) %{
7292 match(Set dst (CMoveL (Binary cmp crx) (Binary dst src)));
7293 predicate(VM_Version::has_isel());
7294 ins_cost(DEFAULT_COST);
7295
7296 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7297 size(4);
7298 ins_encode %{
7299 // This is a Power7 instruction for which no machine description
7300 // exists. Anyways, the scheduler should be off on Power7.
7301 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7302 int cc = $cmp$$cmpcode;
7303 __ isel($dst$$Register, $crx$$CondRegister,
7304 (Assembler::Condition)(cc & 3), /*invert*/((~cc) & 8), $src$$Register);
7305 %}
7306 ins_pipe(pipe_class_default);
7307 %}
7308
7309 instruct cmovL_reg(cmpOp cmp, flagsReg crx, iRegLdst dst, iRegLsrc src) %{
7310 match(Set dst (CMoveL (Binary cmp crx) (Binary dst src)));
7311 predicate(!VM_Version::has_isel());
7312 ins_cost(DEFAULT_COST+BRANCH_COST);
7313
7314 ins_variable_size_depending_on_alignment(true);
7315
7316 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7317 // Worst case is branch + move + stop, no stop without scheduler.
7318 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7319 ins_encode( enc_cmove_reg(dst, crx, src, cmp) );
7320 ins_pipe(pipe_class_default);
7321 %}
7322
7323 instruct cmovL_imm(cmpOp cmp, flagsReg crx, iRegLdst dst, immL16 src) %{
7324 match(Set dst (CMoveL (Binary cmp crx) (Binary dst src)));
7325 ins_cost(DEFAULT_COST+BRANCH_COST);
7326
7327 ins_variable_size_depending_on_alignment(true);
7328
7329 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7330 // Worst case is branch + move + stop, no stop without scheduler.
7331 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7332 ins_encode( enc_cmove_imm(dst, crx, src, cmp) );
7333 ins_pipe(pipe_class_default);
7334 %}
7335
7336 // Cmove using isel.
7337 instruct cmovN_reg_isel(cmpOp cmp, flagsReg crx, iRegNdst dst, iRegNsrc src) %{
7338 match(Set dst (CMoveN (Binary cmp crx) (Binary dst src)));
7339 predicate(VM_Version::has_isel());
7340 ins_cost(DEFAULT_COST);
7341
7342 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7343 size(4);
7344 ins_encode %{
7345 // This is a Power7 instruction for which no machine description
7346 // exists. Anyways, the scheduler should be off on Power7.
7347 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7348 int cc = $cmp$$cmpcode;
7349 __ isel($dst$$Register, $crx$$CondRegister,
7350 (Assembler::Condition)(cc & 3), /*invert*/((~cc) & 8), $src$$Register);
7351 %}
7352 ins_pipe(pipe_class_default);
7353 %}
7354
7355 // Conditional move for RegN. Only cmov(reg, reg).
7356 instruct cmovN_reg(cmpOp cmp, flagsReg crx, iRegNdst dst, iRegNsrc src) %{
7357 match(Set dst (CMoveN (Binary cmp crx) (Binary dst src)));
7358 predicate(!VM_Version::has_isel());
7359 ins_cost(DEFAULT_COST+BRANCH_COST);
7360
7361 ins_variable_size_depending_on_alignment(true);
7362
7363 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7364 // Worst case is branch + move + stop, no stop without scheduler.
7365 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7366 ins_encode( enc_cmove_reg(dst, crx, src, cmp) );
7367 ins_pipe(pipe_class_default);
7368 %}
7369
7370 instruct cmovN_imm(cmpOp cmp, flagsReg crx, iRegNdst dst, immN_0 src) %{
7371 match(Set dst (CMoveN (Binary cmp crx) (Binary dst src)));
7372 ins_cost(DEFAULT_COST+BRANCH_COST);
7373
7374 ins_variable_size_depending_on_alignment(true);
7375
7376 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7377 // Worst case is branch + move + stop, no stop without scheduler.
7378 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7379 ins_encode( enc_cmove_imm(dst, crx, src, cmp) );
7380 ins_pipe(pipe_class_default);
7381 %}
7382
7383 // Cmove using isel.
7384 instruct cmovP_reg_isel(cmpOp cmp, flagsReg crx, iRegPdst dst, iRegPsrc src) %{
7385 match(Set dst (CMoveP (Binary cmp crx) (Binary dst src)));
7386 predicate(VM_Version::has_isel());
7387 ins_cost(DEFAULT_COST);
7388
7389 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7390 size(4);
7391 ins_encode %{
7392 // This is a Power7 instruction for which no machine description
7393 // exists. Anyways, the scheduler should be off on Power7.
7394 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7395 int cc = $cmp$$cmpcode;
7396 __ isel($dst$$Register, $crx$$CondRegister,
7397 (Assembler::Condition)(cc & 3), /*invert*/((~cc) & 8), $src$$Register);
7398 %}
7399 ins_pipe(pipe_class_default);
7400 %}
7401
7402 instruct cmovP_reg(cmpOp cmp, flagsReg crx, iRegPdst dst, iRegP_N2P src) %{
7403 match(Set dst (CMoveP (Binary cmp crx) (Binary dst src)));
7404 predicate(!VM_Version::has_isel());
7405 ins_cost(DEFAULT_COST+BRANCH_COST);
7406
7407 ins_variable_size_depending_on_alignment(true);
7408
7409 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7410 // Worst case is branch + move + stop, no stop without scheduler.
7411 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7412 ins_encode( enc_cmove_reg(dst, crx, src, cmp) );
7413 ins_pipe(pipe_class_default);
7414 %}
7415
7416 instruct cmovP_imm(cmpOp cmp, flagsReg crx, iRegPdst dst, immP_0 src) %{
7417 match(Set dst (CMoveP (Binary cmp crx) (Binary dst src)));
7418 ins_cost(DEFAULT_COST+BRANCH_COST);
7419
7420 ins_variable_size_depending_on_alignment(true);
7421
7422 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7423 // Worst case is branch + move + stop, no stop without scheduler.
7424 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7425 ins_encode( enc_cmove_imm(dst, crx, src, cmp) );
7426 ins_pipe(pipe_class_default);
7427 %}
7428
7429 instruct cmovF_reg(cmpOp cmp, flagsReg crx, regF dst, regF src) %{
7430 match(Set dst (CMoveF (Binary cmp crx) (Binary dst src)));
7431 ins_cost(DEFAULT_COST+BRANCH_COST);
7432
7433 ins_variable_size_depending_on_alignment(true);
7434
7435 format %{ "CMOVEF $cmp, $crx, $dst, $src\n\t" %}
7436 // Worst case is branch + move + stop, no stop without scheduler.
7437 size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8);
7438 ins_encode %{
7439 // TODO: PPC port $archOpcode(ppc64Opcode_cmovef);
7440 Label done;
7441 assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding");
7442 // Branch if not (cmp crx).
7443 __ bc(cc_to_inverse_boint($cmp$$cmpcode), cc_to_biint($cmp$$cmpcode, $crx$$reg), done);
7444 __ fmr($dst$$FloatRegister, $src$$FloatRegister);
7445 // TODO PPC port __ endgroup_if_needed(_size == 12);
7446 __ bind(done);
7447 %}
7448 ins_pipe(pipe_class_default);
7449 %}
7450
7451 instruct cmovD_reg(cmpOp cmp, flagsReg crx, regD dst, regD src) %{
7452 match(Set dst (CMoveD (Binary cmp crx) (Binary dst src)));
7453 ins_cost(DEFAULT_COST+BRANCH_COST);
7454
7455 ins_variable_size_depending_on_alignment(true);
7456
7457 format %{ "CMOVEF $cmp, $crx, $dst, $src\n\t" %}
7458 // Worst case is branch + move + stop, no stop without scheduler.
7459 size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8);
7460 ins_encode %{
7461 // TODO: PPC port $archOpcode(ppc64Opcode_cmovef);
7462 Label done;
7463 assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding");
7464 // Branch if not (cmp crx).
7465 __ bc(cc_to_inverse_boint($cmp$$cmpcode), cc_to_biint($cmp$$cmpcode, $crx$$reg), done);
7466 __ fmr($dst$$FloatRegister, $src$$FloatRegister);
7467 // TODO PPC port __ endgroup_if_needed(_size == 12);
7468 __ bind(done);
7469 %}
7470 ins_pipe(pipe_class_default);
7471 %}
7472
7473 //----------Conditional_store--------------------------------------------------
7474 // Conditional-store of the updated heap-top.
7475 // Used during allocation of the shared heap.
7476 // Sets flags (EQ) on success. Implemented with a CASA on Sparc.
7477
7478 // As compareAndSwapL, but return flag register instead of boolean value in
7479 // int register.
7480 // Used by sun/misc/AtomicLongCSImpl.java.
7481 // Mem_ptr must be a memory operand, else this node does not get
7482 // Flag_needs_anti_dependence_check set by adlc. If this is not set this node
7483 // can be rematerialized which leads to errors.
7484 instruct storeLConditional_regP_regL_regL(flagsReg crx, indirect mem_ptr, iRegLsrc oldVal, iRegLsrc newVal) %{
7485 match(Set crx (StoreLConditional mem_ptr (Binary oldVal newVal)));
7486 format %{ "CMPXCHGD if ($crx = ($oldVal == *$mem_ptr)) *mem_ptr = $newVal; as bool" %}
7487 ins_encode %{
7488 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7489 __ cmpxchgd($crx$$CondRegister, R0, $oldVal$$Register, $newVal$$Register, $mem_ptr$$Register,
7490 MacroAssembler::MemBarNone, MacroAssembler::cmpxchgx_hint_atomic_update(),
7491 noreg, NULL, true);
7492 %}
7493 ins_pipe(pipe_class_default);
7494 %}
7495
7496 // As compareAndSwapP, but return flag register instead of boolean value in
7497 // int register.
7498 // This instruction is matched if UseTLAB is off.
7499 // Mem_ptr must be a memory operand, else this node does not get
7500 // Flag_needs_anti_dependence_check set by adlc. If this is not set this node
7501 // can be rematerialized which leads to errors.
7502 instruct storePConditional_regP_regP_regP(flagsReg crx, indirect mem_ptr, iRegPsrc oldVal, iRegPsrc newVal) %{
7503 match(Set crx (StorePConditional mem_ptr (Binary oldVal newVal)));
7504 format %{ "CMPXCHGD if ($crx = ($oldVal == *$mem_ptr)) *mem_ptr = $newVal; as bool" %}
7505 ins_encode %{
7506 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7507 __ cmpxchgd($crx$$CondRegister, R0, $oldVal$$Register, $newVal$$Register, $mem_ptr$$Register,
7508 MacroAssembler::MemBarNone, MacroAssembler::cmpxchgx_hint_atomic_update(),
7509 noreg, NULL, true);
7510 %}
7511 ins_pipe(pipe_class_default);
7512 %}
7513
7514 // Implement LoadPLocked. Must be ordered against changes of the memory location
7515 // by storePConditional.
7516 // Don't know whether this is ever used.
7517 instruct loadPLocked(iRegPdst dst, memory mem) %{
7518 match(Set dst (LoadPLocked mem));
7519 ins_cost(MEMORY_REF_COST);
7520
7521 format %{ "LD $dst, $mem \t// loadPLocked\n\t"
7522 "TWI $dst\n\t"
7523 "ISYNC" %}
7524 size(12);
7525 ins_encode( enc_ld_ac(dst, mem) );
7526 ins_pipe(pipe_class_memory);
7527 %}
7528
7529 //----------Compare-And-Swap---------------------------------------------------
7530
7531 // CompareAndSwap{P,I,L} have more than one output, therefore "CmpI
7532 // (CompareAndSwap ...)" or "If (CmpI (CompareAndSwap ..))" cannot be
7533 // matched.
7534
7535 instruct compareAndSwapI_regP_regI_regI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src1, iRegIsrc src2) %{
7536 match(Set res (CompareAndSwapI mem_ptr (Binary src1 src2)));
7537 format %{ "CMPXCHGW $res, $mem_ptr, $src1, $src2; as bool" %}
7538 // Variable size: instruction count smaller if regs are disjoint.
7539 ins_encode %{
7540 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7541 // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7542 __ cmpxchgw(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
7543 MacroAssembler::MemBarFenceAfter, MacroAssembler::cmpxchgx_hint_atomic_update(),
7544 $res$$Register, true);
7545 %}
7546 ins_pipe(pipe_class_default);
7547 %}
7548
7549 instruct compareAndSwapN_regP_regN_regN(iRegIdst res, iRegPdst mem_ptr, iRegNsrc src1, iRegNsrc src2) %{
7550 match(Set res (CompareAndSwapN mem_ptr (Binary src1 src2)));
7551 format %{ "CMPXCHGW $res, $mem_ptr, $src1, $src2; as bool" %}
7552 // Variable size: instruction count smaller if regs are disjoint.
7553 ins_encode %{
7554 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7555 // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7556 __ cmpxchgw(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
7557 MacroAssembler::MemBarFenceAfter, MacroAssembler::cmpxchgx_hint_atomic_update(),
7558 $res$$Register, true);
7559 %}
7560 ins_pipe(pipe_class_default);
7561 %}
7562
7563 instruct compareAndSwapL_regP_regL_regL(iRegIdst res, iRegPdst mem_ptr, iRegLsrc src1, iRegLsrc src2) %{
7564 match(Set res (CompareAndSwapL mem_ptr (Binary src1 src2)));
7565 format %{ "CMPXCHGD $res, $mem_ptr, $src1, $src2; as bool" %}
7566 // Variable size: instruction count smaller if regs are disjoint.
7567 ins_encode %{
7568 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7569 // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7570 __ cmpxchgd(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
7571 MacroAssembler::MemBarFenceAfter, MacroAssembler::cmpxchgx_hint_atomic_update(),
7572 $res$$Register, NULL, true);
7573 %}
7574 ins_pipe(pipe_class_default);
7575 %}
7576
7577 instruct compareAndSwapP_regP_regP_regP(iRegIdst res, iRegPdst mem_ptr, iRegPsrc src1, iRegPsrc src2) %{
7578 match(Set res (CompareAndSwapP mem_ptr (Binary src1 src2)));
7579 format %{ "CMPXCHGD $res, $mem_ptr, $src1, $src2; as bool; ptr" %}
7580 // Variable size: instruction count smaller if regs are disjoint.
7581 ins_encode %{
7582 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7583 // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7584 __ cmpxchgd(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
7585 MacroAssembler::MemBarFenceAfter, MacroAssembler::cmpxchgx_hint_atomic_update(),
7586 $res$$Register, NULL, true);
7587 %}
7588 ins_pipe(pipe_class_default);
7589 %}
7590
7591 instruct getAndAddI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src) %{
7592 match(Set res (GetAndAddI mem_ptr src));
7593 format %{ "GetAndAddI $res, $mem_ptr, $src" %}
7594 // Variable size: instruction count smaller if regs are disjoint.
7595 ins_encode( enc_GetAndAddI(res, mem_ptr, src) );
7596 ins_pipe(pipe_class_default);
7597 %}
7598
7599 instruct getAndAddL(iRegLdst res, iRegPdst mem_ptr, iRegLsrc src) %{
7600 match(Set res (GetAndAddL mem_ptr src));
7601 format %{ "GetAndAddL $res, $mem_ptr, $src" %}
7602 // Variable size: instruction count smaller if regs are disjoint.
7603 ins_encode( enc_GetAndAddL(res, mem_ptr, src) );
7604 ins_pipe(pipe_class_default);
7605 %}
7606
7607 instruct getAndSetI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src) %{
7608 match(Set res (GetAndSetI mem_ptr src));
7609 format %{ "GetAndSetI $res, $mem_ptr, $src" %}
7610 // Variable size: instruction count smaller if regs are disjoint.
7611 ins_encode( enc_GetAndSetI(res, mem_ptr, src) );
7612 ins_pipe(pipe_class_default);
7613 %}
7614
7615 instruct getAndSetL(iRegLdst res, iRegPdst mem_ptr, iRegLsrc src) %{
7616 match(Set res (GetAndSetL mem_ptr src));
7617 format %{ "GetAndSetL $res, $mem_ptr, $src" %}
7618 // Variable size: instruction count smaller if regs are disjoint.
7619 ins_encode( enc_GetAndSetL(res, mem_ptr, src) );
7620 ins_pipe(pipe_class_default);
7621 %}
7622
7623 instruct getAndSetP(iRegPdst res, iRegPdst mem_ptr, iRegPsrc src) %{
7624 match(Set res (GetAndSetP mem_ptr src));
7625 format %{ "GetAndSetP $res, $mem_ptr, $src" %}
7626 // Variable size: instruction count smaller if regs are disjoint.
7627 ins_encode( enc_GetAndSetL(res, mem_ptr, src) );
7628 ins_pipe(pipe_class_default);
7629 %}
7630
7631 instruct getAndSetN(iRegNdst res, iRegPdst mem_ptr, iRegNsrc src) %{
7632 match(Set res (GetAndSetN mem_ptr src));
7633 format %{ "GetAndSetN $res, $mem_ptr, $src" %}
7634 // Variable size: instruction count smaller if regs are disjoint.
7635 ins_encode( enc_GetAndSetI(res, mem_ptr, src) );
7636 ins_pipe(pipe_class_default);
7637 %}
7638
7639 //----------Arithmetic Instructions--------------------------------------------
7640 // Addition Instructions
7641
7642 // Register Addition
7643 instruct addI_reg_reg(iRegIdst dst, iRegIsrc_iRegL2Isrc src1, iRegIsrc_iRegL2Isrc src2) %{
7644 match(Set dst (AddI src1 src2));
7645 format %{ "ADD $dst, $src1, $src2" %}
7646 size(4);
7647 ins_encode %{
7648 // TODO: PPC port $archOpcode(ppc64Opcode_add);
7649 __ add($dst$$Register, $src1$$Register, $src2$$Register);
7650 %}
7651 ins_pipe(pipe_class_default);
7652 %}
7653
7654 // Expand does not work with above instruct. (??)
7655 instruct addI_reg_reg_2(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
7656 // no match-rule
7657 effect(DEF dst, USE src1, USE src2);
7658 format %{ "ADD $dst, $src1, $src2" %}
7659 size(4);
7660 ins_encode %{
7661 // TODO: PPC port $archOpcode(ppc64Opcode_add);
7662 __ add($dst$$Register, $src1$$Register, $src2$$Register);
7663 %}
7664 ins_pipe(pipe_class_default);
7665 %}
7666
7667 instruct tree_addI_addI_addI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2, iRegIsrc src3, iRegIsrc src4) %{
7668 match(Set dst (AddI (AddI (AddI src1 src2) src3) src4));
7669 ins_cost(DEFAULT_COST*3);
7670
7671 expand %{
7672 // FIXME: we should do this in the ideal world.
7673 iRegIdst tmp1;
7674 iRegIdst tmp2;
7675 addI_reg_reg(tmp1, src1, src2);
7676 addI_reg_reg_2(tmp2, src3, src4); // Adlc complains about addI_reg_reg.
7677 addI_reg_reg(dst, tmp1, tmp2);
7678 %}
7679 %}
7680
7681 // Immediate Addition
7682 instruct addI_reg_imm16(iRegIdst dst, iRegIsrc src1, immI16 src2) %{
7683 match(Set dst (AddI src1 src2));
7684 format %{ "ADDI $dst, $src1, $src2" %}
7685 size(4);
7686 ins_encode %{
7687 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
7688 __ addi($dst$$Register, $src1$$Register, $src2$$constant);
7689 %}
7690 ins_pipe(pipe_class_default);
7691 %}
7692
7693 // Immediate Addition with 16-bit shifted operand
7694 instruct addI_reg_immhi16(iRegIdst dst, iRegIsrc src1, immIhi16 src2) %{
7695 match(Set dst (AddI src1 src2));
7696 format %{ "ADDIS $dst, $src1, $src2" %}
7697 size(4);
7698 ins_encode %{
7699 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
7700 __ addis($dst$$Register, $src1$$Register, ($src2$$constant)>>16);
7701 %}
7702 ins_pipe(pipe_class_default);
7703 %}
7704
7705 // Long Addition
7706 instruct addL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
7707 match(Set dst (AddL src1 src2));
7708 format %{ "ADD $dst, $src1, $src2 \t// long" %}
7709 size(4);
7710 ins_encode %{
7711 // TODO: PPC port $archOpcode(ppc64Opcode_add);
7712 __ add($dst$$Register, $src1$$Register, $src2$$Register);
7713 %}
7714 ins_pipe(pipe_class_default);
7715 %}
7716
7717 // Expand does not work with above instruct. (??)
7718 instruct addL_reg_reg_2(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
7719 // no match-rule
7720 effect(DEF dst, USE src1, USE src2);
7721 format %{ "ADD $dst, $src1, $src2 \t// long" %}
7722 size(4);
7723 ins_encode %{
7724 // TODO: PPC port $archOpcode(ppc64Opcode_add);
7725 __ add($dst$$Register, $src1$$Register, $src2$$Register);
7726 %}
7727 ins_pipe(pipe_class_default);
7728 %}
7729
7730 instruct tree_addL_addL_addL_reg_reg_Ex(iRegLdst dst, iRegLsrc src1, iRegLsrc src2, iRegLsrc src3, iRegLsrc src4) %{
7731 match(Set dst (AddL (AddL (AddL src1 src2) src3) src4));
7732 ins_cost(DEFAULT_COST*3);
7733
7734 expand %{
7735 // FIXME: we should do this in the ideal world.
7736 iRegLdst tmp1;
7737 iRegLdst tmp2;
7738 addL_reg_reg(tmp1, src1, src2);
7739 addL_reg_reg_2(tmp2, src3, src4); // Adlc complains about orI_reg_reg.
7740 addL_reg_reg(dst, tmp1, tmp2);
7741 %}
7742 %}
7743
7744 // AddL + ConvL2I.
7745 instruct addI_regL_regL(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{
7746 match(Set dst (ConvL2I (AddL src1 src2)));
7747
7748 format %{ "ADD $dst, $src1, $src2 \t// long + l2i" %}
7749 size(4);
7750 ins_encode %{
7751 // TODO: PPC port $archOpcode(ppc64Opcode_add);
7752 __ add($dst$$Register, $src1$$Register, $src2$$Register);
7753 %}
7754 ins_pipe(pipe_class_default);
7755 %}
7756
7757 // No constant pool entries required.
7758 instruct addL_reg_imm16(iRegLdst dst, iRegLsrc src1, immL16 src2) %{
7759 match(Set dst (AddL src1 src2));
7760
7761 format %{ "ADDI $dst, $src1, $src2" %}
7762 size(4);
7763 ins_encode %{
7764 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
7765 __ addi($dst$$Register, $src1$$Register, $src2$$constant);
7766 %}
7767 ins_pipe(pipe_class_default);
7768 %}
7769
7770 // Long Immediate Addition with 16-bit shifted operand.
7771 // No constant pool entries required.
7772 instruct addL_reg_immhi16(iRegLdst dst, iRegLsrc src1, immL32hi16 src2) %{
7773 match(Set dst (AddL src1 src2));
7774
7775 format %{ "ADDIS $dst, $src1, $src2" %}
7776 size(4);
7777 ins_encode %{
7778 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
7779 __ addis($dst$$Register, $src1$$Register, ($src2$$constant)>>16);
7780 %}
7781 ins_pipe(pipe_class_default);
7782 %}
7783
7784 // Pointer Register Addition
7785 instruct addP_reg_reg(iRegPdst dst, iRegP_N2P src1, iRegLsrc src2) %{
7786 match(Set dst (AddP src1 src2));
7787 format %{ "ADD $dst, $src1, $src2" %}
7788 size(4);
7789 ins_encode %{
7790 // TODO: PPC port $archOpcode(ppc64Opcode_add);
7791 __ add($dst$$Register, $src1$$Register, $src2$$Register);
7792 %}
7793 ins_pipe(pipe_class_default);
7794 %}
7795
7796 // Pointer Immediate Addition
7797 // No constant pool entries required.
7798 instruct addP_reg_imm16(iRegPdst dst, iRegP_N2P src1, immL16 src2) %{
7799 match(Set dst (AddP src1 src2));
7800
7801 format %{ "ADDI $dst, $src1, $src2" %}
7802 size(4);
7803 ins_encode %{
7804 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
7805 __ addi($dst$$Register, $src1$$Register, $src2$$constant);
7806 %}
7807 ins_pipe(pipe_class_default);
7808 %}
7809
7810 // Pointer Immediate Addition with 16-bit shifted operand.
7811 // No constant pool entries required.
7812 instruct addP_reg_immhi16(iRegPdst dst, iRegP_N2P src1, immL32hi16 src2) %{
7813 match(Set dst (AddP src1 src2));
7814
7815 format %{ "ADDIS $dst, $src1, $src2" %}
7816 size(4);
7817 ins_encode %{
7818 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
7819 __ addis($dst$$Register, $src1$$Register, ($src2$$constant)>>16);
7820 %}
7821 ins_pipe(pipe_class_default);
7822 %}
7823
7824 //---------------------
7825 // Subtraction Instructions
7826
7827 // Register Subtraction
7828 instruct subI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
7829 match(Set dst (SubI src1 src2));
7830 format %{ "SUBF $dst, $src2, $src1" %}
7831 size(4);
7832 ins_encode %{
7833 // TODO: PPC port $archOpcode(ppc64Opcode_subf);
7834 __ subf($dst$$Register, $src2$$Register, $src1$$Register);
7835 %}
7836 ins_pipe(pipe_class_default);
7837 %}
7838
7839 // Immediate Subtraction
7840 // The compiler converts "x-c0" into "x+ -c0" (see SubINode::Ideal),
7841 // so this rule seems to be unused.
7842 instruct subI_reg_imm16(iRegIdst dst, iRegIsrc src1, immI16 src2) %{
7843 match(Set dst (SubI src1 src2));
7844 format %{ "SUBI $dst, $src1, $src2" %}
7845 size(4);
7846 ins_encode %{
7847 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
7848 __ addi($dst$$Register, $src1$$Register, ($src2$$constant) * (-1));
7849 %}
7850 ins_pipe(pipe_class_default);
7851 %}
7852
7853 // SubI from constant (using subfic).
7854 instruct subI_imm16_reg(iRegIdst dst, immI16 src1, iRegIsrc src2) %{
7855 match(Set dst (SubI src1 src2));
7856 format %{ "SUBI $dst, $src1, $src2" %}
7857
7858 size(4);
7859 ins_encode %{
7860 // TODO: PPC port $archOpcode(ppc64Opcode_subfic);
7861 __ subfic($dst$$Register, $src2$$Register, $src1$$constant);
7862 %}
7863 ins_pipe(pipe_class_default);
7864 %}
7865
7866 // Turn the sign-bit of an integer into a 32-bit mask, 0x0...0 for
7867 // positive integers and 0xF...F for negative ones.
7868 instruct signmask32I_regI(iRegIdst dst, iRegIsrc src) %{
7869 // no match-rule, false predicate
7870 effect(DEF dst, USE src);
7871 predicate(false);
7872
7873 format %{ "SRAWI $dst, $src, #31" %}
7874 size(4);
7875 ins_encode %{
7876 // TODO: PPC port $archOpcode(ppc64Opcode_srawi);
7877 __ srawi($dst$$Register, $src$$Register, 0x1f);
7878 %}
7879 ins_pipe(pipe_class_default);
7880 %}
7881
7882 instruct absI_reg_Ex(iRegIdst dst, iRegIsrc src) %{
7883 match(Set dst (AbsI src));
7884 ins_cost(DEFAULT_COST*3);
7885
7886 expand %{
7887 iRegIdst tmp1;
7888 iRegIdst tmp2;
7889 signmask32I_regI(tmp1, src);
7890 xorI_reg_reg(tmp2, tmp1, src);
7891 subI_reg_reg(dst, tmp2, tmp1);
7892 %}
7893 %}
7894
7895 instruct negI_regI(iRegIdst dst, immI_0 zero, iRegIsrc src2) %{
7896 match(Set dst (SubI zero src2));
7897 format %{ "NEG $dst, $src2" %}
7898 size(4);
7899 ins_encode %{
7900 // TODO: PPC port $archOpcode(ppc64Opcode_neg);
7901 __ neg($dst$$Register, $src2$$Register);
7902 %}
7903 ins_pipe(pipe_class_default);
7904 %}
7905
7906 // Long subtraction
7907 instruct subL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
7908 match(Set dst (SubL src1 src2));
7909 format %{ "SUBF $dst, $src2, $src1 \t// long" %}
7910 size(4);
7911 ins_encode %{
7912 // TODO: PPC port $archOpcode(ppc64Opcode_subf);
7913 __ subf($dst$$Register, $src2$$Register, $src1$$Register);
7914 %}
7915 ins_pipe(pipe_class_default);
7916 %}
7917
7918 // SubL + convL2I.
7919 instruct subI_regL_regL(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{
7920 match(Set dst (ConvL2I (SubL src1 src2)));
7921
7922 format %{ "SUBF $dst, $src2, $src1 \t// long + l2i" %}
7923 size(4);
7924 ins_encode %{
7925 // TODO: PPC port $archOpcode(ppc64Opcode_subf);
7926 __ subf($dst$$Register, $src2$$Register, $src1$$Register);
7927 %}
7928 ins_pipe(pipe_class_default);
7929 %}
7930
7931 // Immediate Subtraction
7932 // The compiler converts "x-c0" into "x+ -c0" (see SubLNode::Ideal),
7933 // so this rule seems to be unused.
7934 // No constant pool entries required.
7935 instruct subL_reg_imm16(iRegLdst dst, iRegLsrc src1, immL16 src2) %{
7936 match(Set dst (SubL src1 src2));
7937
7938 format %{ "SUBI $dst, $src1, $src2 \t// long" %}
7939 size(4);
7940 ins_encode %{
7941 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
7942 __ addi($dst$$Register, $src1$$Register, ($src2$$constant) * (-1));
7943 %}
7944 ins_pipe(pipe_class_default);
7945 %}
7946
7947 // Turn the sign-bit of a long into a 64-bit mask, 0x0...0 for
7948 // positive longs and 0xF...F for negative ones.
7949 instruct signmask64I_regL(iRegIdst dst, iRegLsrc src) %{
7950 // no match-rule, false predicate
7951 effect(DEF dst, USE src);
7952 predicate(false);
7953
7954 format %{ "SRADI $dst, $src, #63" %}
7955 size(4);
7956 ins_encode %{
7957 // TODO: PPC port $archOpcode(ppc64Opcode_sradi);
7958 __ sradi($dst$$Register, $src$$Register, 0x3f);
7959 %}
7960 ins_pipe(pipe_class_default);
7961 %}
7962
7963 // Turn the sign-bit of a long into a 64-bit mask, 0x0...0 for
7964 // positive longs and 0xF...F for negative ones.
7965 instruct signmask64L_regL(iRegLdst dst, iRegLsrc src) %{
7966 // no match-rule, false predicate
7967 effect(DEF dst, USE src);
7968 predicate(false);
7969
7970 format %{ "SRADI $dst, $src, #63" %}
7971 size(4);
7972 ins_encode %{
7973 // TODO: PPC port $archOpcode(ppc64Opcode_sradi);
7974 __ sradi($dst$$Register, $src$$Register, 0x3f);
7975 %}
7976 ins_pipe(pipe_class_default);
7977 %}
7978
7979 // Long negation
7980 instruct negL_reg_reg(iRegLdst dst, immL_0 zero, iRegLsrc src2) %{
7981 match(Set dst (SubL zero src2));
7982 format %{ "NEG $dst, $src2 \t// long" %}
7983 size(4);
7984 ins_encode %{
7985 // TODO: PPC port $archOpcode(ppc64Opcode_neg);
7986 __ neg($dst$$Register, $src2$$Register);
7987 %}
7988 ins_pipe(pipe_class_default);
7989 %}
7990
7991 // NegL + ConvL2I.
7992 instruct negI_con0_regL(iRegIdst dst, immL_0 zero, iRegLsrc src2) %{
7993 match(Set dst (ConvL2I (SubL zero src2)));
7994
7995 format %{ "NEG $dst, $src2 \t// long + l2i" %}
7996 size(4);
7997 ins_encode %{
7998 // TODO: PPC port $archOpcode(ppc64Opcode_neg);
7999 __ neg($dst$$Register, $src2$$Register);
8000 %}
8001 ins_pipe(pipe_class_default);
8002 %}
8003
8004 // Multiplication Instructions
8005 // Integer Multiplication
8006
8007 // Register Multiplication
8008 instruct mulI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8009 match(Set dst (MulI src1 src2));
8010 ins_cost(DEFAULT_COST);
8011
8012 format %{ "MULLW $dst, $src1, $src2" %}
8013 size(4);
8014 ins_encode %{
8015 // TODO: PPC port $archOpcode(ppc64Opcode_mullw);
8016 __ mullw($dst$$Register, $src1$$Register, $src2$$Register);
8017 %}
8018 ins_pipe(pipe_class_default);
8019 %}
8020
8021 // Immediate Multiplication
8022 instruct mulI_reg_imm16(iRegIdst dst, iRegIsrc src1, immI16 src2) %{
8023 match(Set dst (MulI src1 src2));
8024 ins_cost(DEFAULT_COST);
8025
8026 format %{ "MULLI $dst, $src1, $src2" %}
8027 size(4);
8028 ins_encode %{
8029 // TODO: PPC port $archOpcode(ppc64Opcode_mulli);
8030 __ mulli($dst$$Register, $src1$$Register, $src2$$constant);
8031 %}
8032 ins_pipe(pipe_class_default);
8033 %}
8034
8035 instruct mulL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
8036 match(Set dst (MulL src1 src2));
8037 ins_cost(DEFAULT_COST);
8038
8039 format %{ "MULLD $dst $src1, $src2 \t// long" %}
8040 size(4);
8041 ins_encode %{
8042 // TODO: PPC port $archOpcode(ppc64Opcode_mulld);
8043 __ mulld($dst$$Register, $src1$$Register, $src2$$Register);
8044 %}
8045 ins_pipe(pipe_class_default);
8046 %}
8047
8048 // Multiply high for optimized long division by constant.
8049 instruct mulHighL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
8050 match(Set dst (MulHiL src1 src2));
8051 ins_cost(DEFAULT_COST);
8052
8053 format %{ "MULHD $dst $src1, $src2 \t// long" %}
8054 size(4);
8055 ins_encode %{
8056 // TODO: PPC port $archOpcode(ppc64Opcode_mulhd);
8057 __ mulhd($dst$$Register, $src1$$Register, $src2$$Register);
8058 %}
8059 ins_pipe(pipe_class_default);
8060 %}
8061
8062 // Immediate Multiplication
8063 instruct mulL_reg_imm16(iRegLdst dst, iRegLsrc src1, immL16 src2) %{
8064 match(Set dst (MulL src1 src2));
8065 ins_cost(DEFAULT_COST);
8066
8067 format %{ "MULLI $dst, $src1, $src2" %}
8068 size(4);
8069 ins_encode %{
8070 // TODO: PPC port $archOpcode(ppc64Opcode_mulli);
8071 __ mulli($dst$$Register, $src1$$Register, $src2$$constant);
8072 %}
8073 ins_pipe(pipe_class_default);
8074 %}
8075
8076 // Integer Division with Immediate -1: Negate.
8077 instruct divI_reg_immIvalueMinus1(iRegIdst dst, iRegIsrc src1, immI_minus1 src2) %{
8078 match(Set dst (DivI src1 src2));
8079 ins_cost(DEFAULT_COST);
8080
8081 format %{ "NEG $dst, $src1 \t// /-1" %}
8082 size(4);
8083 ins_encode %{
8084 // TODO: PPC port $archOpcode(ppc64Opcode_neg);
8085 __ neg($dst$$Register, $src1$$Register);
8086 %}
8087 ins_pipe(pipe_class_default);
8088 %}
8089
8090 // Integer Division with constant, but not -1.
8091 // We should be able to improve this by checking the type of src2.
8092 // It might well be that src2 is known to be positive.
8093 instruct divI_reg_regnotMinus1(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8094 match(Set dst (DivI src1 src2));
8095 predicate(n->in(2)->find_int_con(-1) != -1); // src2 is a constant, but not -1
8096 ins_cost(2*DEFAULT_COST);
8097
8098 format %{ "DIVW $dst, $src1, $src2 \t// /not-1" %}
8099 size(4);
8100 ins_encode %{
8101 // TODO: PPC port $archOpcode(ppc64Opcode_divw);
8102 __ divw($dst$$Register, $src1$$Register, $src2$$Register);
8103 %}
8104 ins_pipe(pipe_class_default);
8105 %}
8106
8107 instruct cmovI_bne_negI_reg(iRegIdst dst, flagsReg crx, iRegIsrc src1) %{
8108 effect(USE_DEF dst, USE src1, USE crx);
8109 predicate(false);
8110
8111 ins_variable_size_depending_on_alignment(true);
8112
8113 format %{ "CMOVE $dst, neg($src1), $crx" %}
8114 // Worst case is branch + move + stop, no stop without scheduler.
8115 size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8);
8116 ins_encode %{
8117 // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
8118 Label done;
8119 __ bne($crx$$CondRegister, done);
8120 __ neg($dst$$Register, $src1$$Register);
8121 // TODO PPC port __ endgroup_if_needed(_size == 12);
8122 __ bind(done);
8123 %}
8124 ins_pipe(pipe_class_default);
8125 %}
8126
8127 // Integer Division with Registers not containing constants.
8128 instruct divI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8129 match(Set dst (DivI src1 src2));
8130 ins_cost(10*DEFAULT_COST);
8131
8132 expand %{
8133 immI16 imm %{ (int)-1 %}
8134 flagsReg tmp1;
8135 cmpI_reg_imm16(tmp1, src2, imm); // check src2 == -1
8136 divI_reg_regnotMinus1(dst, src1, src2); // dst = src1 / src2
8137 cmovI_bne_negI_reg(dst, tmp1, src1); // cmove dst = neg(src1) if src2 == -1
8138 %}
8139 %}
8140
8141 // Long Division with Immediate -1: Negate.
8142 instruct divL_reg_immLvalueMinus1(iRegLdst dst, iRegLsrc src1, immL_minus1 src2) %{
8143 match(Set dst (DivL src1 src2));
8144 ins_cost(DEFAULT_COST);
8145
8146 format %{ "NEG $dst, $src1 \t// /-1, long" %}
8147 size(4);
8148 ins_encode %{
8149 // TODO: PPC port $archOpcode(ppc64Opcode_neg);
8150 __ neg($dst$$Register, $src1$$Register);
8151 %}
8152 ins_pipe(pipe_class_default);
8153 %}
8154
8155 // Long Division with constant, but not -1.
8156 instruct divL_reg_regnotMinus1(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
8157 match(Set dst (DivL src1 src2));
8158 predicate(n->in(2)->find_long_con(-1L) != -1L); // Src2 is a constant, but not -1.
8159 ins_cost(2*DEFAULT_COST);
8160
8161 format %{ "DIVD $dst, $src1, $src2 \t// /not-1, long" %}
8162 size(4);
8163 ins_encode %{
8164 // TODO: PPC port $archOpcode(ppc64Opcode_divd);
8165 __ divd($dst$$Register, $src1$$Register, $src2$$Register);
8166 %}
8167 ins_pipe(pipe_class_default);
8168 %}
8169
8170 instruct cmovL_bne_negL_reg(iRegLdst dst, flagsReg crx, iRegLsrc src1) %{
8171 effect(USE_DEF dst, USE src1, USE crx);
8172 predicate(false);
8173
8174 ins_variable_size_depending_on_alignment(true);
8175
8176 format %{ "CMOVE $dst, neg($src1), $crx" %}
8177 // Worst case is branch + move + stop, no stop without scheduler.
8178 size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8);
8179 ins_encode %{
8180 // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
8181 Label done;
8182 __ bne($crx$$CondRegister, done);
8183 __ neg($dst$$Register, $src1$$Register);
8184 // TODO PPC port __ endgroup_if_needed(_size == 12);
8185 __ bind(done);
8186 %}
8187 ins_pipe(pipe_class_default);
8188 %}
8189
8190 // Long Division with Registers not containing constants.
8191 instruct divL_reg_reg_Ex(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
8192 match(Set dst (DivL src1 src2));
8193 ins_cost(10*DEFAULT_COST);
8194
8195 expand %{
8196 immL16 imm %{ (int)-1 %}
8197 flagsReg tmp1;
8198 cmpL_reg_imm16(tmp1, src2, imm); // check src2 == -1
8199 divL_reg_regnotMinus1(dst, src1, src2); // dst = src1 / src2
8200 cmovL_bne_negL_reg(dst, tmp1, src1); // cmove dst = neg(src1) if src2 == -1
8201 %}
8202 %}
8203
8204 // Integer Remainder with registers.
8205 instruct modI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8206 match(Set dst (ModI src1 src2));
8207 ins_cost(10*DEFAULT_COST);
8208
8209 expand %{
8210 immI16 imm %{ (int)-1 %}
8211 flagsReg tmp1;
8212 iRegIdst tmp2;
8213 iRegIdst tmp3;
8214 cmpI_reg_imm16(tmp1, src2, imm); // check src2 == -1
8215 divI_reg_regnotMinus1(tmp2, src1, src2); // tmp2 = src1 / src2
8216 cmovI_bne_negI_reg(tmp2, tmp1, src1); // cmove tmp2 = neg(src1) if src2 == -1
8217 mulI_reg_reg(tmp3, src2, tmp2); // tmp3 = src2 * tmp2
8218 subI_reg_reg(dst, src1, tmp3); // dst = src1 - tmp3
8219 %}
8220 %}
8221
8222 // Long Remainder with registers
8223 instruct modL_reg_reg_Ex(iRegLdst dst, iRegLsrc src1, iRegLsrc src2, flagsRegCR0 cr0) %{
8224 match(Set dst (ModL src1 src2));
8225 ins_cost(10*DEFAULT_COST);
8226
8227 expand %{
8228 immL16 imm %{ (int)-1 %}
8229 flagsReg tmp1;
8230 iRegLdst tmp2;
8231 iRegLdst tmp3;
8232 cmpL_reg_imm16(tmp1, src2, imm); // check src2 == -1
8233 divL_reg_regnotMinus1(tmp2, src1, src2); // tmp2 = src1 / src2
8234 cmovL_bne_negL_reg(tmp2, tmp1, src1); // cmove tmp2 = neg(src1) if src2 == -1
8235 mulL_reg_reg(tmp3, src2, tmp2); // tmp3 = src2 * tmp2
8236 subL_reg_reg(dst, src1, tmp3); // dst = src1 - tmp3
8237 %}
8238 %}
8239
8240 // Integer Shift Instructions
8241
8242 // Register Shift Left
8243
8244 // Clear all but the lowest #mask bits.
8245 // Used to normalize shift amounts in registers.
8246 instruct maskI_reg_imm(iRegIdst dst, iRegIsrc src, uimmI6 mask) %{
8247 // no match-rule, false predicate
8248 effect(DEF dst, USE src, USE mask);
8249 predicate(false);
8250
8251 format %{ "MASK $dst, $src, $mask \t// clear $mask upper bits" %}
8252 size(4);
8253 ins_encode %{
8254 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
8255 __ clrldi($dst$$Register, $src$$Register, $mask$$constant);
8256 %}
8257 ins_pipe(pipe_class_default);
8258 %}
8259
8260 instruct lShiftI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8261 // no match-rule, false predicate
8262 effect(DEF dst, USE src1, USE src2);
8263 predicate(false);
8264
8265 format %{ "SLW $dst, $src1, $src2" %}
8266 size(4);
8267 ins_encode %{
8268 // TODO: PPC port $archOpcode(ppc64Opcode_slw);
8269 __ slw($dst$$Register, $src1$$Register, $src2$$Register);
8270 %}
8271 ins_pipe(pipe_class_default);
8272 %}
8273
8274 instruct lShiftI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8275 match(Set dst (LShiftI src1 src2));
8276 ins_cost(DEFAULT_COST*2);
8277 expand %{
8278 uimmI6 mask %{ 0x3b /* clear 59 bits, keep 5 */ %}
8279 iRegIdst tmpI;
8280 maskI_reg_imm(tmpI, src2, mask);
8281 lShiftI_reg_reg(dst, src1, tmpI);
8282 %}
8283 %}
8284
8285 // Register Shift Left Immediate
8286 instruct lShiftI_reg_imm(iRegIdst dst, iRegIsrc src1, immI src2) %{
8287 match(Set dst (LShiftI src1 src2));
8288
8289 format %{ "SLWI $dst, $src1, ($src2 & 0x1f)" %}
8290 size(4);
8291 ins_encode %{
8292 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm);
8293 __ slwi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x1f);
8294 %}
8295 ins_pipe(pipe_class_default);
8296 %}
8297
8298 // AndI with negpow2-constant + LShiftI
8299 instruct lShiftI_andI_immInegpow2_imm5(iRegIdst dst, iRegIsrc src1, immInegpow2 src2, uimmI5 src3) %{
8300 match(Set dst (LShiftI (AndI src1 src2) src3));
8301 predicate(UseRotateAndMaskInstructionsPPC64);
8302
8303 format %{ "RLWINM $dst, lShiftI(AndI($src1, $src2), $src3)" %}
8304 size(4);
8305 ins_encode %{
8306 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm); // FIXME: assert that rlwinm is equal to addi
8307 long src2 = $src2$$constant;
8308 long src3 = $src3$$constant;
8309 long maskbits = src3 + log2_long((jlong) (julong) (juint) -src2);
8310 if (maskbits >= 32) {
8311 __ li($dst$$Register, 0); // addi
8312 } else {
8313 __ rlwinm($dst$$Register, $src1$$Register, src3 & 0x1f, 0, (31-maskbits) & 0x1f);
8314 }
8315 %}
8316 ins_pipe(pipe_class_default);
8317 %}
8318
8319 // RShiftI + AndI with negpow2-constant + LShiftI
8320 instruct lShiftI_andI_immInegpow2_rShiftI_imm5(iRegIdst dst, iRegIsrc src1, immInegpow2 src2, uimmI5 src3) %{
8321 match(Set dst (LShiftI (AndI (RShiftI src1 src3) src2) src3));
8322 predicate(UseRotateAndMaskInstructionsPPC64);
8323
8324 format %{ "RLWINM $dst, lShiftI(AndI(RShiftI($src1, $src3), $src2), $src3)" %}
8325 size(4);
8326 ins_encode %{
8327 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm); // FIXME: assert that rlwinm is equal to addi
8328 long src2 = $src2$$constant;
8329 long src3 = $src3$$constant;
8330 long maskbits = src3 + log2_long((jlong) (julong) (juint) -src2);
8331 if (maskbits >= 32) {
8332 __ li($dst$$Register, 0); // addi
8333 } else {
8334 __ rlwinm($dst$$Register, $src1$$Register, 0, 0, (31-maskbits) & 0x1f);
8335 }
8336 %}
8337 ins_pipe(pipe_class_default);
8338 %}
8339
8340 instruct lShiftL_regL_regI(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{
8341 // no match-rule, false predicate
8342 effect(DEF dst, USE src1, USE src2);
8343 predicate(false);
8344
8345 format %{ "SLD $dst, $src1, $src2" %}
8346 size(4);
8347 ins_encode %{
8348 // TODO: PPC port $archOpcode(ppc64Opcode_sld);
8349 __ sld($dst$$Register, $src1$$Register, $src2$$Register);
8350 %}
8351 ins_pipe(pipe_class_default);
8352 %}
8353
8354 // Register Shift Left
8355 instruct lShiftL_regL_regI_Ex(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{
8356 match(Set dst (LShiftL src1 src2));
8357 ins_cost(DEFAULT_COST*2);
8358 expand %{
8359 uimmI6 mask %{ 0x3a /* clear 58 bits, keep 6 */ %}
8360 iRegIdst tmpI;
8361 maskI_reg_imm(tmpI, src2, mask);
8362 lShiftL_regL_regI(dst, src1, tmpI);
8363 %}
8364 %}
8365
8366 // Register Shift Left Immediate
8367 instruct lshiftL_regL_immI(iRegLdst dst, iRegLsrc src1, immI src2) %{
8368 match(Set dst (LShiftL src1 src2));
8369 format %{ "SLDI $dst, $src1, ($src2 & 0x3f)" %}
8370 size(4);
8371 ins_encode %{
8372 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
8373 __ sldi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
8374 %}
8375 ins_pipe(pipe_class_default);
8376 %}
8377
8378 // If we shift more than 32 bits, we need not convert I2L.
8379 instruct lShiftL_regI_immGE32(iRegLdst dst, iRegIsrc src1, uimmI6_ge32 src2) %{
8380 match(Set dst (LShiftL (ConvI2L src1) src2));
8381 ins_cost(DEFAULT_COST);
8382
8383 size(4);
8384 format %{ "SLDI $dst, i2l($src1), $src2" %}
8385 ins_encode %{
8386 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
8387 __ sldi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
8388 %}
8389 ins_pipe(pipe_class_default);
8390 %}
8391
8392 // Shift a postivie int to the left.
8393 // Clrlsldi clears the upper 32 bits and shifts.
8394 instruct scaledPositiveI2L_lShiftL_convI2L_reg_imm6(iRegLdst dst, iRegIsrc src1, uimmI6 src2) %{
8395 match(Set dst (LShiftL (ConvI2L src1) src2));
8396 predicate(((ConvI2LNode*)(_kids[0]->_leaf))->type()->is_long()->is_positive_int());
8397
8398 format %{ "SLDI $dst, i2l(positive_int($src1)), $src2" %}
8399 size(4);
8400 ins_encode %{
8401 // TODO: PPC port $archOpcode(ppc64Opcode_rldic);
8402 __ clrlsldi($dst$$Register, $src1$$Register, 0x20, $src2$$constant);
8403 %}
8404 ins_pipe(pipe_class_default);
8405 %}
8406
8407 instruct arShiftI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8408 // no match-rule, false predicate
8409 effect(DEF dst, USE src1, USE src2);
8410 predicate(false);
8411
8412 format %{ "SRAW $dst, $src1, $src2" %}
8413 size(4);
8414 ins_encode %{
8415 // TODO: PPC port $archOpcode(ppc64Opcode_sraw);
8416 __ sraw($dst$$Register, $src1$$Register, $src2$$Register);
8417 %}
8418 ins_pipe(pipe_class_default);
8419 %}
8420
8421 // Register Arithmetic Shift Right
8422 instruct arShiftI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8423 match(Set dst (RShiftI src1 src2));
8424 ins_cost(DEFAULT_COST*2);
8425 expand %{
8426 uimmI6 mask %{ 0x3b /* clear 59 bits, keep 5 */ %}
8427 iRegIdst tmpI;
8428 maskI_reg_imm(tmpI, src2, mask);
8429 arShiftI_reg_reg(dst, src1, tmpI);
8430 %}
8431 %}
8432
8433 // Register Arithmetic Shift Right Immediate
8434 instruct arShiftI_reg_imm(iRegIdst dst, iRegIsrc src1, immI src2) %{
8435 match(Set dst (RShiftI src1 src2));
8436
8437 format %{ "SRAWI $dst, $src1, ($src2 & 0x1f)" %}
8438 size(4);
8439 ins_encode %{
8440 // TODO: PPC port $archOpcode(ppc64Opcode_srawi);
8441 __ srawi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x1f);
8442 %}
8443 ins_pipe(pipe_class_default);
8444 %}
8445
8446 instruct arShiftL_regL_regI(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{
8447 // no match-rule, false predicate
8448 effect(DEF dst, USE src1, USE src2);
8449 predicate(false);
8450
8451 format %{ "SRAD $dst, $src1, $src2" %}
8452 size(4);
8453 ins_encode %{
8454 // TODO: PPC port $archOpcode(ppc64Opcode_srad);
8455 __ srad($dst$$Register, $src1$$Register, $src2$$Register);
8456 %}
8457 ins_pipe(pipe_class_default);
8458 %}
8459
8460 // Register Shift Right Arithmetic Long
8461 instruct arShiftL_regL_regI_Ex(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{
8462 match(Set dst (RShiftL src1 src2));
8463 ins_cost(DEFAULT_COST*2);
8464
8465 expand %{
8466 uimmI6 mask %{ 0x3a /* clear 58 bits, keep 6 */ %}
8467 iRegIdst tmpI;
8468 maskI_reg_imm(tmpI, src2, mask);
8469 arShiftL_regL_regI(dst, src1, tmpI);
8470 %}
8471 %}
8472
8473 // Register Shift Right Immediate
8474 instruct arShiftL_regL_immI(iRegLdst dst, iRegLsrc src1, immI src2) %{
8475 match(Set dst (RShiftL src1 src2));
8476
8477 format %{ "SRADI $dst, $src1, ($src2 & 0x3f)" %}
8478 size(4);
8479 ins_encode %{
8480 // TODO: PPC port $archOpcode(ppc64Opcode_sradi);
8481 __ sradi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
8482 %}
8483 ins_pipe(pipe_class_default);
8484 %}
8485
8486 // RShiftL + ConvL2I
8487 instruct convL2I_arShiftL_regL_immI(iRegIdst dst, iRegLsrc src1, immI src2) %{
8488 match(Set dst (ConvL2I (RShiftL src1 src2)));
8489
8490 format %{ "SRADI $dst, $src1, ($src2 & 0x3f) \t// long + l2i" %}
8491 size(4);
8492 ins_encode %{
8493 // TODO: PPC port $archOpcode(ppc64Opcode_sradi);
8494 __ sradi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
8495 %}
8496 ins_pipe(pipe_class_default);
8497 %}
8498
8499 instruct urShiftI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8500 // no match-rule, false predicate
8501 effect(DEF dst, USE src1, USE src2);
8502 predicate(false);
8503
8504 format %{ "SRW $dst, $src1, $src2" %}
8505 size(4);
8506 ins_encode %{
8507 // TODO: PPC port $archOpcode(ppc64Opcode_srw);
8508 __ srw($dst$$Register, $src1$$Register, $src2$$Register);
8509 %}
8510 ins_pipe(pipe_class_default);
8511 %}
8512
8513 // Register Shift Right
8514 instruct urShiftI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8515 match(Set dst (URShiftI src1 src2));
8516 ins_cost(DEFAULT_COST*2);
8517
8518 expand %{
8519 uimmI6 mask %{ 0x3b /* clear 59 bits, keep 5 */ %}
8520 iRegIdst tmpI;
8521 maskI_reg_imm(tmpI, src2, mask);
8522 urShiftI_reg_reg(dst, src1, tmpI);
8523 %}
8524 %}
8525
8526 // Register Shift Right Immediate
8527 instruct urShiftI_reg_imm(iRegIdst dst, iRegIsrc src1, immI src2) %{
8528 match(Set dst (URShiftI src1 src2));
8529
8530 format %{ "SRWI $dst, $src1, ($src2 & 0x1f)" %}
8531 size(4);
8532 ins_encode %{
8533 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm);
8534 __ srwi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x1f);
8535 %}
8536 ins_pipe(pipe_class_default);
8537 %}
8538
8539 instruct urShiftL_regL_regI(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{
8540 // no match-rule, false predicate
8541 effect(DEF dst, USE src1, USE src2);
8542 predicate(false);
8543
8544 format %{ "SRD $dst, $src1, $src2" %}
8545 size(4);
8546 ins_encode %{
8547 // TODO: PPC port $archOpcode(ppc64Opcode_srd);
8548 __ srd($dst$$Register, $src1$$Register, $src2$$Register);
8549 %}
8550 ins_pipe(pipe_class_default);
8551 %}
8552
8553 // Register Shift Right
8554 instruct urShiftL_regL_regI_Ex(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{
8555 match(Set dst (URShiftL src1 src2));
8556 ins_cost(DEFAULT_COST*2);
8557
8558 expand %{
8559 uimmI6 mask %{ 0x3a /* clear 58 bits, keep 6 */ %}
8560 iRegIdst tmpI;
8561 maskI_reg_imm(tmpI, src2, mask);
8562 urShiftL_regL_regI(dst, src1, tmpI);
8563 %}
8564 %}
8565
8566 // Register Shift Right Immediate
8567 instruct urShiftL_regL_immI(iRegLdst dst, iRegLsrc src1, immI src2) %{
8568 match(Set dst (URShiftL src1 src2));
8569
8570 format %{ "SRDI $dst, $src1, ($src2 & 0x3f)" %}
8571 size(4);
8572 ins_encode %{
8573 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
8574 __ srdi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
8575 %}
8576 ins_pipe(pipe_class_default);
8577 %}
8578
8579 // URShiftL + ConvL2I.
8580 instruct convL2I_urShiftL_regL_immI(iRegIdst dst, iRegLsrc src1, immI src2) %{
8581 match(Set dst (ConvL2I (URShiftL src1 src2)));
8582
8583 format %{ "SRDI $dst, $src1, ($src2 & 0x3f) \t// long + l2i" %}
8584 size(4);
8585 ins_encode %{
8586 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
8587 __ srdi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
8588 %}
8589 ins_pipe(pipe_class_default);
8590 %}
8591
8592 // Register Shift Right Immediate with a CastP2X
8593 instruct shrP_convP2X_reg_imm6(iRegLdst dst, iRegP_N2P src1, uimmI6 src2) %{
8594 match(Set dst (URShiftL (CastP2X src1) src2));
8595
8596 format %{ "SRDI $dst, $src1, $src2 \t// Cast ptr $src1 to long and shift" %}
8597 size(4);
8598 ins_encode %{
8599 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
8600 __ srdi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
8601 %}
8602 ins_pipe(pipe_class_default);
8603 %}
8604
8605 instruct sxtI_reg(iRegIdst dst, iRegIsrc src) %{
8606 match(Set dst (ConvL2I (ConvI2L src)));
8607
8608 format %{ "EXTSW $dst, $src \t// int->int" %}
8609 size(4);
8610 ins_encode %{
8611 // TODO: PPC port $archOpcode(ppc64Opcode_extsw);
8612 __ extsw($dst$$Register, $src$$Register);
8613 %}
8614 ins_pipe(pipe_class_default);
8615 %}
8616
8617 //----------Rotate Instructions------------------------------------------------
8618
8619 // Rotate Left by 8-bit immediate
8620 instruct rotlI_reg_immi8(iRegIdst dst, iRegIsrc src, immI8 lshift, immI8 rshift) %{
8621 match(Set dst (OrI (LShiftI src lshift) (URShiftI src rshift)));
8622 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
8623
8624 format %{ "ROTLWI $dst, $src, $lshift" %}
8625 size(4);
8626 ins_encode %{
8627 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm);
8628 __ rotlwi($dst$$Register, $src$$Register, $lshift$$constant);
8629 %}
8630 ins_pipe(pipe_class_default);
8631 %}
8632
8633 // Rotate Right by 8-bit immediate
8634 instruct rotrI_reg_immi8(iRegIdst dst, iRegIsrc src, immI8 rshift, immI8 lshift) %{
8635 match(Set dst (OrI (URShiftI src rshift) (LShiftI src lshift)));
8636 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
8637
8638 format %{ "ROTRWI $dst, $rshift" %}
8639 size(4);
8640 ins_encode %{
8641 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm);
8642 __ rotrwi($dst$$Register, $src$$Register, $rshift$$constant);
8643 %}
8644 ins_pipe(pipe_class_default);
8645 %}
8646
8647 //----------Floating Point Arithmetic Instructions-----------------------------
8648
8649 // Add float single precision
8650 instruct addF_reg_reg(regF dst, regF src1, regF src2) %{
8651 match(Set dst (AddF src1 src2));
8652
8653 format %{ "FADDS $dst, $src1, $src2" %}
8654 size(4);
8655 ins_encode %{
8656 // TODO: PPC port $archOpcode(ppc64Opcode_fadds);
8657 __ fadds($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8658 %}
8659 ins_pipe(pipe_class_default);
8660 %}
8661
8662 // Add float double precision
8663 instruct addD_reg_reg(regD dst, regD src1, regD src2) %{
8664 match(Set dst (AddD src1 src2));
8665
8666 format %{ "FADD $dst, $src1, $src2" %}
8667 size(4);
8668 ins_encode %{
8669 // TODO: PPC port $archOpcode(ppc64Opcode_fadd);
8670 __ fadd($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8671 %}
8672 ins_pipe(pipe_class_default);
8673 %}
8674
8675 // Sub float single precision
8676 instruct subF_reg_reg(regF dst, regF src1, regF src2) %{
8677 match(Set dst (SubF src1 src2));
8678
8679 format %{ "FSUBS $dst, $src1, $src2" %}
8680 size(4);
8681 ins_encode %{
8682 // TODO: PPC port $archOpcode(ppc64Opcode_fsubs);
8683 __ fsubs($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8684 %}
8685 ins_pipe(pipe_class_default);
8686 %}
8687
8688 // Sub float double precision
8689 instruct subD_reg_reg(regD dst, regD src1, regD src2) %{
8690 match(Set dst (SubD src1 src2));
8691 format %{ "FSUB $dst, $src1, $src2" %}
8692 size(4);
8693 ins_encode %{
8694 // TODO: PPC port $archOpcode(ppc64Opcode_fsub);
8695 __ fsub($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8696 %}
8697 ins_pipe(pipe_class_default);
8698 %}
8699
8700 // Mul float single precision
8701 instruct mulF_reg_reg(regF dst, regF src1, regF src2) %{
8702 match(Set dst (MulF src1 src2));
8703 format %{ "FMULS $dst, $src1, $src2" %}
8704 size(4);
8705 ins_encode %{
8706 // TODO: PPC port $archOpcode(ppc64Opcode_fmuls);
8707 __ fmuls($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8708 %}
8709 ins_pipe(pipe_class_default);
8710 %}
8711
8712 // Mul float double precision
8713 instruct mulD_reg_reg(regD dst, regD src1, regD src2) %{
8714 match(Set dst (MulD src1 src2));
8715 format %{ "FMUL $dst, $src1, $src2" %}
8716 size(4);
8717 ins_encode %{
8718 // TODO: PPC port $archOpcode(ppc64Opcode_fmul);
8719 __ fmul($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8720 %}
8721 ins_pipe(pipe_class_default);
8722 %}
8723
8724 // Div float single precision
8725 instruct divF_reg_reg(regF dst, regF src1, regF src2) %{
8726 match(Set dst (DivF src1 src2));
8727 format %{ "FDIVS $dst, $src1, $src2" %}
8728 size(4);
8729 ins_encode %{
8730 // TODO: PPC port $archOpcode(ppc64Opcode_fdivs);
8731 __ fdivs($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8732 %}
8733 ins_pipe(pipe_class_default);
8734 %}
8735
8736 // Div float double precision
8737 instruct divD_reg_reg(regD dst, regD src1, regD src2) %{
8738 match(Set dst (DivD src1 src2));
8739 format %{ "FDIV $dst, $src1, $src2" %}
8740 size(4);
8741 ins_encode %{
8742 // TODO: PPC port $archOpcode(ppc64Opcode_fdiv);
8743 __ fdiv($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8744 %}
8745 ins_pipe(pipe_class_default);
8746 %}
8747
8748 // Absolute float single precision
8749 instruct absF_reg(regF dst, regF src) %{
8750 match(Set dst (AbsF src));
8751 format %{ "FABS $dst, $src \t// float" %}
8752 size(4);
8753 ins_encode %{
8754 // TODO: PPC port $archOpcode(ppc64Opcode_fabs);
8755 __ fabs($dst$$FloatRegister, $src$$FloatRegister);
8756 %}
8757 ins_pipe(pipe_class_default);
8758 %}
8759
8760 // Absolute float double precision
8761 instruct absD_reg(regD dst, regD src) %{
8762 match(Set dst (AbsD src));
8763 format %{ "FABS $dst, $src \t// double" %}
8764 size(4);
8765 ins_encode %{
8766 // TODO: PPC port $archOpcode(ppc64Opcode_fabs);
8767 __ fabs($dst$$FloatRegister, $src$$FloatRegister);
8768 %}
8769 ins_pipe(pipe_class_default);
8770 %}
8771
8772 instruct negF_reg(regF dst, regF src) %{
8773 match(Set dst (NegF src));
8774 format %{ "FNEG $dst, $src \t// float" %}
8775 size(4);
8776 ins_encode %{
8777 // TODO: PPC port $archOpcode(ppc64Opcode_fneg);
8778 __ fneg($dst$$FloatRegister, $src$$FloatRegister);
8779 %}
8780 ins_pipe(pipe_class_default);
8781 %}
8782
8783 instruct negD_reg(regD dst, regD src) %{
8784 match(Set dst (NegD src));
8785 format %{ "FNEG $dst, $src \t// double" %}
8786 size(4);
8787 ins_encode %{
8788 // TODO: PPC port $archOpcode(ppc64Opcode_fneg);
8789 __ fneg($dst$$FloatRegister, $src$$FloatRegister);
8790 %}
8791 ins_pipe(pipe_class_default);
8792 %}
8793
8794 // AbsF + NegF.
8795 instruct negF_absF_reg(regF dst, regF src) %{
8796 match(Set dst (NegF (AbsF src)));
8797 format %{ "FNABS $dst, $src \t// float" %}
8798 size(4);
8799 ins_encode %{
8800 // TODO: PPC port $archOpcode(ppc64Opcode_fnabs);
8801 __ fnabs($dst$$FloatRegister, $src$$FloatRegister);
8802 %}
8803 ins_pipe(pipe_class_default);
8804 %}
8805
8806 // AbsD + NegD.
8807 instruct negD_absD_reg(regD dst, regD src) %{
8808 match(Set dst (NegD (AbsD src)));
8809 format %{ "FNABS $dst, $src \t// double" %}
8810 size(4);
8811 ins_encode %{
8812 // TODO: PPC port $archOpcode(ppc64Opcode_fnabs);
8813 __ fnabs($dst$$FloatRegister, $src$$FloatRegister);
8814 %}
8815 ins_pipe(pipe_class_default);
8816 %}
8817
8818 // VM_Version::has_fsqrt() decides if this node will be used.
8819 // Sqrt float double precision
8820 instruct sqrtD_reg(regD dst, regD src) %{
8821 match(Set dst (SqrtD src));
8822 format %{ "FSQRT $dst, $src" %}
8823 size(4);
8824 ins_encode %{
8825 // TODO: PPC port $archOpcode(ppc64Opcode_fsqrt);
8826 __ fsqrt($dst$$FloatRegister, $src$$FloatRegister);
8827 %}
8828 ins_pipe(pipe_class_default);
8829 %}
8830
8831 // Single-precision sqrt.
8832 instruct sqrtF_reg(regF dst, regF src) %{
8833 match(Set dst (ConvD2F (SqrtD (ConvF2D src))));
8834 predicate(VM_Version::has_fsqrts());
8835 ins_cost(DEFAULT_COST);
8836
8837 format %{ "FSQRTS $dst, $src" %}
8838 size(4);
8839 ins_encode %{
8840 // TODO: PPC port $archOpcode(ppc64Opcode_fsqrts);
8841 __ fsqrts($dst$$FloatRegister, $src$$FloatRegister);
8842 %}
8843 ins_pipe(pipe_class_default);
8844 %}
8845
8846 instruct roundDouble_nop(regD dst) %{
8847 match(Set dst (RoundDouble dst));
8848 ins_cost(0);
8849
8850 format %{ " -- \t// RoundDouble not needed - empty" %}
8851 size(0);
8852 // PPC results are already "rounded" (i.e., normal-format IEEE).
8853 ins_encode( /*empty*/ );
8854 ins_pipe(pipe_class_default);
8855 %}
8856
8857 instruct roundFloat_nop(regF dst) %{
8858 match(Set dst (RoundFloat dst));
8859 ins_cost(0);
8860
8861 format %{ " -- \t// RoundFloat not needed - empty" %}
8862 size(0);
8863 // PPC results are already "rounded" (i.e., normal-format IEEE).
8864 ins_encode( /*empty*/ );
8865 ins_pipe(pipe_class_default);
8866 %}
8867
8868 //----------Logical Instructions-----------------------------------------------
8869
8870 // And Instructions
8871
8872 // Register And
8873 instruct andI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8874 match(Set dst (AndI src1 src2));
8875 format %{ "AND $dst, $src1, $src2" %}
8876 size(4);
8877 ins_encode %{
8878 // TODO: PPC port $archOpcode(ppc64Opcode_and);
8879 __ andr($dst$$Register, $src1$$Register, $src2$$Register);
8880 %}
8881 ins_pipe(pipe_class_default);
8882 %}
8883
8884 // Immediate And
8885 instruct andI_reg_uimm16(iRegIdst dst, iRegIsrc src1, uimmI16 src2, flagsRegCR0 cr0) %{
8886 match(Set dst (AndI src1 src2));
8887 effect(KILL cr0);
8888
8889 format %{ "ANDI $dst, $src1, $src2" %}
8890 size(4);
8891 ins_encode %{
8892 // TODO: PPC port $archOpcode(ppc64Opcode_andi_);
8893 // FIXME: avoid andi_ ?
8894 __ andi_($dst$$Register, $src1$$Register, $src2$$constant);
8895 %}
8896 ins_pipe(pipe_class_default);
8897 %}
8898
8899 // Immediate And where the immediate is a negative power of 2.
8900 instruct andI_reg_immInegpow2(iRegIdst dst, iRegIsrc src1, immInegpow2 src2) %{
8901 match(Set dst (AndI src1 src2));
8902 format %{ "ANDWI $dst, $src1, $src2" %}
8903 size(4);
8904 ins_encode %{
8905 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
8906 __ clrrdi($dst$$Register, $src1$$Register, log2_long((jlong)(julong)(juint)-($src2$$constant)));
8907 %}
8908 ins_pipe(pipe_class_default);
8909 %}
8910
8911 instruct andI_reg_immIpow2minus1(iRegIdst dst, iRegIsrc src1, immIpow2minus1 src2) %{
8912 match(Set dst (AndI src1 src2));
8913 format %{ "ANDWI $dst, $src1, $src2" %}
8914 size(4);
8915 ins_encode %{
8916 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
8917 __ clrldi($dst$$Register, $src1$$Register, 64-log2_long((((jlong) $src2$$constant)+1)));
8918 %}
8919 ins_pipe(pipe_class_default);
8920 %}
8921
8922 instruct andI_reg_immIpowerOf2(iRegIdst dst, iRegIsrc src1, immIpowerOf2 src2) %{
8923 match(Set dst (AndI src1 src2));
8924 predicate(UseRotateAndMaskInstructionsPPC64);
8925 format %{ "ANDWI $dst, $src1, $src2" %}
8926 size(4);
8927 ins_encode %{
8928 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm);
8929 __ rlwinm($dst$$Register, $src1$$Register, 0,
8930 (31-log2_long((jlong) $src2$$constant)) & 0x1f, (31-log2_long((jlong) $src2$$constant)) & 0x1f);
8931 %}
8932 ins_pipe(pipe_class_default);
8933 %}
8934
8935 // Register And Long
8936 instruct andL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
8937 match(Set dst (AndL src1 src2));
8938 ins_cost(DEFAULT_COST);
8939
8940 format %{ "AND $dst, $src1, $src2 \t// long" %}
8941 size(4);
8942 ins_encode %{
8943 // TODO: PPC port $archOpcode(ppc64Opcode_and);
8944 __ andr($dst$$Register, $src1$$Register, $src2$$Register);
8945 %}
8946 ins_pipe(pipe_class_default);
8947 %}
8948
8949 // Immediate And long
8950 instruct andL_reg_uimm16(iRegLdst dst, iRegLsrc src1, uimmL16 src2, flagsRegCR0 cr0) %{
8951 match(Set dst (AndL src1 src2));
8952 effect(KILL cr0);
8953 ins_cost(DEFAULT_COST);
8954
8955 format %{ "ANDI $dst, $src1, $src2 \t// long" %}
8956 size(4);
8957 ins_encode %{
8958 // TODO: PPC port $archOpcode(ppc64Opcode_andi_);
8959 // FIXME: avoid andi_ ?
8960 __ andi_($dst$$Register, $src1$$Register, $src2$$constant);
8961 %}
8962 ins_pipe(pipe_class_default);
8963 %}
8964
8965 // Immediate And Long where the immediate is a negative power of 2.
8966 instruct andL_reg_immLnegpow2(iRegLdst dst, iRegLsrc src1, immLnegpow2 src2) %{
8967 match(Set dst (AndL src1 src2));
8968 format %{ "ANDDI $dst, $src1, $src2" %}
8969 size(4);
8970 ins_encode %{
8971 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
8972 __ clrrdi($dst$$Register, $src1$$Register, log2_long((jlong)-$src2$$constant));
8973 %}
8974 ins_pipe(pipe_class_default);
8975 %}
8976
8977 instruct andL_reg_immLpow2minus1(iRegLdst dst, iRegLsrc src1, immLpow2minus1 src2) %{
8978 match(Set dst (AndL src1 src2));
8979 format %{ "ANDDI $dst, $src1, $src2" %}
8980 size(4);
8981 ins_encode %{
8982 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
8983 __ clrldi($dst$$Register, $src1$$Register, 64-log2_long((((jlong) $src2$$constant)+1)));
8984 %}
8985 ins_pipe(pipe_class_default);
8986 %}
8987
8988 // AndL + ConvL2I.
8989 instruct convL2I_andL_reg_immLpow2minus1(iRegIdst dst, iRegLsrc src1, immLpow2minus1 src2) %{
8990 match(Set dst (ConvL2I (AndL src1 src2)));
8991 ins_cost(DEFAULT_COST);
8992
8993 format %{ "ANDDI $dst, $src1, $src2 \t// long + l2i" %}
8994 size(4);
8995 ins_encode %{
8996 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
8997 __ clrldi($dst$$Register, $src1$$Register, 64-log2_long((((jlong) $src2$$constant)+1)));
8998 %}
8999 ins_pipe(pipe_class_default);
9000 %}
9001
9002 // Or Instructions
9003
9004 // Register Or
9005 instruct orI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
9006 match(Set dst (OrI src1 src2));
9007 format %{ "OR $dst, $src1, $src2" %}
9008 size(4);
9009 ins_encode %{
9010 // TODO: PPC port $archOpcode(ppc64Opcode_or);
9011 __ or_unchecked($dst$$Register, $src1$$Register, $src2$$Register);
9012 %}
9013 ins_pipe(pipe_class_default);
9014 %}
9015
9016 // Expand does not work with above instruct. (??)
9017 instruct orI_reg_reg_2(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
9018 // no match-rule
9019 effect(DEF dst, USE src1, USE src2);
9020 format %{ "OR $dst, $src1, $src2" %}
9021 size(4);
9022 ins_encode %{
9023 // TODO: PPC port $archOpcode(ppc64Opcode_or);
9024 __ or_unchecked($dst$$Register, $src1$$Register, $src2$$Register);
9025 %}
9026 ins_pipe(pipe_class_default);
9027 %}
9028
9029 instruct tree_orI_orI_orI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2, iRegIsrc src3, iRegIsrc src4) %{
9030 match(Set dst (OrI (OrI (OrI src1 src2) src3) src4));
9031 ins_cost(DEFAULT_COST*3);
9032
9033 expand %{
9034 // FIXME: we should do this in the ideal world.
9035 iRegIdst tmp1;
9036 iRegIdst tmp2;
9037 orI_reg_reg(tmp1, src1, src2);
9038 orI_reg_reg_2(tmp2, src3, src4); // Adlc complains about orI_reg_reg.
9039 orI_reg_reg(dst, tmp1, tmp2);
9040 %}
9041 %}
9042
9043 // Immediate Or
9044 instruct orI_reg_uimm16(iRegIdst dst, iRegIsrc src1, uimmI16 src2) %{
9045 match(Set dst (OrI src1 src2));
9046 format %{ "ORI $dst, $src1, $src2" %}
9047 size(4);
9048 ins_encode %{
9049 // TODO: PPC port $archOpcode(ppc64Opcode_ori);
9050 __ ori($dst$$Register, $src1$$Register, ($src2$$constant) & 0xFFFF);
9051 %}
9052 ins_pipe(pipe_class_default);
9053 %}
9054
9055 // Register Or Long
9056 instruct orL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
9057 match(Set dst (OrL src1 src2));
9058 ins_cost(DEFAULT_COST);
9059
9060 size(4);
9061 format %{ "OR $dst, $src1, $src2 \t// long" %}
9062 ins_encode %{
9063 // TODO: PPC port $archOpcode(ppc64Opcode_or);
9064 __ or_unchecked($dst$$Register, $src1$$Register, $src2$$Register);
9065 %}
9066 ins_pipe(pipe_class_default);
9067 %}
9068
9069 // OrL + ConvL2I.
9070 instruct orI_regL_regL(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{
9071 match(Set dst (ConvL2I (OrL src1 src2)));
9072 ins_cost(DEFAULT_COST);
9073
9074 format %{ "OR $dst, $src1, $src2 \t// long + l2i" %}
9075 size(4);
9076 ins_encode %{
9077 // TODO: PPC port $archOpcode(ppc64Opcode_or);
9078 __ or_unchecked($dst$$Register, $src1$$Register, $src2$$Register);
9079 %}
9080 ins_pipe(pipe_class_default);
9081 %}
9082
9083 // Immediate Or long
9084 instruct orL_reg_uimm16(iRegLdst dst, iRegLsrc src1, uimmL16 con) %{
9085 match(Set dst (OrL src1 con));
9086 ins_cost(DEFAULT_COST);
9087
9088 format %{ "ORI $dst, $src1, $con \t// long" %}
9089 size(4);
9090 ins_encode %{
9091 // TODO: PPC port $archOpcode(ppc64Opcode_ori);
9092 __ ori($dst$$Register, $src1$$Register, ($con$$constant) & 0xFFFF);
9093 %}
9094 ins_pipe(pipe_class_default);
9095 %}
9096
9097 // Xor Instructions
9098
9099 // Register Xor
9100 instruct xorI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
9101 match(Set dst (XorI src1 src2));
9102 format %{ "XOR $dst, $src1, $src2" %}
9103 size(4);
9104 ins_encode %{
9105 // TODO: PPC port $archOpcode(ppc64Opcode_xor);
9106 __ xorr($dst$$Register, $src1$$Register, $src2$$Register);
9107 %}
9108 ins_pipe(pipe_class_default);
9109 %}
9110
9111 // Expand does not work with above instruct. (??)
9112 instruct xorI_reg_reg_2(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
9113 // no match-rule
9114 effect(DEF dst, USE src1, USE src2);
9115 format %{ "XOR $dst, $src1, $src2" %}
9116 size(4);
9117 ins_encode %{
9118 // TODO: PPC port $archOpcode(ppc64Opcode_xor);
9119 __ xorr($dst$$Register, $src1$$Register, $src2$$Register);
9120 %}
9121 ins_pipe(pipe_class_default);
9122 %}
9123
9124 instruct tree_xorI_xorI_xorI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2, iRegIsrc src3, iRegIsrc src4) %{
9125 match(Set dst (XorI (XorI (XorI src1 src2) src3) src4));
9126 ins_cost(DEFAULT_COST*3);
9127
9128 expand %{
9129 // FIXME: we should do this in the ideal world.
9130 iRegIdst tmp1;
9131 iRegIdst tmp2;
9132 xorI_reg_reg(tmp1, src1, src2);
9133 xorI_reg_reg_2(tmp2, src3, src4); // Adlc complains about xorI_reg_reg.
9134 xorI_reg_reg(dst, tmp1, tmp2);
9135 %}
9136 %}
9137
9138 // Immediate Xor
9139 instruct xorI_reg_uimm16(iRegIdst dst, iRegIsrc src1, uimmI16 src2) %{
9140 match(Set dst (XorI src1 src2));
9141 format %{ "XORI $dst, $src1, $src2" %}
9142 size(4);
9143 ins_encode %{
9144 // TODO: PPC port $archOpcode(ppc64Opcode_xori);
9145 __ xori($dst$$Register, $src1$$Register, $src2$$constant);
9146 %}
9147 ins_pipe(pipe_class_default);
9148 %}
9149
9150 // Register Xor Long
9151 instruct xorL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
9152 match(Set dst (XorL src1 src2));
9153 ins_cost(DEFAULT_COST);
9154
9155 format %{ "XOR $dst, $src1, $src2 \t// long" %}
9156 size(4);
9157 ins_encode %{
9158 // TODO: PPC port $archOpcode(ppc64Opcode_xor);
9159 __ xorr($dst$$Register, $src1$$Register, $src2$$Register);
9160 %}
9161 ins_pipe(pipe_class_default);
9162 %}
9163
9164 // XorL + ConvL2I.
9165 instruct xorI_regL_regL(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{
9166 match(Set dst (ConvL2I (XorL src1 src2)));
9167 ins_cost(DEFAULT_COST);
9168
9169 format %{ "XOR $dst, $src1, $src2 \t// long + l2i" %}
9170 size(4);
9171 ins_encode %{
9172 // TODO: PPC port $archOpcode(ppc64Opcode_xor);
9173 __ xorr($dst$$Register, $src1$$Register, $src2$$Register);
9174 %}
9175 ins_pipe(pipe_class_default);
9176 %}
9177
9178 // Immediate Xor Long
9179 instruct xorL_reg_uimm16(iRegLdst dst, iRegLsrc src1, uimmL16 src2) %{
9180 match(Set dst (XorL src1 src2));
9181 ins_cost(DEFAULT_COST);
9182
9183 format %{ "XORI $dst, $src1, $src2 \t// long" %}
9184 size(4);
9185 ins_encode %{
9186 // TODO: PPC port $archOpcode(ppc64Opcode_xori);
9187 __ xori($dst$$Register, $src1$$Register, $src2$$constant);
9188 %}
9189 ins_pipe(pipe_class_default);
9190 %}
9191
9192 instruct notI_reg(iRegIdst dst, iRegIsrc src1, immI_minus1 src2) %{
9193 match(Set dst (XorI src1 src2));
9194 ins_cost(DEFAULT_COST);
9195
9196 format %{ "NOT $dst, $src1 ($src2)" %}
9197 size(4);
9198 ins_encode %{
9199 // TODO: PPC port $archOpcode(ppc64Opcode_nor);
9200 __ nor($dst$$Register, $src1$$Register, $src1$$Register);
9201 %}
9202 ins_pipe(pipe_class_default);
9203 %}
9204
9205 instruct notL_reg(iRegLdst dst, iRegLsrc src1, immL_minus1 src2) %{
9206 match(Set dst (XorL src1 src2));
9207 ins_cost(DEFAULT_COST);
9208
9209 format %{ "NOT $dst, $src1 ($src2) \t// long" %}
9210 size(4);
9211 ins_encode %{
9212 // TODO: PPC port $archOpcode(ppc64Opcode_nor);
9213 __ nor($dst$$Register, $src1$$Register, $src1$$Register);
9214 %}
9215 ins_pipe(pipe_class_default);
9216 %}
9217
9218 // And-complement
9219 instruct andcI_reg_reg(iRegIdst dst, iRegIsrc src1, immI_minus1 src2, iRegIsrc src3) %{
9220 match(Set dst (AndI (XorI src1 src2) src3));
9221 ins_cost(DEFAULT_COST);
9222
9223 format %{ "ANDW $dst, xori($src1, $src2), $src3" %}
9224 size(4);
9225 ins_encode( enc_andc(dst, src3, src1) );
9226 ins_pipe(pipe_class_default);
9227 %}
9228
9229 // And-complement
9230 instruct andcL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
9231 // no match-rule, false predicate
9232 effect(DEF dst, USE src1, USE src2);
9233 predicate(false);
9234
9235 format %{ "ANDC $dst, $src1, $src2" %}
9236 size(4);
9237 ins_encode %{
9238 // TODO: PPC port $archOpcode(ppc64Opcode_andc);
9239 __ andc($dst$$Register, $src1$$Register, $src2$$Register);
9240 %}
9241 ins_pipe(pipe_class_default);
9242 %}
9243
9244 //----------Moves between int/long and float/double----------------------------
9245 //
9246 // The following rules move values from int/long registers/stack-locations
9247 // to float/double registers/stack-locations and vice versa, without doing any
9248 // conversions. These rules are used to implement the bit-conversion methods
9249 // of java.lang.Float etc., e.g.
9250 // int floatToIntBits(float value)
9251 // float intBitsToFloat(int bits)
9252 //
9253 // Notes on the implementation on ppc64:
9254 // We only provide rules which move between a register and a stack-location,
9255 // because we always have to go through memory when moving between a float
9256 // register and an integer register.
9257
9258 //---------- Chain stack slots between similar types --------
9259
9260 // These are needed so that the rules below can match.
9261
9262 // Load integer from stack slot
9263 instruct stkI_to_regI(iRegIdst dst, stackSlotI src) %{
9264 match(Set dst src);
9265 ins_cost(MEMORY_REF_COST);
9266
9267 format %{ "LWZ $dst, $src" %}
9268 size(4);
9269 ins_encode( enc_lwz(dst, src) );
9270 ins_pipe(pipe_class_memory);
9271 %}
9272
9273 // Store integer to stack slot
9274 instruct regI_to_stkI(stackSlotI dst, iRegIsrc src) %{
9275 match(Set dst src);
9276 ins_cost(MEMORY_REF_COST);
9277
9278 format %{ "STW $src, $dst \t// stk" %}
9279 size(4);
9280 ins_encode( enc_stw(src, dst) ); // rs=rt
9281 ins_pipe(pipe_class_memory);
9282 %}
9283
9284 // Load long from stack slot
9285 instruct stkL_to_regL(iRegLdst dst, stackSlotL src) %{
9286 match(Set dst src);
9287 ins_cost(MEMORY_REF_COST);
9288
9289 format %{ "LD $dst, $src \t// long" %}
9290 size(4);
9291 ins_encode( enc_ld(dst, src) );
9292 ins_pipe(pipe_class_memory);
9293 %}
9294
9295 // Store long to stack slot
9296 instruct regL_to_stkL(stackSlotL dst, iRegLsrc src) %{
9297 match(Set dst src);
9298 ins_cost(MEMORY_REF_COST);
9299
9300 format %{ "STD $src, $dst \t// long" %}
9301 size(4);
9302 ins_encode( enc_std(src, dst) ); // rs=rt
9303 ins_pipe(pipe_class_memory);
9304 %}
9305
9306 //----------Moves between int and float
9307
9308 // Move float value from float stack-location to integer register.
9309 instruct moveF2I_stack_reg(iRegIdst dst, stackSlotF src) %{
9310 match(Set dst (MoveF2I src));
9311 ins_cost(MEMORY_REF_COST);
9312
9313 format %{ "LWZ $dst, $src \t// MoveF2I" %}
9314 size(4);
9315 ins_encode( enc_lwz(dst, src) );
9316 ins_pipe(pipe_class_memory);
9317 %}
9318
9319 // Move float value from float register to integer stack-location.
9320 instruct moveF2I_reg_stack(stackSlotI dst, regF src) %{
9321 match(Set dst (MoveF2I src));
9322 ins_cost(MEMORY_REF_COST);
9323
9324 format %{ "STFS $src, $dst \t// MoveF2I" %}
9325 size(4);
9326 ins_encode( enc_stfs(src, dst) );
9327 ins_pipe(pipe_class_memory);
9328 %}
9329
9330 // Move integer value from integer stack-location to float register.
9331 instruct moveI2F_stack_reg(regF dst, stackSlotI src) %{
9332 match(Set dst (MoveI2F src));
9333 ins_cost(MEMORY_REF_COST);
9334
9335 format %{ "LFS $dst, $src \t// MoveI2F" %}
9336 size(4);
9337 ins_encode %{
9338 // TODO: PPC port $archOpcode(ppc64Opcode_lfs);
9339 int Idisp = $src$$disp + frame_slots_bias($src$$base, ra_);
9340 __ lfs($dst$$FloatRegister, Idisp, $src$$base$$Register);
9341 %}
9342 ins_pipe(pipe_class_memory);
9343 %}
9344
9345 // Move integer value from integer register to float stack-location.
9346 instruct moveI2F_reg_stack(stackSlotF dst, iRegIsrc src) %{
9347 match(Set dst (MoveI2F src));
9348 ins_cost(MEMORY_REF_COST);
9349
9350 format %{ "STW $src, $dst \t// MoveI2F" %}
9351 size(4);
9352 ins_encode( enc_stw(src, dst) );
9353 ins_pipe(pipe_class_memory);
9354 %}
9355
9356 //----------Moves between long and float
9357
9358 instruct moveF2L_reg_stack(stackSlotL dst, regF src) %{
9359 // no match-rule, false predicate
9360 effect(DEF dst, USE src);
9361 predicate(false);
9362
9363 format %{ "storeD $src, $dst \t// STACK" %}
9364 size(4);
9365 ins_encode( enc_stfd(src, dst) );
9366 ins_pipe(pipe_class_default);
9367 %}
9368
9369 //----------Moves between long and double
9370
9371 // Move double value from double stack-location to long register.
9372 instruct moveD2L_stack_reg(iRegLdst dst, stackSlotD src) %{
9373 match(Set dst (MoveD2L src));
9374 ins_cost(MEMORY_REF_COST);
9375 size(4);
9376 format %{ "LD $dst, $src \t// MoveD2L" %}
9377 ins_encode( enc_ld(dst, src) );
9378 ins_pipe(pipe_class_memory);
9379 %}
9380
9381 // Move double value from double register to long stack-location.
9382 instruct moveD2L_reg_stack(stackSlotL dst, regD src) %{
9383 match(Set dst (MoveD2L src));
9384 effect(DEF dst, USE src);
9385 ins_cost(MEMORY_REF_COST);
9386
9387 format %{ "STFD $src, $dst \t// MoveD2L" %}
9388 size(4);
9389 ins_encode( enc_stfd(src, dst) );
9390 ins_pipe(pipe_class_memory);
9391 %}
9392
9393 // Move long value from long stack-location to double register.
9394 instruct moveL2D_stack_reg(regD dst, stackSlotL src) %{
9395 match(Set dst (MoveL2D src));
9396 ins_cost(MEMORY_REF_COST);
9397
9398 format %{ "LFD $dst, $src \t// MoveL2D" %}
9399 size(4);
9400 ins_encode( enc_lfd(dst, src) );
9401 ins_pipe(pipe_class_memory);
9402 %}
9403
9404 // Move long value from long register to double stack-location.
9405 instruct moveL2D_reg_stack(stackSlotD dst, iRegLsrc src) %{
9406 match(Set dst (MoveL2D src));
9407 ins_cost(MEMORY_REF_COST);
9408
9409 format %{ "STD $src, $dst \t// MoveL2D" %}
9410 size(4);
9411 ins_encode( enc_std(src, dst) );
9412 ins_pipe(pipe_class_memory);
9413 %}
9414
9415 //----------Register Move Instructions-----------------------------------------
9416
9417 // Replicate for Superword
9418
9419 instruct moveReg(iRegLdst dst, iRegIsrc src) %{
9420 predicate(false);
9421 effect(DEF dst, USE src);
9422
9423 format %{ "MR $dst, $src \t// replicate " %}
9424 // variable size, 0 or 4.
9425 ins_encode %{
9426 // TODO: PPC port $archOpcode(ppc64Opcode_or);
9427 __ mr_if_needed($dst$$Register, $src$$Register);
9428 %}
9429 ins_pipe(pipe_class_default);
9430 %}
9431
9432 //----------Cast instructions (Java-level type cast)---------------------------
9433
9434 // Cast Long to Pointer for unsafe natives.
9435 instruct castX2P(iRegPdst dst, iRegLsrc src) %{
9436 match(Set dst (CastX2P src));
9437
9438 format %{ "MR $dst, $src \t// Long->Ptr" %}
9439 // variable size, 0 or 4.
9440 ins_encode %{
9441 // TODO: PPC port $archOpcode(ppc64Opcode_or);
9442 __ mr_if_needed($dst$$Register, $src$$Register);
9443 %}
9444 ins_pipe(pipe_class_default);
9445 %}
9446
9447 // Cast Pointer to Long for unsafe natives.
9448 instruct castP2X(iRegLdst dst, iRegP_N2P src) %{
9449 match(Set dst (CastP2X src));
9450
9451 format %{ "MR $dst, $src \t// Ptr->Long" %}
9452 // variable size, 0 or 4.
9453 ins_encode %{
9454 // TODO: PPC port $archOpcode(ppc64Opcode_or);
9455 __ mr_if_needed($dst$$Register, $src$$Register);
9456 %}
9457 ins_pipe(pipe_class_default);
9458 %}
9459
9460 instruct castPP(iRegPdst dst) %{
9461 match(Set dst (CastPP dst));
9462 format %{ " -- \t// castPP of $dst" %}
9463 size(0);
9464 ins_encode( /*empty*/ );
9465 ins_pipe(pipe_class_default);
9466 %}
9467
9468 instruct castII(iRegIdst dst) %{
9469 match(Set dst (CastII dst));
9470 format %{ " -- \t// castII of $dst" %}
9471 size(0);
9472 ins_encode( /*empty*/ );
9473 ins_pipe(pipe_class_default);
9474 %}
9475
9476 instruct checkCastPP(iRegPdst dst) %{
9477 match(Set dst (CheckCastPP dst));
9478 format %{ " -- \t// checkcastPP of $dst" %}
9479 size(0);
9480 ins_encode( /*empty*/ );
9481 ins_pipe(pipe_class_default);
9482 %}
9483
9484 //----------Convert instructions-----------------------------------------------
9485
9486 // Convert to boolean.
9487
9488 // int_to_bool(src) : { 1 if src != 0
9489 // { 0 else
9490 //
9491 // strategy:
9492 // 1) Count leading zeros of 32 bit-value src,
9493 // this returns 32 (0b10.0000) iff src == 0 and <32 otherwise.
9494 // 2) Shift 5 bits to the right, result is 0b1 iff src == 0, 0b0 otherwise.
9495 // 3) Xori the result to get 0b1 if src != 0 and 0b0 if src == 0.
9496
9497 // convI2Bool
9498 instruct convI2Bool_reg__cntlz_Ex(iRegIdst dst, iRegIsrc src) %{
9499 match(Set dst (Conv2B src));
9500 predicate(UseCountLeadingZerosInstructionsPPC64);
9501 ins_cost(DEFAULT_COST);
9502
9503 expand %{
9504 immI shiftAmount %{ 0x5 %}
9505 uimmI16 mask %{ 0x1 %}
9506 iRegIdst tmp1;
9507 iRegIdst tmp2;
9508 countLeadingZerosI(tmp1, src);
9509 urShiftI_reg_imm(tmp2, tmp1, shiftAmount);
9510 xorI_reg_uimm16(dst, tmp2, mask);
9511 %}
9512 %}
9513
9514 instruct convI2Bool_reg__cmove(iRegIdst dst, iRegIsrc src, flagsReg crx) %{
9515 match(Set dst (Conv2B src));
9516 effect(TEMP crx);
9517 predicate(!UseCountLeadingZerosInstructionsPPC64);
9518 ins_cost(DEFAULT_COST);
9519
9520 format %{ "CMPWI $crx, $src, #0 \t// convI2B"
9521 "LI $dst, #0\n\t"
9522 "BEQ $crx, done\n\t"
9523 "LI $dst, #1\n"
9524 "done:" %}
9525 size(16);
9526 ins_encode( enc_convI2B_regI__cmove(dst, src, crx, 0x0, 0x1) );
9527 ins_pipe(pipe_class_compare);
9528 %}
9529
9530 // ConvI2B + XorI
9531 instruct xorI_convI2Bool_reg_immIvalue1__cntlz_Ex(iRegIdst dst, iRegIsrc src, immI_1 mask) %{
9532 match(Set dst (XorI (Conv2B src) mask));
9533 predicate(UseCountLeadingZerosInstructionsPPC64);
9534 ins_cost(DEFAULT_COST);
9535
9536 expand %{
9537 immI shiftAmount %{ 0x5 %}
9538 iRegIdst tmp1;
9539 countLeadingZerosI(tmp1, src);
9540 urShiftI_reg_imm(dst, tmp1, shiftAmount);
9541 %}
9542 %}
9543
9544 instruct xorI_convI2Bool_reg_immIvalue1__cmove(iRegIdst dst, iRegIsrc src, flagsReg crx, immI_1 mask) %{
9545 match(Set dst (XorI (Conv2B src) mask));
9546 effect(TEMP crx);
9547 predicate(!UseCountLeadingZerosInstructionsPPC64);
9548 ins_cost(DEFAULT_COST);
9549
9550 format %{ "CMPWI $crx, $src, #0 \t// Xor(convI2B($src), $mask)"
9551 "LI $dst, #1\n\t"
9552 "BEQ $crx, done\n\t"
9553 "LI $dst, #0\n"
9554 "done:" %}
9555 size(16);
9556 ins_encode( enc_convI2B_regI__cmove(dst, src, crx, 0x1, 0x0) );
9557 ins_pipe(pipe_class_compare);
9558 %}
9559
9560 // AndI 0b0..010..0 + ConvI2B
9561 instruct convI2Bool_andI_reg_immIpowerOf2(iRegIdst dst, iRegIsrc src, immIpowerOf2 mask) %{
9562 match(Set dst (Conv2B (AndI src mask)));
9563 predicate(UseRotateAndMaskInstructionsPPC64);
9564 ins_cost(DEFAULT_COST);
9565
9566 format %{ "RLWINM $dst, $src, $mask \t// convI2B(AndI($src, $mask))" %}
9567 size(4);
9568 ins_encode %{
9569 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm);
9570 __ rlwinm($dst$$Register, $src$$Register, (32-log2_long((jlong)$mask$$constant)) & 0x1f, 31, 31);
9571 %}
9572 ins_pipe(pipe_class_default);
9573 %}
9574
9575 // Convert pointer to boolean.
9576 //
9577 // ptr_to_bool(src) : { 1 if src != 0
9578 // { 0 else
9579 //
9580 // strategy:
9581 // 1) Count leading zeros of 64 bit-value src,
9582 // this returns 64 (0b100.0000) iff src == 0 and <64 otherwise.
9583 // 2) Shift 6 bits to the right, result is 0b1 iff src == 0, 0b0 otherwise.
9584 // 3) Xori the result to get 0b1 if src != 0 and 0b0 if src == 0.
9585
9586 // ConvP2B
9587 instruct convP2Bool_reg__cntlz_Ex(iRegIdst dst, iRegP_N2P src) %{
9588 match(Set dst (Conv2B src));
9589 predicate(UseCountLeadingZerosInstructionsPPC64);
9590 ins_cost(DEFAULT_COST);
9591
9592 expand %{
9593 immI shiftAmount %{ 0x6 %}
9594 uimmI16 mask %{ 0x1 %}
9595 iRegIdst tmp1;
9596 iRegIdst tmp2;
9597 countLeadingZerosP(tmp1, src);
9598 urShiftI_reg_imm(tmp2, tmp1, shiftAmount);
9599 xorI_reg_uimm16(dst, tmp2, mask);
9600 %}
9601 %}
9602
9603 instruct convP2Bool_reg__cmove(iRegIdst dst, iRegP_N2P src, flagsReg crx) %{
9604 match(Set dst (Conv2B src));
9605 effect(TEMP crx);
9606 predicate(!UseCountLeadingZerosInstructionsPPC64);
9607 ins_cost(DEFAULT_COST);
9608
9609 format %{ "CMPDI $crx, $src, #0 \t// convP2B"
9610 "LI $dst, #0\n\t"
9611 "BEQ $crx, done\n\t"
9612 "LI $dst, #1\n"
9613 "done:" %}
9614 size(16);
9615 ins_encode( enc_convP2B_regP__cmove(dst, src, crx, 0x0, 0x1) );
9616 ins_pipe(pipe_class_compare);
9617 %}
9618
9619 // ConvP2B + XorI
9620 instruct xorI_convP2Bool_reg__cntlz_Ex(iRegIdst dst, iRegP_N2P src, immI_1 mask) %{
9621 match(Set dst (XorI (Conv2B src) mask));
9622 predicate(UseCountLeadingZerosInstructionsPPC64);
9623 ins_cost(DEFAULT_COST);
9624
9625 expand %{
9626 immI shiftAmount %{ 0x6 %}
9627 iRegIdst tmp1;
9628 countLeadingZerosP(tmp1, src);
9629 urShiftI_reg_imm(dst, tmp1, shiftAmount);
9630 %}
9631 %}
9632
9633 instruct xorI_convP2Bool_reg_immIvalue1__cmove(iRegIdst dst, iRegP_N2P src, flagsReg crx, immI_1 mask) %{
9634 match(Set dst (XorI (Conv2B src) mask));
9635 effect(TEMP crx);
9636 predicate(!UseCountLeadingZerosInstructionsPPC64);
9637 ins_cost(DEFAULT_COST);
9638
9639 format %{ "CMPDI $crx, $src, #0 \t// XorI(convP2B($src), $mask)"
9640 "LI $dst, #1\n\t"
9641 "BEQ $crx, done\n\t"
9642 "LI $dst, #0\n"
9643 "done:" %}
9644 size(16);
9645 ins_encode( enc_convP2B_regP__cmove(dst, src, crx, 0x1, 0x0) );
9646 ins_pipe(pipe_class_compare);
9647 %}
9648
9649 // if src1 < src2, return -1 else return 0
9650 instruct cmpLTMask_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
9651 match(Set dst (CmpLTMask src1 src2));
9652 ins_cost(DEFAULT_COST*4);
9653
9654 expand %{
9655 iRegLdst src1s;
9656 iRegLdst src2s;
9657 iRegLdst diff;
9658 convI2L_reg(src1s, src1); // Ensure proper sign extension.
9659 convI2L_reg(src2s, src2); // Ensure proper sign extension.
9660 subL_reg_reg(diff, src1s, src2s);
9661 // Need to consider >=33 bit result, therefore we need signmaskL.
9662 signmask64I_regL(dst, diff);
9663 %}
9664 %}
9665
9666 instruct cmpLTMask_reg_immI0(iRegIdst dst, iRegIsrc src1, immI_0 src2) %{
9667 match(Set dst (CmpLTMask src1 src2)); // if src1 < src2, return -1 else return 0
9668 format %{ "SRAWI $dst, $src1, $src2 \t// CmpLTMask" %}
9669 size(4);
9670 ins_encode %{
9671 // TODO: PPC port $archOpcode(ppc64Opcode_srawi);
9672 __ srawi($dst$$Register, $src1$$Register, 0x1f);
9673 %}
9674 ins_pipe(pipe_class_default);
9675 %}
9676
9677 //----------Arithmetic Conversion Instructions---------------------------------
9678
9679 // Convert to Byte -- nop
9680 // Convert to Short -- nop
9681
9682 // Convert to Int
9683
9684 instruct convB2I_reg(iRegIdst dst, iRegIsrc src, immI_24 amount) %{
9685 match(Set dst (RShiftI (LShiftI src amount) amount));
9686 format %{ "EXTSB $dst, $src \t// byte->int" %}
9687 size(4);
9688 ins_encode %{
9689 // TODO: PPC port $archOpcode(ppc64Opcode_extsb);
9690 __ extsb($dst$$Register, $src$$Register);
9691 %}
9692 ins_pipe(pipe_class_default);
9693 %}
9694
9695 // LShiftI 16 + RShiftI 16 converts short to int.
9696 instruct convS2I_reg(iRegIdst dst, iRegIsrc src, immI_16 amount) %{
9697 match(Set dst (RShiftI (LShiftI src amount) amount));
9698 format %{ "EXTSH $dst, $src \t// short->int" %}
9699 size(4);
9700 ins_encode %{
9701 // TODO: PPC port $archOpcode(ppc64Opcode_extsh);
9702 __ extsh($dst$$Register, $src$$Register);
9703 %}
9704 ins_pipe(pipe_class_default);
9705 %}
9706
9707 // ConvL2I + ConvI2L: Sign extend int in long register.
9708 instruct sxtI_L2L_reg(iRegLdst dst, iRegLsrc src) %{
9709 match(Set dst (ConvI2L (ConvL2I src)));
9710
9711 format %{ "EXTSW $dst, $src \t// long->long" %}
9712 size(4);
9713 ins_encode %{
9714 // TODO: PPC port $archOpcode(ppc64Opcode_extsw);
9715 __ extsw($dst$$Register, $src$$Register);
9716 %}
9717 ins_pipe(pipe_class_default);
9718 %}
9719
9720 instruct convL2I_reg(iRegIdst dst, iRegLsrc src) %{
9721 match(Set dst (ConvL2I src));
9722 format %{ "MR $dst, $src \t// long->int" %}
9723 // variable size, 0 or 4
9724 ins_encode %{
9725 // TODO: PPC port $archOpcode(ppc64Opcode_or);
9726 __ mr_if_needed($dst$$Register, $src$$Register);
9727 %}
9728 ins_pipe(pipe_class_default);
9729 %}
9730
9731 instruct convD2IRaw_regD(regD dst, regD src) %{
9732 // no match-rule, false predicate
9733 effect(DEF dst, USE src);
9734 predicate(false);
9735
9736 format %{ "FCTIWZ $dst, $src \t// convD2I, $src != NaN" %}
9737 size(4);
9738 ins_encode %{
9739 // TODO: PPC port $archOpcode(ppc64Opcode_fctiwz);;
9740 __ fctiwz($dst$$FloatRegister, $src$$FloatRegister);
9741 %}
9742 ins_pipe(pipe_class_default);
9743 %}
9744
9745 instruct cmovI_bso_stackSlotL(iRegIdst dst, flagsReg crx, stackSlotL src) %{
9746 // no match-rule, false predicate
9747 effect(DEF dst, USE crx, USE src);
9748 predicate(false);
9749
9750 ins_variable_size_depending_on_alignment(true);
9751
9752 format %{ "cmovI $crx, $dst, $src" %}
9753 // Worst case is branch + move + stop, no stop without scheduler.
9754 size(false /* TODO: PPC PORT(InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8);
9755 ins_encode( enc_cmove_bso_stackSlotL(dst, crx, src) );
9756 ins_pipe(pipe_class_default);
9757 %}
9758
9759 instruct cmovI_bso_stackSlotL_conLvalue0_Ex(iRegIdst dst, flagsReg crx, stackSlotL mem) %{
9760 // no match-rule, false predicate
9761 effect(DEF dst, USE crx, USE mem);
9762 predicate(false);
9763
9764 format %{ "CmovI $dst, $crx, $mem \t// postalloc expanded" %}
9765 postalloc_expand %{
9766 //
9767 // replaces
9768 //
9769 // region dst crx mem
9770 // \ | | /
9771 // dst=cmovI_bso_stackSlotL_conLvalue0
9772 //
9773 // with
9774 //
9775 // region dst
9776 // \ /
9777 // dst=loadConI16(0)
9778 // |
9779 // ^ region dst crx mem
9780 // | \ | | /
9781 // dst=cmovI_bso_stackSlotL
9782 //
9783
9784 // Create new nodes.
9785 MachNode *m1 = new (C) loadConI16Node();
9786 MachNode *m2 = new (C) cmovI_bso_stackSlotLNode();
9787
9788 // inputs for new nodes
9789 m1->add_req(n_region);
9790 m2->add_req(n_region, n_crx, n_mem);
9791
9792 // precedences for new nodes
9793 m2->add_prec(m1);
9794
9795 // operands for new nodes
9796 m1->_opnds[0] = op_dst;
9797 m1->_opnds[1] = new (C) immI16Oper(0);
9798
9799 m2->_opnds[0] = op_dst;
9800 m2->_opnds[1] = op_crx;
9801 m2->_opnds[2] = op_mem;
9802
9803 // registers for new nodes
9804 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
9805 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
9806
9807 // Insert new nodes.
9808 nodes->push(m1);
9809 nodes->push(m2);
9810 %}
9811 %}
9812
9813 // Double to Int conversion, NaN is mapped to 0.
9814 instruct convD2I_reg_ExEx(iRegIdst dst, regD src) %{
9815 match(Set dst (ConvD2I src));
9816 ins_cost(DEFAULT_COST);
9817
9818 expand %{
9819 regD tmpD;
9820 stackSlotL tmpS;
9821 flagsReg crx;
9822 cmpDUnordered_reg_reg(crx, src, src); // Check whether src is NaN.
9823 convD2IRaw_regD(tmpD, src); // Convert float to int (speculated).
9824 moveD2L_reg_stack(tmpS, tmpD); // Store float to stack (speculated).
9825 cmovI_bso_stackSlotL_conLvalue0_Ex(dst, crx, tmpS); // Cmove based on NaN check.
9826 %}
9827 %}
9828
9829 instruct convF2IRaw_regF(regF dst, regF src) %{
9830 // no match-rule, false predicate
9831 effect(DEF dst, USE src);
9832 predicate(false);
9833
9834 format %{ "FCTIWZ $dst, $src \t// convF2I, $src != NaN" %}
9835 size(4);
9836 ins_encode %{
9837 // TODO: PPC port $archOpcode(ppc64Opcode_fctiwz);
9838 __ fctiwz($dst$$FloatRegister, $src$$FloatRegister);
9839 %}
9840 ins_pipe(pipe_class_default);
9841 %}
9842
9843 // Float to Int conversion, NaN is mapped to 0.
9844 instruct convF2I_regF_ExEx(iRegIdst dst, regF src) %{
9845 match(Set dst (ConvF2I src));
9846 ins_cost(DEFAULT_COST);
9847
9848 expand %{
9849 regF tmpF;
9850 stackSlotL tmpS;
9851 flagsReg crx;
9852 cmpFUnordered_reg_reg(crx, src, src); // Check whether src is NaN.
9853 convF2IRaw_regF(tmpF, src); // Convert float to int (speculated).
9854 moveF2L_reg_stack(tmpS, tmpF); // Store float to stack (speculated).
9855 cmovI_bso_stackSlotL_conLvalue0_Ex(dst, crx, tmpS); // Cmove based on NaN check.
9856 %}
9857 %}
9858
9859 // Convert to Long
9860
9861 instruct convI2L_reg(iRegLdst dst, iRegIsrc src) %{
9862 match(Set dst (ConvI2L src));
9863 format %{ "EXTSW $dst, $src \t// int->long" %}
9864 size(4);
9865 ins_encode %{
9866 // TODO: PPC port $archOpcode(ppc64Opcode_extsw);
9867 __ extsw($dst$$Register, $src$$Register);
9868 %}
9869 ins_pipe(pipe_class_default);
9870 %}
9871
9872 // Zero-extend: convert unsigned int to long (convUI2L).
9873 instruct zeroExtendL_regI(iRegLdst dst, iRegIsrc src, immL_32bits mask) %{
9874 match(Set dst (AndL (ConvI2L src) mask));
9875 ins_cost(DEFAULT_COST);
9876
9877 format %{ "CLRLDI $dst, $src, #32 \t// zero-extend int to long" %}
9878 size(4);
9879 ins_encode %{
9880 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
9881 __ clrldi($dst$$Register, $src$$Register, 32);
9882 %}
9883 ins_pipe(pipe_class_default);
9884 %}
9885
9886 // Zero-extend: convert unsigned int to long in long register.
9887 instruct zeroExtendL_regL(iRegLdst dst, iRegLsrc src, immL_32bits mask) %{
9888 match(Set dst (AndL src mask));
9889 ins_cost(DEFAULT_COST);
9890
9891 format %{ "CLRLDI $dst, $src, #32 \t// zero-extend int to long" %}
9892 size(4);
9893 ins_encode %{
9894 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
9895 __ clrldi($dst$$Register, $src$$Register, 32);
9896 %}
9897 ins_pipe(pipe_class_default);
9898 %}
9899
9900 instruct convF2LRaw_regF(regF dst, regF src) %{
9901 // no match-rule, false predicate
9902 effect(DEF dst, USE src);
9903 predicate(false);
9904
9905 format %{ "FCTIDZ $dst, $src \t// convF2L, $src != NaN" %}
9906 size(4);
9907 ins_encode %{
9908 // TODO: PPC port $archOpcode(ppc64Opcode_fctiwz);
9909 __ fctidz($dst$$FloatRegister, $src$$FloatRegister);
9910 %}
9911 ins_pipe(pipe_class_default);
9912 %}
9913
9914 instruct cmovL_bso_stackSlotL(iRegLdst dst, flagsReg crx, stackSlotL src) %{
9915 // no match-rule, false predicate
9916 effect(DEF dst, USE crx, USE src);
9917 predicate(false);
9918
9919 ins_variable_size_depending_on_alignment(true);
9920
9921 format %{ "cmovL $crx, $dst, $src" %}
9922 // Worst case is branch + move + stop, no stop without scheduler.
9923 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
9924 ins_encode( enc_cmove_bso_stackSlotL(dst, crx, src) );
9925 ins_pipe(pipe_class_default);
9926 %}
9927
9928 instruct cmovL_bso_stackSlotL_conLvalue0_Ex(iRegLdst dst, flagsReg crx, stackSlotL mem) %{
9929 // no match-rule, false predicate
9930 effect(DEF dst, USE crx, USE mem);
9931 predicate(false);
9932
9933 format %{ "CmovL $dst, $crx, $mem \t// postalloc expanded" %}
9934 postalloc_expand %{
9935 //
9936 // replaces
9937 //
9938 // region dst crx mem
9939 // \ | | /
9940 // dst=cmovL_bso_stackSlotL_conLvalue0
9941 //
9942 // with
9943 //
9944 // region dst
9945 // \ /
9946 // dst=loadConL16(0)
9947 // |
9948 // ^ region dst crx mem
9949 // | \ | | /
9950 // dst=cmovL_bso_stackSlotL
9951 //
9952
9953 // Create new nodes.
9954 MachNode *m1 = new (C) loadConL16Node();
9955 MachNode *m2 = new (C) cmovL_bso_stackSlotLNode();
9956
9957 // inputs for new nodes
9958 m1->add_req(n_region);
9959 m2->add_req(n_region, n_crx, n_mem);
9960 m2->add_prec(m1);
9961
9962 // operands for new nodes
9963 m1->_opnds[0] = op_dst;
9964 m1->_opnds[1] = new (C) immL16Oper(0);
9965 m2->_opnds[0] = op_dst;
9966 m2->_opnds[1] = op_crx;
9967 m2->_opnds[2] = op_mem;
9968
9969 // registers for new nodes
9970 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
9971 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
9972
9973 // Insert new nodes.
9974 nodes->push(m1);
9975 nodes->push(m2);
9976 %}
9977 %}
9978
9979 // Float to Long conversion, NaN is mapped to 0.
9980 instruct convF2L_reg_ExEx(iRegLdst dst, regF src) %{
9981 match(Set dst (ConvF2L src));
9982 ins_cost(DEFAULT_COST);
9983
9984 expand %{
9985 regF tmpF;
9986 stackSlotL tmpS;
9987 flagsReg crx;
9988 cmpFUnordered_reg_reg(crx, src, src); // Check whether src is NaN.
9989 convF2LRaw_regF(tmpF, src); // Convert float to long (speculated).
9990 moveF2L_reg_stack(tmpS, tmpF); // Store float to stack (speculated).
9991 cmovL_bso_stackSlotL_conLvalue0_Ex(dst, crx, tmpS); // Cmove based on NaN check.
9992 %}
9993 %}
9994
9995 instruct convD2LRaw_regD(regD dst, regD src) %{
9996 // no match-rule, false predicate
9997 effect(DEF dst, USE src);
9998 predicate(false);
9999
10000 format %{ "FCTIDZ $dst, $src \t// convD2L $src != NaN" %}
10001 size(4);
10002 ins_encode %{
10003 // TODO: PPC port $archOpcode(ppc64Opcode_fctiwz);
10004 __ fctidz($dst$$FloatRegister, $src$$FloatRegister);
10005 %}
10006 ins_pipe(pipe_class_default);
10007 %}
10008
10009 // Double to Long conversion, NaN is mapped to 0.
10010 instruct convD2L_reg_ExEx(iRegLdst dst, regD src) %{
10011 match(Set dst (ConvD2L src));
10012 ins_cost(DEFAULT_COST);
10013
10014 expand %{
10015 regD tmpD;
10016 stackSlotL tmpS;
10017 flagsReg crx;
10018 cmpDUnordered_reg_reg(crx, src, src); // Check whether src is NaN.
10019 convD2LRaw_regD(tmpD, src); // Convert float to long (speculated).
10020 moveD2L_reg_stack(tmpS, tmpD); // Store float to stack (speculated).
10021 cmovL_bso_stackSlotL_conLvalue0_Ex(dst, crx, tmpS); // Cmove based on NaN check.
10022 %}
10023 %}
10024
10025 // Convert to Float
10026
10027 // Placed here as needed in expand.
10028 instruct convL2DRaw_regD(regD dst, regD src) %{
10029 // no match-rule, false predicate
10030 effect(DEF dst, USE src);
10031 predicate(false);
10032
10033 format %{ "FCFID $dst, $src \t// convL2D" %}
10034 size(4);
10035 ins_encode %{
10036 // TODO: PPC port $archOpcode(ppc64Opcode_fcfid);
10037 __ fcfid($dst$$FloatRegister, $src$$FloatRegister);
10038 %}
10039 ins_pipe(pipe_class_default);
10040 %}
10041
10042 // Placed here as needed in expand.
10043 instruct convD2F_reg(regF dst, regD src) %{
10044 match(Set dst (ConvD2F src));
10045 format %{ "FRSP $dst, $src \t// convD2F" %}
10046 size(4);
10047 ins_encode %{
10048 // TODO: PPC port $archOpcode(ppc64Opcode_frsp);
10049 __ frsp($dst$$FloatRegister, $src$$FloatRegister);
10050 %}
10051 ins_pipe(pipe_class_default);
10052 %}
10053
10054 // Integer to Float conversion.
10055 instruct convI2F_ireg_Ex(regF dst, iRegIsrc src) %{
10056 match(Set dst (ConvI2F src));
10057 predicate(!VM_Version::has_fcfids());
10058 ins_cost(DEFAULT_COST);
10059
10060 expand %{
10061 iRegLdst tmpL;
10062 stackSlotL tmpS;
10063 regD tmpD;
10064 regD tmpD2;
10065 convI2L_reg(tmpL, src); // Sign-extension int to long.
10066 regL_to_stkL(tmpS, tmpL); // Store long to stack.
10067 moveL2D_stack_reg(tmpD, tmpS); // Load long into double register.
10068 convL2DRaw_regD(tmpD2, tmpD); // Convert to double.
10069 convD2F_reg(dst, tmpD2); // Convert double to float.
10070 %}
10071 %}
10072
10073 instruct convL2FRaw_regF(regF dst, regD src) %{
10074 // no match-rule, false predicate
10075 effect(DEF dst, USE src);
10076 predicate(false);
10077
10078 format %{ "FCFIDS $dst, $src \t// convL2F" %}
10079 size(4);
10080 ins_encode %{
10081 // TODO: PPC port $archOpcode(ppc64Opcode_fcfid);
10082 __ fcfids($dst$$FloatRegister, $src$$FloatRegister);
10083 %}
10084 ins_pipe(pipe_class_default);
10085 %}
10086
10087 // Integer to Float conversion. Special version for Power7.
10088 instruct convI2F_ireg_fcfids_Ex(regF dst, iRegIsrc src) %{
10089 match(Set dst (ConvI2F src));
10090 predicate(VM_Version::has_fcfids());
10091 ins_cost(DEFAULT_COST);
10092
10093 expand %{
10094 iRegLdst tmpL;
10095 stackSlotL tmpS;
10096 regD tmpD;
10097 convI2L_reg(tmpL, src); // Sign-extension int to long.
10098 regL_to_stkL(tmpS, tmpL); // Store long to stack.
10099 moveL2D_stack_reg(tmpD, tmpS); // Load long into double register.
10100 convL2FRaw_regF(dst, tmpD); // Convert to float.
10101 %}
10102 %}
10103
10104 // L2F to avoid runtime call.
10105 instruct convL2F_ireg_fcfids_Ex(regF dst, iRegLsrc src) %{
10106 match(Set dst (ConvL2F src));
10107 predicate(VM_Version::has_fcfids());
10108 ins_cost(DEFAULT_COST);
10109
10110 expand %{
10111 stackSlotL tmpS;
10112 regD tmpD;
10113 regL_to_stkL(tmpS, src); // Store long to stack.
10114 moveL2D_stack_reg(tmpD, tmpS); // Load long into double register.
10115 convL2FRaw_regF(dst, tmpD); // Convert to float.
10116 %}
10117 %}
10118
10119 // Moved up as used in expand.
10120 //instruct convD2F_reg(regF dst, regD src) %{%}
10121
10122 // Convert to Double
10123
10124 // Integer to Double conversion.
10125 instruct convI2D_reg_Ex(regD dst, iRegIsrc src) %{
10126 match(Set dst (ConvI2D src));
10127 ins_cost(DEFAULT_COST);
10128
10129 expand %{
10130 iRegLdst tmpL;
10131 stackSlotL tmpS;
10132 regD tmpD;
10133 convI2L_reg(tmpL, src); // Sign-extension int to long.
10134 regL_to_stkL(tmpS, tmpL); // Store long to stack.
10135 moveL2D_stack_reg(tmpD, tmpS); // Load long into double register.
10136 convL2DRaw_regD(dst, tmpD); // Convert to double.
10137 %}
10138 %}
10139
10140 // Long to Double conversion
10141 instruct convL2D_reg_Ex(regD dst, stackSlotL src) %{
10142 match(Set dst (ConvL2D src));
10143 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
10144
10145 expand %{
10146 regD tmpD;
10147 moveL2D_stack_reg(tmpD, src);
10148 convL2DRaw_regD(dst, tmpD);
10149 %}
10150 %}
10151
10152 instruct convF2D_reg(regD dst, regF src) %{
10153 match(Set dst (ConvF2D src));
10154 format %{ "FMR $dst, $src \t// float->double" %}
10155 // variable size, 0 or 4
10156 ins_encode %{
10157 // TODO: PPC port $archOpcode(ppc64Opcode_fmr);
10158 __ fmr_if_needed($dst$$FloatRegister, $src$$FloatRegister);
10159 %}
10160 ins_pipe(pipe_class_default);
10161 %}
10162
10163 //----------Control Flow Instructions------------------------------------------
10164 // Compare Instructions
10165
10166 // Compare Integers
10167 instruct cmpI_reg_reg(flagsReg crx, iRegIsrc src1, iRegIsrc src2) %{
10168 match(Set crx (CmpI src1 src2));
10169 size(4);
10170 format %{ "CMPW $crx, $src1, $src2" %}
10171 ins_encode %{
10172 // TODO: PPC port $archOpcode(ppc64Opcode_cmp);
10173 __ cmpw($crx$$CondRegister, $src1$$Register, $src2$$Register);
10174 %}
10175 ins_pipe(pipe_class_compare);
10176 %}
10177
10178 instruct cmpI_reg_imm16(flagsReg crx, iRegIsrc src1, immI16 src2) %{
10179 match(Set crx (CmpI src1 src2));
10180 format %{ "CMPWI $crx, $src1, $src2" %}
10181 size(4);
10182 ins_encode %{
10183 // TODO: PPC port $archOpcode(ppc64Opcode_cmpi);
10184 __ cmpwi($crx$$CondRegister, $src1$$Register, $src2$$constant);
10185 %}
10186 ins_pipe(pipe_class_compare);
10187 %}
10188
10189 // (src1 & src2) == 0?
10190 instruct testI_reg_imm(flagsRegCR0 cr0, iRegIsrc src1, uimmI16 src2, immI_0 zero) %{
10191 match(Set cr0 (CmpI (AndI src1 src2) zero));
10192 // r0 is killed
10193 format %{ "ANDI R0, $src1, $src2 \t// BTST int" %}
10194 size(4);
10195 ins_encode %{
10196 // TODO: PPC port $archOpcode(ppc64Opcode_andi_);
10197 // FIXME: avoid andi_ ?
10198 __ andi_(R0, $src1$$Register, $src2$$constant);
10199 %}
10200 ins_pipe(pipe_class_compare);
10201 %}
10202
10203 instruct cmpL_reg_reg(flagsReg crx, iRegLsrc src1, iRegLsrc src2) %{
10204 match(Set crx (CmpL src1 src2));
10205 format %{ "CMPD $crx, $src1, $src2" %}
10206 size(4);
10207 ins_encode %{
10208 // TODO: PPC port $archOpcode(ppc64Opcode_cmp);
10209 __ cmpd($crx$$CondRegister, $src1$$Register, $src2$$Register);
10210 %}
10211 ins_pipe(pipe_class_compare);
10212 %}
10213
10214 instruct cmpL_reg_imm16(flagsReg crx, iRegLsrc src1, immL16 src2) %{
10215 match(Set crx (CmpL src1 src2));
10216 format %{ "CMPDI $crx, $src1, $src2" %}
10217 size(4);
10218 ins_encode %{
10219 // TODO: PPC port $archOpcode(ppc64Opcode_cmpi);
10220 __ cmpdi($crx$$CondRegister, $src1$$Register, $src2$$constant);
10221 %}
10222 ins_pipe(pipe_class_compare);
10223 %}
10224
10225 instruct testL_reg_reg(flagsRegCR0 cr0, iRegLsrc src1, iRegLsrc src2, immL_0 zero) %{
10226 match(Set cr0 (CmpL (AndL src1 src2) zero));
10227 // r0 is killed
10228 format %{ "AND R0, $src1, $src2 \t// BTST long" %}
10229 size(4);
10230 ins_encode %{
10231 // TODO: PPC port $archOpcode(ppc64Opcode_and_);
10232 __ and_(R0, $src1$$Register, $src2$$Register);
10233 %}
10234 ins_pipe(pipe_class_compare);
10235 %}
10236
10237 instruct testL_reg_imm(flagsRegCR0 cr0, iRegLsrc src1, uimmL16 src2, immL_0 zero) %{
10238 match(Set cr0 (CmpL (AndL src1 src2) zero));
10239 // r0 is killed
10240 format %{ "ANDI R0, $src1, $src2 \t// BTST long" %}
10241 size(4);
10242 ins_encode %{
10243 // TODO: PPC port $archOpcode(ppc64Opcode_andi_);
10244 // FIXME: avoid andi_ ?
10245 __ andi_(R0, $src1$$Register, $src2$$constant);
10246 %}
10247 ins_pipe(pipe_class_compare);
10248 %}
10249
10250 instruct cmovI_conIvalueMinus1_conIvalue1(iRegIdst dst, flagsReg crx) %{
10251 // no match-rule, false predicate
10252 effect(DEF dst, USE crx);
10253 predicate(false);
10254
10255 ins_variable_size_depending_on_alignment(true);
10256
10257 format %{ "cmovI $crx, $dst, -1, 0, +1" %}
10258 // Worst case is branch + move + branch + move + stop, no stop without scheduler.
10259 size(false /* TODO: PPC PORTInsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 20 : 16);
10260 ins_encode %{
10261 // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
10262 Label done;
10263 // li(Rdst, 0); // equal -> 0
10264 __ beq($crx$$CondRegister, done);
10265 __ li($dst$$Register, 1); // greater -> +1
10266 __ bgt($crx$$CondRegister, done);
10267 __ li($dst$$Register, -1); // unordered or less -> -1
10268 // TODO: PPC port__ endgroup_if_needed(_size == 20);
10269 __ bind(done);
10270 %}
10271 ins_pipe(pipe_class_compare);
10272 %}
10273
10274 instruct cmovI_conIvalueMinus1_conIvalue0_conIvalue1_Ex(iRegIdst dst, flagsReg crx) %{
10275 // no match-rule, false predicate
10276 effect(DEF dst, USE crx);
10277 predicate(false);
10278
10279 format %{ "CmovI $crx, $dst, -1, 0, +1 \t// postalloc expanded" %}
10280 postalloc_expand %{
10281 //
10282 // replaces
10283 //
10284 // region crx
10285 // \ |
10286 // dst=cmovI_conIvalueMinus1_conIvalue0_conIvalue1
10287 //
10288 // with
10289 //
10290 // region
10291 // \
10292 // dst=loadConI16(0)
10293 // |
10294 // ^ region crx
10295 // | \ |
10296 // dst=cmovI_conIvalueMinus1_conIvalue1
10297 //
10298
10299 // Create new nodes.
10300 MachNode *m1 = new (C) loadConI16Node();
10301 MachNode *m2 = new (C) cmovI_conIvalueMinus1_conIvalue1Node();
10302
10303 // inputs for new nodes
10304 m1->add_req(n_region);
10305 m2->add_req(n_region, n_crx);
10306 m2->add_prec(m1);
10307
10308 // operands for new nodes
10309 m1->_opnds[0] = op_dst;
10310 m1->_opnds[1] = new (C) immI16Oper(0);
10311 m2->_opnds[0] = op_dst;
10312 m2->_opnds[1] = op_crx;
10313
10314 // registers for new nodes
10315 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
10316 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
10317
10318 // Insert new nodes.
10319 nodes->push(m1);
10320 nodes->push(m2);
10321 %}
10322 %}
10323
10324 // Manifest a CmpL3 result in an integer register. Very painful.
10325 // This is the test to avoid.
10326 // (src1 < src2) ? -1 : ((src1 > src2) ? 1 : 0)
10327 instruct cmpL3_reg_reg_ExEx(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{
10328 match(Set dst (CmpL3 src1 src2));
10329 ins_cost(DEFAULT_COST*5+BRANCH_COST);
10330
10331 expand %{
10332 flagsReg tmp1;
10333 cmpL_reg_reg(tmp1, src1, src2);
10334 cmovI_conIvalueMinus1_conIvalue0_conIvalue1_Ex(dst, tmp1);
10335 %}
10336 %}
10337
10338 // Implicit range checks.
10339 // A range check in the ideal world has one of the following shapes:
10340 // - (If le (CmpU length index)), (IfTrue throw exception)
10341 // - (If lt (CmpU index length)), (IfFalse throw exception)
10342 //
10343 // Match range check 'If le (CmpU length index)'.
10344 instruct rangeCheck_iReg_uimm15(cmpOp cmp, iRegIsrc src_length, uimmI15 index, label labl) %{
10345 match(If cmp (CmpU src_length index));
10346 effect(USE labl);
10347 predicate(TrapBasedRangeChecks &&
10348 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le &&
10349 PROB_UNLIKELY(_leaf->as_If()->_prob) >= PROB_ALWAYS &&
10350 (Matcher::branches_to_uncommon_trap(_leaf)));
10351
10352 ins_is_TrapBasedCheckNode(true);
10353
10354 format %{ "TWI $index $cmp $src_length \t// RangeCheck => trap $labl" %}
10355 size(4);
10356 ins_encode %{
10357 // TODO: PPC port $archOpcode(ppc64Opcode_twi);
10358 if ($cmp$$cmpcode == 0x1 /* less_equal */) {
10359 __ trap_range_check_le($src_length$$Register, $index$$constant);
10360 } else {
10361 // Both successors are uncommon traps, probability is 0.
10362 // Node got flipped during fixup flow.
10363 assert($cmp$$cmpcode == 0x9, "must be greater");
10364 __ trap_range_check_g($src_length$$Register, $index$$constant);
10365 }
10366 %}
10367 ins_pipe(pipe_class_trap);
10368 %}
10369
10370 // Match range check 'If lt (CmpU index length)'.
10371 instruct rangeCheck_iReg_iReg(cmpOp cmp, iRegIsrc src_index, iRegIsrc src_length, label labl) %{
10372 match(If cmp (CmpU src_index src_length));
10373 effect(USE labl);
10374 predicate(TrapBasedRangeChecks &&
10375 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt &&
10376 _leaf->as_If()->_prob >= PROB_ALWAYS &&
10377 (Matcher::branches_to_uncommon_trap(_leaf)));
10378
10379 ins_is_TrapBasedCheckNode(true);
10380
10381 format %{ "TW $src_index $cmp $src_length \t// RangeCheck => trap $labl" %}
10382 size(4);
10383 ins_encode %{
10384 // TODO: PPC port $archOpcode(ppc64Opcode_tw);
10385 if ($cmp$$cmpcode == 0x0 /* greater_equal */) {
10386 __ trap_range_check_ge($src_index$$Register, $src_length$$Register);
10387 } else {
10388 // Both successors are uncommon traps, probability is 0.
10389 // Node got flipped during fixup flow.
10390 assert($cmp$$cmpcode == 0x8, "must be less");
10391 __ trap_range_check_l($src_index$$Register, $src_length$$Register);
10392 }
10393 %}
10394 ins_pipe(pipe_class_trap);
10395 %}
10396
10397 // Match range check 'If lt (CmpU index length)'.
10398 instruct rangeCheck_uimm15_iReg(cmpOp cmp, iRegIsrc src_index, uimmI15 length, label labl) %{
10399 match(If cmp (CmpU src_index length));
10400 effect(USE labl);
10401 predicate(TrapBasedRangeChecks &&
10402 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt &&
10403 _leaf->as_If()->_prob >= PROB_ALWAYS &&
10404 (Matcher::branches_to_uncommon_trap(_leaf)));
10405
10406 ins_is_TrapBasedCheckNode(true);
10407
10408 format %{ "TWI $src_index $cmp $length \t// RangeCheck => trap $labl" %}
10409 size(4);
10410 ins_encode %{
10411 // TODO: PPC port $archOpcode(ppc64Opcode_twi);
10412 if ($cmp$$cmpcode == 0x0 /* greater_equal */) {
10413 __ trap_range_check_ge($src_index$$Register, $length$$constant);
10414 } else {
10415 // Both successors are uncommon traps, probability is 0.
10416 // Node got flipped during fixup flow.
10417 assert($cmp$$cmpcode == 0x8, "must be less");
10418 __ trap_range_check_l($src_index$$Register, $length$$constant);
10419 }
10420 %}
10421 ins_pipe(pipe_class_trap);
10422 %}
10423
10424 instruct compU_reg_reg(flagsReg crx, iRegIsrc src1, iRegIsrc src2) %{
10425 match(Set crx (CmpU src1 src2));
10426 format %{ "CMPLW $crx, $src1, $src2 \t// unsigned" %}
10427 size(4);
10428 ins_encode %{
10429 // TODO: PPC port $archOpcode(ppc64Opcode_cmpl);
10430 __ cmplw($crx$$CondRegister, $src1$$Register, $src2$$Register);
10431 %}
10432 ins_pipe(pipe_class_compare);
10433 %}
10434
10435 instruct compU_reg_uimm16(flagsReg crx, iRegIsrc src1, uimmI16 src2) %{
10436 match(Set crx (CmpU src1 src2));
10437 size(4);
10438 format %{ "CMPLWI $crx, $src1, $src2" %}
10439 ins_encode %{
10440 // TODO: PPC port $archOpcode(ppc64Opcode_cmpli);
10441 __ cmplwi($crx$$CondRegister, $src1$$Register, $src2$$constant);
10442 %}
10443 ins_pipe(pipe_class_compare);
10444 %}
10445
10446 // Implicit zero checks (more implicit null checks).
10447 // No constant pool entries required.
10448 instruct zeroCheckN_iReg_imm0(cmpOp cmp, iRegNsrc value, immN_0 zero, label labl) %{
10449 match(If cmp (CmpN value zero));
10450 effect(USE labl);
10451 predicate(TrapBasedNullChecks &&
10452 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne &&
10453 _leaf->as_If()->_prob >= PROB_LIKELY_MAG(4) &&
10454 Matcher::branches_to_uncommon_trap(_leaf));
10455 ins_cost(1);
10456
10457 ins_is_TrapBasedCheckNode(true);
10458
10459 format %{ "TDI $value $cmp $zero \t// ZeroCheckN => trap $labl" %}
10460 size(4);
10461 ins_encode %{
10462 // TODO: PPC port $archOpcode(ppc64Opcode_tdi);
10463 if ($cmp$$cmpcode == 0xA) {
10464 __ trap_null_check($value$$Register);
10465 } else {
10466 // Both successors are uncommon traps, probability is 0.
10467 // Node got flipped during fixup flow.
10468 assert($cmp$$cmpcode == 0x2 , "must be equal(0xA) or notEqual(0x2)");
10469 __ trap_null_check($value$$Register, Assembler::traptoGreaterThanUnsigned);
10470 }
10471 %}
10472 ins_pipe(pipe_class_trap);
10473 %}
10474
10475 // Compare narrow oops.
10476 instruct cmpN_reg_reg(flagsReg crx, iRegNsrc src1, iRegNsrc src2) %{
10477 match(Set crx (CmpN src1 src2));
10478
10479 size(4);
10480 ins_cost(DEFAULT_COST);
10481 format %{ "CMPLW $crx, $src1, $src2 \t// compressed ptr" %}
10482 ins_encode %{
10483 // TODO: PPC port $archOpcode(ppc64Opcode_cmpl);
10484 __ cmplw($crx$$CondRegister, $src1$$Register, $src2$$Register);
10485 %}
10486 ins_pipe(pipe_class_compare);
10487 %}
10488
10489 instruct cmpN_reg_imm0(flagsReg crx, iRegNsrc src1, immN_0 src2) %{
10490 match(Set crx (CmpN src1 src2));
10491 // Make this more expensive than zeroCheckN_iReg_imm0.
10492 ins_cost(DEFAULT_COST);
10493
10494 format %{ "CMPLWI $crx, $src1, $src2 \t// compressed ptr" %}
10495 size(4);
10496 ins_encode %{
10497 // TODO: PPC port $archOpcode(ppc64Opcode_cmpli);
10498 __ cmplwi($crx$$CondRegister, $src1$$Register, $src2$$constant);
10499 %}
10500 ins_pipe(pipe_class_compare);
10501 %}
10502
10503 // Implicit zero checks (more implicit null checks).
10504 // No constant pool entries required.
10505 instruct zeroCheckP_reg_imm0(cmpOp cmp, iRegP_N2P value, immP_0 zero, label labl) %{
10506 match(If cmp (CmpP value zero));
10507 effect(USE labl);
10508 predicate(TrapBasedNullChecks &&
10509 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne &&
10510 _leaf->as_If()->_prob >= PROB_LIKELY_MAG(4) &&
10511 Matcher::branches_to_uncommon_trap(_leaf));
10512
10513 ins_is_TrapBasedCheckNode(true);
10514
10515 format %{ "TDI $value $cmp $zero \t// ZeroCheckP => trap $labl" %}
10516 size(4);
10517 ins_encode %{
10518 // TODO: PPC port $archOpcode(ppc64Opcode_tdi);
10519 if ($cmp$$cmpcode == 0xA) {
10520 __ trap_null_check($value$$Register);
10521 } else {
10522 // Both successors are uncommon traps, probability is 0.
10523 // Node got flipped during fixup flow.
10524 assert($cmp$$cmpcode == 0x2 , "must be equal(0xA) or notEqual(0x2)");
10525 __ trap_null_check($value$$Register, Assembler::traptoGreaterThanUnsigned);
10526 }
10527 %}
10528 ins_pipe(pipe_class_trap);
10529 %}
10530
10531 // Compare Pointers
10532 instruct cmpP_reg_reg(flagsReg crx, iRegP_N2P src1, iRegP_N2P src2) %{
10533 match(Set crx (CmpP src1 src2));
10534 format %{ "CMPLD $crx, $src1, $src2 \t// ptr" %}
10535 size(4);
10536 ins_encode %{
10537 // TODO: PPC port $archOpcode(ppc64Opcode_cmpl);
10538 __ cmpld($crx$$CondRegister, $src1$$Register, $src2$$Register);
10539 %}
10540 ins_pipe(pipe_class_compare);
10541 %}
10542
10543 // Used in postalloc expand.
10544 instruct cmpP_reg_imm16(flagsReg crx, iRegPsrc src1, immL16 src2) %{
10545 // This match rule prevents reordering of node before a safepoint.
10546 // This only makes sense if this instructions is used exclusively
10547 // for the expansion of EncodeP!
10548 match(Set crx (CmpP src1 src2));
10549 predicate(false);
10550
10551 format %{ "CMPDI $crx, $src1, $src2" %}
10552 size(4);
10553 ins_encode %{
10554 // TODO: PPC port $archOpcode(ppc64Opcode_cmpi);
10555 __ cmpdi($crx$$CondRegister, $src1$$Register, $src2$$constant);
10556 %}
10557 ins_pipe(pipe_class_compare);
10558 %}
10559
10560 //----------Float Compares----------------------------------------------------
10561
10562 instruct cmpFUnordered_reg_reg(flagsReg crx, regF src1, regF src2) %{
10563 // no match-rule, false predicate
10564 effect(DEF crx, USE src1, USE src2);
10565 predicate(false);
10566
10567 format %{ "cmpFUrd $crx, $src1, $src2" %}
10568 size(4);
10569 ins_encode %{
10570 // TODO: PPC port $archOpcode(ppc64Opcode_fcmpu);
10571 __ fcmpu($crx$$CondRegister, $src1$$FloatRegister, $src2$$FloatRegister);
10572 %}
10573 ins_pipe(pipe_class_default);
10574 %}
10575
10576 instruct cmov_bns_less(flagsReg crx) %{
10577 // no match-rule, false predicate
10578 effect(DEF crx);
10579 predicate(false);
10580
10581 ins_variable_size_depending_on_alignment(true);
10582
10583 format %{ "cmov $crx" %}
10584 // Worst case is branch + move + stop, no stop without scheduler.
10585 size(false /* TODO: PPC PORT(InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 16 : 12);
10586 ins_encode %{
10587 // TODO: PPC port $archOpcode(ppc64Opcode_cmovecr);
10588 Label done;
10589 __ bns($crx$$CondRegister, done); // not unordered -> keep crx
10590 __ li(R0, 0);
10591 __ cmpwi($crx$$CondRegister, R0, 1); // unordered -> set crx to 'less'
10592 // TODO PPC port __ endgroup_if_needed(_size == 16);
10593 __ bind(done);
10594 %}
10595 ins_pipe(pipe_class_default);
10596 %}
10597
10598 // Compare floating, generate condition code.
10599 instruct cmpF_reg_reg_Ex(flagsReg crx, regF src1, regF src2) %{
10600 // FIXME: should we match 'If cmp (CmpF src1 src2))' ??
10601 //
10602 // The following code sequence occurs a lot in mpegaudio:
10603 //
10604 // block BXX:
10605 // 0: instruct cmpFUnordered_reg_reg (cmpF_reg_reg-0):
10606 // cmpFUrd CCR6, F11, F9
10607 // 4: instruct cmov_bns_less (cmpF_reg_reg-1):
10608 // cmov CCR6
10609 // 8: instruct branchConSched:
10610 // B_FARle CCR6, B56 P=0.500000 C=-1.000000
10611 match(Set crx (CmpF src1 src2));
10612 ins_cost(DEFAULT_COST+BRANCH_COST);
10613
10614 format %{ "CmpF $crx, $src1, $src2 \t// postalloc expanded" %}
10615 postalloc_expand %{
10616 //
10617 // replaces
10618 //
10619 // region src1 src2
10620 // \ | |
10621 // crx=cmpF_reg_reg
10622 //
10623 // with
10624 //
10625 // region src1 src2
10626 // \ | |
10627 // crx=cmpFUnordered_reg_reg
10628 // |
10629 // ^ region
10630 // | \
10631 // crx=cmov_bns_less
10632 //
10633
10634 // Create new nodes.
10635 MachNode *m1 = new (C) cmpFUnordered_reg_regNode();
10636 MachNode *m2 = new (C) cmov_bns_lessNode();
10637
10638 // inputs for new nodes
10639 m1->add_req(n_region, n_src1, n_src2);
10640 m2->add_req(n_region);
10641 m2->add_prec(m1);
10642
10643 // operands for new nodes
10644 m1->_opnds[0] = op_crx;
10645 m1->_opnds[1] = op_src1;
10646 m1->_opnds[2] = op_src2;
10647 m2->_opnds[0] = op_crx;
10648
10649 // registers for new nodes
10650 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // crx
10651 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // crx
10652
10653 // Insert new nodes.
10654 nodes->push(m1);
10655 nodes->push(m2);
10656 %}
10657 %}
10658
10659 // Compare float, generate -1,0,1
10660 instruct cmpF3_reg_reg_ExEx(iRegIdst dst, regF src1, regF src2) %{
10661 match(Set dst (CmpF3 src1 src2));
10662 ins_cost(DEFAULT_COST*5+BRANCH_COST);
10663
10664 expand %{
10665 flagsReg tmp1;
10666 cmpFUnordered_reg_reg(tmp1, src1, src2);
10667 cmovI_conIvalueMinus1_conIvalue0_conIvalue1_Ex(dst, tmp1);
10668 %}
10669 %}
10670
10671 instruct cmpDUnordered_reg_reg(flagsReg crx, regD src1, regD src2) %{
10672 // no match-rule, false predicate
10673 effect(DEF crx, USE src1, USE src2);
10674 predicate(false);
10675
10676 format %{ "cmpFUrd $crx, $src1, $src2" %}
10677 size(4);
10678 ins_encode %{
10679 // TODO: PPC port $archOpcode(ppc64Opcode_fcmpu);
10680 __ fcmpu($crx$$CondRegister, $src1$$FloatRegister, $src2$$FloatRegister);
10681 %}
10682 ins_pipe(pipe_class_default);
10683 %}
10684
10685 instruct cmpD_reg_reg_Ex(flagsReg crx, regD src1, regD src2) %{
10686 match(Set crx (CmpD src1 src2));
10687 ins_cost(DEFAULT_COST+BRANCH_COST);
10688
10689 format %{ "CmpD $crx, $src1, $src2 \t// postalloc expanded" %}
10690 postalloc_expand %{
10691 //
10692 // replaces
10693 //
10694 // region src1 src2
10695 // \ | |
10696 // crx=cmpD_reg_reg
10697 //
10698 // with
10699 //
10700 // region src1 src2
10701 // \ | |
10702 // crx=cmpDUnordered_reg_reg
10703 // |
10704 // ^ region
10705 // | \
10706 // crx=cmov_bns_less
10707 //
10708
10709 // create new nodes
10710 MachNode *m1 = new (C) cmpDUnordered_reg_regNode();
10711 MachNode *m2 = new (C) cmov_bns_lessNode();
10712
10713 // inputs for new nodes
10714 m1->add_req(n_region, n_src1, n_src2);
10715 m2->add_req(n_region);
10716 m2->add_prec(m1);
10717
10718 // operands for new nodes
10719 m1->_opnds[0] = op_crx;
10720 m1->_opnds[1] = op_src1;
10721 m1->_opnds[2] = op_src2;
10722 m2->_opnds[0] = op_crx;
10723
10724 // registers for new nodes
10725 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // crx
10726 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // crx
10727
10728 // Insert new nodes.
10729 nodes->push(m1);
10730 nodes->push(m2);
10731 %}
10732 %}
10733
10734 // Compare double, generate -1,0,1
10735 instruct cmpD3_reg_reg_ExEx(iRegIdst dst, regD src1, regD src2) %{
10736 match(Set dst (CmpD3 src1 src2));
10737 ins_cost(DEFAULT_COST*5+BRANCH_COST);
10738
10739 expand %{
10740 flagsReg tmp1;
10741 cmpDUnordered_reg_reg(tmp1, src1, src2);
10742 cmovI_conIvalueMinus1_conIvalue0_conIvalue1_Ex(dst, tmp1);
10743 %}
10744 %}
10745
10746 //----------Branches---------------------------------------------------------
10747 // Jump
10748
10749 // Direct Branch.
10750 instruct branch(label labl) %{
10751 match(Goto);
10752 effect(USE labl);
10753 ins_cost(BRANCH_COST);
10754
10755 format %{ "B $labl" %}
10756 size(4);
10757 ins_encode %{
10758 // TODO: PPC port $archOpcode(ppc64Opcode_b);
10759 Label d; // dummy
10760 __ bind(d);
10761 Label* p = $labl$$label;
10762 // `p' is `NULL' when this encoding class is used only to
10763 // determine the size of the encoded instruction.
10764 Label& l = (NULL == p)? d : *(p);
10765 __ b(l);
10766 %}
10767 ins_pipe(pipe_class_default);
10768 %}
10769
10770 // Conditional Near Branch
10771 instruct branchCon(cmpOp cmp, flagsReg crx, label lbl) %{
10772 // Same match rule as `branchConFar'.
10773 match(If cmp crx);
10774 effect(USE lbl);
10775 ins_cost(BRANCH_COST);
10776
10777 // If set to 1 this indicates that the current instruction is a
10778 // short variant of a long branch. This avoids using this
10779 // instruction in first-pass matching. It will then only be used in
10780 // the `Shorten_branches' pass.
10781 ins_short_branch(1);
10782
10783 format %{ "B$cmp $crx, $lbl" %}
10784 size(4);
10785 ins_encode( enc_bc(crx, cmp, lbl) );
10786 ins_pipe(pipe_class_default);
10787 %}
10788
10789 // This is for cases when the ppc64 `bc' instruction does not
10790 // reach far enough. So we emit a far branch here, which is more
10791 // expensive.
10792 //
10793 // Conditional Far Branch
10794 instruct branchConFar(cmpOp cmp, flagsReg crx, label lbl) %{
10795 // Same match rule as `branchCon'.
10796 match(If cmp crx);
10797 effect(USE crx, USE lbl);
10798 predicate(!false /* TODO: PPC port HB_Schedule*/);
10799 // Higher cost than `branchCon'.
10800 ins_cost(5*BRANCH_COST);
10801
10802 // This is not a short variant of a branch, but the long variant.
10803 ins_short_branch(0);
10804
10805 format %{ "B_FAR$cmp $crx, $lbl" %}
10806 size(8);
10807 ins_encode( enc_bc_far(crx, cmp, lbl) );
10808 ins_pipe(pipe_class_default);
10809 %}
10810
10811 // Conditional Branch used with Power6 scheduler (can be far or short).
10812 instruct branchConSched(cmpOp cmp, flagsReg crx, label lbl) %{
10813 // Same match rule as `branchCon'.
10814 match(If cmp crx);
10815 effect(USE crx, USE lbl);
10816 predicate(false /* TODO: PPC port HB_Schedule*/);
10817 // Higher cost than `branchCon'.
10818 ins_cost(5*BRANCH_COST);
10819
10820 // Actually size doesn't depend on alignment but on shortening.
10821 ins_variable_size_depending_on_alignment(true);
10822 // long variant.
10823 ins_short_branch(0);
10824
10825 format %{ "B_FAR$cmp $crx, $lbl" %}
10826 size(8); // worst case
10827 ins_encode( enc_bc_short_far(crx, cmp, lbl) );
10828 ins_pipe(pipe_class_default);
10829 %}
10830
10831 instruct branchLoopEnd(cmpOp cmp, flagsReg crx, label labl) %{
10832 match(CountedLoopEnd cmp crx);
10833 effect(USE labl);
10834 ins_cost(BRANCH_COST);
10835
10836 // short variant.
10837 ins_short_branch(1);
10838
10839 format %{ "B$cmp $crx, $labl \t// counted loop end" %}
10840 size(4);
10841 ins_encode( enc_bc(crx, cmp, labl) );
10842 ins_pipe(pipe_class_default);
10843 %}
10844
10845 instruct branchLoopEndFar(cmpOp cmp, flagsReg crx, label labl) %{
10846 match(CountedLoopEnd cmp crx);
10847 effect(USE labl);
10848 predicate(!false /* TODO: PPC port HB_Schedule */);
10849 ins_cost(BRANCH_COST);
10850
10851 // Long variant.
10852 ins_short_branch(0);
10853
10854 format %{ "B_FAR$cmp $crx, $labl \t// counted loop end" %}
10855 size(8);
10856 ins_encode( enc_bc_far(crx, cmp, labl) );
10857 ins_pipe(pipe_class_default);
10858 %}
10859
10860 // Conditional Branch used with Power6 scheduler (can be far or short).
10861 instruct branchLoopEndSched(cmpOp cmp, flagsReg crx, label labl) %{
10862 match(CountedLoopEnd cmp crx);
10863 effect(USE labl);
10864 predicate(false /* TODO: PPC port HB_Schedule */);
10865 // Higher cost than `branchCon'.
10866 ins_cost(5*BRANCH_COST);
10867
10868 // Actually size doesn't depend on alignment but on shortening.
10869 ins_variable_size_depending_on_alignment(true);
10870 // Long variant.
10871 ins_short_branch(0);
10872
10873 format %{ "B_FAR$cmp $crx, $labl \t// counted loop end" %}
10874 size(8); // worst case
10875 ins_encode( enc_bc_short_far(crx, cmp, labl) );
10876 ins_pipe(pipe_class_default);
10877 %}
10878
10879 // ============================================================================
10880 // Java runtime operations, intrinsics and other complex operations.
10881
10882 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass
10883 // array for an instance of the superklass. Set a hidden internal cache on a
10884 // hit (cache is checked with exposed code in gen_subtype_check()). Return
10885 // not zero for a miss or zero for a hit. The encoding ALSO sets flags.
10886 //
10887 // GL TODO: Improve this.
10888 // - result should not be a TEMP
10889 // - Add match rule as on sparc avoiding additional Cmp.
10890 instruct partialSubtypeCheck(iRegPdst result, iRegP_N2P subklass, iRegP_N2P superklass,
10891 iRegPdst tmp_klass, iRegPdst tmp_arrayptr) %{
10892 match(Set result (PartialSubtypeCheck subklass superklass));
10893 effect(TEMP result, TEMP tmp_klass, TEMP tmp_arrayptr);
10894 ins_cost(DEFAULT_COST*10);
10895
10896 format %{ "PartialSubtypeCheck $result = ($subklass instanceOf $superklass) tmp: $tmp_klass, $tmp_arrayptr" %}
10897 ins_encode %{
10898 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
10899 __ check_klass_subtype_slow_path($subklass$$Register, $superklass$$Register, $tmp_arrayptr$$Register,
10900 $tmp_klass$$Register, NULL, $result$$Register);
10901 %}
10902 ins_pipe(pipe_class_default);
10903 %}
10904
10905 // inlined locking and unlocking
10906
10907 instruct cmpFastLock(flagsReg crx, iRegPdst oop, iRegPdst box, iRegPdst tmp1, iRegPdst tmp2, iRegPdst tmp3) %{
10908 match(Set crx (FastLock oop box));
10909 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3);
10910 // TODO PPC port predicate(!UseNewFastLockPPC64 || UseBiasedLocking);
10911
10912 format %{ "FASTLOCK $oop, $box, $tmp1, $tmp2, $tmp3" %}
10913 ins_encode %{
10914 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
10915 __ compiler_fast_lock_object($crx$$CondRegister, $oop$$Register, $box$$Register,
10916 $tmp3$$Register, $tmp1$$Register, $tmp2$$Register);
10917 // If locking was successfull, crx should indicate 'EQ'.
10918 // The compiler generates a branch to the runtime call to
10919 // _complete_monitor_locking_Java for the case where crx is 'NE'.
10920 %}
10921 ins_pipe(pipe_class_compare);
10922 %}
10923
10924 instruct cmpFastUnlock(flagsReg crx, iRegPdst oop, iRegPdst box, iRegPdst tmp1, iRegPdst tmp2, iRegPdst tmp3) %{
10925 match(Set crx (FastUnlock oop box));
10926 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3);
10927
10928 format %{ "FASTUNLOCK $oop, $box, $tmp1, $tmp2" %}
10929 ins_encode %{
10930 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
10931 __ compiler_fast_unlock_object($crx$$CondRegister, $oop$$Register, $box$$Register,
10932 $tmp3$$Register, $tmp1$$Register, $tmp2$$Register);
10933 // If unlocking was successfull, crx should indicate 'EQ'.
10934 // The compiler generates a branch to the runtime call to
10935 // _complete_monitor_unlocking_Java for the case where crx is 'NE'.
10936 %}
10937 ins_pipe(pipe_class_compare);
10938 %}
10939
10940 // Align address.
10941 instruct align_addr(iRegPdst dst, iRegPsrc src, immLnegpow2 mask) %{
10942 match(Set dst (CastX2P (AndL (CastP2X src) mask)));
10943
10944 format %{ "ANDDI $dst, $src, $mask \t// next aligned address" %}
10945 size(4);
10946 ins_encode %{
10947 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
10948 __ clrrdi($dst$$Register, $src$$Register, log2_long((jlong)-$mask$$constant));
10949 %}
10950 ins_pipe(pipe_class_default);
10951 %}
10952
10953 // Array size computation.
10954 instruct array_size(iRegLdst dst, iRegPsrc end, iRegPsrc start) %{
10955 match(Set dst (SubL (CastP2X end) (CastP2X start)));
10956
10957 format %{ "SUB $dst, $end, $start \t// array size in bytes" %}
10958 size(4);
10959 ins_encode %{
10960 // TODO: PPC port $archOpcode(ppc64Opcode_subf);
10961 __ subf($dst$$Register, $start$$Register, $end$$Register);
10962 %}
10963 ins_pipe(pipe_class_default);
10964 %}
10965
10966 // Clear-array with dynamic array-size.
10967 instruct inlineCallClearArray(rarg1RegL cnt, rarg2RegP base, Universe dummy, regCTR ctr) %{
10968 match(Set dummy (ClearArray cnt base));
10969 effect(USE_KILL cnt, USE_KILL base, KILL ctr);
10970 ins_cost(MEMORY_REF_COST);
10971
10972 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted.
10973
10974 format %{ "ClearArray $cnt, $base" %}
10975 ins_encode %{
10976 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
10977 __ clear_memory_doubleword($base$$Register, $cnt$$Register); // kills cnt, base, R0
10978 %}
10979 ins_pipe(pipe_class_default);
10980 %}
10981
10982 // String_IndexOf for needle of length 1.
10983 //
10984 // Match needle into immediate operands: no loadConP node needed. Saves one
10985 // register and two instructions over string_indexOf_imm1Node.
10986 //
10987 // Assumes register result differs from all input registers.
10988 //
10989 // Preserves registers haystack, haycnt
10990 // Kills registers tmp1, tmp2
10991 // Defines registers result
10992 //
10993 // Use dst register classes if register gets killed, as it is the case for tmp registers!
10994 //
10995 // Unfortunately this does not match too often. In many situations the AddP is used
10996 // by several nodes, even several StrIndexOf nodes, breaking the match tree.
10997 instruct string_indexOf_imm1_char(iRegIdst result, iRegPsrc haystack, iRegIsrc haycnt,
10998 immP needleImm, immL offsetImm, immI_1 needlecntImm,
10999 iRegIdst tmp1, iRegIdst tmp2,
11000 flagsRegCR0 cr0, flagsRegCR1 cr1) %{
11001 predicate(SpecialStringIndexOf); // type check implicit by parameter type, See Matcher::match_rule_supported
11002 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary (AddP needleImm offsetImm) needlecntImm)));
11003
11004 effect(TEMP result, TEMP tmp1, TEMP tmp2, KILL cr0, KILL cr1);
11005
11006 ins_cost(150);
11007 format %{ "String IndexOf CSCL1 $haystack[0..$haycnt], $needleImm+$offsetImm[0..$needlecntImm]"
11008 "-> $result \t// KILL $haycnt, $tmp1, $tmp2, $cr0, $cr1" %}
11009
11010 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted
11011 ins_encode %{
11012 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11013 immPOper *needleOper = (immPOper *)$needleImm;
11014 const TypeOopPtr *t = needleOper->type()->isa_oopptr();
11015 ciTypeArray* needle_values = t->const_oop()->as_type_array(); // Pointer to live char *
11016
11017 __ string_indexof_1($result$$Register,
11018 $haystack$$Register, $haycnt$$Register,
11019 R0, needle_values->char_at(0),
11020 $tmp1$$Register, $tmp2$$Register);
11021 %}
11022 ins_pipe(pipe_class_compare);
11023 %}
11024
11025 // String_IndexOf for needle of length 1.
11026 //
11027 // Special case requires less registers and emits less instructions.
11028 //
11029 // Assumes register result differs from all input registers.
11030 //
11031 // Preserves registers haystack, haycnt
11032 // Kills registers tmp1, tmp2, needle
11033 // Defines registers result
11034 //
11035 // Use dst register classes if register gets killed, as it is the case for tmp registers!
11036 instruct string_indexOf_imm1(iRegIdst result, iRegPsrc haystack, iRegIsrc haycnt,
11037 rscratch2RegP needle, immI_1 needlecntImm,
11038 iRegIdst tmp1, iRegIdst tmp2,
11039 flagsRegCR0 cr0, flagsRegCR1 cr1) %{
11040 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecntImm)));
11041 effect(USE_KILL needle, /* TDEF needle, */ TEMP result,
11042 TEMP tmp1, TEMP tmp2);
11043 // Required for EA: check if it is still a type_array.
11044 predicate(SpecialStringIndexOf && n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop() &&
11045 n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop()->is_type_array());
11046 ins_cost(180);
11047
11048 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted.
11049
11050 format %{ "String IndexOf SCL1 $haystack[0..$haycnt], $needle[0..$needlecntImm]"
11051 " -> $result \t// KILL $haycnt, $needle, $tmp1, $tmp2, $cr0, $cr1" %}
11052 ins_encode %{
11053 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11054 Node *ndl = in(operand_index($needle)); // The node that defines needle.
11055 ciTypeArray* needle_values = ndl->bottom_type()->is_aryptr()->const_oop()->as_type_array();
11056 guarantee(needle_values, "sanity");
11057 if (needle_values != NULL) {
11058 __ string_indexof_1($result$$Register,
11059 $haystack$$Register, $haycnt$$Register,
11060 R0, needle_values->char_at(0),
11061 $tmp1$$Register, $tmp2$$Register);
11062 } else {
11063 __ string_indexof_1($result$$Register,
11064 $haystack$$Register, $haycnt$$Register,
11065 $needle$$Register, 0,
11066 $tmp1$$Register, $tmp2$$Register);
11067 }
11068 %}
11069 ins_pipe(pipe_class_compare);
11070 %}
11071
11072 // String_IndexOf.
11073 //
11074 // Length of needle as immediate. This saves instruction loading constant needle
11075 // length.
11076 // @@@ TODO Specify rules for length < 8 or so, and roll out comparison of needle
11077 // completely or do it in vector instruction. This should save registers for
11078 // needlecnt and needle.
11079 //
11080 // Assumes register result differs from all input registers.
11081 // Overwrites haycnt, needlecnt.
11082 // Use dst register classes if register gets killed, as it is the case for tmp registers!
11083 instruct string_indexOf_imm(iRegIdst result, iRegPsrc haystack, rscratch1RegI haycnt,
11084 iRegPsrc needle, uimmI15 needlecntImm,
11085 iRegIdst tmp1, iRegIdst tmp2, iRegIdst tmp3, iRegIdst tmp4, iRegIdst tmp5,
11086 flagsRegCR0 cr0, flagsRegCR1 cr1, flagsRegCR6 cr6) %{
11087 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecntImm)));
11088 effect(USE_KILL haycnt, /* better: TDEF haycnt, */ TEMP result,
11089 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5, KILL cr0, KILL cr1, KILL cr6);
11090 // Required for EA: check if it is still a type_array.
11091 predicate(SpecialStringIndexOf && n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop() &&
11092 n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop()->is_type_array());
11093 ins_cost(250);
11094
11095 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted.
11096
11097 format %{ "String IndexOf SCL $haystack[0..$haycnt], $needle[0..$needlecntImm]"
11098 " -> $result \t// KILL $haycnt, $tmp1, $tmp2, $tmp3, $tmp4, $tmp5, $cr0, $cr1" %}
11099 ins_encode %{
11100 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11101 Node *ndl = in(operand_index($needle)); // The node that defines needle.
11102 ciTypeArray* needle_values = ndl->bottom_type()->is_aryptr()->const_oop()->as_type_array();
11103
11104 __ string_indexof($result$$Register,
11105 $haystack$$Register, $haycnt$$Register,
11106 $needle$$Register, needle_values, $tmp5$$Register, $needlecntImm$$constant,
11107 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register);
11108 %}
11109 ins_pipe(pipe_class_compare);
11110 %}
11111
11112 // StrIndexOf node.
11113 //
11114 // Assumes register result differs from all input registers.
11115 // Overwrites haycnt, needlecnt.
11116 // Use dst register classes if register gets killed, as it is the case for tmp registers!
11117 instruct string_indexOf(iRegIdst result, iRegPsrc haystack, rscratch1RegI haycnt, iRegPsrc needle, rscratch2RegI needlecnt,
11118 iRegLdst tmp1, iRegLdst tmp2, iRegLdst tmp3, iRegLdst tmp4,
11119 flagsRegCR0 cr0, flagsRegCR1 cr1, flagsRegCR6 cr6) %{
11120 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecnt)));
11121 effect(USE_KILL haycnt, USE_KILL needlecnt, /*better: TDEF haycnt, TDEF needlecnt,*/
11122 TEMP result,
11123 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL cr0, KILL cr1, KILL cr6);
11124 predicate(SpecialStringIndexOf); // See Matcher::match_rule_supported.
11125 ins_cost(300);
11126
11127 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted.
11128
11129 format %{ "String IndexOf $haystack[0..$haycnt], $needle[0..$needlecnt]"
11130 " -> $result \t// KILL $haycnt, $needlecnt, $tmp1, $tmp2, $tmp3, $tmp4, $cr0, $cr1" %}
11131 ins_encode %{
11132 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11133 __ string_indexof($result$$Register,
11134 $haystack$$Register, $haycnt$$Register,
11135 $needle$$Register, NULL, $needlecnt$$Register, 0, // needlecnt not constant.
11136 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register);
11137 %}
11138 ins_pipe(pipe_class_compare);
11139 %}
11140
11141 // String equals with immediate.
11142 instruct string_equals_imm(iRegPsrc str1, iRegPsrc str2, uimmI15 cntImm, iRegIdst result,
11143 iRegPdst tmp1, iRegPdst tmp2,
11144 flagsRegCR0 cr0, flagsRegCR6 cr6, regCTR ctr) %{
11145 match(Set result (StrEquals (Binary str1 str2) cntImm));
11146 effect(TEMP result, TEMP tmp1, TEMP tmp2,
11147 KILL cr0, KILL cr6, KILL ctr);
11148 predicate(SpecialStringEquals); // See Matcher::match_rule_supported.
11149 ins_cost(250);
11150
11151 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted.
11152
11153 format %{ "String Equals SCL [0..$cntImm]($str1),[0..$cntImm]($str2)"
11154 " -> $result \t// KILL $cr0, $cr6, $ctr, TEMP $result, $tmp1, $tmp2" %}
11155 ins_encode %{
11156 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11157 __ char_arrays_equalsImm($str1$$Register, $str2$$Register, $cntImm$$constant,
11158 $result$$Register, $tmp1$$Register, $tmp2$$Register);
11159 %}
11160 ins_pipe(pipe_class_compare);
11161 %}
11162
11163 // String equals.
11164 // Use dst register classes if register gets killed, as it is the case for TEMP operands!
11165 instruct string_equals(iRegPsrc str1, iRegPsrc str2, iRegIsrc cnt, iRegIdst result,
11166 iRegPdst tmp1, iRegPdst tmp2, iRegPdst tmp3, iRegPdst tmp4, iRegPdst tmp5,
11167 flagsRegCR0 cr0, flagsRegCR1 cr1, flagsRegCR6 cr6, regCTR ctr) %{
11168 match(Set result (StrEquals (Binary str1 str2) cnt));
11169 effect(TEMP result, TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5,
11170 KILL cr0, KILL cr1, KILL cr6, KILL ctr);
11171 predicate(SpecialStringEquals); // See Matcher::match_rule_supported.
11172 ins_cost(300);
11173
11174 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted.
11175
11176 format %{ "String Equals [0..$cnt]($str1),[0..$cnt]($str2) -> $result"
11177 " \t// KILL $cr0, $cr1, $cr6, $ctr, TEMP $result, $tmp1, $tmp2, $tmp3, $tmp4, $tmp5" %}
11178 ins_encode %{
11179 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11180 __ char_arrays_equals($str1$$Register, $str2$$Register, $cnt$$Register, $result$$Register,
11181 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register, $tmp5$$Register);
11182 %}
11183 ins_pipe(pipe_class_compare);
11184 %}
11185
11186 // String compare.
11187 // Char[] pointers are passed in.
11188 // Use dst register classes if register gets killed, as it is the case for TEMP operands!
11189 instruct string_compare(rarg1RegP str1, rarg2RegP str2, rarg3RegI cnt1, rarg4RegI cnt2, iRegIdst result,
11190 iRegPdst tmp, flagsRegCR0 cr0, regCTR ctr) %{
11191 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
11192 effect(USE_KILL cnt1, USE_KILL cnt2, USE_KILL str1, USE_KILL str2, TEMP result, TEMP tmp, KILL cr0, KILL ctr);
11193 ins_cost(300);
11194
11195 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted.
11196
11197 format %{ "String Compare $str1[0..$cnt1], $str2[0..$cnt2] -> $result"
11198 " \t// TEMP $tmp, $result KILLs $str1, $cnt1, $str2, $cnt2, $cr0, $ctr" %}
11199 ins_encode %{
11200 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11201 __ string_compare($str1$$Register, $str2$$Register, $cnt1$$Register, $cnt2$$Register,
11202 $result$$Register, $tmp$$Register);
11203 %}
11204 ins_pipe(pipe_class_compare);
11205 %}
11206
11207 //---------- Min/Max Instructions ---------------------------------------------
11208
11209 instruct minI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
11210 match(Set dst (MinI src1 src2));
11211 ins_cost(DEFAULT_COST*6);
11212
11213 expand %{
11214 iRegLdst src1s;
11215 iRegLdst src2s;
11216 iRegLdst diff;
11217 iRegLdst sm;
11218 iRegLdst doz; // difference or zero
11219 convI2L_reg(src1s, src1); // Ensure proper sign extension.
11220 convI2L_reg(src2s, src2); // Ensure proper sign extension.
11221 subL_reg_reg(diff, src2s, src1s);
11222 // Need to consider >=33 bit result, therefore we need signmaskL.
11223 signmask64L_regL(sm, diff);
11224 andL_reg_reg(doz, diff, sm); // <=0
11225 addI_regL_regL(dst, doz, src1s);
11226 %}
11227 %}
11228
11229 instruct maxI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
11230 match(Set dst (MaxI src1 src2));
11231 ins_cost(DEFAULT_COST*6);
11232
11233 expand %{
11234 iRegLdst src1s;
11235 iRegLdst src2s;
11236 iRegLdst diff;
11237 iRegLdst sm;
11238 iRegLdst doz; // difference or zero
11239 convI2L_reg(src1s, src1); // Ensure proper sign extension.
11240 convI2L_reg(src2s, src2); // Ensure proper sign extension.
11241 subL_reg_reg(diff, src2s, src1s);
11242 // Need to consider >=33 bit result, therefore we need signmaskL.
11243 signmask64L_regL(sm, diff);
11244 andcL_reg_reg(doz, diff, sm); // >=0
11245 addI_regL_regL(dst, doz, src1s);
11246 %}
11247 %}
11248
11249 //---------- Population Count Instructions ------------------------------------
11250
11251 // Popcnt for Power7.
11252 instruct popCountI(iRegIdst dst, iRegIsrc src) %{
11253 match(Set dst (PopCountI src));
11254 predicate(UsePopCountInstruction && VM_Version::has_popcntw());
11255 ins_cost(DEFAULT_COST);
11256
11257 format %{ "POPCNTW $dst, $src" %}
11258 size(4);
11259 ins_encode %{
11260 // TODO: PPC port $archOpcode(ppc64Opcode_popcntb);
11261 __ popcntw($dst$$Register, $src$$Register);
11262 %}
11263 ins_pipe(pipe_class_default);
11264 %}
11265
11266 // Popcnt for Power7.
11267 instruct popCountL(iRegIdst dst, iRegLsrc src) %{
11268 predicate(UsePopCountInstruction && VM_Version::has_popcntw());
11269 match(Set dst (PopCountL src));
11270 ins_cost(DEFAULT_COST);
11271
11272 format %{ "POPCNTD $dst, $src" %}
11273 size(4);
11274 ins_encode %{
11275 // TODO: PPC port $archOpcode(ppc64Opcode_popcntb);
11276 __ popcntd($dst$$Register, $src$$Register);
11277 %}
11278 ins_pipe(pipe_class_default);
11279 %}
11280
11281 instruct countLeadingZerosI(iRegIdst dst, iRegIsrc src) %{
11282 match(Set dst (CountLeadingZerosI src));
11283 predicate(UseCountLeadingZerosInstructionsPPC64); // See Matcher::match_rule_supported.
11284 ins_cost(DEFAULT_COST);
11285
11286 format %{ "CNTLZW $dst, $src" %}
11287 size(4);
11288 ins_encode %{
11289 // TODO: PPC port $archOpcode(ppc64Opcode_cntlzw);
11290 __ cntlzw($dst$$Register, $src$$Register);
11291 %}
11292 ins_pipe(pipe_class_default);
11293 %}
11294
11295 instruct countLeadingZerosL(iRegIdst dst, iRegLsrc src) %{
11296 match(Set dst (CountLeadingZerosL src));
11297 predicate(UseCountLeadingZerosInstructionsPPC64); // See Matcher::match_rule_supported.
11298 ins_cost(DEFAULT_COST);
11299
11300 format %{ "CNTLZD $dst, $src" %}
11301 size(4);
11302 ins_encode %{
11303 // TODO: PPC port $archOpcode(ppc64Opcode_cntlzd);
11304 __ cntlzd($dst$$Register, $src$$Register);
11305 %}
11306 ins_pipe(pipe_class_default);
11307 %}
11308
11309 instruct countLeadingZerosP(iRegIdst dst, iRegPsrc src) %{
11310 // no match-rule, false predicate
11311 effect(DEF dst, USE src);
11312 predicate(false);
11313
11314 format %{ "CNTLZD $dst, $src" %}
11315 size(4);
11316 ins_encode %{
11317 // TODO: PPC port $archOpcode(ppc64Opcode_cntlzd);
11318 __ cntlzd($dst$$Register, $src$$Register);
11319 %}
11320 ins_pipe(pipe_class_default);
11321 %}
11322
11323 instruct countTrailingZerosI_Ex(iRegIdst dst, iRegIsrc src) %{
11324 match(Set dst (CountTrailingZerosI src));
11325 predicate(UseCountLeadingZerosInstructionsPPC64);
11326 ins_cost(DEFAULT_COST);
11327
11328 expand %{
11329 immI16 imm1 %{ (int)-1 %}
11330 immI16 imm2 %{ (int)32 %}
11331 immI_minus1 m1 %{ -1 %}
11332 iRegIdst tmpI1;
11333 iRegIdst tmpI2;
11334 iRegIdst tmpI3;
11335 addI_reg_imm16(tmpI1, src, imm1);
11336 andcI_reg_reg(tmpI2, src, m1, tmpI1);
11337 countLeadingZerosI(tmpI3, tmpI2);
11338 subI_imm16_reg(dst, imm2, tmpI3);
11339 %}
11340 %}
11341
11342 instruct countTrailingZerosL_Ex(iRegIdst dst, iRegLsrc src) %{
11343 match(Set dst (CountTrailingZerosL src));
11344 predicate(UseCountLeadingZerosInstructionsPPC64);
11345 ins_cost(DEFAULT_COST);
11346
11347 expand %{
11348 immL16 imm1 %{ (long)-1 %}
11349 immI16 imm2 %{ (int)64 %}
11350 iRegLdst tmpL1;
11351 iRegLdst tmpL2;
11352 iRegIdst tmpL3;
11353 addL_reg_imm16(tmpL1, src, imm1);
11354 andcL_reg_reg(tmpL2, tmpL1, src);
11355 countLeadingZerosL(tmpL3, tmpL2);
11356 subI_imm16_reg(dst, imm2, tmpL3);
11357 %}
11358 %}
11359
11360 // Expand nodes for byte_reverse_int.
11361 instruct insrwi_a(iRegIdst dst, iRegIsrc src, immI16 pos, immI16 shift) %{
11362 effect(DEF dst, USE src, USE pos, USE shift);
11363 predicate(false);
11364
11365 format %{ "INSRWI $dst, $src, $pos, $shift" %}
11366 size(4);
11367 ins_encode %{
11368 // TODO: PPC port $archOpcode(ppc64Opcode_rlwimi);
11369 __ insrwi($dst$$Register, $src$$Register, $shift$$constant, $pos$$constant);
11370 %}
11371 ins_pipe(pipe_class_default);
11372 %}
11373
11374 // As insrwi_a, but with USE_DEF.
11375 instruct insrwi(iRegIdst dst, iRegIsrc src, immI16 pos, immI16 shift) %{
11376 effect(USE_DEF dst, USE src, USE pos, USE shift);
11377 predicate(false);
11378
11379 format %{ "INSRWI $dst, $src, $pos, $shift" %}
11380 size(4);
11381 ins_encode %{
11382 // TODO: PPC port $archOpcode(ppc64Opcode_rlwimi);
11383 __ insrwi($dst$$Register, $src$$Register, $shift$$constant, $pos$$constant);
11384 %}
11385 ins_pipe(pipe_class_default);
11386 %}
11387
11388 // Just slightly faster than java implementation.
11389 instruct bytes_reverse_int_Ex(iRegIdst dst, iRegIsrc src) %{
11390 match(Set dst (ReverseBytesI src));
11391 predicate(UseCountLeadingZerosInstructionsPPC64);
11392 ins_cost(DEFAULT_COST);
11393
11394 expand %{
11395 immI16 imm24 %{ (int) 24 %}
11396 immI16 imm16 %{ (int) 16 %}
11397 immI16 imm8 %{ (int) 8 %}
11398 immI16 imm4 %{ (int) 4 %}
11399 immI16 imm0 %{ (int) 0 %}
11400 iRegLdst tmpI1;
11401 iRegLdst tmpI2;
11402 iRegLdst tmpI3;
11403
11404 urShiftI_reg_imm(tmpI1, src, imm24);
11405 insrwi_a(dst, tmpI1, imm24, imm8);
11406 urShiftI_reg_imm(tmpI2, src, imm16);
11407 insrwi(dst, tmpI2, imm8, imm16);
11408 urShiftI_reg_imm(tmpI3, src, imm8);
11409 insrwi(dst, tmpI3, imm8, imm8);
11410 insrwi(dst, src, imm0, imm8);
11411 %}
11412 %}
11413
11414 //---------- Replicate Vector Instructions ------------------------------------
11415
11416 // Insrdi does replicate if src == dst.
11417 instruct repl32(iRegLdst dst) %{
11418 predicate(false);
11419 effect(USE_DEF dst);
11420
11421 format %{ "INSRDI $dst, #0, $dst, #32 \t// replicate" %}
11422 size(4);
11423 ins_encode %{
11424 // TODO: PPC port $archOpcode(ppc64Opcode_rldimi);
11425 __ insrdi($dst$$Register, $dst$$Register, 32, 0);
11426 %}
11427 ins_pipe(pipe_class_default);
11428 %}
11429
11430 // Insrdi does replicate if src == dst.
11431 instruct repl48(iRegLdst dst) %{
11432 predicate(false);
11433 effect(USE_DEF dst);
11434
11435 format %{ "INSRDI $dst, #0, $dst, #48 \t// replicate" %}
11436 size(4);
11437 ins_encode %{
11438 // TODO: PPC port $archOpcode(ppc64Opcode_rldimi);
11439 __ insrdi($dst$$Register, $dst$$Register, 48, 0);
11440 %}
11441 ins_pipe(pipe_class_default);
11442 %}
11443
11444 // Insrdi does replicate if src == dst.
11445 instruct repl56(iRegLdst dst) %{
11446 predicate(false);
11447 effect(USE_DEF dst);
11448
11449 format %{ "INSRDI $dst, #0, $dst, #56 \t// replicate" %}
11450 size(4);
11451 ins_encode %{
11452 // TODO: PPC port $archOpcode(ppc64Opcode_rldimi);
11453 __ insrdi($dst$$Register, $dst$$Register, 56, 0);
11454 %}
11455 ins_pipe(pipe_class_default);
11456 %}
11457
11458 instruct repl8B_reg_Ex(iRegLdst dst, iRegIsrc src) %{
11459 match(Set dst (ReplicateB src));
11460 predicate(n->as_Vector()->length() == 8);
11461 expand %{
11462 moveReg(dst, src);
11463 repl56(dst);
11464 repl48(dst);
11465 repl32(dst);
11466 %}
11467 %}
11468
11469 instruct repl8B_immI0(iRegLdst dst, immI_0 zero) %{
11470 match(Set dst (ReplicateB zero));
11471 predicate(n->as_Vector()->length() == 8);
11472 format %{ "LI $dst, #0 \t// replicate8B" %}
11473 size(4);
11474 ins_encode %{
11475 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
11476 __ li($dst$$Register, (int)((short)($zero$$constant & 0xFFFF)));
11477 %}
11478 ins_pipe(pipe_class_default);
11479 %}
11480
11481 instruct repl8B_immIminus1(iRegLdst dst, immI_minus1 src) %{
11482 match(Set dst (ReplicateB src));
11483 predicate(n->as_Vector()->length() == 8);
11484 format %{ "LI $dst, #-1 \t// replicate8B" %}
11485 size(4);
11486 ins_encode %{
11487 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
11488 __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF)));
11489 %}
11490 ins_pipe(pipe_class_default);
11491 %}
11492
11493 instruct repl4S_reg_Ex(iRegLdst dst, iRegIsrc src) %{
11494 match(Set dst (ReplicateS src));
11495 predicate(n->as_Vector()->length() == 4);
11496 expand %{
11497 moveReg(dst, src);
11498 repl48(dst);
11499 repl32(dst);
11500 %}
11501 %}
11502
11503 instruct repl4S_immI0(iRegLdst dst, immI_0 zero) %{
11504 match(Set dst (ReplicateS zero));
11505 predicate(n->as_Vector()->length() == 4);
11506 format %{ "LI $dst, #0 \t// replicate4C" %}
11507 size(4);
11508 ins_encode %{
11509 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
11510 __ li($dst$$Register, (int)((short)($zero$$constant & 0xFFFF)));
11511 %}
11512 ins_pipe(pipe_class_default);
11513 %}
11514
11515 instruct repl4S_immIminus1(iRegLdst dst, immI_minus1 src) %{
11516 match(Set dst (ReplicateS src));
11517 predicate(n->as_Vector()->length() == 4);
11518 format %{ "LI $dst, -1 \t// replicate4C" %}
11519 size(4);
11520 ins_encode %{
11521 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
11522 __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF)));
11523 %}
11524 ins_pipe(pipe_class_default);
11525 %}
11526
11527 instruct repl2I_reg_Ex(iRegLdst dst, iRegIsrc src) %{
11528 match(Set dst (ReplicateI src));
11529 predicate(n->as_Vector()->length() == 2);
11530 ins_cost(2 * DEFAULT_COST);
11531 expand %{
11532 moveReg(dst, src);
11533 repl32(dst);
11534 %}
11535 %}
11536
11537 instruct repl2I_immI0(iRegLdst dst, immI_0 zero) %{
11538 match(Set dst (ReplicateI zero));
11539 predicate(n->as_Vector()->length() == 2);
11540 format %{ "LI $dst, #0 \t// replicate4C" %}
11541 size(4);
11542 ins_encode %{
11543 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
11544 __ li($dst$$Register, (int)((short)($zero$$constant & 0xFFFF)));
11545 %}
11546 ins_pipe(pipe_class_default);
11547 %}
11548
11549 instruct repl2I_immIminus1(iRegLdst dst, immI_minus1 src) %{
11550 match(Set dst (ReplicateI src));
11551 predicate(n->as_Vector()->length() == 2);
11552 format %{ "LI $dst, -1 \t// replicate4C" %}
11553 size(4);
11554 ins_encode %{
11555 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
11556 __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF)));
11557 %}
11558 ins_pipe(pipe_class_default);
11559 %}
11560
11561 // Move float to int register via stack, replicate.
11562 instruct repl2F_reg_Ex(iRegLdst dst, regF src) %{
11563 match(Set dst (ReplicateF src));
11564 predicate(n->as_Vector()->length() == 2);
11565 ins_cost(2 * MEMORY_REF_COST + DEFAULT_COST);
11566 expand %{
11567 stackSlotL tmpS;
11568 iRegIdst tmpI;
11569 moveF2I_reg_stack(tmpS, src); // Move float to stack.
11570 moveF2I_stack_reg(tmpI, tmpS); // Move stack to int reg.
11571 moveReg(dst, tmpI); // Move int to long reg.
11572 repl32(dst); // Replicate bitpattern.
11573 %}
11574 %}
11575
11576 // Replicate scalar constant to packed float values in Double register
11577 instruct repl2F_immF_Ex(iRegLdst dst, immF src) %{
11578 match(Set dst (ReplicateF src));
11579 predicate(n->as_Vector()->length() == 2);
11580 ins_cost(5 * DEFAULT_COST);
11581
11582 format %{ "LD $dst, offset, $constanttablebase\t// load replicated float $src $src from table, postalloc expanded" %}
11583 postalloc_expand( postalloc_expand_load_replF_constant(dst, src, constanttablebase) );
11584 %}
11585
11586 // Replicate scalar zero constant to packed float values in Double register
11587 instruct repl2F_immF0(iRegLdst dst, immF_0 zero) %{
11588 match(Set dst (ReplicateF zero));
11589 predicate(n->as_Vector()->length() == 2);
11590
11591 format %{ "LI $dst, #0 \t// replicate2F" %}
11592 ins_encode %{
11593 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
11594 __ li($dst$$Register, 0x0);
11595 %}
11596 ins_pipe(pipe_class_default);
11597 %}
11598
11599 // ============================================================================
11600 // Safepoint Instruction
11601
11602 instruct safePoint_poll(iRegPdst poll) %{
11603 match(SafePoint poll);
11604 predicate(LoadPollAddressFromThread);
11605
11606 // It caused problems to add the effect that r0 is killed, but this
11607 // effect no longer needs to be mentioned, since r0 is not contained
11608 // in a reg_class.
11609
11610 format %{ "LD R0, #0, $poll \t// Safepoint poll for GC" %}
11611 size(4);
11612 ins_encode( enc_poll(0x0, poll) );
11613 ins_pipe(pipe_class_default);
11614 %}
11615
11616 // Safepoint without per-thread support. Load address of page to poll
11617 // as constant.
11618 // Rscratch2RegP is R12.
11619 // LoadConPollAddr node is added in pd_post_matching_hook(). It must be
11620 // a seperate node so that the oop map is at the right location.
11621 instruct safePoint_poll_conPollAddr(rscratch2RegP poll) %{
11622 match(SafePoint poll);
11623 predicate(!LoadPollAddressFromThread);
11624
11625 // It caused problems to add the effect that r0 is killed, but this
11626 // effect no longer needs to be mentioned, since r0 is not contained
11627 // in a reg_class.
11628
11629 format %{ "LD R0, #0, R12 \t// Safepoint poll for GC" %}
11630 ins_encode( enc_poll(0x0, poll) );
11631 ins_pipe(pipe_class_default);
11632 %}
11633
11634 // ============================================================================
11635 // Call Instructions
11636
11637 // Call Java Static Instruction
11638
11639 // Schedulable version of call static node.
11640 instruct CallStaticJavaDirect(method meth) %{
11641 match(CallStaticJava);
11642 effect(USE meth);
11643 predicate(!((CallStaticJavaNode*)n)->is_method_handle_invoke());
11644 ins_cost(CALL_COST);
11645
11646 ins_num_consts(3 /* up to 3 patchable constants: inline cache, 2 call targets. */);
11647
11648 format %{ "CALL,static $meth \t// ==> " %}
11649 size(4);
11650 ins_encode( enc_java_static_call(meth) );
11651 ins_pipe(pipe_class_call);
11652 %}
11653
11654 // Schedulable version of call static node.
11655 instruct CallStaticJavaDirectHandle(method meth) %{
11656 match(CallStaticJava);
11657 effect(USE meth);
11658 predicate(((CallStaticJavaNode*)n)->is_method_handle_invoke());
11659 ins_cost(CALL_COST);
11660
11661 ins_num_consts(3 /* up to 3 patchable constants: inline cache, 2 call targets. */);
11662
11663 format %{ "CALL,static $meth \t// ==> " %}
11664 ins_encode( enc_java_handle_call(meth) );
11665 ins_pipe(pipe_class_call);
11666 %}
11667
11668 // Call Java Dynamic Instruction
11669
11670 // Used by postalloc expand of CallDynamicJavaDirectSchedEx (actual call).
11671 // Loading of IC was postalloc expanded. The nodes loading the IC are reachable
11672 // via fields ins_field_load_ic_hi_node and ins_field_load_ic_node.
11673 // The call destination must still be placed in the constant pool.
11674 instruct CallDynamicJavaDirectSched(method meth) %{
11675 match(CallDynamicJava); // To get all the data fields we need ...
11676 effect(USE meth);
11677 predicate(false); // ... but never match.
11678
11679 ins_field_load_ic_hi_node(loadConL_hiNode*);
11680 ins_field_load_ic_node(loadConLNode*);
11681 ins_num_consts(1 /* 1 patchable constant: call destination */);
11682
11683 format %{ "BL \t// dynamic $meth ==> " %}
11684 size(4);
11685 ins_encode( enc_java_dynamic_call_sched(meth) );
11686 ins_pipe(pipe_class_call);
11687 %}
11688
11689 // Schedulable (i.e. postalloc expanded) version of call dynamic java.
11690 // We use postalloc expanded calls if we use inline caches
11691 // and do not update method data.
11692 //
11693 // This instruction has two constants: inline cache (IC) and call destination.
11694 // Loading the inline cache will be postalloc expanded, thus leaving a call with
11695 // one constant.
11696 instruct CallDynamicJavaDirectSched_Ex(method meth) %{
11697 match(CallDynamicJava);
11698 effect(USE meth);
11699 predicate(UseInlineCaches);
11700 ins_cost(CALL_COST);
11701
11702 ins_num_consts(2 /* 2 patchable constants: inline cache, call destination. */);
11703
11704 format %{ "CALL,dynamic $meth \t// postalloc expanded" %}
11705 postalloc_expand( postalloc_expand_java_dynamic_call_sched(meth, constanttablebase) );
11706 %}
11707
11708 // Compound version of call dynamic java
11709 // We use postalloc expanded calls if we use inline caches
11710 // and do not update method data.
11711 instruct CallDynamicJavaDirect(method meth) %{
11712 match(CallDynamicJava);
11713 effect(USE meth);
11714 predicate(!UseInlineCaches);
11715 ins_cost(CALL_COST);
11716
11717 // Enc_java_to_runtime_call needs up to 4 constants (method data oop).
11718 ins_num_consts(4);
11719
11720 format %{ "CALL,dynamic $meth \t// ==> " %}
11721 ins_encode( enc_java_dynamic_call(meth, constanttablebase) );
11722 ins_pipe(pipe_class_call);
11723 %}
11724
11725 // Call Runtime Instruction
11726
11727 instruct CallRuntimeDirect(method meth) %{
11728 match(CallRuntime);
11729 effect(USE meth);
11730 ins_cost(CALL_COST);
11731
11732 // Enc_java_to_runtime_call needs up to 3 constants: call target,
11733 // env for callee, C-toc.
11734 ins_num_consts(3);
11735
11736 format %{ "CALL,runtime" %}
11737 ins_encode( enc_java_to_runtime_call(meth) );
11738 ins_pipe(pipe_class_call);
11739 %}
11740
11741 // Call Leaf
11742
11743 // Used by postalloc expand of CallLeafDirect_Ex (mtctr).
11744 instruct CallLeafDirect_mtctr(iRegLdst dst, iRegLsrc src) %{
11745 effect(DEF dst, USE src);
11746
11747 ins_num_consts(1);
11748
11749 format %{ "MTCTR $src" %}
11750 size(4);
11751 ins_encode( enc_leaf_call_mtctr(src) );
11752 ins_pipe(pipe_class_default);
11753 %}
11754
11755 // Used by postalloc expand of CallLeafDirect_Ex (actual call).
11756 instruct CallLeafDirect(method meth) %{
11757 match(CallLeaf); // To get the data all the data fields we need ...
11758 effect(USE meth);
11759 predicate(false); // but never match.
11760
11761 format %{ "BCTRL \t// leaf call $meth ==> " %}
11762 size(4);
11763 ins_encode %{
11764 // TODO: PPC port $archOpcode(ppc64Opcode_bctrl);
11765 __ bctrl();
11766 %}
11767 ins_pipe(pipe_class_call);
11768 %}
11769
11770 // postalloc expand of CallLeafDirect.
11771 // Load adress to call from TOC, then bl to it.
11772 instruct CallLeafDirect_Ex(method meth) %{
11773 match(CallLeaf);
11774 effect(USE meth);
11775 ins_cost(CALL_COST);
11776
11777 // Postalloc_expand_java_to_runtime_call needs up to 3 constants: call target,
11778 // env for callee, C-toc.
11779 ins_num_consts(3);
11780
11781 format %{ "CALL,runtime leaf $meth \t// postalloc expanded" %}
11782 postalloc_expand( postalloc_expand_java_to_runtime_call(meth, constanttablebase) );
11783 %}
11784
11785 // Call runtime without safepoint - same as CallLeaf.
11786 // postalloc expand of CallLeafNoFPDirect.
11787 // Load adress to call from TOC, then bl to it.
11788 instruct CallLeafNoFPDirect_Ex(method meth) %{
11789 match(CallLeafNoFP);
11790 effect(USE meth);
11791 ins_cost(CALL_COST);
11792
11793 // Enc_java_to_runtime_call needs up to 3 constants: call target,
11794 // env for callee, C-toc.
11795 ins_num_consts(3);
11796
11797 format %{ "CALL,runtime leaf nofp $meth \t// postalloc expanded" %}
11798 postalloc_expand( postalloc_expand_java_to_runtime_call(meth, constanttablebase) );
11799 %}
11800
11801 // Tail Call; Jump from runtime stub to Java code.
11802 // Also known as an 'interprocedural jump'.
11803 // Target of jump will eventually return to caller.
11804 // TailJump below removes the return address.
11805 instruct TailCalljmpInd(iRegPdstNoScratch jump_target, inline_cache_regP method_oop) %{
11806 match(TailCall jump_target method_oop);
11807 ins_cost(CALL_COST);
11808
11809 format %{ "MTCTR $jump_target \t// $method_oop holds method oop\n\t"
11810 "BCTR \t// tail call" %}
11811 size(8);
11812 ins_encode %{
11813 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11814 __ mtctr($jump_target$$Register);
11815 __ bctr();
11816 %}
11817 ins_pipe(pipe_class_call);
11818 %}
11819
11820 // Return Instruction
11821 instruct Ret() %{
11822 match(Return);
11823 format %{ "BLR \t// branch to link register" %}
11824 size(4);
11825 ins_encode %{
11826 // TODO: PPC port $archOpcode(ppc64Opcode_blr);
11827 // LR is restored in MachEpilogNode. Just do the RET here.
11828 __ blr();
11829 %}
11830 ins_pipe(pipe_class_default);
11831 %}
11832
11833 // Tail Jump; remove the return address; jump to target.
11834 // TailCall above leaves the return address around.
11835 // TailJump is used in only one place, the rethrow_Java stub (fancy_jump=2).
11836 // ex_oop (Exception Oop) is needed in %o0 at the jump. As there would be a
11837 // "restore" before this instruction (in Epilogue), we need to materialize it
11838 // in %i0.
11839 instruct tailjmpInd(iRegPdstNoScratch jump_target, rarg1RegP ex_oop) %{
11840 match(TailJump jump_target ex_oop);
11841 ins_cost(CALL_COST);
11842
11843 format %{ "LD R4_ARG2 = LR\n\t"
11844 "MTCTR $jump_target\n\t"
11845 "BCTR \t// TailJump, exception oop: $ex_oop" %}
11846 size(12);
11847 ins_encode %{
11848 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11849 __ ld(R4_ARG2/* issuing pc */, _abi(lr), R1_SP);
11850 __ mtctr($jump_target$$Register);
11851 __ bctr();
11852 %}
11853 ins_pipe(pipe_class_call);
11854 %}
11855
11856 // Create exception oop: created by stack-crawling runtime code.
11857 // Created exception is now available to this handler, and is setup
11858 // just prior to jumping to this handler. No code emitted.
11859 instruct CreateException(rarg1RegP ex_oop) %{
11860 match(Set ex_oop (CreateEx));
11861 ins_cost(0);
11862
11863 format %{ " -- \t// exception oop; no code emitted" %}
11864 size(0);
11865 ins_encode( /*empty*/ );
11866 ins_pipe(pipe_class_default);
11867 %}
11868
11869 // Rethrow exception: The exception oop will come in the first
11870 // argument position. Then JUMP (not call) to the rethrow stub code.
11871 instruct RethrowException() %{
11872 match(Rethrow);
11873 ins_cost(CALL_COST);
11874
11875 format %{ "Jmp rethrow_stub" %}
11876 ins_encode %{
11877 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11878 cbuf.set_insts_mark();
11879 __ b64_patchable((address)OptoRuntime::rethrow_stub(), relocInfo::runtime_call_type);
11880 %}
11881 ins_pipe(pipe_class_call);
11882 %}
11883
11884 // Die now.
11885 instruct ShouldNotReachHere() %{
11886 match(Halt);
11887 ins_cost(CALL_COST);
11888
11889 format %{ "ShouldNotReachHere" %}
11890 size(4);
11891 ins_encode %{
11892 // TODO: PPC port $archOpcode(ppc64Opcode_tdi);
11893 __ trap_should_not_reach_here();
11894 %}
11895 ins_pipe(pipe_class_default);
11896 %}
11897
11898 // This name is KNOWN by the ADLC and cannot be changed. The ADLC
11899 // forces a 'TypeRawPtr::BOTTOM' output type for this guy.
11900 // Get a DEF on threadRegP, no costs, no encoding, use
11901 // 'ins_should_rematerialize(true)' to avoid spilling.
11902 instruct tlsLoadP(threadRegP dst) %{
11903 match(Set dst (ThreadLocal));
11904 ins_cost(0);
11905
11906 ins_should_rematerialize(true);
11907
11908 format %{ " -- \t// $dst=Thread::current(), empty" %}
11909 size(0);
11910 ins_encode( /*empty*/ );
11911 ins_pipe(pipe_class_empty);
11912 %}
11913
11914 //---Some PPC specific nodes---------------------------------------------------
11915
11916 // Stop a group.
11917 instruct endGroup() %{
11918 ins_cost(0);
11919
11920 ins_is_nop(true);
11921
11922 format %{ "End Bundle (ori r1, r1, 0)" %}
11923 size(4);
11924 ins_encode %{
11925 // TODO: PPC port $archOpcode(ppc64Opcode_endgroup);
11926 __ endgroup();
11927 %}
11928 ins_pipe(pipe_class_default);
11929 %}
11930
11931 // Nop instructions
11932
11933 instruct fxNop() %{
11934 ins_cost(0);
11935
11936 ins_is_nop(true);
11937
11938 format %{ "fxNop" %}
11939 size(4);
11940 ins_encode %{
11941 // TODO: PPC port $archOpcode(ppc64Opcode_fmr);
11942 __ nop();
11943 %}
11944 ins_pipe(pipe_class_default);
11945 %}
11946
11947 instruct fpNop0() %{
11948 ins_cost(0);
11949
11950 ins_is_nop(true);
11951
11952 format %{ "fpNop0" %}
11953 size(4);
11954 ins_encode %{
11955 // TODO: PPC port $archOpcode(ppc64Opcode_fmr);
11956 __ fpnop0();
11957 %}
11958 ins_pipe(pipe_class_default);
11959 %}
11960
11961 instruct fpNop1() %{
11962 ins_cost(0);
11963
11964 ins_is_nop(true);
11965
11966 format %{ "fpNop1" %}
11967 size(4);
11968 ins_encode %{
11969 // TODO: PPC port $archOpcode(ppc64Opcode_fmr);
11970 __ fpnop1();
11971 %}
11972 ins_pipe(pipe_class_default);
11973 %}
11974
11975 instruct brNop0() %{
11976 ins_cost(0);
11977 size(4);
11978 format %{ "brNop0" %}
11979 ins_encode %{
11980 // TODO: PPC port $archOpcode(ppc64Opcode_mcrf);
11981 __ brnop0();
11982 %}
11983 ins_is_nop(true);
11984 ins_pipe(pipe_class_default);
11985 %}
11986
11987 instruct brNop1() %{
11988 ins_cost(0);
11989
11990 ins_is_nop(true);
11991
11992 format %{ "brNop1" %}
11993 size(4);
11994 ins_encode %{
11995 // TODO: PPC port $archOpcode(ppc64Opcode_mcrf);
11996 __ brnop1();
11997 %}
11998 ins_pipe(pipe_class_default);
11999 %}
12000
12001 instruct brNop2() %{
12002 ins_cost(0);
12003
12004 ins_is_nop(true);
12005
12006 format %{ "brNop2" %}
12007 size(4);
12008 ins_encode %{
12009 // TODO: PPC port $archOpcode(ppc64Opcode_mcrf);
12010 __ brnop2();
12011 %}
12012 ins_pipe(pipe_class_default);
12013 %}
12014
12015 //----------PEEPHOLE RULES-----------------------------------------------------
12016 // These must follow all instruction definitions as they use the names
12017 // defined in the instructions definitions.
12018 //
12019 // peepmatch ( root_instr_name [preceeding_instruction]* );
12020 //
12021 // peepconstraint %{
12022 // (instruction_number.operand_name relational_op instruction_number.operand_name
12023 // [, ...] );
12024 // // instruction numbers are zero-based using left to right order in peepmatch
12025 //
12026 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
12027 // // provide an instruction_number.operand_name for each operand that appears
12028 // // in the replacement instruction's match rule
12029 //
12030 // ---------VM FLAGS---------------------------------------------------------
12031 //
12032 // All peephole optimizations can be turned off using -XX:-OptoPeephole
12033 //
12034 // Each peephole rule is given an identifying number starting with zero and
12035 // increasing by one in the order seen by the parser. An individual peephole
12036 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
12037 // on the command-line.
12038 //
12039 // ---------CURRENT LIMITATIONS----------------------------------------------
12040 //
12041 // Only match adjacent instructions in same basic block
12042 // Only equality constraints
12043 // Only constraints between operands, not (0.dest_reg == EAX_enc)
12044 // Only one replacement instruction
12045 //
12046 // ---------EXAMPLE----------------------------------------------------------
12047 //
12048 // // pertinent parts of existing instructions in architecture description
12049 // instruct movI(eRegI dst, eRegI src) %{
12050 // match(Set dst (CopyI src));
12051 // %}
12052 //
12053 // instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{
12054 // match(Set dst (AddI dst src));
12055 // effect(KILL cr);
12056 // %}
12057 //
12058 // // Change (inc mov) to lea
12059 // peephole %{
12060 // // increment preceeded by register-register move
12061 // peepmatch ( incI_eReg movI );
12062 // // require that the destination register of the increment
12063 // // match the destination register of the move
12064 // peepconstraint ( 0.dst == 1.dst );
12065 // // construct a replacement instruction that sets
12066 // // the destination to ( move's source register + one )
12067 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
12068 // %}
12069 //
12070 // Implementation no longer uses movX instructions since
12071 // machine-independent system no longer uses CopyX nodes.
12072 //
12073 // peephole %{
12074 // peepmatch ( incI_eReg movI );
12075 // peepconstraint ( 0.dst == 1.dst );
12076 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
12077 // %}
12078 //
12079 // peephole %{
12080 // peepmatch ( decI_eReg movI );
12081 // peepconstraint ( 0.dst == 1.dst );
12082 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
12083 // %}
12084 //
12085 // peephole %{
12086 // peepmatch ( addI_eReg_imm movI );
12087 // peepconstraint ( 0.dst == 1.dst );
12088 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
12089 // %}
12090 //
12091 // peephole %{
12092 // peepmatch ( addP_eReg_imm movP );
12093 // peepconstraint ( 0.dst == 1.dst );
12094 // peepreplace ( leaP_eReg_immI( 0.dst 1.src 0.src ) );
12095 // %}
12096
12097 // // Change load of spilled value to only a spill
12098 // instruct storeI(memory mem, eRegI src) %{
12099 // match(Set mem (StoreI mem src));
12100 // %}
12101 //
12102 // instruct loadI(eRegI dst, memory mem) %{
12103 // match(Set dst (LoadI mem));
12104 // %}
12105 //
12106 peephole %{
12107 peepmatch ( loadI storeI );
12108 peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem );
12109 peepreplace ( storeI( 1.mem 1.mem 1.src ) );
12110 %}
12111
12112 peephole %{
12113 peepmatch ( loadL storeL );
12114 peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem );
12115 peepreplace ( storeL( 1.mem 1.mem 1.src ) );
12116 %}
12117
12118 peephole %{
12119 peepmatch ( loadP storeP );
12120 peepconstraint ( 1.src == 0.dst, 1.dst == 0.mem );
12121 peepreplace ( storeP( 1.dst 1.dst 1.src ) );
12122 %}
12123
12124 //----------SMARTSPILL RULES---------------------------------------------------
12125 // These must follow all instruction definitions as they use the names
12126 // defined in the instructions definitions.