1 /*
2 * Copyright 1997-2008 Sun Microsystems, Inc. All Rights Reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
20 * CA 95054 USA or visit www.sun.com if you need additional information or
21 * have any questions.
22 *
23 */
24
25 class BiasedLockingCounters;
26
27 // <sys/trap.h> promises that the system will not use traps 16-31
28 #define ST_RESERVED_FOR_USER_0 0x10
29
30 /* Written: David Ungar 4/19/97 */
31
32 // Contains all the definitions needed for sparc assembly code generation.
33
34 // Register aliases for parts of the system:
35
36 // 64 bit values can be kept in g1-g5, o1-o5 and o7 and all 64 bits are safe
37 // across context switches in V8+ ABI. Of course, there are no 64 bit regs
38 // in V8 ABI. All 64 bits are preserved in V9 ABI for all registers.
39
40 // g2-g4 are scratch registers called "application globals". Their
41 // meaning is reserved to the "compilation system"--which means us!
42 // They are are not supposed to be touched by ordinary C code, although
43 // highly-optimized C code might steal them for temps. They are safe
44 // across thread switches, and the ABI requires that they be safe
45 // across function calls.
46 //
47 // g1 and g3 are touched by more modules. V8 allows g1 to be clobbered
48 // across func calls, and V8+ also allows g5 to be clobbered across
49 // func calls. Also, g1 and g5 can get touched while doing shared
50 // library loading.
51 //
52 // We must not touch g7 (it is the thread-self register) and g6 is
53 // reserved for certain tools. g0, of course, is always zero.
54 //
55 // (Sources: SunSoft Compilers Group, thread library engineers.)
56
57 // %%%% The interpreter should be revisited to reduce global scratch regs.
58
59 // This global always holds the current JavaThread pointer:
60
61 REGISTER_DECLARATION(Register, G2_thread , G2);
62 REGISTER_DECLARATION(Register, G6_heapbase , G6);
63
64 // The following globals are part of the Java calling convention:
65
66 REGISTER_DECLARATION(Register, G5_method , G5);
67 REGISTER_DECLARATION(Register, G5_megamorphic_method , G5_method);
68 REGISTER_DECLARATION(Register, G5_inline_cache_reg , G5_method);
69
70 // The following globals are used for the new C1 & interpreter calling convention:
71 REGISTER_DECLARATION(Register, Gargs , G4); // pointing to the last argument
72
73 // This local is used to preserve G2_thread in the interpreter and in stubs:
74 REGISTER_DECLARATION(Register, L7_thread_cache , L7);
75
76 // These globals are used as scratch registers in the interpreter:
77
78 REGISTER_DECLARATION(Register, Gframe_size , G1); // SAME REG as G1_scratch
79 REGISTER_DECLARATION(Register, G1_scratch , G1); // also SAME
80 REGISTER_DECLARATION(Register, G3_scratch , G3);
81 REGISTER_DECLARATION(Register, G4_scratch , G4);
82
83 // These globals are used as short-lived scratch registers in the compiler:
84
85 REGISTER_DECLARATION(Register, Gtemp , G5);
86
87 // The compiler requires that G5_megamorphic_method is G5_inline_cache_klass,
88 // because a single patchable "set" instruction (NativeMovConstReg,
89 // or NativeMovConstPatching for compiler1) instruction
90 // serves to set up either quantity, depending on whether the compiled
91 // call site is an inline cache or is megamorphic. See the function
92 // CompiledIC::set_to_megamorphic.
93 //
94 // On the other hand, G5_inline_cache_klass must differ from G5_method,
95 // because both registers are needed for an inline cache that calls
96 // an interpreted method.
97 //
98 // Note that G5_method is only the method-self for the interpreter,
99 // and is logically unrelated to G5_megamorphic_method.
100 //
101 // Invariants on G2_thread (the JavaThread pointer):
102 // - it should not be used for any other purpose anywhere
103 // - it must be re-initialized by StubRoutines::call_stub()
104 // - it must be preserved around every use of call_VM
105
106 // We can consider using g2/g3/g4 to cache more values than the
107 // JavaThread, such as the card-marking base or perhaps pointers into
108 // Eden. It's something of a waste to use them as scratch temporaries,
109 // since they are not supposed to be volatile. (Of course, if we find
110 // that Java doesn't benefit from application globals, then we can just
111 // use them as ordinary temporaries.)
112 //
113 // Since g1 and g5 (and/or g6) are the volatile (caller-save) registers,
114 // it makes sense to use them routinely for procedure linkage,
115 // whenever the On registers are not applicable. Examples: G5_method,
116 // G5_inline_cache_klass, and a double handful of miscellaneous compiler
117 // stubs. This means that compiler stubs, etc., should be kept to a
118 // maximum of two or three G-register arguments.
119
120
121 // stub frames
122
123 REGISTER_DECLARATION(Register, Lentry_args , L0); // pointer to args passed to callee (interpreter) not stub itself
124
125 // Interpreter frames
126
127 #ifdef CC_INTERP
128 REGISTER_DECLARATION(Register, Lstate , L0); // interpreter state object pointer
129 REGISTER_DECLARATION(Register, L1_scratch , L1); // scratch
130 REGISTER_DECLARATION(Register, Lmirror , L1); // mirror (for native methods only)
131 REGISTER_DECLARATION(Register, L2_scratch , L2);
132 REGISTER_DECLARATION(Register, L3_scratch , L3);
133 REGISTER_DECLARATION(Register, L4_scratch , L4);
134 REGISTER_DECLARATION(Register, Lscratch , L5); // C1 uses
135 REGISTER_DECLARATION(Register, Lscratch2 , L6); // C1 uses
136 REGISTER_DECLARATION(Register, L7_scratch , L7); // constant pool cache
137 REGISTER_DECLARATION(Register, O5_savedSP , O5);
138 REGISTER_DECLARATION(Register, I5_savedSP , I5); // Saved SP before bumping for locals. This is simply
139 // a copy SP, so in 64-bit it's a biased value. The bias
140 // is added and removed as needed in the frame code.
141 // Interface to signature handler
142 REGISTER_DECLARATION(Register, Llocals , L7); // pointer to locals for signature handler
143 REGISTER_DECLARATION(Register, Lmethod , L6); // methodOop when calling signature handler
144
145 #else
146 REGISTER_DECLARATION(Register, Lesp , L0); // expression stack pointer
147 REGISTER_DECLARATION(Register, Lbcp , L1); // pointer to next bytecode
148 REGISTER_DECLARATION(Register, Lmethod , L2);
149 REGISTER_DECLARATION(Register, Llocals , L3);
150 REGISTER_DECLARATION(Register, Largs , L3); // pointer to locals for signature handler
151 // must match Llocals in asm interpreter
152 REGISTER_DECLARATION(Register, Lmonitors , L4);
153 REGISTER_DECLARATION(Register, Lbyte_code , L5);
154 // When calling out from the interpreter we record SP so that we can remove any extra stack
155 // space allocated during adapter transitions. This register is only live from the point
156 // of the call until we return.
157 REGISTER_DECLARATION(Register, Llast_SP , L5);
158 REGISTER_DECLARATION(Register, Lscratch , L5);
159 REGISTER_DECLARATION(Register, Lscratch2 , L6);
160 REGISTER_DECLARATION(Register, LcpoolCache , L6); // constant pool cache
161
162 REGISTER_DECLARATION(Register, O5_savedSP , O5);
163 REGISTER_DECLARATION(Register, I5_savedSP , I5); // Saved SP before bumping for locals. This is simply
164 // a copy SP, so in 64-bit it's a biased value. The bias
165 // is added and removed as needed in the frame code.
166 REGISTER_DECLARATION(Register, IdispatchTables , I4); // Base address of the bytecode dispatch tables
167 REGISTER_DECLARATION(Register, IdispatchAddress , I3); // Register which saves the dispatch address for each bytecode
168 REGISTER_DECLARATION(Register, ImethodDataPtr , I2); // Pointer to the current method data
169 #endif /* CC_INTERP */
170
171 // NOTE: Lscratch2 and LcpoolCache point to the same registers in
172 // the interpreter code. If Lscratch2 needs to be used for some
173 // purpose than LcpoolCache should be restore after that for
174 // the interpreter to work right
175 // (These assignments must be compatible with L7_thread_cache; see above.)
176
177 // Since Lbcp points into the middle of the method object,
178 // it is temporarily converted into a "bcx" during GC.
179
180 // Exception processing
181 // These registers are passed into exception handlers.
182 // All exception handlers require the exception object being thrown.
183 // In addition, an nmethod's exception handler must be passed
184 // the address of the call site within the nmethod, to allow
185 // proper selection of the applicable catch block.
186 // (Interpreter frames use their own bcp() for this purpose.)
187 //
188 // The Oissuing_pc value is not always needed. When jumping to a
189 // handler that is known to be interpreted, the Oissuing_pc value can be
190 // omitted. An actual catch block in compiled code receives (from its
191 // nmethod's exception handler) the thrown exception in the Oexception,
192 // but it doesn't need the Oissuing_pc.
193 //
194 // If an exception handler (either interpreted or compiled)
195 // discovers there is no applicable catch block, it updates
196 // the Oissuing_pc to the continuation PC of its own caller,
197 // pops back to that caller's stack frame, and executes that
198 // caller's exception handler. Obviously, this process will
199 // iterate until the control stack is popped back to a method
200 // containing an applicable catch block. A key invariant is
201 // that the Oissuing_pc value is always a value local to
202 // the method whose exception handler is currently executing.
203 //
204 // Note: The issuing PC value is __not__ a raw return address (I7 value).
205 // It is a "return pc", the address __following__ the call.
206 // Raw return addresses are converted to issuing PCs by frame::pc(),
207 // or by stubs. Issuing PCs can be used directly with PC range tables.
208 //
209 REGISTER_DECLARATION(Register, Oexception , O0); // exception being thrown
210 REGISTER_DECLARATION(Register, Oissuing_pc , O1); // where the exception is coming from
211
212
213 // These must occur after the declarations above
214 #ifndef DONT_USE_REGISTER_DEFINES
215
216 #define Gthread AS_REGISTER(Register, Gthread)
217 #define Gmethod AS_REGISTER(Register, Gmethod)
218 #define Gmegamorphic_method AS_REGISTER(Register, Gmegamorphic_method)
219 #define Ginline_cache_reg AS_REGISTER(Register, Ginline_cache_reg)
220 #define Gargs AS_REGISTER(Register, Gargs)
221 #define Lthread_cache AS_REGISTER(Register, Lthread_cache)
222 #define Gframe_size AS_REGISTER(Register, Gframe_size)
223 #define Gtemp AS_REGISTER(Register, Gtemp)
224
225 #ifdef CC_INTERP
226 #define Lstate AS_REGISTER(Register, Lstate)
227 #define Lesp AS_REGISTER(Register, Lesp)
228 #define L1_scratch AS_REGISTER(Register, L1_scratch)
229 #define Lmirror AS_REGISTER(Register, Lmirror)
230 #define L2_scratch AS_REGISTER(Register, L2_scratch)
231 #define L3_scratch AS_REGISTER(Register, L3_scratch)
232 #define L4_scratch AS_REGISTER(Register, L4_scratch)
233 #define Lscratch AS_REGISTER(Register, Lscratch)
234 #define Lscratch2 AS_REGISTER(Register, Lscratch2)
235 #define L7_scratch AS_REGISTER(Register, L7_scratch)
236 #define Ostate AS_REGISTER(Register, Ostate)
237 #else
238 #define Lesp AS_REGISTER(Register, Lesp)
239 #define Lbcp AS_REGISTER(Register, Lbcp)
240 #define Lmethod AS_REGISTER(Register, Lmethod)
241 #define Llocals AS_REGISTER(Register, Llocals)
242 #define Lmonitors AS_REGISTER(Register, Lmonitors)
243 #define Lbyte_code AS_REGISTER(Register, Lbyte_code)
244 #define Lscratch AS_REGISTER(Register, Lscratch)
245 #define Lscratch2 AS_REGISTER(Register, Lscratch2)
246 #define LcpoolCache AS_REGISTER(Register, LcpoolCache)
247 #endif /* ! CC_INTERP */
248
249 #define Lentry_args AS_REGISTER(Register, Lentry_args)
250 #define I5_savedSP AS_REGISTER(Register, I5_savedSP)
251 #define O5_savedSP AS_REGISTER(Register, O5_savedSP)
252 #define IdispatchAddress AS_REGISTER(Register, IdispatchAddress)
253 #define ImethodDataPtr AS_REGISTER(Register, ImethodDataPtr)
254 #define IdispatchTables AS_REGISTER(Register, IdispatchTables)
255
256 #define Oexception AS_REGISTER(Register, Oexception)
257 #define Oissuing_pc AS_REGISTER(Register, Oissuing_pc)
258
259
260 #endif
261
262 // Address is an abstraction used to represent a memory location.
263 //
264 // Note: A register location is represented via a Register, not
265 // via an address for efficiency & simplicity reasons.
266
267 class Address VALUE_OBJ_CLASS_SPEC {
268 private:
269 Register _base;
270 #ifdef _LP64
271 int _hi32; // bits 63::32
272 int _low32; // bits 31::0
273 #endif
274 int _hi;
275 int _disp;
276 RelocationHolder _rspec;
277
278 RelocationHolder rspec_from_rtype(relocInfo::relocType rt, address a = NULL) {
279 switch (rt) {
280 case relocInfo::external_word_type:
281 return external_word_Relocation::spec(a);
282 case relocInfo::internal_word_type:
283 return internal_word_Relocation::spec(a);
284 #ifdef _LP64
285 case relocInfo::opt_virtual_call_type:
286 return opt_virtual_call_Relocation::spec();
287 case relocInfo::static_call_type:
288 return static_call_Relocation::spec();
289 case relocInfo::runtime_call_type:
290 return runtime_call_Relocation::spec();
291 #endif
292 case relocInfo::none:
293 return RelocationHolder();
294 default:
295 ShouldNotReachHere();
296 return RelocationHolder();
297 }
298 }
299
300 public:
301 Address(Register b, address a, relocInfo::relocType rt = relocInfo::none)
302 : _rspec(rspec_from_rtype(rt, a))
303 {
304 _base = b;
305 #ifdef _LP64
306 _hi32 = (intptr_t)a >> 32; // top 32 bits in 64 bit word
307 _low32 = (intptr_t)a & ~0; // low 32 bits in 64 bit word
308 #endif
309 _hi = (intptr_t)a & ~0x3ff; // top 22 bits in low word
310 _disp = (intptr_t)a & 0x3ff; // bottom 10 bits
311 }
312
313 Address(Register b, address a, RelocationHolder const& rspec)
314 : _rspec(rspec)
315 {
316 _base = b;
317 #ifdef _LP64
318 _hi32 = (intptr_t)a >> 32; // top 32 bits in 64 bit word
319 _low32 = (intptr_t)a & ~0; // low 32 bits in 64 bit word
320 #endif
321 _hi = (intptr_t)a & ~0x3ff; // top 22 bits
322 _disp = (intptr_t)a & 0x3ff; // bottom 10 bits
323 }
324
325 Address(Register b, intptr_t h, intptr_t d, RelocationHolder const& rspec = RelocationHolder())
326 : _rspec(rspec)
327 {
328 _base = b;
329 #ifdef _LP64
330 // [RGV] Put in Assert to force me to check usage of this constructor
331 assert( h == 0, "Check usage of this constructor" );
332 _hi32 = h;
333 _low32 = d;
334 _hi = h;
335 _disp = d;
336 #else
337 _hi = h;
338 _disp = d;
339 #endif
340 }
341
342 Address()
343 : _rspec(RelocationHolder())
344 {
345 _base = G0;
346 #ifdef _LP64
347 _hi32 = 0;
348 _low32 = 0;
349 #endif
350 _hi = 0;
351 _disp = 0;
352 }
353
354 // fancier constructors
355
356 enum addr_type {
357 extra_in_argument, // in the In registers
358 extra_out_argument // in the Outs
359 };
360
361 Address( addr_type, int );
362
363 // accessors
364
365 Register base() const { return _base; }
366 #ifdef _LP64
367 int hi32() const { return _hi32; }
368 int low32() const { return _low32; }
369 #endif
370 int hi() const { return _hi; }
371 int disp() const { return _disp; }
372 #ifdef _LP64
373 intptr_t value() const { return ((intptr_t)_hi32 << 32) |
374 (intptr_t)(uint32_t)_low32; }
375 #else
376 int value() const { return _hi | _disp; }
377 #endif
378 const relocInfo::relocType rtype() { return _rspec.type(); }
379 const RelocationHolder& rspec() { return _rspec; }
380
381 RelocationHolder rspec(int offset) const {
382 return offset == 0 ? _rspec : _rspec.plus(offset);
383 }
384
385 inline bool is_simm13(int offset = 0); // check disp+offset for overflow
386
387 Address split_disp() const { // deal with disp overflow
388 Address a = (*this);
389 int hi_disp = _disp & ~0x3ff;
390 if (hi_disp != 0) {
391 a._disp -= hi_disp;
392 a._hi += hi_disp;
393 }
394 return a;
395 }
396
397 Address after_save() const {
398 Address a = (*this);
399 a._base = a._base->after_save();
400 return a;
401 }
402
403 Address after_restore() const {
404 Address a = (*this);
405 a._base = a._base->after_restore();
406 return a;
407 }
408
409 friend class Assembler;
410 };
411
412
413 inline Address RegisterImpl::address_in_saved_window() const {
414 return (Address(SP, 0, (sp_offset_in_saved_window() * wordSize) + STACK_BIAS));
415 }
416
417
418
419 // Argument is an abstraction used to represent an outgoing
420 // actual argument or an incoming formal parameter, whether
421 // it resides in memory or in a register, in a manner consistent
422 // with the SPARC Application Binary Interface, or ABI. This is
423 // often referred to as the native or C calling convention.
424
425 class Argument VALUE_OBJ_CLASS_SPEC {
426 private:
427 int _number;
428 bool _is_in;
429
430 public:
431 #ifdef _LP64
432 enum {
433 n_register_parameters = 6, // only 6 registers may contain integer parameters
434 n_float_register_parameters = 16 // Can have up to 16 floating registers
435 };
436 #else
437 enum {
438 n_register_parameters = 6 // only 6 registers may contain integer parameters
439 };
440 #endif
441
442 // creation
443 Argument(int number, bool is_in) : _number(number), _is_in(is_in) {}
444
445 int number() const { return _number; }
446 bool is_in() const { return _is_in; }
447 bool is_out() const { return !is_in(); }
448
449 Argument successor() const { return Argument(number() + 1, is_in()); }
450 Argument as_in() const { return Argument(number(), true ); }
451 Argument as_out() const { return Argument(number(), false); }
452
453 // locating register-based arguments:
454 bool is_register() const { return _number < n_register_parameters; }
455
456 #ifdef _LP64
457 // locating Floating Point register-based arguments:
458 bool is_float_register() const { return _number < n_float_register_parameters; }
459
460 FloatRegister as_float_register() const {
461 assert(is_float_register(), "must be a register argument");
462 return as_FloatRegister(( number() *2 ) + 1);
463 }
464 FloatRegister as_double_register() const {
465 assert(is_float_register(), "must be a register argument");
466 return as_FloatRegister(( number() *2 ));
467 }
468 #endif
469
470 Register as_register() const {
471 assert(is_register(), "must be a register argument");
472 return is_in() ? as_iRegister(number()) : as_oRegister(number());
473 }
474
475 // locating memory-based arguments
476 Address as_address() const {
477 assert(!is_register(), "must be a memory argument");
478 return address_in_frame();
479 }
480
481 // When applied to a register-based argument, give the corresponding address
482 // into the 6-word area "into which callee may store register arguments"
483 // (This is a different place than the corresponding register-save area location.)
484 Address address_in_frame() const {
485 return Address( is_in() ? Address::extra_in_argument
486 : Address::extra_out_argument,
487 _number );
488 }
489
490 // debugging
491 const char* name() const;
492
493 friend class Assembler;
494 };
495
496
497 // The SPARC Assembler: Pure assembler doing NO optimizations on the instruction
498 // level; i.e., what you write
499 // is what you get. The Assembler is generating code into a CodeBuffer.
500
501 class Assembler : public AbstractAssembler {
502 protected:
503
504 static void print_instruction(int inst);
505 static int patched_branch(int dest_pos, int inst, int inst_pos);
506 static int branch_destination(int inst, int pos);
507
508
509 friend class AbstractAssembler;
510
511 // code patchers need various routines like inv_wdisp()
512 friend class NativeInstruction;
513 friend class NativeGeneralJump;
514 friend class Relocation;
515 friend class Label;
516
517 public:
518 // op carries format info; see page 62 & 267
519
520 enum ops {
521 call_op = 1, // fmt 1
522 branch_op = 0, // also sethi (fmt2)
523 arith_op = 2, // fmt 3, arith & misc
524 ldst_op = 3 // fmt 3, load/store
525 };
526
527 enum op2s {
528 bpr_op2 = 3,
529 fb_op2 = 6,
530 fbp_op2 = 5,
531 br_op2 = 2,
532 bp_op2 = 1,
533 cb_op2 = 7, // V8
534 sethi_op2 = 4
535 };
536
537 enum op3s {
538 // selected op3s
539 add_op3 = 0x00,
540 and_op3 = 0x01,
541 or_op3 = 0x02,
542 xor_op3 = 0x03,
543 sub_op3 = 0x04,
544 andn_op3 = 0x05,
545 orn_op3 = 0x06,
546 xnor_op3 = 0x07,
547 addc_op3 = 0x08,
548 mulx_op3 = 0x09,
549 umul_op3 = 0x0a,
550 smul_op3 = 0x0b,
551 subc_op3 = 0x0c,
552 udivx_op3 = 0x0d,
553 udiv_op3 = 0x0e,
554 sdiv_op3 = 0x0f,
555
556 addcc_op3 = 0x10,
557 andcc_op3 = 0x11,
558 orcc_op3 = 0x12,
559 xorcc_op3 = 0x13,
560 subcc_op3 = 0x14,
561 andncc_op3 = 0x15,
562 orncc_op3 = 0x16,
563 xnorcc_op3 = 0x17,
564 addccc_op3 = 0x18,
565 umulcc_op3 = 0x1a,
566 smulcc_op3 = 0x1b,
567 subccc_op3 = 0x1c,
568 udivcc_op3 = 0x1e,
569 sdivcc_op3 = 0x1f,
570
571 taddcc_op3 = 0x20,
572 tsubcc_op3 = 0x21,
573 taddcctv_op3 = 0x22,
574 tsubcctv_op3 = 0x23,
575 mulscc_op3 = 0x24,
576 sll_op3 = 0x25,
577 sllx_op3 = 0x25,
578 srl_op3 = 0x26,
579 srlx_op3 = 0x26,
580 sra_op3 = 0x27,
581 srax_op3 = 0x27,
582 rdreg_op3 = 0x28,
583 membar_op3 = 0x28,
584
585 flushw_op3 = 0x2b,
586 movcc_op3 = 0x2c,
587 sdivx_op3 = 0x2d,
588 popc_op3 = 0x2e,
589 movr_op3 = 0x2f,
590
591 sir_op3 = 0x30,
592 wrreg_op3 = 0x30,
593 saved_op3 = 0x31,
594
595 fpop1_op3 = 0x34,
596 fpop2_op3 = 0x35,
597 impdep1_op3 = 0x36,
598 impdep2_op3 = 0x37,
599 jmpl_op3 = 0x38,
600 rett_op3 = 0x39,
601 trap_op3 = 0x3a,
602 flush_op3 = 0x3b,
603 save_op3 = 0x3c,
604 restore_op3 = 0x3d,
605 done_op3 = 0x3e,
606 retry_op3 = 0x3e,
607
608 lduw_op3 = 0x00,
609 ldub_op3 = 0x01,
610 lduh_op3 = 0x02,
611 ldd_op3 = 0x03,
612 stw_op3 = 0x04,
613 stb_op3 = 0x05,
614 sth_op3 = 0x06,
615 std_op3 = 0x07,
616 ldsw_op3 = 0x08,
617 ldsb_op3 = 0x09,
618 ldsh_op3 = 0x0a,
619 ldx_op3 = 0x0b,
620
621 ldstub_op3 = 0x0d,
622 stx_op3 = 0x0e,
623 swap_op3 = 0x0f,
624
625 lduwa_op3 = 0x10,
626 ldxa_op3 = 0x1b,
627
628 stwa_op3 = 0x14,
629 stxa_op3 = 0x1e,
630
631 ldf_op3 = 0x20,
632 ldfsr_op3 = 0x21,
633 ldqf_op3 = 0x22,
634 lddf_op3 = 0x23,
635 stf_op3 = 0x24,
636 stfsr_op3 = 0x25,
637 stqf_op3 = 0x26,
638 stdf_op3 = 0x27,
639
640 prefetch_op3 = 0x2d,
641
642
643 ldc_op3 = 0x30,
644 ldcsr_op3 = 0x31,
645 lddc_op3 = 0x33,
646 stc_op3 = 0x34,
647 stcsr_op3 = 0x35,
648 stdcq_op3 = 0x36,
649 stdc_op3 = 0x37,
650
651 casa_op3 = 0x3c,
652 casxa_op3 = 0x3e,
653
654 alt_bit_op3 = 0x10,
655 cc_bit_op3 = 0x10
656 };
657
658 enum opfs {
659 // selected opfs
660 fmovs_opf = 0x01,
661 fmovd_opf = 0x02,
662
663 fnegs_opf = 0x05,
664 fnegd_opf = 0x06,
665
666 fadds_opf = 0x41,
667 faddd_opf = 0x42,
668 fsubs_opf = 0x45,
669 fsubd_opf = 0x46,
670
671 fmuls_opf = 0x49,
672 fmuld_opf = 0x4a,
673 fdivs_opf = 0x4d,
674 fdivd_opf = 0x4e,
675
676 fcmps_opf = 0x51,
677 fcmpd_opf = 0x52,
678
679 fstox_opf = 0x81,
680 fdtox_opf = 0x82,
681 fxtos_opf = 0x84,
682 fxtod_opf = 0x88,
683 fitos_opf = 0xc4,
684 fdtos_opf = 0xc6,
685 fitod_opf = 0xc8,
686 fstod_opf = 0xc9,
687 fstoi_opf = 0xd1,
688 fdtoi_opf = 0xd2
689 };
690
691 enum RCondition { rc_z = 1, rc_lez = 2, rc_lz = 3, rc_nz = 5, rc_gz = 6, rc_gez = 7 };
692
693 enum Condition {
694 // for FBfcc & FBPfcc instruction
695 f_never = 0,
696 f_notEqual = 1,
697 f_notZero = 1,
698 f_lessOrGreater = 2,
699 f_unorderedOrLess = 3,
700 f_less = 4,
701 f_unorderedOrGreater = 5,
702 f_greater = 6,
703 f_unordered = 7,
704 f_always = 8,
705 f_equal = 9,
706 f_zero = 9,
707 f_unorderedOrEqual = 10,
708 f_greaterOrEqual = 11,
709 f_unorderedOrGreaterOrEqual = 12,
710 f_lessOrEqual = 13,
711 f_unorderedOrLessOrEqual = 14,
712 f_ordered = 15,
713
714 // V8 coproc, pp 123 v8 manual
715
716 cp_always = 8,
717 cp_never = 0,
718 cp_3 = 7,
719 cp_2 = 6,
720 cp_2or3 = 5,
721 cp_1 = 4,
722 cp_1or3 = 3,
723 cp_1or2 = 2,
724 cp_1or2or3 = 1,
725 cp_0 = 9,
726 cp_0or3 = 10,
727 cp_0or2 = 11,
728 cp_0or2or3 = 12,
729 cp_0or1 = 13,
730 cp_0or1or3 = 14,
731 cp_0or1or2 = 15,
732
733
734 // for integers
735
736 never = 0,
737 equal = 1,
738 zero = 1,
739 lessEqual = 2,
740 less = 3,
741 lessEqualUnsigned = 4,
742 lessUnsigned = 5,
743 carrySet = 5,
744 negative = 6,
745 overflowSet = 7,
746 always = 8,
747 notEqual = 9,
748 notZero = 9,
749 greater = 10,
750 greaterEqual = 11,
751 greaterUnsigned = 12,
752 greaterEqualUnsigned = 13,
753 carryClear = 13,
754 positive = 14,
755 overflowClear = 15
756 };
757
758 enum CC {
759 icc = 0, xcc = 2,
760 // ptr_cc is the correct condition code for a pointer or intptr_t:
761 ptr_cc = NOT_LP64(icc) LP64_ONLY(xcc),
762 fcc0 = 0, fcc1 = 1, fcc2 = 2, fcc3 = 3
763 };
764
765 enum PrefetchFcn {
766 severalReads = 0, oneRead = 1, severalWritesAndPossiblyReads = 2, oneWrite = 3, page = 4
767 };
768
769 public:
770 // Helper functions for groups of instructions
771
772 enum Predict { pt = 1, pn = 0 }; // pt = predict taken
773
774 enum Membar_mask_bits { // page 184, v9
775 StoreStore = 1 << 3,
776 LoadStore = 1 << 2,
777 StoreLoad = 1 << 1,
778 LoadLoad = 1 << 0,
779
780 Sync = 1 << 6,
781 MemIssue = 1 << 5,
782 Lookaside = 1 << 4
783 };
784
785 // test if x is within signed immediate range for nbits
786 static bool is_simm(int x, int nbits) { return -( 1 << nbits-1 ) <= x && x < ( 1 << nbits-1 ); }
787
788 // test if -4096 <= x <= 4095
789 static bool is_simm13(int x) { return is_simm(x, 13); }
790
791 enum ASIs { // page 72, v9
792 ASI_PRIMARY = 0x80,
793 ASI_PRIMARY_LITTLE = 0x88
794 // add more from book as needed
795 };
796
797 protected:
798 // helpers
799
800 // x is supposed to fit in a field "nbits" wide
801 // and be sign-extended. Check the range.
802
803 static void assert_signed_range(intptr_t x, int nbits) {
804 assert( nbits == 32
805 || -(1 << nbits-1) <= x && x < ( 1 << nbits-1),
806 "value out of range");
807 }
808
809 static void assert_signed_word_disp_range(intptr_t x, int nbits) {
810 assert( (x & 3) == 0, "not word aligned");
811 assert_signed_range(x, nbits + 2);
812 }
813
814 static void assert_unsigned_const(int x, int nbits) {
815 assert( juint(x) < juint(1 << nbits), "unsigned constant out of range");
816 }
817
818 // fields: note bits numbered from LSB = 0,
819 // fields known by inclusive bit range
820
821 static int fmask(juint hi_bit, juint lo_bit) {
822 assert( hi_bit >= lo_bit && 0 <= lo_bit && hi_bit < 32, "bad bits");
823 return (1 << ( hi_bit-lo_bit + 1 )) - 1;
824 }
825
826 // inverse of u_field
827
828 static int inv_u_field(int x, int hi_bit, int lo_bit) {
829 juint r = juint(x) >> lo_bit;
830 r &= fmask( hi_bit, lo_bit);
831 return int(r);
832 }
833
834
835 // signed version: extract from field and sign-extend
836
837 static int inv_s_field(int x, int hi_bit, int lo_bit) {
838 int sign_shift = 31 - hi_bit;
839 return inv_u_field( ((x << sign_shift) >> sign_shift), hi_bit, lo_bit);
840 }
841
842 // given a field that ranges from hi_bit to lo_bit (inclusive,
843 // LSB = 0), and an unsigned value for the field,
844 // shift it into the field
845
846 #ifdef ASSERT
847 static int u_field(int x, int hi_bit, int lo_bit) {
848 assert( ( x & ~fmask(hi_bit, lo_bit)) == 0,
849 "value out of range");
850 int r = x << lo_bit;
851 assert( inv_u_field(r, hi_bit, lo_bit) == x, "just checking");
852 return r;
853 }
854 #else
855 // make sure this is inlined as it will reduce code size significantly
856 #define u_field(x, hi_bit, lo_bit) ((x) << (lo_bit))
857 #endif
858
859 static int inv_op( int x ) { return inv_u_field(x, 31, 30); }
860 static int inv_op2( int x ) { return inv_u_field(x, 24, 22); }
861 static int inv_op3( int x ) { return inv_u_field(x, 24, 19); }
862 static int inv_cond( int x ){ return inv_u_field(x, 28, 25); }
863
864 static bool inv_immed( int x ) { return (x & Assembler::immed(true)) != 0; }
865
866 static Register inv_rd( int x ) { return as_Register(inv_u_field(x, 29, 25)); }
867 static Register inv_rs1( int x ) { return as_Register(inv_u_field(x, 18, 14)); }
868 static Register inv_rs2( int x ) { return as_Register(inv_u_field(x, 4, 0)); }
869
870 static int op( int x) { return u_field(x, 31, 30); }
871 static int rd( Register r) { return u_field(r->encoding(), 29, 25); }
872 static int fcn( int x) { return u_field(x, 29, 25); }
873 static int op3( int x) { return u_field(x, 24, 19); }
874 static int rs1( Register r) { return u_field(r->encoding(), 18, 14); }
875 static int rs2( Register r) { return u_field(r->encoding(), 4, 0); }
876 static int annul( bool a) { return u_field(a ? 1 : 0, 29, 29); }
877 static int cond( int x) { return u_field(x, 28, 25); }
878 static int cond_mov( int x) { return u_field(x, 17, 14); }
879 static int rcond( RCondition x) { return u_field(x, 12, 10); }
880 static int op2( int x) { return u_field(x, 24, 22); }
881 static int predict( bool p) { return u_field(p ? 1 : 0, 19, 19); }
882 static int branchcc( CC fcca) { return u_field(fcca, 21, 20); }
883 static int cmpcc( CC fcca) { return u_field(fcca, 26, 25); }
884 static int imm_asi( int x) { return u_field(x, 12, 5); }
885 static int immed( bool i) { return u_field(i ? 1 : 0, 13, 13); }
886 static int opf_low6( int w) { return u_field(w, 10, 5); }
887 static int opf_low5( int w) { return u_field(w, 9, 5); }
888 static int trapcc( CC cc) { return u_field(cc, 12, 11); }
889 static int sx( int i) { return u_field(i, 12, 12); } // shift x=1 means 64-bit
890 static int opf( int x) { return u_field(x, 13, 5); }
891
892 static int opf_cc( CC c, bool useFloat ) { return u_field((useFloat ? 0 : 4) + c, 13, 11); }
893 static int mov_cc( CC c, bool useFloat ) { return u_field(useFloat ? 0 : 1, 18, 18) | u_field(c, 12, 11); }
894
895 static int fd( FloatRegister r, FloatRegisterImpl::Width fwa) { return u_field(r->encoding(fwa), 29, 25); };
896 static int fs1(FloatRegister r, FloatRegisterImpl::Width fwa) { return u_field(r->encoding(fwa), 18, 14); };
897 static int fs2(FloatRegister r, FloatRegisterImpl::Width fwa) { return u_field(r->encoding(fwa), 4, 0); };
898
899 // some float instructions use this encoding on the op3 field
900 static int alt_op3(int op, FloatRegisterImpl::Width w) {
901 int r;
902 switch(w) {
903 case FloatRegisterImpl::S: r = op + 0; break;
904 case FloatRegisterImpl::D: r = op + 3; break;
905 case FloatRegisterImpl::Q: r = op + 2; break;
906 default: ShouldNotReachHere(); break;
907 }
908 return op3(r);
909 }
910
911
912 // compute inverse of simm
913 static int inv_simm(int x, int nbits) {
914 return (int)(x << (32 - nbits)) >> (32 - nbits);
915 }
916
917 static int inv_simm13( int x ) { return inv_simm(x, 13); }
918
919 // signed immediate, in low bits, nbits long
920 static int simm(int x, int nbits) {
921 assert_signed_range(x, nbits);
922 return x & (( 1 << nbits ) - 1);
923 }
924
925 // compute inverse of wdisp16
926 static intptr_t inv_wdisp16(int x, intptr_t pos) {
927 int lo = x & (( 1 << 14 ) - 1);
928 int hi = (x >> 20) & 3;
929 if (hi >= 2) hi |= ~1;
930 return (((hi << 14) | lo) << 2) + pos;
931 }
932
933 // word offset, 14 bits at LSend, 2 bits at B21, B20
934 static int wdisp16(intptr_t x, intptr_t off) {
935 intptr_t xx = x - off;
936 assert_signed_word_disp_range(xx, 16);
937 int r = (xx >> 2) & ((1 << 14) - 1)
938 | ( ( (xx>>(2+14)) & 3 ) << 20 );
939 assert( inv_wdisp16(r, off) == x, "inverse is not inverse");
940 return r;
941 }
942
943
944 // word displacement in low-order nbits bits
945
946 static intptr_t inv_wdisp( int x, intptr_t pos, int nbits ) {
947 int pre_sign_extend = x & (( 1 << nbits ) - 1);
948 int r = pre_sign_extend >= ( 1 << (nbits-1) )
949 ? pre_sign_extend | ~(( 1 << nbits ) - 1)
950 : pre_sign_extend;
951 return (r << 2) + pos;
952 }
953
954 static int wdisp( intptr_t x, intptr_t off, int nbits ) {
955 intptr_t xx = x - off;
956 assert_signed_word_disp_range(xx, nbits);
957 int r = (xx >> 2) & (( 1 << nbits ) - 1);
958 assert( inv_wdisp( r, off, nbits ) == x, "inverse not inverse");
959 return r;
960 }
961
962
963 // Extract the top 32 bits in a 64 bit word
964 static int32_t hi32( int64_t x ) {
965 int32_t r = int32_t( (uint64_t)x >> 32 );
966 return r;
967 }
968
969 // given a sethi instruction, extract the constant, left-justified
970 static int inv_hi22( int x ) {
971 return x << 10;
972 }
973
974 // create an imm22 field, given a 32-bit left-justified constant
975 static int hi22( int x ) {
976 int r = int( juint(x) >> 10 );
977 assert( (r & ~((1 << 22) - 1)) == 0, "just checkin'");
978 return r;
979 }
980
981 // create a low10 __value__ (not a field) for a given a 32-bit constant
982 static int low10( int x ) {
983 return x & ((1 << 10) - 1);
984 }
985
986 // instruction only in v9
987 static void v9_only() { assert( VM_Version::v9_instructions_work(), "This instruction only works on SPARC V9"); }
988
989 // instruction only in v8
990 static void v8_only() { assert( VM_Version::v8_instructions_work(), "This instruction only works on SPARC V8"); }
991
992 // instruction deprecated in v9
993 static void v9_dep() { } // do nothing for now
994
995 // some float instructions only exist for single prec. on v8
996 static void v8_s_only(FloatRegisterImpl::Width w) { if (w != FloatRegisterImpl::S) v9_only(); }
997
998 // v8 has no CC field
999 static void v8_no_cc(CC cc) { if (cc) v9_only(); }
1000
1001 protected:
1002 // Simple delay-slot scheme:
1003 // In order to check the programmer, the assembler keeps track of deley slots.
1004 // It forbids CTIs in delay slots (conservative, but should be OK).
1005 // Also, when putting an instruction into a delay slot, you must say
1006 // asm->delayed()->add(...), in order to check that you don't omit
1007 // delay-slot instructions.
1008 // To implement this, we use a simple FSA
1009
1010 #ifdef ASSERT
1011 #define CHECK_DELAY
1012 #endif
1013 #ifdef CHECK_DELAY
1014 enum Delay_state { no_delay, at_delay_slot, filling_delay_slot } delay_state;
1015 #endif
1016
1017 public:
1018 // Tells assembler next instruction must NOT be in delay slot.
1019 // Use at start of multinstruction macros.
1020 void assert_not_delayed() {
1021 // This is a separate overloading to avoid creation of string constants
1022 // in non-asserted code--with some compilers this pollutes the object code.
1023 #ifdef CHECK_DELAY
1024 assert_not_delayed("next instruction should not be a delay slot");
1025 #endif
1026 }
1027 void assert_not_delayed(const char* msg) {
1028 #ifdef CHECK_DELAY
1029 assert_msg ( delay_state == no_delay, msg);
1030 #endif
1031 }
1032
1033 protected:
1034 // Delay slot helpers
1035 // cti is called when emitting control-transfer instruction,
1036 // BEFORE doing the emitting.
1037 // Only effective when assertion-checking is enabled.
1038 void cti() {
1039 #ifdef CHECK_DELAY
1040 assert_not_delayed("cti should not be in delay slot");
1041 #endif
1042 }
1043
1044 // called when emitting cti with a delay slot, AFTER emitting
1045 void has_delay_slot() {
1046 #ifdef CHECK_DELAY
1047 assert_not_delayed("just checking");
1048 delay_state = at_delay_slot;
1049 #endif
1050 }
1051
1052 public:
1053 // Tells assembler you know that next instruction is delayed
1054 Assembler* delayed() {
1055 #ifdef CHECK_DELAY
1056 assert ( delay_state == at_delay_slot, "delayed instruction is not in delay slot");
1057 delay_state = filling_delay_slot;
1058 #endif
1059 return this;
1060 }
1061
1062 void flush() {
1063 #ifdef CHECK_DELAY
1064 assert ( delay_state == no_delay, "ending code with a delay slot");
1065 #endif
1066 AbstractAssembler::flush();
1067 }
1068
1069 inline void emit_long(int); // shadows AbstractAssembler::emit_long
1070 inline void emit_data(int x) { emit_long(x); }
1071 inline void emit_data(int, RelocationHolder const&);
1072 inline void emit_data(int, relocInfo::relocType rtype);
1073 // helper for above fcns
1074 inline void check_delay();
1075
1076
1077 public:
1078 // instructions, refer to page numbers in the SPARC Architecture Manual, V9
1079
1080 // pp 135 (addc was addx in v8)
1081
1082 inline void add( Register s1, Register s2, Register d );
1083 inline void add( Register s1, int simm13a, Register d, relocInfo::relocType rtype = relocInfo::none);
1084 inline void add( Register s1, int simm13a, Register d, RelocationHolder const& rspec);
1085 inline void add( const Address& a, Register d, int offset = 0);
1086
1087 void addcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(add_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
1088 void addcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(add_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1089 void addc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(addc_op3 ) | rs1(s1) | rs2(s2) ); }
1090 void addc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(addc_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1091 void addccc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(addc_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
1092 void addccc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(addc_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1093
1094 // pp 136
1095
1096 inline void bpr( RCondition c, bool a, Predict p, Register s1, address d, relocInfo::relocType rt = relocInfo::none );
1097 inline void bpr( RCondition c, bool a, Predict p, Register s1, Label& L);
1098
1099 protected: // use MacroAssembler::br instead
1100
1101 // pp 138
1102
1103 inline void fb( Condition c, bool a, address d, relocInfo::relocType rt = relocInfo::none );
1104 inline void fb( Condition c, bool a, Label& L );
1105
1106 // pp 141
1107
1108 inline void fbp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt = relocInfo::none );
1109 inline void fbp( Condition c, bool a, CC cc, Predict p, Label& L );
1110
1111 public:
1112
1113 // pp 144
1114
1115 inline void br( Condition c, bool a, address d, relocInfo::relocType rt = relocInfo::none );
1116 inline void br( Condition c, bool a, Label& L );
1117
1118 // pp 146
1119
1120 inline void bp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt = relocInfo::none );
1121 inline void bp( Condition c, bool a, CC cc, Predict p, Label& L );
1122
1123 // pp 121 (V8)
1124
1125 inline void cb( Condition c, bool a, address d, relocInfo::relocType rt = relocInfo::none );
1126 inline void cb( Condition c, bool a, Label& L );
1127
1128 // pp 149
1129
1130 inline void call( address d, relocInfo::relocType rt = relocInfo::runtime_call_type );
1131 inline void call( Label& L, relocInfo::relocType rt = relocInfo::runtime_call_type );
1132
1133 // pp 150
1134
1135 // These instructions compare the contents of s2 with the contents of
1136 // memory at address in s1. If the values are equal, the contents of memory
1137 // at address s1 is swapped with the data in d. If the values are not equal,
1138 // the the contents of memory at s1 is loaded into d, without the swap.
1139
1140 void casa( Register s1, Register s2, Register d, int ia = -1 ) { v9_only(); emit_long( op(ldst_op) | rd(d) | op3(casa_op3 ) | rs1(s1) | (ia == -1 ? immed(true) : imm_asi(ia)) | rs2(s2)); }
1141 void casxa( Register s1, Register s2, Register d, int ia = -1 ) { v9_only(); emit_long( op(ldst_op) | rd(d) | op3(casxa_op3) | rs1(s1) | (ia == -1 ? immed(true) : imm_asi(ia)) | rs2(s2)); }
1142
1143 // pp 152
1144
1145 void udiv( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(udiv_op3 ) | rs1(s1) | rs2(s2)); }
1146 void udiv( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(udiv_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1147 void sdiv( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sdiv_op3 ) | rs1(s1) | rs2(s2)); }
1148 void sdiv( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sdiv_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1149 void udivcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(udiv_op3 | cc_bit_op3) | rs1(s1) | rs2(s2)); }
1150 void udivcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(udiv_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1151 void sdivcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sdiv_op3 | cc_bit_op3) | rs1(s1) | rs2(s2)); }
1152 void sdivcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sdiv_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1153
1154 // pp 155
1155
1156 void done() { v9_only(); cti(); emit_long( op(arith_op) | fcn(0) | op3(done_op3) ); }
1157 void retry() { v9_only(); cti(); emit_long( op(arith_op) | fcn(1) | op3(retry_op3) ); }
1158
1159 // pp 156
1160
1161 void fadd( FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d ) { emit_long( op(arith_op) | fd(d, w) | op3(fpop1_op3) | fs1(s1, w) | opf(0x40 + w) | fs2(s2, w)); }
1162 void fsub( FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d ) { emit_long( op(arith_op) | fd(d, w) | op3(fpop1_op3) | fs1(s1, w) | opf(0x44 + w) | fs2(s2, w)); }
1163
1164 // pp 157
1165
1166 void fcmp( FloatRegisterImpl::Width w, CC cc, FloatRegister s1, FloatRegister s2) { v8_no_cc(cc); emit_long( op(arith_op) | cmpcc(cc) | op3(fpop2_op3) | fs1(s1, w) | opf(0x50 + w) | fs2(s2, w)); }
1167 void fcmpe( FloatRegisterImpl::Width w, CC cc, FloatRegister s1, FloatRegister s2) { v8_no_cc(cc); emit_long( op(arith_op) | cmpcc(cc) | op3(fpop2_op3) | fs1(s1, w) | opf(0x54 + w) | fs2(s2, w)); }
1168
1169 // pp 159
1170
1171 void ftox( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { v9_only(); emit_long( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x80 + w) | fs2(s, w)); }
1172 void ftoi( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { emit_long( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0xd0 + w) | fs2(s, w)); }
1173
1174 // pp 160
1175
1176 void ftof( FloatRegisterImpl::Width sw, FloatRegisterImpl::Width dw, FloatRegister s, FloatRegister d ) { emit_long( op(arith_op) | fd(d, dw) | op3(fpop1_op3) | opf(0xc0 + sw + dw*4) | fs2(s, sw)); }
1177
1178 // pp 161
1179
1180 void fxtof( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { v9_only(); emit_long( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x80 + w*4) | fs2(s, w)); }
1181 void fitof( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { emit_long( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0xc0 + w*4) | fs2(s, w)); }
1182
1183 // pp 162
1184
1185 void fmov( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { v8_s_only(w); emit_long( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x00 + w) | fs2(s, w)); }
1186
1187 void fneg( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { v8_s_only(w); emit_long( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x04 + w) | fs2(s, w)); }
1188
1189 // page 144 sparc v8 architecture (double prec works on v8 if the source and destination registers are the same). fnegs is the only instruction available
1190 // on v8 to do negation of single, double and quad precision floats.
1191
1192 void fneg( FloatRegisterImpl::Width w, FloatRegister sd ) { if (VM_Version::v9_instructions_work()) emit_long( op(arith_op) | fd(sd, w) | op3(fpop1_op3) | opf(0x04 + w) | fs2(sd, w)); else emit_long( op(arith_op) | fd(sd, w) | op3(fpop1_op3) | opf(0x05) | fs2(sd, w)); }
1193
1194 void fabs( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { v8_s_only(w); emit_long( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x08 + w) | fs2(s, w)); }
1195
1196 // page 144 sparc v8 architecture (double prec works on v8 if the source and destination registers are the same). fabss is the only instruction available
1197 // on v8 to do abs operation on single/double/quad precision floats.
1198
1199 void fabs( FloatRegisterImpl::Width w, FloatRegister sd ) { if (VM_Version::v9_instructions_work()) emit_long( op(arith_op) | fd(sd, w) | op3(fpop1_op3) | opf(0x08 + w) | fs2(sd, w)); else emit_long( op(arith_op) | fd(sd, w) | op3(fpop1_op3) | opf(0x09) | fs2(sd, w)); }
1200
1201 // pp 163
1202
1203 void fmul( FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d ) { emit_long( op(arith_op) | fd(d, w) | op3(fpop1_op3) | fs1(s1, w) | opf(0x48 + w) | fs2(s2, w)); }
1204 void fmul( FloatRegisterImpl::Width sw, FloatRegisterImpl::Width dw, FloatRegister s1, FloatRegister s2, FloatRegister d ) { emit_long( op(arith_op) | fd(d, dw) | op3(fpop1_op3) | fs1(s1, sw) | opf(0x60 + sw + dw*4) | fs2(s2, sw)); }
1205 void fdiv( FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d ) { emit_long( op(arith_op) | fd(d, w) | op3(fpop1_op3) | fs1(s1, w) | opf(0x4c + w) | fs2(s2, w)); }
1206
1207 // pp 164
1208
1209 void fsqrt( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { emit_long( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x28 + w) | fs2(s, w)); }
1210
1211 // pp 165
1212
1213 inline void flush( Register s1, Register s2 );
1214 inline void flush( Register s1, int simm13a);
1215
1216 // pp 167
1217
1218 void flushw() { v9_only(); emit_long( op(arith_op) | op3(flushw_op3) ); }
1219
1220 // pp 168
1221
1222 void illtrap( int const22a) { if (const22a != 0) v9_only(); emit_long( op(branch_op) | u_field(const22a, 21, 0) ); }
1223 // v8 unimp == illtrap(0)
1224
1225 // pp 169
1226
1227 void impdep1( int id1, int const19a ) { v9_only(); emit_long( op(arith_op) | fcn(id1) | op3(impdep1_op3) | u_field(const19a, 18, 0)); }
1228 void impdep2( int id1, int const19a ) { v9_only(); emit_long( op(arith_op) | fcn(id1) | op3(impdep2_op3) | u_field(const19a, 18, 0)); }
1229
1230 // pp 149 (v8)
1231
1232 void cpop1( int opc, int cr1, int cr2, int crd ) { v8_only(); emit_long( op(arith_op) | fcn(crd) | op3(impdep1_op3) | u_field(cr1, 18, 14) | opf(opc) | u_field(cr2, 4, 0)); }
1233 void cpop2( int opc, int cr1, int cr2, int crd ) { v8_only(); emit_long( op(arith_op) | fcn(crd) | op3(impdep2_op3) | u_field(cr1, 18, 14) | opf(opc) | u_field(cr2, 4, 0)); }
1234
1235 // pp 170
1236
1237 void jmpl( Register s1, Register s2, Register d );
1238 void jmpl( Register s1, int simm13a, Register d, RelocationHolder const& rspec = RelocationHolder() );
1239
1240 inline void jmpl( Address& a, Register d, int offset = 0);
1241
1242 // 171
1243
1244 inline void ldf( FloatRegisterImpl::Width w, Register s1, Register s2, FloatRegister d );
1245 inline void ldf( FloatRegisterImpl::Width w, Register s1, int simm13a, FloatRegister d );
1246
1247 inline void ldf( FloatRegisterImpl::Width w, const Address& a, FloatRegister d, int offset = 0);
1248
1249
1250 inline void ldfsr( Register s1, Register s2 );
1251 inline void ldfsr( Register s1, int simm13a);
1252 inline void ldxfsr( Register s1, Register s2 );
1253 inline void ldxfsr( Register s1, int simm13a);
1254
1255 // pp 94 (v8)
1256
1257 inline void ldc( Register s1, Register s2, int crd );
1258 inline void ldc( Register s1, int simm13a, int crd);
1259 inline void lddc( Register s1, Register s2, int crd );
1260 inline void lddc( Register s1, int simm13a, int crd);
1261 inline void ldcsr( Register s1, Register s2, int crd );
1262 inline void ldcsr( Register s1, int simm13a, int crd);
1263
1264
1265 // 173
1266
1267 void ldfa( FloatRegisterImpl::Width w, Register s1, Register s2, int ia, FloatRegister d ) { v9_only(); emit_long( op(ldst_op) | fd(d, w) | alt_op3(ldf_op3 | alt_bit_op3, w) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1268 void ldfa( FloatRegisterImpl::Width w, Register s1, int simm13a, FloatRegister d ) { v9_only(); emit_long( op(ldst_op) | fd(d, w) | alt_op3(ldf_op3 | alt_bit_op3, w) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1269
1270 // pp 175, lduw is ld on v8
1271
1272 inline void ldsb( Register s1, Register s2, Register d );
1273 inline void ldsb( Register s1, int simm13a, Register d);
1274 inline void ldsh( Register s1, Register s2, Register d );
1275 inline void ldsh( Register s1, int simm13a, Register d);
1276 inline void ldsw( Register s1, Register s2, Register d );
1277 inline void ldsw( Register s1, int simm13a, Register d);
1278 inline void ldub( Register s1, Register s2, Register d );
1279 inline void ldub( Register s1, int simm13a, Register d);
1280 inline void lduh( Register s1, Register s2, Register d );
1281 inline void lduh( Register s1, int simm13a, Register d);
1282 inline void lduw( Register s1, Register s2, Register d );
1283 inline void lduw( Register s1, int simm13a, Register d);
1284 inline void ldx( Register s1, Register s2, Register d );
1285 inline void ldx( Register s1, int simm13a, Register d);
1286 inline void ld( Register s1, Register s2, Register d );
1287 inline void ld( Register s1, int simm13a, Register d);
1288 inline void ldd( Register s1, Register s2, Register d );
1289 inline void ldd( Register s1, int simm13a, Register d);
1290
1291 inline void ldsb( const Address& a, Register d, int offset = 0 );
1292 inline void ldsh( const Address& a, Register d, int offset = 0 );
1293 inline void ldsw( const Address& a, Register d, int offset = 0 );
1294 inline void ldub( const Address& a, Register d, int offset = 0 );
1295 inline void lduh( const Address& a, Register d, int offset = 0 );
1296 inline void lduw( const Address& a, Register d, int offset = 0 );
1297 inline void ldx( const Address& a, Register d, int offset = 0 );
1298 inline void ld( const Address& a, Register d, int offset = 0 );
1299 inline void ldd( const Address& a, Register d, int offset = 0 );
1300
1301 // pp 177
1302
1303 void ldsba( Register s1, Register s2, int ia, Register d ) { emit_long( op(ldst_op) | rd(d) | op3(ldsb_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1304 void ldsba( Register s1, int simm13a, Register d ) { emit_long( op(ldst_op) | rd(d) | op3(ldsb_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1305 void ldsha( Register s1, Register s2, int ia, Register d ) { emit_long( op(ldst_op) | rd(d) | op3(ldsh_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1306 void ldsha( Register s1, int simm13a, Register d ) { emit_long( op(ldst_op) | rd(d) | op3(ldsh_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1307 void ldswa( Register s1, Register s2, int ia, Register d ) { v9_only(); emit_long( op(ldst_op) | rd(d) | op3(ldsw_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1308 void ldswa( Register s1, int simm13a, Register d ) { v9_only(); emit_long( op(ldst_op) | rd(d) | op3(ldsw_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1309 void lduba( Register s1, Register s2, int ia, Register d ) { emit_long( op(ldst_op) | rd(d) | op3(ldub_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1310 void lduba( Register s1, int simm13a, Register d ) { emit_long( op(ldst_op) | rd(d) | op3(ldub_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1311 void lduha( Register s1, Register s2, int ia, Register d ) { emit_long( op(ldst_op) | rd(d) | op3(lduh_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1312 void lduha( Register s1, int simm13a, Register d ) { emit_long( op(ldst_op) | rd(d) | op3(lduh_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1313 void lduwa( Register s1, Register s2, int ia, Register d ) { emit_long( op(ldst_op) | rd(d) | op3(lduw_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1314 void lduwa( Register s1, int simm13a, Register d ) { emit_long( op(ldst_op) | rd(d) | op3(lduw_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1315 void ldxa( Register s1, Register s2, int ia, Register d ) { v9_only(); emit_long( op(ldst_op) | rd(d) | op3(ldx_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1316 void ldxa( Register s1, int simm13a, Register d ) { v9_only(); emit_long( op(ldst_op) | rd(d) | op3(ldx_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1317 void ldda( Register s1, Register s2, int ia, Register d ) { v9_dep(); emit_long( op(ldst_op) | rd(d) | op3(ldd_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1318 void ldda( Register s1, int simm13a, Register d ) { v9_dep(); emit_long( op(ldst_op) | rd(d) | op3(ldd_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1319
1320 // pp 179
1321
1322 inline void ldstub( Register s1, Register s2, Register d );
1323 inline void ldstub( Register s1, int simm13a, Register d);
1324
1325 // pp 180
1326
1327 void ldstuba( Register s1, Register s2, int ia, Register d ) { emit_long( op(ldst_op) | rd(d) | op3(ldstub_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1328 void ldstuba( Register s1, int simm13a, Register d ) { emit_long( op(ldst_op) | rd(d) | op3(ldstub_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1329
1330 // pp 181
1331
1332 void and3( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(and_op3 ) | rs1(s1) | rs2(s2) ); }
1333 void and3( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(and_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1334 void andcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(and_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
1335 void andcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(and_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1336 void andn( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(andn_op3 ) | rs1(s1) | rs2(s2) ); }
1337 void andn( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(andn_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1338 void andncc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(andn_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
1339 void andncc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(andn_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1340 void or3( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(or_op3 ) | rs1(s1) | rs2(s2) ); }
1341 void or3( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(or_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1342 void orcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(or_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
1343 void orcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(or_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1344 void orn( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(orn_op3) | rs1(s1) | rs2(s2) ); }
1345 void orn( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(orn_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1346 void orncc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(orn_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
1347 void orncc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(orn_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1348 void xor3( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(xor_op3 ) | rs1(s1) | rs2(s2) ); }
1349 void xor3( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(xor_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1350 void xorcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(xor_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
1351 void xorcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(xor_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1352 void xnor( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(xnor_op3 ) | rs1(s1) | rs2(s2) ); }
1353 void xnor( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(xnor_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1354 void xnorcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(xnor_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
1355 void xnorcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(xnor_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1356
1357 // pp 183
1358
1359 void membar( Membar_mask_bits const7a ) { v9_only(); emit_long( op(arith_op) | op3(membar_op3) | rs1(O7) | immed(true) | u_field( int(const7a), 6, 0)); }
1360
1361 // pp 185
1362
1363 void fmov( FloatRegisterImpl::Width w, Condition c, bool floatCC, CC cca, FloatRegister s2, FloatRegister d ) { v9_only(); emit_long( op(arith_op) | fd(d, w) | op3(fpop2_op3) | cond_mov(c) | opf_cc(cca, floatCC) | opf_low6(w) | fs2(s2, w)); }
1364
1365 // pp 189
1366
1367 void fmov( FloatRegisterImpl::Width w, RCondition c, Register s1, FloatRegister s2, FloatRegister d ) { v9_only(); emit_long( op(arith_op) | fd(d, w) | op3(fpop2_op3) | rs1(s1) | rcond(c) | opf_low5(4 + w) | fs2(s2, w)); }
1368
1369 // pp 191
1370
1371 void movcc( Condition c, bool floatCC, CC cca, Register s2, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(movcc_op3) | mov_cc(cca, floatCC) | cond_mov(c) | rs2(s2) ); }
1372 void movcc( Condition c, bool floatCC, CC cca, int simm11a, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(movcc_op3) | mov_cc(cca, floatCC) | cond_mov(c) | immed(true) | simm(simm11a, 11) ); }
1373
1374 // pp 195
1375
1376 void movr( RCondition c, Register s1, Register s2, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(movr_op3) | rs1(s1) | rcond(c) | rs2(s2) ); }
1377 void movr( RCondition c, Register s1, int simm10a, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(movr_op3) | rs1(s1) | rcond(c) | immed(true) | simm(simm10a, 10) ); }
1378
1379 // pp 196
1380
1381 void mulx( Register s1, Register s2, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(mulx_op3 ) | rs1(s1) | rs2(s2) ); }
1382 void mulx( Register s1, int simm13a, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(mulx_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1383 void sdivx( Register s1, Register s2, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(sdivx_op3) | rs1(s1) | rs2(s2) ); }
1384 void sdivx( Register s1, int simm13a, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(sdivx_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1385 void udivx( Register s1, Register s2, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(udivx_op3) | rs1(s1) | rs2(s2) ); }
1386 void udivx( Register s1, int simm13a, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(udivx_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1387
1388 // pp 197
1389
1390 void umul( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(umul_op3 ) | rs1(s1) | rs2(s2) ); }
1391 void umul( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(umul_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1392 void smul( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(smul_op3 ) | rs1(s1) | rs2(s2) ); }
1393 void smul( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(smul_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1394 void umulcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(umul_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
1395 void umulcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(umul_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1396 void smulcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(smul_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
1397 void smulcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(smul_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1398
1399 // pp 199
1400
1401 void mulscc( Register s1, Register s2, Register d ) { v9_dep(); emit_long( op(arith_op) | rd(d) | op3(mulscc_op3) | rs1(s1) | rs2(s2) ); }
1402 void mulscc( Register s1, int simm13a, Register d ) { v9_dep(); emit_long( op(arith_op) | rd(d) | op3(mulscc_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1403
1404 // pp 201
1405
1406 void nop() { emit_long( op(branch_op) | op2(sethi_op2) ); }
1407
1408
1409 // pp 202
1410
1411 void popc( Register s, Register d) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(popc_op3) | rs2(s)); }
1412 void popc( int simm13a, Register d) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(popc_op3) | immed(true) | simm(simm13a, 13)); }
1413
1414 // pp 203
1415
1416 void prefetch( Register s1, Register s2, PrefetchFcn f);
1417 void prefetch( Register s1, int simm13a, PrefetchFcn f);
1418 void prefetcha( Register s1, Register s2, int ia, PrefetchFcn f ) { v9_only(); emit_long( op(ldst_op) | fcn(f) | op3(prefetch_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1419 void prefetcha( Register s1, int simm13a, PrefetchFcn f ) { v9_only(); emit_long( op(ldst_op) | fcn(f) | op3(prefetch_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1420
1421 inline void prefetch(const Address& a, PrefetchFcn F, int offset = 0);
1422
1423 // pp 208
1424
1425 // not implementing read privileged register
1426
1427 inline void rdy( Register d) { v9_dep(); emit_long( op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(0, 18, 14)); }
1428 inline void rdccr( Register d) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(2, 18, 14)); }
1429 inline void rdasi( Register d) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(3, 18, 14)); }
1430 inline void rdtick( Register d) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(4, 18, 14)); } // Spoon!
1431 inline void rdpc( Register d) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(5, 18, 14)); }
1432 inline void rdfprs( Register d) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(6, 18, 14)); }
1433
1434 // pp 213
1435
1436 inline void rett( Register s1, Register s2);
1437 inline void rett( Register s1, int simm13a, relocInfo::relocType rt = relocInfo::none);
1438
1439 // pp 214
1440
1441 void save( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(save_op3) | rs1(s1) | rs2(s2) ); }
1442 void save( Register s1, int simm13a, Register d ) {
1443 // make sure frame is at least large enough for the register save area
1444 assert(-simm13a >= 16 * wordSize, "frame too small");
1445 emit_long( op(arith_op) | rd(d) | op3(save_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) );
1446 }
1447
1448 void restore( Register s1 = G0, Register s2 = G0, Register d = G0 ) { emit_long( op(arith_op) | rd(d) | op3(restore_op3) | rs1(s1) | rs2(s2) ); }
1449 void restore( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(restore_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1450
1451 // pp 216
1452
1453 void saved() { v9_only(); emit_long( op(arith_op) | fcn(0) | op3(saved_op3)); }
1454 void restored() { v9_only(); emit_long( op(arith_op) | fcn(1) | op3(saved_op3)); }
1455
1456 // pp 217
1457
1458 inline void sethi( int imm22a, Register d, RelocationHolder const& rspec = RelocationHolder() );
1459 // pp 218
1460
1461 void sll( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sll_op3) | rs1(s1) | sx(0) | rs2(s2) ); }
1462 void sll( Register s1, int imm5a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sll_op3) | rs1(s1) | sx(0) | immed(true) | u_field(imm5a, 4, 0) ); }
1463 void srl( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(srl_op3) | rs1(s1) | sx(0) | rs2(s2) ); }
1464 void srl( Register s1, int imm5a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(srl_op3) | rs1(s1) | sx(0) | immed(true) | u_field(imm5a, 4, 0) ); }
1465 void sra( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sra_op3) | rs1(s1) | sx(0) | rs2(s2) ); }
1466 void sra( Register s1, int imm5a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sra_op3) | rs1(s1) | sx(0) | immed(true) | u_field(imm5a, 4, 0) ); }
1467
1468 void sllx( Register s1, Register s2, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(sll_op3) | rs1(s1) | sx(1) | rs2(s2) ); }
1469 void sllx( Register s1, int imm6a, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(sll_op3) | rs1(s1) | sx(1) | immed(true) | u_field(imm6a, 5, 0) ); }
1470 void srlx( Register s1, Register s2, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(srl_op3) | rs1(s1) | sx(1) | rs2(s2) ); }
1471 void srlx( Register s1, int imm6a, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(srl_op3) | rs1(s1) | sx(1) | immed(true) | u_field(imm6a, 5, 0) ); }
1472 void srax( Register s1, Register s2, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(sra_op3) | rs1(s1) | sx(1) | rs2(s2) ); }
1473 void srax( Register s1, int imm6a, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(sra_op3) | rs1(s1) | sx(1) | immed(true) | u_field(imm6a, 5, 0) ); }
1474
1475 // pp 220
1476
1477 void sir( int simm13a ) { emit_long( op(arith_op) | fcn(15) | op3(sir_op3) | immed(true) | simm(simm13a, 13)); }
1478
1479 // pp 221
1480
1481 void stbar() { emit_long( op(arith_op) | op3(membar_op3) | u_field(15, 18, 14)); }
1482
1483 // pp 222
1484
1485 inline void stf( FloatRegisterImpl::Width w, FloatRegister d, Register s1, Register s2 );
1486 inline void stf( FloatRegisterImpl::Width w, FloatRegister d, Register s1, int simm13a);
1487 inline void stf( FloatRegisterImpl::Width w, FloatRegister d, const Address& a, int offset = 0);
1488
1489 inline void stfsr( Register s1, Register s2 );
1490 inline void stfsr( Register s1, int simm13a);
1491 inline void stxfsr( Register s1, Register s2 );
1492 inline void stxfsr( Register s1, int simm13a);
1493
1494 // pp 224
1495
1496 void stfa( FloatRegisterImpl::Width w, FloatRegister d, Register s1, Register s2, int ia ) { v9_only(); emit_long( op(ldst_op) | fd(d, w) | alt_op3(stf_op3 | alt_bit_op3, w) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1497 void stfa( FloatRegisterImpl::Width w, FloatRegister d, Register s1, int simm13a ) { v9_only(); emit_long( op(ldst_op) | fd(d, w) | alt_op3(stf_op3 | alt_bit_op3, w) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1498
1499 // p 226
1500
1501 inline void stb( Register d, Register s1, Register s2 );
1502 inline void stb( Register d, Register s1, int simm13a);
1503 inline void sth( Register d, Register s1, Register s2 );
1504 inline void sth( Register d, Register s1, int simm13a);
1505 inline void stw( Register d, Register s1, Register s2 );
1506 inline void stw( Register d, Register s1, int simm13a);
1507 inline void st( Register d, Register s1, Register s2 );
1508 inline void st( Register d, Register s1, int simm13a);
1509 inline void stx( Register d, Register s1, Register s2 );
1510 inline void stx( Register d, Register s1, int simm13a);
1511 inline void std( Register d, Register s1, Register s2 );
1512 inline void std( Register d, Register s1, int simm13a);
1513
1514 inline void stb( Register d, const Address& a, int offset = 0 );
1515 inline void sth( Register d, const Address& a, int offset = 0 );
1516 inline void stw( Register d, const Address& a, int offset = 0 );
1517 inline void stx( Register d, const Address& a, int offset = 0 );
1518 inline void st( Register d, const Address& a, int offset = 0 );
1519 inline void std( Register d, const Address& a, int offset = 0 );
1520
1521 // pp 177
1522
1523 void stba( Register d, Register s1, Register s2, int ia ) { emit_long( op(ldst_op) | rd(d) | op3(stb_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1524 void stba( Register d, Register s1, int simm13a ) { emit_long( op(ldst_op) | rd(d) | op3(stb_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1525 void stha( Register d, Register s1, Register s2, int ia ) { emit_long( op(ldst_op) | rd(d) | op3(sth_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1526 void stha( Register d, Register s1, int simm13a ) { emit_long( op(ldst_op) | rd(d) | op3(sth_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1527 void stwa( Register d, Register s1, Register s2, int ia ) { emit_long( op(ldst_op) | rd(d) | op3(stw_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1528 void stwa( Register d, Register s1, int simm13a ) { emit_long( op(ldst_op) | rd(d) | op3(stw_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1529 void stxa( Register d, Register s1, Register s2, int ia ) { v9_only(); emit_long( op(ldst_op) | rd(d) | op3(stx_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1530 void stxa( Register d, Register s1, int simm13a ) { v9_only(); emit_long( op(ldst_op) | rd(d) | op3(stx_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1531 void stda( Register d, Register s1, Register s2, int ia ) { emit_long( op(ldst_op) | rd(d) | op3(std_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1532 void stda( Register d, Register s1, int simm13a ) { emit_long( op(ldst_op) | rd(d) | op3(std_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1533
1534 // pp 97 (v8)
1535
1536 inline void stc( int crd, Register s1, Register s2 );
1537 inline void stc( int crd, Register s1, int simm13a);
1538 inline void stdc( int crd, Register s1, Register s2 );
1539 inline void stdc( int crd, Register s1, int simm13a);
1540 inline void stcsr( int crd, Register s1, Register s2 );
1541 inline void stcsr( int crd, Register s1, int simm13a);
1542 inline void stdcq( int crd, Register s1, Register s2 );
1543 inline void stdcq( int crd, Register s1, int simm13a);
1544
1545 // pp 230
1546
1547 void sub( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sub_op3 ) | rs1(s1) | rs2(s2) ); }
1548 void sub( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sub_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1549 void subcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sub_op3 | cc_bit_op3 ) | rs1(s1) | rs2(s2) ); }
1550 void subcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sub_op3 | cc_bit_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1551 void subc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(subc_op3 ) | rs1(s1) | rs2(s2) ); }
1552 void subc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(subc_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1553 void subccc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(subc_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
1554 void subccc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(subc_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1555
1556 // pp 231
1557
1558 inline void swap( Register s1, Register s2, Register d );
1559 inline void swap( Register s1, int simm13a, Register d);
1560 inline void swap( Address& a, Register d, int offset = 0 );
1561
1562 // pp 232
1563
1564 void swapa( Register s1, Register s2, int ia, Register d ) { v9_dep(); emit_long( op(ldst_op) | rd(d) | op3(swap_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); }
1565 void swapa( Register s1, int simm13a, Register d ) { v9_dep(); emit_long( op(ldst_op) | rd(d) | op3(swap_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1566
1567 // pp 234, note op in book is wrong, see pp 268
1568
1569 void taddcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(taddcc_op3 ) | rs1(s1) | rs2(s2) ); }
1570 void taddcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(taddcc_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1571 void taddcctv( Register s1, Register s2, Register d ) { v9_dep(); emit_long( op(arith_op) | rd(d) | op3(taddcctv_op3) | rs1(s1) | rs2(s2) ); }
1572 void taddcctv( Register s1, int simm13a, Register d ) { v9_dep(); emit_long( op(arith_op) | rd(d) | op3(taddcctv_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1573
1574 // pp 235
1575
1576 void tsubcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(tsubcc_op3 ) | rs1(s1) | rs2(s2) ); }
1577 void tsubcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(tsubcc_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1578 void tsubcctv( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(tsubcctv_op3) | rs1(s1) | rs2(s2) ); }
1579 void tsubcctv( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(tsubcctv_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
1580
1581 // pp 237
1582
1583 void trap( Condition c, CC cc, Register s1, Register s2 ) { v8_no_cc(cc); emit_long( op(arith_op) | cond(c) | op3(trap_op3) | rs1(s1) | trapcc(cc) | rs2(s2)); }
1584 void trap( Condition c, CC cc, Register s1, int trapa ) { v8_no_cc(cc); emit_long( op(arith_op) | cond(c) | op3(trap_op3) | rs1(s1) | trapcc(cc) | immed(true) | u_field(trapa, 6, 0)); }
1585 // simple uncond. trap
1586 void trap( int trapa ) { trap( always, icc, G0, trapa ); }
1587
1588 // pp 239 omit write priv register for now
1589
1590 inline void wry( Register d) { v9_dep(); emit_long( op(arith_op) | rs1(d) | op3(wrreg_op3) | u_field(0, 29, 25)); }
1591 inline void wrccr(Register s) { v9_only(); emit_long( op(arith_op) | rs1(s) | op3(wrreg_op3) | u_field(2, 29, 25)); }
1592 inline void wrccr(Register s, int simm13a) { v9_only(); emit_long( op(arith_op) |
1593 rs1(s) |
1594 op3(wrreg_op3) |
1595 u_field(2, 29, 25) |
1596 u_field(1, 13, 13) |
1597 simm(simm13a, 13)); }
1598 inline void wrasi( Register d) { v9_only(); emit_long( op(arith_op) | rs1(d) | op3(wrreg_op3) | u_field(3, 29, 25)); }
1599 inline void wrfprs( Register d) { v9_only(); emit_long( op(arith_op) | rs1(d) | op3(wrreg_op3) | u_field(6, 29, 25)); }
1600
1601 // For a given register condition, return the appropriate condition code
1602 // Condition (the one you would use to get the same effect after "tst" on
1603 // the target register.)
1604 Assembler::Condition reg_cond_to_cc_cond(RCondition in);
1605
1606
1607 // Creation
1608 Assembler(CodeBuffer* code) : AbstractAssembler(code) {
1609 #ifdef CHECK_DELAY
1610 delay_state = no_delay;
1611 #endif
1612 }
1613
1614 // Testing
1615 #ifndef PRODUCT
1616 void test_v9();
1617 void test_v8_onlys();
1618 #endif
1619 };
1620
1621
1622 class RegistersForDebugging : public StackObj {
1623 public:
1624 intptr_t i[8], l[8], o[8], g[8];
1625 float f[32];
1626 double d[32];
1627
1628 void print(outputStream* s);
1629
1630 static int i_offset(int j) { return offset_of(RegistersForDebugging, i[j]); }
1631 static int l_offset(int j) { return offset_of(RegistersForDebugging, l[j]); }
1632 static int o_offset(int j) { return offset_of(RegistersForDebugging, o[j]); }
1633 static int g_offset(int j) { return offset_of(RegistersForDebugging, g[j]); }
1634 static int f_offset(int j) { return offset_of(RegistersForDebugging, f[j]); }
1635 static int d_offset(int j) { return offset_of(RegistersForDebugging, d[j / 2]); }
1636
1637 // gen asm code to save regs
1638 static void save_registers(MacroAssembler* a);
1639
1640 // restore global registers in case C code disturbed them
1641 static void restore_registers(MacroAssembler* a, Register r);
1642
1643
1644 };
1645
1646
1647 // MacroAssembler extends Assembler by a few frequently used macros.
1648 //
1649 // Most of the standard SPARC synthetic ops are defined here.
1650 // Instructions for which a 'better' code sequence exists depending
1651 // on arguments should also go in here.
1652
1653 #define JMP2(r1, r2) jmp(r1, r2, __FILE__, __LINE__)
1654 #define JMP(r1, off) jmp(r1, off, __FILE__, __LINE__)
1655 #define JUMP(a, off) jump(a, off, __FILE__, __LINE__)
1656 #define JUMPL(a, d, off) jumpl(a, d, off, __FILE__, __LINE__)
1657
1658
1659 class MacroAssembler: public Assembler {
1660 protected:
1661 // Support for VM calls
1662 // This is the base routine called by the different versions of call_VM_leaf. The interpreter
1663 // may customize this version by overriding it for its purposes (e.g., to save/restore
1664 // additional registers when doing a VM call).
1665 #ifdef CC_INTERP
1666 #define VIRTUAL
1667 #else
1668 #define VIRTUAL virtual
1669 #endif
1670
1671 VIRTUAL void call_VM_leaf_base(Register thread_cache, address entry_point, int number_of_arguments);
1672
1673 //
1674 // It is imperative that all calls into the VM are handled via the call_VM macros.
1675 // They make sure that the stack linkage is setup correctly. call_VM's correspond
1676 // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points.
1677 //
1678 // This is the base routine called by the different versions of call_VM. The interpreter
1679 // may customize this version by overriding it for its purposes (e.g., to save/restore
1680 // additional registers when doing a VM call).
1681 //
1682 // A non-volatile java_thread_cache register should be specified so
1683 // that the G2_thread value can be preserved across the call.
1684 // (If java_thread_cache is noreg, then a slow get_thread call
1685 // will re-initialize the G2_thread.) call_VM_base returns the register that contains the
1686 // thread.
1687 //
1688 // If no last_java_sp is specified (noreg) than SP will be used instead.
1689
1690 virtual void call_VM_base(
1691 Register oop_result, // where an oop-result ends up if any; use noreg otherwise
1692 Register java_thread_cache, // the thread if computed before ; use noreg otherwise
1693 Register last_java_sp, // to set up last_Java_frame in stubs; use noreg otherwise
1694 address entry_point, // the entry point
1695 int number_of_arguments, // the number of arguments (w/o thread) to pop after call
1696 bool check_exception=true // flag which indicates if exception should be checked
1697 );
1698
1699 // This routine should emit JVMTI PopFrame and ForceEarlyReturn handling code.
1700 // The implementation is only non-empty for the InterpreterMacroAssembler,
1701 // as only the interpreter handles and ForceEarlyReturn PopFrame requests.
1702 virtual void check_and_handle_popframe(Register scratch_reg);
1703 virtual void check_and_handle_earlyret(Register scratch_reg);
1704
1705 public:
1706 MacroAssembler(CodeBuffer* code) : Assembler(code) {}
1707
1708 // Support for NULL-checks
1709 //
1710 // Generates code that causes a NULL OS exception if the content of reg is NULL.
1711 // If the accessed location is M[reg + offset] and the offset is known, provide the
1712 // offset. No explicit code generation is needed if the offset is within a certain
1713 // range (0 <= offset <= page_size).
1714 //
1715 // %%%%%% Currently not done for SPARC
1716
1717 void null_check(Register reg, int offset = -1);
1718 static bool needs_explicit_null_check(intptr_t offset);
1719
1720 // support for delayed instructions
1721 MacroAssembler* delayed() { Assembler::delayed(); return this; }
1722
1723 // branches that use right instruction for v8 vs. v9
1724 inline void br( Condition c, bool a, Predict p, address d, relocInfo::relocType rt = relocInfo::none );
1725 inline void br( Condition c, bool a, Predict p, Label& L );
1726 inline void fb( Condition c, bool a, Predict p, address d, relocInfo::relocType rt = relocInfo::none );
1727 inline void fb( Condition c, bool a, Predict p, Label& L );
1728
1729 // compares register with zero and branches (V9 and V8 instructions)
1730 void br_zero( Condition c, bool a, Predict p, Register s1, Label& L);
1731 // Compares a pointer register with zero and branches on (not)null.
1732 // Does a test & branch on 32-bit systems and a register-branch on 64-bit.
1733 void br_null ( Register s1, bool a, Predict p, Label& L );
1734 void br_notnull( Register s1, bool a, Predict p, Label& L );
1735
1736 // These versions will do the most efficient thing on v8 and v9. Perhaps
1737 // this is what the routine above was meant to do, but it didn't (and
1738 // didn't cover both target address kinds.)
1739 void br_on_reg_cond( RCondition c, bool a, Predict p, Register s1, address d, relocInfo::relocType rt = relocInfo::none );
1740 void br_on_reg_cond( RCondition c, bool a, Predict p, Register s1, Label& L);
1741
1742 inline void bp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt = relocInfo::none );
1743 inline void bp( Condition c, bool a, CC cc, Predict p, Label& L );
1744
1745 // Branch that tests xcc in LP64 and icc in !LP64
1746 inline void brx( Condition c, bool a, Predict p, address d, relocInfo::relocType rt = relocInfo::none );
1747 inline void brx( Condition c, bool a, Predict p, Label& L );
1748
1749 // unconditional short branch
1750 inline void ba( bool a, Label& L );
1751
1752 // Branch that tests fp condition codes
1753 inline void fbp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt = relocInfo::none );
1754 inline void fbp( Condition c, bool a, CC cc, Predict p, Label& L );
1755
1756 // get PC the best way
1757 inline int get_pc( Register d );
1758
1759 // Sparc shorthands(pp 85, V8 manual, pp 289 V9 manual)
1760 inline void cmp( Register s1, Register s2 ) { subcc( s1, s2, G0 ); }
1761 inline void cmp( Register s1, int simm13a ) { subcc( s1, simm13a, G0 ); }
1762
1763 inline void jmp( Register s1, Register s2 );
1764 inline void jmp( Register s1, int simm13a, RelocationHolder const& rspec = RelocationHolder() );
1765
1766 inline void call( address d, relocInfo::relocType rt = relocInfo::runtime_call_type );
1767 inline void call( Label& L, relocInfo::relocType rt = relocInfo::runtime_call_type );
1768 inline void callr( Register s1, Register s2 );
1769 inline void callr( Register s1, int simm13a, RelocationHolder const& rspec = RelocationHolder() );
1770
1771 // Emits nothing on V8
1772 inline void iprefetch( address d, relocInfo::relocType rt = relocInfo::none );
1773 inline void iprefetch( Label& L);
1774
1775 inline void tst( Register s ) { orcc( G0, s, G0 ); }
1776
1777 #ifdef PRODUCT
1778 inline void ret( bool trace = TraceJumps ) { if (trace) {
1779 mov(I7, O7); // traceable register
1780 JMP(O7, 2 * BytesPerInstWord);
1781 } else {
1782 jmpl( I7, 2 * BytesPerInstWord, G0 );
1783 }
1784 }
1785
1786 inline void retl( bool trace = TraceJumps ) { if (trace) JMP(O7, 2 * BytesPerInstWord);
1787 else jmpl( O7, 2 * BytesPerInstWord, G0 ); }
1788 #else
1789 void ret( bool trace = TraceJumps );
1790 void retl( bool trace = TraceJumps );
1791 #endif /* PRODUCT */
1792
1793 // Required platform-specific helpers for Label::patch_instructions.
1794 // They _shadow_ the declarations in AbstractAssembler, which are undefined.
1795 void pd_patch_instruction(address branch, address target);
1796 #ifndef PRODUCT
1797 static void pd_print_patched_instruction(address branch);
1798 #endif
1799
1800 // sethi Macro handles optimizations and relocations
1801 void sethi( Address& a, bool ForceRelocatable = false );
1802 void sethi( intptr_t imm22a, Register d, bool ForceRelocatable = false, RelocationHolder const& rspec = RelocationHolder());
1803
1804 // compute the size of a sethi/set
1805 static int size_of_sethi( address a, bool worst_case = false );
1806 static int worst_case_size_of_set();
1807
1808 // set may be either setsw or setuw (high 32 bits may be zero or sign)
1809 void set( intptr_t value, Register d, RelocationHolder const& rspec = RelocationHolder() );
1810 void setsw( int value, Register d, RelocationHolder const& rspec = RelocationHolder() );
1811 void set64( jlong value, Register d, Register tmp);
1812
1813 // sign-extend 32 to 64
1814 inline void signx( Register s, Register d ) { sra( s, G0, d); }
1815 inline void signx( Register d ) { sra( d, G0, d); }
1816
1817 inline void not1( Register s, Register d ) { xnor( s, G0, d ); }
1818 inline void not1( Register d ) { xnor( d, G0, d ); }
1819
1820 inline void neg( Register s, Register d ) { sub( G0, s, d ); }
1821 inline void neg( Register d ) { sub( G0, d, d ); }
1822
1823 inline void cas( Register s1, Register s2, Register d) { casa( s1, s2, d, ASI_PRIMARY); }
1824 inline void casx( Register s1, Register s2, Register d) { casxa(s1, s2, d, ASI_PRIMARY); }
1825 // Functions for isolating 64 bit atomic swaps for LP64
1826 // cas_ptr will perform cas for 32 bit VM's and casx for 64 bit VM's
1827 inline void cas_ptr( Register s1, Register s2, Register d) {
1828 #ifdef _LP64
1829 casx( s1, s2, d );
1830 #else
1831 cas( s1, s2, d );
1832 #endif
1833 }
1834
1835 // Functions for isolating 64 bit shifts for LP64
1836 inline void sll_ptr( Register s1, Register s2, Register d );
1837 inline void sll_ptr( Register s1, int imm6a, Register d );
1838 inline void srl_ptr( Register s1, Register s2, Register d );
1839 inline void srl_ptr( Register s1, int imm6a, Register d );
1840
1841 // little-endian
1842 inline void casl( Register s1, Register s2, Register d) { casa( s1, s2, d, ASI_PRIMARY_LITTLE); }
1843 inline void casxl( Register s1, Register s2, Register d) { casxa(s1, s2, d, ASI_PRIMARY_LITTLE); }
1844
1845 inline void inc( Register d, int const13 = 1 ) { add( d, const13, d); }
1846 inline void inccc( Register d, int const13 = 1 ) { addcc( d, const13, d); }
1847
1848 inline void dec( Register d, int const13 = 1 ) { sub( d, const13, d); }
1849 inline void deccc( Register d, int const13 = 1 ) { subcc( d, const13, d); }
1850
1851 inline void btst( Register s1, Register s2 ) { andcc( s1, s2, G0 ); }
1852 inline void btst( int simm13a, Register s ) { andcc( s, simm13a, G0 ); }
1853
1854 inline void bset( Register s1, Register s2 ) { or3( s1, s2, s2 ); }
1855 inline void bset( int simm13a, Register s ) { or3( s, simm13a, s ); }
1856
1857 inline void bclr( Register s1, Register s2 ) { andn( s1, s2, s2 ); }
1858 inline void bclr( int simm13a, Register s ) { andn( s, simm13a, s ); }
1859
1860 inline void btog( Register s1, Register s2 ) { xor3( s1, s2, s2 ); }
1861 inline void btog( int simm13a, Register s ) { xor3( s, simm13a, s ); }
1862
1863 inline void clr( Register d ) { or3( G0, G0, d ); }
1864
1865 inline void clrb( Register s1, Register s2);
1866 inline void clrh( Register s1, Register s2);
1867 inline void clr( Register s1, Register s2);
1868 inline void clrx( Register s1, Register s2);
1869
1870 inline void clrb( Register s1, int simm13a);
1871 inline void clrh( Register s1, int simm13a);
1872 inline void clr( Register s1, int simm13a);
1873 inline void clrx( Register s1, int simm13a);
1874
1875 // copy & clear upper word
1876 inline void clruw( Register s, Register d ) { srl( s, G0, d); }
1877 // clear upper word
1878 inline void clruwu( Register d ) { srl( d, G0, d); }
1879
1880 // membar psuedo instruction. takes into account target memory model.
1881 inline void membar( Assembler::Membar_mask_bits const7a );
1882
1883 // returns if membar generates anything.
1884 inline bool membar_has_effect( Assembler::Membar_mask_bits const7a );
1885
1886 // mov pseudo instructions
1887 inline void mov( Register s, Register d) {
1888 if ( s != d ) or3( G0, s, d);
1889 else assert_not_delayed(); // Put something useful in the delay slot!
1890 }
1891
1892 inline void mov_or_nop( Register s, Register d) {
1893 if ( s != d ) or3( G0, s, d);
1894 else nop();
1895 }
1896
1897 inline void mov( int simm13a, Register d) { or3( G0, simm13a, d); }
1898
1899 // address pseudos: make these names unlike instruction names to avoid confusion
1900 inline void split_disp( Address& a, Register temp );
1901 inline intptr_t load_pc_address( Register reg, int bytes_to_skip );
1902 inline void load_address( Address& a, int offset = 0 );
1903 inline void load_contents( Address& a, Register d, int offset = 0 );
1904 inline void load_ptr_contents( Address& a, Register d, int offset = 0 );
1905 inline void store_contents( Register s, Address& a, int offset = 0 );
1906 inline void store_ptr_contents( Register s, Address& a, int offset = 0 );
1907 inline void jumpl_to( Address& a, Register d, int offset = 0 );
1908 inline void jump_to( Address& a, int offset = 0 );
1909
1910 // ring buffer traceable jumps
1911
1912 void jmp2( Register r1, Register r2, const char* file, int line );
1913 void jmp ( Register r1, int offset, const char* file, int line );
1914
1915 void jumpl( Address& a, Register d, int offset, const char* file, int line );
1916 void jump ( Address& a, int offset, const char* file, int line );
1917
1918
1919 // argument pseudos:
1920
1921 inline void load_argument( Argument& a, Register d );
1922 inline void store_argument( Register s, Argument& a );
1923 inline void store_ptr_argument( Register s, Argument& a );
1924 inline void store_float_argument( FloatRegister s, Argument& a );
1925 inline void store_double_argument( FloatRegister s, Argument& a );
1926 inline void store_long_argument( Register s, Argument& a );
1927
1928 // handy macros:
1929
1930 inline void round_to( Register r, int modulus ) {
1931 assert_not_delayed();
1932 inc( r, modulus - 1 );
1933 and3( r, -modulus, r );
1934 }
1935
1936 // --------------------------------------------------
1937
1938 // Functions for isolating 64 bit loads for LP64
1939 // ld_ptr will perform ld for 32 bit VM's and ldx for 64 bit VM's
1940 // st_ptr will perform st for 32 bit VM's and stx for 64 bit VM's
1941 inline void ld_ptr( Register s1, Register s2, Register d );
1942 inline void ld_ptr( Register s1, int simm13a, Register d);
1943 inline void ld_ptr( const Address& a, Register d, int offset = 0 );
1944 inline void st_ptr( Register d, Register s1, Register s2 );
1945 inline void st_ptr( Register d, Register s1, int simm13a);
1946 inline void st_ptr( Register d, const Address& a, int offset = 0 );
1947
1948 // ld_long will perform ld for 32 bit VM's and ldx for 64 bit VM's
1949 // st_long will perform st for 32 bit VM's and stx for 64 bit VM's
1950 inline void ld_long( Register s1, Register s2, Register d );
1951 inline void ld_long( Register s1, int simm13a, Register d );
1952 inline void ld_long( const Address& a, Register d, int offset = 0 );
1953 inline void st_long( Register d, Register s1, Register s2 );
1954 inline void st_long( Register d, Register s1, int simm13a );
1955 inline void st_long( Register d, const Address& a, int offset = 0 );
1956
1957 // --------------------------------------------------
1958
1959 public:
1960 // traps as per trap.h (SPARC ABI?)
1961
1962 void breakpoint_trap();
1963 void breakpoint_trap(Condition c, CC cc = icc);
1964 void flush_windows_trap();
1965 void clean_windows_trap();
1966 void get_psr_trap();
1967 void set_psr_trap();
1968
1969 // V8/V9 flush_windows
1970 void flush_windows();
1971
1972 // Support for serializing memory accesses between threads
1973 void serialize_memory(Register thread, Register tmp1, Register tmp2);
1974
1975 // Stack frame creation/removal
1976 void enter();
1977 void leave();
1978
1979 // V8/V9 integer multiply
1980 void mult(Register s1, Register s2, Register d);
1981 void mult(Register s1, int simm13a, Register d);
1982
1983 // V8/V9 read and write of condition codes.
1984 void read_ccr(Register d);
1985 void write_ccr(Register s);
1986
1987 // Manipulation of C++ bools
1988 // These are idioms to flag the need for care with accessing bools but on
1989 // this platform we assume byte size
1990
1991 inline void stbool( Register d, const Address& a, int offset = 0 ) { stb(d, a, offset); }
1992 inline void ldbool( const Address& a, Register d, int offset = 0 ) { ldsb( a, d, offset ); }
1993 inline void tstbool( Register s ) { tst(s); }
1994 inline void movbool( bool boolconst, Register d) { mov( (int) boolconst, d); }
1995
1996 // klass oop manipulations if compressed
1997 void load_klass(Register src_oop, Register klass);
1998 void store_klass(Register klass, Register dst_oop);
1999 void store_klass_gap(Register s, Register dst_oop);
2000
2001 // oop manipulations
2002 void load_heap_oop(const Address& s, Register d, int offset = 0);
2003 void load_heap_oop(Register s1, Register s2, Register d);
2004 void load_heap_oop(Register s1, int simm13a, Register d);
2005 void store_heap_oop(Register d, Register s1, Register s2);
2006 void store_heap_oop(Register d, Register s1, int simm13a);
2007 void store_heap_oop(Register d, const Address& a, int offset = 0);
2008
2009 void encode_heap_oop(Register src, Register dst);
2010 void encode_heap_oop(Register r) {
2011 encode_heap_oop(r, r);
2012 }
2013 void decode_heap_oop(Register src, Register dst);
2014 void decode_heap_oop(Register r) {
2015 decode_heap_oop(r, r);
2016 }
2017 void encode_heap_oop_not_null(Register r);
2018 void decode_heap_oop_not_null(Register r);
2019 void encode_heap_oop_not_null(Register src, Register dst);
2020 void decode_heap_oop_not_null(Register src, Register dst);
2021
2022 // Support for managing the JavaThread pointer (i.e.; the reference to
2023 // thread-local information).
2024 void get_thread(); // load G2_thread
2025 void verify_thread(); // verify G2_thread contents
2026 void save_thread (const Register threache); // save to cache
2027 void restore_thread(const Register thread_cache); // restore from cache
2028
2029 // Support for last Java frame (but use call_VM instead where possible)
2030 void set_last_Java_frame(Register last_java_sp, Register last_Java_pc);
2031 void reset_last_Java_frame(void);
2032
2033 // Call into the VM.
2034 // Passes the thread pointer (in O0) as a prepended argument.
2035 // Makes sure oop return values are visible to the GC.
2036 void call_VM(Register oop_result, address entry_point, int number_of_arguments = 0, bool check_exceptions = true);
2037 void call_VM(Register oop_result, address entry_point, Register arg_1, bool check_exceptions = true);
2038 void call_VM(Register oop_result, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true);
2039 void call_VM(Register oop_result, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true);
2040
2041 // these overloadings are not presently used on SPARC:
2042 void call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments = 0, bool check_exceptions = true);
2043 void call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions = true);
2044 void call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true);
2045 void call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true);
2046
2047 void call_VM_leaf(Register thread_cache, address entry_point, int number_of_arguments = 0);
2048 void call_VM_leaf(Register thread_cache, address entry_point, Register arg_1);
2049 void call_VM_leaf(Register thread_cache, address entry_point, Register arg_1, Register arg_2);
2050 void call_VM_leaf(Register thread_cache, address entry_point, Register arg_1, Register arg_2, Register arg_3);
2051
2052 void get_vm_result (Register oop_result);
2053 void get_vm_result_2(Register oop_result);
2054
2055 // vm result is currently getting hijacked to for oop preservation
2056 void set_vm_result(Register oop_result);
2057
2058 // if call_VM_base was called with check_exceptions=false, then call
2059 // check_and_forward_exception to handle exceptions when it is safe
2060 void check_and_forward_exception(Register scratch_reg);
2061
2062 private:
2063 // For V8
2064 void read_ccr_trap(Register ccr_save);
2065 void write_ccr_trap(Register ccr_save1, Register scratch1, Register scratch2);
2066
2067 #ifdef ASSERT
2068 // For V8 debugging. Uses V8 instruction sequence and checks
2069 // result with V9 insturctions rdccr and wrccr.
2070 // Uses Gscatch and Gscatch2
2071 void read_ccr_v8_assert(Register ccr_save);
2072 void write_ccr_v8_assert(Register ccr_save);
2073 #endif // ASSERT
2074
2075 public:
2076
2077 // Write to card table for - register is destroyed afterwards.
2078 void card_table_write(jbyte* byte_map_base, Register tmp, Register obj);
2079
2080 void card_write_barrier_post(Register store_addr, Register new_val, Register tmp);
2081
2082 #ifndef SERIALGC
2083 // Array store and offset
2084 void g1_write_barrier_pre(Register obj, Register index, int offset, Register tmp, bool preserve_o_regs);
2085
2086 void g1_write_barrier_post(Register store_addr, Register new_val, Register tmp);
2087
2088 // May do filtering, depending on the boolean arguments.
2089 void g1_card_table_write(jbyte* byte_map_base,
2090 Register tmp, Register obj, Register new_val,
2091 bool region_filter, bool null_filter);
2092 #endif // SERIALGC
2093
2094 // pushes double TOS element of FPU stack on CPU stack; pops from FPU stack
2095 void push_fTOS();
2096
2097 // pops double TOS element from CPU stack and pushes on FPU stack
2098 void pop_fTOS();
2099
2100 void empty_FPU_stack();
2101
2102 void push_IU_state();
2103 void pop_IU_state();
2104
2105 void push_FPU_state();
2106 void pop_FPU_state();
2107
2108 void push_CPU_state();
2109 void pop_CPU_state();
2110
2111 // if heap base register is used - reinit it with the correct value
2112 void reinit_heapbase();
2113
2114 // Debugging
2115 void _verify_oop(Register reg, const char * msg, const char * file, int line);
2116 void _verify_oop_addr(Address addr, const char * msg, const char * file, int line);
2117
2118 #define verify_oop(reg) _verify_oop(reg, "broken oop " #reg, __FILE__, __LINE__)
2119 #define verify_oop_addr(addr) _verify_oop_addr(addr, "broken oop addr ", __FILE__, __LINE__)
2120
2121 // only if +VerifyOops
2122 void verify_FPU(int stack_depth, const char* s = "illegal FPU state");
2123 // only if +VerifyFPU
2124 void stop(const char* msg); // prints msg, dumps registers and stops execution
2125 void warn(const char* msg); // prints msg, but don't stop
2126 void untested(const char* what = "");
2127 void unimplemented(const char* what = "") { char* b = new char[1024]; sprintf(b, "unimplemented: %s", what); stop(b); }
2128 void should_not_reach_here() { stop("should not reach here"); }
2129 void print_CPU_state();
2130
2131 // oops in code
2132 Address allocate_oop_address( jobject obj, Register d ); // allocate_index
2133 Address constant_oop_address( jobject obj, Register d ); // find_index
2134 inline void set_oop ( jobject obj, Register d ); // uses allocate_oop_address
2135 inline void set_oop_constant( jobject obj, Register d ); // uses constant_oop_address
2136 inline void set_oop ( Address obj_addr ); // same as load_address
2137
2138 void set_narrow_oop( jobject obj, Register d );
2139
2140 // nop padding
2141 void align(int modulus);
2142
2143 // declare a safepoint
2144 void safepoint();
2145
2146 // factor out part of stop into subroutine to save space
2147 void stop_subroutine();
2148 // factor out part of verify_oop into subroutine to save space
2149 void verify_oop_subroutine();
2150
2151 // side-door communication with signalHandler in os_solaris.cpp
2152 static address _verify_oop_implicit_branch[3];
2153
2154 #ifndef PRODUCT
2155 static void test();
2156 #endif
2157
2158 // convert an incoming arglist to varargs format; put the pointer in d
2159 void set_varargs( Argument a, Register d );
2160
2161 int total_frame_size_in_bytes(int extraWords);
2162
2163 // used when extraWords known statically
2164 void save_frame(int extraWords);
2165 void save_frame_c1(int size_in_bytes);
2166 // make a frame, and simultaneously pass up one or two register value
2167 // into the new register window
2168 void save_frame_and_mov(int extraWords, Register s1, Register d1, Register s2 = Register(), Register d2 = Register());
2169
2170 // give no. (outgoing) params, calc # of words will need on frame
2171 void calc_mem_param_words(Register Rparam_words, Register Rresult);
2172
2173 // used to calculate frame size dynamically
2174 // result is in bytes and must be negated for save inst
2175 void calc_frame_size(Register extraWords, Register resultReg);
2176
2177 // calc and also save
2178 void calc_frame_size_and_save(Register extraWords, Register resultReg);
2179
2180 static void debug(char* msg, RegistersForDebugging* outWindow);
2181
2182 // implementations of bytecodes used by both interpreter and compiler
2183
2184 void lcmp( Register Ra_hi, Register Ra_low,
2185 Register Rb_hi, Register Rb_low,
2186 Register Rresult);
2187
2188 void lneg( Register Rhi, Register Rlow );
2189
2190 void lshl( Register Rin_high, Register Rin_low, Register Rcount,
2191 Register Rout_high, Register Rout_low, Register Rtemp );
2192
2193 void lshr( Register Rin_high, Register Rin_low, Register Rcount,
2194 Register Rout_high, Register Rout_low, Register Rtemp );
2195
2196 void lushr( Register Rin_high, Register Rin_low, Register Rcount,
2197 Register Rout_high, Register Rout_low, Register Rtemp );
2198
2199 #ifdef _LP64
2200 void lcmp( Register Ra, Register Rb, Register Rresult);
2201 #endif
2202
2203 void float_cmp( bool is_float, int unordered_result,
2204 FloatRegister Fa, FloatRegister Fb,
2205 Register Rresult);
2206
2207 void fneg( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d);
2208 void fneg( FloatRegisterImpl::Width w, FloatRegister sd ) { Assembler::fneg(w, sd); }
2209 void fmov( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d);
2210 void fabs( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d);
2211
2212 void save_all_globals_into_locals();
2213 void restore_globals_from_locals();
2214
2215 void casx_under_lock(Register top_ptr_reg, Register top_reg, Register ptr_reg,
2216 address lock_addr=0, bool use_call_vm=false);
2217 void cas_under_lock(Register top_ptr_reg, Register top_reg, Register ptr_reg,
2218 address lock_addr=0, bool use_call_vm=false);
2219 void casn (Register addr_reg, Register cmp_reg, Register set_reg) ;
2220
2221 // These set the icc condition code to equal if the lock succeeded
2222 // and notEqual if it failed and requires a slow case
2223 void compiler_lock_object(Register Roop, Register Rmark, Register Rbox,
2224 Register Rscratch,
2225 BiasedLockingCounters* counters = NULL,
2226 bool try_bias = UseBiasedLocking);
2227 void compiler_unlock_object(Register Roop, Register Rmark, Register Rbox,
2228 Register Rscratch,
2229 bool try_bias = UseBiasedLocking);
2230
2231 // Biased locking support
2232 // Upon entry, lock_reg must point to the lock record on the stack,
2233 // obj_reg must contain the target object, and mark_reg must contain
2234 // the target object's header.
2235 // Destroys mark_reg if an attempt is made to bias an anonymously
2236 // biased lock. In this case a failure will go either to the slow
2237 // case or fall through with the notEqual condition code set with
2238 // the expectation that the slow case in the runtime will be called.
2239 // In the fall-through case where the CAS-based lock is done,
2240 // mark_reg is not destroyed.
2241 void biased_locking_enter(Register obj_reg, Register mark_reg, Register temp_reg,
2242 Label& done, Label* slow_case = NULL,
2243 BiasedLockingCounters* counters = NULL);
2244 // Upon entry, the base register of mark_addr must contain the oop.
2245 // Destroys temp_reg.
2246
2247 // If allow_delay_slot_filling is set to true, the next instruction
2248 // emitted after this one will go in an annulled delay slot if the
2249 // biased locking exit case failed.
2250 void biased_locking_exit(Address mark_addr, Register temp_reg, Label& done, bool allow_delay_slot_filling = false);
2251
2252 // allocation
2253 void eden_allocate(
2254 Register obj, // result: pointer to object after successful allocation
2255 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
2256 int con_size_in_bytes, // object size in bytes if known at compile time
2257 Register t1, // temp register
2258 Register t2, // temp register
2259 Label& slow_case // continuation point if fast allocation fails
2260 );
2261 void tlab_allocate(
2262 Register obj, // result: pointer to object after successful allocation
2263 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
2264 int con_size_in_bytes, // object size in bytes if known at compile time
2265 Register t1, // temp register
2266 Label& slow_case // continuation point if fast allocation fails
2267 );
2268 void tlab_refill(Label& retry_tlab, Label& try_eden, Label& slow_case);
2269
2270 // Stack overflow checking
2271
2272 // Note: this clobbers G3_scratch
2273 void bang_stack_with_offset(int offset) {
2274 // stack grows down, caller passes positive offset
2275 assert(offset > 0, "must bang with negative offset");
2276 set((-offset)+STACK_BIAS, G3_scratch);
2277 st(G0, SP, G3_scratch);
2278 }
2279
2280 // Writes to stack successive pages until offset reached to check for
2281 // stack overflow + shadow pages. Clobbers tsp and scratch registers.
2282 void bang_stack_size(Register Rsize, Register Rtsp, Register Rscratch);
2283
2284 void verify_tlab();
2285
2286 Condition negate_condition(Condition cond);
2287
2288 // Helper functions for statistics gathering.
2289 // Conditionally (non-atomically) increments passed counter address, preserving condition codes.
2290 void cond_inc(Condition cond, address counter_addr, Register Rtemp1, Register Rtemp2);
2291 // Unconditional increment.
2292 void inc_counter(address counter_addr, Register Rtemp1, Register Rtemp2);
2293
2294 #undef VIRTUAL
2295
2296 };
2297
2298 /**
2299 * class SkipIfEqual:
2300 *
2301 * Instantiating this class will result in assembly code being output that will
2302 * jump around any code emitted between the creation of the instance and it's
2303 * automatic destruction at the end of a scope block, depending on the value of
2304 * the flag passed to the constructor, which will be checked at run-time.
2305 */
2306 class SkipIfEqual : public StackObj {
2307 private:
2308 MacroAssembler* _masm;
2309 Label _label;
2310
2311 public:
2312 // 'temp' is a temp register that this object can use (and trash)
2313 SkipIfEqual(MacroAssembler*, Register temp,
2314 const bool* flag_addr, Assembler::Condition condition);
2315 ~SkipIfEqual();
2316 };
2317
2318 #ifdef ASSERT
2319 // On RISC, there's no benefit to verifying instruction boundaries.
2320 inline bool AbstractAssembler::pd_check_instruction_mark() { return false; }
2321 #endif