1 #ifdef USE_PRAGMA_IDENT_HDR 2 #pragma ident "@(#)nativeInst_x86.hpp 1.81 07/09/17 09:28:55 JVM" 3 #endif 4 /* 5 * Copyright 1997-2006 Sun Microsystems, Inc. All Rights Reserved. 6 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 7 * 8 * This code is free software; you can redistribute it and/or modify it 9 * under the terms of the GNU General Public License version 2 only, as 10 * published by the Free Software Foundation. 11 * 12 * This code is distributed in the hope that it will be useful, but WITHOUT 13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 15 * version 2 for more details (a copy is included in the LICENSE file that 16 * accompanied this code). 17 * 18 * You should have received a copy of the GNU General Public License version 19 * 2 along with this work; if not, write to the Free Software Foundation, 20 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 21 * 22 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 23 * CA 95054 USA or visit www.sun.com if you need additional information or 24 * have any questions. 25 * 26 */ 27 28 // We have interfaces for the following instructions: 29 // - NativeInstruction 30 // - - NativeCall 31 // - - NativeMovConstReg 32 // - - NativeMovConstRegPatching 33 // - - NativeMovRegMem 34 // - - NativeMovRegMemPatching 35 // - - NativeJump 36 // - - NativeIllegalOpCode 37 // - - NativeGeneralJump 38 // - - NativeReturn 39 // - - NativeReturnX (return with argument) 40 // - - NativePushConst 41 // - - NativeTstRegMem 42 43 // The base class for different kinds of native instruction abstractions. 44 // Provides the primitive operations to manipulate code relative to this. 45 46 class NativeInstruction VALUE_OBJ_CLASS_SPEC { 47 friend class Relocation; 48 49 public: 50 enum Intel_specific_constants { 51 nop_instruction_code = 0x90, 52 nop_instruction_size = 1 53 }; 54 55 bool is_nop() { return ubyte_at(0) == nop_instruction_code; } 56 inline bool is_call(); 57 inline bool is_illegal(); 58 inline bool is_return(); 59 inline bool is_jump(); 60 inline bool is_cond_jump(); 61 inline bool is_safepoint_poll(); 62 inline bool is_mov_literal64(); 63 64 protected: 65 address addr_at(int offset) const { return address(this) + offset; } 66 67 s_char sbyte_at(int offset) const { return *(s_char*) addr_at(offset); } 68 u_char ubyte_at(int offset) const { return *(u_char*) addr_at(offset); } 69 70 jint int_at(int offset) const { return *(jint*) addr_at(offset); } 71 72 intptr_t ptr_at(int offset) const { return *(intptr_t*) addr_at(offset); } 73 74 oop oop_at (int offset) const { return *(oop*) addr_at(offset); } 75 76 77 void set_char_at(int offset, char c) { *addr_at(offset) = (u_char)c; wrote(offset); } 78 void set_int_at(int offset, jint i) { *(jint*)addr_at(offset) = i; wrote(offset); } 79 void set_ptr_at (int offset, intptr_t ptr) { *(intptr_t*) addr_at(offset) = ptr; wrote(offset); } 80 void set_oop_at (int offset, oop o) { *(oop*) addr_at(offset) = o; wrote(offset); } 81 82 // This doesn't really do anything on Intel, but it is the place where 83 // cache invalidation belongs, generically: 84 void wrote(int offset); 85 86 public: 87 88 // unit test stuff 89 static void test() {} // override for testing 90 91 inline friend NativeInstruction* nativeInstruction_at(address address); 92 }; 93 94 inline NativeInstruction* nativeInstruction_at(address address) { 95 NativeInstruction* inst = (NativeInstruction*)address; 96 #ifdef ASSERT 97 //inst->verify(); 98 #endif 99 return inst; 100 } 101 102 inline NativeCall* nativeCall_at(address address); 103 // The NativeCall is an abstraction for accessing/manipulating native call imm32/rel32off 104 // instructions (used to manipulate inline caches, primitive & dll calls, etc.). 105 106 class NativeCall: public NativeInstruction { 107 public: 108 enum Intel_specific_constants { 109 instruction_code = 0xE8, 110 instruction_size = 5, 111 instruction_offset = 0, 112 displacement_offset = 1, 113 return_address_offset = 5 114 }; 115 116 enum { cache_line_size = BytesPerWord }; // conservative estimate! 117 118 address instruction_address() const { return addr_at(instruction_offset); } 119 address next_instruction_address() const { return addr_at(return_address_offset); } 120 int displacement() const { return (jint) int_at(displacement_offset); } 121 address displacement_address() const { return addr_at(displacement_offset); } 122 address return_address() const { return addr_at(return_address_offset); } 123 address destination() const; 124 void set_destination(address dest) { 125 #ifdef AMD64 126 assert((labs((intptr_t) dest - (intptr_t) return_address()) & 127 0xFFFFFFFF00000000) == 0, 128 "must be 32bit offset"); 129 #endif // AMD64 130 set_int_at(displacement_offset, dest - return_address()); 131 } 132 void set_destination_mt_safe(address dest); 133 134 void verify_alignment() { assert((intptr_t)addr_at(displacement_offset) % BytesPerInt == 0, "must be aligned"); } 135 void verify(); 136 void print(); 137 138 // Creation 139 inline friend NativeCall* nativeCall_at(address address); 140 inline friend NativeCall* nativeCall_before(address return_address); 141 142 static bool is_call_at(address instr) { 143 return ((*instr) & 0xFF) == NativeCall::instruction_code; 144 } 145 146 static bool is_call_before(address return_address) { 147 return is_call_at(return_address - NativeCall::return_address_offset); 148 } 149 150 static bool is_call_to(address instr, address target) { 151 return nativeInstruction_at(instr)->is_call() && 152 nativeCall_at(instr)->destination() == target; 153 } 154 155 // MT-safe patching of a call instruction. 156 static void insert(address code_pos, address entry); 157 158 static void replace_mt_safe(address instr_addr, address code_buffer); 159 }; 160 161 inline NativeCall* nativeCall_at(address address) { 162 NativeCall* call = (NativeCall*)(address - NativeCall::instruction_offset); 163 #ifdef ASSERT 164 call->verify(); 165 #endif 166 return call; 167 } 168 169 inline NativeCall* nativeCall_before(address return_address) { 170 NativeCall* call = (NativeCall*)(return_address - NativeCall::return_address_offset); 171 #ifdef ASSERT 172 call->verify(); 173 #endif 174 return call; 175 } 176 177 // An interface for accessing/manipulating native mov reg, imm32 instructions. 178 // (used to manipulate inlined 32bit data dll calls, etc.) 179 class NativeMovConstReg: public NativeInstruction { 180 #ifdef AMD64 181 static const bool has_rex = true; 182 static const int rex_size = 1; 183 #else 184 static const bool has_rex = false; 185 static const int rex_size = 0; 186 #endif // AMD64 187 public: 188 enum Intel_specific_constants { 189 instruction_code = 0xB8, 190 instruction_size = 1 + rex_size + wordSize, 191 instruction_offset = 0, 192 data_offset = 1 + rex_size, 193 next_instruction_offset = instruction_size, 194 register_mask = 0x07 195 }; 196 197 address instruction_address() const { return addr_at(instruction_offset); } 198 address next_instruction_address() const { return addr_at(next_instruction_offset); } 199 intptr_t data() const { return ptr_at(data_offset); } 200 void set_data(intptr_t x) { set_ptr_at(data_offset, x); } 201 202 void verify(); 203 void print(); 204 205 // unit test stuff 206 static void test() {} 207 208 // Creation 209 inline friend NativeMovConstReg* nativeMovConstReg_at(address address); 210 inline friend NativeMovConstReg* nativeMovConstReg_before(address address); 211 }; 212 213 inline NativeMovConstReg* nativeMovConstReg_at(address address) { 214 NativeMovConstReg* test = (NativeMovConstReg*)(address - NativeMovConstReg::instruction_offset); 215 #ifdef ASSERT 216 test->verify(); 217 #endif 218 return test; 219 } 220 221 inline NativeMovConstReg* nativeMovConstReg_before(address address) { 222 NativeMovConstReg* test = (NativeMovConstReg*)(address - NativeMovConstReg::instruction_size - NativeMovConstReg::instruction_offset); 223 #ifdef ASSERT 224 test->verify(); 225 #endif 226 return test; 227 } 228 229 class NativeMovConstRegPatching: public NativeMovConstReg { 230 private: 231 friend NativeMovConstRegPatching* nativeMovConstRegPatching_at(address address) { 232 NativeMovConstRegPatching* test = (NativeMovConstRegPatching*)(address - instruction_offset); 233 #ifdef ASSERT 234 test->verify(); 235 #endif 236 return test; 237 } 238 }; 239 240 #ifndef AMD64 241 242 // An interface for accessing/manipulating native moves of the form: 243 // mov[b/w/l] [reg + offset], reg (instruction_code_reg2mem) 244 // mov[b/w/l] reg, [reg+offset] (instruction_code_mem2reg 245 // mov[s/z]x[w/b] [reg + offset], reg 246 // fld_s [reg+offset] 247 // fld_d [reg+offset] 248 // fstp_s [reg + offset] 249 // fstp_d [reg + offset] 250 // 251 // Warning: These routines must be able to handle any instruction sequences 252 // that are generated as a result of the load/store byte,word,long 253 // macros. For example: The load_unsigned_byte instruction generates 254 // an xor reg,reg inst prior to generating the movb instruction. This 255 // class must skip the xor instruction. 256 257 class NativeMovRegMem: public NativeInstruction { 258 public: 259 enum Intel_specific_constants { 260 instruction_code_xor = 0x33, 261 instruction_extended_prefix = 0x0F, 262 instruction_code_mem2reg_movzxb = 0xB6, 263 instruction_code_mem2reg_movsxb = 0xBE, 264 instruction_code_mem2reg_movzxw = 0xB7, 265 instruction_code_mem2reg_movsxw = 0xBF, 266 instruction_operandsize_prefix = 0x66, 267 instruction_code_reg2meml = 0x89, 268 instruction_code_mem2regl = 0x8b, 269 instruction_code_reg2memb = 0x88, 270 instruction_code_mem2regb = 0x8a, 271 instruction_code_float_s = 0xd9, 272 instruction_code_float_d = 0xdd, 273 instruction_code_long_volatile = 0xdf, 274 instruction_code_xmm_ss_prefix = 0xf3, 275 instruction_code_xmm_sd_prefix = 0xf2, 276 instruction_code_xmm_code = 0x0f, 277 instruction_code_xmm_load = 0x10, 278 instruction_code_xmm_store = 0x11, 279 instruction_code_xmm_lpd = 0x12, 280 281 instruction_size = 4, 282 instruction_offset = 0, 283 data_offset = 2, 284 next_instruction_offset = 4 285 }; 286 287 address instruction_address() const { 288 if (*addr_at(instruction_offset) == instruction_operandsize_prefix && 289 *addr_at(instruction_offset+1) != instruction_code_xmm_code) { 290 return addr_at(instruction_offset+1); // Not SSE instructions 291 } 292 else if (*addr_at(instruction_offset) == instruction_extended_prefix) { 293 return addr_at(instruction_offset+1); 294 } 295 else if (*addr_at(instruction_offset) == instruction_code_xor) { 296 return addr_at(instruction_offset+2); 297 } 298 else return addr_at(instruction_offset); 299 } 300 301 address next_instruction_address() const { 302 switch (*addr_at(instruction_offset)) { 303 case instruction_operandsize_prefix: 304 if (*addr_at(instruction_offset+1) == instruction_code_xmm_code) 305 return instruction_address() + instruction_size; // SSE instructions 306 case instruction_extended_prefix: 307 return instruction_address() + instruction_size + 1; 308 case instruction_code_reg2meml: 309 case instruction_code_mem2regl: 310 case instruction_code_reg2memb: 311 case instruction_code_mem2regb: 312 case instruction_code_xor: 313 return instruction_address() + instruction_size + 2; 314 default: 315 return instruction_address() + instruction_size; 316 } 317 } 318 int offset() const{ 319 if (*addr_at(instruction_offset) == instruction_operandsize_prefix && 320 *addr_at(instruction_offset+1) != instruction_code_xmm_code) { 321 return int_at(data_offset+1); // Not SSE instructions 322 } 323 else if (*addr_at(instruction_offset) == instruction_extended_prefix) { 324 return int_at(data_offset+1); 325 } 326 else if (*addr_at(instruction_offset) == instruction_code_xor || 327 *addr_at(instruction_offset) == instruction_code_xmm_ss_prefix || 328 *addr_at(instruction_offset) == instruction_code_xmm_sd_prefix || 329 *addr_at(instruction_offset) == instruction_operandsize_prefix) { 330 return int_at(data_offset+2); 331 } 332 else return int_at(data_offset); 333 } 334 335 void set_offset(int x) { 336 if (*addr_at(instruction_offset) == instruction_operandsize_prefix && 337 *addr_at(instruction_offset+1) != instruction_code_xmm_code) { 338 set_int_at(data_offset+1, x); // Not SSE instructions 339 } 340 else if (*addr_at(instruction_offset) == instruction_extended_prefix) { 341 set_int_at(data_offset+1, x); 342 } 343 else if (*addr_at(instruction_offset) == instruction_code_xor || 344 *addr_at(instruction_offset) == instruction_code_xmm_ss_prefix || 345 *addr_at(instruction_offset) == instruction_code_xmm_sd_prefix || 346 *addr_at(instruction_offset) == instruction_operandsize_prefix) { 347 set_int_at(data_offset+2, x); 348 } 349 else set_int_at(data_offset, x); 350 } 351 352 void add_offset_in_bytes(int add_offset) { set_offset ( ( offset() + add_offset ) ); } 353 void copy_instruction_to(address new_instruction_address); 354 355 void verify(); 356 void print (); 357 358 // unit test stuff 359 static void test() {} 360 361 private: 362 inline friend NativeMovRegMem* nativeMovRegMem_at (address address); 363 }; 364 365 inline NativeMovRegMem* nativeMovRegMem_at (address address) { 366 NativeMovRegMem* test = (NativeMovRegMem*)(address - NativeMovRegMem::instruction_offset); 367 #ifdef ASSERT 368 test->verify(); 369 #endif 370 return test; 371 } 372 373 class NativeMovRegMemPatching: public NativeMovRegMem { 374 private: 375 friend NativeMovRegMemPatching* nativeMovRegMemPatching_at (address address) { 376 NativeMovRegMemPatching* test = (NativeMovRegMemPatching*)(address - instruction_offset); 377 #ifdef ASSERT 378 test->verify(); 379 #endif 380 return test; 381 } 382 }; 383 384 385 386 // An interface for accessing/manipulating native leal instruction of form: 387 // leal reg, [reg + offset] 388 389 class NativeLoadAddress: public NativeMovRegMem { 390 public: 391 enum Intel_specific_constants { 392 instruction_code = 0x8D 393 }; 394 395 void verify(); 396 void print (); 397 398 // unit test stuff 399 static void test() {} 400 401 private: 402 friend NativeLoadAddress* nativeLoadAddress_at (address address) { 403 NativeLoadAddress* test = (NativeLoadAddress*)(address - instruction_offset); 404 #ifdef ASSERT 405 test->verify(); 406 #endif 407 return test; 408 } 409 }; 410 411 #endif // AMD64 412 413 // jump rel32off 414 415 class NativeJump: public NativeInstruction { 416 public: 417 enum Intel_specific_constants { 418 instruction_code = 0xe9, 419 instruction_size = 5, 420 instruction_offset = 0, 421 data_offset = 1, 422 next_instruction_offset = 5 423 }; 424 425 address instruction_address() const { return addr_at(instruction_offset); } 426 address next_instruction_address() const { return addr_at(next_instruction_offset); } 427 address jump_destination() const { 428 address dest = (int_at(data_offset)+next_instruction_address()); 429 #ifdef AMD64 // What is this about? 430 // return -1 if jump to self 431 dest = (dest == (address) this) ? (address) -1 : dest; 432 #endif // AMD64 433 return dest; 434 } 435 436 void set_jump_destination(address dest) { 437 intptr_t val = dest - next_instruction_address(); 438 #ifdef AMD64 439 if (dest == (address) -1) { // can't encode jump to -1 440 val = -5; // jump to self 441 } else { 442 assert((labs(val) & 0xFFFFFFFF00000000) == 0, 443 "must be 32bit offset"); 444 } 445 #endif // AMD64 446 set_int_at(data_offset, (jint)val); 447 } 448 449 // Creation 450 inline friend NativeJump* nativeJump_at(address address); 451 452 void verify(); 453 454 // Unit testing stuff 455 static void test() {} 456 457 // Insertion of native jump instruction 458 static void insert(address code_pos, address entry); 459 // MT-safe insertion of native jump at verified method entry 460 static void check_verified_entry_alignment(address entry, address verified_entry); 461 static void patch_verified_entry(address entry, address verified_entry, address dest); 462 }; 463 464 inline NativeJump* nativeJump_at(address address) { 465 NativeJump* jump = (NativeJump*)(address - NativeJump::instruction_offset); 466 #ifdef ASSERT 467 jump->verify(); 468 #endif 469 return jump; 470 } 471 472 // Handles all kinds of jump on Intel. Long/far, conditional/unconditional 473 class NativeGeneralJump: public NativeInstruction { 474 public: 475 enum Intel_specific_constants { 476 // Constants does not apply, since the lengths and offsets depends on the actual jump 477 // used 478 // Instruction codes: 479 // Unconditional jumps: 0xE9 (rel32off), 0xEB (rel8off) 480 // Conditional jumps: 0x0F8x (rel32off), 0x7x (rel8off) 481 unconditional_long_jump = 0xe9, 482 unconditional_short_jump = 0xeb, 483 instruction_size = 5 484 }; 485 486 address instruction_address() const { return addr_at(0); } 487 address jump_destination() const; 488 489 // Creation 490 inline friend NativeGeneralJump* nativeGeneralJump_at(address address); 491 492 // Insertion of native general jump instruction 493 static void insert_unconditional(address code_pos, address entry); 494 static void replace_mt_safe(address instr_addr, address code_buffer); 495 496 void verify(); 497 }; 498 499 inline NativeGeneralJump* nativeGeneralJump_at(address address) { 500 NativeGeneralJump* jump = (NativeGeneralJump*)(address); 501 debug_only(jump->verify();) 502 return jump; 503 } 504 505 class NativePopReg : public NativeInstruction { 506 public: 507 enum Intel_specific_constants { 508 instruction_code = 0x58, 509 instruction_size = 1, 510 instruction_offset = 0, 511 data_offset = 1, 512 next_instruction_offset = 1 513 }; 514 515 // Insert a pop instruction 516 static void insert(address code_pos, Register reg); 517 }; 518 519 520 class NativeIllegalInstruction: public NativeInstruction { 521 public: 522 enum Intel_specific_constants { 523 instruction_code = 0x0B0F, // Real byte order is: 0x0F, 0x0B 524 instruction_size = 2, 525 instruction_offset = 0, 526 next_instruction_offset = 2 527 }; 528 529 // Insert illegal opcode as specific address 530 static void insert(address code_pos); 531 }; 532 533 // return instruction that does not pop values of the stack 534 class NativeReturn: public NativeInstruction { 535 public: 536 enum Intel_specific_constants { 537 instruction_code = 0xC3, 538 instruction_size = 1, 539 instruction_offset = 0, 540 next_instruction_offset = 1 541 }; 542 }; 543 544 // return instruction that does pop values of the stack 545 class NativeReturnX: public NativeInstruction { 546 public: 547 enum Intel_specific_constants { 548 instruction_code = 0xC2, 549 instruction_size = 2, 550 instruction_offset = 0, 551 next_instruction_offset = 2 552 }; 553 }; 554 555 // Simple test vs memory 556 class NativeTstRegMem: public NativeInstruction { 557 public: 558 enum Intel_specific_constants { 559 instruction_code_memXregl = 0x85 560 }; 561 }; 562 563 inline bool NativeInstruction::is_illegal() { return (short)int_at(0) == (short)NativeIllegalInstruction::instruction_code; } 564 inline bool NativeInstruction::is_call() { return ubyte_at(0) == NativeCall::instruction_code; } 565 inline bool NativeInstruction::is_return() { return ubyte_at(0) == NativeReturn::instruction_code || 566 ubyte_at(0) == NativeReturnX::instruction_code; } 567 inline bool NativeInstruction::is_jump() { return ubyte_at(0) == NativeJump::instruction_code || 568 ubyte_at(0) == 0xEB; /* short jump */ } 569 inline bool NativeInstruction::is_cond_jump() { return (int_at(0) & 0xF0FF) == 0x800F /* long jump */ || 570 (ubyte_at(0) & 0xF0) == 0x70; /* short jump */ } 571 inline bool NativeInstruction::is_safepoint_poll() { 572 #ifdef AMD64 573 return ubyte_at(0) == NativeTstRegMem::instruction_code_memXregl && 574 ubyte_at(1) == 0x05 && // 00 rax 101 575 ((intptr_t) addr_at(6)) + int_at(2) == (intptr_t) os::get_polling_page(); 576 #else 577 return ( ubyte_at(0) == NativeMovRegMem::instruction_code_mem2regl || 578 ubyte_at(0) == NativeTstRegMem::instruction_code_memXregl ) && 579 (ubyte_at(1)&0xC7) == 0x05 && /* Mod R/M == disp32 */ 580 (os::is_poll_address((address)int_at(2))); 581 #endif // AMD64 582 } 583 584 inline bool NativeInstruction::is_mov_literal64() { 585 #ifdef AMD64 586 return ((ubyte_at(0) == Assembler::REX_W || ubyte_at(0) == Assembler::REX_WB) && 587 (ubyte_at(1) & (0xff ^ NativeMovConstReg::register_mask)) == 0xB8); 588 #else 589 return false; 590 #endif // AMD64 591 } 592