1 #ifdef USE_PRAGMA_IDENT_HDR
2 #pragma ident "@(#)nativeInst_x86.hpp 1.81 07/09/17 09:28:55 JVM"
3 #endif
4 /*
5 * Copyright 1997-2006 Sun Microsystems, Inc. All Rights Reserved.
6 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
7 *
8 * This code is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License version 2 only, as
10 * published by the Free Software Foundation.
11 *
12 * This code is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15 * version 2 for more details (a copy is included in the LICENSE file that
16 * accompanied this code).
17 *
18 * You should have received a copy of the GNU General Public License version
19 * 2 along with this work; if not, write to the Free Software Foundation,
20 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
21 *
22 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
23 * CA 95054 USA or visit www.sun.com if you need additional information or
24 * have any questions.
25 *
36 // - - NativeIllegalOpCode
37 // - - NativeGeneralJump
38 // - - NativeReturn
39 // - - NativeReturnX (return with argument)
40 // - - NativePushConst
41 // - - NativeTstRegMem
42
43 // The base class for different kinds of native instruction abstractions.
44 // Provides the primitive operations to manipulate code relative to this.
45
46 class NativeInstruction VALUE_OBJ_CLASS_SPEC {
47 friend class Relocation;
48
49 public:
50 enum Intel_specific_constants {
51 nop_instruction_code = 0x90,
52 nop_instruction_size = 1
53 };
54
55 bool is_nop() { return ubyte_at(0) == nop_instruction_code; }
56 inline bool is_call();
57 inline bool is_illegal();
58 inline bool is_return();
59 inline bool is_jump();
60 inline bool is_cond_jump();
61 inline bool is_safepoint_poll();
62 inline bool is_mov_literal64();
63
64 protected:
65 address addr_at(int offset) const { return address(this) + offset; }
66
67 s_char sbyte_at(int offset) const { return *(s_char*) addr_at(offset); }
68 u_char ubyte_at(int offset) const { return *(u_char*) addr_at(offset); }
69
70 jint int_at(int offset) const { return *(jint*) addr_at(offset); }
71
72 intptr_t ptr_at(int offset) const { return *(intptr_t*) addr_at(offset); }
73
74 oop oop_at (int offset) const { return *(oop*) addr_at(offset); }
75
220
221 inline NativeMovConstReg* nativeMovConstReg_before(address address) {
222 NativeMovConstReg* test = (NativeMovConstReg*)(address - NativeMovConstReg::instruction_size - NativeMovConstReg::instruction_offset);
223 #ifdef ASSERT
224 test->verify();
225 #endif
226 return test;
227 }
228
229 class NativeMovConstRegPatching: public NativeMovConstReg {
230 private:
231 friend NativeMovConstRegPatching* nativeMovConstRegPatching_at(address address) {
232 NativeMovConstRegPatching* test = (NativeMovConstRegPatching*)(address - instruction_offset);
233 #ifdef ASSERT
234 test->verify();
235 #endif
236 return test;
237 }
238 };
239
240 #ifndef AMD64
241
242 // An interface for accessing/manipulating native moves of the form:
243 // mov[b/w/l] [reg + offset], reg (instruction_code_reg2mem)
244 // mov[b/w/l] reg, [reg+offset] (instruction_code_mem2reg
245 // mov[s/z]x[w/b] [reg + offset], reg
246 // fld_s [reg+offset]
247 // fld_d [reg+offset]
248 // fstp_s [reg + offset]
249 // fstp_d [reg + offset]
250 //
251 // Warning: These routines must be able to handle any instruction sequences
252 // that are generated as a result of the load/store byte,word,long
253 // macros. For example: The load_unsigned_byte instruction generates
254 // an xor reg,reg inst prior to generating the movb instruction. This
255 // class must skip the xor instruction.
256
257 class NativeMovRegMem: public NativeInstruction {
258 public:
259 enum Intel_specific_constants {
260 instruction_code_xor = 0x33,
261 instruction_extended_prefix = 0x0F,
262 instruction_code_mem2reg_movzxb = 0xB6,
263 instruction_code_mem2reg_movsxb = 0xBE,
264 instruction_code_mem2reg_movzxw = 0xB7,
265 instruction_code_mem2reg_movsxw = 0xBF,
266 instruction_operandsize_prefix = 0x66,
267 instruction_code_reg2meml = 0x89,
268 instruction_code_mem2regl = 0x8b,
269 instruction_code_reg2memb = 0x88,
270 instruction_code_mem2regb = 0x8a,
271 instruction_code_float_s = 0xd9,
272 instruction_code_float_d = 0xdd,
273 instruction_code_long_volatile = 0xdf,
274 instruction_code_xmm_ss_prefix = 0xf3,
275 instruction_code_xmm_sd_prefix = 0xf2,
276 instruction_code_xmm_code = 0x0f,
277 instruction_code_xmm_load = 0x10,
278 instruction_code_xmm_store = 0x11,
279 instruction_code_xmm_lpd = 0x12,
280
281 instruction_size = 4,
282 instruction_offset = 0,
283 data_offset = 2,
284 next_instruction_offset = 4
285 };
286
287 address instruction_address() const {
288 if (*addr_at(instruction_offset) == instruction_operandsize_prefix &&
289 *addr_at(instruction_offset+1) != instruction_code_xmm_code) {
290 return addr_at(instruction_offset+1); // Not SSE instructions
291 }
292 else if (*addr_at(instruction_offset) == instruction_extended_prefix) {
293 return addr_at(instruction_offset+1);
294 }
295 else if (*addr_at(instruction_offset) == instruction_code_xor) {
296 return addr_at(instruction_offset+2);
297 }
298 else return addr_at(instruction_offset);
299 }
300
301 address next_instruction_address() const {
302 switch (*addr_at(instruction_offset)) {
303 case instruction_operandsize_prefix:
304 if (*addr_at(instruction_offset+1) == instruction_code_xmm_code)
305 return instruction_address() + instruction_size; // SSE instructions
306 case instruction_extended_prefix:
307 return instruction_address() + instruction_size + 1;
308 case instruction_code_reg2meml:
309 case instruction_code_mem2regl:
310 case instruction_code_reg2memb:
311 case instruction_code_mem2regb:
312 case instruction_code_xor:
313 return instruction_address() + instruction_size + 2;
314 default:
315 return instruction_address() + instruction_size;
316 }
317 }
318 int offset() const{
319 if (*addr_at(instruction_offset) == instruction_operandsize_prefix &&
320 *addr_at(instruction_offset+1) != instruction_code_xmm_code) {
321 return int_at(data_offset+1); // Not SSE instructions
322 }
323 else if (*addr_at(instruction_offset) == instruction_extended_prefix) {
324 return int_at(data_offset+1);
325 }
326 else if (*addr_at(instruction_offset) == instruction_code_xor ||
327 *addr_at(instruction_offset) == instruction_code_xmm_ss_prefix ||
328 *addr_at(instruction_offset) == instruction_code_xmm_sd_prefix ||
329 *addr_at(instruction_offset) == instruction_operandsize_prefix) {
330 return int_at(data_offset+2);
331 }
332 else return int_at(data_offset);
333 }
334
335 void set_offset(int x) {
336 if (*addr_at(instruction_offset) == instruction_operandsize_prefix &&
337 *addr_at(instruction_offset+1) != instruction_code_xmm_code) {
338 set_int_at(data_offset+1, x); // Not SSE instructions
339 }
340 else if (*addr_at(instruction_offset) == instruction_extended_prefix) {
341 set_int_at(data_offset+1, x);
342 }
343 else if (*addr_at(instruction_offset) == instruction_code_xor ||
344 *addr_at(instruction_offset) == instruction_code_xmm_ss_prefix ||
345 *addr_at(instruction_offset) == instruction_code_xmm_sd_prefix ||
346 *addr_at(instruction_offset) == instruction_operandsize_prefix) {
347 set_int_at(data_offset+2, x);
348 }
349 else set_int_at(data_offset, x);
350 }
351
352 void add_offset_in_bytes(int add_offset) { set_offset ( ( offset() + add_offset ) ); }
353 void copy_instruction_to(address new_instruction_address);
354
355 void verify();
356 void print ();
357
358 // unit test stuff
359 static void test() {}
360
361 private:
362 inline friend NativeMovRegMem* nativeMovRegMem_at (address address);
363 };
364
365 inline NativeMovRegMem* nativeMovRegMem_at (address address) {
366 NativeMovRegMem* test = (NativeMovRegMem*)(address - NativeMovRegMem::instruction_offset);
367 #ifdef ASSERT
368 test->verify();
369 #endif
370 return test;
371 }
372
373 class NativeMovRegMemPatching: public NativeMovRegMem {
374 private:
375 friend NativeMovRegMemPatching* nativeMovRegMemPatching_at (address address) {
376 NativeMovRegMemPatching* test = (NativeMovRegMemPatching*)(address - instruction_offset);
377 #ifdef ASSERT
378 test->verify();
379 #endif
380 return test;
381 }
382 };
383
384
385
386 // An interface for accessing/manipulating native leal instruction of form:
387 // leal reg, [reg + offset]
388
389 class NativeLoadAddress: public NativeMovRegMem {
390 public:
391 enum Intel_specific_constants {
392 instruction_code = 0x8D
393 };
394
395 void verify();
396 void print ();
397
398 // unit test stuff
399 static void test() {}
400
401 private:
402 friend NativeLoadAddress* nativeLoadAddress_at (address address) {
403 NativeLoadAddress* test = (NativeLoadAddress*)(address - instruction_offset);
404 #ifdef ASSERT
405 test->verify();
406 #endif
407 return test;
408 }
409 };
410
411 #endif // AMD64
412
413 // jump rel32off
414
415 class NativeJump: public NativeInstruction {
416 public:
417 enum Intel_specific_constants {
418 instruction_code = 0xe9,
419 instruction_size = 5,
420 instruction_offset = 0,
421 data_offset = 1,
422 next_instruction_offset = 5
423 };
424
425 address instruction_address() const { return addr_at(instruction_offset); }
426 address next_instruction_address() const { return addr_at(next_instruction_offset); }
427 address jump_destination() const {
428 address dest = (int_at(data_offset)+next_instruction_address());
429 #ifdef AMD64 // What is this about?
430 // return -1 if jump to self
431 dest = (dest == (address) this) ? (address) -1 : dest;
432 #endif // AMD64
433 return dest;
434 }
435
436 void set_jump_destination(address dest) {
437 intptr_t val = dest - next_instruction_address();
438 #ifdef AMD64
439 if (dest == (address) -1) { // can't encode jump to -1
440 val = -5; // jump to self
441 } else {
442 assert((labs(val) & 0xFFFFFFFF00000000) == 0,
443 "must be 32bit offset");
444 }
445 #endif // AMD64
446 set_int_at(data_offset, (jint)val);
447 }
448
449 // Creation
450 inline friend NativeJump* nativeJump_at(address address);
451
452 void verify();
453
454 // Unit testing stuff
455 static void test() {}
456
457 // Insertion of native jump instruction
458 static void insert(address code_pos, address entry);
459 // MT-safe insertion of native jump at verified method entry
460 static void check_verified_entry_alignment(address entry, address verified_entry);
461 static void patch_verified_entry(address entry, address verified_entry, address dest);
462 };
463
464 inline NativeJump* nativeJump_at(address address) {
553 };
554
555 // Simple test vs memory
556 class NativeTstRegMem: public NativeInstruction {
557 public:
558 enum Intel_specific_constants {
559 instruction_code_memXregl = 0x85
560 };
561 };
562
563 inline bool NativeInstruction::is_illegal() { return (short)int_at(0) == (short)NativeIllegalInstruction::instruction_code; }
564 inline bool NativeInstruction::is_call() { return ubyte_at(0) == NativeCall::instruction_code; }
565 inline bool NativeInstruction::is_return() { return ubyte_at(0) == NativeReturn::instruction_code ||
566 ubyte_at(0) == NativeReturnX::instruction_code; }
567 inline bool NativeInstruction::is_jump() { return ubyte_at(0) == NativeJump::instruction_code ||
568 ubyte_at(0) == 0xEB; /* short jump */ }
569 inline bool NativeInstruction::is_cond_jump() { return (int_at(0) & 0xF0FF) == 0x800F /* long jump */ ||
570 (ubyte_at(0) & 0xF0) == 0x70; /* short jump */ }
571 inline bool NativeInstruction::is_safepoint_poll() {
572 #ifdef AMD64
573 return ubyte_at(0) == NativeTstRegMem::instruction_code_memXregl &&
574 ubyte_at(1) == 0x05 && // 00 rax 101
575 ((intptr_t) addr_at(6)) + int_at(2) == (intptr_t) os::get_polling_page();
576 #else
577 return ( ubyte_at(0) == NativeMovRegMem::instruction_code_mem2regl ||
578 ubyte_at(0) == NativeTstRegMem::instruction_code_memXregl ) &&
579 (ubyte_at(1)&0xC7) == 0x05 && /* Mod R/M == disp32 */
580 (os::is_poll_address((address)int_at(2)));
581 #endif // AMD64
582 }
583
584 inline bool NativeInstruction::is_mov_literal64() {
585 #ifdef AMD64
586 return ((ubyte_at(0) == Assembler::REX_W || ubyte_at(0) == Assembler::REX_WB) &&
587 (ubyte_at(1) & (0xff ^ NativeMovConstReg::register_mask)) == 0xB8);
588 #else
589 return false;
590 #endif // AMD64
591 }
592
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1 /*
2 * Copyright 1997-2008 Sun Microsystems, Inc. All Rights Reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
20 * CA 95054 USA or visit www.sun.com if you need additional information or
21 * have any questions.
22 *
33 // - - NativeIllegalOpCode
34 // - - NativeGeneralJump
35 // - - NativeReturn
36 // - - NativeReturnX (return with argument)
37 // - - NativePushConst
38 // - - NativeTstRegMem
39
40 // The base class for different kinds of native instruction abstractions.
41 // Provides the primitive operations to manipulate code relative to this.
42
43 class NativeInstruction VALUE_OBJ_CLASS_SPEC {
44 friend class Relocation;
45
46 public:
47 enum Intel_specific_constants {
48 nop_instruction_code = 0x90,
49 nop_instruction_size = 1
50 };
51
52 bool is_nop() { return ubyte_at(0) == nop_instruction_code; }
53 bool is_dtrace_trap();
54 inline bool is_call();
55 inline bool is_illegal();
56 inline bool is_return();
57 inline bool is_jump();
58 inline bool is_cond_jump();
59 inline bool is_safepoint_poll();
60 inline bool is_mov_literal64();
61
62 protected:
63 address addr_at(int offset) const { return address(this) + offset; }
64
65 s_char sbyte_at(int offset) const { return *(s_char*) addr_at(offset); }
66 u_char ubyte_at(int offset) const { return *(u_char*) addr_at(offset); }
67
68 jint int_at(int offset) const { return *(jint*) addr_at(offset); }
69
70 intptr_t ptr_at(int offset) const { return *(intptr_t*) addr_at(offset); }
71
72 oop oop_at (int offset) const { return *(oop*) addr_at(offset); }
73
218
219 inline NativeMovConstReg* nativeMovConstReg_before(address address) {
220 NativeMovConstReg* test = (NativeMovConstReg*)(address - NativeMovConstReg::instruction_size - NativeMovConstReg::instruction_offset);
221 #ifdef ASSERT
222 test->verify();
223 #endif
224 return test;
225 }
226
227 class NativeMovConstRegPatching: public NativeMovConstReg {
228 private:
229 friend NativeMovConstRegPatching* nativeMovConstRegPatching_at(address address) {
230 NativeMovConstRegPatching* test = (NativeMovConstRegPatching*)(address - instruction_offset);
231 #ifdef ASSERT
232 test->verify();
233 #endif
234 return test;
235 }
236 };
237
238 // An interface for accessing/manipulating native moves of the form:
239 // mov[b/w/l/q] [reg + offset], reg (instruction_code_reg2mem)
240 // mov[b/w/l/q] reg, [reg+offset] (instruction_code_mem2reg
241 // mov[s/z]x[w/b/q] [reg + offset], reg
242 // fld_s [reg+offset]
243 // fld_d [reg+offset]
244 // fstp_s [reg + offset]
245 // fstp_d [reg + offset]
246 // mov_literal64 scratch,<pointer> ; mov[b/w/l/q] 0(scratch),reg | mov[b/w/l/q] reg,0(scratch)
247 //
248 // Warning: These routines must be able to handle any instruction sequences
249 // that are generated as a result of the load/store byte,word,long
250 // macros. For example: The load_unsigned_byte instruction generates
251 // an xor reg,reg inst prior to generating the movb instruction. This
252 // class must skip the xor instruction.
253
254 class NativeMovRegMem: public NativeInstruction {
255 public:
256 enum Intel_specific_constants {
257 instruction_prefix_wide_lo = Assembler::REX,
258 instruction_prefix_wide_hi = Assembler::REX_WRXB,
259 instruction_code_xor = 0x33,
260 instruction_extended_prefix = 0x0F,
261 instruction_code_mem2reg_movslq = 0x63,
262 instruction_code_mem2reg_movzxb = 0xB6,
263 instruction_code_mem2reg_movsxb = 0xBE,
264 instruction_code_mem2reg_movzxw = 0xB7,
265 instruction_code_mem2reg_movsxw = 0xBF,
266 instruction_operandsize_prefix = 0x66,
267 instruction_code_reg2mem = 0x89,
268 instruction_code_mem2reg = 0x8b,
269 instruction_code_reg2memb = 0x88,
270 instruction_code_mem2regb = 0x8a,
271 instruction_code_float_s = 0xd9,
272 instruction_code_float_d = 0xdd,
273 instruction_code_long_volatile = 0xdf,
274 instruction_code_xmm_ss_prefix = 0xf3,
275 instruction_code_xmm_sd_prefix = 0xf2,
276 instruction_code_xmm_code = 0x0f,
277 instruction_code_xmm_load = 0x10,
278 instruction_code_xmm_store = 0x11,
279 instruction_code_xmm_lpd = 0x12,
280
281 instruction_size = 4,
282 instruction_offset = 0,
283 data_offset = 2,
284 next_instruction_offset = 4
285 };
286
287 // helper
288 int instruction_start() const;
289
290 address instruction_address() const;
291
292 address next_instruction_address() const;
293
294 int offset() const;
295
296 void set_offset(int x);
297
298 void add_offset_in_bytes(int add_offset) { set_offset ( ( offset() + add_offset ) ); }
299
300 void verify();
301 void print ();
302
303 // unit test stuff
304 static void test() {}
305
306 private:
307 inline friend NativeMovRegMem* nativeMovRegMem_at (address address);
308 };
309
310 inline NativeMovRegMem* nativeMovRegMem_at (address address) {
311 NativeMovRegMem* test = (NativeMovRegMem*)(address - NativeMovRegMem::instruction_offset);
312 #ifdef ASSERT
313 test->verify();
314 #endif
315 return test;
316 }
317
318 class NativeMovRegMemPatching: public NativeMovRegMem {
319 private:
320 friend NativeMovRegMemPatching* nativeMovRegMemPatching_at (address address) {
321 NativeMovRegMemPatching* test = (NativeMovRegMemPatching*)(address - instruction_offset);
322 #ifdef ASSERT
323 test->verify();
324 #endif
325 return test;
326 }
327 };
328
329
330
331 // An interface for accessing/manipulating native leal instruction of form:
332 // leal reg, [reg + offset]
333
334 class NativeLoadAddress: public NativeMovRegMem {
335 #ifdef AMD64
336 static const bool has_rex = true;
337 static const int rex_size = 1;
338 #else
339 static const bool has_rex = false;
340 static const int rex_size = 0;
341 #endif // AMD64
342 public:
343 enum Intel_specific_constants {
344 instruction_prefix_wide = Assembler::REX_W,
345 instruction_prefix_wide_extended = Assembler::REX_WB,
346 lea_instruction_code = 0x8D,
347 mov64_instruction_code = 0xB8
348 };
349
350 void verify();
351 void print ();
352
353 // unit test stuff
354 static void test() {}
355
356 private:
357 friend NativeLoadAddress* nativeLoadAddress_at (address address) {
358 NativeLoadAddress* test = (NativeLoadAddress*)(address - instruction_offset);
359 #ifdef ASSERT
360 test->verify();
361 #endif
362 return test;
363 }
364 };
365
366 // jump rel32off
367
368 class NativeJump: public NativeInstruction {
369 public:
370 enum Intel_specific_constants {
371 instruction_code = 0xe9,
372 instruction_size = 5,
373 instruction_offset = 0,
374 data_offset = 1,
375 next_instruction_offset = 5
376 };
377
378 address instruction_address() const { return addr_at(instruction_offset); }
379 address next_instruction_address() const { return addr_at(next_instruction_offset); }
380 address jump_destination() const {
381 address dest = (int_at(data_offset)+next_instruction_address());
382 // 32bit used to encode unresolved jmp as jmp -1
383 // 64bit can't produce this so it used jump to self.
384 // Now 32bit and 64bit use jump to self as the unresolved address
385 // which the inline cache code (and relocs) know about
386
387 // return -1 if jump to self
388 dest = (dest == (address) this) ? (address) -1 : dest;
389 return dest;
390 }
391
392 void set_jump_destination(address dest) {
393 intptr_t val = dest - next_instruction_address();
394 if (dest == (address) -1) {
395 val = -5; // jump to self
396 }
397 #ifdef AMD64
398 assert((labs(val) & 0xFFFFFFFF00000000) == 0 || dest == (address)-1, "must be 32bit offset or -1");
399 #endif // AMD64
400 set_int_at(data_offset, (jint)val);
401 }
402
403 // Creation
404 inline friend NativeJump* nativeJump_at(address address);
405
406 void verify();
407
408 // Unit testing stuff
409 static void test() {}
410
411 // Insertion of native jump instruction
412 static void insert(address code_pos, address entry);
413 // MT-safe insertion of native jump at verified method entry
414 static void check_verified_entry_alignment(address entry, address verified_entry);
415 static void patch_verified_entry(address entry, address verified_entry, address dest);
416 };
417
418 inline NativeJump* nativeJump_at(address address) {
507 };
508
509 // Simple test vs memory
510 class NativeTstRegMem: public NativeInstruction {
511 public:
512 enum Intel_specific_constants {
513 instruction_code_memXregl = 0x85
514 };
515 };
516
517 inline bool NativeInstruction::is_illegal() { return (short)int_at(0) == (short)NativeIllegalInstruction::instruction_code; }
518 inline bool NativeInstruction::is_call() { return ubyte_at(0) == NativeCall::instruction_code; }
519 inline bool NativeInstruction::is_return() { return ubyte_at(0) == NativeReturn::instruction_code ||
520 ubyte_at(0) == NativeReturnX::instruction_code; }
521 inline bool NativeInstruction::is_jump() { return ubyte_at(0) == NativeJump::instruction_code ||
522 ubyte_at(0) == 0xEB; /* short jump */ }
523 inline bool NativeInstruction::is_cond_jump() { return (int_at(0) & 0xF0FF) == 0x800F /* long jump */ ||
524 (ubyte_at(0) & 0xF0) == 0x70; /* short jump */ }
525 inline bool NativeInstruction::is_safepoint_poll() {
526 #ifdef AMD64
527 if ( ubyte_at(0) == NativeTstRegMem::instruction_code_memXregl &&
528 ubyte_at(1) == 0x05 ) { // 00 rax 101
529 address fault = addr_at(6) + int_at(2);
530 return os::is_poll_address(fault);
531 } else {
532 return false;
533 }
534 #else
535 return ( ubyte_at(0) == NativeMovRegMem::instruction_code_mem2reg ||
536 ubyte_at(0) == NativeTstRegMem::instruction_code_memXregl ) &&
537 (ubyte_at(1)&0xC7) == 0x05 && /* Mod R/M == disp32 */
538 (os::is_poll_address((address)int_at(2)));
539 #endif // AMD64
540 }
541
542 inline bool NativeInstruction::is_mov_literal64() {
543 #ifdef AMD64
544 return ((ubyte_at(0) == Assembler::REX_W || ubyte_at(0) == Assembler::REX_WB) &&
545 (ubyte_at(1) & (0xff ^ NativeMovConstReg::register_mask)) == 0xB8);
546 #else
547 return false;
548 #endif // AMD64
549 }
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