hotspot/src/cpu/x86/vm/vm_version_x86_64.cpp
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rev 611 : Merge
@@ -1,10 +1,7 @@
-#ifdef USE_PRAGMA_IDENT_SRC
-#pragma ident "@(#)vm_version_x86_64.cpp 1.25 07/09/20 10:42:57 JVM"
-#endif
/*
- * Copyright 2003-2007 Sun Microsystems, Inc. All Rights Reserved.
+ * Copyright 2003-2008 Sun Microsystems, Inc. All Rights Reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 only, as
* published by the Free Software Foundation.
@@ -61,21 +58,21 @@
//
// void getPsrInfo(VM_Version::CpuidInfo* cpuid_info);
//
// rcx and rdx are first and second argument registers on windows
- __ pushq(rbp);
- __ movq(rbp, c_rarg0); // cpuid_info address
- __ pushq(rbx);
- __ pushq(rsi);
+ __ push(rbp);
+ __ mov(rbp, c_rarg0); // cpuid_info address
+ __ push(rbx);
+ __ push(rsi);
//
// we have a chip which supports the "cpuid" instruction
//
__ xorl(rax, rax);
__ cpuid();
- __ leaq(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid0_offset())));
+ __ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid0_offset())));
__ movl(Address(rsi, 0), rax);
__ movl(Address(rsi, 4), rbx);
__ movl(Address(rsi, 8), rcx);
__ movl(Address(rsi,12), rdx);
@@ -86,17 +83,17 @@
// cpuid(0x4) Deterministic cache params
//
__ movl(rax, 4);
__ xorl(rcx, rcx); // L1 cache
__ cpuid();
- __ pushq(rax);
+ __ push(rax);
__ andl(rax, 0x1f); // Determine if valid cache parameters used
__ orl(rax, rax); // eax[4:0] == 0 indicates invalid cache
- __ popq(rax);
+ __ pop(rax);
__ jccb(Assembler::equal, std_cpuid1);
- __ leaq(rsi, Address(rbp, in_bytes(VM_Version::dcp_cpuid4_offset())));
+ __ lea(rsi, Address(rbp, in_bytes(VM_Version::dcp_cpuid4_offset())));
__ movl(Address(rsi, 0), rax);
__ movl(Address(rsi, 4), rbx);
__ movl(Address(rsi, 8), rcx);
__ movl(Address(rsi,12), rdx);
@@ -104,11 +101,11 @@
// Standard cpuid(0x1)
//
__ bind(std_cpuid1);
__ movl(rax, 1);
__ cpuid();
- __ leaq(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())));
+ __ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())));
__ movl(Address(rsi, 0), rax);
__ movl(Address(rsi, 4), rbx);
__ movl(Address(rsi, 8), rcx);
__ movl(Address(rsi,12), rdx);
@@ -123,11 +120,11 @@
//
// Extended cpuid(0x80000008)
//
__ movl(rax, 0x80000008);
__ cpuid();
- __ leaq(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid8_offset())));
+ __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid8_offset())));
__ movl(Address(rsi, 0), rax);
__ movl(Address(rsi, 4), rbx);
__ movl(Address(rsi, 8), rcx);
__ movl(Address(rsi,12), rdx);
@@ -135,11 +132,11 @@
// Extended cpuid(0x80000005)
//
__ bind(ext_cpuid5);
__ movl(rax, 0x80000005);
__ cpuid();
- __ leaq(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid5_offset())));
+ __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid5_offset())));
__ movl(Address(rsi, 0), rax);
__ movl(Address(rsi, 4), rbx);
__ movl(Address(rsi, 8), rcx);
__ movl(Address(rsi,12), rdx);
@@ -147,23 +144,23 @@
// Extended cpuid(0x80000001)
//
__ bind(ext_cpuid1);
__ movl(rax, 0x80000001);
__ cpuid();
- __ leaq(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid1_offset())));
+ __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid1_offset())));
__ movl(Address(rsi, 0), rax);
__ movl(Address(rsi, 4), rbx);
__ movl(Address(rsi, 8), rcx);
__ movl(Address(rsi,12), rdx);
//
// return
//
__ bind(done);
- __ popq(rsi);
- __ popq(rbx);
- __ popq(rbp);
+ __ pop(rsi);
+ __ pop(rbx);
+ __ pop(rbp);
__ ret(0);
# undef __
return start;
@@ -187,12 +184,14 @@
_supports_cx8 = supports_cmpxchg8();
// OS should support SSE for x64 and hardware should support at least SSE2.
if (!VM_Version::supports_sse2()) {
vm_exit_during_initialization("Unknown x64 processor: SSE2 not supported");
}
- if (UseSSE < 4)
- _cpuFeatures &= ~CPU_SSE4;
+ if (UseSSE < 4) {
+ _cpuFeatures &= ~CPU_SSE4_1;
+ _cpuFeatures &= ~CPU_SSE4_2;
+ }
if (UseSSE < 3) {
_cpuFeatures &= ~CPU_SSE3;
_cpuFeatures &= ~CPU_SSSE3;
_cpuFeatures &= ~CPU_SSE4A;
}
@@ -205,22 +204,23 @@
// HT processor could be installed on a system which doesn't support HT.
_cpuFeatures &= ~CPU_HT;
}
char buf[256];
- jio_snprintf(buf, sizeof(buf), "(%u cores per cpu, %u threads per core) family %d model %d stepping %d%s%s%s%s%s%s%s%s%s%s%s%s%s%s",
+ jio_snprintf(buf, sizeof(buf), "(%u cores per cpu, %u threads per core) family %d model %d stepping %d%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s",
cores_per_cpu(), threads_per_core(),
cpu_family(), _model, _stepping,
(supports_cmov() ? ", cmov" : ""),
(supports_cmpxchg8() ? ", cx8" : ""),
(supports_fxsr() ? ", fxsr" : ""),
(supports_mmx() ? ", mmx" : ""),
(supports_sse() ? ", sse" : ""),
(supports_sse2() ? ", sse2" : ""),
(supports_sse3() ? ", sse3" : ""),
(supports_ssse3()? ", ssse3": ""),
- (supports_sse4() ? ", sse4" : ""),
+ (supports_sse4_1() ? ", sse4.1" : ""),
+ (supports_sse4_2() ? ", sse4.2" : ""),
(supports_mmx_ext() ? ", mmxext" : ""),
(supports_3dnow() ? ", 3dnow" : ""),
(supports_3dnow2() ? ", 3dnowext" : ""),
(supports_sse4a() ? ", sse4a": ""),
(supports_ht() ? ", ht": ""));
@@ -229,11 +229,11 @@
// UseSSE is set to the smaller of what hardware supports and what
// the command line requires. I.e., you cannot set UseSSE to 2 on
// older Pentiums which do not support it.
if( UseSSE > 4 ) UseSSE=4;
if( UseSSE < 0 ) UseSSE=0;
- if( !supports_sse4() ) // Drop to 3 if no SSE4 support
+ if( !supports_sse4_1() ) // Drop to 3 if no SSE4 support
UseSSE = MIN2((intx)3,UseSSE);
if( !supports_sse3() ) // Drop to 2 if no SSE3 support
UseSSE = MIN2((intx)2,UseSSE);
if( !supports_sse2() ) // Drop to 1 if no SSE2 support
UseSSE = MIN2((intx)1,UseSSE);
@@ -266,10 +266,24 @@
UseXmmRegToRegMoveAll = true; // use movaps, movapd only on '10h'
} else {
UseXmmRegToRegMoveAll = false;
}
}
+ if( FLAG_IS_DEFAULT(UseXmmI2F) ) {
+ if( supports_sse4a() ) {
+ UseXmmI2F = true;
+ } else {
+ UseXmmI2F = false;
+ }
+ }
+ if( FLAG_IS_DEFAULT(UseXmmI2D) ) {
+ if( supports_sse4a() ) {
+ UseXmmI2D = true;
+ } else {
+ UseXmmI2D = false;
+ }
+ }
}
if( is_intel() ) { // Intel cpus specific settings
if( FLAG_IS_DEFAULT(UseStoreImmI16) ) {
UseStoreImmI16 = false; // don't use it on Intel cpus
@@ -301,10 +315,18 @@
// generated NOP instructions. 11 is the largest size of one
// address NOP instruction '0F 1F' (see Assembler::nop(i)).
MaxLoopPad = 11;
}
#endif // COMPILER2
+ if( FLAG_IS_DEFAULT(UseXMMForArrayCopy) ) {
+ UseXMMForArrayCopy = true; // use SSE2 movq on new Intel cpus
+ }
+ if( supports_sse4_2() && supports_ht() ) { // Newest Intel cpus
+ if( FLAG_IS_DEFAULT(UseUnalignedLoadStores) && UseXMMForArrayCopy ) {
+ UseUnalignedLoadStores = true; // use movdqu on newest Intel cpus
+ }
+ }
}
}
assert(0 <= ReadPrefetchInstr && ReadPrefetchInstr <= 3, "invalid value");
assert(0 <= AllocatePrefetchInstr && AllocatePrefetchInstr <= 3, "invalid value");
@@ -342,11 +364,11 @@
PrefetchScanIntervalInBytes = prefetch_scan_interval_in_bytes();
PrefetchFieldsAhead = prefetch_fields_ahead();
#ifndef PRODUCT
if (PrintMiscellaneous && Verbose) {
- tty->print_cr("Logical CPUs per package: %u",
+ tty->print_cr("Logical CPUs per core: %u",
logical_processors_per_package());
tty->print_cr("UseSSE=%d",UseSSE);
tty->print("Allocation: ");
if (AllocatePrefetchStyle <= 0) {
tty->print_cr("no prefetching");