1 #ifdef USE_PRAGMA_IDENT_SRC
2 #pragma ident "@(#)chaitin.cpp 1.116 07/09/28 10:23:12 JVM"
3 #endif
4 /*
5 * Copyright 2000-2008 Sun Microsystems, Inc. All Rights Reserved.
6 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
7 *
8 * This code is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License version 2 only, as
10 * published by the Free Software Foundation.
11 *
12 * This code is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15 * version 2 for more details (a copy is included in the LICENSE file that
16 * accompanied this code).
17 *
18 * You should have received a copy of the GNU General Public License version
19 * 2 along with this work; if not, write to the Free Software Foundation,
20 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
21 *
22 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
23 * CA 95054 USA or visit www.sun.com if you need additional information or
24 * have any questions.
25 *
26 */
27
28 #include "incls/_precompiled.incl"
29 #include "incls/_chaitin.cpp.incl"
30
31 //=============================================================================
32
33 #ifndef PRODUCT
34 void LRG::dump( ) const {
35 ttyLocker ttyl;
36 tty->print("%d ",num_regs());
37 _mask.dump();
38 if( _msize_valid ) {
39 if( mask_size() == compute_mask_size() ) tty->print(", #%d ",_mask_size);
40 else tty->print(", #!!!_%d_vs_%d ",_mask_size,_mask.Size());
41 } else {
42 tty->print(", #?(%d) ",_mask.Size());
43 }
44
45 tty->print("EffDeg: ");
46 if( _degree_valid ) tty->print( "%d ", _eff_degree );
47 else tty->print("? ");
48
49 if( is_multidef() ) {
50 tty->print("MultiDef ");
51 if (_defs != NULL) {
52 tty->print("(");
53 for (int i = 0; i < _defs->length(); i++) {
54 tty->print("N%d ", _defs->at(i)->_idx);
55 }
56 tty->print(") ");
57 }
58 }
59 else if( _def == 0 ) tty->print("Dead ");
60 else tty->print("Def: N%d ",_def->_idx);
61
62 tty->print("Cost:%4.2g Area:%4.2g Score:%4.2g ",_cost,_area, score());
63 // Flags
64 if( _is_oop ) tty->print("Oop ");
65 if( _is_float ) tty->print("Float ");
66 if( _was_spilled1 ) tty->print("Spilled ");
67 if( _was_spilled2 ) tty->print("Spilled2 ");
68 if( _direct_conflict ) tty->print("Direct_conflict ");
69 if( _fat_proj ) tty->print("Fat ");
70 if( _was_lo ) tty->print("Lo ");
71 if( _has_copy ) tty->print("Copy ");
72 if( _at_risk ) tty->print("Risk ");
73
74 if( _must_spill ) tty->print("Must_spill ");
75 if( _is_bound ) tty->print("Bound ");
76 if( _msize_valid ) {
77 if( _degree_valid && lo_degree() ) tty->print("Trivial ");
78 }
79
80 tty->cr();
81 }
82 #endif
83
84 //------------------------------score------------------------------------------
85 // Compute score from cost and area. Low score is best to spill.
86 static double raw_score( double cost, double area ) {
87 return cost - (area*RegisterCostAreaRatio) * 1.52588e-5;
88 }
89
90 double LRG::score() const {
91 // Scale _area by RegisterCostAreaRatio/64K then subtract from cost.
92 // Bigger area lowers score, encourages spilling this live range.
93 // Bigger cost raise score, prevents spilling this live range.
94 // (Note: 1/65536 is the magic constant below; I dont trust the C optimizer
95 // to turn a divide by a constant into a multiply by the reciprical).
96 double score = raw_score( _cost, _area);
97
98 // Account for area. Basically, LRGs covering large areas are better
99 // to spill because more other LRGs get freed up.
100 if( _area == 0.0 ) // No area? Then no progress to spill
101 return 1e35;
102
103 if( _was_spilled2 ) // If spilled once before, we are unlikely
104 return score + 1e30; // to make progress again.
105
106 if( _cost >= _area*3.0 ) // Tiny area relative to cost
107 return score + 1e17; // Probably no progress to spill
108
109 if( (_cost+_cost) >= _area*3.0 ) // Small area relative to cost
110 return score + 1e10; // Likely no progress to spill
111
112 return score;
113 }
114
115 //------------------------------LRG_List---------------------------------------
116 LRG_List::LRG_List( uint max ) : _cnt(max), _max(max), _lidxs(NEW_RESOURCE_ARRAY(uint,max)) {
117 memset( _lidxs, 0, sizeof(uint)*max );
118 }
119
120 void LRG_List::extend( uint nidx, uint lidx ) {
121 _nesting.check();
122 if( nidx >= _max ) {
123 uint size = 16;
124 while( size <= nidx ) size <<=1;
125 _lidxs = REALLOC_RESOURCE_ARRAY( uint, _lidxs, _max, size );
126 _max = size;
127 }
128 while( _cnt <= nidx )
129 _lidxs[_cnt++] = 0;
130 _lidxs[nidx] = lidx;
131 }
132
133 #define NUMBUCKS 3
134
135 //------------------------------Chaitin----------------------------------------
136 PhaseChaitin::PhaseChaitin(uint unique, PhaseCFG &cfg, Matcher &matcher)
137 : PhaseRegAlloc(unique, cfg, matcher,
138 #ifndef PRODUCT
139 print_chaitin_statistics
140 #else
141 NULL
142 #endif
143 ),
144 _names(unique), _uf_map(unique),
145 _maxlrg(0), _live(0),
146 _spilled_once(Thread::current()->resource_area()),
147 _spilled_twice(Thread::current()->resource_area()),
148 _lo_degree(0), _lo_stk_degree(0), _hi_degree(0), _simplified(0),
149 _oldphi(unique)
150 #ifndef PRODUCT
151 , _trace_spilling(TraceSpilling || C->method_has_option("TraceSpilling"))
152 #endif
153 {
154 NOT_PRODUCT( Compile::TracePhase t3("ctorChaitin", &_t_ctorChaitin, TimeCompiler); )
155 uint i,j;
156 // Build a list of basic blocks, sorted by frequency
157 _blks = NEW_RESOURCE_ARRAY( Block *, _cfg._num_blocks );
158 // Experiment with sorting strategies to speed compilation
159 double cutoff = BLOCK_FREQUENCY(1.0); // Cutoff for high frequency bucket
160 Block **buckets[NUMBUCKS]; // Array of buckets
161 uint buckcnt[NUMBUCKS]; // Array of bucket counters
162 double buckval[NUMBUCKS]; // Array of bucket value cutoffs
163 for( i = 0; i < NUMBUCKS; i++ ) {
164 buckets[i] = NEW_RESOURCE_ARRAY( Block *, _cfg._num_blocks );
165 buckcnt[i] = 0;
166 // Bump by three orders of magnitude each time
167 cutoff *= 0.001;
168 buckval[i] = cutoff;
169 for( j = 0; j < _cfg._num_blocks; j++ ) {
170 buckets[i][j] = NULL;
171 }
172 }
173 // Sort blocks into buckets
174 for( i = 0; i < _cfg._num_blocks; i++ ) {
175 for( j = 0; j < NUMBUCKS; j++ ) {
176 if( (j == NUMBUCKS-1) || (_cfg._blocks[i]->_freq > buckval[j]) ) {
177 // Assign block to end of list for appropriate bucket
178 buckets[j][buckcnt[j]++] = _cfg._blocks[i];
179 break; // kick out of inner loop
180 }
181 }
182 }
183 // Dump buckets into final block array
184 uint blkcnt = 0;
185 for( i = 0; i < NUMBUCKS; i++ ) {
186 for( j = 0; j < buckcnt[i]; j++ ) {
187 _blks[blkcnt++] = buckets[i][j];
188 }
189 }
190
191 assert(blkcnt == _cfg._num_blocks, "Block array not totally filled");
192 }
193
194 void PhaseChaitin::Register_Allocate() {
195
196 // Above the OLD FP (and in registers) are the incoming arguments. Stack
197 // slots in this area are called "arg_slots". Above the NEW FP (and in
198 // registers) is the outgoing argument area; above that is the spill/temp
199 // area. These are all "frame_slots". Arg_slots start at the zero
200 // stack_slots and count up to the known arg_size. Frame_slots start at
201 // the stack_slot #arg_size and go up. After allocation I map stack
202 // slots to actual offsets. Stack-slots in the arg_slot area are biased
203 // by the frame_size; stack-slots in the frame_slot area are biased by 0.
204
205 _trip_cnt = 0;
206 _alternate = 0;
207 _matcher._allocation_started = true;
208
209 ResourceArea live_arena; // Arena for liveness & IFG info
210 ResourceMark rm(&live_arena);
211
212 // Need live-ness for the IFG; need the IFG for coalescing. If the
213 // liveness is JUST for coalescing, then I can get some mileage by renaming
214 // all copy-related live ranges low and then using the max copy-related
215 // live range as a cut-off for LIVE and the IFG. In other words, I can
216 // build a subset of LIVE and IFG just for copies.
217 PhaseLive live(_cfg,_names,&live_arena);
218
219 // Need IFG for coalescing and coloring
220 PhaseIFG ifg( &live_arena );
221 _ifg = &ifg;
222
223 if (C->unique() > _names.Size()) _names.extend(C->unique()-1, 0);
224
225 // Come out of SSA world to the Named world. Assign (virtual) registers to
226 // Nodes. Use the same register for all inputs and the output of PhiNodes
227 // - effectively ending SSA form. This requires either coalescing live
228 // ranges or inserting copies. For the moment, we insert "virtual copies"
229 // - we pretend there is a copy prior to each Phi in predecessor blocks.
230 // We will attempt to coalesce such "virtual copies" before we manifest
231 // them for real.
232 de_ssa();
233
234 {
235 NOT_PRODUCT( Compile::TracePhase t3("computeLive", &_t_computeLive, TimeCompiler); )
236 _live = NULL; // Mark live as being not available
237 rm.reset_to_mark(); // Reclaim working storage
238 IndexSet::reset_memory(C, &live_arena);
239 ifg.init(_maxlrg); // Empty IFG
240 gather_lrg_masks( false ); // Collect LRG masks
241 live.compute( _maxlrg ); // Compute liveness
242 _live = &live; // Mark LIVE as being available
243 }
244
245 // Base pointers are currently "used" by instructions which define new
246 // derived pointers. This makes base pointers live up to the where the
247 // derived pointer is made, but not beyond. Really, they need to be live
248 // across any GC point where the derived value is live. So this code looks
249 // at all the GC points, and "stretches" the live range of any base pointer
250 // to the GC point.
251 if( stretch_base_pointer_live_ranges(&live_arena) ) {
252 NOT_PRODUCT( Compile::TracePhase t3("computeLive (sbplr)", &_t_computeLive, TimeCompiler); )
253 // Since some live range stretched, I need to recompute live
254 _live = NULL;
255 rm.reset_to_mark(); // Reclaim working storage
256 IndexSet::reset_memory(C, &live_arena);
257 ifg.init(_maxlrg);
258 gather_lrg_masks( false );
259 live.compute( _maxlrg );
260 _live = &live;
261 }
262 // Create the interference graph using virtual copies
263 build_ifg_virtual( ); // Include stack slots this time
264
265 // Aggressive (but pessimistic) copy coalescing.
266 // This pass works on virtual copies. Any virtual copies which are not
267 // coalesced get manifested as actual copies
268 {
269 // The IFG is/was triangular. I am 'squaring it up' so Union can run
270 // faster. Union requires a 'for all' operation which is slow on the
271 // triangular adjacency matrix (quick reminder: the IFG is 'sparse' -
272 // meaning I can visit all the Nodes neighbors less than a Node in time
273 // O(# of neighbors), but I have to visit all the Nodes greater than a
274 // given Node and search them for an instance, i.e., time O(#MaxLRG)).
275 _ifg->SquareUp();
276
277 PhaseAggressiveCoalesce coalesce( *this );
278 coalesce.coalesce_driver( );
279 // Insert un-coalesced copies. Visit all Phis. Where inputs to a Phi do
280 // not match the Phi itself, insert a copy.
281 coalesce.insert_copies(_matcher);
282 }
283
284 // After aggressive coalesce, attempt a first cut at coloring.
285 // To color, we need the IFG and for that we need LIVE.
286 {
287 NOT_PRODUCT( Compile::TracePhase t3("computeLive", &_t_computeLive, TimeCompiler); )
288 _live = NULL;
289 rm.reset_to_mark(); // Reclaim working storage
290 IndexSet::reset_memory(C, &live_arena);
291 ifg.init(_maxlrg);
292 gather_lrg_masks( true );
293 live.compute( _maxlrg );
294 _live = &live;
295 }
296
297 // Build physical interference graph
298 uint must_spill = 0;
299 must_spill = build_ifg_physical( &live_arena );
300 // If we have a guaranteed spill, might as well spill now
301 if( must_spill ) {
302 if( !_maxlrg ) return;
303 // Bail out if unique gets too large (ie - unique > MaxNodeLimit)
304 C->check_node_count(10*must_spill, "out of nodes before split");
305 if (C->failing()) return;
306 _maxlrg = Split( _maxlrg ); // Split spilling LRG everywhere
307 // Bail out if unique gets too large (ie - unique > MaxNodeLimit - 2*NodeLimitFudgeFactor)
308 // or we failed to split
309 C->check_node_count(2*NodeLimitFudgeFactor, "out of nodes after physical split");
310 if (C->failing()) return;
311
312 #ifdef ASSERT
313 if( VerifyOpto ) {
314 _cfg.verify();
315 verify_base_ptrs(&live_arena);
316 }
317 #endif
318 NOT_PRODUCT( C->verify_graph_edges(); )
319
320 compact(); // Compact LRGs; return new lower max lrg
321
322 {
323 NOT_PRODUCT( Compile::TracePhase t3("computeLive", &_t_computeLive, TimeCompiler); )
324 _live = NULL;
325 rm.reset_to_mark(); // Reclaim working storage
326 IndexSet::reset_memory(C, &live_arena);
327 ifg.init(_maxlrg); // Build a new interference graph
328 gather_lrg_masks( true ); // Collect intersect mask
329 live.compute( _maxlrg ); // Compute LIVE
330 _live = &live;
331 }
332 build_ifg_physical( &live_arena );
333 _ifg->SquareUp();
334 _ifg->Compute_Effective_Degree();
335 // Only do conservative coalescing if requested
336 if( OptoCoalesce ) {
337 // Conservative (and pessimistic) copy coalescing of those spills
338 PhaseConservativeCoalesce coalesce( *this );
339 // If max live ranges greater than cutoff, don't color the stack.
340 // This cutoff can be larger than below since it is only done once.
341 coalesce.coalesce_driver( );
342 }
343 compress_uf_map_for_nodes();
344
345 #ifdef ASSERT
346 if( VerifyOpto ) _ifg->verify(this);
347 #endif
348 } else {
349 ifg.SquareUp();
350 ifg.Compute_Effective_Degree();
351 #ifdef ASSERT
352 set_was_low();
353 #endif
354 }
355
356 // Prepare for Simplify & Select
357 cache_lrg_info(); // Count degree of LRGs
358
359 // Simplify the InterFerence Graph by removing LRGs of low degree.
360 // LRGs of low degree are trivially colorable.
361 Simplify();
362
363 // Select colors by re-inserting LRGs back into the IFG in reverse order.
364 // Return whether or not something spills.
365 uint spills = Select( );
366
367 // If we spill, split and recycle the entire thing
368 while( spills ) {
369 if( _trip_cnt++ > 24 ) {
370 DEBUG_ONLY( dump_for_spill_split_recycle(); )
371 if( _trip_cnt > 27 ) {
372 C->record_method_not_compilable("failed spill-split-recycle sanity check");
373 return;
374 }
375 }
376
377 if( !_maxlrg ) return;
378 _maxlrg = Split( _maxlrg ); // Split spilling LRG everywhere
379 // Bail out if unique gets too large (ie - unique > MaxNodeLimit - 2*NodeLimitFudgeFactor)
380 C->check_node_count(2*NodeLimitFudgeFactor, "out of nodes after split");
381 if (C->failing()) return;
382 #ifdef ASSERT
383 if( VerifyOpto ) {
384 _cfg.verify();
385 verify_base_ptrs(&live_arena);
386 }
387 #endif
388
389 compact(); // Compact LRGs; return new lower max lrg
390
391 // Nuke the live-ness and interference graph and LiveRanGe info
392 {
393 NOT_PRODUCT( Compile::TracePhase t3("computeLive", &_t_computeLive, TimeCompiler); )
394 _live = NULL;
395 rm.reset_to_mark(); // Reclaim working storage
396 IndexSet::reset_memory(C, &live_arena);
397 ifg.init(_maxlrg);
398
399 // Create LiveRanGe array.
400 // Intersect register masks for all USEs and DEFs
401 gather_lrg_masks( true );
402 live.compute( _maxlrg );
403 _live = &live;
404 }
405 must_spill = build_ifg_physical( &live_arena );
406 _ifg->SquareUp();
407 _ifg->Compute_Effective_Degree();
408
409 // Only do conservative coalescing if requested
410 if( OptoCoalesce ) {
411 // Conservative (and pessimistic) copy coalescing
412 PhaseConservativeCoalesce coalesce( *this );
413 // Check for few live ranges determines how aggressive coalesce is.
414 coalesce.coalesce_driver( );
415 }
416 compress_uf_map_for_nodes();
417 #ifdef ASSERT
418 if( VerifyOpto ) _ifg->verify(this);
419 #endif
420 cache_lrg_info(); // Count degree of LRGs
421
422 // Simplify the InterFerence Graph by removing LRGs of low degree.
423 // LRGs of low degree are trivially colorable.
424 Simplify();
425
426 // Select colors by re-inserting LRGs back into the IFG in reverse order.
427 // Return whether or not something spills.
428 spills = Select( );
429 }
430
431 // Count number of Simplify-Select trips per coloring success.
432 _allocator_attempts += _trip_cnt + 1;
433 _allocator_successes += 1;
434
435 // Peephole remove copies
436 post_allocate_copy_removal();
437
438 // max_reg is past the largest *register* used.
439 // Convert that to a frame_slot number.
440 if( _max_reg <= _matcher._new_SP )
441 _framesize = C->out_preserve_stack_slots();
442 else _framesize = _max_reg -_matcher._new_SP;
443 assert((int)(_matcher._new_SP+_framesize) >= (int)_matcher._out_arg_limit, "framesize must be large enough");
444
445 // This frame must preserve the required fp alignment
446 _framesize = round_to(_framesize, Matcher::stack_alignment_in_slots());
447 assert( _framesize >= 0 && _framesize <= 1000000, "sanity check" );
448 #ifndef PRODUCT
449 _total_framesize += _framesize;
450 if( (int)_framesize > _max_framesize )
451 _max_framesize = _framesize;
452 #endif
453
454 // Convert CISC spills
455 fixup_spills();
456
457 // Log regalloc results
458 CompileLog* log = Compile::current()->log();
459 if (log != NULL) {
460 log->elem("regalloc attempts='%d' success='%d'", _trip_cnt, !C->failing());
461 }
462
463 if (C->failing()) return;
464
465 NOT_PRODUCT( C->verify_graph_edges(); )
466
467 // Move important info out of the live_arena to longer lasting storage.
468 alloc_node_regs(_names.Size());
469 for( uint i=0; i < _names.Size(); i++ ) {
470 if( _names[i] ) { // Live range associated with Node?
471 LRG &lrg = lrgs( _names[i] );
472 if( lrg.num_regs() == 1 ) {
473 _node_regs[i].set1( lrg.reg() );
474 } else { // Must be a register-pair
475 if( !lrg._fat_proj ) { // Must be aligned adjacent register pair
476 // Live ranges record the highest register in their mask.
477 // We want the low register for the AD file writer's convenience.
478 _node_regs[i].set2( OptoReg::add(lrg.reg(),-1) );
479 } else { // Misaligned; extract 2 bits
480 OptoReg::Name hi = lrg.reg(); // Get hi register
481 lrg.Remove(hi); // Yank from mask
482 int lo = lrg.mask().find_first_elem(); // Find lo
483 _node_regs[i].set_pair( hi, lo );
484 }
485 }
486 if( lrg._is_oop ) _node_oops.set(i);
487 } else {
488 _node_regs[i].set_bad();
489 }
490 }
491
492 // Done!
493 _live = NULL;
494 _ifg = NULL;
495 C->set_indexSet_arena(NULL); // ResourceArea is at end of scope
496 }
497
498 //------------------------------de_ssa-----------------------------------------
499 void PhaseChaitin::de_ssa() {
500 // Set initial Names for all Nodes. Most Nodes get the virtual register
501 // number. A few get the ZERO live range number. These do not
502 // get allocated, but instead rely on correct scheduling to ensure that
503 // only one instance is simultaneously live at a time.
504 uint lr_counter = 1;
505 for( uint i = 0; i < _cfg._num_blocks; i++ ) {
506 Block *b = _cfg._blocks[i];
507 uint cnt = b->_nodes.size();
508
509 // Handle all the normal Nodes in the block
510 for( uint j = 0; j < cnt; j++ ) {
511 Node *n = b->_nodes[j];
512 // Pre-color to the zero live range, or pick virtual register
513 const RegMask &rm = n->out_RegMask();
514 _names.map( n->_idx, rm.is_NotEmpty() ? lr_counter++ : 0 );
515 }
516 }
517 // Reset the Union-Find mapping to be identity
518 reset_uf_map(lr_counter);
519 }
520
521
522 //------------------------------gather_lrg_masks-------------------------------
523 // Gather LiveRanGe information, including register masks. Modification of
524 // cisc spillable in_RegMasks should not be done before AggressiveCoalesce.
525 void PhaseChaitin::gather_lrg_masks( bool after_aggressive ) {
526
527 // Nail down the frame pointer live range
528 uint fp_lrg = n2lidx(_cfg._root->in(1)->in(TypeFunc::FramePtr));
529 lrgs(fp_lrg)._cost += 1e12; // Cost is infinite
530
531 // For all blocks
532 for( uint i = 0; i < _cfg._num_blocks; i++ ) {
533 Block *b = _cfg._blocks[i];
534
535 // For all instructions
536 for( uint j = 1; j < b->_nodes.size(); j++ ) {
537 Node *n = b->_nodes[j];
538 uint input_edge_start =1; // Skip control most nodes
539 if( n->is_Mach() ) input_edge_start = n->as_Mach()->oper_input_base();
540 uint idx = n->is_Copy();
541
542 // Get virtual register number, same as LiveRanGe index
543 uint vreg = n2lidx(n);
544 LRG &lrg = lrgs(vreg);
545 if( vreg ) { // No vreg means un-allocable (e.g. memory)
546
547 // Collect has-copy bit
548 if( idx ) {
549 lrg._has_copy = 1;
550 uint clidx = n2lidx(n->in(idx));
551 LRG ©_src = lrgs(clidx);
552 copy_src._has_copy = 1;
553 }
554
555 // Check for float-vs-int live range (used in register-pressure
556 // calculations)
557 const Type *n_type = n->bottom_type();
558 if( n_type->is_floatingpoint() )
559 lrg._is_float = 1;
560
561 // Check for twice prior spilling. Once prior spilling might have
562 // spilled 'soft', 2nd prior spill should have spilled 'hard' and
563 // further spilling is unlikely to make progress.
564 if( _spilled_once.test(n->_idx) ) {
565 lrg._was_spilled1 = 1;
566 if( _spilled_twice.test(n->_idx) )
567 lrg._was_spilled2 = 1;
568 }
569
570 #ifndef PRODUCT
571 if (trace_spilling() && lrg._def != NULL) {
572 // collect defs for MultiDef printing
573 if (lrg._defs == NULL) {
574 lrg._defs = new (_ifg->_arena) GrowableArray<Node*>();
575 lrg._defs->append(lrg._def);
576 }
577 lrg._defs->append(n);
578 }
579 #endif
580
581 // Check for a single def LRG; these can spill nicely
582 // via rematerialization. Flag as NULL for no def found
583 // yet, or 'n' for single def or -1 for many defs.
584 lrg._def = lrg._def ? NodeSentinel : n;
585
586 // Limit result register mask to acceptable registers
587 const RegMask &rm = n->out_RegMask();
588 lrg.AND( rm );
589 // Check for bound register masks
590 const RegMask &lrgmask = lrg.mask();
591 if( lrgmask.is_bound1() || lrgmask.is_bound2() )
592 lrg._is_bound = 1;
593
594 // Check for maximum frequency value
595 if( lrg._maxfreq < b->_freq )
596 lrg._maxfreq = b->_freq;
597
598 int ireg = n->ideal_reg();
599 assert( !n->bottom_type()->isa_oop_ptr() || ireg == Op_RegP,
600 "oops must be in Op_RegP's" );
601 // Check for oop-iness, or long/double
602 // Check for multi-kill projection
603 switch( ireg ) {
604 case MachProjNode::fat_proj:
605 // Fat projections have size equal to number of registers killed
606 lrg.set_num_regs(rm.Size());
607 lrg.set_reg_pressure(lrg.num_regs());
608 lrg._fat_proj = 1;
609 lrg._is_bound = 1;
610 break;
611 case Op_RegP:
612 #ifdef _LP64
613 lrg.set_num_regs(2); // Size is 2 stack words
614 #else
615 lrg.set_num_regs(1); // Size is 1 stack word
616 #endif
617 // Register pressure is tracked relative to the maximum values
618 // suggested for that platform, INTPRESSURE and FLOATPRESSURE,
619 // and relative to other types which compete for the same regs.
620 //
621 // The following table contains suggested values based on the
622 // architectures as defined in each .ad file.
623 // INTPRESSURE and FLOATPRESSURE may be tuned differently for
624 // compile-speed or performance.
625 // Note1:
626 // SPARC and SPARCV9 reg_pressures are at 2 instead of 1
627 // since .ad registers are defined as high and low halves.
628 // These reg_pressure values remain compatible with the code
629 // in is_high_pressure() which relates get_invalid_mask_size(),
630 // Block::_reg_pressure and INTPRESSURE, FLOATPRESSURE.
631 // Note2:
632 // SPARC -d32 has 24 registers available for integral values,
633 // but only 10 of these are safe for 64-bit longs.
634 // Using set_reg_pressure(2) for both int and long means
635 // the allocator will believe it can fit 26 longs into
636 // registers. Using 2 for longs and 1 for ints means the
637 // allocator will attempt to put 52 integers into registers.
638 // The settings below limit this problem to methods with
639 // many long values which are being run on 32-bit SPARC.
640 //
641 // ------------------- reg_pressure --------------------
642 // Each entry is reg_pressure_per_value,number_of_regs
643 // RegL RegI RegFlags RegF RegD INTPRESSURE FLOATPRESSURE
644 // IA32 2 1 1 1 1 6 6
645 // IA64 1 1 1 1 1 50 41
646 // SPARC 2 2 2 2 2 48 (24) 52 (26)
647 // SPARCV9 2 2 2 2 2 48 (24) 52 (26)
648 // AMD64 1 1 1 1 1 14 15
649 // -----------------------------------------------------
650 #if defined(SPARC)
651 lrg.set_reg_pressure(2); // use for v9 as well
652 #else
653 lrg.set_reg_pressure(1); // normally one value per register
654 #endif
655 if( n_type->isa_oop_ptr() ) {
656 lrg._is_oop = 1;
657 }
658 break;
659 case Op_RegL: // Check for long or double
660 case Op_RegD:
661 lrg.set_num_regs(2);
662 // Define platform specific register pressure
663 #ifdef SPARC
664 lrg.set_reg_pressure(2);
665 #elif defined(IA32)
666 if( ireg == Op_RegL ) {
667 lrg.set_reg_pressure(2);
668 } else {
669 lrg.set_reg_pressure(1);
670 }
671 #else
672 lrg.set_reg_pressure(1); // normally one value per register
673 #endif
674 // If this def of a double forces a mis-aligned double,
675 // flag as '_fat_proj' - really flag as allowing misalignment
676 // AND changes how we count interferences. A mis-aligned
677 // double can interfere with TWO aligned pairs, or effectively
678 // FOUR registers!
679 if( rm.is_misaligned_Pair() ) {
680 lrg._fat_proj = 1;
681 lrg._is_bound = 1;
682 }
683 break;
684 case Op_RegF:
685 case Op_RegI:
686 case Op_RegN:
687 case Op_RegFlags:
688 case 0: // not an ideal register
689 lrg.set_num_regs(1);
690 #ifdef SPARC
691 lrg.set_reg_pressure(2);
692 #else
693 lrg.set_reg_pressure(1);
694 #endif
695 break;
696 default:
697 ShouldNotReachHere();
698 }
699 }
700
701 // Now do the same for inputs
702 uint cnt = n->req();
703 // Setup for CISC SPILLING
704 uint inp = (uint)AdlcVMDeps::Not_cisc_spillable;
705 if( UseCISCSpill && after_aggressive ) {
706 inp = n->cisc_operand();
707 if( inp != (uint)AdlcVMDeps::Not_cisc_spillable )
708 // Convert operand number to edge index number
709 inp = n->as_Mach()->operand_index(inp);
710 }
711 // Prepare register mask for each input
712 for( uint k = input_edge_start; k < cnt; k++ ) {
713 uint vreg = n2lidx(n->in(k));
714 if( !vreg ) continue;
715
716 // If this instruction is CISC Spillable, add the flags
717 // bit to its appropriate input
718 if( UseCISCSpill && after_aggressive && inp == k ) {
719 #ifndef PRODUCT
720 if( TraceCISCSpill ) {
721 tty->print(" use_cisc_RegMask: ");
722 n->dump();
723 }
724 #endif
725 n->as_Mach()->use_cisc_RegMask();
726 }
727
728 LRG &lrg = lrgs(vreg);
729 // // Testing for floating point code shape
730 // Node *test = n->in(k);
731 // if( test->is_Mach() ) {
732 // MachNode *m = test->as_Mach();
733 // int op = m->ideal_Opcode();
734 // if (n->is_Call() && (op == Op_AddF || op == Op_MulF) ) {
735 // int zzz = 1;
736 // }
737 // }
738
739 // Limit result register mask to acceptable registers.
740 // Do not limit registers from uncommon uses before
741 // AggressiveCoalesce. This effectively pre-virtual-splits
742 // around uncommon uses of common defs.
743 const RegMask &rm = n->in_RegMask(k);
744 if( !after_aggressive &&
745 _cfg._bbs[n->in(k)->_idx]->_freq > 1000*b->_freq ) {
746 // Since we are BEFORE aggressive coalesce, leave the register
747 // mask untrimmed by the call. This encourages more coalescing.
748 // Later, AFTER aggressive, this live range will have to spill
749 // but the spiller handles slow-path calls very nicely.
750 } else {
751 lrg.AND( rm );
752 }
753 // Check for bound register masks
754 const RegMask &lrgmask = lrg.mask();
755 if( lrgmask.is_bound1() || lrgmask.is_bound2() )
756 lrg._is_bound = 1;
757 // If this use of a double forces a mis-aligned double,
758 // flag as '_fat_proj' - really flag as allowing misalignment
759 // AND changes how we count interferences. A mis-aligned
760 // double can interfere with TWO aligned pairs, or effectively
761 // FOUR registers!
762 if( lrg.num_regs() == 2 && !lrg._fat_proj && rm.is_misaligned_Pair() ) {
763 lrg._fat_proj = 1;
764 lrg._is_bound = 1;
765 }
766 // if the LRG is an unaligned pair, we will have to spill
767 // so clear the LRG's register mask if it is not already spilled
768 if ( !n->is_SpillCopy() &&
769 (lrg._def == NULL || lrg.is_multidef() || !lrg._def->is_SpillCopy()) &&
770 lrgmask.is_misaligned_Pair()) {
771 lrg.Clear();
772 }
773
774 // Check for maximum frequency value
775 if( lrg._maxfreq < b->_freq )
776 lrg._maxfreq = b->_freq;
777
778 } // End for all allocated inputs
779 } // end for all instructions
780 } // end for all blocks
781
782 // Final per-liverange setup
783 for( uint i2=0; i2<_maxlrg; i2++ ) {
784 LRG &lrg = lrgs(i2);
785 if( lrg.num_regs() == 2 && !lrg._fat_proj )
786 lrg.ClearToPairs();
787 lrg.compute_set_mask_size();
788 if( lrg.not_free() ) { // Handle case where we lose from the start
789 lrg.set_reg(OptoReg::Name(LRG::SPILL_REG));
790 lrg._direct_conflict = 1;
791 }
792 lrg.set_degree(0); // no neighbors in IFG yet
793 }
794 }
795
796 //------------------------------set_was_low------------------------------------
797 // Set the was-lo-degree bit. Conservative coalescing should not change the
798 // colorability of the graph. If any live range was of low-degree before
799 // coalescing, it should Simplify. This call sets the was-lo-degree bit.
800 // The bit is checked in Simplify.
801 void PhaseChaitin::set_was_low() {
802 #ifdef ASSERT
803 for( uint i = 1; i < _maxlrg; i++ ) {
804 int size = lrgs(i).num_regs();
805 uint old_was_lo = lrgs(i)._was_lo;
806 lrgs(i)._was_lo = 0;
807 if( lrgs(i).lo_degree() ) {
808 lrgs(i)._was_lo = 1; // Trivially of low degree
809 } else { // Else check the Brigg's assertion
810 // Brigg's observation is that the lo-degree neighbors of a
811 // hi-degree live range will not interfere with the color choices
812 // of said hi-degree live range. The Simplify reverse-stack-coloring
813 // order takes care of the details. Hence you do not have to count
814 // low-degree neighbors when determining if this guy colors.
815 int briggs_degree = 0;
816 IndexSet *s = _ifg->neighbors(i);
817 IndexSetIterator elements(s);
818 uint lidx;
819 while((lidx = elements.next()) != 0) {
820 if( !lrgs(lidx).lo_degree() )
821 briggs_degree += MAX2(size,lrgs(lidx).num_regs());
822 }
823 if( briggs_degree < lrgs(i).degrees_of_freedom() )
824 lrgs(i)._was_lo = 1; // Low degree via the briggs assertion
825 }
826 assert(old_was_lo <= lrgs(i)._was_lo, "_was_lo may not decrease");
827 }
828 #endif
829 }
830
831 #define REGISTER_CONSTRAINED 16
832
833 //------------------------------cache_lrg_info---------------------------------
834 // Compute cost/area ratio, in case we spill. Build the lo-degree list.
835 void PhaseChaitin::cache_lrg_info( ) {
836
837 for( uint i = 1; i < _maxlrg; i++ ) {
838 LRG &lrg = lrgs(i);
839
840 // Check for being of low degree: means we can be trivially colored.
841 // Low degree, dead or must-spill guys just get to simplify right away
842 if( lrg.lo_degree() ||
843 !lrg.alive() ||
844 lrg._must_spill ) {
845 // Split low degree list into those guys that must get a
846 // register and those that can go to register or stack.
847 // The idea is LRGs that can go register or stack color first when
848 // they have a good chance of getting a register. The register-only
849 // lo-degree live ranges always get a register.
850 OptoReg::Name hi_reg = lrg.mask().find_last_elem();
851 if( OptoReg::is_stack(hi_reg)) { // Can go to stack?
852 lrg._next = _lo_stk_degree;
853 _lo_stk_degree = i;
854 } else {
855 lrg._next = _lo_degree;
856 _lo_degree = i;
857 }
858 } else { // Else high degree
859 lrgs(_hi_degree)._prev = i;
860 lrg._next = _hi_degree;
861 lrg._prev = 0;
862 _hi_degree = i;
863 }
864 }
865 }
866
867 //------------------------------Pre-Simplify-----------------------------------
868 // Simplify the IFG by removing LRGs of low degree that have NO copies
869 void PhaseChaitin::Pre_Simplify( ) {
870
871 // Warm up the lo-degree no-copy list
872 int lo_no_copy = 0;
873 for( uint i = 1; i < _maxlrg; i++ ) {
874 if( (lrgs(i).lo_degree() && !lrgs(i)._has_copy) ||
875 !lrgs(i).alive() ||
876 lrgs(i)._must_spill ) {
877 lrgs(i)._next = lo_no_copy;
878 lo_no_copy = i;
879 }
880 }
881
882 while( lo_no_copy ) {
883 uint lo = lo_no_copy;
884 lo_no_copy = lrgs(lo)._next;
885 int size = lrgs(lo).num_regs();
886
887 // Put the simplified guy on the simplified list.
888 lrgs(lo)._next = _simplified;
889 _simplified = lo;
890
891 // Yank this guy from the IFG.
892 IndexSet *adj = _ifg->remove_node( lo );
893
894 // If any neighbors' degrees fall below their number of
895 // allowed registers, then put that neighbor on the low degree
896 // list. Note that 'degree' can only fall and 'numregs' is
897 // unchanged by this action. Thus the two are equal at most once,
898 // so LRGs hit the lo-degree worklists at most once.
899 IndexSetIterator elements(adj);
900 uint neighbor;
901 while ((neighbor = elements.next()) != 0) {
902 LRG *n = &lrgs(neighbor);
903 assert( _ifg->effective_degree(neighbor) == n->degree(), "" );
904
905 // Check for just becoming of-low-degree
906 if( n->just_lo_degree() && !n->_has_copy ) {
907 assert(!(*_ifg->_yanked)[neighbor],"Cannot move to lo degree twice");
908 // Put on lo-degree list
909 n->_next = lo_no_copy;
910 lo_no_copy = neighbor;
911 }
912 }
913 } // End of while lo-degree no_copy worklist not empty
914
915 // No more lo-degree no-copy live ranges to simplify
916 }
917
918 //------------------------------Simplify---------------------------------------
919 // Simplify the IFG by removing LRGs of low degree.
920 void PhaseChaitin::Simplify( ) {
921
922 while( 1 ) { // Repeat till simplified it all
923 // May want to explore simplifying lo_degree before _lo_stk_degree.
924 // This might result in more spills coloring into registers during
925 // Select().
926 while( _lo_degree || _lo_stk_degree ) {
927 // If possible, pull from lo_stk first
928 uint lo;
929 if( _lo_degree ) {
930 lo = _lo_degree;
931 _lo_degree = lrgs(lo)._next;
932 } else {
933 lo = _lo_stk_degree;
934 _lo_stk_degree = lrgs(lo)._next;
935 }
936
937 // Put the simplified guy on the simplified list.
938 lrgs(lo)._next = _simplified;
939 _simplified = lo;
940 // If this guy is "at risk" then mark his current neighbors
941 if( lrgs(lo)._at_risk ) {
942 IndexSetIterator elements(_ifg->neighbors(lo));
943 uint datum;
944 while ((datum = elements.next()) != 0) {
945 lrgs(datum)._risk_bias = lo;
946 }
947 }
948
949 // Yank this guy from the IFG.
950 IndexSet *adj = _ifg->remove_node( lo );
951
952 // If any neighbors' degrees fall below their number of
953 // allowed registers, then put that neighbor on the low degree
954 // list. Note that 'degree' can only fall and 'numregs' is
955 // unchanged by this action. Thus the two are equal at most once,
956 // so LRGs hit the lo-degree worklist at most once.
957 IndexSetIterator elements(adj);
958 uint neighbor;
959 while ((neighbor = elements.next()) != 0) {
960 LRG *n = &lrgs(neighbor);
961 #ifdef ASSERT
962 if( VerifyOpto ) {
963 assert( _ifg->effective_degree(neighbor) == n->degree(), "" );
964 }
965 #endif
966
967 // Check for just becoming of-low-degree just counting registers.
968 // _must_spill live ranges are already on the low degree list.
969 if( n->just_lo_degree() && !n->_must_spill ) {
970 assert(!(*_ifg->_yanked)[neighbor],"Cannot move to lo degree twice");
971 // Pull from hi-degree list
972 uint prev = n->_prev;
973 uint next = n->_next;
974 if( prev ) lrgs(prev)._next = next;
975 else _hi_degree = next;
976 lrgs(next)._prev = prev;
977 n->_next = _lo_degree;
978 _lo_degree = neighbor;
979 }
980 }
981 } // End of while lo-degree/lo_stk_degree worklist not empty
982
983 // Check for got everything: is hi-degree list empty?
984 if( !_hi_degree ) break;
985
986 // Time to pick a potential spill guy
987 uint lo_score = _hi_degree;
988 double score = lrgs(lo_score).score();
989 double area = lrgs(lo_score)._area;
990
991 // Find cheapest guy
992 debug_only( int lo_no_simplify=0; );
993 for( uint i = _hi_degree; i; i = lrgs(i)._next ) {
994 assert( !(*_ifg->_yanked)[i], "" );
995 // It's just vaguely possible to move hi-degree to lo-degree without
996 // going through a just-lo-degree stage: If you remove a double from
997 // a float live range it's degree will drop by 2 and you can skip the
998 // just-lo-degree stage. It's very rare (shows up after 5000+ methods
999 // in -Xcomp of Java2Demo). So just choose this guy to simplify next.
1000 if( lrgs(i).lo_degree() ) {
1001 lo_score = i;
1002 break;
1003 }
1004 debug_only( if( lrgs(i)._was_lo ) lo_no_simplify=i; );
1005 double iscore = lrgs(i).score();
1006 double iarea = lrgs(i)._area;
1007
1008 // Compare cost/area of i vs cost/area of lo_score. Smaller cost/area
1009 // wins. Ties happen because all live ranges in question have spilled
1010 // a few times before and the spill-score adds a huge number which
1011 // washes out the low order bits. We are choosing the lesser of 2
1012 // evils; in this case pick largest area to spill.
1013 if( iscore < score ||
1014 (iscore == score && iarea > area && lrgs(lo_score)._was_spilled2) ) {
1015 lo_score = i;
1016 score = iscore;
1017 area = iarea;
1018 }
1019 }
1020 LRG *lo_lrg = &lrgs(lo_score);
1021 // The live range we choose for spilling is either hi-degree, or very
1022 // rarely it can be low-degree. If we choose a hi-degree live range
1023 // there better not be any lo-degree choices.
1024 assert( lo_lrg->lo_degree() || !lo_no_simplify, "Live range was lo-degree before coalesce; should simplify" );
1025
1026 // Pull from hi-degree list
1027 uint prev = lo_lrg->_prev;
1028 uint next = lo_lrg->_next;
1029 if( prev ) lrgs(prev)._next = next;
1030 else _hi_degree = next;
1031 lrgs(next)._prev = prev;
1032 // Jam him on the lo-degree list, despite his high degree.
1033 // Maybe he'll get a color, and maybe he'll spill.
1034 // Only Select() will know.
1035 lrgs(lo_score)._at_risk = true;
1036 _lo_degree = lo_score;
1037 lo_lrg->_next = 0;
1038
1039 } // End of while not simplified everything
1040
1041 }
1042
1043 //------------------------------bias_color-------------------------------------
1044 // Choose a color using the biasing heuristic
1045 OptoReg::Name PhaseChaitin::bias_color( LRG &lrg, int chunk ) {
1046
1047 // Check for "at_risk" LRG's
1048 uint risk_lrg = Find(lrg._risk_bias);
1049 if( risk_lrg != 0 ) {
1050 // Walk the colored neighbors of the "at_risk" candidate
1051 // Choose a color which is both legal and already taken by a neighbor
1052 // of the "at_risk" candidate in order to improve the chances of the
1053 // "at_risk" candidate of coloring
1054 IndexSetIterator elements(_ifg->neighbors(risk_lrg));
1055 uint datum;
1056 while ((datum = elements.next()) != 0) {
1057 OptoReg::Name reg = lrgs(datum).reg();
1058 // If this LRG's register is legal for us, choose it
1059 if( reg >= chunk && reg < chunk + RegMask::CHUNK_SIZE &&
1060 lrg.mask().Member(OptoReg::add(reg,-chunk)) &&
1061 (lrg.num_regs()==1 || // either size 1
1062 (reg&1) == 1) ) // or aligned (adjacent reg is available since we already cleared-to-pairs)
1063 return reg;
1064 }
1065 }
1066
1067 uint copy_lrg = Find(lrg._copy_bias);
1068 if( copy_lrg != 0 ) {
1069 // If he has a color,
1070 if( !(*(_ifg->_yanked))[copy_lrg] ) {
1071 OptoReg::Name reg = lrgs(copy_lrg).reg();
1072 // And it is legal for you,
1073 if( reg >= chunk && reg < chunk + RegMask::CHUNK_SIZE &&
1074 lrg.mask().Member(OptoReg::add(reg,-chunk)) &&
1075 (lrg.num_regs()==1 || // either size 1
1076 (reg&1) == 1) ) // or aligned (adjacent reg is available since we already cleared-to-pairs)
1077 return reg;
1078 } else if( chunk == 0 ) {
1079 // Choose a color which is legal for him
1080 RegMask tempmask = lrg.mask();
1081 tempmask.AND(lrgs(copy_lrg).mask());
1082 OptoReg::Name reg;
1083 if( lrg.num_regs() == 1 ) {
1084 reg = tempmask.find_first_elem();
1085 } else {
1086 tempmask.ClearToPairs();
1087 reg = tempmask.find_first_pair();
1088 }
1089 if( OptoReg::is_valid(reg) )
1090 return reg;
1091 }
1092 }
1093
1094 // If no bias info exists, just go with the register selection ordering
1095 if( lrg.num_regs() == 2 ) {
1096 // Find an aligned pair
1097 return OptoReg::add(lrg.mask().find_first_pair(),chunk);
1098 }
1099
1100 // CNC - Fun hack. Alternate 1st and 2nd selection. Enables post-allocate
1101 // copy removal to remove many more copies, by preventing a just-assigned
1102 // register from being repeatedly assigned.
1103 OptoReg::Name reg = lrg.mask().find_first_elem();
1104 if( (++_alternate & 1) && OptoReg::is_valid(reg) ) {
1105 // This 'Remove; find; Insert' idiom is an expensive way to find the
1106 // SECOND element in the mask.
1107 lrg.Remove(reg);
1108 OptoReg::Name reg2 = lrg.mask().find_first_elem();
1109 lrg.Insert(reg);
1110 if( OptoReg::is_reg(reg2))
1111 reg = reg2;
1112 }
1113 return OptoReg::add( reg, chunk );
1114 }
1115
1116 //------------------------------choose_color-----------------------------------
1117 // Choose a color in the current chunk
1118 OptoReg::Name PhaseChaitin::choose_color( LRG &lrg, int chunk ) {
1119 assert( C->in_preserve_stack_slots() == 0 || chunk != 0 || lrg._is_bound || lrg.mask().is_bound1() || !lrg.mask().Member(OptoReg::Name(_matcher._old_SP-1)), "must not allocate stack0 (inside preserve area)");
1120 assert(C->out_preserve_stack_slots() == 0 || chunk != 0 || lrg._is_bound || lrg.mask().is_bound1() || !lrg.mask().Member(OptoReg::Name(_matcher._old_SP+0)), "must not allocate stack0 (inside preserve area)");
1121
1122 if( lrg.num_regs() == 1 || // Common Case
1123 !lrg._fat_proj ) // Aligned+adjacent pairs ok
1124 // Use a heuristic to "bias" the color choice
1125 return bias_color(lrg, chunk);
1126
1127 assert( lrg.num_regs() >= 2, "dead live ranges do not color" );
1128
1129 // Fat-proj case or misaligned double argument.
1130 assert(lrg.compute_mask_size() == lrg.num_regs() ||
1131 lrg.num_regs() == 2,"fat projs exactly color" );
1132 assert( !chunk, "always color in 1st chunk" );
1133 // Return the highest element in the set.
1134 return lrg.mask().find_last_elem();
1135 }
1136
1137 //------------------------------Select-----------------------------------------
1138 // Select colors by re-inserting LRGs back into the IFG. LRGs are re-inserted
1139 // in reverse order of removal. As long as nothing of hi-degree was yanked,
1140 // everything going back is guaranteed a color. Select that color. If some
1141 // hi-degree LRG cannot get a color then we record that we must spill.
1142 uint PhaseChaitin::Select( ) {
1143 uint spill_reg = LRG::SPILL_REG;
1144 _max_reg = OptoReg::Name(0); // Past max register used
1145 while( _simplified ) {
1146 // Pull next LRG from the simplified list - in reverse order of removal
1147 uint lidx = _simplified;
1148 LRG *lrg = &lrgs(lidx);
1149 _simplified = lrg->_next;
1150
1151
1152 #ifndef PRODUCT
1153 if (trace_spilling()) {
1154 ttyLocker ttyl;
1155 tty->print_cr("L%d selecting degree %d degrees_of_freedom %d", lidx, lrg->degree(),
1156 lrg->degrees_of_freedom());
1157 lrg->dump();
1158 }
1159 #endif
1160
1161 // Re-insert into the IFG
1162 _ifg->re_insert(lidx);
1163 if( !lrg->alive() ) continue;
1164 // capture allstackedness flag before mask is hacked
1165 const int is_allstack = lrg->mask().is_AllStack();
1166
1167 // Yeah, yeah, yeah, I know, I know. I can refactor this
1168 // to avoid the GOTO, although the refactored code will not
1169 // be much clearer. We arrive here IFF we have a stack-based
1170 // live range that cannot color in the current chunk, and it
1171 // has to move into the next free stack chunk.
1172 int chunk = 0; // Current chunk is first chunk
1173 retry_next_chunk:
1174
1175 // Remove neighbor colors
1176 IndexSet *s = _ifg->neighbors(lidx);
1177
1178 debug_only(RegMask orig_mask = lrg->mask();)
1179 IndexSetIterator elements(s);
1180 uint neighbor;
1181 while ((neighbor = elements.next()) != 0) {
1182 // Note that neighbor might be a spill_reg. In this case, exclusion
1183 // of its color will be a no-op, since the spill_reg chunk is in outer
1184 // space. Also, if neighbor is in a different chunk, this exclusion
1185 // will be a no-op. (Later on, if lrg runs out of possible colors in
1186 // its chunk, a new chunk of color may be tried, in which case
1187 // examination of neighbors is started again, at retry_next_chunk.)
1188 LRG &nlrg = lrgs(neighbor);
1189 OptoReg::Name nreg = nlrg.reg();
1190 // Only subtract masks in the same chunk
1191 if( nreg >= chunk && nreg < chunk + RegMask::CHUNK_SIZE ) {
1192 #ifndef PRODUCT
1193 uint size = lrg->mask().Size();
1194 RegMask rm = lrg->mask();
1195 #endif
1196 lrg->SUBTRACT(nlrg.mask());
1197 #ifndef PRODUCT
1198 if (trace_spilling() && lrg->mask().Size() != size) {
1199 ttyLocker ttyl;
1200 tty->print("L%d ", lidx);
1201 rm.dump();
1202 tty->print(" intersected L%d ", neighbor);
1203 nlrg.mask().dump();
1204 tty->print(" removed ");
1205 rm.SUBTRACT(lrg->mask());
1206 rm.dump();
1207 tty->print(" leaving ");
1208 lrg->mask().dump();
1209 tty->cr();
1210 }
1211 #endif
1212 }
1213 }
1214 //assert(is_allstack == lrg->mask().is_AllStack(), "nbrs must not change AllStackedness");
1215 // Aligned pairs need aligned masks
1216 if( lrg->num_regs() == 2 && !lrg->_fat_proj )
1217 lrg->ClearToPairs();
1218
1219 // Check if a color is available and if so pick the color
1220 OptoReg::Name reg = choose_color( *lrg, chunk );
1221 #ifdef SPARC
1222 debug_only(lrg->compute_set_mask_size());
1223 assert(lrg->num_regs() != 2 || lrg->is_bound() || is_even(reg-1), "allocate all doubles aligned");
1224 #endif
1225
1226 //---------------
1227 // If we fail to color and the AllStack flag is set, trigger
1228 // a chunk-rollover event
1229 if(!OptoReg::is_valid(OptoReg::add(reg,-chunk)) && is_allstack) {
1230 // Bump register mask up to next stack chunk
1231 chunk += RegMask::CHUNK_SIZE;
1232 lrg->Set_All();
1233
1234 goto retry_next_chunk;
1235 }
1236
1237 //---------------
1238 // Did we get a color?
1239 else if( OptoReg::is_valid(reg)) {
1240 #ifndef PRODUCT
1241 RegMask avail_rm = lrg->mask();
1242 #endif
1243
1244 // Record selected register
1245 lrg->set_reg(reg);
1246
1247 if( reg >= _max_reg ) // Compute max register limit
1248 _max_reg = OptoReg::add(reg,1);
1249 // Fold reg back into normal space
1250 reg = OptoReg::add(reg,-chunk);
1251
1252 // If the live range is not bound, then we actually had some choices
1253 // to make. In this case, the mask has more bits in it than the colors
1254 // choosen. Restrict the mask to just what was picked.
1255 if( lrg->num_regs() == 1 ) { // Size 1 live range
1256 lrg->Clear(); // Clear the mask
1257 lrg->Insert(reg); // Set regmask to match selected reg
1258 lrg->set_mask_size(1);
1259 } else if( !lrg->_fat_proj ) {
1260 // For pairs, also insert the low bit of the pair
1261 assert( lrg->num_regs() == 2, "unbound fatproj???" );
1262 lrg->Clear(); // Clear the mask
1263 lrg->Insert(reg); // Set regmask to match selected reg
1264 lrg->Insert(OptoReg::add(reg,-1));
1265 lrg->set_mask_size(2);
1266 } else { // Else fatproj
1267 // mask must be equal to fatproj bits, by definition
1268 }
1269 #ifndef PRODUCT
1270 if (trace_spilling()) {
1271 ttyLocker ttyl;
1272 tty->print("L%d selected ", lidx);
1273 lrg->mask().dump();
1274 tty->print(" from ");
1275 avail_rm.dump();
1276 tty->cr();
1277 }
1278 #endif
1279 // Note that reg is the highest-numbered register in the newly-bound mask.
1280 } // end color available case
1281
1282 //---------------
1283 // Live range is live and no colors available
1284 else {
1285 assert( lrg->alive(), "" );
1286 assert( !lrg->_fat_proj || lrg->is_multidef() ||
1287 lrg->_def->outcnt() > 0, "fat_proj cannot spill");
1288 assert( !orig_mask.is_AllStack(), "All Stack does not spill" );
1289
1290 // Assign the special spillreg register
1291 lrg->set_reg(OptoReg::Name(spill_reg++));
1292 // Do not empty the regmask; leave mask_size lying around
1293 // for use during Spilling
1294 #ifndef PRODUCT
1295 if( trace_spilling() ) {
1296 ttyLocker ttyl;
1297 tty->print("L%d spilling with neighbors: ", lidx);
1298 s->dump();
1299 debug_only(tty->print(" original mask: "));
1300 debug_only(orig_mask.dump());
1301 dump_lrg(lidx);
1302 }
1303 #endif
1304 } // end spill case
1305
1306 }
1307
1308 return spill_reg-LRG::SPILL_REG; // Return number of spills
1309 }
1310
1311
1312 //------------------------------copy_was_spilled-------------------------------
1313 // Copy 'was_spilled'-edness from the source Node to the dst Node.
1314 void PhaseChaitin::copy_was_spilled( Node *src, Node *dst ) {
1315 if( _spilled_once.test(src->_idx) ) {
1316 _spilled_once.set(dst->_idx);
1317 lrgs(Find(dst))._was_spilled1 = 1;
1318 if( _spilled_twice.test(src->_idx) ) {
1319 _spilled_twice.set(dst->_idx);
1320 lrgs(Find(dst))._was_spilled2 = 1;
1321 }
1322 }
1323 }
1324
1325 //------------------------------set_was_spilled--------------------------------
1326 // Set the 'spilled_once' or 'spilled_twice' flag on a node.
1327 void PhaseChaitin::set_was_spilled( Node *n ) {
1328 if( _spilled_once.test_set(n->_idx) )
1329 _spilled_twice.set(n->_idx);
1330 }
1331
1332 //------------------------------fixup_spills-----------------------------------
1333 // Convert Ideal spill instructions into proper FramePtr + offset Loads and
1334 // Stores. Use-def chains are NOT preserved, but Node->LRG->reg maps are.
1335 void PhaseChaitin::fixup_spills() {
1336 // This function does only cisc spill work.
1337 if( !UseCISCSpill ) return;
1338
1339 NOT_PRODUCT( Compile::TracePhase t3("fixupSpills", &_t_fixupSpills, TimeCompiler); )
1340
1341 // Grab the Frame Pointer
1342 Node *fp = _cfg._broot->head()->in(1)->in(TypeFunc::FramePtr);
1343
1344 // For all blocks
1345 for( uint i = 0; i < _cfg._num_blocks; i++ ) {
1346 Block *b = _cfg._blocks[i];
1347
1348 // For all instructions in block
1349 uint last_inst = b->end_idx();
1350 for( uint j = 1; j <= last_inst; j++ ) {
1351 Node *n = b->_nodes[j];
1352
1353 // Dead instruction???
1354 assert( n->outcnt() != 0 ||// Nothing dead after post alloc
1355 C->top() == n || // Or the random TOP node
1356 n->is_Proj(), // Or a fat-proj kill node
1357 "No dead instructions after post-alloc" );
1358
1359 int inp = n->cisc_operand();
1360 if( inp != AdlcVMDeps::Not_cisc_spillable ) {
1361 // Convert operand number to edge index number
1362 MachNode *mach = n->as_Mach();
1363 inp = mach->operand_index(inp);
1364 Node *src = n->in(inp); // Value to load or store
1365 LRG &lrg_cisc = lrgs( Find_const(src) );
1366 OptoReg::Name src_reg = lrg_cisc.reg();
1367 // Doubles record the HIGH register of an adjacent pair.
1368 src_reg = OptoReg::add(src_reg,1-lrg_cisc.num_regs());
1369 if( OptoReg::is_stack(src_reg) ) { // If input is on stack
1370 // This is a CISC Spill, get stack offset and construct new node
1371 #ifndef PRODUCT
1372 if( TraceCISCSpill ) {
1373 tty->print(" reg-instr: ");
1374 n->dump();
1375 }
1376 #endif
1377 int stk_offset = reg2offset(src_reg);
1378 // Bailout if we might exceed node limit when spilling this instruction
1379 C->check_node_count(0, "out of nodes fixing spills");
1380 if (C->failing()) return;
1381 // Transform node
1382 MachNode *cisc = mach->cisc_version(stk_offset, C)->as_Mach();
1383 cisc->set_req(inp,fp); // Base register is frame pointer
1384 if( cisc->oper_input_base() > 1 && mach->oper_input_base() <= 1 ) {
1385 assert( cisc->oper_input_base() == 2, "Only adding one edge");
1386 cisc->ins_req(1,src); // Requires a memory edge
1387 }
1388 b->_nodes.map(j,cisc); // Insert into basic block
1389 n->subsume_by(cisc); // Correct graph
1390 //
1391 ++_used_cisc_instructions;
1392 #ifndef PRODUCT
1393 if( TraceCISCSpill ) {
1394 tty->print(" cisc-instr: ");
1395 cisc->dump();
1396 }
1397 #endif
1398 } else {
1399 #ifndef PRODUCT
1400 if( TraceCISCSpill ) {
1401 tty->print(" using reg-instr: ");
1402 n->dump();
1403 }
1404 #endif
1405 ++_unused_cisc_instructions; // input can be on stack
1406 }
1407 }
1408
1409 } // End of for all instructions
1410
1411 } // End of for all blocks
1412 }
1413
1414 //------------------------------find_base_for_derived--------------------------
1415 // Helper to stretch above; recursively discover the base Node for a
1416 // given derived Node. Easy for AddP-related machine nodes, but needs
1417 // to be recursive for derived Phis.
1418 Node *PhaseChaitin::find_base_for_derived( Node **derived_base_map, Node *derived, uint &maxlrg ) {
1419 // See if already computed; if so return it
1420 if( derived_base_map[derived->_idx] )
1421 return derived_base_map[derived->_idx];
1422
1423 // See if this happens to be a base.
1424 // NOTE: we use TypePtr instead of TypeOopPtr because we can have
1425 // pointers derived from NULL! These are always along paths that
1426 // can't happen at run-time but the optimizer cannot deduce it so
1427 // we have to handle it gracefully.
1428 const TypePtr *tj = derived->bottom_type()->isa_ptr();
1429 // If its an OOP with a non-zero offset, then it is derived.
1430 if( tj->_offset == 0 ) {
1431 derived_base_map[derived->_idx] = derived;
1432 return derived;
1433 }
1434 // Derived is NULL+offset? Base is NULL!
1435 if( derived->is_Con() ) {
1436 Node *base = new (C, 1) ConPNode( TypePtr::NULL_PTR );
1437 uint no_lidx = 0; // an unmatched constant in debug info has no LRG
1438 _names.extend(base->_idx, no_lidx);
1439 derived_base_map[derived->_idx] = base;
1440 return base;
1441 }
1442
1443 // Check for AddP-related opcodes
1444 if( !derived->is_Phi() ) {
1445 assert( derived->as_Mach()->ideal_Opcode() == Op_AddP, "" );
1446 Node *base = derived->in(AddPNode::Base);
1447 derived_base_map[derived->_idx] = base;
1448 return base;
1449 }
1450
1451 // Recursively find bases for Phis.
1452 // First check to see if we can avoid a base Phi here.
1453 Node *base = find_base_for_derived( derived_base_map, derived->in(1),maxlrg);
1454 uint i;
1455 for( i = 2; i < derived->req(); i++ )
1456 if( base != find_base_for_derived( derived_base_map,derived->in(i),maxlrg))
1457 break;
1458 // Went to the end without finding any different bases?
1459 if( i == derived->req() ) { // No need for a base Phi here
1460 derived_base_map[derived->_idx] = base;
1461 return base;
1462 }
1463
1464 // Now we see we need a base-Phi here to merge the bases
1465 base = new (C, derived->req()) PhiNode( derived->in(0), base->bottom_type() );
1466 for( i = 1; i < derived->req(); i++ )
1467 base->init_req(i, find_base_for_derived(derived_base_map, derived->in(i), maxlrg));
1468
1469 // Search the current block for an existing base-Phi
1470 Block *b = _cfg._bbs[derived->_idx];
1471 for( i = 1; i <= b->end_idx(); i++ ) {// Search for matching Phi
1472 Node *phi = b->_nodes[i];
1473 if( !phi->is_Phi() ) { // Found end of Phis with no match?
1474 b->_nodes.insert( i, base ); // Must insert created Phi here as base
1475 _cfg._bbs.map( base->_idx, b );
1476 new_lrg(base,maxlrg++);
1477 break;
1478 }
1479 // See if Phi matches.
1480 uint j;
1481 for( j = 1; j < base->req(); j++ )
1482 if( phi->in(j) != base->in(j) &&
1483 !(phi->in(j)->is_Con() && base->in(j)->is_Con()) ) // allow different NULLs
1484 break;
1485 if( j == base->req() ) { // All inputs match?
1486 base = phi; // Then use existing 'phi' and drop 'base'
1487 break;
1488 }
1489 }
1490
1491
1492 // Cache info for later passes
1493 derived_base_map[derived->_idx] = base;
1494 return base;
1495 }
1496
1497
1498 //------------------------------stretch_base_pointer_live_ranges---------------
1499 // At each Safepoint, insert extra debug edges for each pair of derived value/
1500 // base pointer that is live across the Safepoint for oopmap building. The
1501 // edge pairs get added in after sfpt->jvmtail()->oopoff(), but are in the
1502 // required edge set.
1503 bool PhaseChaitin::stretch_base_pointer_live_ranges( ResourceArea *a ) {
1504 int must_recompute_live = false;
1505 uint maxlrg = _maxlrg;
1506 Node **derived_base_map = (Node**)a->Amalloc(sizeof(Node*)*C->unique());
1507 memset( derived_base_map, 0, sizeof(Node*)*C->unique() );
1508
1509 // For all blocks in RPO do...
1510 for( uint i=0; i<_cfg._num_blocks; i++ ) {
1511 Block *b = _cfg._blocks[i];
1512 // Note use of deep-copy constructor. I cannot hammer the original
1513 // liveout bits, because they are needed by the following coalesce pass.
1514 IndexSet liveout(_live->live(b));
1515
1516 for( uint j = b->end_idx() + 1; j > 1; j-- ) {
1517 Node *n = b->_nodes[j-1];
1518
1519 // Pre-split compares of loop-phis. Loop-phis form a cycle we would
1520 // like to see in the same register. Compare uses the loop-phi and so
1521 // extends its live range BUT cannot be part of the cycle. If this
1522 // extended live range overlaps with the update of the loop-phi value
1523 // we need both alive at the same time -- which requires at least 1
1524 // copy. But because Intel has only 2-address registers we end up with
1525 // at least 2 copies, one before the loop-phi update instruction and
1526 // one after. Instead we split the input to the compare just after the
1527 // phi.
1528 if( n->is_Mach() && n->as_Mach()->ideal_Opcode() == Op_CmpI ) {
1529 Node *phi = n->in(1);
1530 if( phi->is_Phi() && phi->as_Phi()->region()->is_Loop() ) {
1531 Block *phi_block = _cfg._bbs[phi->_idx];
1532 if( _cfg._bbs[phi_block->pred(2)->_idx] == b ) {
1533 const RegMask *mask = C->matcher()->idealreg2spillmask[Op_RegI];
1534 Node *spill = new (C) MachSpillCopyNode( phi, *mask, *mask );
1535 insert_proj( phi_block, 1, spill, maxlrg++ );
1536 n->set_req(1,spill);
1537 must_recompute_live = true;
1538 }
1539 }
1540 }
1541
1542 // Get value being defined
1543 uint lidx = n2lidx(n);
1544 if( lidx && lidx < _maxlrg /* Ignore the occasional brand-new live range */) {
1545 // Remove from live-out set
1546 liveout.remove(lidx);
1547
1548 // Copies do not define a new value and so do not interfere.
1549 // Remove the copies source from the liveout set before interfering.
1550 uint idx = n->is_Copy();
1551 if( idx ) liveout.remove( n2lidx(n->in(idx)) );
1552 }
1553
1554 // Found a safepoint?
1555 JVMState *jvms = n->jvms();
1556 if( jvms ) {
1557 // Now scan for a live derived pointer
1558 IndexSetIterator elements(&liveout);
1559 uint neighbor;
1560 while ((neighbor = elements.next()) != 0) {
1561 // Find reaching DEF for base and derived values
1562 // This works because we are still in SSA during this call.
1563 Node *derived = lrgs(neighbor)._def;
1564 const TypePtr *tj = derived->bottom_type()->isa_ptr();
1565 // If its an OOP with a non-zero offset, then it is derived.
1566 if( tj && tj->_offset != 0 && tj->isa_oop_ptr() ) {
1567 Node *base = find_base_for_derived( derived_base_map, derived, maxlrg );
1568 assert( base->_idx < _names.Size(), "" );
1569 // Add reaching DEFs of derived pointer and base pointer as a
1570 // pair of inputs
1571 n->add_req( derived );
1572 n->add_req( base );
1573
1574 // See if the base pointer is already live to this point.
1575 // Since I'm working on the SSA form, live-ness amounts to
1576 // reaching def's. So if I find the base's live range then
1577 // I know the base's def reaches here.
1578 if( (n2lidx(base) >= _maxlrg ||// (Brand new base (hence not live) or
1579 !liveout.member( n2lidx(base) ) ) && // not live) AND
1580 (n2lidx(base) > 0) && // not a constant
1581 _cfg._bbs[base->_idx] != b ) { // base not def'd in blk)
1582 // Base pointer is not currently live. Since I stretched
1583 // the base pointer to here and it crosses basic-block
1584 // boundaries, the global live info is now incorrect.
1585 // Recompute live.
1586 must_recompute_live = true;
1587 } // End of if base pointer is not live to debug info
1588 }
1589 } // End of scan all live data for derived ptrs crossing GC point
1590 } // End of if found a GC point
1591
1592 // Make all inputs live
1593 if( !n->is_Phi() ) { // Phi function uses come from prior block
1594 for( uint k = 1; k < n->req(); k++ ) {
1595 uint lidx = n2lidx(n->in(k));
1596 if( lidx < _maxlrg )
1597 liveout.insert( lidx );
1598 }
1599 }
1600
1601 } // End of forall instructions in block
1602 liveout.clear(); // Free the memory used by liveout.
1603
1604 } // End of forall blocks
1605 _maxlrg = maxlrg;
1606
1607 // If I created a new live range I need to recompute live
1608 if( maxlrg != _ifg->_maxlrg )
1609 must_recompute_live = true;
1610
1611 return must_recompute_live != 0;
1612 }
1613
1614
1615 //------------------------------add_reference----------------------------------
1616 // Extend the node to LRG mapping
1617 void PhaseChaitin::add_reference( const Node *node, const Node *old_node ) {
1618 _names.extend( node->_idx, n2lidx(old_node) );
1619 }
1620
1621 //------------------------------dump-------------------------------------------
1622 #ifndef PRODUCT
1623 void PhaseChaitin::dump( const Node *n ) const {
1624 uint r = (n->_idx < _names.Size() ) ? Find_const(n) : 0;
1625 tty->print("L%d",r);
1626 if( r && n->Opcode() != Op_Phi ) {
1627 if( _node_regs ) { // Got a post-allocation copy of allocation?
1628 tty->print("[");
1629 OptoReg::Name second = get_reg_second(n);
1630 if( OptoReg::is_valid(second) ) {
1631 if( OptoReg::is_reg(second) )
1632 tty->print("%s:",Matcher::regName[second]);
1633 else
1634 tty->print("%s+%d:",OptoReg::regname(OptoReg::c_frame_pointer), reg2offset_unchecked(second));
1635 }
1636 OptoReg::Name first = get_reg_first(n);
1637 if( OptoReg::is_reg(first) )
1638 tty->print("%s]",Matcher::regName[first]);
1639 else
1640 tty->print("%s+%d]",OptoReg::regname(OptoReg::c_frame_pointer), reg2offset_unchecked(first));
1641 } else
1642 n->out_RegMask().dump();
1643 }
1644 tty->print("/N%d\t",n->_idx);
1645 tty->print("%s === ", n->Name());
1646 uint k;
1647 for( k = 0; k < n->req(); k++) {
1648 Node *m = n->in(k);
1649 if( !m ) tty->print("_ ");
1650 else {
1651 uint r = (m->_idx < _names.Size() ) ? Find_const(m) : 0;
1652 tty->print("L%d",r);
1653 // Data MultiNode's can have projections with no real registers.
1654 // Don't die while dumping them.
1655 int op = n->Opcode();
1656 if( r && op != Op_Phi && op != Op_Proj && op != Op_SCMemProj) {
1657 if( _node_regs ) {
1658 tty->print("[");
1659 OptoReg::Name second = get_reg_second(n->in(k));
1660 if( OptoReg::is_valid(second) ) {
1661 if( OptoReg::is_reg(second) )
1662 tty->print("%s:",Matcher::regName[second]);
1663 else
1664 tty->print("%s+%d:",OptoReg::regname(OptoReg::c_frame_pointer),
1665 reg2offset_unchecked(second));
1666 }
1667 OptoReg::Name first = get_reg_first(n->in(k));
1668 if( OptoReg::is_reg(first) )
1669 tty->print("%s]",Matcher::regName[first]);
1670 else
1671 tty->print("%s+%d]",OptoReg::regname(OptoReg::c_frame_pointer),
1672 reg2offset_unchecked(first));
1673 } else
1674 n->in_RegMask(k).dump();
1675 }
1676 tty->print("/N%d ",m->_idx);
1677 }
1678 }
1679 if( k < n->len() && n->in(k) ) tty->print("| ");
1680 for( ; k < n->len(); k++ ) {
1681 Node *m = n->in(k);
1682 if( !m ) break;
1683 uint r = (m->_idx < _names.Size() ) ? Find_const(m) : 0;
1684 tty->print("L%d",r);
1685 tty->print("/N%d ",m->_idx);
1686 }
1687 if( n->is_Mach() ) n->as_Mach()->dump_spec(tty);
1688 else n->dump_spec(tty);
1689 if( _spilled_once.test(n->_idx ) ) {
1690 tty->print(" Spill_1");
1691 if( _spilled_twice.test(n->_idx ) )
1692 tty->print(" Spill_2");
1693 }
1694 tty->print("\n");
1695 }
1696
1697 void PhaseChaitin::dump( const Block * b ) const {
1698 b->dump_head( &_cfg._bbs );
1699
1700 // For all instructions
1701 for( uint j = 0; j < b->_nodes.size(); j++ )
1702 dump(b->_nodes[j]);
1703 // Print live-out info at end of block
1704 if( _live ) {
1705 tty->print("Liveout: ");
1706 IndexSet *live = _live->live(b);
1707 IndexSetIterator elements(live);
1708 tty->print("{");
1709 uint i;
1710 while ((i = elements.next()) != 0) {
1711 tty->print("L%d ", Find_const(i));
1712 }
1713 tty->print_cr("}");
1714 }
1715 tty->print("\n");
1716 }
1717
1718 void PhaseChaitin::dump() const {
1719 tty->print( "--- Chaitin -- argsize: %d framesize: %d ---\n",
1720 _matcher._new_SP, _framesize );
1721
1722 // For all blocks
1723 for( uint i = 0; i < _cfg._num_blocks; i++ )
1724 dump(_cfg._blocks[i]);
1725 // End of per-block dump
1726 tty->print("\n");
1727
1728 if (!_ifg) {
1729 tty->print("(No IFG.)\n");
1730 return;
1731 }
1732
1733 // Dump LRG array
1734 tty->print("--- Live RanGe Array ---\n");
1735 for(uint i2 = 1; i2 < _maxlrg; i2++ ) {
1736 tty->print("L%d: ",i2);
1737 if( i2 < _ifg->_maxlrg ) lrgs(i2).dump( );
1738 else tty->print("new LRG");
1739 }
1740 tty->print_cr("");
1741
1742 // Dump lo-degree list
1743 tty->print("Lo degree: ");
1744 for(uint i3 = _lo_degree; i3; i3 = lrgs(i3)._next )
1745 tty->print("L%d ",i3);
1746 tty->print_cr("");
1747
1748 // Dump lo-stk-degree list
1749 tty->print("Lo stk degree: ");
1750 for(uint i4 = _lo_stk_degree; i4; i4 = lrgs(i4)._next )
1751 tty->print("L%d ",i4);
1752 tty->print_cr("");
1753
1754 // Dump lo-degree list
1755 tty->print("Hi degree: ");
1756 for(uint i5 = _hi_degree; i5; i5 = lrgs(i5)._next )
1757 tty->print("L%d ",i5);
1758 tty->print_cr("");
1759 }
1760
1761 //------------------------------dump_degree_lists------------------------------
1762 void PhaseChaitin::dump_degree_lists() const {
1763 // Dump lo-degree list
1764 tty->print("Lo degree: ");
1765 for( uint i = _lo_degree; i; i = lrgs(i)._next )
1766 tty->print("L%d ",i);
1767 tty->print_cr("");
1768
1769 // Dump lo-stk-degree list
1770 tty->print("Lo stk degree: ");
1771 for(uint i2 = _lo_stk_degree; i2; i2 = lrgs(i2)._next )
1772 tty->print("L%d ",i2);
1773 tty->print_cr("");
1774
1775 // Dump lo-degree list
1776 tty->print("Hi degree: ");
1777 for(uint i3 = _hi_degree; i3; i3 = lrgs(i3)._next )
1778 tty->print("L%d ",i3);
1779 tty->print_cr("");
1780 }
1781
1782 //------------------------------dump_simplified--------------------------------
1783 void PhaseChaitin::dump_simplified() const {
1784 tty->print("Simplified: ");
1785 for( uint i = _simplified; i; i = lrgs(i)._next )
1786 tty->print("L%d ",i);
1787 tty->print_cr("");
1788 }
1789
1790 static char *print_reg( OptoReg::Name reg, const PhaseChaitin *pc, char *buf ) {
1791 if ((int)reg < 0)
1792 sprintf(buf, "<OptoReg::%d>", (int)reg);
1793 else if (OptoReg::is_reg(reg))
1794 strcpy(buf, Matcher::regName[reg]);
1795 else
1796 sprintf(buf,"%s + #%d",OptoReg::regname(OptoReg::c_frame_pointer),
1797 pc->reg2offset(reg));
1798 return buf+strlen(buf);
1799 }
1800
1801 //------------------------------dump_register----------------------------------
1802 // Dump a register name into a buffer. Be intelligent if we get called
1803 // before allocation is complete.
1804 char *PhaseChaitin::dump_register( const Node *n, char *buf ) const {
1805 if( !this ) { // Not got anything?
1806 sprintf(buf,"N%d",n->_idx); // Then use Node index
1807 } else if( _node_regs ) {
1808 // Post allocation, use direct mappings, no LRG info available
1809 print_reg( get_reg_first(n), this, buf );
1810 } else {
1811 uint lidx = Find_const(n); // Grab LRG number
1812 if( !_ifg ) {
1813 sprintf(buf,"L%d",lidx); // No register binding yet
1814 } else if( !lidx ) { // Special, not allocated value
1815 strcpy(buf,"Special");
1816 } else if( (lrgs(lidx).num_regs() == 1)
1817 ? !lrgs(lidx).mask().is_bound1()
1818 : !lrgs(lidx).mask().is_bound2() ) {
1819 sprintf(buf,"L%d",lidx); // No register binding yet
1820 } else { // Hah! We have a bound machine register
1821 print_reg( lrgs(lidx).reg(), this, buf );
1822 }
1823 }
1824 return buf+strlen(buf);
1825 }
1826
1827 //----------------------dump_for_spill_split_recycle--------------------------
1828 void PhaseChaitin::dump_for_spill_split_recycle() const {
1829 if( WizardMode && (PrintCompilation || PrintOpto) ) {
1830 // Display which live ranges need to be split and the allocator's state
1831 tty->print_cr("Graph-Coloring Iteration %d will split the following live ranges", _trip_cnt);
1832 for( uint bidx = 1; bidx < _maxlrg; bidx++ ) {
1833 if( lrgs(bidx).alive() && lrgs(bidx).reg() >= LRG::SPILL_REG ) {
1834 tty->print("L%d: ", bidx);
1835 lrgs(bidx).dump();
1836 }
1837 }
1838 tty->cr();
1839 dump();
1840 }
1841 }
1842
1843 //------------------------------dump_frame------------------------------------
1844 void PhaseChaitin::dump_frame() const {
1845 const char *fp = OptoReg::regname(OptoReg::c_frame_pointer);
1846 const TypeTuple *domain = C->tf()->domain();
1847 const int argcnt = domain->cnt() - TypeFunc::Parms;
1848
1849 // Incoming arguments in registers dump
1850 for( int k = 0; k < argcnt; k++ ) {
1851 OptoReg::Name parmreg = _matcher._parm_regs[k].first();
1852 if( OptoReg::is_reg(parmreg)) {
1853 const char *reg_name = OptoReg::regname(parmreg);
1854 tty->print("#r%3.3d %s", parmreg, reg_name);
1855 parmreg = _matcher._parm_regs[k].second();
1856 if( OptoReg::is_reg(parmreg)) {
1857 tty->print(":%s", OptoReg::regname(parmreg));
1858 }
1859 tty->print(" : parm %d: ", k);
1860 domain->field_at(k + TypeFunc::Parms)->dump();
1861 tty->print_cr("");
1862 }
1863 }
1864
1865 // Check for un-owned padding above incoming args
1866 OptoReg::Name reg = _matcher._new_SP;
1867 if( reg > _matcher._in_arg_limit ) {
1868 reg = OptoReg::add(reg, -1);
1869 tty->print_cr("#r%3.3d %s+%2d: pad0, owned by CALLER", reg, fp, reg2offset_unchecked(reg));
1870 }
1871
1872 // Incoming argument area dump
1873 OptoReg::Name begin_in_arg = OptoReg::add(_matcher._old_SP,C->out_preserve_stack_slots());
1874 while( reg > begin_in_arg ) {
1875 reg = OptoReg::add(reg, -1);
1876 tty->print("#r%3.3d %s+%2d: ",reg,fp,reg2offset_unchecked(reg));
1877 int j;
1878 for( j = 0; j < argcnt; j++) {
1879 if( _matcher._parm_regs[j].first() == reg ||
1880 _matcher._parm_regs[j].second() == reg ) {
1881 tty->print("parm %d: ",j);
1882 domain->field_at(j + TypeFunc::Parms)->dump();
1883 tty->print_cr("");
1884 break;
1885 }
1886 }
1887 if( j >= argcnt )
1888 tty->print_cr("HOLE, owned by SELF");
1889 }
1890
1891 // Old outgoing preserve area
1892 while( reg > _matcher._old_SP ) {
1893 reg = OptoReg::add(reg, -1);
1894 tty->print_cr("#r%3.3d %s+%2d: old out preserve",reg,fp,reg2offset_unchecked(reg));
1895 }
1896
1897 // Old SP
1898 tty->print_cr("# -- Old %s -- Framesize: %d --",fp,
1899 reg2offset_unchecked(OptoReg::add(_matcher._old_SP,-1)) - reg2offset_unchecked(_matcher._new_SP)+jintSize);
1900
1901 // Preserve area dump
1902 reg = OptoReg::add(reg, -1);
1903 while( OptoReg::is_stack(reg)) {
1904 tty->print("#r%3.3d %s+%2d: ",reg,fp,reg2offset_unchecked(reg));
1905 if( _matcher.return_addr() == reg )
1906 tty->print_cr("return address");
1907 else if( _matcher.return_addr() == OptoReg::add(reg,1) &&
1908 VerifyStackAtCalls )
1909 tty->print_cr("0xBADB100D +VerifyStackAtCalls");
1910 else if ((int)OptoReg::reg2stack(reg) < C->fixed_slots())
1911 tty->print_cr("Fixed slot %d", OptoReg::reg2stack(reg));
1912 else
1913 tty->print_cr("pad2, in_preserve");
1914 reg = OptoReg::add(reg, -1);
1915 }
1916
1917 // Spill area dump
1918 reg = OptoReg::add(_matcher._new_SP, _framesize );
1919 while( reg > _matcher._out_arg_limit ) {
1920 reg = OptoReg::add(reg, -1);
1921 tty->print_cr("#r%3.3d %s+%2d: spill",reg,fp,reg2offset_unchecked(reg));
1922 }
1923
1924 // Outgoing argument area dump
1925 while( reg > OptoReg::add(_matcher._new_SP, C->out_preserve_stack_slots()) ) {
1926 reg = OptoReg::add(reg, -1);
1927 tty->print_cr("#r%3.3d %s+%2d: outgoing argument",reg,fp,reg2offset_unchecked(reg));
1928 }
1929
1930 // Outgoing new preserve area
1931 while( reg > _matcher._new_SP ) {
1932 reg = OptoReg::add(reg, -1);
1933 tty->print_cr("#r%3.3d %s+%2d: new out preserve",reg,fp,reg2offset_unchecked(reg));
1934 }
1935 tty->print_cr("#");
1936 }
1937
1938 //------------------------------dump_bb----------------------------------------
1939 void PhaseChaitin::dump_bb( uint pre_order ) const {
1940 tty->print_cr("---dump of B%d---",pre_order);
1941 for( uint i = 0; i < _cfg._num_blocks; i++ ) {
1942 Block *b = _cfg._blocks[i];
1943 if( b->_pre_order == pre_order )
1944 dump(b);
1945 }
1946 }
1947
1948 //------------------------------dump_lrg---------------------------------------
1949 void PhaseChaitin::dump_lrg( uint lidx ) const {
1950 tty->print_cr("---dump of L%d---",lidx);
1951
1952 if( _ifg ) {
1953 if( lidx >= _maxlrg ) {
1954 tty->print("Attempt to print live range index beyond max live range.\n");
1955 return;
1956 }
1957 tty->print("L%d: ",lidx);
1958 lrgs(lidx).dump( );
1959 }
1960 if( _ifg ) { tty->print("Neighbors: %d - ", _ifg->neighbor_cnt(lidx));
1961 _ifg->neighbors(lidx)->dump();
1962 tty->cr();
1963 }
1964 // For all blocks
1965 for( uint i = 0; i < _cfg._num_blocks; i++ ) {
1966 Block *b = _cfg._blocks[i];
1967 int dump_once = 0;
1968
1969 // For all instructions
1970 for( uint j = 0; j < b->_nodes.size(); j++ ) {
1971 Node *n = b->_nodes[j];
1972 if( Find_const(n) == lidx ) {
1973 if( !dump_once++ ) {
1974 tty->cr();
1975 b->dump_head( &_cfg._bbs );
1976 }
1977 dump(n);
1978 continue;
1979 }
1980 uint cnt = n->req();
1981 for( uint k = 1; k < cnt; k++ ) {
1982 Node *m = n->in(k);
1983 if (!m) continue; // be robust in the dumper
1984 if( Find_const(m) == lidx ) {
1985 if( !dump_once++ ) {
1986 tty->cr();
1987 b->dump_head( &_cfg._bbs );
1988 }
1989 dump(n);
1990 }
1991 }
1992 }
1993 } // End of per-block dump
1994 tty->cr();
1995 }
1996 #endif // not PRODUCT
1997
1998 //------------------------------print_chaitin_statistics-------------------------------
1999 int PhaseChaitin::_final_loads = 0;
2000 int PhaseChaitin::_final_stores = 0;
2001 int PhaseChaitin::_final_memoves= 0;
2002 int PhaseChaitin::_final_copies = 0;
2003 double PhaseChaitin::_final_load_cost = 0;
2004 double PhaseChaitin::_final_store_cost = 0;
2005 double PhaseChaitin::_final_memove_cost= 0;
2006 double PhaseChaitin::_final_copy_cost = 0;
2007 int PhaseChaitin::_conserv_coalesce = 0;
2008 int PhaseChaitin::_conserv_coalesce_pair = 0;
2009 int PhaseChaitin::_conserv_coalesce_trie = 0;
2010 int PhaseChaitin::_conserv_coalesce_quad = 0;
2011 int PhaseChaitin::_post_alloc = 0;
2012 int PhaseChaitin::_lost_opp_pp_coalesce = 0;
2013 int PhaseChaitin::_lost_opp_cflow_coalesce = 0;
2014 int PhaseChaitin::_used_cisc_instructions = 0;
2015 int PhaseChaitin::_unused_cisc_instructions = 0;
2016 int PhaseChaitin::_allocator_attempts = 0;
2017 int PhaseChaitin::_allocator_successes = 0;
2018
2019 #ifndef PRODUCT
2020 uint PhaseChaitin::_high_pressure = 0;
2021 uint PhaseChaitin::_low_pressure = 0;
2022
2023 void PhaseChaitin::print_chaitin_statistics() {
2024 tty->print_cr("Inserted %d spill loads, %d spill stores, %d mem-mem moves and %d copies.", _final_loads, _final_stores, _final_memoves, _final_copies);
2025 tty->print_cr("Total load cost= %6.0f, store cost = %6.0f, mem-mem cost = %5.2f, copy cost = %5.0f.", _final_load_cost, _final_store_cost, _final_memove_cost, _final_copy_cost);
2026 tty->print_cr("Adjusted spill cost = %7.0f.",
2027 _final_load_cost*4.0 + _final_store_cost * 2.0 +
2028 _final_copy_cost*1.0 + _final_memove_cost*12.0);
2029 tty->print("Conservatively coalesced %d copies, %d pairs",
2030 _conserv_coalesce, _conserv_coalesce_pair);
2031 if( _conserv_coalesce_trie || _conserv_coalesce_quad )
2032 tty->print(", %d tries, %d quads", _conserv_coalesce_trie, _conserv_coalesce_quad);
2033 tty->print_cr(", %d post alloc.", _post_alloc);
2034 if( _lost_opp_pp_coalesce || _lost_opp_cflow_coalesce )
2035 tty->print_cr("Lost coalesce opportunity, %d private-private, and %d cflow interfered.",
2036 _lost_opp_pp_coalesce, _lost_opp_cflow_coalesce );
2037 if( _used_cisc_instructions || _unused_cisc_instructions )
2038 tty->print_cr("Used cisc instruction %d, remained in register %d",
2039 _used_cisc_instructions, _unused_cisc_instructions);
2040 if( _allocator_successes != 0 )
2041 tty->print_cr("Average allocation trips %f", (float)_allocator_attempts/(float)_allocator_successes);
2042 tty->print_cr("High Pressure Blocks = %d, Low Pressure Blocks = %d", _high_pressure, _low_pressure);
2043 }
2044 #endif // not PRODUCT