1 #ifdef USE_PRAGMA_IDENT_SRC
2 #pragma ident "@(#)chaitin.cpp 1.116 07/09/28 10:23:12 JVM"
3 #endif
4 /*
5 * Copyright 2000-2007 Sun Microsystems, Inc. All Rights Reserved.
6 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
7 *
8 * This code is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License version 2 only, as
10 * published by the Free Software Foundation.
11 *
12 * This code is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15 * version 2 for more details (a copy is included in the LICENSE file that
16 * accompanied this code).
17 *
18 * You should have received a copy of the GNU General Public License version
19 * 2 along with this work; if not, write to the Free Software Foundation,
20 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
21 *
22 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
23 * CA 95054 USA or visit www.sun.com if you need additional information or
24 * have any questions.
25 *
426 // Select colors by re-inserting LRGs back into the IFG in reverse order.
427 // Return whether or not something spills.
428 spills = Select( );
429 }
430
431 // Count number of Simplify-Select trips per coloring success.
432 _allocator_attempts += _trip_cnt + 1;
433 _allocator_successes += 1;
434
435 // Peephole remove copies
436 post_allocate_copy_removal();
437
438 // max_reg is past the largest *register* used.
439 // Convert that to a frame_slot number.
440 if( _max_reg <= _matcher._new_SP )
441 _framesize = C->out_preserve_stack_slots();
442 else _framesize = _max_reg -_matcher._new_SP;
443 assert((int)(_matcher._new_SP+_framesize) >= (int)_matcher._out_arg_limit, "framesize must be large enough");
444
445 // This frame must preserve the required fp alignment
446 const int stack_alignment_in_words = Matcher::stack_alignment_in_slots();
447 if (stack_alignment_in_words > 0)
448 _framesize = round_to(_framesize, Matcher::stack_alignment_in_bytes());
449 assert( _framesize >= 0 && _framesize <= 1000000, "sanity check" );
450 #ifndef PRODUCT
451 _total_framesize += _framesize;
452 if( (int)_framesize > _max_framesize )
453 _max_framesize = _framesize;
454 #endif
455
456 // Convert CISC spills
457 fixup_spills();
458
459 // Log regalloc results
460 CompileLog* log = Compile::current()->log();
461 if (log != NULL) {
462 log->elem("regalloc attempts='%d' success='%d'", _trip_cnt, !C->failing());
463 }
464
465 if (C->failing()) return;
466
467 NOT_PRODUCT( C->verify_graph_edges(); )
468
668 if( ireg == Op_RegL ) {
669 lrg.set_reg_pressure(2);
670 } else {
671 lrg.set_reg_pressure(1);
672 }
673 #else
674 lrg.set_reg_pressure(1); // normally one value per register
675 #endif
676 // If this def of a double forces a mis-aligned double,
677 // flag as '_fat_proj' - really flag as allowing misalignment
678 // AND changes how we count interferences. A mis-aligned
679 // double can interfere with TWO aligned pairs, or effectively
680 // FOUR registers!
681 if( rm.is_misaligned_Pair() ) {
682 lrg._fat_proj = 1;
683 lrg._is_bound = 1;
684 }
685 break;
686 case Op_RegF:
687 case Op_RegI:
688 case Op_RegFlags:
689 case 0: // not an ideal register
690 lrg.set_num_regs(1);
691 #ifdef SPARC
692 lrg.set_reg_pressure(2);
693 #else
694 lrg.set_reg_pressure(1);
695 #endif
696 break;
697 default:
698 ShouldNotReachHere();
699 }
700 }
701
702 // Now do the same for inputs
703 uint cnt = n->req();
704 // Setup for CISC SPILLING
705 uint inp = (uint)AdlcVMDeps::Not_cisc_spillable;
706 if( UseCISCSpill && after_aggressive ) {
707 inp = n->cisc_operand();
1370 if( OptoReg::is_stack(src_reg) ) { // If input is on stack
1371 // This is a CISC Spill, get stack offset and construct new node
1372 #ifndef PRODUCT
1373 if( TraceCISCSpill ) {
1374 tty->print(" reg-instr: ");
1375 n->dump();
1376 }
1377 #endif
1378 int stk_offset = reg2offset(src_reg);
1379 // Bailout if we might exceed node limit when spilling this instruction
1380 C->check_node_count(0, "out of nodes fixing spills");
1381 if (C->failing()) return;
1382 // Transform node
1383 MachNode *cisc = mach->cisc_version(stk_offset, C)->as_Mach();
1384 cisc->set_req(inp,fp); // Base register is frame pointer
1385 if( cisc->oper_input_base() > 1 && mach->oper_input_base() <= 1 ) {
1386 assert( cisc->oper_input_base() == 2, "Only adding one edge");
1387 cisc->ins_req(1,src); // Requires a memory edge
1388 }
1389 b->_nodes.map(j,cisc); // Insert into basic block
1390 n->replace_by(cisc); // Correct graph
1391 //
1392 ++_used_cisc_instructions;
1393 #ifndef PRODUCT
1394 if( TraceCISCSpill ) {
1395 tty->print(" cisc-instr: ");
1396 cisc->dump();
1397 }
1398 #endif
1399 } else {
1400 #ifndef PRODUCT
1401 if( TraceCISCSpill ) {
1402 tty->print(" using reg-instr: ");
1403 n->dump();
1404 }
1405 #endif
1406 ++_unused_cisc_instructions; // input can be on stack
1407 }
1408 }
1409
1410 } // End of for all instructions
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1 #ifdef USE_PRAGMA_IDENT_SRC
2 #pragma ident "@(#)chaitin.cpp 1.116 07/09/28 10:23:12 JVM"
3 #endif
4 /*
5 * Copyright 2000-2008 Sun Microsystems, Inc. All Rights Reserved.
6 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
7 *
8 * This code is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License version 2 only, as
10 * published by the Free Software Foundation.
11 *
12 * This code is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15 * version 2 for more details (a copy is included in the LICENSE file that
16 * accompanied this code).
17 *
18 * You should have received a copy of the GNU General Public License version
19 * 2 along with this work; if not, write to the Free Software Foundation,
20 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
21 *
22 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
23 * CA 95054 USA or visit www.sun.com if you need additional information or
24 * have any questions.
25 *
426 // Select colors by re-inserting LRGs back into the IFG in reverse order.
427 // Return whether or not something spills.
428 spills = Select( );
429 }
430
431 // Count number of Simplify-Select trips per coloring success.
432 _allocator_attempts += _trip_cnt + 1;
433 _allocator_successes += 1;
434
435 // Peephole remove copies
436 post_allocate_copy_removal();
437
438 // max_reg is past the largest *register* used.
439 // Convert that to a frame_slot number.
440 if( _max_reg <= _matcher._new_SP )
441 _framesize = C->out_preserve_stack_slots();
442 else _framesize = _max_reg -_matcher._new_SP;
443 assert((int)(_matcher._new_SP+_framesize) >= (int)_matcher._out_arg_limit, "framesize must be large enough");
444
445 // This frame must preserve the required fp alignment
446 _framesize = round_to(_framesize, Matcher::stack_alignment_in_slots());
447 assert( _framesize >= 0 && _framesize <= 1000000, "sanity check" );
448 #ifndef PRODUCT
449 _total_framesize += _framesize;
450 if( (int)_framesize > _max_framesize )
451 _max_framesize = _framesize;
452 #endif
453
454 // Convert CISC spills
455 fixup_spills();
456
457 // Log regalloc results
458 CompileLog* log = Compile::current()->log();
459 if (log != NULL) {
460 log->elem("regalloc attempts='%d' success='%d'", _trip_cnt, !C->failing());
461 }
462
463 if (C->failing()) return;
464
465 NOT_PRODUCT( C->verify_graph_edges(); )
466
666 if( ireg == Op_RegL ) {
667 lrg.set_reg_pressure(2);
668 } else {
669 lrg.set_reg_pressure(1);
670 }
671 #else
672 lrg.set_reg_pressure(1); // normally one value per register
673 #endif
674 // If this def of a double forces a mis-aligned double,
675 // flag as '_fat_proj' - really flag as allowing misalignment
676 // AND changes how we count interferences. A mis-aligned
677 // double can interfere with TWO aligned pairs, or effectively
678 // FOUR registers!
679 if( rm.is_misaligned_Pair() ) {
680 lrg._fat_proj = 1;
681 lrg._is_bound = 1;
682 }
683 break;
684 case Op_RegF:
685 case Op_RegI:
686 case Op_RegN:
687 case Op_RegFlags:
688 case 0: // not an ideal register
689 lrg.set_num_regs(1);
690 #ifdef SPARC
691 lrg.set_reg_pressure(2);
692 #else
693 lrg.set_reg_pressure(1);
694 #endif
695 break;
696 default:
697 ShouldNotReachHere();
698 }
699 }
700
701 // Now do the same for inputs
702 uint cnt = n->req();
703 // Setup for CISC SPILLING
704 uint inp = (uint)AdlcVMDeps::Not_cisc_spillable;
705 if( UseCISCSpill && after_aggressive ) {
706 inp = n->cisc_operand();
1369 if( OptoReg::is_stack(src_reg) ) { // If input is on stack
1370 // This is a CISC Spill, get stack offset and construct new node
1371 #ifndef PRODUCT
1372 if( TraceCISCSpill ) {
1373 tty->print(" reg-instr: ");
1374 n->dump();
1375 }
1376 #endif
1377 int stk_offset = reg2offset(src_reg);
1378 // Bailout if we might exceed node limit when spilling this instruction
1379 C->check_node_count(0, "out of nodes fixing spills");
1380 if (C->failing()) return;
1381 // Transform node
1382 MachNode *cisc = mach->cisc_version(stk_offset, C)->as_Mach();
1383 cisc->set_req(inp,fp); // Base register is frame pointer
1384 if( cisc->oper_input_base() > 1 && mach->oper_input_base() <= 1 ) {
1385 assert( cisc->oper_input_base() == 2, "Only adding one edge");
1386 cisc->ins_req(1,src); // Requires a memory edge
1387 }
1388 b->_nodes.map(j,cisc); // Insert into basic block
1389 n->subsume_by(cisc); // Correct graph
1390 //
1391 ++_used_cisc_instructions;
1392 #ifndef PRODUCT
1393 if( TraceCISCSpill ) {
1394 tty->print(" cisc-instr: ");
1395 cisc->dump();
1396 }
1397 #endif
1398 } else {
1399 #ifndef PRODUCT
1400 if( TraceCISCSpill ) {
1401 tty->print(" using reg-instr: ");
1402 n->dump();
1403 }
1404 #endif
1405 ++_unused_cisc_instructions; // input can be on stack
1406 }
1407 }
1408
1409 } // End of for all instructions
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