1 #ifdef USE_PRAGMA_IDENT_SRC
2 #pragma ident "@(#)matcher.cpp 1.388 07/09/28 10:33:13 JVM"
3 #endif
4 /*
5 * Copyright 1997-2008 Sun Microsystems, Inc. All Rights Reserved.
6 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
7 *
8 * This code is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License version 2 only, as
10 * published by the Free Software Foundation.
11 *
12 * This code is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15 * version 2 for more details (a copy is included in the LICENSE file that
16 * accompanied this code).
17 *
18 * You should have received a copy of the GNU General Public License version
19 * 2 along with this work; if not, write to the Free Software Foundation,
20 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
21 *
22 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
23 * CA 95054 USA or visit www.sun.com if you need additional information or
24 * have any questions.
25 *
26 */
27
28 #include "incls/_precompiled.incl"
29 #include "incls/_matcher.cpp.incl"
30
31 OptoReg::Name OptoReg::c_frame_pointer;
32
33
34
35 const int Matcher::base2reg[Type::lastype] = {
36 Node::NotAMachineReg,0,0, Op_RegI, Op_RegL, 0, Op_RegN,
37 Node::NotAMachineReg, Node::NotAMachineReg, /* tuple, array */
38 Op_RegP, Op_RegP, Op_RegP, Op_RegP, Op_RegP, Op_RegP, /* the pointers */
39 0, 0/*abio*/,
40 Op_RegP /* Return address */, 0, /* the memories */
41 Op_RegF, Op_RegF, Op_RegF, Op_RegD, Op_RegD, Op_RegD,
42 0 /*bottom*/
43 };
44
45 const RegMask *Matcher::idealreg2regmask[_last_machine_leaf];
46 RegMask Matcher::mreg2regmask[_last_Mach_Reg];
47 RegMask Matcher::STACK_ONLY_mask;
48 RegMask Matcher::c_frame_ptr_mask;
49 const uint Matcher::_begin_rematerialize = _BEGIN_REMATERIALIZE;
50 const uint Matcher::_end_rematerialize = _END_REMATERIALIZE;
51
52 //---------------------------Matcher-------------------------------------------
53 Matcher::Matcher( Node_List &proj_list ) :
54 PhaseTransform( Phase::Ins_Select ),
55 #ifdef ASSERT
56 _old2new_map(C->comp_arena()),
57 _new2old_map(C->comp_arena()),
58 #endif
59 _shared_nodes(C->comp_arena()),
60 _reduceOp(reduceOp), _leftOp(leftOp), _rightOp(rightOp),
61 _swallowed(swallowed),
62 _begin_inst_chain_rule(_BEGIN_INST_CHAIN_RULE),
63 _end_inst_chain_rule(_END_INST_CHAIN_RULE),
64 _must_clone(must_clone), _proj_list(proj_list),
65 _register_save_policy(register_save_policy),
66 _c_reg_save_policy(c_reg_save_policy),
67 _register_save_type(register_save_type),
68 _ruleName(ruleName),
69 _allocation_started(false),
70 _states_arena(Chunk::medium_size),
71 _visited(&_states_arena),
72 _shared(&_states_arena),
73 _dontcare(&_states_arena) {
74 C->set_matcher(this);
75
76 idealreg2spillmask[Op_RegI] = NULL;
77 idealreg2spillmask[Op_RegN] = NULL;
78 idealreg2spillmask[Op_RegL] = NULL;
79 idealreg2spillmask[Op_RegF] = NULL;
80 idealreg2spillmask[Op_RegD] = NULL;
81 idealreg2spillmask[Op_RegP] = NULL;
82
83 idealreg2debugmask[Op_RegI] = NULL;
84 idealreg2debugmask[Op_RegN] = NULL;
85 idealreg2debugmask[Op_RegL] = NULL;
86 idealreg2debugmask[Op_RegF] = NULL;
87 idealreg2debugmask[Op_RegD] = NULL;
88 idealreg2debugmask[Op_RegP] = NULL;
89 debug_only(_mem_node = NULL;) // Ideal memory node consumed by mach node
90 }
91
92 //------------------------------warp_incoming_stk_arg------------------------
93 // This warps a VMReg into an OptoReg::Name
94 OptoReg::Name Matcher::warp_incoming_stk_arg( VMReg reg ) {
95 OptoReg::Name warped;
96 if( reg->is_stack() ) { // Stack slot argument?
97 warped = OptoReg::add(_old_SP, reg->reg2stack() );
98 warped = OptoReg::add(warped, C->out_preserve_stack_slots());
99 if( warped >= _in_arg_limit )
100 _in_arg_limit = OptoReg::add(warped, 1); // Bump max stack slot seen
101 if (!RegMask::can_represent(warped)) {
102 // the compiler cannot represent this method's calling sequence
103 C->record_method_not_compilable_all_tiers("unsupported incoming calling sequence");
104 return OptoReg::Bad;
105 }
106 return warped;
107 }
108 return OptoReg::as_OptoReg(reg);
109 }
110
111 //---------------------------compute_old_SP------------------------------------
112 OptoReg::Name Compile::compute_old_SP() {
113 int fixed = fixed_slots();
114 int preserve = in_preserve_stack_slots();
115 return OptoReg::stack2reg(round_to(fixed + preserve, Matcher::stack_alignment_in_slots()));
116 }
117
118
119
120 #ifdef ASSERT
121 void Matcher::verify_new_nodes_only(Node* xroot) {
122 // Make sure that the new graph only references new nodes
123 ResourceMark rm;
124 Unique_Node_List worklist;
125 VectorSet visited(Thread::current()->resource_area());
126 worklist.push(xroot);
127 while (worklist.size() > 0) {
128 Node* n = worklist.pop();
129 visited <<= n->_idx;
130 assert(C->node_arena()->contains(n), "dead node");
131 for (uint j = 0; j < n->req(); j++) {
132 Node* in = n->in(j);
133 if (in != NULL) {
134 assert(C->node_arena()->contains(in), "dead node");
135 if (!visited.test(in->_idx)) {
136 worklist.push(in);
137 }
138 }
139 }
140 }
141 }
142 #endif
143
144
145 //---------------------------match---------------------------------------------
146 void Matcher::match( ) {
147 // One-time initialization of some register masks.
148 init_spill_mask( C->root()->in(1) );
149 _return_addr_mask = return_addr();
150 #ifdef _LP64
151 // Pointers take 2 slots in 64-bit land
152 _return_addr_mask.Insert(OptoReg::add(return_addr(),1));
153 #endif
154
155 // Map a Java-signature return type into return register-value
156 // machine registers for 0, 1 and 2 returned values.
157 const TypeTuple *range = C->tf()->range();
158 if( range->cnt() > TypeFunc::Parms ) { // If not a void function
159 // Get ideal-register return type
160 int ireg = base2reg[range->field_at(TypeFunc::Parms)->base()];
161 // Get machine return register
162 uint sop = C->start()->Opcode();
163 OptoRegPair regs = return_value(ireg, false);
164
165 // And mask for same
166 _return_value_mask = RegMask(regs.first());
167 if( OptoReg::is_valid(regs.second()) )
168 _return_value_mask.Insert(regs.second());
169 }
170
171 // ---------------
172 // Frame Layout
173
174 // Need the method signature to determine the incoming argument types,
175 // because the types determine which registers the incoming arguments are
176 // in, and this affects the matched code.
177 const TypeTuple *domain = C->tf()->domain();
178 uint argcnt = domain->cnt() - TypeFunc::Parms;
179 BasicType *sig_bt = NEW_RESOURCE_ARRAY( BasicType, argcnt );
180 VMRegPair *vm_parm_regs = NEW_RESOURCE_ARRAY( VMRegPair, argcnt );
181 _parm_regs = NEW_RESOURCE_ARRAY( OptoRegPair, argcnt );
182 _calling_convention_mask = NEW_RESOURCE_ARRAY( RegMask, argcnt );
183 uint i;
184 for( i = 0; i<argcnt; i++ ) {
185 sig_bt[i] = domain->field_at(i+TypeFunc::Parms)->basic_type();
186 }
187
188 // Pass array of ideal registers and length to USER code (from the AD file)
189 // that will convert this to an array of register numbers.
190 const StartNode *start = C->start();
191 start->calling_convention( sig_bt, vm_parm_regs, argcnt );
192 #ifdef ASSERT
193 // Sanity check users' calling convention. Real handy while trying to
194 // get the initial port correct.
195 { for (uint i = 0; i<argcnt; i++) {
196 if( !vm_parm_regs[i].first()->is_valid() && !vm_parm_regs[i].second()->is_valid() ) {
197 assert(domain->field_at(i+TypeFunc::Parms)==Type::HALF, "only allowed on halve" );
198 _parm_regs[i].set_bad();
199 continue;
200 }
201 VMReg parm_reg = vm_parm_regs[i].first();
202 assert(parm_reg->is_valid(), "invalid arg?");
203 if (parm_reg->is_reg()) {
204 OptoReg::Name opto_parm_reg = OptoReg::as_OptoReg(parm_reg);
205 assert(can_be_java_arg(opto_parm_reg) ||
206 C->stub_function() == CAST_FROM_FN_PTR(address, OptoRuntime::rethrow_C) ||
207 opto_parm_reg == inline_cache_reg(),
208 "parameters in register must be preserved by runtime stubs");
209 }
210 for (uint j = 0; j < i; j++) {
211 assert(parm_reg != vm_parm_regs[j].first(),
212 "calling conv. must produce distinct regs");
213 }
214 }
215 }
216 #endif
217
218 // Do some initial frame layout.
219
220 // Compute the old incoming SP (may be called FP) as
221 // OptoReg::stack0() + locks + in_preserve_stack_slots + pad2.
222 _old_SP = C->compute_old_SP();
223 assert( is_even(_old_SP), "must be even" );
224
225 // Compute highest incoming stack argument as
226 // _old_SP + out_preserve_stack_slots + incoming argument size.
227 _in_arg_limit = OptoReg::add(_old_SP, C->out_preserve_stack_slots());
228 assert( is_even(_in_arg_limit), "out_preserve must be even" );
229 for( i = 0; i < argcnt; i++ ) {
230 // Permit args to have no register
231 _calling_convention_mask[i].Clear();
232 if( !vm_parm_regs[i].first()->is_valid() && !vm_parm_regs[i].second()->is_valid() ) {
233 continue;
234 }
235 // calling_convention returns stack arguments as a count of
236 // slots beyond OptoReg::stack0()/VMRegImpl::stack0. We need to convert this to
237 // the allocators point of view, taking into account all the
238 // preserve area, locks & pad2.
239
240 OptoReg::Name reg1 = warp_incoming_stk_arg(vm_parm_regs[i].first());
241 if( OptoReg::is_valid(reg1))
242 _calling_convention_mask[i].Insert(reg1);
243
244 OptoReg::Name reg2 = warp_incoming_stk_arg(vm_parm_regs[i].second());
245 if( OptoReg::is_valid(reg2))
246 _calling_convention_mask[i].Insert(reg2);
247
248 // Saved biased stack-slot register number
249 _parm_regs[i].set_pair(reg2, reg1);
250 }
251
252 // Finally, make sure the incoming arguments take up an even number of
253 // words, in case the arguments or locals need to contain doubleword stack
254 // slots. The rest of the system assumes that stack slot pairs (in
255 // particular, in the spill area) which look aligned will in fact be
256 // aligned relative to the stack pointer in the target machine. Double
257 // stack slots will always be allocated aligned.
258 _new_SP = OptoReg::Name(round_to(_in_arg_limit, RegMask::SlotsPerLong));
259
260 // Compute highest outgoing stack argument as
261 // _new_SP + out_preserve_stack_slots + max(outgoing argument size).
262 _out_arg_limit = OptoReg::add(_new_SP, C->out_preserve_stack_slots());
263 assert( is_even(_out_arg_limit), "out_preserve must be even" );
264
265 if (!RegMask::can_represent(OptoReg::add(_out_arg_limit,-1))) {
266 // the compiler cannot represent this method's calling sequence
267 C->record_method_not_compilable("must be able to represent all call arguments in reg mask");
268 }
269
270 if (C->failing()) return; // bailed out on incoming arg failure
271
272 // ---------------
273 // Collect roots of matcher trees. Every node for which
274 // _shared[_idx] is cleared is guaranteed to not be shared, and thus
275 // can be a valid interior of some tree.
276 find_shared( C->root() );
277 find_shared( C->top() );
278
279 C->print_method("Before Matching");
280
281 // Swap out to old-space; emptying new-space
282 Arena *old = C->node_arena()->move_contents(C->old_arena());
283
284 // Save debug and profile information for nodes in old space:
285 _old_node_note_array = C->node_note_array();
286 if (_old_node_note_array != NULL) {
287 C->set_node_note_array(new(C->comp_arena()) GrowableArray<Node_Notes*>
288 (C->comp_arena(), _old_node_note_array->length(),
289 0, NULL));
290 }
291
292 // Pre-size the new_node table to avoid the need for range checks.
293 grow_new_node_array(C->unique());
294
295 // Reset node counter so MachNodes start with _idx at 0
296 int nodes = C->unique(); // save value
297 C->set_unique(0);
298
299 // Recursively match trees from old space into new space.
300 // Correct leaves of new-space Nodes; they point to old-space.
301 _visited.Clear(); // Clear visit bits for xform call
302 C->set_cached_top_node(xform( C->top(), nodes ));
303 if (!C->failing()) {
304 Node* xroot = xform( C->root(), 1 );
305 if (xroot == NULL) {
306 Matcher::soft_match_failure(); // recursive matching process failed
307 C->record_method_not_compilable("instruction match failed");
308 } else {
309 // During matching shared constants were attached to C->root()
310 // because xroot wasn't available yet, so transfer the uses to
311 // the xroot.
312 for( DUIterator_Fast jmax, j = C->root()->fast_outs(jmax); j < jmax; j++ ) {
313 Node* n = C->root()->fast_out(j);
314 if (C->node_arena()->contains(n)) {
315 assert(n->in(0) == C->root(), "should be control user");
316 n->set_req(0, xroot);
317 --j;
318 --jmax;
319 }
320 }
321
322 C->set_root(xroot->is_Root() ? xroot->as_Root() : NULL);
323 #ifdef ASSERT
324 verify_new_nodes_only(xroot);
325 #endif
326 }
327 }
328 if (C->top() == NULL || C->root() == NULL) {
329 C->record_method_not_compilable("graph lost"); // %%% cannot happen?
330 }
331 if (C->failing()) {
332 // delete old;
333 old->destruct_contents();
334 return;
335 }
336 assert( C->top(), "" );
337 assert( C->root(), "" );
338 validate_null_checks();
339
340 // Now smoke old-space
341 NOT_DEBUG( old->destruct_contents() );
342
343 // ------------------------
344 // Set up save-on-entry registers
345 Fixup_Save_On_Entry( );
346 }
347
348
349 //------------------------------Fixup_Save_On_Entry----------------------------
350 // The stated purpose of this routine is to take care of save-on-entry
351 // registers. However, the overall goal of the Match phase is to convert into
352 // machine-specific instructions which have RegMasks to guide allocation.
353 // So what this procedure really does is put a valid RegMask on each input
354 // to the machine-specific variations of all Return, TailCall and Halt
355 // instructions. It also adds edgs to define the save-on-entry values (and of
356 // course gives them a mask).
357
358 static RegMask *init_input_masks( uint size, RegMask &ret_adr, RegMask &fp ) {
359 RegMask *rms = NEW_RESOURCE_ARRAY( RegMask, size );
360 // Do all the pre-defined register masks
361 rms[TypeFunc::Control ] = RegMask::Empty;
362 rms[TypeFunc::I_O ] = RegMask::Empty;
363 rms[TypeFunc::Memory ] = RegMask::Empty;
364 rms[TypeFunc::ReturnAdr] = ret_adr;
365 rms[TypeFunc::FramePtr ] = fp;
366 return rms;
367 }
368
369 //---------------------------init_first_stack_mask-----------------------------
370 // Create the initial stack mask used by values spilling to the stack.
371 // Disallow any debug info in outgoing argument areas by setting the
372 // initial mask accordingly.
373 void Matcher::init_first_stack_mask() {
374
375 // Allocate storage for spill masks as masks for the appropriate load type.
376 RegMask *rms = (RegMask*)C->comp_arena()->Amalloc_D(sizeof(RegMask)*12);
377 idealreg2spillmask[Op_RegN] = &rms[0];
378 idealreg2spillmask[Op_RegI] = &rms[1];
379 idealreg2spillmask[Op_RegL] = &rms[2];
380 idealreg2spillmask[Op_RegF] = &rms[3];
381 idealreg2spillmask[Op_RegD] = &rms[4];
382 idealreg2spillmask[Op_RegP] = &rms[5];
383 idealreg2debugmask[Op_RegN] = &rms[6];
384 idealreg2debugmask[Op_RegI] = &rms[7];
385 idealreg2debugmask[Op_RegL] = &rms[8];
386 idealreg2debugmask[Op_RegF] = &rms[9];
387 idealreg2debugmask[Op_RegD] = &rms[10];
388 idealreg2debugmask[Op_RegP] = &rms[11];
389
390 OptoReg::Name i;
391
392 // At first, start with the empty mask
393 C->FIRST_STACK_mask().Clear();
394
395 // Add in the incoming argument area
396 OptoReg::Name init = OptoReg::add(_old_SP, C->out_preserve_stack_slots());
397 for (i = init; i < _in_arg_limit; i = OptoReg::add(i,1))
398 C->FIRST_STACK_mask().Insert(i);
399
400 // Add in all bits past the outgoing argument area
401 guarantee(RegMask::can_represent(OptoReg::add(_out_arg_limit,-1)),
402 "must be able to represent all call arguments in reg mask");
403 init = _out_arg_limit;
404 for (i = init; RegMask::can_represent(i); i = OptoReg::add(i,1))
405 C->FIRST_STACK_mask().Insert(i);
406
407 // Finally, set the "infinite stack" bit.
408 C->FIRST_STACK_mask().set_AllStack();
409
410 // Make spill masks. Registers for their class, plus FIRST_STACK_mask.
411 #ifdef _LP64
412 *idealreg2spillmask[Op_RegN] = *idealreg2regmask[Op_RegN];
413 idealreg2spillmask[Op_RegN]->OR(C->FIRST_STACK_mask());
414 #endif
415 *idealreg2spillmask[Op_RegI] = *idealreg2regmask[Op_RegI];
416 idealreg2spillmask[Op_RegI]->OR(C->FIRST_STACK_mask());
417 *idealreg2spillmask[Op_RegL] = *idealreg2regmask[Op_RegL];
418 idealreg2spillmask[Op_RegL]->OR(C->FIRST_STACK_mask());
419 *idealreg2spillmask[Op_RegF] = *idealreg2regmask[Op_RegF];
420 idealreg2spillmask[Op_RegF]->OR(C->FIRST_STACK_mask());
421 *idealreg2spillmask[Op_RegD] = *idealreg2regmask[Op_RegD];
422 idealreg2spillmask[Op_RegD]->OR(C->FIRST_STACK_mask());
423 *idealreg2spillmask[Op_RegP] = *idealreg2regmask[Op_RegP];
424 idealreg2spillmask[Op_RegP]->OR(C->FIRST_STACK_mask());
425
426 // Make up debug masks. Any spill slot plus callee-save registers.
427 // Caller-save registers are assumed to be trashable by the various
428 // inline-cache fixup routines.
429 *idealreg2debugmask[Op_RegN]= *idealreg2spillmask[Op_RegN];
430 *idealreg2debugmask[Op_RegI]= *idealreg2spillmask[Op_RegI];
431 *idealreg2debugmask[Op_RegL]= *idealreg2spillmask[Op_RegL];
432 *idealreg2debugmask[Op_RegF]= *idealreg2spillmask[Op_RegF];
433 *idealreg2debugmask[Op_RegD]= *idealreg2spillmask[Op_RegD];
434 *idealreg2debugmask[Op_RegP]= *idealreg2spillmask[Op_RegP];
435
436 // Prevent stub compilations from attempting to reference
437 // callee-saved registers from debug info
438 bool exclude_soe = !Compile::current()->is_method_compilation();
439
440 for( i=OptoReg::Name(0); i<OptoReg::Name(_last_Mach_Reg); i = OptoReg::add(i,1) ) {
441 // registers the caller has to save do not work
442 if( _register_save_policy[i] == 'C' ||
443 _register_save_policy[i] == 'A' ||
444 (_register_save_policy[i] == 'E' && exclude_soe) ) {
445 idealreg2debugmask[Op_RegN]->Remove(i);
446 idealreg2debugmask[Op_RegI]->Remove(i); // Exclude save-on-call
447 idealreg2debugmask[Op_RegL]->Remove(i); // registers from debug
448 idealreg2debugmask[Op_RegF]->Remove(i); // masks
449 idealreg2debugmask[Op_RegD]->Remove(i);
450 idealreg2debugmask[Op_RegP]->Remove(i);
451 }
452 }
453 }
454
455 //---------------------------is_save_on_entry----------------------------------
456 bool Matcher::is_save_on_entry( int reg ) {
457 return
458 _register_save_policy[reg] == 'E' ||
459 _register_save_policy[reg] == 'A' || // Save-on-entry register?
460 // Also save argument registers in the trampolining stubs
461 (C->save_argument_registers() && is_spillable_arg(reg));
462 }
463
464 //---------------------------Fixup_Save_On_Entry-------------------------------
465 void Matcher::Fixup_Save_On_Entry( ) {
466 init_first_stack_mask();
467
468 Node *root = C->root(); // Short name for root
469 // Count number of save-on-entry registers.
470 uint soe_cnt = number_of_saved_registers();
471 uint i;
472
473 // Find the procedure Start Node
474 StartNode *start = C->start();
475 assert( start, "Expect a start node" );
476
477 // Save argument registers in the trampolining stubs
478 if( C->save_argument_registers() )
479 for( i = 0; i < _last_Mach_Reg; i++ )
480 if( is_spillable_arg(i) )
481 soe_cnt++;
482
483 // Input RegMask array shared by all Returns.
484 // The type for doubles and longs has a count of 2, but
485 // there is only 1 returned value
486 uint ret_edge_cnt = TypeFunc::Parms + ((C->tf()->range()->cnt() == TypeFunc::Parms) ? 0 : 1);
487 RegMask *ret_rms = init_input_masks( ret_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
488 // Returns have 0 or 1 returned values depending on call signature.
489 // Return register is specified by return_value in the AD file.
490 if (ret_edge_cnt > TypeFunc::Parms)
491 ret_rms[TypeFunc::Parms+0] = _return_value_mask;
492
493 // Input RegMask array shared by all Rethrows.
494 uint reth_edge_cnt = TypeFunc::Parms+1;
495 RegMask *reth_rms = init_input_masks( reth_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
496 // Rethrow takes exception oop only, but in the argument 0 slot.
497 reth_rms[TypeFunc::Parms] = mreg2regmask[find_receiver(false)];
498 #ifdef _LP64
499 // Need two slots for ptrs in 64-bit land
500 reth_rms[TypeFunc::Parms].Insert(OptoReg::add(OptoReg::Name(find_receiver(false)),1));
501 #endif
502
503 // Input RegMask array shared by all TailCalls
504 uint tail_call_edge_cnt = TypeFunc::Parms+2;
505 RegMask *tail_call_rms = init_input_masks( tail_call_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
506
507 // Input RegMask array shared by all TailJumps
508 uint tail_jump_edge_cnt = TypeFunc::Parms+2;
509 RegMask *tail_jump_rms = init_input_masks( tail_jump_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
510
511 // TailCalls have 2 returned values (target & moop), whose masks come
512 // from the usual MachNode/MachOper mechanism. Find a sample
513 // TailCall to extract these masks and put the correct masks into
514 // the tail_call_rms array.
515 for( i=1; i < root->req(); i++ ) {
516 MachReturnNode *m = root->in(i)->as_MachReturn();
517 if( m->ideal_Opcode() == Op_TailCall ) {
518 tail_call_rms[TypeFunc::Parms+0] = m->MachNode::in_RegMask(TypeFunc::Parms+0);
519 tail_call_rms[TypeFunc::Parms+1] = m->MachNode::in_RegMask(TypeFunc::Parms+1);
520 break;
521 }
522 }
523
524 // TailJumps have 2 returned values (target & ex_oop), whose masks come
525 // from the usual MachNode/MachOper mechanism. Find a sample
526 // TailJump to extract these masks and put the correct masks into
527 // the tail_jump_rms array.
528 for( i=1; i < root->req(); i++ ) {
529 MachReturnNode *m = root->in(i)->as_MachReturn();
530 if( m->ideal_Opcode() == Op_TailJump ) {
531 tail_jump_rms[TypeFunc::Parms+0] = m->MachNode::in_RegMask(TypeFunc::Parms+0);
532 tail_jump_rms[TypeFunc::Parms+1] = m->MachNode::in_RegMask(TypeFunc::Parms+1);
533 break;
534 }
535 }
536
537 // Input RegMask array shared by all Halts
538 uint halt_edge_cnt = TypeFunc::Parms;
539 RegMask *halt_rms = init_input_masks( halt_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
540
541 // Capture the return input masks into each exit flavor
542 for( i=1; i < root->req(); i++ ) {
543 MachReturnNode *exit = root->in(i)->as_MachReturn();
544 switch( exit->ideal_Opcode() ) {
545 case Op_Return : exit->_in_rms = ret_rms; break;
546 case Op_Rethrow : exit->_in_rms = reth_rms; break;
547 case Op_TailCall : exit->_in_rms = tail_call_rms; break;
548 case Op_TailJump : exit->_in_rms = tail_jump_rms; break;
549 case Op_Halt : exit->_in_rms = halt_rms; break;
550 default : ShouldNotReachHere();
551 }
552 }
553
554 // Next unused projection number from Start.
555 int proj_cnt = C->tf()->domain()->cnt();
556
557 // Do all the save-on-entry registers. Make projections from Start for
558 // them, and give them a use at the exit points. To the allocator, they
559 // look like incoming register arguments.
560 for( i = 0; i < _last_Mach_Reg; i++ ) {
561 if( is_save_on_entry(i) ) {
562
563 // Add the save-on-entry to the mask array
564 ret_rms [ ret_edge_cnt] = mreg2regmask[i];
565 reth_rms [ reth_edge_cnt] = mreg2regmask[i];
566 tail_call_rms[tail_call_edge_cnt] = mreg2regmask[i];
567 tail_jump_rms[tail_jump_edge_cnt] = mreg2regmask[i];
568 // Halts need the SOE registers, but only in the stack as debug info.
569 // A just-prior uncommon-trap or deoptimization will use the SOE regs.
570 halt_rms [ halt_edge_cnt] = *idealreg2spillmask[_register_save_type[i]];
571
572 Node *mproj;
573
574 // Is this a RegF low half of a RegD? Double up 2 adjacent RegF's
575 // into a single RegD.
576 if( (i&1) == 0 &&
577 _register_save_type[i ] == Op_RegF &&
578 _register_save_type[i+1] == Op_RegF &&
579 is_save_on_entry(i+1) ) {
580 // Add other bit for double
581 ret_rms [ ret_edge_cnt].Insert(OptoReg::Name(i+1));
582 reth_rms [ reth_edge_cnt].Insert(OptoReg::Name(i+1));
583 tail_call_rms[tail_call_edge_cnt].Insert(OptoReg::Name(i+1));
584 tail_jump_rms[tail_jump_edge_cnt].Insert(OptoReg::Name(i+1));
585 halt_rms [ halt_edge_cnt].Insert(OptoReg::Name(i+1));
586 mproj = new (C, 1) MachProjNode( start, proj_cnt, ret_rms[ret_edge_cnt], Op_RegD );
587 proj_cnt += 2; // Skip 2 for doubles
588 }
589 else if( (i&1) == 1 && // Else check for high half of double
590 _register_save_type[i-1] == Op_RegF &&
591 _register_save_type[i ] == Op_RegF &&
592 is_save_on_entry(i-1) ) {
593 ret_rms [ ret_edge_cnt] = RegMask::Empty;
594 reth_rms [ reth_edge_cnt] = RegMask::Empty;
595 tail_call_rms[tail_call_edge_cnt] = RegMask::Empty;
596 tail_jump_rms[tail_jump_edge_cnt] = RegMask::Empty;
597 halt_rms [ halt_edge_cnt] = RegMask::Empty;
598 mproj = C->top();
599 }
600 // Is this a RegI low half of a RegL? Double up 2 adjacent RegI's
601 // into a single RegL.
602 else if( (i&1) == 0 &&
603 _register_save_type[i ] == Op_RegI &&
604 _register_save_type[i+1] == Op_RegI &&
605 is_save_on_entry(i+1) ) {
606 // Add other bit for long
607 ret_rms [ ret_edge_cnt].Insert(OptoReg::Name(i+1));
608 reth_rms [ reth_edge_cnt].Insert(OptoReg::Name(i+1));
609 tail_call_rms[tail_call_edge_cnt].Insert(OptoReg::Name(i+1));
610 tail_jump_rms[tail_jump_edge_cnt].Insert(OptoReg::Name(i+1));
611 halt_rms [ halt_edge_cnt].Insert(OptoReg::Name(i+1));
612 mproj = new (C, 1) MachProjNode( start, proj_cnt, ret_rms[ret_edge_cnt], Op_RegL );
613 proj_cnt += 2; // Skip 2 for longs
614 }
615 else if( (i&1) == 1 && // Else check for high half of long
616 _register_save_type[i-1] == Op_RegI &&
617 _register_save_type[i ] == Op_RegI &&
618 is_save_on_entry(i-1) ) {
619 ret_rms [ ret_edge_cnt] = RegMask::Empty;
620 reth_rms [ reth_edge_cnt] = RegMask::Empty;
621 tail_call_rms[tail_call_edge_cnt] = RegMask::Empty;
622 tail_jump_rms[tail_jump_edge_cnt] = RegMask::Empty;
623 halt_rms [ halt_edge_cnt] = RegMask::Empty;
624 mproj = C->top();
625 } else {
626 // Make a projection for it off the Start
627 mproj = new (C, 1) MachProjNode( start, proj_cnt++, ret_rms[ret_edge_cnt], _register_save_type[i] );
628 }
629
630 ret_edge_cnt ++;
631 reth_edge_cnt ++;
632 tail_call_edge_cnt ++;
633 tail_jump_edge_cnt ++;
634 halt_edge_cnt ++;
635
636 // Add a use of the SOE register to all exit paths
637 for( uint j=1; j < root->req(); j++ )
638 root->in(j)->add_req(mproj);
639 } // End of if a save-on-entry register
640 } // End of for all machine registers
641 }
642
643 //------------------------------init_spill_mask--------------------------------
644 void Matcher::init_spill_mask( Node *ret ) {
645 if( idealreg2regmask[Op_RegI] ) return; // One time only init
646
647 OptoReg::c_frame_pointer = c_frame_pointer();
648 c_frame_ptr_mask = c_frame_pointer();
649 #ifdef _LP64
650 // pointers are twice as big
651 c_frame_ptr_mask.Insert(OptoReg::add(c_frame_pointer(),1));
652 #endif
653
654 // Start at OptoReg::stack0()
655 STACK_ONLY_mask.Clear();
656 OptoReg::Name init = OptoReg::stack2reg(0);
657 // STACK_ONLY_mask is all stack bits
658 OptoReg::Name i;
659 for (i = init; RegMask::can_represent(i); i = OptoReg::add(i,1))
660 STACK_ONLY_mask.Insert(i);
661 // Also set the "infinite stack" bit.
662 STACK_ONLY_mask.set_AllStack();
663
664 // Copy the register names over into the shared world
665 for( i=OptoReg::Name(0); i<OptoReg::Name(_last_Mach_Reg); i = OptoReg::add(i,1) ) {
666 // SharedInfo::regName[i] = regName[i];
667 // Handy RegMasks per machine register
668 mreg2regmask[i].Insert(i);
669 }
670
671 // Grab the Frame Pointer
672 Node *fp = ret->in(TypeFunc::FramePtr);
673 Node *mem = ret->in(TypeFunc::Memory);
674 const TypePtr* atp = TypePtr::BOTTOM;
675 // Share frame pointer while making spill ops
676 set_shared(fp);
677
678 // Compute generic short-offset Loads
679 #ifdef _LP64
680 MachNode *spillCP = match_tree(new (C, 3) LoadNNode(NULL,mem,fp,atp,TypeInstPtr::BOTTOM));
681 #endif
682 MachNode *spillI = match_tree(new (C, 3) LoadINode(NULL,mem,fp,atp));
683 MachNode *spillL = match_tree(new (C, 3) LoadLNode(NULL,mem,fp,atp));
684 MachNode *spillF = match_tree(new (C, 3) LoadFNode(NULL,mem,fp,atp));
685 MachNode *spillD = match_tree(new (C, 3) LoadDNode(NULL,mem,fp,atp));
686 MachNode *spillP = match_tree(new (C, 3) LoadPNode(NULL,mem,fp,atp,TypeInstPtr::BOTTOM));
687 assert(spillI != NULL && spillL != NULL && spillF != NULL &&
688 spillD != NULL && spillP != NULL, "");
689
690 // Get the ADLC notion of the right regmask, for each basic type.
691 #ifdef _LP64
692 idealreg2regmask[Op_RegN] = &spillCP->out_RegMask();
693 #endif
694 idealreg2regmask[Op_RegI] = &spillI->out_RegMask();
695 idealreg2regmask[Op_RegL] = &spillL->out_RegMask();
696 idealreg2regmask[Op_RegF] = &spillF->out_RegMask();
697 idealreg2regmask[Op_RegD] = &spillD->out_RegMask();
698 idealreg2regmask[Op_RegP] = &spillP->out_RegMask();
699 }
700
701 #ifdef ASSERT
702 static void match_alias_type(Compile* C, Node* n, Node* m) {
703 if (!VerifyAliases) return; // do not go looking for trouble by default
704 const TypePtr* nat = n->adr_type();
705 const TypePtr* mat = m->adr_type();
706 int nidx = C->get_alias_index(nat);
707 int midx = C->get_alias_index(mat);
708 // Detune the assert for cases like (AndI 0xFF (LoadB p)).
709 if (nidx == Compile::AliasIdxTop && midx >= Compile::AliasIdxRaw) {
710 for (uint i = 1; i < n->req(); i++) {
711 Node* n1 = n->in(i);
712 const TypePtr* n1at = n1->adr_type();
713 if (n1at != NULL) {
714 nat = n1at;
715 nidx = C->get_alias_index(n1at);
716 }
717 }
718 }
719 // %%% Kludgery. Instead, fix ideal adr_type methods for all these cases:
720 if (nidx == Compile::AliasIdxTop && midx == Compile::AliasIdxRaw) {
721 switch (n->Opcode()) {
722 case Op_PrefetchRead:
723 case Op_PrefetchWrite:
724 nidx = Compile::AliasIdxRaw;
725 nat = TypeRawPtr::BOTTOM;
726 break;
727 }
728 }
729 if (nidx == Compile::AliasIdxRaw && midx == Compile::AliasIdxTop) {
730 switch (n->Opcode()) {
731 case Op_ClearArray:
732 midx = Compile::AliasIdxRaw;
733 mat = TypeRawPtr::BOTTOM;
734 break;
735 }
736 }
737 if (nidx == Compile::AliasIdxTop && midx == Compile::AliasIdxBot) {
738 switch (n->Opcode()) {
739 case Op_Return:
740 case Op_Rethrow:
741 case Op_Halt:
742 case Op_TailCall:
743 case Op_TailJump:
744 nidx = Compile::AliasIdxBot;
745 nat = TypePtr::BOTTOM;
746 break;
747 }
748 }
749 if (nidx == Compile::AliasIdxBot && midx == Compile::AliasIdxTop) {
750 switch (n->Opcode()) {
751 case Op_StrComp:
752 case Op_AryEq:
753 case Op_MemBarVolatile:
754 case Op_MemBarCPUOrder: // %%% these ideals should have narrower adr_type?
755 nidx = Compile::AliasIdxTop;
756 nat = NULL;
757 break;
758 }
759 }
760 if (nidx != midx) {
761 if (PrintOpto || (PrintMiscellaneous && (WizardMode || Verbose))) {
762 tty->print_cr("==== Matcher alias shift %d => %d", nidx, midx);
763 n->dump();
764 m->dump();
765 }
766 assert(C->subsume_loads() && C->must_alias(nat, midx),
767 "must not lose alias info when matching");
768 }
769 }
770 #endif
771
772
773 //------------------------------MStack-----------------------------------------
774 // State and MStack class used in xform() and find_shared() iterative methods.
775 enum Node_State { Pre_Visit, // node has to be pre-visited
776 Visit, // visit node
777 Post_Visit, // post-visit node
778 Alt_Post_Visit // alternative post-visit path
779 };
780
781 class MStack: public Node_Stack {
782 public:
783 MStack(int size) : Node_Stack(size) { }
784
785 void push(Node *n, Node_State ns) {
786 Node_Stack::push(n, (uint)ns);
787 }
788 void push(Node *n, Node_State ns, Node *parent, int indx) {
789 ++_inode_top;
790 if ((_inode_top + 1) >= _inode_max) grow();
791 _inode_top->node = parent;
792 _inode_top->indx = (uint)indx;
793 ++_inode_top;
794 _inode_top->node = n;
795 _inode_top->indx = (uint)ns;
796 }
797 Node *parent() {
798 pop();
799 return node();
800 }
801 Node_State state() const {
802 return (Node_State)index();
803 }
804 void set_state(Node_State ns) {
805 set_index((uint)ns);
806 }
807 };
808
809
810 //------------------------------xform------------------------------------------
811 // Given a Node in old-space, Match him (Label/Reduce) to produce a machine
812 // Node in new-space. Given a new-space Node, recursively walk his children.
813 Node *Matcher::transform( Node *n ) { ShouldNotCallThis(); return n; }
814 Node *Matcher::xform( Node *n, int max_stack ) {
815 // Use one stack to keep both: child's node/state and parent's node/index
816 MStack mstack(max_stack * 2 * 2); // C->unique() * 2 * 2
817 mstack.push(n, Visit, NULL, -1); // set NULL as parent to indicate root
818
819 while (mstack.is_nonempty()) {
820 n = mstack.node(); // Leave node on stack
821 Node_State nstate = mstack.state();
822 if (nstate == Visit) {
823 mstack.set_state(Post_Visit);
824 Node *oldn = n;
825 // Old-space or new-space check
826 if (!C->node_arena()->contains(n)) {
827 // Old space!
828 Node* m;
829 if (has_new_node(n)) { // Not yet Label/Reduced
830 m = new_node(n);
831 } else {
832 if (!is_dontcare(n)) { // Matcher can match this guy
833 // Calls match special. They match alone with no children.
834 // Their children, the incoming arguments, match normally.
835 m = n->is_SafePoint() ? match_sfpt(n->as_SafePoint()):match_tree(n);
836 if (C->failing()) return NULL;
837 if (m == NULL) { Matcher::soft_match_failure(); return NULL; }
838 } else { // Nothing the matcher cares about
839 if( n->is_Proj() && n->in(0)->is_Multi()) { // Projections?
840 // Convert to machine-dependent projection
841 m = n->in(0)->as_Multi()->match( n->as_Proj(), this );
842 #ifdef ASSERT
843 _new2old_map.map(m->_idx, n);
844 #endif
845 if (m->in(0) != NULL) // m might be top
846 collect_null_checks(m, n);
847 } else { // Else just a regular 'ol guy
848 m = n->clone(); // So just clone into new-space
849 #ifdef ASSERT
850 _new2old_map.map(m->_idx, n);
851 #endif
852 // Def-Use edges will be added incrementally as Uses
853 // of this node are matched.
854 assert(m->outcnt() == 0, "no Uses of this clone yet");
855 }
856 }
857
858 set_new_node(n, m); // Map old to new
859 if (_old_node_note_array != NULL) {
860 Node_Notes* nn = C->locate_node_notes(_old_node_note_array,
861 n->_idx);
862 C->set_node_notes_at(m->_idx, nn);
863 }
864 debug_only(match_alias_type(C, n, m));
865 }
866 n = m; // n is now a new-space node
867 mstack.set_node(n);
868 }
869
870 // New space!
871 if (_visited.test_set(n->_idx)) continue; // while(mstack.is_nonempty())
872
873 int i;
874 // Put precedence edges on stack first (match them last).
875 for (i = oldn->req(); (uint)i < oldn->len(); i++) {
876 Node *m = oldn->in(i);
877 if (m == NULL) break;
878 // set -1 to call add_prec() instead of set_req() during Step1
879 mstack.push(m, Visit, n, -1);
880 }
881
882 // For constant debug info, I'd rather have unmatched constants.
883 int cnt = n->req();
884 JVMState* jvms = n->jvms();
885 int debug_cnt = jvms ? jvms->debug_start() : cnt;
886
887 // Now do only debug info. Clone constants rather than matching.
888 // Constants are represented directly in the debug info without
889 // the need for executable machine instructions.
890 // Monitor boxes are also represented directly.
891 for (i = cnt - 1; i >= debug_cnt; --i) { // For all debug inputs do
892 Node *m = n->in(i); // Get input
893 int op = m->Opcode();
894 assert((op == Op_BoxLock) == jvms->is_monitor_use(i), "boxes only at monitor sites");
895 if( op == Op_ConI || op == Op_ConP || op == Op_ConN ||
896 op == Op_ConF || op == Op_ConD || op == Op_ConL
897 // || op == Op_BoxLock // %%%% enable this and remove (+++) in chaitin.cpp
898 ) {
899 m = m->clone();
900 #ifdef ASSERT
901 _new2old_map.map(m->_idx, n);
902 #endif
903 mstack.push(m, Post_Visit, n, i); // Don't neet to visit
904 mstack.push(m->in(0), Visit, m, 0);
905 } else {
906 mstack.push(m, Visit, n, i);
907 }
908 }
909
910 // And now walk his children, and convert his inputs to new-space.
911 for( ; i >= 0; --i ) { // For all normal inputs do
912 Node *m = n->in(i); // Get input
913 if(m != NULL)
914 mstack.push(m, Visit, n, i);
915 }
916
917 }
918 else if (nstate == Post_Visit) {
919 // Set xformed input
920 Node *p = mstack.parent();
921 if (p != NULL) { // root doesn't have parent
922 int i = (int)mstack.index();
923 if (i >= 0)
924 p->set_req(i, n); // required input
925 else if (i == -1)
926 p->add_prec(n); // precedence input
927 else
928 ShouldNotReachHere();
929 }
930 mstack.pop(); // remove processed node from stack
931 }
932 else {
933 ShouldNotReachHere();
934 }
935 } // while (mstack.is_nonempty())
936 return n; // Return new-space Node
937 }
938
939 //------------------------------warp_outgoing_stk_arg------------------------
940 OptoReg::Name Matcher::warp_outgoing_stk_arg( VMReg reg, OptoReg::Name begin_out_arg_area, OptoReg::Name &out_arg_limit_per_call ) {
941 // Convert outgoing argument location to a pre-biased stack offset
942 if (reg->is_stack()) {
943 OptoReg::Name warped = reg->reg2stack();
944 // Adjust the stack slot offset to be the register number used
945 // by the allocator.
946 warped = OptoReg::add(begin_out_arg_area, warped);
947 // Keep track of the largest numbered stack slot used for an arg.
948 // Largest used slot per call-site indicates the amount of stack
949 // that is killed by the call.
950 if( warped >= out_arg_limit_per_call )
951 out_arg_limit_per_call = OptoReg::add(warped,1);
952 if (!RegMask::can_represent(warped)) {
953 C->record_method_not_compilable_all_tiers("unsupported calling sequence");
954 return OptoReg::Bad;
955 }
956 return warped;
957 }
958 return OptoReg::as_OptoReg(reg);
959 }
960
961
962 //------------------------------match_sfpt-------------------------------------
963 // Helper function to match call instructions. Calls match special.
964 // They match alone with no children. Their children, the incoming
965 // arguments, match normally.
966 MachNode *Matcher::match_sfpt( SafePointNode *sfpt ) {
967 MachSafePointNode *msfpt = NULL;
968 MachCallNode *mcall = NULL;
969 uint cnt;
970 // Split out case for SafePoint vs Call
971 CallNode *call;
972 const TypeTuple *domain;
973 ciMethod* method = NULL;
974 if( sfpt->is_Call() ) {
975 call = sfpt->as_Call();
976 domain = call->tf()->domain();
977 cnt = domain->cnt();
978
979 // Match just the call, nothing else
980 MachNode *m = match_tree(call);
981 if (C->failing()) return NULL;
982 if( m == NULL ) { Matcher::soft_match_failure(); return NULL; }
983
984 // Copy data from the Ideal SafePoint to the machine version
985 mcall = m->as_MachCall();
986
987 mcall->set_tf( call->tf());
988 mcall->set_entry_point(call->entry_point());
989 mcall->set_cnt( call->cnt());
990
991 if( mcall->is_MachCallJava() ) {
992 MachCallJavaNode *mcall_java = mcall->as_MachCallJava();
993 const CallJavaNode *call_java = call->as_CallJava();
994 method = call_java->method();
995 mcall_java->_method = method;
996 mcall_java->_bci = call_java->_bci;
997 mcall_java->_optimized_virtual = call_java->is_optimized_virtual();
998 if( mcall_java->is_MachCallStaticJava() )
999 mcall_java->as_MachCallStaticJava()->_name =
1000 call_java->as_CallStaticJava()->_name;
1001 if( mcall_java->is_MachCallDynamicJava() )
1002 mcall_java->as_MachCallDynamicJava()->_vtable_index =
1003 call_java->as_CallDynamicJava()->_vtable_index;
1004 }
1005 else if( mcall->is_MachCallRuntime() ) {
1006 mcall->as_MachCallRuntime()->_name = call->as_CallRuntime()->_name;
1007 }
1008 msfpt = mcall;
1009 }
1010 // This is a non-call safepoint
1011 else {
1012 call = NULL;
1013 domain = NULL;
1014 MachNode *mn = match_tree(sfpt);
1015 if (C->failing()) return NULL;
1016 msfpt = mn->as_MachSafePoint();
1017 cnt = TypeFunc::Parms;
1018 }
1019
1020 // Advertise the correct memory effects (for anti-dependence computation).
1021 msfpt->set_adr_type(sfpt->adr_type());
1022
1023 // Allocate a private array of RegMasks. These RegMasks are not shared.
1024 msfpt->_in_rms = NEW_RESOURCE_ARRAY( RegMask, cnt );
1025 // Empty them all.
1026 memset( msfpt->_in_rms, 0, sizeof(RegMask)*cnt );
1027
1028 // Do all the pre-defined non-Empty register masks
1029 msfpt->_in_rms[TypeFunc::ReturnAdr] = _return_addr_mask;
1030 msfpt->_in_rms[TypeFunc::FramePtr ] = c_frame_ptr_mask;
1031
1032 // Place first outgoing argument can possibly be put.
1033 OptoReg::Name begin_out_arg_area = OptoReg::add(_new_SP, C->out_preserve_stack_slots());
1034 assert( is_even(begin_out_arg_area), "" );
1035 // Compute max outgoing register number per call site.
1036 OptoReg::Name out_arg_limit_per_call = begin_out_arg_area;
1037 // Calls to C may hammer extra stack slots above and beyond any arguments.
1038 // These are usually backing store for register arguments for varargs.
1039 if( call != NULL && call->is_CallRuntime() )
1040 out_arg_limit_per_call = OptoReg::add(out_arg_limit_per_call,C->varargs_C_out_slots_killed());
1041
1042
1043 // Do the normal argument list (parameters) register masks
1044 int argcnt = cnt - TypeFunc::Parms;
1045 if( argcnt > 0 ) { // Skip it all if we have no args
1046 BasicType *sig_bt = NEW_RESOURCE_ARRAY( BasicType, argcnt );
1047 VMRegPair *parm_regs = NEW_RESOURCE_ARRAY( VMRegPair, argcnt );
1048 int i;
1049 for( i = 0; i < argcnt; i++ ) {
1050 sig_bt[i] = domain->field_at(i+TypeFunc::Parms)->basic_type();
1051 }
1052 // V-call to pick proper calling convention
1053 call->calling_convention( sig_bt, parm_regs, argcnt );
1054
1055 #ifdef ASSERT
1056 // Sanity check users' calling convention. Really handy during
1057 // the initial porting effort. Fairly expensive otherwise.
1058 { for (int i = 0; i<argcnt; i++) {
1059 if( !parm_regs[i].first()->is_valid() &&
1060 !parm_regs[i].second()->is_valid() ) continue;
1061 VMReg reg1 = parm_regs[i].first();
1062 VMReg reg2 = parm_regs[i].second();
1063 for (int j = 0; j < i; j++) {
1064 if( !parm_regs[j].first()->is_valid() &&
1065 !parm_regs[j].second()->is_valid() ) continue;
1066 VMReg reg3 = parm_regs[j].first();
1067 VMReg reg4 = parm_regs[j].second();
1068 if( !reg1->is_valid() ) {
1069 assert( !reg2->is_valid(), "valid halvsies" );
1070 } else if( !reg3->is_valid() ) {
1071 assert( !reg4->is_valid(), "valid halvsies" );
1072 } else {
1073 assert( reg1 != reg2, "calling conv. must produce distinct regs");
1074 assert( reg1 != reg3, "calling conv. must produce distinct regs");
1075 assert( reg1 != reg4, "calling conv. must produce distinct regs");
1076 assert( reg2 != reg3, "calling conv. must produce distinct regs");
1077 assert( reg2 != reg4 || !reg2->is_valid(), "calling conv. must produce distinct regs");
1078 assert( reg3 != reg4, "calling conv. must produce distinct regs");
1079 }
1080 }
1081 }
1082 }
1083 #endif
1084
1085 // Visit each argument. Compute its outgoing register mask.
1086 // Return results now can have 2 bits returned.
1087 // Compute max over all outgoing arguments both per call-site
1088 // and over the entire method.
1089 for( i = 0; i < argcnt; i++ ) {
1090 // Address of incoming argument mask to fill in
1091 RegMask *rm = &mcall->_in_rms[i+TypeFunc::Parms];
1092 if( !parm_regs[i].first()->is_valid() &&
1093 !parm_regs[i].second()->is_valid() ) {
1094 continue; // Avoid Halves
1095 }
1096 // Grab first register, adjust stack slots and insert in mask.
1097 OptoReg::Name reg1 = warp_outgoing_stk_arg(parm_regs[i].first(), begin_out_arg_area, out_arg_limit_per_call );
1098 if (OptoReg::is_valid(reg1))
1099 rm->Insert( reg1 );
1100 // Grab second register (if any), adjust stack slots and insert in mask.
1101 OptoReg::Name reg2 = warp_outgoing_stk_arg(parm_regs[i].second(), begin_out_arg_area, out_arg_limit_per_call );
1102 if (OptoReg::is_valid(reg2))
1103 rm->Insert( reg2 );
1104 } // End of for all arguments
1105
1106 // Compute number of stack slots needed to restore stack in case of
1107 // Pascal-style argument popping.
1108 mcall->_argsize = out_arg_limit_per_call - begin_out_arg_area;
1109 }
1110
1111 // Compute the max stack slot killed by any call. These will not be
1112 // available for debug info, and will be used to adjust FIRST_STACK_mask
1113 // after all call sites have been visited.
1114 if( _out_arg_limit < out_arg_limit_per_call)
1115 _out_arg_limit = out_arg_limit_per_call;
1116
1117 if (mcall) {
1118 // Kill the outgoing argument area, including any non-argument holes and
1119 // any legacy C-killed slots. Use Fat-Projections to do the killing.
1120 // Since the max-per-method covers the max-per-call-site and debug info
1121 // is excluded on the max-per-method basis, debug info cannot land in
1122 // this killed area.
1123 uint r_cnt = mcall->tf()->range()->cnt();
1124 MachProjNode *proj = new (C, 1) MachProjNode( mcall, r_cnt+10000, RegMask::Empty, MachProjNode::fat_proj );
1125 if (!RegMask::can_represent(OptoReg::Name(out_arg_limit_per_call-1))) {
1126 C->record_method_not_compilable_all_tiers("unsupported outgoing calling sequence");
1127 } else {
1128 for (int i = begin_out_arg_area; i < out_arg_limit_per_call; i++)
1129 proj->_rout.Insert(OptoReg::Name(i));
1130 }
1131 if( proj->_rout.is_NotEmpty() )
1132 _proj_list.push(proj);
1133 }
1134 // Transfer the safepoint information from the call to the mcall
1135 // Move the JVMState list
1136 msfpt->set_jvms(sfpt->jvms());
1137 for (JVMState* jvms = msfpt->jvms(); jvms; jvms = jvms->caller()) {
1138 jvms->set_map(sfpt);
1139 }
1140
1141 // Debug inputs begin just after the last incoming parameter
1142 assert( (mcall == NULL) || (mcall->jvms() == NULL) ||
1143 (mcall->jvms()->debug_start() + mcall->_jvmadj == mcall->tf()->domain()->cnt()), "" );
1144
1145 // Move the OopMap
1146 msfpt->_oop_map = sfpt->_oop_map;
1147
1148 // Registers killed by the call are set in the local scheduling pass
1149 // of Global Code Motion.
1150 return msfpt;
1151 }
1152
1153 //---------------------------match_tree----------------------------------------
1154 // Match a Ideal Node DAG - turn it into a tree; Label & Reduce. Used as part
1155 // of the whole-sale conversion from Ideal to Mach Nodes. Also used for
1156 // making GotoNodes while building the CFG and in init_spill_mask() to identify
1157 // a Load's result RegMask for memoization in idealreg2regmask[]
1158 MachNode *Matcher::match_tree( const Node *n ) {
1159 assert( n->Opcode() != Op_Phi, "cannot match" );
1160 assert( !n->is_block_start(), "cannot match" );
1161 // Set the mark for all locally allocated State objects.
1162 // When this call returns, the _states_arena arena will be reset
1163 // freeing all State objects.
1164 ResourceMark rm( &_states_arena );
1165
1166 LabelRootDepth = 0;
1167
1168 // StoreNodes require their Memory input to match any LoadNodes
1169 Node *mem = n->is_Store() ? n->in(MemNode::Memory) : (Node*)1 ;
1170 #ifdef ASSERT
1171 Node* save_mem_node = _mem_node;
1172 _mem_node = n->is_Store() ? (Node*)n : NULL;
1173 #endif
1174 // State object for root node of match tree
1175 // Allocate it on _states_arena - stack allocation can cause stack overflow.
1176 State *s = new (&_states_arena) State;
1177 s->_kids[0] = NULL;
1178 s->_kids[1] = NULL;
1179 s->_leaf = (Node*)n;
1180 // Label the input tree, allocating labels from top-level arena
1181 Label_Root( n, s, n->in(0), mem );
1182 if (C->failing()) return NULL;
1183
1184 // The minimum cost match for the whole tree is found at the root State
1185 uint mincost = max_juint;
1186 uint cost = max_juint;
1187 uint i;
1188 for( i = 0; i < NUM_OPERANDS; i++ ) {
1189 if( s->valid(i) && // valid entry and
1190 s->_cost[i] < cost && // low cost and
1191 s->_rule[i] >= NUM_OPERANDS ) // not an operand
1192 cost = s->_cost[mincost=i];
1193 }
1194 if (mincost == max_juint) {
1195 #ifndef PRODUCT
1196 tty->print("No matching rule for:");
1197 s->dump();
1198 #endif
1199 Matcher::soft_match_failure();
1200 return NULL;
1201 }
1202 // Reduce input tree based upon the state labels to machine Nodes
1203 MachNode *m = ReduceInst( s, s->_rule[mincost], mem );
1204 #ifdef ASSERT
1205 _old2new_map.map(n->_idx, m);
1206 _new2old_map.map(m->_idx, (Node*)n);
1207 #endif
1208
1209 // Add any Matcher-ignored edges
1210 uint cnt = n->req();
1211 uint start = 1;
1212 if( mem != (Node*)1 ) start = MemNode::Memory+1;
1213 if( n->is_AddP() ) {
1214 assert( mem == (Node*)1, "" );
1215 start = AddPNode::Base+1;
1216 }
1217 for( i = start; i < cnt; i++ ) {
1218 if( !n->match_edge(i) ) {
1219 if( i < m->req() )
1220 m->ins_req( i, n->in(i) );
1221 else
1222 m->add_req( n->in(i) );
1223 }
1224 }
1225
1226 debug_only( _mem_node = save_mem_node; )
1227 return m;
1228 }
1229
1230
1231 //------------------------------match_into_reg---------------------------------
1232 // Choose to either match this Node in a register or part of the current
1233 // match tree. Return true for requiring a register and false for matching
1234 // as part of the current match tree.
1235 static bool match_into_reg( const Node *n, Node *m, Node *control, int i, bool shared ) {
1236
1237 const Type *t = m->bottom_type();
1238
1239 if( t->singleton() ) {
1240 // Never force constants into registers. Allow them to match as
1241 // constants or registers. Copies of the same value will share
1242 // the same register. See find_shared_node.
1243 return false;
1244 } else { // Not a constant
1245 // Stop recursion if they have different Controls.
1246 // Slot 0 of constants is not really a Control.
1247 if( control && m->in(0) && control != m->in(0) ) {
1248
1249 // Actually, we can live with the most conservative control we
1250 // find, if it post-dominates the others. This allows us to
1251 // pick up load/op/store trees where the load can float a little
1252 // above the store.
1253 Node *x = control;
1254 const uint max_scan = 6; // Arbitrary scan cutoff
1255 uint j;
1256 for( j=0; j<max_scan; j++ ) {
1257 if( x->is_Region() ) // Bail out at merge points
1258 return true;
1259 x = x->in(0);
1260 if( x == m->in(0) ) // Does 'control' post-dominate
1261 break; // m->in(0)? If so, we can use it
1262 }
1263 if( j == max_scan ) // No post-domination before scan end?
1264 return true; // Then break the match tree up
1265 }
1266 if (m->is_DecodeN() && Matcher::clone_shift_expressions) {
1267 // These are commonly used in address expressions and can
1268 // efficiently fold into them on X64 in some cases.
1269 return false;
1270 }
1271 }
1272
1273 // Not forceably cloning. If shared, put it into a register.
1274 return shared;
1275 }
1276
1277
1278 //------------------------------Instruction Selection--------------------------
1279 // Label method walks a "tree" of nodes, using the ADLC generated DFA to match
1280 // ideal nodes to machine instructions. Trees are delimited by shared Nodes,
1281 // things the Matcher does not match (e.g., Memory), and things with different
1282 // Controls (hence forced into different blocks). We pass in the Control
1283 // selected for this entire State tree.
1284
1285 // The Matcher works on Trees, but an Intel add-to-memory requires a DAG: the
1286 // Store and the Load must have identical Memories (as well as identical
1287 // pointers). Since the Matcher does not have anything for Memory (and
1288 // does not handle DAGs), I have to match the Memory input myself. If the
1289 // Tree root is a Store, I require all Loads to have the identical memory.
1290 Node *Matcher::Label_Root( const Node *n, State *svec, Node *control, const Node *mem){
1291 // Since Label_Root is a recursive function, its possible that we might run
1292 // out of stack space. See bugs 6272980 & 6227033 for more info.
1293 LabelRootDepth++;
1294 if (LabelRootDepth > MaxLabelRootDepth) {
1295 C->record_method_not_compilable_all_tiers("Out of stack space, increase MaxLabelRootDepth");
1296 return NULL;
1297 }
1298 uint care = 0; // Edges matcher cares about
1299 uint cnt = n->req();
1300 uint i = 0;
1301
1302 // Examine children for memory state
1303 // Can only subsume a child into your match-tree if that child's memory state
1304 // is not modified along the path to another input.
1305 // It is unsafe even if the other inputs are separate roots.
1306 Node *input_mem = NULL;
1307 for( i = 1; i < cnt; i++ ) {
1308 if( !n->match_edge(i) ) continue;
1309 Node *m = n->in(i); // Get ith input
1310 assert( m, "expect non-null children" );
1311 if( m->is_Load() ) {
1312 if( input_mem == NULL ) {
1313 input_mem = m->in(MemNode::Memory);
1314 } else if( input_mem != m->in(MemNode::Memory) ) {
1315 input_mem = NodeSentinel;
1316 }
1317 }
1318 }
1319
1320 for( i = 1; i < cnt; i++ ){// For my children
1321 if( !n->match_edge(i) ) continue;
1322 Node *m = n->in(i); // Get ith input
1323 // Allocate states out of a private arena
1324 State *s = new (&_states_arena) State;
1325 svec->_kids[care++] = s;
1326 assert( care <= 2, "binary only for now" );
1327
1328 // Recursively label the State tree.
1329 s->_kids[0] = NULL;
1330 s->_kids[1] = NULL;
1331 s->_leaf = m;
1332
1333 // Check for leaves of the State Tree; things that cannot be a part of
1334 // the current tree. If it finds any, that value is matched as a
1335 // register operand. If not, then the normal matching is used.
1336 if( match_into_reg(n, m, control, i, is_shared(m)) ||
1337 //
1338 // Stop recursion if this is LoadNode and the root of this tree is a
1339 // StoreNode and the load & store have different memories.
1340 ((mem!=(Node*)1) && m->is_Load() && m->in(MemNode::Memory) != mem) ||
1341 // Can NOT include the match of a subtree when its memory state
1342 // is used by any of the other subtrees
1343 (input_mem == NodeSentinel) ) {
1344 #ifndef PRODUCT
1345 // Print when we exclude matching due to different memory states at input-loads
1346 if( PrintOpto && (Verbose && WizardMode) && (input_mem == NodeSentinel)
1347 && !((mem!=(Node*)1) && m->is_Load() && m->in(MemNode::Memory) != mem) ) {
1348 tty->print_cr("invalid input_mem");
1349 }
1350 #endif
1351 // Switch to a register-only opcode; this value must be in a register
1352 // and cannot be subsumed as part of a larger instruction.
1353 s->DFA( m->ideal_reg(), m );
1354
1355 } else {
1356 // If match tree has no control and we do, adopt it for entire tree
1357 if( control == NULL && m->in(0) != NULL && m->req() > 1 )
1358 control = m->in(0); // Pick up control
1359 // Else match as a normal part of the match tree.
1360 control = Label_Root(m,s,control,mem);
1361 if (C->failing()) return NULL;
1362 }
1363 }
1364
1365
1366 // Call DFA to match this node, and return
1367 svec->DFA( n->Opcode(), n );
1368
1369 #ifdef ASSERT
1370 uint x;
1371 for( x = 0; x < _LAST_MACH_OPER; x++ )
1372 if( svec->valid(x) )
1373 break;
1374
1375 if (x >= _LAST_MACH_OPER) {
1376 n->dump();
1377 svec->dump();
1378 assert( false, "bad AD file" );
1379 }
1380 #endif
1381 return control;
1382 }
1383
1384
1385 // Con nodes reduced using the same rule can share their MachNode
1386 // which reduces the number of copies of a constant in the final
1387 // program. The register allocator is free to split uses later to
1388 // split live ranges.
1389 MachNode* Matcher::find_shared_node(Node* leaf, uint rule) {
1390 if (!leaf->is_Con() && !leaf->is_DecodeN()) return NULL;
1391
1392 // See if this Con has already been reduced using this rule.
1393 if (_shared_nodes.Size() <= leaf->_idx) return NULL;
1394 MachNode* last = (MachNode*)_shared_nodes.at(leaf->_idx);
1395 if (last != NULL && rule == last->rule()) {
1396 // Don't expect control change for DecodeN
1397 if (leaf->is_DecodeN())
1398 return last;
1399 // Get the new space root.
1400 Node* xroot = new_node(C->root());
1401 if (xroot == NULL) {
1402 // This shouldn't happen give the order of matching.
1403 return NULL;
1404 }
1405
1406 // Shared constants need to have their control be root so they
1407 // can be scheduled properly.
1408 Node* control = last->in(0);
1409 if (control != xroot) {
1410 if (control == NULL || control == C->root()) {
1411 last->set_req(0, xroot);
1412 } else {
1413 assert(false, "unexpected control");
1414 return NULL;
1415 }
1416 }
1417 return last;
1418 }
1419 return NULL;
1420 }
1421
1422
1423 //------------------------------ReduceInst-------------------------------------
1424 // Reduce a State tree (with given Control) into a tree of MachNodes.
1425 // This routine (and it's cohort ReduceOper) convert Ideal Nodes into
1426 // complicated machine Nodes. Each MachNode covers some tree of Ideal Nodes.
1427 // Each MachNode has a number of complicated MachOper operands; each
1428 // MachOper also covers a further tree of Ideal Nodes.
1429
1430 // The root of the Ideal match tree is always an instruction, so we enter
1431 // the recursion here. After building the MachNode, we need to recurse
1432 // the tree checking for these cases:
1433 // (1) Child is an instruction -
1434 // Build the instruction (recursively), add it as an edge.
1435 // Build a simple operand (register) to hold the result of the instruction.
1436 // (2) Child is an interior part of an instruction -
1437 // Skip over it (do nothing)
1438 // (3) Child is the start of a operand -
1439 // Build the operand, place it inside the instruction
1440 // Call ReduceOper.
1441 MachNode *Matcher::ReduceInst( State *s, int rule, Node *&mem ) {
1442 assert( rule >= NUM_OPERANDS, "called with operand rule" );
1443
1444 MachNode* shared_node = find_shared_node(s->_leaf, rule);
1445 if (shared_node != NULL) {
1446 return shared_node;
1447 }
1448
1449 // Build the object to represent this state & prepare for recursive calls
1450 MachNode *mach = s->MachNodeGenerator( rule, C );
1451 mach->_opnds[0] = s->MachOperGenerator( _reduceOp[rule], C );
1452 assert( mach->_opnds[0] != NULL, "Missing result operand" );
1453 Node *leaf = s->_leaf;
1454 // Check for instruction or instruction chain rule
1455 if( rule >= _END_INST_CHAIN_RULE || rule < _BEGIN_INST_CHAIN_RULE ) {
1456 assert(C->node_arena()->contains(s->_leaf) || !has_new_node(s->_leaf),
1457 "duplicating node that's already been matched");
1458 // Instruction
1459 mach->add_req( leaf->in(0) ); // Set initial control
1460 // Reduce interior of complex instruction
1461 ReduceInst_Interior( s, rule, mem, mach, 1 );
1462 } else {
1463 // Instruction chain rules are data-dependent on their inputs
1464 mach->add_req(0); // Set initial control to none
1465 ReduceInst_Chain_Rule( s, rule, mem, mach );
1466 }
1467
1468 // If a Memory was used, insert a Memory edge
1469 if( mem != (Node*)1 ) {
1470 mach->ins_req(MemNode::Memory,mem);
1471 #ifdef ASSERT
1472 // Verify adr type after matching memory operation
1473 const MachOper* oper = mach->memory_operand();
1474 if (oper != NULL && oper != (MachOper*)-1 &&
1475 mach->adr_type() != TypeRawPtr::BOTTOM) { // non-direct addressing mode
1476 // It has a unique memory operand. Find corresponding ideal mem node.
1477 Node* m = NULL;
1478 if (leaf->is_Mem()) {
1479 m = leaf;
1480 } else {
1481 m = _mem_node;
1482 assert(m != NULL && m->is_Mem(), "expecting memory node");
1483 }
1484 const Type* mach_at = mach->adr_type();
1485 // DecodeN node consumed by an address may have different type
1486 // then its input. Don't compare types for such case.
1487 if (m->adr_type() != mach_at && m->in(MemNode::Address)->is_AddP() &&
1488 m->in(MemNode::Address)->in(AddPNode::Address)->is_DecodeN()) {
1489 mach_at = m->adr_type();
1490 }
1491 if (m->adr_type() != mach_at) {
1492 m->dump();
1493 tty->print_cr("mach:");
1494 mach->dump(1);
1495 }
1496 assert(m->adr_type() == mach_at, "matcher should not change adr type");
1497 }
1498 #endif
1499 }
1500
1501 // If the _leaf is an AddP, insert the base edge
1502 if( leaf->is_AddP() )
1503 mach->ins_req(AddPNode::Base,leaf->in(AddPNode::Base));
1504
1505 uint num_proj = _proj_list.size();
1506
1507 // Perform any 1-to-many expansions required
1508 MachNode *ex = mach->Expand(s,_proj_list);
1509 if( ex != mach ) {
1510 assert(ex->ideal_reg() == mach->ideal_reg(), "ideal types should match");
1511 if( ex->in(1)->is_Con() )
1512 ex->in(1)->set_req(0, C->root());
1513 // Remove old node from the graph
1514 for( uint i=0; i<mach->req(); i++ ) {
1515 mach->set_req(i,NULL);
1516 }
1517 #ifdef ASSERT
1518 _new2old_map.map(ex->_idx, s->_leaf);
1519 #endif
1520 }
1521
1522 // PhaseChaitin::fixup_spills will sometimes generate spill code
1523 // via the matcher. By the time, nodes have been wired into the CFG,
1524 // and any further nodes generated by expand rules will be left hanging
1525 // in space, and will not get emitted as output code. Catch this.
1526 // Also, catch any new register allocation constraints ("projections")
1527 // generated belatedly during spill code generation.
1528 if (_allocation_started) {
1529 guarantee(ex == mach, "no expand rules during spill generation");
1530 guarantee(_proj_list.size() == num_proj, "no allocation during spill generation");
1531 }
1532
1533 if (leaf->is_Con() || leaf->is_DecodeN()) {
1534 // Record the con for sharing
1535 _shared_nodes.map(leaf->_idx, ex);
1536 }
1537
1538 return ex;
1539 }
1540
1541 void Matcher::ReduceInst_Chain_Rule( State *s, int rule, Node *&mem, MachNode *mach ) {
1542 // 'op' is what I am expecting to receive
1543 int op = _leftOp[rule];
1544 // Operand type to catch childs result
1545 // This is what my child will give me.
1546 int opnd_class_instance = s->_rule[op];
1547 // Choose between operand class or not.
1548 // This is what I will recieve.
1549 int catch_op = (FIRST_OPERAND_CLASS <= op && op < NUM_OPERANDS) ? opnd_class_instance : op;
1550 // New rule for child. Chase operand classes to get the actual rule.
1551 int newrule = s->_rule[catch_op];
1552
1553 if( newrule < NUM_OPERANDS ) {
1554 // Chain from operand or operand class, may be output of shared node
1555 assert( 0 <= opnd_class_instance && opnd_class_instance < NUM_OPERANDS,
1556 "Bad AD file: Instruction chain rule must chain from operand");
1557 // Insert operand into array of operands for this instruction
1558 mach->_opnds[1] = s->MachOperGenerator( opnd_class_instance, C );
1559
1560 ReduceOper( s, newrule, mem, mach );
1561 } else {
1562 // Chain from the result of an instruction
1563 assert( newrule >= _LAST_MACH_OPER, "Do NOT chain from internal operand");
1564 mach->_opnds[1] = s->MachOperGenerator( _reduceOp[catch_op], C );
1565 Node *mem1 = (Node*)1;
1566 debug_only(Node *save_mem_node = _mem_node;)
1567 mach->add_req( ReduceInst(s, newrule, mem1) );
1568 debug_only(_mem_node = save_mem_node;)
1569 }
1570 return;
1571 }
1572
1573
1574 uint Matcher::ReduceInst_Interior( State *s, int rule, Node *&mem, MachNode *mach, uint num_opnds ) {
1575 if( s->_leaf->is_Load() ) {
1576 Node *mem2 = s->_leaf->in(MemNode::Memory);
1577 assert( mem == (Node*)1 || mem == mem2, "multiple Memories being matched at once?" );
1578 debug_only( if( mem == (Node*)1 ) _mem_node = s->_leaf;)
1579 mem = mem2;
1580 }
1581 if( s->_leaf->in(0) != NULL && s->_leaf->req() > 1) {
1582 if( mach->in(0) == NULL )
1583 mach->set_req(0, s->_leaf->in(0));
1584 }
1585
1586 // Now recursively walk the state tree & add operand list.
1587 for( uint i=0; i<2; i++ ) { // binary tree
1588 State *newstate = s->_kids[i];
1589 if( newstate == NULL ) break; // Might only have 1 child
1590 // 'op' is what I am expecting to receive
1591 int op;
1592 if( i == 0 ) {
1593 op = _leftOp[rule];
1594 } else {
1595 op = _rightOp[rule];
1596 }
1597 // Operand type to catch childs result
1598 // This is what my child will give me.
1599 int opnd_class_instance = newstate->_rule[op];
1600 // Choose between operand class or not.
1601 // This is what I will receive.
1602 int catch_op = (op >= FIRST_OPERAND_CLASS && op < NUM_OPERANDS) ? opnd_class_instance : op;
1603 // New rule for child. Chase operand classes to get the actual rule.
1604 int newrule = newstate->_rule[catch_op];
1605
1606 if( newrule < NUM_OPERANDS ) { // Operand/operandClass or internalOp/instruction?
1607 // Operand/operandClass
1608 // Insert operand into array of operands for this instruction
1609 mach->_opnds[num_opnds++] = newstate->MachOperGenerator( opnd_class_instance, C );
1610 ReduceOper( newstate, newrule, mem, mach );
1611
1612 } else { // Child is internal operand or new instruction
1613 if( newrule < _LAST_MACH_OPER ) { // internal operand or instruction?
1614 // internal operand --> call ReduceInst_Interior
1615 // Interior of complex instruction. Do nothing but recurse.
1616 num_opnds = ReduceInst_Interior( newstate, newrule, mem, mach, num_opnds );
1617 } else {
1618 // instruction --> call build operand( ) to catch result
1619 // --> ReduceInst( newrule )
1620 mach->_opnds[num_opnds++] = s->MachOperGenerator( _reduceOp[catch_op], C );
1621 Node *mem1 = (Node*)1;
1622 debug_only(Node *save_mem_node = _mem_node;)
1623 mach->add_req( ReduceInst( newstate, newrule, mem1 ) );
1624 debug_only(_mem_node = save_mem_node;)
1625 }
1626 }
1627 assert( mach->_opnds[num_opnds-1], "" );
1628 }
1629 return num_opnds;
1630 }
1631
1632 // This routine walks the interior of possible complex operands.
1633 // At each point we check our children in the match tree:
1634 // (1) No children -
1635 // We are a leaf; add _leaf field as an input to the MachNode
1636 // (2) Child is an internal operand -
1637 // Skip over it ( do nothing )
1638 // (3) Child is an instruction -
1639 // Call ReduceInst recursively and
1640 // and instruction as an input to the MachNode
1641 void Matcher::ReduceOper( State *s, int rule, Node *&mem, MachNode *mach ) {
1642 assert( rule < _LAST_MACH_OPER, "called with operand rule" );
1643 State *kid = s->_kids[0];
1644 assert( kid == NULL || s->_leaf->in(0) == NULL, "internal operands have no control" );
1645
1646 // Leaf? And not subsumed?
1647 if( kid == NULL && !_swallowed[rule] ) {
1648 mach->add_req( s->_leaf ); // Add leaf pointer
1649 return; // Bail out
1650 }
1651
1652 if( s->_leaf->is_Load() ) {
1653 assert( mem == (Node*)1, "multiple Memories being matched at once?" );
1654 mem = s->_leaf->in(MemNode::Memory);
1655 debug_only(_mem_node = s->_leaf;)
1656 }
1657 if( s->_leaf->in(0) && s->_leaf->req() > 1) {
1658 if( !mach->in(0) )
1659 mach->set_req(0,s->_leaf->in(0));
1660 else {
1661 assert( s->_leaf->in(0) == mach->in(0), "same instruction, differing controls?" );
1662 }
1663 }
1664
1665 for( uint i=0; kid != NULL && i<2; kid = s->_kids[1], i++ ) { // binary tree
1666 int newrule;
1667 if( i == 0 )
1668 newrule = kid->_rule[_leftOp[rule]];
1669 else
1670 newrule = kid->_rule[_rightOp[rule]];
1671
1672 if( newrule < _LAST_MACH_OPER ) { // Operand or instruction?
1673 // Internal operand; recurse but do nothing else
1674 ReduceOper( kid, newrule, mem, mach );
1675
1676 } else { // Child is a new instruction
1677 // Reduce the instruction, and add a direct pointer from this
1678 // machine instruction to the newly reduced one.
1679 Node *mem1 = (Node*)1;
1680 debug_only(Node *save_mem_node = _mem_node;)
1681 mach->add_req( ReduceInst( kid, newrule, mem1 ) );
1682 debug_only(_mem_node = save_mem_node;)
1683 }
1684 }
1685 }
1686
1687
1688 // -------------------------------------------------------------------------
1689 // Java-Java calling convention
1690 // (what you use when Java calls Java)
1691
1692 //------------------------------find_receiver----------------------------------
1693 // For a given signature, return the OptoReg for parameter 0.
1694 OptoReg::Name Matcher::find_receiver( bool is_outgoing ) {
1695 VMRegPair regs;
1696 BasicType sig_bt = T_OBJECT;
1697 calling_convention(&sig_bt, ®s, 1, is_outgoing);
1698 // Return argument 0 register. In the LP64 build pointers
1699 // take 2 registers, but the VM wants only the 'main' name.
1700 return OptoReg::as_OptoReg(regs.first());
1701 }
1702
1703 // A method-klass-holder may be passed in the inline_cache_reg
1704 // and then expanded into the inline_cache_reg and a method_oop register
1705 // defined in ad_<arch>.cpp
1706
1707
1708 //------------------------------find_shared------------------------------------
1709 // Set bits if Node is shared or otherwise a root
1710 void Matcher::find_shared( Node *n ) {
1711 // Allocate stack of size C->unique() * 2 to avoid frequent realloc
1712 MStack mstack(C->unique() * 2);
1713 mstack.push(n, Visit); // Don't need to pre-visit root node
1714 while (mstack.is_nonempty()) {
1715 n = mstack.node(); // Leave node on stack
1716 Node_State nstate = mstack.state();
1717 if (nstate == Pre_Visit) {
1718 if (is_visited(n)) { // Visited already?
1719 // Node is shared and has no reason to clone. Flag it as shared.
1720 // This causes it to match into a register for the sharing.
1721 set_shared(n); // Flag as shared and
1722 mstack.pop(); // remove node from stack
1723 continue;
1724 }
1725 nstate = Visit; // Not already visited; so visit now
1726 }
1727 if (nstate == Visit) {
1728 mstack.set_state(Post_Visit);
1729 set_visited(n); // Flag as visited now
1730 bool mem_op = false;
1731
1732 switch( n->Opcode() ) { // Handle some opcodes special
1733 case Op_Phi: // Treat Phis as shared roots
1734 case Op_Parm:
1735 case Op_Proj: // All handled specially during matching
1736 case Op_SafePointScalarObject:
1737 set_shared(n);
1738 set_dontcare(n);
1739 break;
1740 case Op_If:
1741 case Op_CountedLoopEnd:
1742 mstack.set_state(Alt_Post_Visit); // Alternative way
1743 // Convert (If (Bool (CmpX A B))) into (If (Bool) (CmpX A B)). Helps
1744 // with matching cmp/branch in 1 instruction. The Matcher needs the
1745 // Bool and CmpX side-by-side, because it can only get at constants
1746 // that are at the leaves of Match trees, and the Bool's condition acts
1747 // as a constant here.
1748 mstack.push(n->in(1), Visit); // Clone the Bool
1749 mstack.push(n->in(0), Pre_Visit); // Visit control input
1750 continue; // while (mstack.is_nonempty())
1751 case Op_ConvI2D: // These forms efficiently match with a prior
1752 case Op_ConvI2F: // Load but not a following Store
1753 if( n->in(1)->is_Load() && // Prior load
1754 n->outcnt() == 1 && // Not already shared
1755 n->unique_out()->is_Store() ) // Following store
1756 set_shared(n); // Force it to be a root
1757 break;
1758 case Op_ReverseBytesI:
1759 case Op_ReverseBytesL:
1760 if( n->in(1)->is_Load() && // Prior load
1761 n->outcnt() == 1 ) // Not already shared
1762 set_shared(n); // Force it to be a root
1763 break;
1764 case Op_BoxLock: // Cant match until we get stack-regs in ADLC
1765 case Op_IfFalse:
1766 case Op_IfTrue:
1767 case Op_MachProj:
1768 case Op_MergeMem:
1769 case Op_Catch:
1770 case Op_CatchProj:
1771 case Op_CProj:
1772 case Op_JumpProj:
1773 case Op_JProj:
1774 case Op_NeverBranch:
1775 set_dontcare(n);
1776 break;
1777 case Op_Jump:
1778 mstack.push(n->in(1), Visit); // Switch Value
1779 mstack.push(n->in(0), Pre_Visit); // Visit Control input
1780 continue; // while (mstack.is_nonempty())
1781 case Op_StrComp:
1782 case Op_AryEq:
1783 set_shared(n); // Force result into register (it will be anyways)
1784 break;
1785 case Op_ConP: { // Convert pointers above the centerline to NUL
1786 TypeNode *tn = n->as_Type(); // Constants derive from type nodes
1787 const TypePtr* tp = tn->type()->is_ptr();
1788 if (tp->_ptr == TypePtr::AnyNull) {
1789 tn->set_type(TypePtr::NULL_PTR);
1790 }
1791 break;
1792 }
1793 case Op_ConN: { // Convert narrow pointers above the centerline to NUL
1794 TypeNode *tn = n->as_Type(); // Constants derive from type nodes
1795 const TypePtr* tp = tn->type()->make_ptr();
1796 if (tp && tp->_ptr == TypePtr::AnyNull) {
1797 tn->set_type(TypeNarrowOop::NULL_PTR);
1798 }
1799 break;
1800 }
1801 case Op_Binary: // These are introduced in the Post_Visit state.
1802 ShouldNotReachHere();
1803 break;
1804 case Op_StoreB: // Do match these, despite no ideal reg
1805 case Op_StoreC:
1806 case Op_StoreCM:
1807 case Op_StoreD:
1808 case Op_StoreF:
1809 case Op_StoreI:
1810 case Op_StoreL:
1811 case Op_StoreP:
1812 case Op_StoreN:
1813 case Op_Store16B:
1814 case Op_Store8B:
1815 case Op_Store4B:
1816 case Op_Store8C:
1817 case Op_Store4C:
1818 case Op_Store2C:
1819 case Op_Store4I:
1820 case Op_Store2I:
1821 case Op_Store2L:
1822 case Op_Store4F:
1823 case Op_Store2F:
1824 case Op_Store2D:
1825 case Op_ClearArray:
1826 case Op_SafePoint:
1827 mem_op = true;
1828 break;
1829 case Op_LoadB:
1830 case Op_LoadC:
1831 case Op_LoadD:
1832 case Op_LoadF:
1833 case Op_LoadI:
1834 case Op_LoadKlass:
1835 case Op_LoadNKlass:
1836 case Op_LoadL:
1837 case Op_LoadS:
1838 case Op_LoadP:
1839 case Op_LoadN:
1840 case Op_LoadRange:
1841 case Op_LoadD_unaligned:
1842 case Op_LoadL_unaligned:
1843 case Op_Load16B:
1844 case Op_Load8B:
1845 case Op_Load4B:
1846 case Op_Load4C:
1847 case Op_Load2C:
1848 case Op_Load8C:
1849 case Op_Load8S:
1850 case Op_Load4S:
1851 case Op_Load2S:
1852 case Op_Load4I:
1853 case Op_Load2I:
1854 case Op_Load2L:
1855 case Op_Load4F:
1856 case Op_Load2F:
1857 case Op_Load2D:
1858 mem_op = true;
1859 // Must be root of match tree due to prior load conflict
1860 if( C->subsume_loads() == false ) {
1861 set_shared(n);
1862 }
1863 // Fall into default case
1864 default:
1865 if( !n->ideal_reg() )
1866 set_dontcare(n); // Unmatchable Nodes
1867 } // end_switch
1868
1869 for(int i = n->req() - 1; i >= 0; --i) { // For my children
1870 Node *m = n->in(i); // Get ith input
1871 if (m == NULL) continue; // Ignore NULLs
1872 uint mop = m->Opcode();
1873
1874 // Must clone all producers of flags, or we will not match correctly.
1875 // Suppose a compare setting int-flags is shared (e.g., a switch-tree)
1876 // then it will match into an ideal Op_RegFlags. Alas, the fp-flags
1877 // are also there, so we may match a float-branch to int-flags and
1878 // expect the allocator to haul the flags from the int-side to the
1879 // fp-side. No can do.
1880 if( _must_clone[mop] ) {
1881 mstack.push(m, Visit);
1882 continue; // for(int i = ...)
1883 }
1884
1885 // Clone addressing expressions as they are "free" in most instructions
1886 if( mem_op && i == MemNode::Address && mop == Op_AddP ) {
1887 if (m->in(AddPNode::Base)->Opcode() == Op_DecodeN) {
1888 // Bases used in addresses must be shared but since
1889 // they are shared through a DecodeN they may appear
1890 // to have a single use so force sharing here.
1891 set_shared(m->in(AddPNode::Base)->in(1));
1892 }
1893 Node *off = m->in(AddPNode::Offset);
1894 if( off->is_Con() ) {
1895 set_visited(m); // Flag as visited now
1896 Node *adr = m->in(AddPNode::Address);
1897
1898 // Intel, ARM and friends can handle 2 adds in addressing mode
1899 if( clone_shift_expressions && adr->is_AddP() &&
1900 // AtomicAdd is not an addressing expression.
1901 // Cheap to find it by looking for screwy base.
1902 !adr->in(AddPNode::Base)->is_top() ) {
1903 set_visited(adr); // Flag as visited now
1904 Node *shift = adr->in(AddPNode::Offset);
1905 // Check for shift by small constant as well
1906 if( shift->Opcode() == Op_LShiftX && shift->in(2)->is_Con() &&
1907 shift->in(2)->get_int() <= 3 ) {
1908 set_visited(shift); // Flag as visited now
1909 mstack.push(shift->in(2), Visit);
1910 #ifdef _LP64
1911 // Allow Matcher to match the rule which bypass
1912 // ConvI2L operation for an array index on LP64
1913 // if the index value is positive.
1914 if( shift->in(1)->Opcode() == Op_ConvI2L &&
1915 shift->in(1)->as_Type()->type()->is_long()->_lo >= 0 ) {
1916 set_visited(shift->in(1)); // Flag as visited now
1917 mstack.push(shift->in(1)->in(1), Pre_Visit);
1918 } else
1919 #endif
1920 mstack.push(shift->in(1), Pre_Visit);
1921 } else {
1922 mstack.push(shift, Pre_Visit);
1923 }
1924 mstack.push(adr->in(AddPNode::Address), Pre_Visit);
1925 mstack.push(adr->in(AddPNode::Base), Pre_Visit);
1926 } else { // Sparc, Alpha, PPC and friends
1927 mstack.push(adr, Pre_Visit);
1928 }
1929
1930 // Clone X+offset as it also folds into most addressing expressions
1931 mstack.push(off, Visit);
1932 mstack.push(m->in(AddPNode::Base), Pre_Visit);
1933 continue; // for(int i = ...)
1934 } // if( off->is_Con() )
1935 } // if( mem_op &&
1936 mstack.push(m, Pre_Visit);
1937 } // for(int i = ...)
1938 }
1939 else if (nstate == Alt_Post_Visit) {
1940 mstack.pop(); // Remove node from stack
1941 // We cannot remove the Cmp input from the Bool here, as the Bool may be
1942 // shared and all users of the Bool need to move the Cmp in parallel.
1943 // This leaves both the Bool and the If pointing at the Cmp. To
1944 // prevent the Matcher from trying to Match the Cmp along both paths
1945 // BoolNode::match_edge always returns a zero.
1946
1947 // We reorder the Op_If in a pre-order manner, so we can visit without
1948 // accidently sharing the Cmp (the Bool and the If make 2 users).
1949 n->add_req( n->in(1)->in(1) ); // Add the Cmp next to the Bool
1950 }
1951 else if (nstate == Post_Visit) {
1952 mstack.pop(); // Remove node from stack
1953
1954 // Now hack a few special opcodes
1955 switch( n->Opcode() ) { // Handle some opcodes special
1956 case Op_StorePConditional:
1957 case Op_StoreIConditional:
1958 case Op_StoreLConditional:
1959 case Op_CompareAndSwapI:
1960 case Op_CompareAndSwapL:
1961 case Op_CompareAndSwapP:
1962 case Op_CompareAndSwapN: { // Convert trinary to binary-tree
1963 Node *newval = n->in(MemNode::ValueIn );
1964 Node *oldval = n->in(LoadStoreNode::ExpectedIn);
1965 Node *pair = new (C, 3) BinaryNode( oldval, newval );
1966 n->set_req(MemNode::ValueIn,pair);
1967 n->del_req(LoadStoreNode::ExpectedIn);
1968 break;
1969 }
1970 case Op_CMoveD: // Convert trinary to binary-tree
1971 case Op_CMoveF:
1972 case Op_CMoveI:
1973 case Op_CMoveL:
1974 case Op_CMoveN:
1975 case Op_CMoveP: {
1976 // Restructure into a binary tree for Matching. It's possible that
1977 // we could move this code up next to the graph reshaping for IfNodes
1978 // or vice-versa, but I do not want to debug this for Ladybird.
1979 // 10/2/2000 CNC.
1980 Node *pair1 = new (C, 3) BinaryNode(n->in(1),n->in(1)->in(1));
1981 n->set_req(1,pair1);
1982 Node *pair2 = new (C, 3) BinaryNode(n->in(2),n->in(3));
1983 n->set_req(2,pair2);
1984 n->del_req(3);
1985 break;
1986 }
1987 default:
1988 break;
1989 }
1990 }
1991 else {
1992 ShouldNotReachHere();
1993 }
1994 } // end of while (mstack.is_nonempty())
1995 }
1996
1997 #ifdef ASSERT
1998 // machine-independent root to machine-dependent root
1999 void Matcher::dump_old2new_map() {
2000 _old2new_map.dump();
2001 }
2002 #endif
2003
2004 //---------------------------collect_null_checks-------------------------------
2005 // Find null checks in the ideal graph; write a machine-specific node for
2006 // it. Used by later implicit-null-check handling. Actually collects
2007 // either an IfTrue or IfFalse for the common NOT-null path, AND the ideal
2008 // value being tested.
2009 void Matcher::collect_null_checks( Node *proj, Node *orig_proj ) {
2010 Node *iff = proj->in(0);
2011 if( iff->Opcode() == Op_If ) {
2012 // During matching If's have Bool & Cmp side-by-side
2013 BoolNode *b = iff->in(1)->as_Bool();
2014 Node *cmp = iff->in(2);
2015 int opc = cmp->Opcode();
2016 if (opc != Op_CmpP && opc != Op_CmpN) return;
2017
2018 const Type* ct = cmp->in(2)->bottom_type();
2019 if (ct == TypePtr::NULL_PTR ||
2020 (opc == Op_CmpN && ct == TypeNarrowOop::NULL_PTR)) {
2021
2022 bool push_it = false;
2023 if( proj->Opcode() == Op_IfTrue ) {
2024 extern int all_null_checks_found;
2025 all_null_checks_found++;
2026 if( b->_test._test == BoolTest::ne ) {
2027 push_it = true;
2028 }
2029 } else {
2030 assert( proj->Opcode() == Op_IfFalse, "" );
2031 if( b->_test._test == BoolTest::eq ) {
2032 push_it = true;
2033 }
2034 }
2035 if( push_it ) {
2036 _null_check_tests.push(proj);
2037 Node* val = cmp->in(1);
2038 #ifdef _LP64
2039 if (UseCompressedOops && !Matcher::clone_shift_expressions &&
2040 val->bottom_type()->isa_narrowoop()) {
2041 //
2042 // Look for DecodeN node which should be pinned to orig_proj.
2043 // On platforms (Sparc) which can not handle 2 adds
2044 // in addressing mode we have to keep a DecodeN node and
2045 // use it to do implicit NULL check in address.
2046 //
2047 // DecodeN node was pinned to non-null path (orig_proj) during
2048 // CastPP transformation in final_graph_reshaping_impl().
2049 //
2050 uint cnt = orig_proj->outcnt();
2051 for (uint i = 0; i < orig_proj->outcnt(); i++) {
2052 Node* d = orig_proj->raw_out(i);
2053 if (d->is_DecodeN() && d->in(1) == val) {
2054 val = d;
2055 val->set_req(0, NULL); // Unpin now.
2056 break;
2057 }
2058 }
2059 }
2060 #endif
2061 _null_check_tests.push(val);
2062 }
2063 }
2064 }
2065 }
2066
2067 //---------------------------validate_null_checks------------------------------
2068 // Its possible that the value being NULL checked is not the root of a match
2069 // tree. If so, I cannot use the value in an implicit null check.
2070 void Matcher::validate_null_checks( ) {
2071 uint cnt = _null_check_tests.size();
2072 for( uint i=0; i < cnt; i+=2 ) {
2073 Node *test = _null_check_tests[i];
2074 Node *val = _null_check_tests[i+1];
2075 if (has_new_node(val)) {
2076 // Is a match-tree root, so replace with the matched value
2077 _null_check_tests.map(i+1, new_node(val));
2078 } else {
2079 // Yank from candidate list
2080 _null_check_tests.map(i+1,_null_check_tests[--cnt]);
2081 _null_check_tests.map(i,_null_check_tests[--cnt]);
2082 _null_check_tests.pop();
2083 _null_check_tests.pop();
2084 i-=2;
2085 }
2086 }
2087 }
2088
2089
2090 // Used by the DFA in dfa_sparc.cpp. Check for a prior FastLock
2091 // acting as an Acquire and thus we don't need an Acquire here. We
2092 // retain the Node to act as a compiler ordering barrier.
2093 bool Matcher::prior_fast_lock( const Node *acq ) {
2094 Node *r = acq->in(0);
2095 if( !r->is_Region() || r->req() <= 1 ) return false;
2096 Node *proj = r->in(1);
2097 if( !proj->is_Proj() ) return false;
2098 Node *call = proj->in(0);
2099 if( !call->is_Call() || call->as_Call()->entry_point() != OptoRuntime::complete_monitor_locking_Java() )
2100 return false;
2101
2102 return true;
2103 }
2104
2105 // Used by the DFA in dfa_sparc.cpp. Check for a following FastUnLock
2106 // acting as a Release and thus we don't need a Release here. We
2107 // retain the Node to act as a compiler ordering barrier.
2108 bool Matcher::post_fast_unlock( const Node *rel ) {
2109 Compile *C = Compile::current();
2110 assert( rel->Opcode() == Op_MemBarRelease, "" );
2111 const MemBarReleaseNode *mem = (const MemBarReleaseNode*)rel;
2112 DUIterator_Fast imax, i = mem->fast_outs(imax);
2113 Node *ctrl = NULL;
2114 while( true ) {
2115 ctrl = mem->fast_out(i); // Throw out-of-bounds if proj not found
2116 assert( ctrl->is_Proj(), "only projections here" );
2117 ProjNode *proj = (ProjNode*)ctrl;
2118 if( proj->_con == TypeFunc::Control &&
2119 !C->node_arena()->contains(ctrl) ) // Unmatched old-space only
2120 break;
2121 i++;
2122 }
2123 Node *iff = NULL;
2124 for( DUIterator_Fast jmax, j = ctrl->fast_outs(jmax); j < jmax; j++ ) {
2125 Node *x = ctrl->fast_out(j);
2126 if( x->is_If() && x->req() > 1 &&
2127 !C->node_arena()->contains(x) ) { // Unmatched old-space only
2128 iff = x;
2129 break;
2130 }
2131 }
2132 if( !iff ) return false;
2133 Node *bol = iff->in(1);
2134 // The iff might be some random subclass of If or bol might be Con-Top
2135 if (!bol->is_Bool()) return false;
2136 assert( bol->req() > 1, "" );
2137 return (bol->in(1)->Opcode() == Op_FastUnlock);
2138 }
2139
2140 // Used by the DFA in dfa_xxx.cpp. Check for a following barrier or
2141 // atomic instruction acting as a store_load barrier without any
2142 // intervening volatile load, and thus we don't need a barrier here.
2143 // We retain the Node to act as a compiler ordering barrier.
2144 bool Matcher::post_store_load_barrier(const Node *vmb) {
2145 Compile *C = Compile::current();
2146 assert( vmb->is_MemBar(), "" );
2147 assert( vmb->Opcode() != Op_MemBarAcquire, "" );
2148 const MemBarNode *mem = (const MemBarNode*)vmb;
2149
2150 // Get the Proj node, ctrl, that can be used to iterate forward
2151 Node *ctrl = NULL;
2152 DUIterator_Fast imax, i = mem->fast_outs(imax);
2153 while( true ) {
2154 ctrl = mem->fast_out(i); // Throw out-of-bounds if proj not found
2155 assert( ctrl->is_Proj(), "only projections here" );
2156 ProjNode *proj = (ProjNode*)ctrl;
2157 if( proj->_con == TypeFunc::Control &&
2158 !C->node_arena()->contains(ctrl) ) // Unmatched old-space only
2159 break;
2160 i++;
2161 }
2162
2163 for( DUIterator_Fast jmax, j = ctrl->fast_outs(jmax); j < jmax; j++ ) {
2164 Node *x = ctrl->fast_out(j);
2165 int xop = x->Opcode();
2166
2167 // We don't need current barrier if we see another or a lock
2168 // before seeing volatile load.
2169 //
2170 // Op_Fastunlock previously appeared in the Op_* list below.
2171 // With the advent of 1-0 lock operations we're no longer guaranteed
2172 // that a monitor exit operation contains a serializing instruction.
2173
2174 if (xop == Op_MemBarVolatile ||
2175 xop == Op_FastLock ||
2176 xop == Op_CompareAndSwapL ||
2177 xop == Op_CompareAndSwapP ||
2178 xop == Op_CompareAndSwapN ||
2179 xop == Op_CompareAndSwapI)
2180 return true;
2181
2182 if (x->is_MemBar()) {
2183 // We must retain this membar if there is an upcoming volatile
2184 // load, which will be preceded by acquire membar.
2185 if (xop == Op_MemBarAcquire)
2186 return false;
2187 // For other kinds of barriers, check by pretending we
2188 // are them, and seeing if we can be removed.
2189 else
2190 return post_store_load_barrier((const MemBarNode*)x);
2191 }
2192
2193 // Delicate code to detect case of an upcoming fastlock block
2194 if( x->is_If() && x->req() > 1 &&
2195 !C->node_arena()->contains(x) ) { // Unmatched old-space only
2196 Node *iff = x;
2197 Node *bol = iff->in(1);
2198 // The iff might be some random subclass of If or bol might be Con-Top
2199 if (!bol->is_Bool()) return false;
2200 assert( bol->req() > 1, "" );
2201 return (bol->in(1)->Opcode() == Op_FastUnlock);
2202 }
2203 // probably not necessary to check for these
2204 if (x->is_Call() || x->is_SafePoint() || x->is_block_proj())
2205 return false;
2206 }
2207 return false;
2208 }
2209
2210 //=============================================================================
2211 //---------------------------State---------------------------------------------
2212 State::State(void) {
2213 #ifdef ASSERT
2214 _id = 0;
2215 _kids[0] = _kids[1] = (State*)(intptr_t) CONST64(0xcafebabecafebabe);
2216 _leaf = (Node*)(intptr_t) CONST64(0xbaadf00dbaadf00d);
2217 //memset(_cost, -1, sizeof(_cost));
2218 //memset(_rule, -1, sizeof(_rule));
2219 #endif
2220 memset(_valid, 0, sizeof(_valid));
2221 }
2222
2223 #ifdef ASSERT
2224 State::~State() {
2225 _id = 99;
2226 _kids[0] = _kids[1] = (State*)(intptr_t) CONST64(0xcafebabecafebabe);
2227 _leaf = (Node*)(intptr_t) CONST64(0xbaadf00dbaadf00d);
2228 memset(_cost, -3, sizeof(_cost));
2229 memset(_rule, -3, sizeof(_rule));
2230 }
2231 #endif
2232
2233 #ifndef PRODUCT
2234 //---------------------------dump----------------------------------------------
2235 void State::dump() {
2236 tty->print("\n");
2237 dump(0);
2238 }
2239
2240 void State::dump(int depth) {
2241 for( int j = 0; j < depth; j++ )
2242 tty->print(" ");
2243 tty->print("--N: ");
2244 _leaf->dump();
2245 uint i;
2246 for( i = 0; i < _LAST_MACH_OPER; i++ )
2247 // Check for valid entry
2248 if( valid(i) ) {
2249 for( int j = 0; j < depth; j++ )
2250 tty->print(" ");
2251 assert(_cost[i] != max_juint, "cost must be a valid value");
2252 assert(_rule[i] < _last_Mach_Node, "rule[i] must be valid rule");
2253 tty->print_cr("%s %d %s",
2254 ruleName[i], _cost[i], ruleName[_rule[i]] );
2255 }
2256 tty->print_cr("");
2257
2258 for( i=0; i<2; i++ )
2259 if( _kids[i] )
2260 _kids[i]->dump(depth+1);
2261 }
2262 #endif
2263