1 #ifdef USE_PRAGMA_IDENT_HDR
2 #pragma ident "@(#)matcher.hpp 1.188 07/07/19 19:08:27 JVM"
3 #endif
4 /*
5 * Copyright 1997-2007 Sun Microsystems, Inc. All Rights Reserved.
6 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
7 *
8 * This code is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License version 2 only, as
10 * published by the Free Software Foundation.
11 *
12 * This code is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15 * version 2 for more details (a copy is included in the LICENSE file that
16 * accompanied this code).
17 *
18 * You should have received a copy of the GNU General Public License version
19 * 2 along with this work; if not, write to the Free Software Foundation,
20 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
21 *
22 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
23 * CA 95054 USA or visit www.sun.com if you need additional information or
24 * have any questions.
25 *
34 //---------------------------Matcher-------------------------------------------
35 class Matcher : public PhaseTransform {
36 friend class VMStructs;
37 // Private arena of State objects
38 ResourceArea _states_arena;
39
40 VectorSet _visited; // Visit bits
41
42 // Used to control the Label pass
43 VectorSet _shared; // Shared Ideal Node
44 VectorSet _dontcare; // Nothing the matcher cares about
45
46 // Private methods which perform the actual matching and reduction
47 // Walks the label tree, generating machine nodes
48 MachNode *ReduceInst( State *s, int rule, Node *&mem);
49 void ReduceInst_Chain_Rule( State *s, int rule, Node *&mem, MachNode *mach);
50 uint ReduceInst_Interior(State *s, int rule, Node *&mem, MachNode *mach, uint num_opnds);
51 void ReduceOper( State *s, int newrule, Node *&mem, MachNode *mach );
52
53 // If this node already matched using "rule", return the MachNode for it.
54 MachNode* find_shared_constant(Node* con, uint rule);
55
56 // Convert a dense opcode number to an expanded rule number
57 const int *_reduceOp;
58 const int *_leftOp;
59 const int *_rightOp;
60
61 // Map dense opcode number to info on when rule is swallowed constant.
62 const bool *_swallowed;
63
64 // Map dense rule number to determine if this is an instruction chain rule
65 const uint _begin_inst_chain_rule;
66 const uint _end_inst_chain_rule;
67
68 // We want to clone constants and possible CmpI-variants.
69 // If we do not clone CmpI, then we can have many instances of
70 // condition codes alive at once. This is OK on some chips and
71 // bad on others. Hence the machine-dependent table lookup.
72 const char *_must_clone;
73
74 // Find shared Nodes, or Nodes that otherwise are Matcher roots
75 void find_shared( Node *n );
76
77 // Debug and profile information for nodes in old space:
78 GrowableArray<Node_Notes*>* _old_node_note_array;
79
80 // Node labeling iterator for instruction selection
81 Node *Label_Root( const Node *n, State *svec, Node *control, const Node *mem );
82
83 Node *transform( Node *dummy );
84
85 Node_List &_proj_list; // For Machine nodes killing many values
86
87 Node_Array _shared_constants;
88
89 debug_only(Node_Array _old2new_map;) // Map roots of ideal-trees to machine-roots
90
91 // Accessors for the inherited field PhaseTransform::_nodes:
92 void grow_new_node_array(uint idx_limit) {
93 _nodes.map(idx_limit-1, NULL);
94 }
95 bool has_new_node(const Node* n) const {
96 return _nodes.at(n->_idx) != NULL;
97 }
98 Node* new_node(const Node* n) const {
99 assert(has_new_node(n), "set before get");
100 return _nodes.at(n->_idx);
101 }
102 void set_new_node(const Node* n, Node *nn) {
103 assert(!has_new_node(n), "set only once");
104 _nodes.map(n->_idx, nn);
105 }
106
107 #ifdef ASSERT
108 // Make sure only new nodes are reachable from this node
109 void verify_new_nodes_only(Node* root);
110 #endif
111
112 public:
113 int LabelRootDepth;
114 static const int base2reg[]; // Map Types to machine register types
115 // Convert ideal machine register to a register mask for spill-loads
116 static const RegMask *idealreg2regmask[];
117 RegMask *idealreg2spillmask[_last_machine_leaf];
118 RegMask *idealreg2debugmask[_last_machine_leaf];
119 void init_spill_mask( Node *ret );
120 // Convert machine register number to register mask
121 static uint mreg2regmask_max;
122 static RegMask mreg2regmask[];
123 static RegMask STACK_ONLY_mask;
124
125 bool is_shared( Node *n ) { return _shared.test(n->_idx) != 0; }
126 void set_shared( Node *n ) { _shared.set(n->_idx); }
127 bool is_visited( Node *n ) { return _visited.test(n->_idx) != 0; }
128 void set_visited( Node *n ) { _visited.set(n->_idx); }
129 bool is_dontcare( Node *n ) { return _dontcare.test(n->_idx) != 0; }
149 // An array of chars, from 0 to _last_Mach_Reg.
150 // No Save = 'N' (for register windows)
151 // Save on Entry = 'E'
152 // Save on Call = 'C'
153 // Always Save = 'A' (same as SOE + SOC)
154 const char *_register_save_policy;
155 const char *_c_reg_save_policy;
156 // Convert a machine register to a machine register type, so-as to
157 // properly match spill code.
158 const int *_register_save_type;
159 // Maps from machine register to boolean; true if machine register can
160 // be holding a call argument in some signature.
161 static bool can_be_java_arg( int reg );
162 // Maps from machine register to boolean; true if machine register holds
163 // a spillable argument.
164 static bool is_spillable_arg( int reg );
165
166 // List of IfFalse or IfTrue Nodes that indicate a taken null test.
167 // List is valid in the post-matching space.
168 Node_List _null_check_tests;
169 void collect_null_checks( Node *proj );
170 void validate_null_checks( );
171
172 Matcher( Node_List &proj_list );
173
174 // Select instructions for entire method
175 void match( );
176 // Helper for match
177 OptoReg::Name warp_incoming_stk_arg( VMReg reg );
178
179 // Transform, then walk. Does implicit DCE while walking.
180 // Name changed from "transform" to avoid it being virtual.
181 Node *xform( Node *old_space_node, int Nodes );
182
183 // Match a single Ideal Node - turn it into a 1-Node tree; Label & Reduce.
184 MachNode *match_tree( const Node *n );
185 MachNode *match_sfpt( SafePointNode *sfpt );
186 // Helper for match_sfpt
187 OptoReg::Name warp_outgoing_stk_arg( VMReg reg, OptoReg::Name begin_out_arg_area, OptoReg::Name &out_arg_limit_per_call );
188
189 // Initialize first stack mask and related masks.
307 // Interpreter's Frame Pointer Register
308 static OptoReg::Name interpreter_frame_pointer_reg();
309 static const RegMask &interpreter_frame_pointer_reg_mask();
310
311 // Java-Native calling convention
312 // (what you use when intercalling between Java and C++ code)
313
314 // Array mapping arguments to registers. Argument 0 is usually the 'this'
315 // pointer. Registers can include stack-slots and regular registers.
316 static void c_calling_convention( BasicType*, VMRegPair *, uint );
317 // Frame pointer. The frame pointer is kept at the base of the stack
318 // and so is probably the stack pointer for most machines. On Intel
319 // it is ESP. On the PowerPC it is R1. On Sparc it is SP.
320 OptoReg::Name c_frame_pointer() const;
321 static RegMask c_frame_ptr_mask;
322
323 // !!!!! Special stuff for building ScopeDescs
324 virtual int regnum_to_fpu_offset(int regnum);
325
326 // Is this branch offset small enough to be addressed by a short branch?
327 bool is_short_branch_offset(int offset);
328
329 // Optional scaling for the parameter to the ClearArray/CopyArray node.
330 static const bool init_array_count_is_in_bytes;
331
332 // Threshold small size (in bytes) for a ClearArray/CopyArray node.
333 // Anything this size or smaller may get converted to discrete scalar stores.
334 static const int init_array_short_size;
335
336 // Should the Matcher clone shifts on addressing modes, expecting them to
337 // be subsumed into complex addressing expressions or compute them into
338 // registers? True for Intel but false for most RISCs
339 static const bool clone_shift_expressions;
340
341 // Is it better to copy float constants, or load them directly from memory?
342 // Intel can load a float constant from a direct address, requiring no
343 // extra registers. Most RISCs will have to materialize an address into a
344 // register first, so they may as well materialize the constant immediately.
345 static const bool rematerialize_float_constants;
346
347 // If CPU can load and store mis-aligned doubles directly then no fixup is
374 }
375
376 // Used by the DFA in dfa_sparc.cpp. Check for a prior FastLock
377 // acting as an Acquire and thus we don't need an Acquire here. We
378 // retain the Node to act as a compiler ordering barrier.
379 static bool prior_fast_lock( const Node *acq );
380
381 // Used by the DFA in dfa_sparc.cpp. Check for a following
382 // FastUnLock acting as a Release and thus we don't need a Release
383 // here. We retain the Node to act as a compiler ordering barrier.
384 static bool post_fast_unlock( const Node *rel );
385
386 // Check for a following volatile memory barrier without an
387 // intervening load and thus we don't need a barrier here. We
388 // retain the Node to act as a compiler ordering barrier.
389 static bool post_store_load_barrier(const Node* mb);
390
391
392 #ifdef ASSERT
393 void dump_old2new_map(); // machine-independent to machine-dependent
394 #endif
395 };
|
1 #ifdef USE_PRAGMA_IDENT_HDR
2 #pragma ident "@(#)matcher.hpp 1.188 07/07/19 19:08:27 JVM"
3 #endif
4 /*
5 * Copyright 1997-2008 Sun Microsystems, Inc. All Rights Reserved.
6 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
7 *
8 * This code is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License version 2 only, as
10 * published by the Free Software Foundation.
11 *
12 * This code is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15 * version 2 for more details (a copy is included in the LICENSE file that
16 * accompanied this code).
17 *
18 * You should have received a copy of the GNU General Public License version
19 * 2 along with this work; if not, write to the Free Software Foundation,
20 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
21 *
22 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
23 * CA 95054 USA or visit www.sun.com if you need additional information or
24 * have any questions.
25 *
34 //---------------------------Matcher-------------------------------------------
35 class Matcher : public PhaseTransform {
36 friend class VMStructs;
37 // Private arena of State objects
38 ResourceArea _states_arena;
39
40 VectorSet _visited; // Visit bits
41
42 // Used to control the Label pass
43 VectorSet _shared; // Shared Ideal Node
44 VectorSet _dontcare; // Nothing the matcher cares about
45
46 // Private methods which perform the actual matching and reduction
47 // Walks the label tree, generating machine nodes
48 MachNode *ReduceInst( State *s, int rule, Node *&mem);
49 void ReduceInst_Chain_Rule( State *s, int rule, Node *&mem, MachNode *mach);
50 uint ReduceInst_Interior(State *s, int rule, Node *&mem, MachNode *mach, uint num_opnds);
51 void ReduceOper( State *s, int newrule, Node *&mem, MachNode *mach );
52
53 // If this node already matched using "rule", return the MachNode for it.
54 MachNode* find_shared_node(Node* n, uint rule);
55
56 // Convert a dense opcode number to an expanded rule number
57 const int *_reduceOp;
58 const int *_leftOp;
59 const int *_rightOp;
60
61 // Map dense opcode number to info on when rule is swallowed constant.
62 const bool *_swallowed;
63
64 // Map dense rule number to determine if this is an instruction chain rule
65 const uint _begin_inst_chain_rule;
66 const uint _end_inst_chain_rule;
67
68 // We want to clone constants and possible CmpI-variants.
69 // If we do not clone CmpI, then we can have many instances of
70 // condition codes alive at once. This is OK on some chips and
71 // bad on others. Hence the machine-dependent table lookup.
72 const char *_must_clone;
73
74 // Find shared Nodes, or Nodes that otherwise are Matcher roots
75 void find_shared( Node *n );
76
77 // Debug and profile information for nodes in old space:
78 GrowableArray<Node_Notes*>* _old_node_note_array;
79
80 // Node labeling iterator for instruction selection
81 Node *Label_Root( const Node *n, State *svec, Node *control, const Node *mem );
82
83 Node *transform( Node *dummy );
84
85 Node_List &_proj_list; // For Machine nodes killing many values
86
87 Node_Array _shared_nodes;
88
89 debug_only(Node_Array _old2new_map;) // Map roots of ideal-trees to machine-roots
90 debug_only(Node_Array _new2old_map;) // Maps machine nodes back to ideal
91
92 // Accessors for the inherited field PhaseTransform::_nodes:
93 void grow_new_node_array(uint idx_limit) {
94 _nodes.map(idx_limit-1, NULL);
95 }
96 bool has_new_node(const Node* n) const {
97 return _nodes.at(n->_idx) != NULL;
98 }
99 Node* new_node(const Node* n) const {
100 assert(has_new_node(n), "set before get");
101 return _nodes.at(n->_idx);
102 }
103 void set_new_node(const Node* n, Node *nn) {
104 assert(!has_new_node(n), "set only once");
105 _nodes.map(n->_idx, nn);
106 }
107
108 #ifdef ASSERT
109 // Make sure only new nodes are reachable from this node
110 void verify_new_nodes_only(Node* root);
111
112 Node* _mem_node; // Ideal memory node consumed by mach node
113 #endif
114
115 public:
116 int LabelRootDepth;
117 static const int base2reg[]; // Map Types to machine register types
118 // Convert ideal machine register to a register mask for spill-loads
119 static const RegMask *idealreg2regmask[];
120 RegMask *idealreg2spillmask[_last_machine_leaf];
121 RegMask *idealreg2debugmask[_last_machine_leaf];
122 void init_spill_mask( Node *ret );
123 // Convert machine register number to register mask
124 static uint mreg2regmask_max;
125 static RegMask mreg2regmask[];
126 static RegMask STACK_ONLY_mask;
127
128 bool is_shared( Node *n ) { return _shared.test(n->_idx) != 0; }
129 void set_shared( Node *n ) { _shared.set(n->_idx); }
130 bool is_visited( Node *n ) { return _visited.test(n->_idx) != 0; }
131 void set_visited( Node *n ) { _visited.set(n->_idx); }
132 bool is_dontcare( Node *n ) { return _dontcare.test(n->_idx) != 0; }
152 // An array of chars, from 0 to _last_Mach_Reg.
153 // No Save = 'N' (for register windows)
154 // Save on Entry = 'E'
155 // Save on Call = 'C'
156 // Always Save = 'A' (same as SOE + SOC)
157 const char *_register_save_policy;
158 const char *_c_reg_save_policy;
159 // Convert a machine register to a machine register type, so-as to
160 // properly match spill code.
161 const int *_register_save_type;
162 // Maps from machine register to boolean; true if machine register can
163 // be holding a call argument in some signature.
164 static bool can_be_java_arg( int reg );
165 // Maps from machine register to boolean; true if machine register holds
166 // a spillable argument.
167 static bool is_spillable_arg( int reg );
168
169 // List of IfFalse or IfTrue Nodes that indicate a taken null test.
170 // List is valid in the post-matching space.
171 Node_List _null_check_tests;
172 void collect_null_checks( Node *proj, Node *orig_proj );
173 void validate_null_checks( );
174
175 Matcher( Node_List &proj_list );
176
177 // Select instructions for entire method
178 void match( );
179 // Helper for match
180 OptoReg::Name warp_incoming_stk_arg( VMReg reg );
181
182 // Transform, then walk. Does implicit DCE while walking.
183 // Name changed from "transform" to avoid it being virtual.
184 Node *xform( Node *old_space_node, int Nodes );
185
186 // Match a single Ideal Node - turn it into a 1-Node tree; Label & Reduce.
187 MachNode *match_tree( const Node *n );
188 MachNode *match_sfpt( SafePointNode *sfpt );
189 // Helper for match_sfpt
190 OptoReg::Name warp_outgoing_stk_arg( VMReg reg, OptoReg::Name begin_out_arg_area, OptoReg::Name &out_arg_limit_per_call );
191
192 // Initialize first stack mask and related masks.
310 // Interpreter's Frame Pointer Register
311 static OptoReg::Name interpreter_frame_pointer_reg();
312 static const RegMask &interpreter_frame_pointer_reg_mask();
313
314 // Java-Native calling convention
315 // (what you use when intercalling between Java and C++ code)
316
317 // Array mapping arguments to registers. Argument 0 is usually the 'this'
318 // pointer. Registers can include stack-slots and regular registers.
319 static void c_calling_convention( BasicType*, VMRegPair *, uint );
320 // Frame pointer. The frame pointer is kept at the base of the stack
321 // and so is probably the stack pointer for most machines. On Intel
322 // it is ESP. On the PowerPC it is R1. On Sparc it is SP.
323 OptoReg::Name c_frame_pointer() const;
324 static RegMask c_frame_ptr_mask;
325
326 // !!!!! Special stuff for building ScopeDescs
327 virtual int regnum_to_fpu_offset(int regnum);
328
329 // Is this branch offset small enough to be addressed by a short branch?
330 bool is_short_branch_offset(int rule, int offset);
331
332 // Optional scaling for the parameter to the ClearArray/CopyArray node.
333 static const bool init_array_count_is_in_bytes;
334
335 // Threshold small size (in bytes) for a ClearArray/CopyArray node.
336 // Anything this size or smaller may get converted to discrete scalar stores.
337 static const int init_array_short_size;
338
339 // Should the Matcher clone shifts on addressing modes, expecting them to
340 // be subsumed into complex addressing expressions or compute them into
341 // registers? True for Intel but false for most RISCs
342 static const bool clone_shift_expressions;
343
344 // Is it better to copy float constants, or load them directly from memory?
345 // Intel can load a float constant from a direct address, requiring no
346 // extra registers. Most RISCs will have to materialize an address into a
347 // register first, so they may as well materialize the constant immediately.
348 static const bool rematerialize_float_constants;
349
350 // If CPU can load and store mis-aligned doubles directly then no fixup is
377 }
378
379 // Used by the DFA in dfa_sparc.cpp. Check for a prior FastLock
380 // acting as an Acquire and thus we don't need an Acquire here. We
381 // retain the Node to act as a compiler ordering barrier.
382 static bool prior_fast_lock( const Node *acq );
383
384 // Used by the DFA in dfa_sparc.cpp. Check for a following
385 // FastUnLock acting as a Release and thus we don't need a Release
386 // here. We retain the Node to act as a compiler ordering barrier.
387 static bool post_fast_unlock( const Node *rel );
388
389 // Check for a following volatile memory barrier without an
390 // intervening load and thus we don't need a barrier here. We
391 // retain the Node to act as a compiler ordering barrier.
392 static bool post_store_load_barrier(const Node* mb);
393
394
395 #ifdef ASSERT
396 void dump_old2new_map(); // machine-independent to machine-dependent
397
398 Node* find_old_node(Node* new_node) {
399 return _new2old_map[new_node->_idx];
400 }
401 #endif
402 };
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