1 /* 2 * Copyright (c) 2000, 2012, Oracle and/or its affiliates. All rights reserved. 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 4 * 5 * This code is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 only, as 7 * published by the Free Software Foundation. 8 * 9 * This code is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * version 2 for more details (a copy is included in the LICENSE file that 13 * accompanied this code). 14 * 15 * You should have received a copy of the GNU General Public License version 16 * 2 along with this work; if not, write to the Free Software Foundation, 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 18 * 19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 20 * or visit www.oracle.com if you need additional information or have any 21 * questions. 22 * 23 */ 24 25 #include "precompiled.hpp" 26 #include "asm/assembler.hpp" 27 #include "c1/c1_Compilation.hpp" 28 #include "c1/c1_LIRAssembler.hpp" 29 #include "c1/c1_MacroAssembler.hpp" 30 #include "c1/c1_Runtime1.hpp" 31 #include "c1/c1_ValueStack.hpp" 32 #include "ci/ciArrayKlass.hpp" 33 #include "ci/ciInstance.hpp" 34 #include "gc_interface/collectedHeap.hpp" 35 #include "memory/barrierSet.hpp" 36 #include "memory/cardTableModRefBS.hpp" 37 #include "nativeInst_x86.hpp" 38 #include "oops/objArrayKlass.hpp" 39 #include "runtime/sharedRuntime.hpp" 40 41 42 // These masks are used to provide 128-bit aligned bitmasks to the XMM 43 // instructions, to allow sign-masking or sign-bit flipping. They allow 44 // fast versions of NegF/NegD and AbsF/AbsD. 45 46 // Note: 'double' and 'long long' have 32-bits alignment on x86. 47 static jlong* double_quadword(jlong *adr, jlong lo, jlong hi) { 48 // Use the expression (adr)&(~0xF) to provide 128-bits aligned address 49 // of 128-bits operands for SSE instructions. 50 jlong *operand = (jlong*)(((intptr_t)adr) & ((intptr_t)(~0xF))); 51 // Store the value to a 128-bits operand. 52 operand[0] = lo; 53 operand[1] = hi; 54 return operand; 55 } 56 57 // Buffer for 128-bits masks used by SSE instructions. 58 static jlong fp_signmask_pool[(4+1)*2]; // 4*128bits(data) + 128bits(alignment) 59 60 // Static initialization during VM startup. 61 static jlong *float_signmask_pool = double_quadword(&fp_signmask_pool[1*2], CONST64(0x7FFFFFFF7FFFFFFF), CONST64(0x7FFFFFFF7FFFFFFF)); 62 static jlong *double_signmask_pool = double_quadword(&fp_signmask_pool[2*2], CONST64(0x7FFFFFFFFFFFFFFF), CONST64(0x7FFFFFFFFFFFFFFF)); 63 static jlong *float_signflip_pool = double_quadword(&fp_signmask_pool[3*2], CONST64(0x8000000080000000), CONST64(0x8000000080000000)); 64 static jlong *double_signflip_pool = double_quadword(&fp_signmask_pool[4*2], CONST64(0x8000000000000000), CONST64(0x8000000000000000)); 65 66 67 68 NEEDS_CLEANUP // remove this definitions ? 69 const Register IC_Klass = rax; // where the IC klass is cached 70 const Register SYNC_header = rax; // synchronization header 71 const Register SHIFT_count = rcx; // where count for shift operations must be 72 73 #define __ _masm-> 74 75 76 static void select_different_registers(Register preserve, 77 Register extra, 78 Register &tmp1, 79 Register &tmp2) { 80 if (tmp1 == preserve) { 81 assert_different_registers(tmp1, tmp2, extra); 82 tmp1 = extra; 83 } else if (tmp2 == preserve) { 84 assert_different_registers(tmp1, tmp2, extra); 85 tmp2 = extra; 86 } 87 assert_different_registers(preserve, tmp1, tmp2); 88 } 89 90 91 92 static void select_different_registers(Register preserve, 93 Register extra, 94 Register &tmp1, 95 Register &tmp2, 96 Register &tmp3) { 97 if (tmp1 == preserve) { 98 assert_different_registers(tmp1, tmp2, tmp3, extra); 99 tmp1 = extra; 100 } else if (tmp2 == preserve) { 101 assert_different_registers(tmp1, tmp2, tmp3, extra); 102 tmp2 = extra; 103 } else if (tmp3 == preserve) { 104 assert_different_registers(tmp1, tmp2, tmp3, extra); 105 tmp3 = extra; 106 } 107 assert_different_registers(preserve, tmp1, tmp2, tmp3); 108 } 109 110 111 112 bool LIR_Assembler::is_small_constant(LIR_Opr opr) { 113 if (opr->is_constant()) { 114 LIR_Const* constant = opr->as_constant_ptr(); 115 switch (constant->type()) { 116 case T_INT: { 117 return true; 118 } 119 120 default: 121 return false; 122 } 123 } 124 return false; 125 } 126 127 128 LIR_Opr LIR_Assembler::receiverOpr() { 129 return FrameMap::receiver_opr; 130 } 131 132 LIR_Opr LIR_Assembler::osrBufferPointer() { 133 return FrameMap::as_pointer_opr(receiverOpr()->as_register()); 134 } 135 136 //--------------fpu register translations----------------------- 137 138 139 address LIR_Assembler::float_constant(float f) { 140 address const_addr = __ float_constant(f); 141 if (const_addr == NULL) { 142 bailout("const section overflow"); 143 return __ code()->consts()->start(); 144 } else { 145 return const_addr; 146 } 147 } 148 149 150 address LIR_Assembler::double_constant(double d) { 151 address const_addr = __ double_constant(d); 152 if (const_addr == NULL) { 153 bailout("const section overflow"); 154 return __ code()->consts()->start(); 155 } else { 156 return const_addr; 157 } 158 } 159 160 161 void LIR_Assembler::set_24bit_FPU() { 162 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24())); 163 } 164 165 void LIR_Assembler::reset_FPU() { 166 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std())); 167 } 168 169 void LIR_Assembler::fpop() { 170 __ fpop(); 171 } 172 173 void LIR_Assembler::fxch(int i) { 174 __ fxch(i); 175 } 176 177 void LIR_Assembler::fld(int i) { 178 __ fld_s(i); 179 } 180 181 void LIR_Assembler::ffree(int i) { 182 __ ffree(i); 183 } 184 185 void LIR_Assembler::breakpoint() { 186 __ int3(); 187 } 188 189 void LIR_Assembler::push(LIR_Opr opr) { 190 if (opr->is_single_cpu()) { 191 __ push_reg(opr->as_register()); 192 } else if (opr->is_double_cpu()) { 193 NOT_LP64(__ push_reg(opr->as_register_hi())); 194 __ push_reg(opr->as_register_lo()); 195 } else if (opr->is_stack()) { 196 __ push_addr(frame_map()->address_for_slot(opr->single_stack_ix())); 197 } else if (opr->is_constant()) { 198 LIR_Const* const_opr = opr->as_constant_ptr(); 199 if (const_opr->type() == T_OBJECT) { 200 __ push_oop(const_opr->as_jobject()); 201 } else if (const_opr->type() == T_INT) { 202 __ push_jint(const_opr->as_jint()); 203 } else { 204 ShouldNotReachHere(); 205 } 206 207 } else { 208 ShouldNotReachHere(); 209 } 210 } 211 212 void LIR_Assembler::pop(LIR_Opr opr) { 213 if (opr->is_single_cpu()) { 214 __ pop_reg(opr->as_register()); 215 } else { 216 ShouldNotReachHere(); 217 } 218 } 219 220 bool LIR_Assembler::is_literal_address(LIR_Address* addr) { 221 return addr->base()->is_illegal() && addr->index()->is_illegal(); 222 } 223 224 //------------------------------------------- 225 226 Address LIR_Assembler::as_Address(LIR_Address* addr) { 227 return as_Address(addr, rscratch1); 228 } 229 230 Address LIR_Assembler::as_Address(LIR_Address* addr, Register tmp) { 231 if (addr->base()->is_illegal()) { 232 assert(addr->index()->is_illegal(), "must be illegal too"); 233 AddressLiteral laddr((address)addr->disp(), relocInfo::none); 234 if (! __ reachable(laddr)) { 235 __ movptr(tmp, laddr.addr()); 236 Address res(tmp, 0); 237 return res; 238 } else { 239 return __ as_Address(laddr); 240 } 241 } 242 243 Register base = addr->base()->as_pointer_register(); 244 245 if (addr->index()->is_illegal()) { 246 return Address( base, addr->disp()); 247 } else if (addr->index()->is_cpu_register()) { 248 Register index = addr->index()->as_pointer_register(); 249 return Address(base, index, (Address::ScaleFactor) addr->scale(), addr->disp()); 250 } else if (addr->index()->is_constant()) { 251 intptr_t addr_offset = (addr->index()->as_constant_ptr()->as_jint() << addr->scale()) + addr->disp(); 252 assert(Assembler::is_simm32(addr_offset), "must be"); 253 254 return Address(base, addr_offset); 255 } else { 256 Unimplemented(); 257 return Address(); 258 } 259 } 260 261 262 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) { 263 Address base = as_Address(addr); 264 return Address(base._base, base._index, base._scale, base._disp + BytesPerWord); 265 } 266 267 268 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) { 269 return as_Address(addr); 270 } 271 272 273 void LIR_Assembler::osr_entry() { 274 offsets()->set_value(CodeOffsets::OSR_Entry, code_offset()); 275 BlockBegin* osr_entry = compilation()->hir()->osr_entry(); 276 ValueStack* entry_state = osr_entry->state(); 277 int number_of_locks = entry_state->locks_size(); 278 279 // we jump here if osr happens with the interpreter 280 // state set up to continue at the beginning of the 281 // loop that triggered osr - in particular, we have 282 // the following registers setup: 283 // 284 // rcx: osr buffer 285 // 286 287 // build frame 288 ciMethod* m = compilation()->method(); 289 __ build_frame(initial_frame_size_in_bytes()); 290 291 // OSR buffer is 292 // 293 // locals[nlocals-1..0] 294 // monitors[0..number_of_locks] 295 // 296 // locals is a direct copy of the interpreter frame so in the osr buffer 297 // so first slot in the local array is the last local from the interpreter 298 // and last slot is local[0] (receiver) from the interpreter 299 // 300 // Similarly with locks. The first lock slot in the osr buffer is the nth lock 301 // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock 302 // in the interpreter frame (the method lock if a sync method) 303 304 // Initialize monitors in the compiled activation. 305 // rcx: pointer to osr buffer 306 // 307 // All other registers are dead at this point and the locals will be 308 // copied into place by code emitted in the IR. 309 310 Register OSR_buf = osrBufferPointer()->as_pointer_register(); 311 { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below"); 312 int monitor_offset = BytesPerWord * method()->max_locals() + 313 (2 * BytesPerWord) * (number_of_locks - 1); 314 // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in 315 // the OSR buffer using 2 word entries: first the lock and then 316 // the oop. 317 for (int i = 0; i < number_of_locks; i++) { 318 int slot_offset = monitor_offset - ((i * 2) * BytesPerWord); 319 #ifdef ASSERT 320 // verify the interpreter's monitor has a non-null object 321 { 322 Label L; 323 __ cmpptr(Address(OSR_buf, slot_offset + 1*BytesPerWord), (int32_t)NULL_WORD); 324 __ jcc(Assembler::notZero, L); 325 __ stop("locked object is NULL"); 326 __ bind(L); 327 } 328 #endif 329 __ movptr(rbx, Address(OSR_buf, slot_offset + 0)); 330 __ movptr(frame_map()->address_for_monitor_lock(i), rbx); 331 __ movptr(rbx, Address(OSR_buf, slot_offset + 1*BytesPerWord)); 332 __ movptr(frame_map()->address_for_monitor_object(i), rbx); 333 } 334 } 335 } 336 337 338 // inline cache check; done before the frame is built. 339 int LIR_Assembler::check_icache() { 340 Register receiver = FrameMap::receiver_opr->as_register(); 341 Register ic_klass = IC_Klass; 342 const int ic_cmp_size = LP64_ONLY(10) NOT_LP64(9); 343 const bool do_post_padding = VerifyOops || UseCompressedOops; 344 if (!do_post_padding) { 345 // insert some nops so that the verified entry point is aligned on CodeEntryAlignment 346 while ((__ offset() + ic_cmp_size) % CodeEntryAlignment != 0) { 347 __ nop(); 348 } 349 } 350 int offset = __ offset(); 351 __ inline_cache_check(receiver, IC_Klass); 352 assert(__ offset() % CodeEntryAlignment == 0 || do_post_padding, "alignment must be correct"); 353 if (do_post_padding) { 354 // force alignment after the cache check. 355 // It's been verified to be aligned if !VerifyOops 356 __ align(CodeEntryAlignment); 357 } 358 return offset; 359 } 360 361 362 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo* info) { 363 jobject o = NULL; 364 PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_klass_id); 365 __ movoop(reg, o); 366 patching_epilog(patch, lir_patch_normal, reg, info); 367 } 368 369 370 // This specifies the rsp decrement needed to build the frame 371 int LIR_Assembler::initial_frame_size_in_bytes() { 372 // if rounding, must let FrameMap know! 373 374 // The frame_map records size in slots (32bit word) 375 376 // subtract two words to account for return address and link 377 return (frame_map()->framesize() - (2*VMRegImpl::slots_per_word)) * VMRegImpl::stack_slot_size; 378 } 379 380 381 int LIR_Assembler::emit_exception_handler() { 382 // if the last instruction is a call (typically to do a throw which 383 // is coming at the end after block reordering) the return address 384 // must still point into the code area in order to avoid assertion 385 // failures when searching for the corresponding bci => add a nop 386 // (was bug 5/14/1999 - gri) 387 __ nop(); 388 389 // generate code for exception handler 390 address handler_base = __ start_a_stub(exception_handler_size); 391 if (handler_base == NULL) { 392 // not enough space left for the handler 393 bailout("exception handler overflow"); 394 return -1; 395 } 396 397 int offset = code_offset(); 398 399 // the exception oop and pc are in rax, and rdx 400 // no other registers need to be preserved, so invalidate them 401 __ invalidate_registers(false, true, true, false, true, true); 402 403 // check that there is really an exception 404 __ verify_not_null_oop(rax); 405 406 // search an exception handler (rax: exception oop, rdx: throwing pc) 407 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::handle_exception_from_callee_id))); 408 __ should_not_reach_here(); 409 guarantee(code_offset() - offset <= exception_handler_size, "overflow"); 410 __ end_a_stub(); 411 412 return offset; 413 } 414 415 416 // Emit the code to remove the frame from the stack in the exception 417 // unwind path. 418 int LIR_Assembler::emit_unwind_handler() { 419 #ifndef PRODUCT 420 if (CommentedAssembly) { 421 _masm->block_comment("Unwind handler"); 422 } 423 #endif 424 425 int offset = code_offset(); 426 427 // Fetch the exception from TLS and clear out exception related thread state 428 __ get_thread(rsi); 429 __ movptr(rax, Address(rsi, JavaThread::exception_oop_offset())); 430 __ movptr(Address(rsi, JavaThread::exception_oop_offset()), (intptr_t)NULL_WORD); 431 __ movptr(Address(rsi, JavaThread::exception_pc_offset()), (intptr_t)NULL_WORD); 432 433 __ bind(_unwind_handler_entry); 434 __ verify_not_null_oop(rax); 435 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) { 436 __ mov(rsi, rax); // Preserve the exception 437 } 438 439 // Preform needed unlocking 440 MonitorExitStub* stub = NULL; 441 if (method()->is_synchronized()) { 442 monitor_address(0, FrameMap::rax_opr); 443 stub = new MonitorExitStub(FrameMap::rax_opr, true, 0); 444 __ unlock_object(rdi, rbx, rax, *stub->entry()); 445 __ bind(*stub->continuation()); 446 } 447 448 if (compilation()->env()->dtrace_method_probes()) { 449 __ get_thread(rax); 450 __ movptr(Address(rsp, 0), rax); 451 __ movoop(Address(rsp, sizeof(void*)), method()->constant_encoding()); 452 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit))); 453 } 454 455 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) { 456 __ mov(rax, rsi); // Restore the exception 457 } 458 459 // remove the activation and dispatch to the unwind handler 460 __ remove_frame(initial_frame_size_in_bytes()); 461 __ jump(RuntimeAddress(Runtime1::entry_for(Runtime1::unwind_exception_id))); 462 463 // Emit the slow path assembly 464 if (stub != NULL) { 465 stub->emit_code(this); 466 } 467 468 return offset; 469 } 470 471 472 int LIR_Assembler::emit_deopt_handler() { 473 // if the last instruction is a call (typically to do a throw which 474 // is coming at the end after block reordering) the return address 475 // must still point into the code area in order to avoid assertion 476 // failures when searching for the corresponding bci => add a nop 477 // (was bug 5/14/1999 - gri) 478 __ nop(); 479 480 // generate code for exception handler 481 address handler_base = __ start_a_stub(deopt_handler_size); 482 if (handler_base == NULL) { 483 // not enough space left for the handler 484 bailout("deopt handler overflow"); 485 return -1; 486 } 487 488 int offset = code_offset(); 489 InternalAddress here(__ pc()); 490 491 __ pushptr(here.addr()); 492 __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack())); 493 guarantee(code_offset() - offset <= deopt_handler_size, "overflow"); 494 __ end_a_stub(); 495 496 return offset; 497 } 498 499 500 // This is the fast version of java.lang.String.compare; it has not 501 // OSR-entry and therefore, we generate a slow version for OSR's 502 void LIR_Assembler::emit_string_compare(LIR_Opr arg0, LIR_Opr arg1, LIR_Opr dst, CodeEmitInfo* info) { 503 __ movptr (rbx, rcx); // receiver is in rcx 504 __ movptr (rax, arg1->as_register()); 505 506 // Get addresses of first characters from both Strings 507 __ load_heap_oop(rsi, Address(rax, java_lang_String::value_offset_in_bytes())); 508 if (java_lang_String::has_offset_field()) { 509 __ movptr (rcx, Address(rax, java_lang_String::offset_offset_in_bytes())); 510 __ movl (rax, Address(rax, java_lang_String::count_offset_in_bytes())); 511 __ lea (rsi, Address(rsi, rcx, Address::times_2, arrayOopDesc::base_offset_in_bytes(T_CHAR))); 512 } else { 513 __ movl (rax, Address(rsi, arrayOopDesc::length_offset_in_bytes())); 514 __ lea (rsi, Address(rsi, arrayOopDesc::base_offset_in_bytes(T_CHAR))); 515 } 516 517 // rbx, may be NULL 518 add_debug_info_for_null_check_here(info); 519 __ load_heap_oop(rdi, Address(rbx, java_lang_String::value_offset_in_bytes())); 520 if (java_lang_String::has_offset_field()) { 521 __ movptr (rcx, Address(rbx, java_lang_String::offset_offset_in_bytes())); 522 __ movl (rbx, Address(rbx, java_lang_String::count_offset_in_bytes())); 523 __ lea (rdi, Address(rdi, rcx, Address::times_2, arrayOopDesc::base_offset_in_bytes(T_CHAR))); 524 } else { 525 __ movl (rbx, Address(rdi, arrayOopDesc::length_offset_in_bytes())); 526 __ lea (rdi, Address(rdi, arrayOopDesc::base_offset_in_bytes(T_CHAR))); 527 } 528 529 // compute minimum length (in rax) and difference of lengths (on top of stack) 530 __ mov (rcx, rbx); 531 __ subptr(rbx, rax); // subtract lengths 532 __ push (rbx); // result 533 __ cmov (Assembler::lessEqual, rax, rcx); 534 535 // is minimum length 0? 536 Label noLoop, haveResult; 537 __ testptr (rax, rax); 538 __ jcc (Assembler::zero, noLoop); 539 540 // compare first characters 541 __ load_unsigned_short(rcx, Address(rdi, 0)); 542 __ load_unsigned_short(rbx, Address(rsi, 0)); 543 __ subl(rcx, rbx); 544 __ jcc(Assembler::notZero, haveResult); 545 // starting loop 546 __ decrement(rax); // we already tested index: skip one 547 __ jcc(Assembler::zero, noLoop); 548 549 // set rsi.edi to the end of the arrays (arrays have same length) 550 // negate the index 551 552 __ lea(rsi, Address(rsi, rax, Address::times_2, type2aelembytes(T_CHAR))); 553 __ lea(rdi, Address(rdi, rax, Address::times_2, type2aelembytes(T_CHAR))); 554 __ negptr(rax); 555 556 // compare the strings in a loop 557 558 Label loop; 559 __ align(wordSize); 560 __ bind(loop); 561 __ load_unsigned_short(rcx, Address(rdi, rax, Address::times_2, 0)); 562 __ load_unsigned_short(rbx, Address(rsi, rax, Address::times_2, 0)); 563 __ subl(rcx, rbx); 564 __ jcc(Assembler::notZero, haveResult); 565 __ increment(rax); 566 __ jcc(Assembler::notZero, loop); 567 568 // strings are equal up to min length 569 570 __ bind(noLoop); 571 __ pop(rax); 572 return_op(LIR_OprFact::illegalOpr); 573 574 __ bind(haveResult); 575 // leave instruction is going to discard the TOS value 576 __ mov (rax, rcx); // result of call is in rax, 577 } 578 579 580 void LIR_Assembler::return_op(LIR_Opr result) { 581 assert(result->is_illegal() || !result->is_single_cpu() || result->as_register() == rax, "word returns are in rax,"); 582 if (!result->is_illegal() && result->is_float_kind() && !result->is_xmm_register()) { 583 assert(result->fpu() == 0, "result must already be on TOS"); 584 } 585 586 // Pop the stack before the safepoint code 587 __ remove_frame(initial_frame_size_in_bytes()); 588 589 bool result_is_oop = result->is_valid() ? result->is_oop() : false; 590 591 // Note: we do not need to round double result; float result has the right precision 592 // the poll sets the condition code, but no data registers 593 AddressLiteral polling_page(os::get_polling_page() + (SafepointPollOffset % os::vm_page_size()), 594 relocInfo::poll_return_type); 595 596 if (Assembler::is_polling_page_far()) { 597 __ lea(rscratch1, polling_page); 598 __ relocate(relocInfo::poll_return_type); 599 __ testl(rax, Address(rscratch1, 0)); 600 } else { 601 __ testl(rax, polling_page); 602 } 603 __ ret(0); 604 } 605 606 607 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) { 608 AddressLiteral polling_page(os::get_polling_page() + (SafepointPollOffset % os::vm_page_size()), 609 relocInfo::poll_type); 610 guarantee(info != NULL, "Shouldn't be NULL"); 611 int offset = __ offset(); 612 if (Assembler::is_polling_page_far()) { 613 __ lea(rscratch1, polling_page); 614 offset = __ offset(); 615 add_debug_info_for_branch(info); 616 __ testl(rax, Address(rscratch1, 0)); 617 } else { 618 add_debug_info_for_branch(info); 619 __ testl(rax, polling_page); 620 } 621 return offset; 622 } 623 624 625 void LIR_Assembler::move_regs(Register from_reg, Register to_reg) { 626 if (from_reg != to_reg) __ mov(to_reg, from_reg); 627 } 628 629 void LIR_Assembler::swap_reg(Register a, Register b) { 630 __ xchgptr(a, b); 631 } 632 633 634 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) { 635 assert(src->is_constant(), "should not call otherwise"); 636 assert(dest->is_register(), "should not call otherwise"); 637 LIR_Const* c = src->as_constant_ptr(); 638 639 switch (c->type()) { 640 case T_INT: { 641 assert(patch_code == lir_patch_none, "no patching handled here"); 642 __ movl(dest->as_register(), c->as_jint()); 643 break; 644 } 645 646 case T_ADDRESS: { 647 assert(patch_code == lir_patch_none, "no patching handled here"); 648 __ movptr(dest->as_register(), c->as_jint()); 649 break; 650 } 651 652 case T_LONG: { 653 assert(patch_code == lir_patch_none, "no patching handled here"); 654 #ifdef _LP64 655 __ movptr(dest->as_register_lo(), (intptr_t)c->as_jlong()); 656 #else 657 __ movptr(dest->as_register_lo(), c->as_jint_lo()); 658 __ movptr(dest->as_register_hi(), c->as_jint_hi()); 659 #endif // _LP64 660 break; 661 } 662 663 case T_OBJECT: { 664 if (patch_code != lir_patch_none) { 665 jobject2reg_with_patching(dest->as_register(), info); 666 } else { 667 __ movoop(dest->as_register(), c->as_jobject()); 668 } 669 break; 670 } 671 672 case T_FLOAT: { 673 if (dest->is_single_xmm()) { 674 if (c->is_zero_float()) { 675 __ xorps(dest->as_xmm_float_reg(), dest->as_xmm_float_reg()); 676 } else { 677 __ movflt(dest->as_xmm_float_reg(), 678 InternalAddress(float_constant(c->as_jfloat()))); 679 } 680 } else { 681 assert(dest->is_single_fpu(), "must be"); 682 assert(dest->fpu_regnr() == 0, "dest must be TOS"); 683 if (c->is_zero_float()) { 684 __ fldz(); 685 } else if (c->is_one_float()) { 686 __ fld1(); 687 } else { 688 __ fld_s (InternalAddress(float_constant(c->as_jfloat()))); 689 } 690 } 691 break; 692 } 693 694 case T_DOUBLE: { 695 if (dest->is_double_xmm()) { 696 if (c->is_zero_double()) { 697 __ xorpd(dest->as_xmm_double_reg(), dest->as_xmm_double_reg()); 698 } else { 699 __ movdbl(dest->as_xmm_double_reg(), 700 InternalAddress(double_constant(c->as_jdouble()))); 701 } 702 } else { 703 assert(dest->is_double_fpu(), "must be"); 704 assert(dest->fpu_regnrLo() == 0, "dest must be TOS"); 705 if (c->is_zero_double()) { 706 __ fldz(); 707 } else if (c->is_one_double()) { 708 __ fld1(); 709 } else { 710 __ fld_d (InternalAddress(double_constant(c->as_jdouble()))); 711 } 712 } 713 break; 714 } 715 716 default: 717 ShouldNotReachHere(); 718 } 719 } 720 721 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) { 722 assert(src->is_constant(), "should not call otherwise"); 723 assert(dest->is_stack(), "should not call otherwise"); 724 LIR_Const* c = src->as_constant_ptr(); 725 726 switch (c->type()) { 727 case T_INT: // fall through 728 case T_FLOAT: 729 __ movl(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jint_bits()); 730 break; 731 732 case T_ADDRESS: 733 __ movptr(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jint_bits()); 734 break; 735 736 case T_OBJECT: 737 __ movoop(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jobject()); 738 break; 739 740 case T_LONG: // fall through 741 case T_DOUBLE: 742 #ifdef _LP64 743 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(), 744 lo_word_offset_in_bytes), (intptr_t)c->as_jlong_bits()); 745 #else 746 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(), 747 lo_word_offset_in_bytes), c->as_jint_lo_bits()); 748 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(), 749 hi_word_offset_in_bytes), c->as_jint_hi_bits()); 750 #endif // _LP64 751 break; 752 753 default: 754 ShouldNotReachHere(); 755 } 756 } 757 758 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide) { 759 assert(src->is_constant(), "should not call otherwise"); 760 assert(dest->is_address(), "should not call otherwise"); 761 LIR_Const* c = src->as_constant_ptr(); 762 LIR_Address* addr = dest->as_address_ptr(); 763 764 int null_check_here = code_offset(); 765 switch (type) { 766 case T_INT: // fall through 767 case T_FLOAT: 768 __ movl(as_Address(addr), c->as_jint_bits()); 769 break; 770 771 case T_ADDRESS: 772 __ movptr(as_Address(addr), c->as_jint_bits()); 773 break; 774 775 case T_OBJECT: // fall through 776 case T_ARRAY: 777 if (c->as_jobject() == NULL) { 778 if (UseCompressedOops && !wide) { 779 __ movl(as_Address(addr), (int32_t)NULL_WORD); 780 } else { 781 __ movptr(as_Address(addr), NULL_WORD); 782 } 783 } else { 784 if (is_literal_address(addr)) { 785 ShouldNotReachHere(); 786 __ movoop(as_Address(addr, noreg), c->as_jobject()); 787 } else { 788 #ifdef _LP64 789 __ movoop(rscratch1, c->as_jobject()); 790 if (UseCompressedOops && !wide) { 791 __ encode_heap_oop(rscratch1); 792 null_check_here = code_offset(); 793 __ movl(as_Address_lo(addr), rscratch1); 794 } else { 795 null_check_here = code_offset(); 796 __ movptr(as_Address_lo(addr), rscratch1); 797 } 798 #else 799 __ movoop(as_Address(addr), c->as_jobject()); 800 #endif 801 } 802 } 803 break; 804 805 case T_LONG: // fall through 806 case T_DOUBLE: 807 #ifdef _LP64 808 if (is_literal_address(addr)) { 809 ShouldNotReachHere(); 810 __ movptr(as_Address(addr, r15_thread), (intptr_t)c->as_jlong_bits()); 811 } else { 812 __ movptr(r10, (intptr_t)c->as_jlong_bits()); 813 null_check_here = code_offset(); 814 __ movptr(as_Address_lo(addr), r10); 815 } 816 #else 817 // Always reachable in 32bit so this doesn't produce useless move literal 818 __ movptr(as_Address_hi(addr), c->as_jint_hi_bits()); 819 __ movptr(as_Address_lo(addr), c->as_jint_lo_bits()); 820 #endif // _LP64 821 break; 822 823 case T_BOOLEAN: // fall through 824 case T_BYTE: 825 __ movb(as_Address(addr), c->as_jint() & 0xFF); 826 break; 827 828 case T_CHAR: // fall through 829 case T_SHORT: 830 __ movw(as_Address(addr), c->as_jint() & 0xFFFF); 831 break; 832 833 default: 834 ShouldNotReachHere(); 835 }; 836 837 if (info != NULL) { 838 add_debug_info_for_null_check(null_check_here, info); 839 } 840 } 841 842 843 void LIR_Assembler::reg2reg(LIR_Opr src, LIR_Opr dest) { 844 assert(src->is_register(), "should not call otherwise"); 845 assert(dest->is_register(), "should not call otherwise"); 846 847 // move between cpu-registers 848 if (dest->is_single_cpu()) { 849 #ifdef _LP64 850 if (src->type() == T_LONG) { 851 // Can do LONG -> OBJECT 852 move_regs(src->as_register_lo(), dest->as_register()); 853 return; 854 } 855 #endif 856 assert(src->is_single_cpu(), "must match"); 857 if (src->type() == T_OBJECT) { 858 __ verify_oop(src->as_register()); 859 } 860 move_regs(src->as_register(), dest->as_register()); 861 862 } else if (dest->is_double_cpu()) { 863 #ifdef _LP64 864 if (src->type() == T_OBJECT || src->type() == T_ARRAY) { 865 // Surprising to me but we can see move of a long to t_object 866 __ verify_oop(src->as_register()); 867 move_regs(src->as_register(), dest->as_register_lo()); 868 return; 869 } 870 #endif 871 assert(src->is_double_cpu(), "must match"); 872 Register f_lo = src->as_register_lo(); 873 Register f_hi = src->as_register_hi(); 874 Register t_lo = dest->as_register_lo(); 875 Register t_hi = dest->as_register_hi(); 876 #ifdef _LP64 877 assert(f_hi == f_lo, "must be same"); 878 assert(t_hi == t_lo, "must be same"); 879 move_regs(f_lo, t_lo); 880 #else 881 assert(f_lo != f_hi && t_lo != t_hi, "invalid register allocation"); 882 883 884 if (f_lo == t_hi && f_hi == t_lo) { 885 swap_reg(f_lo, f_hi); 886 } else if (f_hi == t_lo) { 887 assert(f_lo != t_hi, "overwriting register"); 888 move_regs(f_hi, t_hi); 889 move_regs(f_lo, t_lo); 890 } else { 891 assert(f_hi != t_lo, "overwriting register"); 892 move_regs(f_lo, t_lo); 893 move_regs(f_hi, t_hi); 894 } 895 #endif // LP64 896 897 // special moves from fpu-register to xmm-register 898 // necessary for method results 899 } else if (src->is_single_xmm() && !dest->is_single_xmm()) { 900 __ movflt(Address(rsp, 0), src->as_xmm_float_reg()); 901 __ fld_s(Address(rsp, 0)); 902 } else if (src->is_double_xmm() && !dest->is_double_xmm()) { 903 __ movdbl(Address(rsp, 0), src->as_xmm_double_reg()); 904 __ fld_d(Address(rsp, 0)); 905 } else if (dest->is_single_xmm() && !src->is_single_xmm()) { 906 __ fstp_s(Address(rsp, 0)); 907 __ movflt(dest->as_xmm_float_reg(), Address(rsp, 0)); 908 } else if (dest->is_double_xmm() && !src->is_double_xmm()) { 909 __ fstp_d(Address(rsp, 0)); 910 __ movdbl(dest->as_xmm_double_reg(), Address(rsp, 0)); 911 912 // move between xmm-registers 913 } else if (dest->is_single_xmm()) { 914 assert(src->is_single_xmm(), "must match"); 915 __ movflt(dest->as_xmm_float_reg(), src->as_xmm_float_reg()); 916 } else if (dest->is_double_xmm()) { 917 assert(src->is_double_xmm(), "must match"); 918 __ movdbl(dest->as_xmm_double_reg(), src->as_xmm_double_reg()); 919 920 // move between fpu-registers (no instruction necessary because of fpu-stack) 921 } else if (dest->is_single_fpu() || dest->is_double_fpu()) { 922 assert(src->is_single_fpu() || src->is_double_fpu(), "must match"); 923 assert(src->fpu() == dest->fpu(), "currently should be nothing to do"); 924 } else { 925 ShouldNotReachHere(); 926 } 927 } 928 929 void LIR_Assembler::reg2stack(LIR_Opr src, LIR_Opr dest, BasicType type, bool pop_fpu_stack) { 930 assert(src->is_register(), "should not call otherwise"); 931 assert(dest->is_stack(), "should not call otherwise"); 932 933 if (src->is_single_cpu()) { 934 Address dst = frame_map()->address_for_slot(dest->single_stack_ix()); 935 if (type == T_OBJECT || type == T_ARRAY) { 936 __ verify_oop(src->as_register()); 937 __ movptr (dst, src->as_register()); 938 } else { 939 __ movl (dst, src->as_register()); 940 } 941 942 } else if (src->is_double_cpu()) { 943 Address dstLO = frame_map()->address_for_slot(dest->double_stack_ix(), lo_word_offset_in_bytes); 944 Address dstHI = frame_map()->address_for_slot(dest->double_stack_ix(), hi_word_offset_in_bytes); 945 __ movptr (dstLO, src->as_register_lo()); 946 NOT_LP64(__ movptr (dstHI, src->as_register_hi())); 947 948 } else if (src->is_single_xmm()) { 949 Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix()); 950 __ movflt(dst_addr, src->as_xmm_float_reg()); 951 952 } else if (src->is_double_xmm()) { 953 Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix()); 954 __ movdbl(dst_addr, src->as_xmm_double_reg()); 955 956 } else if (src->is_single_fpu()) { 957 assert(src->fpu_regnr() == 0, "argument must be on TOS"); 958 Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix()); 959 if (pop_fpu_stack) __ fstp_s (dst_addr); 960 else __ fst_s (dst_addr); 961 962 } else if (src->is_double_fpu()) { 963 assert(src->fpu_regnrLo() == 0, "argument must be on TOS"); 964 Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix()); 965 if (pop_fpu_stack) __ fstp_d (dst_addr); 966 else __ fst_d (dst_addr); 967 968 } else { 969 ShouldNotReachHere(); 970 } 971 } 972 973 974 void LIR_Assembler::reg2mem(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack, bool wide, bool /* unaligned */) { 975 LIR_Address* to_addr = dest->as_address_ptr(); 976 PatchingStub* patch = NULL; 977 Register compressed_src = rscratch1; 978 979 if (type == T_ARRAY || type == T_OBJECT) { 980 __ verify_oop(src->as_register()); 981 #ifdef _LP64 982 if (UseCompressedOops && !wide) { 983 __ movptr(compressed_src, src->as_register()); 984 __ encode_heap_oop(compressed_src); 985 } 986 #endif 987 } 988 989 if (patch_code != lir_patch_none) { 990 patch = new PatchingStub(_masm, PatchingStub::access_field_id); 991 Address toa = as_Address(to_addr); 992 assert(toa.disp() != 0, "must have"); 993 } 994 995 int null_check_here = code_offset(); 996 switch (type) { 997 case T_FLOAT: { 998 if (src->is_single_xmm()) { 999 __ movflt(as_Address(to_addr), src->as_xmm_float_reg()); 1000 } else { 1001 assert(src->is_single_fpu(), "must be"); 1002 assert(src->fpu_regnr() == 0, "argument must be on TOS"); 1003 if (pop_fpu_stack) __ fstp_s(as_Address(to_addr)); 1004 else __ fst_s (as_Address(to_addr)); 1005 } 1006 break; 1007 } 1008 1009 case T_DOUBLE: { 1010 if (src->is_double_xmm()) { 1011 __ movdbl(as_Address(to_addr), src->as_xmm_double_reg()); 1012 } else { 1013 assert(src->is_double_fpu(), "must be"); 1014 assert(src->fpu_regnrLo() == 0, "argument must be on TOS"); 1015 if (pop_fpu_stack) __ fstp_d(as_Address(to_addr)); 1016 else __ fst_d (as_Address(to_addr)); 1017 } 1018 break; 1019 } 1020 1021 case T_ARRAY: // fall through 1022 case T_OBJECT: // fall through 1023 if (UseCompressedOops && !wide) { 1024 __ movl(as_Address(to_addr), compressed_src); 1025 } else { 1026 __ movptr(as_Address(to_addr), src->as_register()); 1027 } 1028 break; 1029 case T_ADDRESS: 1030 __ movptr(as_Address(to_addr), src->as_register()); 1031 break; 1032 case T_INT: 1033 __ movl(as_Address(to_addr), src->as_register()); 1034 break; 1035 1036 case T_LONG: { 1037 Register from_lo = src->as_register_lo(); 1038 Register from_hi = src->as_register_hi(); 1039 #ifdef _LP64 1040 __ movptr(as_Address_lo(to_addr), from_lo); 1041 #else 1042 Register base = to_addr->base()->as_register(); 1043 Register index = noreg; 1044 if (to_addr->index()->is_register()) { 1045 index = to_addr->index()->as_register(); 1046 } 1047 if (base == from_lo || index == from_lo) { 1048 assert(base != from_hi, "can't be"); 1049 assert(index == noreg || (index != base && index != from_hi), "can't handle this"); 1050 __ movl(as_Address_hi(to_addr), from_hi); 1051 if (patch != NULL) { 1052 patching_epilog(patch, lir_patch_high, base, info); 1053 patch = new PatchingStub(_masm, PatchingStub::access_field_id); 1054 patch_code = lir_patch_low; 1055 } 1056 __ movl(as_Address_lo(to_addr), from_lo); 1057 } else { 1058 assert(index == noreg || (index != base && index != from_lo), "can't handle this"); 1059 __ movl(as_Address_lo(to_addr), from_lo); 1060 if (patch != NULL) { 1061 patching_epilog(patch, lir_patch_low, base, info); 1062 patch = new PatchingStub(_masm, PatchingStub::access_field_id); 1063 patch_code = lir_patch_high; 1064 } 1065 __ movl(as_Address_hi(to_addr), from_hi); 1066 } 1067 #endif // _LP64 1068 break; 1069 } 1070 1071 case T_BYTE: // fall through 1072 case T_BOOLEAN: { 1073 Register src_reg = src->as_register(); 1074 Address dst_addr = as_Address(to_addr); 1075 assert(VM_Version::is_P6() || src_reg->has_byte_register(), "must use byte registers if not P6"); 1076 __ movb(dst_addr, src_reg); 1077 break; 1078 } 1079 1080 case T_CHAR: // fall through 1081 case T_SHORT: 1082 __ movw(as_Address(to_addr), src->as_register()); 1083 break; 1084 1085 default: 1086 ShouldNotReachHere(); 1087 } 1088 if (info != NULL) { 1089 add_debug_info_for_null_check(null_check_here, info); 1090 } 1091 1092 if (patch_code != lir_patch_none) { 1093 patching_epilog(patch, patch_code, to_addr->base()->as_register(), info); 1094 } 1095 } 1096 1097 1098 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) { 1099 assert(src->is_stack(), "should not call otherwise"); 1100 assert(dest->is_register(), "should not call otherwise"); 1101 1102 if (dest->is_single_cpu()) { 1103 if (type == T_ARRAY || type == T_OBJECT) { 1104 __ movptr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix())); 1105 __ verify_oop(dest->as_register()); 1106 } else { 1107 __ movl(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix())); 1108 } 1109 1110 } else if (dest->is_double_cpu()) { 1111 Address src_addr_LO = frame_map()->address_for_slot(src->double_stack_ix(), lo_word_offset_in_bytes); 1112 Address src_addr_HI = frame_map()->address_for_slot(src->double_stack_ix(), hi_word_offset_in_bytes); 1113 __ movptr(dest->as_register_lo(), src_addr_LO); 1114 NOT_LP64(__ movptr(dest->as_register_hi(), src_addr_HI)); 1115 1116 } else if (dest->is_single_xmm()) { 1117 Address src_addr = frame_map()->address_for_slot(src->single_stack_ix()); 1118 __ movflt(dest->as_xmm_float_reg(), src_addr); 1119 1120 } else if (dest->is_double_xmm()) { 1121 Address src_addr = frame_map()->address_for_slot(src->double_stack_ix()); 1122 __ movdbl(dest->as_xmm_double_reg(), src_addr); 1123 1124 } else if (dest->is_single_fpu()) { 1125 assert(dest->fpu_regnr() == 0, "dest must be TOS"); 1126 Address src_addr = frame_map()->address_for_slot(src->single_stack_ix()); 1127 __ fld_s(src_addr); 1128 1129 } else if (dest->is_double_fpu()) { 1130 assert(dest->fpu_regnrLo() == 0, "dest must be TOS"); 1131 Address src_addr = frame_map()->address_for_slot(src->double_stack_ix()); 1132 __ fld_d(src_addr); 1133 1134 } else { 1135 ShouldNotReachHere(); 1136 } 1137 } 1138 1139 1140 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) { 1141 if (src->is_single_stack()) { 1142 if (type == T_OBJECT || type == T_ARRAY) { 1143 __ pushptr(frame_map()->address_for_slot(src ->single_stack_ix())); 1144 __ popptr (frame_map()->address_for_slot(dest->single_stack_ix())); 1145 } else { 1146 #ifndef _LP64 1147 __ pushl(frame_map()->address_for_slot(src ->single_stack_ix())); 1148 __ popl (frame_map()->address_for_slot(dest->single_stack_ix())); 1149 #else 1150 //no pushl on 64bits 1151 __ movl(rscratch1, frame_map()->address_for_slot(src ->single_stack_ix())); 1152 __ movl(frame_map()->address_for_slot(dest->single_stack_ix()), rscratch1); 1153 #endif 1154 } 1155 1156 } else if (src->is_double_stack()) { 1157 #ifdef _LP64 1158 __ pushptr(frame_map()->address_for_slot(src ->double_stack_ix())); 1159 __ popptr (frame_map()->address_for_slot(dest->double_stack_ix())); 1160 #else 1161 __ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), 0)); 1162 // push and pop the part at src + wordSize, adding wordSize for the previous push 1163 __ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), 2 * wordSize)); 1164 __ popl (frame_map()->address_for_slot(dest->double_stack_ix(), 2 * wordSize)); 1165 __ popl (frame_map()->address_for_slot(dest->double_stack_ix(), 0)); 1166 #endif // _LP64 1167 1168 } else { 1169 ShouldNotReachHere(); 1170 } 1171 } 1172 1173 1174 void LIR_Assembler::mem2reg(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide, bool /* unaligned */) { 1175 assert(src->is_address(), "should not call otherwise"); 1176 assert(dest->is_register(), "should not call otherwise"); 1177 1178 LIR_Address* addr = src->as_address_ptr(); 1179 Address from_addr = as_Address(addr); 1180 1181 switch (type) { 1182 case T_BOOLEAN: // fall through 1183 case T_BYTE: // fall through 1184 case T_CHAR: // fall through 1185 case T_SHORT: 1186 if (!VM_Version::is_P6() && !from_addr.uses(dest->as_register())) { 1187 // on pre P6 processors we may get partial register stalls 1188 // so blow away the value of to_rinfo before loading a 1189 // partial word into it. Do it here so that it precedes 1190 // the potential patch point below. 1191 __ xorptr(dest->as_register(), dest->as_register()); 1192 } 1193 break; 1194 } 1195 1196 PatchingStub* patch = NULL; 1197 if (patch_code != lir_patch_none) { 1198 patch = new PatchingStub(_masm, PatchingStub::access_field_id); 1199 assert(from_addr.disp() != 0, "must have"); 1200 } 1201 if (info != NULL) { 1202 add_debug_info_for_null_check_here(info); 1203 } 1204 1205 switch (type) { 1206 case T_FLOAT: { 1207 if (dest->is_single_xmm()) { 1208 __ movflt(dest->as_xmm_float_reg(), from_addr); 1209 } else { 1210 assert(dest->is_single_fpu(), "must be"); 1211 assert(dest->fpu_regnr() == 0, "dest must be TOS"); 1212 __ fld_s(from_addr); 1213 } 1214 break; 1215 } 1216 1217 case T_DOUBLE: { 1218 if (dest->is_double_xmm()) { 1219 __ movdbl(dest->as_xmm_double_reg(), from_addr); 1220 } else { 1221 assert(dest->is_double_fpu(), "must be"); 1222 assert(dest->fpu_regnrLo() == 0, "dest must be TOS"); 1223 __ fld_d(from_addr); 1224 } 1225 break; 1226 } 1227 1228 case T_OBJECT: // fall through 1229 case T_ARRAY: // fall through 1230 if (UseCompressedOops && !wide) { 1231 __ movl(dest->as_register(), from_addr); 1232 } else { 1233 __ movptr(dest->as_register(), from_addr); 1234 } 1235 break; 1236 1237 case T_ADDRESS: 1238 __ movptr(dest->as_register(), from_addr); 1239 break; 1240 case T_INT: 1241 __ movl(dest->as_register(), from_addr); 1242 break; 1243 1244 case T_LONG: { 1245 Register to_lo = dest->as_register_lo(); 1246 Register to_hi = dest->as_register_hi(); 1247 #ifdef _LP64 1248 __ movptr(to_lo, as_Address_lo(addr)); 1249 #else 1250 Register base = addr->base()->as_register(); 1251 Register index = noreg; 1252 if (addr->index()->is_register()) { 1253 index = addr->index()->as_register(); 1254 } 1255 if ((base == to_lo && index == to_hi) || 1256 (base == to_hi && index == to_lo)) { 1257 // addresses with 2 registers are only formed as a result of 1258 // array access so this code will never have to deal with 1259 // patches or null checks. 1260 assert(info == NULL && patch == NULL, "must be"); 1261 __ lea(to_hi, as_Address(addr)); 1262 __ movl(to_lo, Address(to_hi, 0)); 1263 __ movl(to_hi, Address(to_hi, BytesPerWord)); 1264 } else if (base == to_lo || index == to_lo) { 1265 assert(base != to_hi, "can't be"); 1266 assert(index == noreg || (index != base && index != to_hi), "can't handle this"); 1267 __ movl(to_hi, as_Address_hi(addr)); 1268 if (patch != NULL) { 1269 patching_epilog(patch, lir_patch_high, base, info); 1270 patch = new PatchingStub(_masm, PatchingStub::access_field_id); 1271 patch_code = lir_patch_low; 1272 } 1273 __ movl(to_lo, as_Address_lo(addr)); 1274 } else { 1275 assert(index == noreg || (index != base && index != to_lo), "can't handle this"); 1276 __ movl(to_lo, as_Address_lo(addr)); 1277 if (patch != NULL) { 1278 patching_epilog(patch, lir_patch_low, base, info); 1279 patch = new PatchingStub(_masm, PatchingStub::access_field_id); 1280 patch_code = lir_patch_high; 1281 } 1282 __ movl(to_hi, as_Address_hi(addr)); 1283 } 1284 #endif // _LP64 1285 break; 1286 } 1287 1288 case T_BOOLEAN: // fall through 1289 case T_BYTE: { 1290 Register dest_reg = dest->as_register(); 1291 assert(VM_Version::is_P6() || dest_reg->has_byte_register(), "must use byte registers if not P6"); 1292 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) { 1293 __ movsbl(dest_reg, from_addr); 1294 } else { 1295 __ movb(dest_reg, from_addr); 1296 __ shll(dest_reg, 24); 1297 __ sarl(dest_reg, 24); 1298 } 1299 break; 1300 } 1301 1302 case T_CHAR: { 1303 Register dest_reg = dest->as_register(); 1304 assert(VM_Version::is_P6() || dest_reg->has_byte_register(), "must use byte registers if not P6"); 1305 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) { 1306 __ movzwl(dest_reg, from_addr); 1307 } else { 1308 __ movw(dest_reg, from_addr); 1309 } 1310 break; 1311 } 1312 1313 case T_SHORT: { 1314 Register dest_reg = dest->as_register(); 1315 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) { 1316 __ movswl(dest_reg, from_addr); 1317 } else { 1318 __ movw(dest_reg, from_addr); 1319 __ shll(dest_reg, 16); 1320 __ sarl(dest_reg, 16); 1321 } 1322 break; 1323 } 1324 1325 default: 1326 ShouldNotReachHere(); 1327 } 1328 1329 if (patch != NULL) { 1330 patching_epilog(patch, patch_code, addr->base()->as_register(), info); 1331 } 1332 1333 if (type == T_ARRAY || type == T_OBJECT) { 1334 #ifdef _LP64 1335 if (UseCompressedOops && !wide) { 1336 __ decode_heap_oop(dest->as_register()); 1337 } 1338 #endif 1339 __ verify_oop(dest->as_register()); 1340 } 1341 } 1342 1343 1344 void LIR_Assembler::prefetchr(LIR_Opr src) { 1345 LIR_Address* addr = src->as_address_ptr(); 1346 Address from_addr = as_Address(addr); 1347 1348 if (VM_Version::supports_sse()) { 1349 switch (ReadPrefetchInstr) { 1350 case 0: 1351 __ prefetchnta(from_addr); break; 1352 case 1: 1353 __ prefetcht0(from_addr); break; 1354 case 2: 1355 __ prefetcht2(from_addr); break; 1356 default: 1357 ShouldNotReachHere(); break; 1358 } 1359 } else if (VM_Version::supports_3dnow_prefetch()) { 1360 __ prefetchr(from_addr); 1361 } 1362 } 1363 1364 1365 void LIR_Assembler::prefetchw(LIR_Opr src) { 1366 LIR_Address* addr = src->as_address_ptr(); 1367 Address from_addr = as_Address(addr); 1368 1369 if (VM_Version::supports_sse()) { 1370 switch (AllocatePrefetchInstr) { 1371 case 0: 1372 __ prefetchnta(from_addr); break; 1373 case 1: 1374 __ prefetcht0(from_addr); break; 1375 case 2: 1376 __ prefetcht2(from_addr); break; 1377 case 3: 1378 __ prefetchw(from_addr); break; 1379 default: 1380 ShouldNotReachHere(); break; 1381 } 1382 } else if (VM_Version::supports_3dnow_prefetch()) { 1383 __ prefetchw(from_addr); 1384 } 1385 } 1386 1387 1388 NEEDS_CLEANUP; // This could be static? 1389 Address::ScaleFactor LIR_Assembler::array_element_size(BasicType type) const { 1390 int elem_size = type2aelembytes(type); 1391 switch (elem_size) { 1392 case 1: return Address::times_1; 1393 case 2: return Address::times_2; 1394 case 4: return Address::times_4; 1395 case 8: return Address::times_8; 1396 } 1397 ShouldNotReachHere(); 1398 return Address::no_scale; 1399 } 1400 1401 1402 void LIR_Assembler::emit_op3(LIR_Op3* op) { 1403 switch (op->code()) { 1404 case lir_idiv: 1405 case lir_irem: 1406 arithmetic_idiv(op->code(), 1407 op->in_opr1(), 1408 op->in_opr2(), 1409 op->in_opr3(), 1410 op->result_opr(), 1411 op->info()); 1412 break; 1413 default: ShouldNotReachHere(); break; 1414 } 1415 } 1416 1417 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) { 1418 #ifdef ASSERT 1419 assert(op->block() == NULL || op->block()->label() == op->label(), "wrong label"); 1420 if (op->block() != NULL) _branch_target_blocks.append(op->block()); 1421 if (op->ublock() != NULL) _branch_target_blocks.append(op->ublock()); 1422 #endif 1423 1424 if (op->cond() == lir_cond_always) { 1425 if (op->info() != NULL) add_debug_info_for_branch(op->info()); 1426 __ jmp (*(op->label())); 1427 } else { 1428 Assembler::Condition acond = Assembler::zero; 1429 if (op->code() == lir_cond_float_branch) { 1430 assert(op->ublock() != NULL, "must have unordered successor"); 1431 __ jcc(Assembler::parity, *(op->ublock()->label())); 1432 switch(op->cond()) { 1433 case lir_cond_equal: acond = Assembler::equal; break; 1434 case lir_cond_notEqual: acond = Assembler::notEqual; break; 1435 case lir_cond_less: acond = Assembler::below; break; 1436 case lir_cond_lessEqual: acond = Assembler::belowEqual; break; 1437 case lir_cond_greaterEqual: acond = Assembler::aboveEqual; break; 1438 case lir_cond_greater: acond = Assembler::above; break; 1439 default: ShouldNotReachHere(); 1440 } 1441 } else { 1442 switch (op->cond()) { 1443 case lir_cond_equal: acond = Assembler::equal; break; 1444 case lir_cond_notEqual: acond = Assembler::notEqual; break; 1445 case lir_cond_less: acond = Assembler::less; break; 1446 case lir_cond_lessEqual: acond = Assembler::lessEqual; break; 1447 case lir_cond_greaterEqual: acond = Assembler::greaterEqual;break; 1448 case lir_cond_greater: acond = Assembler::greater; break; 1449 case lir_cond_belowEqual: acond = Assembler::belowEqual; break; 1450 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; break; 1451 default: ShouldNotReachHere(); 1452 } 1453 } 1454 __ jcc(acond,*(op->label())); 1455 } 1456 } 1457 1458 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) { 1459 LIR_Opr src = op->in_opr(); 1460 LIR_Opr dest = op->result_opr(); 1461 1462 switch (op->bytecode()) { 1463 case Bytecodes::_i2l: 1464 #ifdef _LP64 1465 __ movl2ptr(dest->as_register_lo(), src->as_register()); 1466 #else 1467 move_regs(src->as_register(), dest->as_register_lo()); 1468 move_regs(src->as_register(), dest->as_register_hi()); 1469 __ sarl(dest->as_register_hi(), 31); 1470 #endif // LP64 1471 break; 1472 1473 case Bytecodes::_l2i: 1474 #ifdef _LP64 1475 __ movl(dest->as_register(), src->as_register_lo()); 1476 #else 1477 move_regs(src->as_register_lo(), dest->as_register()); 1478 #endif 1479 break; 1480 1481 case Bytecodes::_i2b: 1482 move_regs(src->as_register(), dest->as_register()); 1483 __ sign_extend_byte(dest->as_register()); 1484 break; 1485 1486 case Bytecodes::_i2c: 1487 move_regs(src->as_register(), dest->as_register()); 1488 __ andl(dest->as_register(), 0xFFFF); 1489 break; 1490 1491 case Bytecodes::_i2s: 1492 move_regs(src->as_register(), dest->as_register()); 1493 __ sign_extend_short(dest->as_register()); 1494 break; 1495 1496 1497 case Bytecodes::_f2d: 1498 case Bytecodes::_d2f: 1499 if (dest->is_single_xmm()) { 1500 __ cvtsd2ss(dest->as_xmm_float_reg(), src->as_xmm_double_reg()); 1501 } else if (dest->is_double_xmm()) { 1502 __ cvtss2sd(dest->as_xmm_double_reg(), src->as_xmm_float_reg()); 1503 } else { 1504 assert(src->fpu() == dest->fpu(), "register must be equal"); 1505 // do nothing (float result is rounded later through spilling) 1506 } 1507 break; 1508 1509 case Bytecodes::_i2f: 1510 case Bytecodes::_i2d: 1511 if (dest->is_single_xmm()) { 1512 __ cvtsi2ssl(dest->as_xmm_float_reg(), src->as_register()); 1513 } else if (dest->is_double_xmm()) { 1514 __ cvtsi2sdl(dest->as_xmm_double_reg(), src->as_register()); 1515 } else { 1516 assert(dest->fpu() == 0, "result must be on TOS"); 1517 __ movl(Address(rsp, 0), src->as_register()); 1518 __ fild_s(Address(rsp, 0)); 1519 } 1520 break; 1521 1522 case Bytecodes::_f2i: 1523 case Bytecodes::_d2i: 1524 if (src->is_single_xmm()) { 1525 __ cvttss2sil(dest->as_register(), src->as_xmm_float_reg()); 1526 } else if (src->is_double_xmm()) { 1527 __ cvttsd2sil(dest->as_register(), src->as_xmm_double_reg()); 1528 } else { 1529 assert(src->fpu() == 0, "input must be on TOS"); 1530 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_trunc())); 1531 __ fist_s(Address(rsp, 0)); 1532 __ movl(dest->as_register(), Address(rsp, 0)); 1533 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std())); 1534 } 1535 1536 // IA32 conversion instructions do not match JLS for overflow, underflow and NaN -> fixup in stub 1537 assert(op->stub() != NULL, "stub required"); 1538 __ cmpl(dest->as_register(), 0x80000000); 1539 __ jcc(Assembler::equal, *op->stub()->entry()); 1540 __ bind(*op->stub()->continuation()); 1541 break; 1542 1543 case Bytecodes::_l2f: 1544 case Bytecodes::_l2d: 1545 assert(!dest->is_xmm_register(), "result in xmm register not supported (no SSE instruction present)"); 1546 assert(dest->fpu() == 0, "result must be on TOS"); 1547 1548 __ movptr(Address(rsp, 0), src->as_register_lo()); 1549 NOT_LP64(__ movl(Address(rsp, BytesPerWord), src->as_register_hi())); 1550 __ fild_d(Address(rsp, 0)); 1551 // float result is rounded later through spilling 1552 break; 1553 1554 case Bytecodes::_f2l: 1555 case Bytecodes::_d2l: 1556 assert(!src->is_xmm_register(), "input in xmm register not supported (no SSE instruction present)"); 1557 assert(src->fpu() == 0, "input must be on TOS"); 1558 assert(dest == FrameMap::long0_opr, "runtime stub places result in these registers"); 1559 1560 // instruction sequence too long to inline it here 1561 { 1562 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::fpu2long_stub_id))); 1563 } 1564 break; 1565 1566 default: ShouldNotReachHere(); 1567 } 1568 } 1569 1570 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) { 1571 if (op->init_check()) { 1572 __ cmpb(Address(op->klass()->as_register(), 1573 instanceKlass::init_state_offset()), 1574 instanceKlass::fully_initialized); 1575 add_debug_info_for_null_check_here(op->stub()->info()); 1576 __ jcc(Assembler::notEqual, *op->stub()->entry()); 1577 } 1578 __ allocate_object(op->obj()->as_register(), 1579 op->tmp1()->as_register(), 1580 op->tmp2()->as_register(), 1581 op->header_size(), 1582 op->object_size(), 1583 op->klass()->as_register(), 1584 *op->stub()->entry()); 1585 __ bind(*op->stub()->continuation()); 1586 } 1587 1588 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) { 1589 Register len = op->len()->as_register(); 1590 LP64_ONLY( __ movslq(len, len); ) 1591 1592 if (UseSlowPath || 1593 (!UseFastNewObjectArray && (op->type() == T_OBJECT || op->type() == T_ARRAY)) || 1594 (!UseFastNewTypeArray && (op->type() != T_OBJECT && op->type() != T_ARRAY))) { 1595 __ jmp(*op->stub()->entry()); 1596 } else { 1597 Register tmp1 = op->tmp1()->as_register(); 1598 Register tmp2 = op->tmp2()->as_register(); 1599 Register tmp3 = op->tmp3()->as_register(); 1600 if (len == tmp1) { 1601 tmp1 = tmp3; 1602 } else if (len == tmp2) { 1603 tmp2 = tmp3; 1604 } else if (len == tmp3) { 1605 // everything is ok 1606 } else { 1607 __ mov(tmp3, len); 1608 } 1609 __ allocate_array(op->obj()->as_register(), 1610 len, 1611 tmp1, 1612 tmp2, 1613 arrayOopDesc::header_size(op->type()), 1614 array_element_size(op->type()), 1615 op->klass()->as_register(), 1616 *op->stub()->entry()); 1617 } 1618 __ bind(*op->stub()->continuation()); 1619 } 1620 1621 void LIR_Assembler::type_profile_helper(Register mdo, 1622 ciMethodData *md, ciProfileData *data, 1623 Register recv, Label* update_done) { 1624 for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) { 1625 Label next_test; 1626 // See if the receiver is receiver[n]. 1627 __ cmpptr(recv, Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)))); 1628 __ jccb(Assembler::notEqual, next_test); 1629 Address data_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i))); 1630 __ addptr(data_addr, DataLayout::counter_increment); 1631 __ jmp(*update_done); 1632 __ bind(next_test); 1633 } 1634 1635 // Didn't find receiver; find next empty slot and fill it in 1636 for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) { 1637 Label next_test; 1638 Address recv_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i))); 1639 __ cmpptr(recv_addr, (intptr_t)NULL_WORD); 1640 __ jccb(Assembler::notEqual, next_test); 1641 __ movptr(recv_addr, recv); 1642 __ movptr(Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i))), DataLayout::counter_increment); 1643 __ jmp(*update_done); 1644 __ bind(next_test); 1645 } 1646 } 1647 1648 void LIR_Assembler::emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null) { 1649 // we always need a stub for the failure case. 1650 CodeStub* stub = op->stub(); 1651 Register obj = op->object()->as_register(); 1652 Register k_RInfo = op->tmp1()->as_register(); 1653 Register klass_RInfo = op->tmp2()->as_register(); 1654 Register dst = op->result_opr()->as_register(); 1655 ciKlass* k = op->klass(); 1656 Register Rtmp1 = noreg; 1657 1658 // check if it needs to be profiled 1659 ciMethodData* md; 1660 ciProfileData* data; 1661 1662 if (op->should_profile()) { 1663 ciMethod* method = op->profiled_method(); 1664 assert(method != NULL, "Should have method"); 1665 int bci = op->profiled_bci(); 1666 md = method->method_data_or_null(); 1667 assert(md != NULL, "Sanity"); 1668 data = md->bci_to_data(bci); 1669 assert(data != NULL, "need data for type check"); 1670 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check"); 1671 } 1672 Label profile_cast_success, profile_cast_failure; 1673 Label *success_target = op->should_profile() ? &profile_cast_success : success; 1674 Label *failure_target = op->should_profile() ? &profile_cast_failure : failure; 1675 1676 if (obj == k_RInfo) { 1677 k_RInfo = dst; 1678 } else if (obj == klass_RInfo) { 1679 klass_RInfo = dst; 1680 } 1681 if (k->is_loaded() && !UseCompressedOops) { 1682 select_different_registers(obj, dst, k_RInfo, klass_RInfo); 1683 } else { 1684 Rtmp1 = op->tmp3()->as_register(); 1685 select_different_registers(obj, dst, k_RInfo, klass_RInfo, Rtmp1); 1686 } 1687 1688 assert_different_registers(obj, k_RInfo, klass_RInfo); 1689 if (!k->is_loaded()) { 1690 jobject2reg_with_patching(k_RInfo, op->info_for_patch()); 1691 } else { 1692 #ifdef _LP64 1693 __ movoop(k_RInfo, k->constant_encoding()); 1694 #endif // _LP64 1695 } 1696 assert(obj != k_RInfo, "must be different"); 1697 1698 __ cmpptr(obj, (int32_t)NULL_WORD); 1699 if (op->should_profile()) { 1700 Label not_null; 1701 __ jccb(Assembler::notEqual, not_null); 1702 // Object is null; update MDO and exit 1703 Register mdo = klass_RInfo; 1704 __ movoop(mdo, md->constant_encoding()); 1705 Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::header_offset())); 1706 int header_bits = DataLayout::flag_mask_to_header_mask(BitData::null_seen_byte_constant()); 1707 __ orl(data_addr, header_bits); 1708 __ jmp(*obj_is_null); 1709 __ bind(not_null); 1710 } else { 1711 __ jcc(Assembler::equal, *obj_is_null); 1712 } 1713 __ verify_oop(obj); 1714 1715 if (op->fast_check()) { 1716 // get object class 1717 // not a safepoint as obj null check happens earlier 1718 #ifdef _LP64 1719 if (UseCompressedOops) { 1720 __ load_klass(Rtmp1, obj); 1721 __ cmpptr(k_RInfo, Rtmp1); 1722 } else { 1723 __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes())); 1724 } 1725 #else 1726 if (k->is_loaded()) { 1727 __ cmpoop(Address(obj, oopDesc::klass_offset_in_bytes()), k->constant_encoding()); 1728 } else { 1729 __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes())); 1730 } 1731 #endif 1732 __ jcc(Assembler::notEqual, *failure_target); 1733 // successful cast, fall through to profile or jump 1734 } else { 1735 // get object class 1736 // not a safepoint as obj null check happens earlier 1737 __ load_klass(klass_RInfo, obj); 1738 if (k->is_loaded()) { 1739 // See if we get an immediate positive hit 1740 #ifdef _LP64 1741 __ cmpptr(k_RInfo, Address(klass_RInfo, k->super_check_offset())); 1742 #else 1743 __ cmpoop(Address(klass_RInfo, k->super_check_offset()), k->constant_encoding()); 1744 #endif // _LP64 1745 if ((juint)in_bytes(Klass::secondary_super_cache_offset()) != k->super_check_offset()) { 1746 __ jcc(Assembler::notEqual, *failure_target); 1747 // successful cast, fall through to profile or jump 1748 } else { 1749 // See if we get an immediate positive hit 1750 __ jcc(Assembler::equal, *success_target); 1751 // check for self 1752 #ifdef _LP64 1753 __ cmpptr(klass_RInfo, k_RInfo); 1754 #else 1755 __ cmpoop(klass_RInfo, k->constant_encoding()); 1756 #endif // _LP64 1757 __ jcc(Assembler::equal, *success_target); 1758 1759 __ push(klass_RInfo); 1760 #ifdef _LP64 1761 __ push(k_RInfo); 1762 #else 1763 __ pushoop(k->constant_encoding()); 1764 #endif // _LP64 1765 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id))); 1766 __ pop(klass_RInfo); 1767 __ pop(klass_RInfo); 1768 // result is a boolean 1769 __ cmpl(klass_RInfo, 0); 1770 __ jcc(Assembler::equal, *failure_target); 1771 // successful cast, fall through to profile or jump 1772 } 1773 } else { 1774 // perform the fast part of the checking logic 1775 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, NULL); 1776 // call out-of-line instance of __ check_klass_subtype_slow_path(...): 1777 __ push(klass_RInfo); 1778 __ push(k_RInfo); 1779 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id))); 1780 __ pop(klass_RInfo); 1781 __ pop(k_RInfo); 1782 // result is a boolean 1783 __ cmpl(k_RInfo, 0); 1784 __ jcc(Assembler::equal, *failure_target); 1785 // successful cast, fall through to profile or jump 1786 } 1787 } 1788 if (op->should_profile()) { 1789 Register mdo = klass_RInfo, recv = k_RInfo; 1790 __ bind(profile_cast_success); 1791 __ movoop(mdo, md->constant_encoding()); 1792 __ load_klass(recv, obj); 1793 Label update_done; 1794 type_profile_helper(mdo, md, data, recv, success); 1795 __ jmp(*success); 1796 1797 __ bind(profile_cast_failure); 1798 __ movoop(mdo, md->constant_encoding()); 1799 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset())); 1800 __ subptr(counter_addr, DataLayout::counter_increment); 1801 __ jmp(*failure); 1802 } 1803 __ jmp(*success); 1804 } 1805 1806 1807 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) { 1808 LIR_Code code = op->code(); 1809 if (code == lir_store_check) { 1810 Register value = op->object()->as_register(); 1811 Register array = op->array()->as_register(); 1812 Register k_RInfo = op->tmp1()->as_register(); 1813 Register klass_RInfo = op->tmp2()->as_register(); 1814 Register Rtmp1 = op->tmp3()->as_register(); 1815 1816 CodeStub* stub = op->stub(); 1817 1818 // check if it needs to be profiled 1819 ciMethodData* md; 1820 ciProfileData* data; 1821 1822 if (op->should_profile()) { 1823 ciMethod* method = op->profiled_method(); 1824 assert(method != NULL, "Should have method"); 1825 int bci = op->profiled_bci(); 1826 md = method->method_data_or_null(); 1827 assert(md != NULL, "Sanity"); 1828 data = md->bci_to_data(bci); 1829 assert(data != NULL, "need data for type check"); 1830 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check"); 1831 } 1832 Label profile_cast_success, profile_cast_failure, done; 1833 Label *success_target = op->should_profile() ? &profile_cast_success : &done; 1834 Label *failure_target = op->should_profile() ? &profile_cast_failure : stub->entry(); 1835 1836 __ cmpptr(value, (int32_t)NULL_WORD); 1837 if (op->should_profile()) { 1838 Label not_null; 1839 __ jccb(Assembler::notEqual, not_null); 1840 // Object is null; update MDO and exit 1841 Register mdo = klass_RInfo; 1842 __ movoop(mdo, md->constant_encoding()); 1843 Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::header_offset())); 1844 int header_bits = DataLayout::flag_mask_to_header_mask(BitData::null_seen_byte_constant()); 1845 __ orl(data_addr, header_bits); 1846 __ jmp(done); 1847 __ bind(not_null); 1848 } else { 1849 __ jcc(Assembler::equal, done); 1850 } 1851 1852 add_debug_info_for_null_check_here(op->info_for_exception()); 1853 __ load_klass(k_RInfo, array); 1854 __ load_klass(klass_RInfo, value); 1855 1856 // get instance klass (it's already uncompressed) 1857 __ movptr(k_RInfo, Address(k_RInfo, objArrayKlass::element_klass_offset())); 1858 // perform the fast part of the checking logic 1859 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, NULL); 1860 // call out-of-line instance of __ check_klass_subtype_slow_path(...): 1861 __ push(klass_RInfo); 1862 __ push(k_RInfo); 1863 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id))); 1864 __ pop(klass_RInfo); 1865 __ pop(k_RInfo); 1866 // result is a boolean 1867 __ cmpl(k_RInfo, 0); 1868 __ jcc(Assembler::equal, *failure_target); 1869 // fall through to the success case 1870 1871 if (op->should_profile()) { 1872 Register mdo = klass_RInfo, recv = k_RInfo; 1873 __ bind(profile_cast_success); 1874 __ movoop(mdo, md->constant_encoding()); 1875 __ load_klass(recv, value); 1876 Label update_done; 1877 type_profile_helper(mdo, md, data, recv, &done); 1878 __ jmpb(done); 1879 1880 __ bind(profile_cast_failure); 1881 __ movoop(mdo, md->constant_encoding()); 1882 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset())); 1883 __ subptr(counter_addr, DataLayout::counter_increment); 1884 __ jmp(*stub->entry()); 1885 } 1886 1887 __ bind(done); 1888 } else 1889 if (code == lir_checkcast) { 1890 Register obj = op->object()->as_register(); 1891 Register dst = op->result_opr()->as_register(); 1892 Label success; 1893 emit_typecheck_helper(op, &success, op->stub()->entry(), &success); 1894 __ bind(success); 1895 if (dst != obj) { 1896 __ mov(dst, obj); 1897 } 1898 } else 1899 if (code == lir_instanceof) { 1900 Register obj = op->object()->as_register(); 1901 Register dst = op->result_opr()->as_register(); 1902 Label success, failure, done; 1903 emit_typecheck_helper(op, &success, &failure, &failure); 1904 __ bind(failure); 1905 __ xorptr(dst, dst); 1906 __ jmpb(done); 1907 __ bind(success); 1908 __ movptr(dst, 1); 1909 __ bind(done); 1910 } else { 1911 ShouldNotReachHere(); 1912 } 1913 1914 } 1915 1916 1917 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) { 1918 if (LP64_ONLY(false &&) op->code() == lir_cas_long && VM_Version::supports_cx8()) { 1919 assert(op->cmp_value()->as_register_lo() == rax, "wrong register"); 1920 assert(op->cmp_value()->as_register_hi() == rdx, "wrong register"); 1921 assert(op->new_value()->as_register_lo() == rbx, "wrong register"); 1922 assert(op->new_value()->as_register_hi() == rcx, "wrong register"); 1923 Register addr = op->addr()->as_register(); 1924 if (os::is_MP()) { 1925 __ lock(); 1926 } 1927 NOT_LP64(__ cmpxchg8(Address(addr, 0))); 1928 1929 } else if (op->code() == lir_cas_int || op->code() == lir_cas_obj ) { 1930 NOT_LP64(assert(op->addr()->is_single_cpu(), "must be single");) 1931 Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo()); 1932 Register newval = op->new_value()->as_register(); 1933 Register cmpval = op->cmp_value()->as_register(); 1934 assert(cmpval == rax, "wrong register"); 1935 assert(newval != NULL, "new val must be register"); 1936 assert(cmpval != newval, "cmp and new values must be in different registers"); 1937 assert(cmpval != addr, "cmp and addr must be in different registers"); 1938 assert(newval != addr, "new value and addr must be in different registers"); 1939 1940 if ( op->code() == lir_cas_obj) { 1941 #ifdef _LP64 1942 if (UseCompressedOops) { 1943 __ encode_heap_oop(cmpval); 1944 __ mov(rscratch1, newval); 1945 __ encode_heap_oop(rscratch1); 1946 if (os::is_MP()) { 1947 __ lock(); 1948 } 1949 // cmpval (rax) is implicitly used by this instruction 1950 __ cmpxchgl(rscratch1, Address(addr, 0)); 1951 } else 1952 #endif 1953 { 1954 if (os::is_MP()) { 1955 __ lock(); 1956 } 1957 __ cmpxchgptr(newval, Address(addr, 0)); 1958 } 1959 } else { 1960 assert(op->code() == lir_cas_int, "lir_cas_int expected"); 1961 if (os::is_MP()) { 1962 __ lock(); 1963 } 1964 __ cmpxchgl(newval, Address(addr, 0)); 1965 } 1966 #ifdef _LP64 1967 } else if (op->code() == lir_cas_long) { 1968 Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo()); 1969 Register newval = op->new_value()->as_register_lo(); 1970 Register cmpval = op->cmp_value()->as_register_lo(); 1971 assert(cmpval == rax, "wrong register"); 1972 assert(newval != NULL, "new val must be register"); 1973 assert(cmpval != newval, "cmp and new values must be in different registers"); 1974 assert(cmpval != addr, "cmp and addr must be in different registers"); 1975 assert(newval != addr, "new value and addr must be in different registers"); 1976 if (os::is_MP()) { 1977 __ lock(); 1978 } 1979 __ cmpxchgq(newval, Address(addr, 0)); 1980 #endif // _LP64 1981 } else { 1982 Unimplemented(); 1983 } 1984 } 1985 1986 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type) { 1987 Assembler::Condition acond, ncond; 1988 switch (condition) { 1989 case lir_cond_equal: acond = Assembler::equal; ncond = Assembler::notEqual; break; 1990 case lir_cond_notEqual: acond = Assembler::notEqual; ncond = Assembler::equal; break; 1991 case lir_cond_less: acond = Assembler::less; ncond = Assembler::greaterEqual; break; 1992 case lir_cond_lessEqual: acond = Assembler::lessEqual; ncond = Assembler::greater; break; 1993 case lir_cond_greaterEqual: acond = Assembler::greaterEqual; ncond = Assembler::less; break; 1994 case lir_cond_greater: acond = Assembler::greater; ncond = Assembler::lessEqual; break; 1995 case lir_cond_belowEqual: acond = Assembler::belowEqual; ncond = Assembler::above; break; 1996 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; ncond = Assembler::below; break; 1997 default: ShouldNotReachHere(); 1998 } 1999 2000 if (opr1->is_cpu_register()) { 2001 reg2reg(opr1, result); 2002 } else if (opr1->is_stack()) { 2003 stack2reg(opr1, result, result->type()); 2004 } else if (opr1->is_constant()) { 2005 const2reg(opr1, result, lir_patch_none, NULL); 2006 } else { 2007 ShouldNotReachHere(); 2008 } 2009 2010 if (VM_Version::supports_cmov() && !opr2->is_constant()) { 2011 // optimized version that does not require a branch 2012 if (opr2->is_single_cpu()) { 2013 assert(opr2->cpu_regnr() != result->cpu_regnr(), "opr2 already overwritten by previous move"); 2014 __ cmov(ncond, result->as_register(), opr2->as_register()); 2015 } else if (opr2->is_double_cpu()) { 2016 assert(opr2->cpu_regnrLo() != result->cpu_regnrLo() && opr2->cpu_regnrLo() != result->cpu_regnrHi(), "opr2 already overwritten by previous move"); 2017 assert(opr2->cpu_regnrHi() != result->cpu_regnrLo() && opr2->cpu_regnrHi() != result->cpu_regnrHi(), "opr2 already overwritten by previous move"); 2018 __ cmovptr(ncond, result->as_register_lo(), opr2->as_register_lo()); 2019 NOT_LP64(__ cmovptr(ncond, result->as_register_hi(), opr2->as_register_hi());) 2020 } else if (opr2->is_single_stack()) { 2021 __ cmovl(ncond, result->as_register(), frame_map()->address_for_slot(opr2->single_stack_ix())); 2022 } else if (opr2->is_double_stack()) { 2023 __ cmovptr(ncond, result->as_register_lo(), frame_map()->address_for_slot(opr2->double_stack_ix(), lo_word_offset_in_bytes)); 2024 NOT_LP64(__ cmovptr(ncond, result->as_register_hi(), frame_map()->address_for_slot(opr2->double_stack_ix(), hi_word_offset_in_bytes));) 2025 } else { 2026 ShouldNotReachHere(); 2027 } 2028 2029 } else { 2030 Label skip; 2031 __ jcc (acond, skip); 2032 if (opr2->is_cpu_register()) { 2033 reg2reg(opr2, result); 2034 } else if (opr2->is_stack()) { 2035 stack2reg(opr2, result, result->type()); 2036 } else if (opr2->is_constant()) { 2037 const2reg(opr2, result, lir_patch_none, NULL); 2038 } else { 2039 ShouldNotReachHere(); 2040 } 2041 __ bind(skip); 2042 } 2043 } 2044 2045 2046 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info, bool pop_fpu_stack) { 2047 assert(info == NULL, "should never be used, idiv/irem and ldiv/lrem not handled by this method"); 2048 2049 if (left->is_single_cpu()) { 2050 assert(left == dest, "left and dest must be equal"); 2051 Register lreg = left->as_register(); 2052 2053 if (right->is_single_cpu()) { 2054 // cpu register - cpu register 2055 Register rreg = right->as_register(); 2056 switch (code) { 2057 case lir_add: __ addl (lreg, rreg); break; 2058 case lir_sub: __ subl (lreg, rreg); break; 2059 case lir_mul: __ imull(lreg, rreg); break; 2060 default: ShouldNotReachHere(); 2061 } 2062 2063 } else if (right->is_stack()) { 2064 // cpu register - stack 2065 Address raddr = frame_map()->address_for_slot(right->single_stack_ix()); 2066 switch (code) { 2067 case lir_add: __ addl(lreg, raddr); break; 2068 case lir_sub: __ subl(lreg, raddr); break; 2069 default: ShouldNotReachHere(); 2070 } 2071 2072 } else if (right->is_constant()) { 2073 // cpu register - constant 2074 jint c = right->as_constant_ptr()->as_jint(); 2075 switch (code) { 2076 case lir_add: { 2077 __ incrementl(lreg, c); 2078 break; 2079 } 2080 case lir_sub: { 2081 __ decrementl(lreg, c); 2082 break; 2083 } 2084 default: ShouldNotReachHere(); 2085 } 2086 2087 } else { 2088 ShouldNotReachHere(); 2089 } 2090 2091 } else if (left->is_double_cpu()) { 2092 assert(left == dest, "left and dest must be equal"); 2093 Register lreg_lo = left->as_register_lo(); 2094 Register lreg_hi = left->as_register_hi(); 2095 2096 if (right->is_double_cpu()) { 2097 // cpu register - cpu register 2098 Register rreg_lo = right->as_register_lo(); 2099 Register rreg_hi = right->as_register_hi(); 2100 NOT_LP64(assert_different_registers(lreg_lo, lreg_hi, rreg_lo, rreg_hi)); 2101 LP64_ONLY(assert_different_registers(lreg_lo, rreg_lo)); 2102 switch (code) { 2103 case lir_add: 2104 __ addptr(lreg_lo, rreg_lo); 2105 NOT_LP64(__ adcl(lreg_hi, rreg_hi)); 2106 break; 2107 case lir_sub: 2108 __ subptr(lreg_lo, rreg_lo); 2109 NOT_LP64(__ sbbl(lreg_hi, rreg_hi)); 2110 break; 2111 case lir_mul: 2112 #ifdef _LP64 2113 __ imulq(lreg_lo, rreg_lo); 2114 #else 2115 assert(lreg_lo == rax && lreg_hi == rdx, "must be"); 2116 __ imull(lreg_hi, rreg_lo); 2117 __ imull(rreg_hi, lreg_lo); 2118 __ addl (rreg_hi, lreg_hi); 2119 __ mull (rreg_lo); 2120 __ addl (lreg_hi, rreg_hi); 2121 #endif // _LP64 2122 break; 2123 default: 2124 ShouldNotReachHere(); 2125 } 2126 2127 } else if (right->is_constant()) { 2128 // cpu register - constant 2129 #ifdef _LP64 2130 jlong c = right->as_constant_ptr()->as_jlong_bits(); 2131 __ movptr(r10, (intptr_t) c); 2132 switch (code) { 2133 case lir_add: 2134 __ addptr(lreg_lo, r10); 2135 break; 2136 case lir_sub: 2137 __ subptr(lreg_lo, r10); 2138 break; 2139 default: 2140 ShouldNotReachHere(); 2141 } 2142 #else 2143 jint c_lo = right->as_constant_ptr()->as_jint_lo(); 2144 jint c_hi = right->as_constant_ptr()->as_jint_hi(); 2145 switch (code) { 2146 case lir_add: 2147 __ addptr(lreg_lo, c_lo); 2148 __ adcl(lreg_hi, c_hi); 2149 break; 2150 case lir_sub: 2151 __ subptr(lreg_lo, c_lo); 2152 __ sbbl(lreg_hi, c_hi); 2153 break; 2154 default: 2155 ShouldNotReachHere(); 2156 } 2157 #endif // _LP64 2158 2159 } else { 2160 ShouldNotReachHere(); 2161 } 2162 2163 } else if (left->is_single_xmm()) { 2164 assert(left == dest, "left and dest must be equal"); 2165 XMMRegister lreg = left->as_xmm_float_reg(); 2166 2167 if (right->is_single_xmm()) { 2168 XMMRegister rreg = right->as_xmm_float_reg(); 2169 switch (code) { 2170 case lir_add: __ addss(lreg, rreg); break; 2171 case lir_sub: __ subss(lreg, rreg); break; 2172 case lir_mul_strictfp: // fall through 2173 case lir_mul: __ mulss(lreg, rreg); break; 2174 case lir_div_strictfp: // fall through 2175 case lir_div: __ divss(lreg, rreg); break; 2176 default: ShouldNotReachHere(); 2177 } 2178 } else { 2179 Address raddr; 2180 if (right->is_single_stack()) { 2181 raddr = frame_map()->address_for_slot(right->single_stack_ix()); 2182 } else if (right->is_constant()) { 2183 // hack for now 2184 raddr = __ as_Address(InternalAddress(float_constant(right->as_jfloat()))); 2185 } else { 2186 ShouldNotReachHere(); 2187 } 2188 switch (code) { 2189 case lir_add: __ addss(lreg, raddr); break; 2190 case lir_sub: __ subss(lreg, raddr); break; 2191 case lir_mul_strictfp: // fall through 2192 case lir_mul: __ mulss(lreg, raddr); break; 2193 case lir_div_strictfp: // fall through 2194 case lir_div: __ divss(lreg, raddr); break; 2195 default: ShouldNotReachHere(); 2196 } 2197 } 2198 2199 } else if (left->is_double_xmm()) { 2200 assert(left == dest, "left and dest must be equal"); 2201 2202 XMMRegister lreg = left->as_xmm_double_reg(); 2203 if (right->is_double_xmm()) { 2204 XMMRegister rreg = right->as_xmm_double_reg(); 2205 switch (code) { 2206 case lir_add: __ addsd(lreg, rreg); break; 2207 case lir_sub: __ subsd(lreg, rreg); break; 2208 case lir_mul_strictfp: // fall through 2209 case lir_mul: __ mulsd(lreg, rreg); break; 2210 case lir_div_strictfp: // fall through 2211 case lir_div: __ divsd(lreg, rreg); break; 2212 default: ShouldNotReachHere(); 2213 } 2214 } else { 2215 Address raddr; 2216 if (right->is_double_stack()) { 2217 raddr = frame_map()->address_for_slot(right->double_stack_ix()); 2218 } else if (right->is_constant()) { 2219 // hack for now 2220 raddr = __ as_Address(InternalAddress(double_constant(right->as_jdouble()))); 2221 } else { 2222 ShouldNotReachHere(); 2223 } 2224 switch (code) { 2225 case lir_add: __ addsd(lreg, raddr); break; 2226 case lir_sub: __ subsd(lreg, raddr); break; 2227 case lir_mul_strictfp: // fall through 2228 case lir_mul: __ mulsd(lreg, raddr); break; 2229 case lir_div_strictfp: // fall through 2230 case lir_div: __ divsd(lreg, raddr); break; 2231 default: ShouldNotReachHere(); 2232 } 2233 } 2234 2235 } else if (left->is_single_fpu()) { 2236 assert(dest->is_single_fpu(), "fpu stack allocation required"); 2237 2238 if (right->is_single_fpu()) { 2239 arith_fpu_implementation(code, left->fpu_regnr(), right->fpu_regnr(), dest->fpu_regnr(), pop_fpu_stack); 2240 2241 } else { 2242 assert(left->fpu_regnr() == 0, "left must be on TOS"); 2243 assert(dest->fpu_regnr() == 0, "dest must be on TOS"); 2244 2245 Address raddr; 2246 if (right->is_single_stack()) { 2247 raddr = frame_map()->address_for_slot(right->single_stack_ix()); 2248 } else if (right->is_constant()) { 2249 address const_addr = float_constant(right->as_jfloat()); 2250 assert(const_addr != NULL, "incorrect float/double constant maintainance"); 2251 // hack for now 2252 raddr = __ as_Address(InternalAddress(const_addr)); 2253 } else { 2254 ShouldNotReachHere(); 2255 } 2256 2257 switch (code) { 2258 case lir_add: __ fadd_s(raddr); break; 2259 case lir_sub: __ fsub_s(raddr); break; 2260 case lir_mul_strictfp: // fall through 2261 case lir_mul: __ fmul_s(raddr); break; 2262 case lir_div_strictfp: // fall through 2263 case lir_div: __ fdiv_s(raddr); break; 2264 default: ShouldNotReachHere(); 2265 } 2266 } 2267 2268 } else if (left->is_double_fpu()) { 2269 assert(dest->is_double_fpu(), "fpu stack allocation required"); 2270 2271 if (code == lir_mul_strictfp || code == lir_div_strictfp) { 2272 // Double values require special handling for strictfp mul/div on x86 2273 __ fld_x(ExternalAddress(StubRoutines::addr_fpu_subnormal_bias1())); 2274 __ fmulp(left->fpu_regnrLo() + 1); 2275 } 2276 2277 if (right->is_double_fpu()) { 2278 arith_fpu_implementation(code, left->fpu_regnrLo(), right->fpu_regnrLo(), dest->fpu_regnrLo(), pop_fpu_stack); 2279 2280 } else { 2281 assert(left->fpu_regnrLo() == 0, "left must be on TOS"); 2282 assert(dest->fpu_regnrLo() == 0, "dest must be on TOS"); 2283 2284 Address raddr; 2285 if (right->is_double_stack()) { 2286 raddr = frame_map()->address_for_slot(right->double_stack_ix()); 2287 } else if (right->is_constant()) { 2288 // hack for now 2289 raddr = __ as_Address(InternalAddress(double_constant(right->as_jdouble()))); 2290 } else { 2291 ShouldNotReachHere(); 2292 } 2293 2294 switch (code) { 2295 case lir_add: __ fadd_d(raddr); break; 2296 case lir_sub: __ fsub_d(raddr); break; 2297 case lir_mul_strictfp: // fall through 2298 case lir_mul: __ fmul_d(raddr); break; 2299 case lir_div_strictfp: // fall through 2300 case lir_div: __ fdiv_d(raddr); break; 2301 default: ShouldNotReachHere(); 2302 } 2303 } 2304 2305 if (code == lir_mul_strictfp || code == lir_div_strictfp) { 2306 // Double values require special handling for strictfp mul/div on x86 2307 __ fld_x(ExternalAddress(StubRoutines::addr_fpu_subnormal_bias2())); 2308 __ fmulp(dest->fpu_regnrLo() + 1); 2309 } 2310 2311 } else if (left->is_single_stack() || left->is_address()) { 2312 assert(left == dest, "left and dest must be equal"); 2313 2314 Address laddr; 2315 if (left->is_single_stack()) { 2316 laddr = frame_map()->address_for_slot(left->single_stack_ix()); 2317 } else if (left->is_address()) { 2318 laddr = as_Address(left->as_address_ptr()); 2319 } else { 2320 ShouldNotReachHere(); 2321 } 2322 2323 if (right->is_single_cpu()) { 2324 Register rreg = right->as_register(); 2325 switch (code) { 2326 case lir_add: __ addl(laddr, rreg); break; 2327 case lir_sub: __ subl(laddr, rreg); break; 2328 default: ShouldNotReachHere(); 2329 } 2330 } else if (right->is_constant()) { 2331 jint c = right->as_constant_ptr()->as_jint(); 2332 switch (code) { 2333 case lir_add: { 2334 __ incrementl(laddr, c); 2335 break; 2336 } 2337 case lir_sub: { 2338 __ decrementl(laddr, c); 2339 break; 2340 } 2341 default: ShouldNotReachHere(); 2342 } 2343 } else { 2344 ShouldNotReachHere(); 2345 } 2346 2347 } else { 2348 ShouldNotReachHere(); 2349 } 2350 } 2351 2352 void LIR_Assembler::arith_fpu_implementation(LIR_Code code, int left_index, int right_index, int dest_index, bool pop_fpu_stack) { 2353 assert(pop_fpu_stack || (left_index == dest_index || right_index == dest_index), "invalid LIR"); 2354 assert(!pop_fpu_stack || (left_index - 1 == dest_index || right_index - 1 == dest_index), "invalid LIR"); 2355 assert(left_index == 0 || right_index == 0, "either must be on top of stack"); 2356 2357 bool left_is_tos = (left_index == 0); 2358 bool dest_is_tos = (dest_index == 0); 2359 int non_tos_index = (left_is_tos ? right_index : left_index); 2360 2361 switch (code) { 2362 case lir_add: 2363 if (pop_fpu_stack) __ faddp(non_tos_index); 2364 else if (dest_is_tos) __ fadd (non_tos_index); 2365 else __ fadda(non_tos_index); 2366 break; 2367 2368 case lir_sub: 2369 if (left_is_tos) { 2370 if (pop_fpu_stack) __ fsubrp(non_tos_index); 2371 else if (dest_is_tos) __ fsub (non_tos_index); 2372 else __ fsubra(non_tos_index); 2373 } else { 2374 if (pop_fpu_stack) __ fsubp (non_tos_index); 2375 else if (dest_is_tos) __ fsubr (non_tos_index); 2376 else __ fsuba (non_tos_index); 2377 } 2378 break; 2379 2380 case lir_mul_strictfp: // fall through 2381 case lir_mul: 2382 if (pop_fpu_stack) __ fmulp(non_tos_index); 2383 else if (dest_is_tos) __ fmul (non_tos_index); 2384 else __ fmula(non_tos_index); 2385 break; 2386 2387 case lir_div_strictfp: // fall through 2388 case lir_div: 2389 if (left_is_tos) { 2390 if (pop_fpu_stack) __ fdivrp(non_tos_index); 2391 else if (dest_is_tos) __ fdiv (non_tos_index); 2392 else __ fdivra(non_tos_index); 2393 } else { 2394 if (pop_fpu_stack) __ fdivp (non_tos_index); 2395 else if (dest_is_tos) __ fdivr (non_tos_index); 2396 else __ fdiva (non_tos_index); 2397 } 2398 break; 2399 2400 case lir_rem: 2401 assert(left_is_tos && dest_is_tos && right_index == 1, "must be guaranteed by FPU stack allocation"); 2402 __ fremr(noreg); 2403 break; 2404 2405 default: 2406 ShouldNotReachHere(); 2407 } 2408 } 2409 2410 2411 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr unused, LIR_Opr dest, LIR_Op* op) { 2412 if (value->is_double_xmm()) { 2413 switch(code) { 2414 case lir_abs : 2415 { 2416 if (dest->as_xmm_double_reg() != value->as_xmm_double_reg()) { 2417 __ movdbl(dest->as_xmm_double_reg(), value->as_xmm_double_reg()); 2418 } 2419 __ andpd(dest->as_xmm_double_reg(), 2420 ExternalAddress((address)double_signmask_pool)); 2421 } 2422 break; 2423 2424 case lir_sqrt: __ sqrtsd(dest->as_xmm_double_reg(), value->as_xmm_double_reg()); break; 2425 // all other intrinsics are not available in the SSE instruction set, so FPU is used 2426 default : ShouldNotReachHere(); 2427 } 2428 2429 } else if (value->is_double_fpu()) { 2430 assert(value->fpu_regnrLo() == 0 && dest->fpu_regnrLo() == 0, "both must be on TOS"); 2431 switch(code) { 2432 case lir_log : __ flog() ; break; 2433 case lir_log10 : __ flog10() ; break; 2434 case lir_abs : __ fabs() ; break; 2435 case lir_sqrt : __ fsqrt(); break; 2436 case lir_sin : 2437 // Should consider not saving rbx, if not necessary 2438 __ trigfunc('s', op->as_Op2()->fpu_stack_size()); 2439 break; 2440 case lir_cos : 2441 // Should consider not saving rbx, if not necessary 2442 assert(op->as_Op2()->fpu_stack_size() <= 6, "sin and cos need two free stack slots"); 2443 __ trigfunc('c', op->as_Op2()->fpu_stack_size()); 2444 break; 2445 case lir_tan : 2446 // Should consider not saving rbx, if not necessary 2447 __ trigfunc('t', op->as_Op2()->fpu_stack_size()); 2448 break; 2449 default : ShouldNotReachHere(); 2450 } 2451 } else { 2452 Unimplemented(); 2453 } 2454 } 2455 2456 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst) { 2457 // assert(left->destroys_register(), "check"); 2458 if (left->is_single_cpu()) { 2459 Register reg = left->as_register(); 2460 if (right->is_constant()) { 2461 int val = right->as_constant_ptr()->as_jint(); 2462 switch (code) { 2463 case lir_logic_and: __ andl (reg, val); break; 2464 case lir_logic_or: __ orl (reg, val); break; 2465 case lir_logic_xor: __ xorl (reg, val); break; 2466 default: ShouldNotReachHere(); 2467 } 2468 } else if (right->is_stack()) { 2469 // added support for stack operands 2470 Address raddr = frame_map()->address_for_slot(right->single_stack_ix()); 2471 switch (code) { 2472 case lir_logic_and: __ andl (reg, raddr); break; 2473 case lir_logic_or: __ orl (reg, raddr); break; 2474 case lir_logic_xor: __ xorl (reg, raddr); break; 2475 default: ShouldNotReachHere(); 2476 } 2477 } else { 2478 Register rright = right->as_register(); 2479 switch (code) { 2480 case lir_logic_and: __ andptr (reg, rright); break; 2481 case lir_logic_or : __ orptr (reg, rright); break; 2482 case lir_logic_xor: __ xorptr (reg, rright); break; 2483 default: ShouldNotReachHere(); 2484 } 2485 } 2486 move_regs(reg, dst->as_register()); 2487 } else { 2488 Register l_lo = left->as_register_lo(); 2489 Register l_hi = left->as_register_hi(); 2490 if (right->is_constant()) { 2491 #ifdef _LP64 2492 __ mov64(rscratch1, right->as_constant_ptr()->as_jlong()); 2493 switch (code) { 2494 case lir_logic_and: 2495 __ andq(l_lo, rscratch1); 2496 break; 2497 case lir_logic_or: 2498 __ orq(l_lo, rscratch1); 2499 break; 2500 case lir_logic_xor: 2501 __ xorq(l_lo, rscratch1); 2502 break; 2503 default: ShouldNotReachHere(); 2504 } 2505 #else 2506 int r_lo = right->as_constant_ptr()->as_jint_lo(); 2507 int r_hi = right->as_constant_ptr()->as_jint_hi(); 2508 switch (code) { 2509 case lir_logic_and: 2510 __ andl(l_lo, r_lo); 2511 __ andl(l_hi, r_hi); 2512 break; 2513 case lir_logic_or: 2514 __ orl(l_lo, r_lo); 2515 __ orl(l_hi, r_hi); 2516 break; 2517 case lir_logic_xor: 2518 __ xorl(l_lo, r_lo); 2519 __ xorl(l_hi, r_hi); 2520 break; 2521 default: ShouldNotReachHere(); 2522 } 2523 #endif // _LP64 2524 } else { 2525 #ifdef _LP64 2526 Register r_lo; 2527 if (right->type() == T_OBJECT || right->type() == T_ARRAY) { 2528 r_lo = right->as_register(); 2529 } else { 2530 r_lo = right->as_register_lo(); 2531 } 2532 #else 2533 Register r_lo = right->as_register_lo(); 2534 Register r_hi = right->as_register_hi(); 2535 assert(l_lo != r_hi, "overwriting registers"); 2536 #endif 2537 switch (code) { 2538 case lir_logic_and: 2539 __ andptr(l_lo, r_lo); 2540 NOT_LP64(__ andptr(l_hi, r_hi);) 2541 break; 2542 case lir_logic_or: 2543 __ orptr(l_lo, r_lo); 2544 NOT_LP64(__ orptr(l_hi, r_hi);) 2545 break; 2546 case lir_logic_xor: 2547 __ xorptr(l_lo, r_lo); 2548 NOT_LP64(__ xorptr(l_hi, r_hi);) 2549 break; 2550 default: ShouldNotReachHere(); 2551 } 2552 } 2553 2554 Register dst_lo = dst->as_register_lo(); 2555 Register dst_hi = dst->as_register_hi(); 2556 2557 #ifdef _LP64 2558 move_regs(l_lo, dst_lo); 2559 #else 2560 if (dst_lo == l_hi) { 2561 assert(dst_hi != l_lo, "overwriting registers"); 2562 move_regs(l_hi, dst_hi); 2563 move_regs(l_lo, dst_lo); 2564 } else { 2565 assert(dst_lo != l_hi, "overwriting registers"); 2566 move_regs(l_lo, dst_lo); 2567 move_regs(l_hi, dst_hi); 2568 } 2569 #endif // _LP64 2570 } 2571 } 2572 2573 2574 // we assume that rax, and rdx can be overwritten 2575 void LIR_Assembler::arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr temp, LIR_Opr result, CodeEmitInfo* info) { 2576 2577 assert(left->is_single_cpu(), "left must be register"); 2578 assert(right->is_single_cpu() || right->is_constant(), "right must be register or constant"); 2579 assert(result->is_single_cpu(), "result must be register"); 2580 2581 // assert(left->destroys_register(), "check"); 2582 // assert(right->destroys_register(), "check"); 2583 2584 Register lreg = left->as_register(); 2585 Register dreg = result->as_register(); 2586 2587 if (right->is_constant()) { 2588 int divisor = right->as_constant_ptr()->as_jint(); 2589 assert(divisor > 0 && is_power_of_2(divisor), "must be"); 2590 if (code == lir_idiv) { 2591 assert(lreg == rax, "must be rax,"); 2592 assert(temp->as_register() == rdx, "tmp register must be rdx"); 2593 __ cdql(); // sign extend into rdx:rax 2594 if (divisor == 2) { 2595 __ subl(lreg, rdx); 2596 } else { 2597 __ andl(rdx, divisor - 1); 2598 __ addl(lreg, rdx); 2599 } 2600 __ sarl(lreg, log2_intptr(divisor)); 2601 move_regs(lreg, dreg); 2602 } else if (code == lir_irem) { 2603 Label done; 2604 __ mov(dreg, lreg); 2605 __ andl(dreg, 0x80000000 | (divisor - 1)); 2606 __ jcc(Assembler::positive, done); 2607 __ decrement(dreg); 2608 __ orl(dreg, ~(divisor - 1)); 2609 __ increment(dreg); 2610 __ bind(done); 2611 } else { 2612 ShouldNotReachHere(); 2613 } 2614 } else { 2615 Register rreg = right->as_register(); 2616 assert(lreg == rax, "left register must be rax,"); 2617 assert(rreg != rdx, "right register must not be rdx"); 2618 assert(temp->as_register() == rdx, "tmp register must be rdx"); 2619 2620 move_regs(lreg, rax); 2621 2622 int idivl_offset = __ corrected_idivl(rreg); 2623 add_debug_info_for_div0(idivl_offset, info); 2624 if (code == lir_irem) { 2625 move_regs(rdx, dreg); // result is in rdx 2626 } else { 2627 move_regs(rax, dreg); 2628 } 2629 } 2630 } 2631 2632 2633 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) { 2634 if (opr1->is_single_cpu()) { 2635 Register reg1 = opr1->as_register(); 2636 if (opr2->is_single_cpu()) { 2637 // cpu register - cpu register 2638 if (opr1->type() == T_OBJECT || opr1->type() == T_ARRAY) { 2639 __ cmpptr(reg1, opr2->as_register()); 2640 } else { 2641 assert(opr2->type() != T_OBJECT && opr2->type() != T_ARRAY, "cmp int, oop?"); 2642 __ cmpl(reg1, opr2->as_register()); 2643 } 2644 } else if (opr2->is_stack()) { 2645 // cpu register - stack 2646 if (opr1->type() == T_OBJECT || opr1->type() == T_ARRAY) { 2647 __ cmpptr(reg1, frame_map()->address_for_slot(opr2->single_stack_ix())); 2648 } else { 2649 __ cmpl(reg1, frame_map()->address_for_slot(opr2->single_stack_ix())); 2650 } 2651 } else if (opr2->is_constant()) { 2652 // cpu register - constant 2653 LIR_Const* c = opr2->as_constant_ptr(); 2654 if (c->type() == T_INT) { 2655 __ cmpl(reg1, c->as_jint()); 2656 } else if (c->type() == T_OBJECT || c->type() == T_ARRAY) { 2657 // In 64bit oops are single register 2658 jobject o = c->as_jobject(); 2659 if (o == NULL) { 2660 __ cmpptr(reg1, (int32_t)NULL_WORD); 2661 } else { 2662 #ifdef _LP64 2663 __ movoop(rscratch1, o); 2664 __ cmpptr(reg1, rscratch1); 2665 #else 2666 __ cmpoop(reg1, c->as_jobject()); 2667 #endif // _LP64 2668 } 2669 } else { 2670 fatal(err_msg("unexpected type: %s", basictype_to_str(c->type()))); 2671 } 2672 // cpu register - address 2673 } else if (opr2->is_address()) { 2674 if (op->info() != NULL) { 2675 add_debug_info_for_null_check_here(op->info()); 2676 } 2677 __ cmpl(reg1, as_Address(opr2->as_address_ptr())); 2678 } else { 2679 ShouldNotReachHere(); 2680 } 2681 2682 } else if(opr1->is_double_cpu()) { 2683 Register xlo = opr1->as_register_lo(); 2684 Register xhi = opr1->as_register_hi(); 2685 if (opr2->is_double_cpu()) { 2686 #ifdef _LP64 2687 __ cmpptr(xlo, opr2->as_register_lo()); 2688 #else 2689 // cpu register - cpu register 2690 Register ylo = opr2->as_register_lo(); 2691 Register yhi = opr2->as_register_hi(); 2692 __ subl(xlo, ylo); 2693 __ sbbl(xhi, yhi); 2694 if (condition == lir_cond_equal || condition == lir_cond_notEqual) { 2695 __ orl(xhi, xlo); 2696 } 2697 #endif // _LP64 2698 } else if (opr2->is_constant()) { 2699 // cpu register - constant 0 2700 assert(opr2->as_jlong() == (jlong)0, "only handles zero"); 2701 #ifdef _LP64 2702 __ cmpptr(xlo, (int32_t)opr2->as_jlong()); 2703 #else 2704 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "only handles equals case"); 2705 __ orl(xhi, xlo); 2706 #endif // _LP64 2707 } else { 2708 ShouldNotReachHere(); 2709 } 2710 2711 } else if (opr1->is_single_xmm()) { 2712 XMMRegister reg1 = opr1->as_xmm_float_reg(); 2713 if (opr2->is_single_xmm()) { 2714 // xmm register - xmm register 2715 __ ucomiss(reg1, opr2->as_xmm_float_reg()); 2716 } else if (opr2->is_stack()) { 2717 // xmm register - stack 2718 __ ucomiss(reg1, frame_map()->address_for_slot(opr2->single_stack_ix())); 2719 } else if (opr2->is_constant()) { 2720 // xmm register - constant 2721 __ ucomiss(reg1, InternalAddress(float_constant(opr2->as_jfloat()))); 2722 } else if (opr2->is_address()) { 2723 // xmm register - address 2724 if (op->info() != NULL) { 2725 add_debug_info_for_null_check_here(op->info()); 2726 } 2727 __ ucomiss(reg1, as_Address(opr2->as_address_ptr())); 2728 } else { 2729 ShouldNotReachHere(); 2730 } 2731 2732 } else if (opr1->is_double_xmm()) { 2733 XMMRegister reg1 = opr1->as_xmm_double_reg(); 2734 if (opr2->is_double_xmm()) { 2735 // xmm register - xmm register 2736 __ ucomisd(reg1, opr2->as_xmm_double_reg()); 2737 } else if (opr2->is_stack()) { 2738 // xmm register - stack 2739 __ ucomisd(reg1, frame_map()->address_for_slot(opr2->double_stack_ix())); 2740 } else if (opr2->is_constant()) { 2741 // xmm register - constant 2742 __ ucomisd(reg1, InternalAddress(double_constant(opr2->as_jdouble()))); 2743 } else if (opr2->is_address()) { 2744 // xmm register - address 2745 if (op->info() != NULL) { 2746 add_debug_info_for_null_check_here(op->info()); 2747 } 2748 __ ucomisd(reg1, as_Address(opr2->pointer()->as_address())); 2749 } else { 2750 ShouldNotReachHere(); 2751 } 2752 2753 } else if(opr1->is_single_fpu() || opr1->is_double_fpu()) { 2754 assert(opr1->is_fpu_register() && opr1->fpu() == 0, "currently left-hand side must be on TOS (relax this restriction)"); 2755 assert(opr2->is_fpu_register(), "both must be registers"); 2756 __ fcmp(noreg, opr2->fpu(), op->fpu_pop_count() > 0, op->fpu_pop_count() > 1); 2757 2758 } else if (opr1->is_address() && opr2->is_constant()) { 2759 LIR_Const* c = opr2->as_constant_ptr(); 2760 #ifdef _LP64 2761 if (c->type() == T_OBJECT || c->type() == T_ARRAY) { 2762 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "need to reverse"); 2763 __ movoop(rscratch1, c->as_jobject()); 2764 } 2765 #endif // LP64 2766 if (op->info() != NULL) { 2767 add_debug_info_for_null_check_here(op->info()); 2768 } 2769 // special case: address - constant 2770 LIR_Address* addr = opr1->as_address_ptr(); 2771 if (c->type() == T_INT) { 2772 __ cmpl(as_Address(addr), c->as_jint()); 2773 } else if (c->type() == T_OBJECT || c->type() == T_ARRAY) { 2774 #ifdef _LP64 2775 // %%% Make this explode if addr isn't reachable until we figure out a 2776 // better strategy by giving noreg as the temp for as_Address 2777 __ cmpptr(rscratch1, as_Address(addr, noreg)); 2778 #else 2779 __ cmpoop(as_Address(addr), c->as_jobject()); 2780 #endif // _LP64 2781 } else { 2782 ShouldNotReachHere(); 2783 } 2784 2785 } else { 2786 ShouldNotReachHere(); 2787 } 2788 } 2789 2790 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op) { 2791 if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) { 2792 if (left->is_single_xmm()) { 2793 assert(right->is_single_xmm(), "must match"); 2794 __ cmpss2int(left->as_xmm_float_reg(), right->as_xmm_float_reg(), dst->as_register(), code == lir_ucmp_fd2i); 2795 } else if (left->is_double_xmm()) { 2796 assert(right->is_double_xmm(), "must match"); 2797 __ cmpsd2int(left->as_xmm_double_reg(), right->as_xmm_double_reg(), dst->as_register(), code == lir_ucmp_fd2i); 2798 2799 } else { 2800 assert(left->is_single_fpu() || left->is_double_fpu(), "must be"); 2801 assert(right->is_single_fpu() || right->is_double_fpu(), "must match"); 2802 2803 assert(left->fpu() == 0, "left must be on TOS"); 2804 __ fcmp2int(dst->as_register(), code == lir_ucmp_fd2i, right->fpu(), 2805 op->fpu_pop_count() > 0, op->fpu_pop_count() > 1); 2806 } 2807 } else { 2808 assert(code == lir_cmp_l2i, "check"); 2809 #ifdef _LP64 2810 Label done; 2811 Register dest = dst->as_register(); 2812 __ cmpptr(left->as_register_lo(), right->as_register_lo()); 2813 __ movl(dest, -1); 2814 __ jccb(Assembler::less, done); 2815 __ set_byte_if_not_zero(dest); 2816 __ movzbl(dest, dest); 2817 __ bind(done); 2818 #else 2819 __ lcmp2int(left->as_register_hi(), 2820 left->as_register_lo(), 2821 right->as_register_hi(), 2822 right->as_register_lo()); 2823 move_regs(left->as_register_hi(), dst->as_register()); 2824 #endif // _LP64 2825 } 2826 } 2827 2828 2829 void LIR_Assembler::align_call(LIR_Code code) { 2830 if (os::is_MP()) { 2831 // make sure that the displacement word of the call ends up word aligned 2832 int offset = __ offset(); 2833 switch (code) { 2834 case lir_static_call: 2835 case lir_optvirtual_call: 2836 case lir_dynamic_call: 2837 offset += NativeCall::displacement_offset; 2838 break; 2839 case lir_icvirtual_call: 2840 offset += NativeCall::displacement_offset + NativeMovConstReg::instruction_size; 2841 break; 2842 case lir_virtual_call: // currently, sparc-specific for niagara 2843 default: ShouldNotReachHere(); 2844 } 2845 while (offset++ % BytesPerWord != 0) { 2846 __ nop(); 2847 } 2848 } 2849 } 2850 2851 2852 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) { 2853 assert(!os::is_MP() || (__ offset() + NativeCall::displacement_offset) % BytesPerWord == 0, 2854 "must be aligned"); 2855 __ call(AddressLiteral(op->addr(), rtype)); 2856 add_call_info(code_offset(), op->info()); 2857 } 2858 2859 2860 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) { 2861 RelocationHolder rh = virtual_call_Relocation::spec(pc()); 2862 __ movoop(IC_Klass, (jobject)Universe::non_oop_word()); 2863 assert(!os::is_MP() || 2864 (__ offset() + NativeCall::displacement_offset) % BytesPerWord == 0, 2865 "must be aligned"); 2866 __ call(AddressLiteral(op->addr(), rh)); 2867 add_call_info(code_offset(), op->info()); 2868 } 2869 2870 2871 /* Currently, vtable-dispatch is only enabled for sparc platforms */ 2872 void LIR_Assembler::vtable_call(LIR_OpJavaCall* op) { 2873 ShouldNotReachHere(); 2874 } 2875 2876 2877 void LIR_Assembler::emit_static_call_stub() { 2878 address call_pc = __ pc(); 2879 address stub = __ start_a_stub(call_stub_size); 2880 if (stub == NULL) { 2881 bailout("static call stub overflow"); 2882 return; 2883 } 2884 2885 int start = __ offset(); 2886 if (os::is_MP()) { 2887 // make sure that the displacement word of the call ends up word aligned 2888 int offset = __ offset() + NativeMovConstReg::instruction_size + NativeCall::displacement_offset; 2889 while (offset++ % BytesPerWord != 0) { 2890 __ nop(); 2891 } 2892 } 2893 __ relocate(static_stub_Relocation::spec(call_pc)); 2894 __ movoop(rbx, (jobject)NULL); 2895 // must be set to -1 at code generation time 2896 assert(!os::is_MP() || ((__ offset() + 1) % BytesPerWord) == 0, "must be aligned on MP"); 2897 // On 64bit this will die since it will take a movq & jmp, must be only a jmp 2898 __ jump(RuntimeAddress(__ pc())); 2899 2900 assert(__ offset() - start <= call_stub_size, "stub too big"); 2901 __ end_a_stub(); 2902 } 2903 2904 2905 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) { 2906 assert(exceptionOop->as_register() == rax, "must match"); 2907 assert(exceptionPC->as_register() == rdx, "must match"); 2908 2909 // exception object is not added to oop map by LinearScan 2910 // (LinearScan assumes that no oops are in fixed registers) 2911 info->add_register_oop(exceptionOop); 2912 Runtime1::StubID unwind_id; 2913 2914 // get current pc information 2915 // pc is only needed if the method has an exception handler, the unwind code does not need it. 2916 int pc_for_athrow_offset = __ offset(); 2917 InternalAddress pc_for_athrow(__ pc()); 2918 __ lea(exceptionPC->as_register(), pc_for_athrow); 2919 add_call_info(pc_for_athrow_offset, info); // for exception handler 2920 2921 __ verify_not_null_oop(rax); 2922 // search an exception handler (rax: exception oop, rdx: throwing pc) 2923 if (compilation()->has_fpu_code()) { 2924 unwind_id = Runtime1::handle_exception_id; 2925 } else { 2926 unwind_id = Runtime1::handle_exception_nofpu_id; 2927 } 2928 __ call(RuntimeAddress(Runtime1::entry_for(unwind_id))); 2929 2930 // enough room for two byte trap 2931 __ nop(); 2932 } 2933 2934 2935 void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) { 2936 assert(exceptionOop->as_register() == rax, "must match"); 2937 2938 __ jmp(_unwind_handler_entry); 2939 } 2940 2941 2942 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) { 2943 2944 // optimized version for linear scan: 2945 // * count must be already in ECX (guaranteed by LinearScan) 2946 // * left and dest must be equal 2947 // * tmp must be unused 2948 assert(count->as_register() == SHIFT_count, "count must be in ECX"); 2949 assert(left == dest, "left and dest must be equal"); 2950 assert(tmp->is_illegal(), "wasting a register if tmp is allocated"); 2951 2952 if (left->is_single_cpu()) { 2953 Register value = left->as_register(); 2954 assert(value != SHIFT_count, "left cannot be ECX"); 2955 2956 switch (code) { 2957 case lir_shl: __ shll(value); break; 2958 case lir_shr: __ sarl(value); break; 2959 case lir_ushr: __ shrl(value); break; 2960 default: ShouldNotReachHere(); 2961 } 2962 } else if (left->is_double_cpu()) { 2963 Register lo = left->as_register_lo(); 2964 Register hi = left->as_register_hi(); 2965 assert(lo != SHIFT_count && hi != SHIFT_count, "left cannot be ECX"); 2966 #ifdef _LP64 2967 switch (code) { 2968 case lir_shl: __ shlptr(lo); break; 2969 case lir_shr: __ sarptr(lo); break; 2970 case lir_ushr: __ shrptr(lo); break; 2971 default: ShouldNotReachHere(); 2972 } 2973 #else 2974 2975 switch (code) { 2976 case lir_shl: __ lshl(hi, lo); break; 2977 case lir_shr: __ lshr(hi, lo, true); break; 2978 case lir_ushr: __ lshr(hi, lo, false); break; 2979 default: ShouldNotReachHere(); 2980 } 2981 #endif // LP64 2982 } else { 2983 ShouldNotReachHere(); 2984 } 2985 } 2986 2987 2988 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) { 2989 if (dest->is_single_cpu()) { 2990 // first move left into dest so that left is not destroyed by the shift 2991 Register value = dest->as_register(); 2992 count = count & 0x1F; // Java spec 2993 2994 move_regs(left->as_register(), value); 2995 switch (code) { 2996 case lir_shl: __ shll(value, count); break; 2997 case lir_shr: __ sarl(value, count); break; 2998 case lir_ushr: __ shrl(value, count); break; 2999 default: ShouldNotReachHere(); 3000 } 3001 } else if (dest->is_double_cpu()) { 3002 #ifndef _LP64 3003 Unimplemented(); 3004 #else 3005 // first move left into dest so that left is not destroyed by the shift 3006 Register value = dest->as_register_lo(); 3007 count = count & 0x1F; // Java spec 3008 3009 move_regs(left->as_register_lo(), value); 3010 switch (code) { 3011 case lir_shl: __ shlptr(value, count); break; 3012 case lir_shr: __ sarptr(value, count); break; 3013 case lir_ushr: __ shrptr(value, count); break; 3014 default: ShouldNotReachHere(); 3015 } 3016 #endif // _LP64 3017 } else { 3018 ShouldNotReachHere(); 3019 } 3020 } 3021 3022 3023 void LIR_Assembler::store_parameter(Register r, int offset_from_rsp_in_words) { 3024 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp"); 3025 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord; 3026 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset"); 3027 __ movptr (Address(rsp, offset_from_rsp_in_bytes), r); 3028 } 3029 3030 3031 void LIR_Assembler::store_parameter(jint c, int offset_from_rsp_in_words) { 3032 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp"); 3033 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord; 3034 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset"); 3035 __ movptr (Address(rsp, offset_from_rsp_in_bytes), c); 3036 } 3037 3038 3039 void LIR_Assembler::store_parameter(jobject o, int offset_from_rsp_in_words) { 3040 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp"); 3041 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord; 3042 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset"); 3043 __ movoop (Address(rsp, offset_from_rsp_in_bytes), o); 3044 } 3045 3046 3047 // This code replaces a call to arraycopy; no exception may 3048 // be thrown in this code, they must be thrown in the System.arraycopy 3049 // activation frame; we could save some checks if this would not be the case 3050 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) { 3051 ciArrayKlass* default_type = op->expected_type(); 3052 Register src = op->src()->as_register(); 3053 Register dst = op->dst()->as_register(); 3054 Register src_pos = op->src_pos()->as_register(); 3055 Register dst_pos = op->dst_pos()->as_register(); 3056 Register length = op->length()->as_register(); 3057 Register tmp = op->tmp()->as_register(); 3058 3059 CodeStub* stub = op->stub(); 3060 int flags = op->flags(); 3061 BasicType basic_type = default_type != NULL ? default_type->element_type()->basic_type() : T_ILLEGAL; 3062 if (basic_type == T_ARRAY) basic_type = T_OBJECT; 3063 3064 // if we don't know anything, just go through the generic arraycopy 3065 if (default_type == NULL) { 3066 Label done; 3067 // save outgoing arguments on stack in case call to System.arraycopy is needed 3068 // HACK ALERT. This code used to push the parameters in a hardwired fashion 3069 // for interpreter calling conventions. Now we have to do it in new style conventions. 3070 // For the moment until C1 gets the new register allocator I just force all the 3071 // args to the right place (except the register args) and then on the back side 3072 // reload the register args properly if we go slow path. Yuck 3073 3074 // These are proper for the calling convention 3075 store_parameter(length, 2); 3076 store_parameter(dst_pos, 1); 3077 store_parameter(dst, 0); 3078 3079 // these are just temporary placements until we need to reload 3080 store_parameter(src_pos, 3); 3081 store_parameter(src, 4); 3082 NOT_LP64(assert(src == rcx && src_pos == rdx, "mismatch in calling convention");) 3083 3084 address C_entry = CAST_FROM_FN_PTR(address, Runtime1::arraycopy); 3085 3086 address copyfunc_addr = StubRoutines::generic_arraycopy(); 3087 3088 // pass arguments: may push as this is not a safepoint; SP must be fix at each safepoint 3089 #ifdef _LP64 3090 // The arguments are in java calling convention so we can trivially shift them to C 3091 // convention 3092 assert_different_registers(c_rarg0, j_rarg1, j_rarg2, j_rarg3, j_rarg4); 3093 __ mov(c_rarg0, j_rarg0); 3094 assert_different_registers(c_rarg1, j_rarg2, j_rarg3, j_rarg4); 3095 __ mov(c_rarg1, j_rarg1); 3096 assert_different_registers(c_rarg2, j_rarg3, j_rarg4); 3097 __ mov(c_rarg2, j_rarg2); 3098 assert_different_registers(c_rarg3, j_rarg4); 3099 __ mov(c_rarg3, j_rarg3); 3100 #ifdef _WIN64 3101 // Allocate abi space for args but be sure to keep stack aligned 3102 __ subptr(rsp, 6*wordSize); 3103 store_parameter(j_rarg4, 4); 3104 if (copyfunc_addr == NULL) { // Use C version if stub was not generated 3105 __ call(RuntimeAddress(C_entry)); 3106 } else { 3107 #ifndef PRODUCT 3108 if (PrintC1Statistics) { 3109 __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt)); 3110 } 3111 #endif 3112 __ call(RuntimeAddress(copyfunc_addr)); 3113 } 3114 __ addptr(rsp, 6*wordSize); 3115 #else 3116 __ mov(c_rarg4, j_rarg4); 3117 if (copyfunc_addr == NULL) { // Use C version if stub was not generated 3118 __ call(RuntimeAddress(C_entry)); 3119 } else { 3120 #ifndef PRODUCT 3121 if (PrintC1Statistics) { 3122 __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt)); 3123 } 3124 #endif 3125 __ call(RuntimeAddress(copyfunc_addr)); 3126 } 3127 #endif // _WIN64 3128 #else 3129 __ push(length); 3130 __ push(dst_pos); 3131 __ push(dst); 3132 __ push(src_pos); 3133 __ push(src); 3134 3135 if (copyfunc_addr == NULL) { // Use C version if stub was not generated 3136 __ call_VM_leaf(C_entry, 5); // removes pushed parameter from the stack 3137 } else { 3138 #ifndef PRODUCT 3139 if (PrintC1Statistics) { 3140 __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt)); 3141 } 3142 #endif 3143 __ call_VM_leaf(copyfunc_addr, 5); // removes pushed parameter from the stack 3144 } 3145 3146 #endif // _LP64 3147 3148 __ cmpl(rax, 0); 3149 __ jcc(Assembler::equal, *stub->continuation()); 3150 3151 if (copyfunc_addr != NULL) { 3152 __ mov(tmp, rax); 3153 __ xorl(tmp, -1); 3154 } 3155 3156 // Reload values from the stack so they are where the stub 3157 // expects them. 3158 __ movptr (dst, Address(rsp, 0*BytesPerWord)); 3159 __ movptr (dst_pos, Address(rsp, 1*BytesPerWord)); 3160 __ movptr (length, Address(rsp, 2*BytesPerWord)); 3161 __ movptr (src_pos, Address(rsp, 3*BytesPerWord)); 3162 __ movptr (src, Address(rsp, 4*BytesPerWord)); 3163 3164 if (copyfunc_addr != NULL) { 3165 __ subl(length, tmp); 3166 __ addl(src_pos, tmp); 3167 __ addl(dst_pos, tmp); 3168 } 3169 __ jmp(*stub->entry()); 3170 3171 __ bind(*stub->continuation()); 3172 return; 3173 } 3174 3175 assert(default_type != NULL && default_type->is_array_klass() && default_type->is_loaded(), "must be true at this point"); 3176 3177 int elem_size = type2aelembytes(basic_type); 3178 int shift_amount; 3179 Address::ScaleFactor scale; 3180 3181 switch (elem_size) { 3182 case 1 : 3183 shift_amount = 0; 3184 scale = Address::times_1; 3185 break; 3186 case 2 : 3187 shift_amount = 1; 3188 scale = Address::times_2; 3189 break; 3190 case 4 : 3191 shift_amount = 2; 3192 scale = Address::times_4; 3193 break; 3194 case 8 : 3195 shift_amount = 3; 3196 scale = Address::times_8; 3197 break; 3198 default: 3199 ShouldNotReachHere(); 3200 } 3201 3202 Address src_length_addr = Address(src, arrayOopDesc::length_offset_in_bytes()); 3203 Address dst_length_addr = Address(dst, arrayOopDesc::length_offset_in_bytes()); 3204 Address src_klass_addr = Address(src, oopDesc::klass_offset_in_bytes()); 3205 Address dst_klass_addr = Address(dst, oopDesc::klass_offset_in_bytes()); 3206 3207 // length and pos's are all sign extended at this point on 64bit 3208 3209 // test for NULL 3210 if (flags & LIR_OpArrayCopy::src_null_check) { 3211 __ testptr(src, src); 3212 __ jcc(Assembler::zero, *stub->entry()); 3213 } 3214 if (flags & LIR_OpArrayCopy::dst_null_check) { 3215 __ testptr(dst, dst); 3216 __ jcc(Assembler::zero, *stub->entry()); 3217 } 3218 3219 // check if negative 3220 if (flags & LIR_OpArrayCopy::src_pos_positive_check) { 3221 __ testl(src_pos, src_pos); 3222 __ jcc(Assembler::less, *stub->entry()); 3223 } 3224 if (flags & LIR_OpArrayCopy::dst_pos_positive_check) { 3225 __ testl(dst_pos, dst_pos); 3226 __ jcc(Assembler::less, *stub->entry()); 3227 } 3228 3229 if (flags & LIR_OpArrayCopy::src_range_check) { 3230 __ lea(tmp, Address(src_pos, length, Address::times_1, 0)); 3231 __ cmpl(tmp, src_length_addr); 3232 __ jcc(Assembler::above, *stub->entry()); 3233 } 3234 if (flags & LIR_OpArrayCopy::dst_range_check) { 3235 __ lea(tmp, Address(dst_pos, length, Address::times_1, 0)); 3236 __ cmpl(tmp, dst_length_addr); 3237 __ jcc(Assembler::above, *stub->entry()); 3238 } 3239 3240 if (flags & LIR_OpArrayCopy::length_positive_check) { 3241 __ testl(length, length); 3242 __ jcc(Assembler::less, *stub->entry()); 3243 __ jcc(Assembler::zero, *stub->continuation()); 3244 } 3245 3246 #ifdef _LP64 3247 __ movl2ptr(src_pos, src_pos); //higher 32bits must be null 3248 __ movl2ptr(dst_pos, dst_pos); //higher 32bits must be null 3249 #endif 3250 3251 if (flags & LIR_OpArrayCopy::type_check) { 3252 // We don't know the array types are compatible 3253 if (basic_type != T_OBJECT) { 3254 // Simple test for basic type arrays 3255 if (UseCompressedOops) { 3256 __ movl(tmp, src_klass_addr); 3257 __ cmpl(tmp, dst_klass_addr); 3258 } else { 3259 __ movptr(tmp, src_klass_addr); 3260 __ cmpptr(tmp, dst_klass_addr); 3261 } 3262 __ jcc(Assembler::notEqual, *stub->entry()); 3263 } else { 3264 // For object arrays, if src is a sub class of dst then we can 3265 // safely do the copy. 3266 Label cont, slow; 3267 3268 __ push(src); 3269 __ push(dst); 3270 3271 __ load_klass(src, src); 3272 __ load_klass(dst, dst); 3273 3274 __ check_klass_subtype_fast_path(src, dst, tmp, &cont, &slow, NULL); 3275 3276 __ push(src); 3277 __ push(dst); 3278 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id))); 3279 __ pop(dst); 3280 __ pop(src); 3281 3282 __ cmpl(src, 0); 3283 __ jcc(Assembler::notEqual, cont); 3284 3285 __ bind(slow); 3286 __ pop(dst); 3287 __ pop(src); 3288 3289 address copyfunc_addr = StubRoutines::checkcast_arraycopy(); 3290 if (copyfunc_addr != NULL) { // use stub if available 3291 // src is not a sub class of dst so we have to do a 3292 // per-element check. 3293 3294 int mask = LIR_OpArrayCopy::src_objarray|LIR_OpArrayCopy::dst_objarray; 3295 if ((flags & mask) != mask) { 3296 // Check that at least both of them object arrays. 3297 assert(flags & mask, "one of the two should be known to be an object array"); 3298 3299 if (!(flags & LIR_OpArrayCopy::src_objarray)) { 3300 __ load_klass(tmp, src); 3301 } else if (!(flags & LIR_OpArrayCopy::dst_objarray)) { 3302 __ load_klass(tmp, dst); 3303 } 3304 int lh_offset = in_bytes(Klass::layout_helper_offset()); 3305 Address klass_lh_addr(tmp, lh_offset); 3306 jint objArray_lh = Klass::array_layout_helper(T_OBJECT); 3307 __ cmpl(klass_lh_addr, objArray_lh); 3308 __ jcc(Assembler::notEqual, *stub->entry()); 3309 } 3310 3311 // Spill because stubs can use any register they like and it's 3312 // easier to restore just those that we care about. 3313 store_parameter(dst, 0); 3314 store_parameter(dst_pos, 1); 3315 store_parameter(length, 2); 3316 store_parameter(src_pos, 3); 3317 store_parameter(src, 4); 3318 3319 #ifndef _LP64 3320 __ movptr(tmp, dst_klass_addr); 3321 __ movptr(tmp, Address(tmp, objArrayKlass::element_klass_offset())); 3322 __ push(tmp); 3323 __ movl(tmp, Address(tmp, Klass::super_check_offset_offset())); 3324 __ push(tmp); 3325 __ push(length); 3326 __ lea(tmp, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); 3327 __ push(tmp); 3328 __ lea(tmp, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); 3329 __ push(tmp); 3330 3331 __ call_VM_leaf(copyfunc_addr, 5); 3332 #else 3333 __ movl2ptr(length, length); //higher 32bits must be null 3334 3335 __ lea(c_rarg0, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); 3336 assert_different_registers(c_rarg0, dst, dst_pos, length); 3337 __ lea(c_rarg1, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); 3338 assert_different_registers(c_rarg1, dst, length); 3339 3340 __ mov(c_rarg2, length); 3341 assert_different_registers(c_rarg2, dst); 3342 3343 #ifdef _WIN64 3344 // Allocate abi space for args but be sure to keep stack aligned 3345 __ subptr(rsp, 6*wordSize); 3346 __ load_klass(c_rarg3, dst); 3347 __ movptr(c_rarg3, Address(c_rarg3, objArrayKlass::element_klass_offset())); 3348 store_parameter(c_rarg3, 4); 3349 __ movl(c_rarg3, Address(c_rarg3, Klass::super_check_offset_offset())); 3350 __ call(RuntimeAddress(copyfunc_addr)); 3351 __ addptr(rsp, 6*wordSize); 3352 #else 3353 __ load_klass(c_rarg4, dst); 3354 __ movptr(c_rarg4, Address(c_rarg4, objArrayKlass::element_klass_offset())); 3355 __ movl(c_rarg3, Address(c_rarg4, Klass::super_check_offset_offset())); 3356 __ call(RuntimeAddress(copyfunc_addr)); 3357 #endif 3358 3359 #endif 3360 3361 #ifndef PRODUCT 3362 if (PrintC1Statistics) { 3363 Label failed; 3364 __ testl(rax, rax); 3365 __ jcc(Assembler::notZero, failed); 3366 __ incrementl(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_cnt)); 3367 __ bind(failed); 3368 } 3369 #endif 3370 3371 __ testl(rax, rax); 3372 __ jcc(Assembler::zero, *stub->continuation()); 3373 3374 #ifndef PRODUCT 3375 if (PrintC1Statistics) { 3376 __ incrementl(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_attempt_cnt)); 3377 } 3378 #endif 3379 3380 __ mov(tmp, rax); 3381 3382 __ xorl(tmp, -1); 3383 3384 // Restore previously spilled arguments 3385 __ movptr (dst, Address(rsp, 0*BytesPerWord)); 3386 __ movptr (dst_pos, Address(rsp, 1*BytesPerWord)); 3387 __ movptr (length, Address(rsp, 2*BytesPerWord)); 3388 __ movptr (src_pos, Address(rsp, 3*BytesPerWord)); 3389 __ movptr (src, Address(rsp, 4*BytesPerWord)); 3390 3391 3392 __ subl(length, tmp); 3393 __ addl(src_pos, tmp); 3394 __ addl(dst_pos, tmp); 3395 } 3396 3397 __ jmp(*stub->entry()); 3398 3399 __ bind(cont); 3400 __ pop(dst); 3401 __ pop(src); 3402 } 3403 } 3404 3405 #ifdef ASSERT 3406 if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) { 3407 // Sanity check the known type with the incoming class. For the 3408 // primitive case the types must match exactly with src.klass and 3409 // dst.klass each exactly matching the default type. For the 3410 // object array case, if no type check is needed then either the 3411 // dst type is exactly the expected type and the src type is a 3412 // subtype which we can't check or src is the same array as dst 3413 // but not necessarily exactly of type default_type. 3414 Label known_ok, halt; 3415 __ movoop(tmp, default_type->constant_encoding()); 3416 #ifdef _LP64 3417 if (UseCompressedOops) { 3418 __ encode_heap_oop(tmp); 3419 } 3420 #endif 3421 3422 if (basic_type != T_OBJECT) { 3423 3424 if (UseCompressedOops) __ cmpl(tmp, dst_klass_addr); 3425 else __ cmpptr(tmp, dst_klass_addr); 3426 __ jcc(Assembler::notEqual, halt); 3427 if (UseCompressedOops) __ cmpl(tmp, src_klass_addr); 3428 else __ cmpptr(tmp, src_klass_addr); 3429 __ jcc(Assembler::equal, known_ok); 3430 } else { 3431 if (UseCompressedOops) __ cmpl(tmp, dst_klass_addr); 3432 else __ cmpptr(tmp, dst_klass_addr); 3433 __ jcc(Assembler::equal, known_ok); 3434 __ cmpptr(src, dst); 3435 __ jcc(Assembler::equal, known_ok); 3436 } 3437 __ bind(halt); 3438 __ stop("incorrect type information in arraycopy"); 3439 __ bind(known_ok); 3440 } 3441 #endif 3442 3443 #ifndef PRODUCT 3444 if (PrintC1Statistics) { 3445 __ incrementl(ExternalAddress(Runtime1::arraycopy_count_address(basic_type))); 3446 } 3447 #endif 3448 3449 #ifdef _LP64 3450 assert_different_registers(c_rarg0, dst, dst_pos, length); 3451 __ lea(c_rarg0, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); 3452 assert_different_registers(c_rarg1, length); 3453 __ lea(c_rarg1, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); 3454 __ mov(c_rarg2, length); 3455 3456 #else 3457 __ lea(tmp, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); 3458 store_parameter(tmp, 0); 3459 __ lea(tmp, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); 3460 store_parameter(tmp, 1); 3461 store_parameter(length, 2); 3462 #endif // _LP64 3463 3464 bool disjoint = (flags & LIR_OpArrayCopy::overlapping) == 0; 3465 bool aligned = (flags & LIR_OpArrayCopy::unaligned) == 0; 3466 const char *name; 3467 address entry = StubRoutines::select_arraycopy_function(basic_type, aligned, disjoint, name, false); 3468 __ call_VM_leaf(entry, 0); 3469 3470 __ bind(*stub->continuation()); 3471 } 3472 3473 3474 void LIR_Assembler::emit_lock(LIR_OpLock* op) { 3475 Register obj = op->obj_opr()->as_register(); // may not be an oop 3476 Register hdr = op->hdr_opr()->as_register(); 3477 Register lock = op->lock_opr()->as_register(); 3478 if (!UseFastLocking) { 3479 __ jmp(*op->stub()->entry()); 3480 } else if (op->code() == lir_lock) { 3481 Register scratch = noreg; 3482 if (UseBiasedLocking) { 3483 scratch = op->scratch_opr()->as_register(); 3484 } 3485 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header"); 3486 // add debug info for NullPointerException only if one is possible 3487 int null_check_offset = __ lock_object(hdr, obj, lock, scratch, *op->stub()->entry()); 3488 if (op->info() != NULL) { 3489 add_debug_info_for_null_check(null_check_offset, op->info()); 3490 } 3491 // done 3492 } else if (op->code() == lir_unlock) { 3493 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header"); 3494 __ unlock_object(hdr, obj, lock, *op->stub()->entry()); 3495 } else { 3496 Unimplemented(); 3497 } 3498 __ bind(*op->stub()->continuation()); 3499 } 3500 3501 3502 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) { 3503 ciMethod* method = op->profiled_method(); 3504 int bci = op->profiled_bci(); 3505 3506 // Update counter for all call types 3507 ciMethodData* md = method->method_data_or_null(); 3508 assert(md != NULL, "Sanity"); 3509 ciProfileData* data = md->bci_to_data(bci); 3510 assert(data->is_CounterData(), "need CounterData for calls"); 3511 assert(op->mdo()->is_single_cpu(), "mdo must be allocated"); 3512 Register mdo = op->mdo()->as_register(); 3513 __ movoop(mdo, md->constant_encoding()); 3514 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset())); 3515 Bytecodes::Code bc = method->java_code_at_bci(bci); 3516 // Perform additional virtual call profiling for invokevirtual and 3517 // invokeinterface bytecodes 3518 if ((bc == Bytecodes::_invokevirtual || bc == Bytecodes::_invokeinterface) && 3519 C1ProfileVirtualCalls) { 3520 assert(op->recv()->is_single_cpu(), "recv must be allocated"); 3521 Register recv = op->recv()->as_register(); 3522 assert_different_registers(mdo, recv); 3523 assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls"); 3524 ciKlass* known_klass = op->known_holder(); 3525 if (C1OptimizeVirtualCallProfiling && known_klass != NULL) { 3526 // We know the type that will be seen at this call site; we can 3527 // statically update the methodDataOop rather than needing to do 3528 // dynamic tests on the receiver type 3529 3530 // NOTE: we should probably put a lock around this search to 3531 // avoid collisions by concurrent compilations 3532 ciVirtualCallData* vc_data = (ciVirtualCallData*) data; 3533 uint i; 3534 for (i = 0; i < VirtualCallData::row_limit(); i++) { 3535 ciKlass* receiver = vc_data->receiver(i); 3536 if (known_klass->equals(receiver)) { 3537 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i))); 3538 __ addptr(data_addr, DataLayout::counter_increment); 3539 return; 3540 } 3541 } 3542 3543 // Receiver type not found in profile data; select an empty slot 3544 3545 // Note that this is less efficient than it should be because it 3546 // always does a write to the receiver part of the 3547 // VirtualCallData rather than just the first time 3548 for (i = 0; i < VirtualCallData::row_limit(); i++) { 3549 ciKlass* receiver = vc_data->receiver(i); 3550 if (receiver == NULL) { 3551 Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i))); 3552 __ movoop(recv_addr, known_klass->constant_encoding()); 3553 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i))); 3554 __ addptr(data_addr, DataLayout::counter_increment); 3555 return; 3556 } 3557 } 3558 } else { 3559 __ load_klass(recv, recv); 3560 Label update_done; 3561 type_profile_helper(mdo, md, data, recv, &update_done); 3562 // Receiver did not match any saved receiver and there is no empty row for it. 3563 // Increment total counter to indicate polymorphic case. 3564 __ addptr(counter_addr, DataLayout::counter_increment); 3565 3566 __ bind(update_done); 3567 } 3568 } else { 3569 // Static call 3570 __ addptr(counter_addr, DataLayout::counter_increment); 3571 } 3572 } 3573 3574 void LIR_Assembler::emit_delay(LIR_OpDelay*) { 3575 Unimplemented(); 3576 } 3577 3578 3579 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst) { 3580 __ lea(dst->as_register(), frame_map()->address_for_monitor_lock(monitor_no)); 3581 } 3582 3583 3584 void LIR_Assembler::align_backward_branch_target() { 3585 __ align(BytesPerWord); 3586 } 3587 3588 3589 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest) { 3590 if (left->is_single_cpu()) { 3591 __ negl(left->as_register()); 3592 move_regs(left->as_register(), dest->as_register()); 3593 3594 } else if (left->is_double_cpu()) { 3595 Register lo = left->as_register_lo(); 3596 #ifdef _LP64 3597 Register dst = dest->as_register_lo(); 3598 __ movptr(dst, lo); 3599 __ negptr(dst); 3600 #else 3601 Register hi = left->as_register_hi(); 3602 __ lneg(hi, lo); 3603 if (dest->as_register_lo() == hi) { 3604 assert(dest->as_register_hi() != lo, "destroying register"); 3605 move_regs(hi, dest->as_register_hi()); 3606 move_regs(lo, dest->as_register_lo()); 3607 } else { 3608 move_regs(lo, dest->as_register_lo()); 3609 move_regs(hi, dest->as_register_hi()); 3610 } 3611 #endif // _LP64 3612 3613 } else if (dest->is_single_xmm()) { 3614 if (left->as_xmm_float_reg() != dest->as_xmm_float_reg()) { 3615 __ movflt(dest->as_xmm_float_reg(), left->as_xmm_float_reg()); 3616 } 3617 __ xorps(dest->as_xmm_float_reg(), 3618 ExternalAddress((address)float_signflip_pool)); 3619 3620 } else if (dest->is_double_xmm()) { 3621 if (left->as_xmm_double_reg() != dest->as_xmm_double_reg()) { 3622 __ movdbl(dest->as_xmm_double_reg(), left->as_xmm_double_reg()); 3623 } 3624 __ xorpd(dest->as_xmm_double_reg(), 3625 ExternalAddress((address)double_signflip_pool)); 3626 3627 } else if (left->is_single_fpu() || left->is_double_fpu()) { 3628 assert(left->fpu() == 0, "arg must be on TOS"); 3629 assert(dest->fpu() == 0, "dest must be TOS"); 3630 __ fchs(); 3631 3632 } else { 3633 ShouldNotReachHere(); 3634 } 3635 } 3636 3637 3638 void LIR_Assembler::leal(LIR_Opr addr, LIR_Opr dest) { 3639 assert(addr->is_address() && dest->is_register(), "check"); 3640 Register reg; 3641 reg = dest->as_pointer_register(); 3642 __ lea(reg, as_Address(addr->as_address_ptr())); 3643 } 3644 3645 3646 3647 void LIR_Assembler::rt_call(LIR_Opr result, address dest, const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) { 3648 assert(!tmp->is_valid(), "don't need temporary"); 3649 __ call(RuntimeAddress(dest)); 3650 if (info != NULL) { 3651 add_call_info_here(info); 3652 } 3653 } 3654 3655 3656 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) { 3657 assert(type == T_LONG, "only for volatile long fields"); 3658 3659 if (info != NULL) { 3660 add_debug_info_for_null_check_here(info); 3661 } 3662 3663 if (src->is_double_xmm()) { 3664 if (dest->is_double_cpu()) { 3665 #ifdef _LP64 3666 __ movdq(dest->as_register_lo(), src->as_xmm_double_reg()); 3667 #else 3668 __ movdl(dest->as_register_lo(), src->as_xmm_double_reg()); 3669 __ psrlq(src->as_xmm_double_reg(), 32); 3670 __ movdl(dest->as_register_hi(), src->as_xmm_double_reg()); 3671 #endif // _LP64 3672 } else if (dest->is_double_stack()) { 3673 __ movdbl(frame_map()->address_for_slot(dest->double_stack_ix()), src->as_xmm_double_reg()); 3674 } else if (dest->is_address()) { 3675 __ movdbl(as_Address(dest->as_address_ptr()), src->as_xmm_double_reg()); 3676 } else { 3677 ShouldNotReachHere(); 3678 } 3679 3680 } else if (dest->is_double_xmm()) { 3681 if (src->is_double_stack()) { 3682 __ movdbl(dest->as_xmm_double_reg(), frame_map()->address_for_slot(src->double_stack_ix())); 3683 } else if (src->is_address()) { 3684 __ movdbl(dest->as_xmm_double_reg(), as_Address(src->as_address_ptr())); 3685 } else { 3686 ShouldNotReachHere(); 3687 } 3688 3689 } else if (src->is_double_fpu()) { 3690 assert(src->fpu_regnrLo() == 0, "must be TOS"); 3691 if (dest->is_double_stack()) { 3692 __ fistp_d(frame_map()->address_for_slot(dest->double_stack_ix())); 3693 } else if (dest->is_address()) { 3694 __ fistp_d(as_Address(dest->as_address_ptr())); 3695 } else { 3696 ShouldNotReachHere(); 3697 } 3698 3699 } else if (dest->is_double_fpu()) { 3700 assert(dest->fpu_regnrLo() == 0, "must be TOS"); 3701 if (src->is_double_stack()) { 3702 __ fild_d(frame_map()->address_for_slot(src->double_stack_ix())); 3703 } else if (src->is_address()) { 3704 __ fild_d(as_Address(src->as_address_ptr())); 3705 } else { 3706 ShouldNotReachHere(); 3707 } 3708 } else { 3709 ShouldNotReachHere(); 3710 } 3711 } 3712 3713 3714 void LIR_Assembler::membar() { 3715 // QQQ sparc TSO uses this, 3716 __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad)); 3717 } 3718 3719 void LIR_Assembler::membar_acquire() { 3720 // No x86 machines currently require load fences 3721 // __ load_fence(); 3722 } 3723 3724 void LIR_Assembler::membar_release() { 3725 // No x86 machines currently require store fences 3726 // __ store_fence(); 3727 } 3728 3729 void LIR_Assembler::membar_loadload() { 3730 // no-op 3731 //__ membar(Assembler::Membar_mask_bits(Assembler::loadload)); 3732 } 3733 3734 void LIR_Assembler::membar_storestore() { 3735 // no-op 3736 //__ membar(Assembler::Membar_mask_bits(Assembler::storestore)); 3737 } 3738 3739 void LIR_Assembler::membar_loadstore() { 3740 // no-op 3741 //__ membar(Assembler::Membar_mask_bits(Assembler::loadstore)); 3742 } 3743 3744 void LIR_Assembler::membar_storeload() { 3745 __ membar(Assembler::Membar_mask_bits(Assembler::StoreLoad)); 3746 } 3747 3748 void LIR_Assembler::get_thread(LIR_Opr result_reg) { 3749 assert(result_reg->is_register(), "check"); 3750 #ifdef _LP64 3751 // __ get_thread(result_reg->as_register_lo()); 3752 __ mov(result_reg->as_register(), r15_thread); 3753 #else 3754 __ get_thread(result_reg->as_register()); 3755 #endif // _LP64 3756 } 3757 3758 3759 void LIR_Assembler::peephole(LIR_List*) { 3760 // do nothing for now 3761 } 3762 3763 3764 #undef __