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src/cpu/ppc/vm/ppc.ad

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rev 5788 : 8181420: PPC: Image conversion improvements
Reviewed-by: thartmann, simonis, mbaesken
rev 5791 : 8185716: OpenJDK 7 PPC64 port uses a different ins_encode format in ppc.ad
Summary: Use existing ins_encode format for implementing 8181420
Reviewed-by: omajid


3481   %}
3482 
3483   enc_class enc_cmpwi(flagsReg crx, iRegIsrc src1, immL16 src2) %{
3484     // TODO: PPC port $archOpcode(ppc64Opcode_cmpi);
3485     MacroAssembler _masm(&cbuf);
3486     Register Rsrc1 = reg_to_register_object($src1$$reg);
3487     int Isrc2 = $src2$$constant;
3488     ConditionRegister Rcrx = reg_to_ConditionRegister_object($crx$$reg);
3489     __ cmpwi(Rcrx, Rsrc1, Isrc2);
3490   %}
3491 
3492   enc_class enc_cmplwi(flagsReg crx, iRegIsrc src1, immL16 src2) %{
3493     // TODO: PPC port $archOpcode(ppc64Opcode_cmpli);
3494     MacroAssembler _masm(&cbuf);
3495     Register Rsrc1 = reg_to_register_object($src1$$reg);
3496     int Isrc2 = $src2$$constant;
3497     ConditionRegister Rcrx = reg_to_ConditionRegister_object($crx$$reg);
3498     __ cmplwi(Rcrx, Rsrc1, Isrc2);
3499   %}
3500 








3501   enc_class enc_btst_reg(iRegIsrc src1, iRegIsrc src2) %{
3502     // TODO: PPC port $archOpcode(ppc64Opcode_and_);
3503 
3504     MacroAssembler _masm(&cbuf);
3505     Register Rsrc1 = reg_to_register_object($src1$$reg);
3506     Register Rsrc2 = reg_to_register_object($src2$$reg);
3507     __ and_(R0, Rsrc1, Rsrc2);
3508   %}
3509 
3510   enc_class enc_slwi(iRegIdst dst, iRegIsrc src1, immI src2) %{
3511     // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm);
3512 
3513     MacroAssembler _masm(&cbuf);
3514     Register Rdst  = reg_to_register_object($dst$$reg);
3515     Register Rsrc1 = reg_to_register_object($src1$$reg);
3516     int isrc = ($src2$$constant) & 0x1f;
3517     __ slwi(Rdst, Rsrc1, isrc);
3518   %}
3519 
3520   enc_class enc_slw(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{


11336   // r0 is killed
11337   format %{ "ANDI    R0, $src1, $src2 \t// BTST int" %}
11338   size(4);
11339   ins_encode( enc_andi(R0, src1, src2) );
11340   ins_pipe(pipe_class_compare);
11341 %}
11342 
11343 instruct cmpL_reg_reg(flagsReg crx, iRegLsrc src1, iRegLsrc src2) %{
11344   match(Set crx (CmpL src1 src2));
11345   format %{ "CMPD    $crx, $src1, $src2" %}
11346   size(4);
11347   ins_encode( enc_cmpd(crx, src1, src2) );
11348   ins_pipe(pipe_class_compare);
11349 %}
11350 
11351 instruct cmpL_reg_imm16(flagsReg crx, iRegLsrc src1, immL16 con) %{
11352   match(Set crx (CmpL src1 con));
11353   format %{ "CMPDI   $crx, $src1, $con" %}
11354   size(4);
11355   ins_encode( enc_cmpdi(crx, src1, con) );

















11356   ins_pipe(pipe_class_compare);
11357 %}
11358 
11359 instruct testL_reg_reg(flagsRegCR0 cr0, iRegLsrc src1, iRegLsrc src2, immL_0 zero) %{
11360   match(Set cr0 (CmpL (AndL src1 src2) zero));
11361   // r0 is killed
11362   format %{ "AND     R0, $src1, $src2 \t// BTST long" %}
11363   size(4);
11364   ins_encode( enc_btst_reg(src1, src2) );
11365   ins_pipe(pipe_class_compare);
11366 %}
11367 
11368 instruct testL_reg_imm(flagsRegCR0 cr0, iRegLsrc src1, uimmL16 src2, immL_0 zero) %{
11369   match(Set cr0 (CmpL (AndL src1 src2) zero));
11370   // r0 is killed
11371   format %{ "ANDI    R0, $src1, $src2 \t// BTST long" %}
11372   size(4);
11373   ins_encode( enc_andi(R0, src1, src2) );
11374   ins_pipe(pipe_class_compare);
11375 %}




3481   %}
3482 
3483   enc_class enc_cmpwi(flagsReg crx, iRegIsrc src1, immL16 src2) %{
3484     // TODO: PPC port $archOpcode(ppc64Opcode_cmpi);
3485     MacroAssembler _masm(&cbuf);
3486     Register Rsrc1 = reg_to_register_object($src1$$reg);
3487     int Isrc2 = $src2$$constant;
3488     ConditionRegister Rcrx = reg_to_ConditionRegister_object($crx$$reg);
3489     __ cmpwi(Rcrx, Rsrc1, Isrc2);
3490   %}
3491 
3492   enc_class enc_cmplwi(flagsReg crx, iRegIsrc src1, immL16 src2) %{
3493     // TODO: PPC port $archOpcode(ppc64Opcode_cmpli);
3494     MacroAssembler _masm(&cbuf);
3495     Register Rsrc1 = reg_to_register_object($src1$$reg);
3496     int Isrc2 = $src2$$constant;
3497     ConditionRegister Rcrx = reg_to_ConditionRegister_object($crx$$reg);
3498     __ cmplwi(Rcrx, Rsrc1, Isrc2);
3499   %}
3500 
3501   enc_class enc_cmpldi(flagsReg crx, iRegIsrc src1, uimmL16 src2) %{
3502     // TODO: PPC port $archOpcode(ppc64Opcode_cmpli);
3503     MacroAssembler _masm(&cbuf);
3504     Register Rsrc1 = reg_to_register_object($src1$$reg);
3505     ConditionRegister Rcrx = reg_to_ConditionRegister_object($crx$$reg);
3506     __ cmpldi(Rcrx, Rsrc1, $src2$$constant);
3507   %}
3508   
3509   enc_class enc_btst_reg(iRegIsrc src1, iRegIsrc src2) %{
3510     // TODO: PPC port $archOpcode(ppc64Opcode_and_);
3511 
3512     MacroAssembler _masm(&cbuf);
3513     Register Rsrc1 = reg_to_register_object($src1$$reg);
3514     Register Rsrc2 = reg_to_register_object($src2$$reg);
3515     __ and_(R0, Rsrc1, Rsrc2);
3516   %}
3517 
3518   enc_class enc_slwi(iRegIdst dst, iRegIsrc src1, immI src2) %{
3519     // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm);
3520 
3521     MacroAssembler _masm(&cbuf);
3522     Register Rdst  = reg_to_register_object($dst$$reg);
3523     Register Rsrc1 = reg_to_register_object($src1$$reg);
3524     int isrc = ($src2$$constant) & 0x1f;
3525     __ slwi(Rdst, Rsrc1, isrc);
3526   %}
3527 
3528   enc_class enc_slw(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{


11344   // r0 is killed
11345   format %{ "ANDI    R0, $src1, $src2 \t// BTST int" %}
11346   size(4);
11347   ins_encode( enc_andi(R0, src1, src2) );
11348   ins_pipe(pipe_class_compare);
11349 %}
11350 
11351 instruct cmpL_reg_reg(flagsReg crx, iRegLsrc src1, iRegLsrc src2) %{
11352   match(Set crx (CmpL src1 src2));
11353   format %{ "CMPD    $crx, $src1, $src2" %}
11354   size(4);
11355   ins_encode( enc_cmpd(crx, src1, src2) );
11356   ins_pipe(pipe_class_compare);
11357 %}
11358 
11359 instruct cmpL_reg_imm16(flagsReg crx, iRegLsrc src1, immL16 con) %{
11360   match(Set crx (CmpL src1 con));
11361   format %{ "CMPDI   $crx, $src1, $con" %}
11362   size(4);
11363   ins_encode( enc_cmpdi(crx, src1, con) );
11364   ins_pipe(pipe_class_compare);
11365 %}
11366 
11367 // Added CmpUL for LoopPredicate.
11368 instruct cmpUL_reg_reg(flagsReg crx, iRegLsrc src1, iRegLsrc src2) %{
11369   match(Set crx (CmpUL src1 src2));
11370   format %{ "CMPLD   $crx, $src1, $src2" %}
11371   size(4);
11372   ins_encode( enc_cmpld(crx, src1, src2) );
11373   ins_pipe(pipe_class_compare);
11374 %}
11375 
11376 instruct cmpUL_reg_imm16(flagsReg crx, iRegLsrc src1, uimmL16 src2) %{
11377   match(Set crx (CmpUL src1 src2));
11378   format %{ "CMPLDI  $crx, $src1, $src2" %}
11379   size(4);
11380   ins_encode( enc_cmpldi(crx, src1, src2) );
11381   ins_pipe(pipe_class_compare);
11382 %}
11383 
11384 instruct testL_reg_reg(flagsRegCR0 cr0, iRegLsrc src1, iRegLsrc src2, immL_0 zero) %{
11385   match(Set cr0 (CmpL (AndL src1 src2) zero));
11386   // r0 is killed
11387   format %{ "AND     R0, $src1, $src2 \t// BTST long" %}
11388   size(4);
11389   ins_encode( enc_btst_reg(src1, src2) );
11390   ins_pipe(pipe_class_compare);
11391 %}
11392 
11393 instruct testL_reg_imm(flagsRegCR0 cr0, iRegLsrc src1, uimmL16 src2, immL_0 zero) %{
11394   match(Set cr0 (CmpL (AndL src1 src2) zero));
11395   // r0 is killed
11396   format %{ "ANDI    R0, $src1, $src2 \t// BTST long" %}
11397   size(4);
11398   ins_encode( enc_andi(R0, src1, src2) );
11399   ins_pipe(pipe_class_compare);
11400 %}
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