1 //
2 // Copyright (c) 1998, 2013, Oracle and/or its affiliates. All rights reserved.
3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 //
5 // This code is free software; you can redistribute it and/or modify it
6 // under the terms of the GNU General Public License version 2 only, as
7 // published by the Free Software Foundation.
8 //
9 // This code is distributed in the hope that it will be useful, but WITHOUT
10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 // version 2 for more details (a copy is included in the LICENSE file that
13 // accompanied this code).
14 //
15 // You should have received a copy of the GNU General Public License version
16 // 2 along with this work; if not, write to the Free Software Foundation,
17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 //
19 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 // or visit www.oracle.com if you need additional information or have any
21 // questions.
22 //
23 //
24
25 // SPARC Architecture Description File
26
27 //----------REGISTER DEFINITION BLOCK------------------------------------------
28 // This information is used by the matcher and the register allocator to
29 // describe individual registers and classes of registers within the target
30 // archtecture.
31 register %{
32 //----------Architecture Description Register Definitions----------------------
33 // General Registers
34 // "reg_def" name ( register save type, C convention save type,
35 // ideal register type, encoding, vm name );
36 // Register Save Types:
37 //
38 // NS = No-Save: The register allocator assumes that these registers
39 // can be used without saving upon entry to the method, &
40 // that they do not need to be saved at call sites.
41 //
42 // SOC = Save-On-Call: The register allocator assumes that these registers
43 // can be used without saving upon entry to the method,
44 // but that they must be saved at call sites.
45 //
46 // SOE = Save-On-Entry: The register allocator assumes that these registers
47 // must be saved before using them upon entry to the
48 // method, but they do not need to be saved at call
49 // sites.
50 //
51 // AS = Always-Save: The register allocator assumes that these registers
52 // must be saved before using them upon entry to the
53 // method, & that they must be saved at call sites.
54 //
55 // Ideal Register Type is used to determine how to save & restore a
56 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
57 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
58 //
59 // The encoding number is the actual bit-pattern placed into the opcodes.
60
61
62 // ----------------------------
63 // Integer/Long Registers
64 // ----------------------------
65
66 // Need to expose the hi/lo aspect of 64-bit registers
67 // This register set is used for both the 64-bit build and
68 // the 32-bit build with 1-register longs.
69
70 // Global Registers 0-7
71 reg_def R_G0H( NS, NS, Op_RegI,128, G0->as_VMReg()->next());
72 reg_def R_G0 ( NS, NS, Op_RegI, 0, G0->as_VMReg());
73 reg_def R_G1H(SOC, SOC, Op_RegI,129, G1->as_VMReg()->next());
74 reg_def R_G1 (SOC, SOC, Op_RegI, 1, G1->as_VMReg());
75 reg_def R_G2H( NS, NS, Op_RegI,130, G2->as_VMReg()->next());
76 reg_def R_G2 ( NS, NS, Op_RegI, 2, G2->as_VMReg());
77 reg_def R_G3H(SOC, SOC, Op_RegI,131, G3->as_VMReg()->next());
78 reg_def R_G3 (SOC, SOC, Op_RegI, 3, G3->as_VMReg());
79 reg_def R_G4H(SOC, SOC, Op_RegI,132, G4->as_VMReg()->next());
80 reg_def R_G4 (SOC, SOC, Op_RegI, 4, G4->as_VMReg());
81 reg_def R_G5H(SOC, SOC, Op_RegI,133, G5->as_VMReg()->next());
82 reg_def R_G5 (SOC, SOC, Op_RegI, 5, G5->as_VMReg());
83 reg_def R_G6H( NS, NS, Op_RegI,134, G6->as_VMReg()->next());
84 reg_def R_G6 ( NS, NS, Op_RegI, 6, G6->as_VMReg());
85 reg_def R_G7H( NS, NS, Op_RegI,135, G7->as_VMReg()->next());
86 reg_def R_G7 ( NS, NS, Op_RegI, 7, G7->as_VMReg());
87
88 // Output Registers 0-7
89 reg_def R_O0H(SOC, SOC, Op_RegI,136, O0->as_VMReg()->next());
90 reg_def R_O0 (SOC, SOC, Op_RegI, 8, O0->as_VMReg());
91 reg_def R_O1H(SOC, SOC, Op_RegI,137, O1->as_VMReg()->next());
92 reg_def R_O1 (SOC, SOC, Op_RegI, 9, O1->as_VMReg());
93 reg_def R_O2H(SOC, SOC, Op_RegI,138, O2->as_VMReg()->next());
94 reg_def R_O2 (SOC, SOC, Op_RegI, 10, O2->as_VMReg());
95 reg_def R_O3H(SOC, SOC, Op_RegI,139, O3->as_VMReg()->next());
96 reg_def R_O3 (SOC, SOC, Op_RegI, 11, O3->as_VMReg());
97 reg_def R_O4H(SOC, SOC, Op_RegI,140, O4->as_VMReg()->next());
98 reg_def R_O4 (SOC, SOC, Op_RegI, 12, O4->as_VMReg());
99 reg_def R_O5H(SOC, SOC, Op_RegI,141, O5->as_VMReg()->next());
100 reg_def R_O5 (SOC, SOC, Op_RegI, 13, O5->as_VMReg());
101 reg_def R_SPH( NS, NS, Op_RegI,142, SP->as_VMReg()->next());
102 reg_def R_SP ( NS, NS, Op_RegI, 14, SP->as_VMReg());
103 reg_def R_O7H(SOC, SOC, Op_RegI,143, O7->as_VMReg()->next());
104 reg_def R_O7 (SOC, SOC, Op_RegI, 15, O7->as_VMReg());
105
106 // Local Registers 0-7
107 reg_def R_L0H( NS, NS, Op_RegI,144, L0->as_VMReg()->next());
108 reg_def R_L0 ( NS, NS, Op_RegI, 16, L0->as_VMReg());
109 reg_def R_L1H( NS, NS, Op_RegI,145, L1->as_VMReg()->next());
110 reg_def R_L1 ( NS, NS, Op_RegI, 17, L1->as_VMReg());
111 reg_def R_L2H( NS, NS, Op_RegI,146, L2->as_VMReg()->next());
112 reg_def R_L2 ( NS, NS, Op_RegI, 18, L2->as_VMReg());
113 reg_def R_L3H( NS, NS, Op_RegI,147, L3->as_VMReg()->next());
114 reg_def R_L3 ( NS, NS, Op_RegI, 19, L3->as_VMReg());
115 reg_def R_L4H( NS, NS, Op_RegI,148, L4->as_VMReg()->next());
116 reg_def R_L4 ( NS, NS, Op_RegI, 20, L4->as_VMReg());
117 reg_def R_L5H( NS, NS, Op_RegI,149, L5->as_VMReg()->next());
118 reg_def R_L5 ( NS, NS, Op_RegI, 21, L5->as_VMReg());
119 reg_def R_L6H( NS, NS, Op_RegI,150, L6->as_VMReg()->next());
120 reg_def R_L6 ( NS, NS, Op_RegI, 22, L6->as_VMReg());
121 reg_def R_L7H( NS, NS, Op_RegI,151, L7->as_VMReg()->next());
122 reg_def R_L7 ( NS, NS, Op_RegI, 23, L7->as_VMReg());
123
124 // Input Registers 0-7
125 reg_def R_I0H( NS, NS, Op_RegI,152, I0->as_VMReg()->next());
126 reg_def R_I0 ( NS, NS, Op_RegI, 24, I0->as_VMReg());
127 reg_def R_I1H( NS, NS, Op_RegI,153, I1->as_VMReg()->next());
128 reg_def R_I1 ( NS, NS, Op_RegI, 25, I1->as_VMReg());
129 reg_def R_I2H( NS, NS, Op_RegI,154, I2->as_VMReg()->next());
130 reg_def R_I2 ( NS, NS, Op_RegI, 26, I2->as_VMReg());
131 reg_def R_I3H( NS, NS, Op_RegI,155, I3->as_VMReg()->next());
132 reg_def R_I3 ( NS, NS, Op_RegI, 27, I3->as_VMReg());
133 reg_def R_I4H( NS, NS, Op_RegI,156, I4->as_VMReg()->next());
134 reg_def R_I4 ( NS, NS, Op_RegI, 28, I4->as_VMReg());
135 reg_def R_I5H( NS, NS, Op_RegI,157, I5->as_VMReg()->next());
136 reg_def R_I5 ( NS, NS, Op_RegI, 29, I5->as_VMReg());
137 reg_def R_FPH( NS, NS, Op_RegI,158, FP->as_VMReg()->next());
138 reg_def R_FP ( NS, NS, Op_RegI, 30, FP->as_VMReg());
139 reg_def R_I7H( NS, NS, Op_RegI,159, I7->as_VMReg()->next());
140 reg_def R_I7 ( NS, NS, Op_RegI, 31, I7->as_VMReg());
141
142 // ----------------------------
143 // Float/Double Registers
144 // ----------------------------
145
146 // Float Registers
147 reg_def R_F0 ( SOC, SOC, Op_RegF, 0, F0->as_VMReg());
148 reg_def R_F1 ( SOC, SOC, Op_RegF, 1, F1->as_VMReg());
149 reg_def R_F2 ( SOC, SOC, Op_RegF, 2, F2->as_VMReg());
150 reg_def R_F3 ( SOC, SOC, Op_RegF, 3, F3->as_VMReg());
151 reg_def R_F4 ( SOC, SOC, Op_RegF, 4, F4->as_VMReg());
152 reg_def R_F5 ( SOC, SOC, Op_RegF, 5, F5->as_VMReg());
153 reg_def R_F6 ( SOC, SOC, Op_RegF, 6, F6->as_VMReg());
154 reg_def R_F7 ( SOC, SOC, Op_RegF, 7, F7->as_VMReg());
155 reg_def R_F8 ( SOC, SOC, Op_RegF, 8, F8->as_VMReg());
156 reg_def R_F9 ( SOC, SOC, Op_RegF, 9, F9->as_VMReg());
157 reg_def R_F10( SOC, SOC, Op_RegF, 10, F10->as_VMReg());
158 reg_def R_F11( SOC, SOC, Op_RegF, 11, F11->as_VMReg());
159 reg_def R_F12( SOC, SOC, Op_RegF, 12, F12->as_VMReg());
160 reg_def R_F13( SOC, SOC, Op_RegF, 13, F13->as_VMReg());
161 reg_def R_F14( SOC, SOC, Op_RegF, 14, F14->as_VMReg());
162 reg_def R_F15( SOC, SOC, Op_RegF, 15, F15->as_VMReg());
163 reg_def R_F16( SOC, SOC, Op_RegF, 16, F16->as_VMReg());
164 reg_def R_F17( SOC, SOC, Op_RegF, 17, F17->as_VMReg());
165 reg_def R_F18( SOC, SOC, Op_RegF, 18, F18->as_VMReg());
166 reg_def R_F19( SOC, SOC, Op_RegF, 19, F19->as_VMReg());
167 reg_def R_F20( SOC, SOC, Op_RegF, 20, F20->as_VMReg());
168 reg_def R_F21( SOC, SOC, Op_RegF, 21, F21->as_VMReg());
169 reg_def R_F22( SOC, SOC, Op_RegF, 22, F22->as_VMReg());
170 reg_def R_F23( SOC, SOC, Op_RegF, 23, F23->as_VMReg());
171 reg_def R_F24( SOC, SOC, Op_RegF, 24, F24->as_VMReg());
172 reg_def R_F25( SOC, SOC, Op_RegF, 25, F25->as_VMReg());
173 reg_def R_F26( SOC, SOC, Op_RegF, 26, F26->as_VMReg());
174 reg_def R_F27( SOC, SOC, Op_RegF, 27, F27->as_VMReg());
175 reg_def R_F28( SOC, SOC, Op_RegF, 28, F28->as_VMReg());
176 reg_def R_F29( SOC, SOC, Op_RegF, 29, F29->as_VMReg());
177 reg_def R_F30( SOC, SOC, Op_RegF, 30, F30->as_VMReg());
178 reg_def R_F31( SOC, SOC, Op_RegF, 31, F31->as_VMReg());
179
180 // Double Registers
181 // The rules of ADL require that double registers be defined in pairs.
182 // Each pair must be two 32-bit values, but not necessarily a pair of
183 // single float registers. In each pair, ADLC-assigned register numbers
184 // must be adjacent, with the lower number even. Finally, when the
185 // CPU stores such a register pair to memory, the word associated with
186 // the lower ADLC-assigned number must be stored to the lower address.
187
188 // These definitions specify the actual bit encodings of the sparc
189 // double fp register numbers. FloatRegisterImpl in register_sparc.hpp
190 // wants 0-63, so we have to convert every time we want to use fp regs
191 // with the macroassembler, using reg_to_DoubleFloatRegister_object().
192 // 255 is a flag meaning "don't go here".
193 // I believe we can't handle callee-save doubles D32 and up until
194 // the place in the sparc stack crawler that asserts on the 255 is
195 // fixed up.
196 reg_def R_D32 (SOC, SOC, Op_RegD, 1, F32->as_VMReg());
197 reg_def R_D32x(SOC, SOC, Op_RegD,255, F32->as_VMReg()->next());
198 reg_def R_D34 (SOC, SOC, Op_RegD, 3, F34->as_VMReg());
199 reg_def R_D34x(SOC, SOC, Op_RegD,255, F34->as_VMReg()->next());
200 reg_def R_D36 (SOC, SOC, Op_RegD, 5, F36->as_VMReg());
201 reg_def R_D36x(SOC, SOC, Op_RegD,255, F36->as_VMReg()->next());
202 reg_def R_D38 (SOC, SOC, Op_RegD, 7, F38->as_VMReg());
203 reg_def R_D38x(SOC, SOC, Op_RegD,255, F38->as_VMReg()->next());
204 reg_def R_D40 (SOC, SOC, Op_RegD, 9, F40->as_VMReg());
205 reg_def R_D40x(SOC, SOC, Op_RegD,255, F40->as_VMReg()->next());
206 reg_def R_D42 (SOC, SOC, Op_RegD, 11, F42->as_VMReg());
207 reg_def R_D42x(SOC, SOC, Op_RegD,255, F42->as_VMReg()->next());
208 reg_def R_D44 (SOC, SOC, Op_RegD, 13, F44->as_VMReg());
209 reg_def R_D44x(SOC, SOC, Op_RegD,255, F44->as_VMReg()->next());
210 reg_def R_D46 (SOC, SOC, Op_RegD, 15, F46->as_VMReg());
211 reg_def R_D46x(SOC, SOC, Op_RegD,255, F46->as_VMReg()->next());
212 reg_def R_D48 (SOC, SOC, Op_RegD, 17, F48->as_VMReg());
213 reg_def R_D48x(SOC, SOC, Op_RegD,255, F48->as_VMReg()->next());
214 reg_def R_D50 (SOC, SOC, Op_RegD, 19, F50->as_VMReg());
215 reg_def R_D50x(SOC, SOC, Op_RegD,255, F50->as_VMReg()->next());
216 reg_def R_D52 (SOC, SOC, Op_RegD, 21, F52->as_VMReg());
217 reg_def R_D52x(SOC, SOC, Op_RegD,255, F52->as_VMReg()->next());
218 reg_def R_D54 (SOC, SOC, Op_RegD, 23, F54->as_VMReg());
219 reg_def R_D54x(SOC, SOC, Op_RegD,255, F54->as_VMReg()->next());
220 reg_def R_D56 (SOC, SOC, Op_RegD, 25, F56->as_VMReg());
221 reg_def R_D56x(SOC, SOC, Op_RegD,255, F56->as_VMReg()->next());
222 reg_def R_D58 (SOC, SOC, Op_RegD, 27, F58->as_VMReg());
223 reg_def R_D58x(SOC, SOC, Op_RegD,255, F58->as_VMReg()->next());
224 reg_def R_D60 (SOC, SOC, Op_RegD, 29, F60->as_VMReg());
225 reg_def R_D60x(SOC, SOC, Op_RegD,255, F60->as_VMReg()->next());
226 reg_def R_D62 (SOC, SOC, Op_RegD, 31, F62->as_VMReg());
227 reg_def R_D62x(SOC, SOC, Op_RegD,255, F62->as_VMReg()->next());
228
229
230 // ----------------------------
231 // Special Registers
232 // Condition Codes Flag Registers
233 // I tried to break out ICC and XCC but it's not very pretty.
234 // Every Sparc instruction which defs/kills one also kills the other.
235 // Hence every compare instruction which defs one kind of flags ends
236 // up needing a kill of the other.
237 reg_def CCR (SOC, SOC, Op_RegFlags, 0, VMRegImpl::Bad());
238
239 reg_def FCC0(SOC, SOC, Op_RegFlags, 0, VMRegImpl::Bad());
240 reg_def FCC1(SOC, SOC, Op_RegFlags, 1, VMRegImpl::Bad());
241 reg_def FCC2(SOC, SOC, Op_RegFlags, 2, VMRegImpl::Bad());
242 reg_def FCC3(SOC, SOC, Op_RegFlags, 3, VMRegImpl::Bad());
243
244 // ----------------------------
245 // Specify the enum values for the registers. These enums are only used by the
246 // OptoReg "class". We can convert these enum values at will to VMReg when needed
247 // for visibility to the rest of the vm. The order of this enum influences the
248 // register allocator so having the freedom to set this order and not be stuck
249 // with the order that is natural for the rest of the vm is worth it.
250 alloc_class chunk0(
251 R_L0,R_L0H, R_L1,R_L1H, R_L2,R_L2H, R_L3,R_L3H, R_L4,R_L4H, R_L5,R_L5H, R_L6,R_L6H, R_L7,R_L7H,
252 R_G0,R_G0H, R_G1,R_G1H, R_G2,R_G2H, R_G3,R_G3H, R_G4,R_G4H, R_G5,R_G5H, R_G6,R_G6H, R_G7,R_G7H,
253 R_O7,R_O7H, R_SP,R_SPH, R_O0,R_O0H, R_O1,R_O1H, R_O2,R_O2H, R_O3,R_O3H, R_O4,R_O4H, R_O5,R_O5H,
254 R_I0,R_I0H, R_I1,R_I1H, R_I2,R_I2H, R_I3,R_I3H, R_I4,R_I4H, R_I5,R_I5H, R_FP,R_FPH, R_I7,R_I7H);
255
256 // Note that a register is not allocatable unless it is also mentioned
257 // in a widely-used reg_class below. Thus, R_G7 and R_G0 are outside i_reg.
258
259 alloc_class chunk1(
260 // The first registers listed here are those most likely to be used
261 // as temporaries. We move F0..F7 away from the front of the list,
262 // to reduce the likelihood of interferences with parameters and
263 // return values. Likewise, we avoid using F0/F1 for parameters,
264 // since they are used for return values.
265 // This FPU fine-tuning is worth about 1% on the SPEC geomean.
266 R_F8 ,R_F9 ,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,
267 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,
268 R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,R_F30,R_F31,
269 R_F0 ,R_F1 ,R_F2 ,R_F3 ,R_F4 ,R_F5 ,R_F6 ,R_F7 , // used for arguments and return values
270 R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x,
271 R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x,
272 R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x,
273 R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x);
274
275 alloc_class chunk2(CCR, FCC0, FCC1, FCC2, FCC3);
276
277 //----------Architecture Description Register Classes--------------------------
278 // Several register classes are automatically defined based upon information in
279 // this architecture description.
280 // 1) reg_class inline_cache_reg ( as defined in frame section )
281 // 2) reg_class interpreter_method_oop_reg ( as defined in frame section )
282 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
283 //
284
285 // G0 is not included in integer class since it has special meaning.
286 reg_class g0_reg(R_G0);
287
288 // ----------------------------
289 // Integer Register Classes
290 // ----------------------------
291 // Exclusions from i_reg:
292 // R_G0: hardwired zero
293 // R_G2: reserved by HotSpot to the TLS register (invariant within Java)
294 // R_G6: reserved by Solaris ABI to tools
295 // R_G7: reserved by Solaris ABI to libthread
296 // R_O7: Used as a temp in many encodings
297 reg_class int_reg(R_G1,R_G3,R_G4,R_G5,R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
298
299 // Class for all integer registers, except the G registers. This is used for
300 // encodings which use G registers as temps. The regular inputs to such
301 // instructions use a "notemp_" prefix, as a hack to ensure that the allocator
302 // will not put an input into a temp register.
303 reg_class notemp_int_reg(R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
304
305 reg_class g1_regI(R_G1);
306 reg_class g3_regI(R_G3);
307 reg_class g4_regI(R_G4);
308 reg_class o0_regI(R_O0);
309 reg_class o7_regI(R_O7);
310
311 // ----------------------------
312 // Pointer Register Classes
313 // ----------------------------
314 #ifdef _LP64
315 // 64-bit build means 64-bit pointers means hi/lo pairs
316 reg_class ptr_reg( R_G1H,R_G1, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5,
317 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5,
318 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7,
319 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 );
320 // Lock encodings use G3 and G4 internally
321 reg_class lock_ptr_reg( R_G1H,R_G1, R_G5H,R_G5,
322 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5,
323 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7,
324 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 );
325 // Special class for storeP instructions, which can store SP or RPC to TLS.
326 // It is also used for memory addressing, allowing direct TLS addressing.
327 reg_class sp_ptr_reg( R_G1H,R_G1, R_G2H,R_G2, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5,
328 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5, R_SPH,R_SP,
329 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7,
330 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5, R_FPH,R_FP );
331 // R_L7 is the lowest-priority callee-save (i.e., NS) register
332 // We use it to save R_G2 across calls out of Java.
333 reg_class l7_regP(R_L7H,R_L7);
334
335 // Other special pointer regs
336 reg_class g1_regP(R_G1H,R_G1);
337 reg_class g2_regP(R_G2H,R_G2);
338 reg_class g3_regP(R_G3H,R_G3);
339 reg_class g4_regP(R_G4H,R_G4);
340 reg_class g5_regP(R_G5H,R_G5);
341 reg_class i0_regP(R_I0H,R_I0);
342 reg_class o0_regP(R_O0H,R_O0);
343 reg_class o1_regP(R_O1H,R_O1);
344 reg_class o2_regP(R_O2H,R_O2);
345 reg_class o7_regP(R_O7H,R_O7);
346
347 #else // _LP64
348 // 32-bit build means 32-bit pointers means 1 register.
349 reg_class ptr_reg( R_G1, R_G3,R_G4,R_G5,
350 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,
351 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,
352 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
353 // Lock encodings use G3 and G4 internally
354 reg_class lock_ptr_reg(R_G1, R_G5,
355 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,
356 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,
357 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
358 // Special class for storeP instructions, which can store SP or RPC to TLS.
359 // It is also used for memory addressing, allowing direct TLS addressing.
360 reg_class sp_ptr_reg( R_G1,R_G2,R_G3,R_G4,R_G5,
361 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_SP,
362 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,
363 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5,R_FP);
364 // R_L7 is the lowest-priority callee-save (i.e., NS) register
365 // We use it to save R_G2 across calls out of Java.
366 reg_class l7_regP(R_L7);
367
368 // Other special pointer regs
369 reg_class g1_regP(R_G1);
370 reg_class g2_regP(R_G2);
371 reg_class g3_regP(R_G3);
372 reg_class g4_regP(R_G4);
373 reg_class g5_regP(R_G5);
374 reg_class i0_regP(R_I0);
375 reg_class o0_regP(R_O0);
376 reg_class o1_regP(R_O1);
377 reg_class o2_regP(R_O2);
378 reg_class o7_regP(R_O7);
379 #endif // _LP64
380
381
382 // ----------------------------
383 // Long Register Classes
384 // ----------------------------
385 // Longs in 1 register. Aligned adjacent hi/lo pairs.
386 // Note: O7 is never in this class; it is sometimes used as an encoding temp.
387 reg_class long_reg( R_G1H,R_G1, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5
388 ,R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5
389 #ifdef _LP64
390 // 64-bit, longs in 1 register: use all 64-bit integer registers
391 // 32-bit, longs in 1 register: cannot use I's and L's. Restrict to O's and G's.
392 ,R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7
393 ,R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5
394 #endif // _LP64
395 );
396
397 reg_class g1_regL(R_G1H,R_G1);
398 reg_class g3_regL(R_G3H,R_G3);
399 reg_class o2_regL(R_O2H,R_O2);
400 reg_class o7_regL(R_O7H,R_O7);
401
402 // ----------------------------
403 // Special Class for Condition Code Flags Register
404 reg_class int_flags(CCR);
405 reg_class float_flags(FCC0,FCC1,FCC2,FCC3);
406 reg_class float_flag0(FCC0);
407
408
409 // ----------------------------
410 // Float Point Register Classes
411 // ----------------------------
412 // Skip F30/F31, they are reserved for mem-mem copies
413 reg_class sflt_reg(R_F0,R_F1,R_F2,R_F3,R_F4,R_F5,R_F6,R_F7,R_F8,R_F9,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29);
414
415 // Paired floating point registers--they show up in the same order as the floats,
416 // but they are used with the "Op_RegD" type, and always occur in even/odd pairs.
417 reg_class dflt_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,
418 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,
419 /* Use extra V9 double registers; this AD file does not support V8 */
420 R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x,R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x,
421 R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x,R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x
422 );
423
424 // Paired floating point registers--they show up in the same order as the floats,
425 // but they are used with the "Op_RegD" type, and always occur in even/odd pairs.
426 // This class is usable for mis-aligned loads as happen in I2C adapters.
427 reg_class dflt_low_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,
428 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29);
429 %}
430
431 //----------DEFINITION BLOCK---------------------------------------------------
432 // Define name --> value mappings to inform the ADLC of an integer valued name
433 // Current support includes integer values in the range [0, 0x7FFFFFFF]
434 // Format:
435 // int_def <name> ( <int_value>, <expression>);
436 // Generated Code in ad_<arch>.hpp
437 // #define <name> (<expression>)
438 // // value == <int_value>
439 // Generated code in ad_<arch>.cpp adlc_verification()
440 // assert( <name> == <int_value>, "Expect (<expression>) to equal <int_value>");
441 //
442 definitions %{
443 // The default cost (of an ALU instruction).
444 int_def DEFAULT_COST ( 100, 100);
445 int_def HUGE_COST (1000000, 1000000);
446
447 // Memory refs are twice as expensive as run-of-the-mill.
448 int_def MEMORY_REF_COST ( 200, DEFAULT_COST * 2);
449
450 // Branches are even more expensive.
451 int_def BRANCH_COST ( 300, DEFAULT_COST * 3);
452 int_def CALL_COST ( 300, DEFAULT_COST * 3);
453 %}
454
455
456 //----------SOURCE BLOCK-------------------------------------------------------
457 // This is a block of C++ code which provides values, functions, and
458 // definitions necessary in the rest of the architecture description
459 source_hpp %{
460 // Must be visible to the DFA in dfa_sparc.cpp
461 extern bool can_branch_register( Node *bol, Node *cmp );
462
463 extern bool use_block_zeroing(Node* count);
464
465 // Macros to extract hi & lo halves from a long pair.
466 // G0 is not part of any long pair, so assert on that.
467 // Prevents accidentally using G1 instead of G0.
468 #define LONG_HI_REG(x) (x)
469 #define LONG_LO_REG(x) (x)
470
471 %}
472
473 source %{
474 #define __ _masm.
475
476 // tertiary op of a LoadP or StoreP encoding
477 #define REGP_OP true
478
479 static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding);
480 static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding);
481 static Register reg_to_register_object(int register_encoding);
482
483 // Used by the DFA in dfa_sparc.cpp.
484 // Check for being able to use a V9 branch-on-register. Requires a
485 // compare-vs-zero, equal/not-equal, of a value which was zero- or sign-
486 // extended. Doesn't work following an integer ADD, for example, because of
487 // overflow (-1 incremented yields 0 plus a carry in the high-order word). On
488 // 32-bit V9 systems, interrupts currently blow away the high-order 32 bits and
489 // replace them with zero, which could become sign-extension in a different OS
490 // release. There's no obvious reason why an interrupt will ever fill these
491 // bits with non-zero junk (the registers are reloaded with standard LD
492 // instructions which either zero-fill or sign-fill).
493 bool can_branch_register( Node *bol, Node *cmp ) {
494 if( !BranchOnRegister ) return false;
495 #ifdef _LP64
496 if( cmp->Opcode() == Op_CmpP )
497 return true; // No problems with pointer compares
498 #endif
499 if( cmp->Opcode() == Op_CmpL )
500 return true; // No problems with long compares
501
502 if( !SparcV9RegsHiBitsZero ) return false;
503 if( bol->as_Bool()->_test._test != BoolTest::ne &&
504 bol->as_Bool()->_test._test != BoolTest::eq )
505 return false;
506
507 // Check for comparing against a 'safe' value. Any operation which
508 // clears out the high word is safe. Thus, loads and certain shifts
509 // are safe, as are non-negative constants. Any operation which
510 // preserves zero bits in the high word is safe as long as each of its
511 // inputs are safe. Thus, phis and bitwise booleans are safe if their
512 // inputs are safe. At present, the only important case to recognize
513 // seems to be loads. Constants should fold away, and shifts &
514 // logicals can use the 'cc' forms.
515 Node *x = cmp->in(1);
516 if( x->is_Load() ) return true;
517 if( x->is_Phi() ) {
518 for( uint i = 1; i < x->req(); i++ )
519 if( !x->in(i)->is_Load() )
520 return false;
521 return true;
522 }
523 return false;
524 }
525
526 bool use_block_zeroing(Node* count) {
527 // Use BIS for zeroing if count is not constant
528 // or it is >= BlockZeroingLowLimit.
529 return UseBlockZeroing && (count->find_intptr_t_con(BlockZeroingLowLimit) >= BlockZeroingLowLimit);
530 }
531
532 // ****************************************************************************
533
534 // REQUIRED FUNCTIONALITY
535
536 // !!!!! Special hack to get all type of calls to specify the byte offset
537 // from the start of the call to the point where the return address
538 // will point.
539 // The "return address" is the address of the call instruction, plus 8.
540
541 int MachCallStaticJavaNode::ret_addr_offset() {
542 int offset = NativeCall::instruction_size; // call; delay slot
543 if (_method_handle_invoke)
544 offset += 4; // restore SP
545 return offset;
546 }
547
548 int MachCallDynamicJavaNode::ret_addr_offset() {
549 int vtable_index = this->_vtable_index;
550 if (vtable_index < 0) {
551 // must be invalid_vtable_index, not nonvirtual_vtable_index
552 assert(vtable_index == methodOopDesc::invalid_vtable_index, "correct sentinel value");
553 return (NativeMovConstReg::instruction_size +
554 NativeCall::instruction_size); // sethi; setlo; call; delay slot
555 } else {
556 assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
557 int entry_offset = instanceKlass::vtable_start_offset() + vtable_index*vtableEntry::size();
558 int v_off = entry_offset*wordSize + vtableEntry::method_offset_in_bytes();
559 int klass_load_size;
560 if (UseCompressedOops) {
561 assert(Universe::heap() != NULL, "java heap should be initialized");
562 if (Universe::narrow_oop_base() == NULL)
563 klass_load_size = 2*BytesPerInstWord; // see MacroAssembler::load_klass()
564 else
565 klass_load_size = 3*BytesPerInstWord;
566 } else {
567 klass_load_size = 1*BytesPerInstWord;
568 }
569 if (Assembler::is_simm13(v_off)) {
570 return klass_load_size +
571 (2*BytesPerInstWord + // ld_ptr, ld_ptr
572 NativeCall::instruction_size); // call; delay slot
573 } else {
574 return klass_load_size +
575 (4*BytesPerInstWord + // set_hi, set, ld_ptr, ld_ptr
576 NativeCall::instruction_size); // call; delay slot
577 }
578 }
579 }
580
581 int MachCallRuntimeNode::ret_addr_offset() {
582 #ifdef _LP64
583 if (MacroAssembler::is_far_target(entry_point())) {
584 return NativeFarCall::instruction_size;
585 } else {
586 return NativeCall::instruction_size;
587 }
588 #else
589 return NativeCall::instruction_size; // call; delay slot
590 #endif
591 }
592
593 // Indicate if the safepoint node needs the polling page as an input.
594 // Since Sparc does not have absolute addressing, it does.
595 bool SafePointNode::needs_polling_address_input() {
596 return true;
597 }
598
599 // emit an interrupt that is caught by the debugger (for debugging compiler)
600 void emit_break(CodeBuffer &cbuf) {
601 MacroAssembler _masm(&cbuf);
602 __ breakpoint_trap();
603 }
604
605 #ifndef PRODUCT
606 void MachBreakpointNode::format( PhaseRegAlloc *, outputStream *st ) const {
607 st->print("TA");
608 }
609 #endif
610
611 void MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
612 emit_break(cbuf);
613 }
614
615 uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const {
616 return MachNode::size(ra_);
617 }
618
619 // Traceable jump
620 void emit_jmpl(CodeBuffer &cbuf, int jump_target) {
621 MacroAssembler _masm(&cbuf);
622 Register rdest = reg_to_register_object(jump_target);
623 __ JMP(rdest, 0);
624 __ delayed()->nop();
625 }
626
627 // Traceable jump and set exception pc
628 void emit_jmpl_set_exception_pc(CodeBuffer &cbuf, int jump_target) {
629 MacroAssembler _masm(&cbuf);
630 Register rdest = reg_to_register_object(jump_target);
631 __ JMP(rdest, 0);
632 __ delayed()->add(O7, frame::pc_return_offset, Oissuing_pc );
633 }
634
635 void emit_nop(CodeBuffer &cbuf) {
636 MacroAssembler _masm(&cbuf);
637 __ nop();
638 }
639
640 void emit_illtrap(CodeBuffer &cbuf) {
641 MacroAssembler _masm(&cbuf);
642 __ illtrap(0);
643 }
644
645
646 intptr_t get_offset_from_base(const MachNode* n, const TypePtr* atype, int disp32) {
647 assert(n->rule() != loadUB_rule, "");
648
649 intptr_t offset = 0;
650 const TypePtr *adr_type = TYPE_PTR_SENTINAL; // Check for base==RegI, disp==immP
651 const Node* addr = n->get_base_and_disp(offset, adr_type);
652 assert(adr_type == (const TypePtr*)-1, "VerifyOops: no support for sparc operands with base==RegI, disp==immP");
653 assert(addr != NULL && addr != (Node*)-1, "invalid addr");
654 assert(addr->bottom_type()->isa_oopptr() == atype, "");
655 atype = atype->add_offset(offset);
656 assert(disp32 == offset, "wrong disp32");
657 return atype->_offset;
658 }
659
660
661 intptr_t get_offset_from_base_2(const MachNode* n, const TypePtr* atype, int disp32) {
662 assert(n->rule() != loadUB_rule, "");
663
664 intptr_t offset = 0;
665 Node* addr = n->in(2);
666 assert(addr->bottom_type()->isa_oopptr() == atype, "");
667 if (addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP) {
668 Node* a = addr->in(2/*AddPNode::Address*/);
669 Node* o = addr->in(3/*AddPNode::Offset*/);
670 offset = o->is_Con() ? o->bottom_type()->is_intptr_t()->get_con() : Type::OffsetBot;
671 atype = a->bottom_type()->is_ptr()->add_offset(offset);
672 assert(atype->isa_oop_ptr(), "still an oop");
673 }
674 offset = atype->is_ptr()->_offset;
675 if (offset != Type::OffsetBot) offset += disp32;
676 return offset;
677 }
678
679 static inline jdouble replicate_immI(int con, int count, int width) {
680 // Load a constant replicated "count" times with width "width"
681 assert(count*width == 8 && width <= 4, "sanity");
682 int bit_width = width * 8;
683 jlong val = con;
684 val &= (((jlong) 1) << bit_width) - 1; // mask off sign bits
685 for (int i = 0; i < count - 1; i++) {
686 val |= (val << bit_width);
687 }
688 jdouble dval = *((jdouble*) &val); // coerce to double type
689 return dval;
690 }
691
692 static inline jdouble replicate_immF(float con) {
693 // Replicate float con 2 times and pack into vector.
694 int val = *((int*)&con);
695 jlong lval = val;
696 lval = (lval << 32) | (lval & 0xFFFFFFFFl);
697 jdouble dval = *((jdouble*) &lval); // coerce to double type
698 return dval;
699 }
700
701 // Standard Sparc opcode form2 field breakdown
702 static inline void emit2_19(CodeBuffer &cbuf, int f30, int f29, int f25, int f22, int f20, int f19, int f0 ) {
703 f0 &= (1<<19)-1; // Mask displacement to 19 bits
704 int op = (f30 << 30) |
705 (f29 << 29) |
706 (f25 << 25) |
707 (f22 << 22) |
708 (f20 << 20) |
709 (f19 << 19) |
710 (f0 << 0);
711 cbuf.insts()->emit_int32(op);
712 }
713
714 // Standard Sparc opcode form2 field breakdown
715 static inline void emit2_22(CodeBuffer &cbuf, int f30, int f25, int f22, int f0 ) {
716 f0 >>= 10; // Drop 10 bits
717 f0 &= (1<<22)-1; // Mask displacement to 22 bits
718 int op = (f30 << 30) |
719 (f25 << 25) |
720 (f22 << 22) |
721 (f0 << 0);
722 cbuf.insts()->emit_int32(op);
723 }
724
725 // Standard Sparc opcode form3 field breakdown
726 static inline void emit3(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int f5, int f0 ) {
727 int op = (f30 << 30) |
728 (f25 << 25) |
729 (f19 << 19) |
730 (f14 << 14) |
731 (f5 << 5) |
732 (f0 << 0);
733 cbuf.insts()->emit_int32(op);
734 }
735
736 // Standard Sparc opcode form3 field breakdown
737 static inline void emit3_simm13(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm13 ) {
738 simm13 &= (1<<13)-1; // Mask to 13 bits
739 int op = (f30 << 30) |
740 (f25 << 25) |
741 (f19 << 19) |
742 (f14 << 14) |
743 (1 << 13) | // bit to indicate immediate-mode
744 (simm13<<0);
745 cbuf.insts()->emit_int32(op);
746 }
747
748 static inline void emit3_simm10(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm10 ) {
749 simm10 &= (1<<10)-1; // Mask to 10 bits
750 emit3_simm13(cbuf,f30,f25,f19,f14,simm10);
751 }
752
753 #ifdef ASSERT
754 // Helper function for VerifyOops in emit_form3_mem_reg
755 void verify_oops_warning(const MachNode *n, int ideal_op, int mem_op) {
756 warning("VerifyOops encountered unexpected instruction:");
757 n->dump(2);
758 warning("Instruction has ideal_Opcode==Op_%s and op_ld==Op_%s \n", NodeClassNames[ideal_op], NodeClassNames[mem_op]);
759 }
760 #endif
761
762
763 void emit_form3_mem_reg(CodeBuffer &cbuf, const MachNode* n, int primary, int tertiary,
764 int src1_enc, int disp32, int src2_enc, int dst_enc) {
765
766 #ifdef ASSERT
767 // The following code implements the +VerifyOops feature.
768 // It verifies oop values which are loaded into or stored out of
769 // the current method activation. +VerifyOops complements techniques
770 // like ScavengeALot, because it eagerly inspects oops in transit,
771 // as they enter or leave the stack, as opposed to ScavengeALot,
772 // which inspects oops "at rest", in the stack or heap, at safepoints.
773 // For this reason, +VerifyOops can sometimes detect bugs very close
774 // to their point of creation. It can also serve as a cross-check
775 // on the validity of oop maps, when used toegether with ScavengeALot.
776
777 // It would be good to verify oops at other points, especially
778 // when an oop is used as a base pointer for a load or store.
779 // This is presently difficult, because it is hard to know when
780 // a base address is biased or not. (If we had such information,
781 // it would be easy and useful to make a two-argument version of
782 // verify_oop which unbiases the base, and performs verification.)
783
784 assert((uint)tertiary == 0xFFFFFFFF || tertiary == REGP_OP, "valid tertiary");
785 bool is_verified_oop_base = false;
786 bool is_verified_oop_load = false;
787 bool is_verified_oop_store = false;
788 int tmp_enc = -1;
789 if (VerifyOops && src1_enc != R_SP_enc) {
790 // classify the op, mainly for an assert check
791 int st_op = 0, ld_op = 0;
792 switch (primary) {
793 case Assembler::stb_op3: st_op = Op_StoreB; break;
794 case Assembler::sth_op3: st_op = Op_StoreC; break;
795 case Assembler::stx_op3: // may become StoreP or stay StoreI or StoreD0
796 case Assembler::stw_op3: st_op = Op_StoreI; break;
797 case Assembler::std_op3: st_op = Op_StoreL; break;
798 case Assembler::stf_op3: st_op = Op_StoreF; break;
799 case Assembler::stdf_op3: st_op = Op_StoreD; break;
800
801 case Assembler::ldsb_op3: ld_op = Op_LoadB; break;
802 case Assembler::ldub_op3: ld_op = Op_LoadUB; break;
803 case Assembler::lduh_op3: ld_op = Op_LoadUS; break;
804 case Assembler::ldsh_op3: ld_op = Op_LoadS; break;
805 case Assembler::ldx_op3: // may become LoadP or stay LoadI
806 case Assembler::ldsw_op3: // may become LoadP or stay LoadI
807 case Assembler::lduw_op3: ld_op = Op_LoadI; break;
808 case Assembler::ldd_op3: ld_op = Op_LoadL; break;
809 case Assembler::ldf_op3: ld_op = Op_LoadF; break;
810 case Assembler::lddf_op3: ld_op = Op_LoadD; break;
811 case Assembler::prefetch_op3: ld_op = Op_LoadI; break;
812
813 default: ShouldNotReachHere();
814 }
815 if (tertiary == REGP_OP) {
816 if (st_op == Op_StoreI) st_op = Op_StoreP;
817 else if (ld_op == Op_LoadI) ld_op = Op_LoadP;
818 else ShouldNotReachHere();
819 if (st_op) {
820 // a store
821 // inputs are (0:control, 1:memory, 2:address, 3:value)
822 Node* n2 = n->in(3);
823 if (n2 != NULL) {
824 const Type* t = n2->bottom_type();
825 is_verified_oop_store = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false;
826 }
827 } else {
828 // a load
829 const Type* t = n->bottom_type();
830 is_verified_oop_load = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false;
831 }
832 }
833
834 if (ld_op) {
835 // a Load
836 // inputs are (0:control, 1:memory, 2:address)
837 if (!(n->ideal_Opcode()==ld_op) && // Following are special cases
838 !(n->ideal_Opcode()==Op_LoadPLocked && ld_op==Op_LoadP) &&
839 !(n->ideal_Opcode()==Op_LoadI && ld_op==Op_LoadF) &&
840 !(n->ideal_Opcode()==Op_LoadF && ld_op==Op_LoadI) &&
841 !(n->ideal_Opcode()==Op_LoadRange && ld_op==Op_LoadI) &&
842 !(n->ideal_Opcode()==Op_LoadKlass && ld_op==Op_LoadP) &&
843 !(n->ideal_Opcode()==Op_LoadL && ld_op==Op_LoadI) &&
844 !(n->ideal_Opcode()==Op_LoadL_unaligned && ld_op==Op_LoadI) &&
845 !(n->ideal_Opcode()==Op_LoadD_unaligned && ld_op==Op_LoadF) &&
846 !(n->ideal_Opcode()==Op_ConvI2F && ld_op==Op_LoadF) &&
847 !(n->ideal_Opcode()==Op_ConvI2D && ld_op==Op_LoadF) &&
848 !(n->ideal_Opcode()==Op_PrefetchRead && ld_op==Op_LoadI) &&
849 !(n->ideal_Opcode()==Op_PrefetchWrite && ld_op==Op_LoadI) &&
850 !(n->ideal_Opcode()==Op_PrefetchAllocation && ld_op==Op_LoadI) &&
851 !(n->ideal_Opcode()==Op_LoadVector && ld_op==Op_LoadD) &&
852 !(n->rule() == loadUB_rule)) {
853 verify_oops_warning(n, n->ideal_Opcode(), ld_op);
854 }
855 } else if (st_op) {
856 // a Store
857 // inputs are (0:control, 1:memory, 2:address, 3:value)
858 if (!(n->ideal_Opcode()==st_op) && // Following are special cases
859 !(n->ideal_Opcode()==Op_StoreCM && st_op==Op_StoreB) &&
860 !(n->ideal_Opcode()==Op_StoreI && st_op==Op_StoreF) &&
861 !(n->ideal_Opcode()==Op_StoreF && st_op==Op_StoreI) &&
862 !(n->ideal_Opcode()==Op_StoreL && st_op==Op_StoreI) &&
863 !(n->ideal_Opcode()==Op_StoreVector && st_op==Op_StoreD) &&
864 !(n->ideal_Opcode()==Op_StoreD && st_op==Op_StoreI && n->rule() == storeD0_rule)) {
865 verify_oops_warning(n, n->ideal_Opcode(), st_op);
866 }
867 }
868
869 if (src2_enc == R_G0_enc && n->rule() != loadUB_rule && n->ideal_Opcode() != Op_StoreCM ) {
870 Node* addr = n->in(2);
871 if (!(addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP)) {
872 const TypeOopPtr* atype = addr->bottom_type()->isa_instptr(); // %%% oopptr?
873 if (atype != NULL) {
874 intptr_t offset = get_offset_from_base(n, atype, disp32);
875 intptr_t offset_2 = get_offset_from_base_2(n, atype, disp32);
876 if (offset != offset_2) {
877 get_offset_from_base(n, atype, disp32);
878 get_offset_from_base_2(n, atype, disp32);
879 }
880 assert(offset == offset_2, "different offsets");
881 if (offset == disp32) {
882 // we now know that src1 is a true oop pointer
883 is_verified_oop_base = true;
884 if (ld_op && src1_enc == dst_enc && ld_op != Op_LoadF && ld_op != Op_LoadD) {
885 if( primary == Assembler::ldd_op3 ) {
886 is_verified_oop_base = false; // Cannot 'ldd' into O7
887 } else {
888 tmp_enc = dst_enc;
889 dst_enc = R_O7_enc; // Load into O7; preserve source oop
890 assert(src1_enc != dst_enc, "");
891 }
892 }
893 }
894 if (st_op && (( offset == oopDesc::klass_offset_in_bytes())
895 || offset == oopDesc::mark_offset_in_bytes())) {
896 // loading the mark should not be allowed either, but
897 // we don't check this since it conflicts with InlineObjectHash
898 // usage of LoadINode to get the mark. We could keep the
899 // check if we create a new LoadMarkNode
900 // but do not verify the object before its header is initialized
901 ShouldNotReachHere();
902 }
903 }
904 }
905 }
906 }
907 #endif
908
909 uint instr;
910 instr = (Assembler::ldst_op << 30)
911 | (dst_enc << 25)
912 | (primary << 19)
913 | (src1_enc << 14);
914
915 uint index = src2_enc;
916 int disp = disp32;
917
918 if (src1_enc == R_SP_enc || src1_enc == R_FP_enc)
919 disp += STACK_BIAS;
920
921 // We should have a compiler bailout here rather than a guarantee.
922 // Better yet would be some mechanism to handle variable-size matches correctly.
923 guarantee(Assembler::is_simm13(disp), "Do not match large constant offsets" );
924
925 if( disp == 0 ) {
926 // use reg-reg form
927 // bit 13 is already zero
928 instr |= index;
929 } else {
930 // use reg-imm form
931 instr |= 0x00002000; // set bit 13 to one
932 instr |= disp & 0x1FFF;
933 }
934
935 cbuf.insts()->emit_int32(instr);
936
937 #ifdef ASSERT
938 {
939 MacroAssembler _masm(&cbuf);
940 if (is_verified_oop_base) {
941 __ verify_oop(reg_to_register_object(src1_enc));
942 }
943 if (is_verified_oop_store) {
944 __ verify_oop(reg_to_register_object(dst_enc));
945 }
946 if (tmp_enc != -1) {
947 __ mov(O7, reg_to_register_object(tmp_enc));
948 }
949 if (is_verified_oop_load) {
950 __ verify_oop(reg_to_register_object(dst_enc));
951 }
952 }
953 #endif
954 }
955
956 void emit_call_reloc(CodeBuffer &cbuf, intptr_t entry_point, relocInfo::relocType rtype, bool preserve_g2 = false) {
957 // The method which records debug information at every safepoint
958 // expects the call to be the first instruction in the snippet as
959 // it creates a PcDesc structure which tracks the offset of a call
960 // from the start of the codeBlob. This offset is computed as
961 // code_end() - code_begin() of the code which has been emitted
962 // so far.
963 // In this particular case we have skirted around the problem by
964 // putting the "mov" instruction in the delay slot but the problem
965 // may bite us again at some other point and a cleaner/generic
966 // solution using relocations would be needed.
967 MacroAssembler _masm(&cbuf);
968 __ set_inst_mark();
969
970 // We flush the current window just so that there is a valid stack copy
971 // the fact that the current window becomes active again instantly is
972 // not a problem there is nothing live in it.
973
974 #ifdef ASSERT
975 int startpos = __ offset();
976 #endif /* ASSERT */
977
978 __ call((address)entry_point, rtype);
979
980 if (preserve_g2) __ delayed()->mov(G2, L7);
981 else __ delayed()->nop();
982
983 if (preserve_g2) __ mov(L7, G2);
984
985 #ifdef ASSERT
986 if (preserve_g2 && (VerifyCompiledCode || VerifyOops)) {
987 #ifdef _LP64
988 // Trash argument dump slots.
989 __ set(0xb0b8ac0db0b8ac0d, G1);
990 __ mov(G1, G5);
991 __ stx(G1, SP, STACK_BIAS + 0x80);
992 __ stx(G1, SP, STACK_BIAS + 0x88);
993 __ stx(G1, SP, STACK_BIAS + 0x90);
994 __ stx(G1, SP, STACK_BIAS + 0x98);
995 __ stx(G1, SP, STACK_BIAS + 0xA0);
996 __ stx(G1, SP, STACK_BIAS + 0xA8);
997 #else // _LP64
998 // this is also a native call, so smash the first 7 stack locations,
999 // and the various registers
1000
1001 // Note: [SP+0x40] is sp[callee_aggregate_return_pointer_sp_offset],
1002 // while [SP+0x44..0x58] are the argument dump slots.
1003 __ set((intptr_t)0xbaadf00d, G1);
1004 __ mov(G1, G5);
1005 __ sllx(G1, 32, G1);
1006 __ or3(G1, G5, G1);
1007 __ mov(G1, G5);
1008 __ stx(G1, SP, 0x40);
1009 __ stx(G1, SP, 0x48);
1010 __ stx(G1, SP, 0x50);
1011 __ stw(G1, SP, 0x58); // Do not trash [SP+0x5C] which is a usable spill slot
1012 #endif // _LP64
1013 }
1014 #endif /*ASSERT*/
1015 }
1016
1017 //=============================================================================
1018 // REQUIRED FUNCTIONALITY for encoding
1019 void emit_lo(CodeBuffer &cbuf, int val) { }
1020 void emit_hi(CodeBuffer &cbuf, int val) { }
1021
1022
1023 //=============================================================================
1024 const RegMask& MachConstantBaseNode::_out_RegMask = PTR_REG_mask();
1025
1026 int Compile::ConstantTable::calculate_table_base_offset() const {
1027 if (UseRDPCForConstantTableBase) {
1028 // The table base offset might be less but then it fits into
1029 // simm13 anyway and we are good (cf. MachConstantBaseNode::emit).
1030 return Assembler::min_simm13();
1031 } else {
1032 int offset = -(size() / 2);
1033 if (!Assembler::is_simm13(offset)) {
1034 offset = Assembler::min_simm13();
1035 }
1036 return offset;
1037 }
1038 }
1039
1040 bool MachConstantBaseNode::requires_late_expand() const { return false; }
1041 void MachConstantBaseNode::lateExpand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) {
1042 ShouldNotReachHere();
1043 }
1044
1045 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
1046 Compile* C = ra_->C;
1047 Compile::ConstantTable& constant_table = C->constant_table();
1048 MacroAssembler _masm(&cbuf);
1049
1050 Register r = as_Register(ra_->get_encode(this));
1051 CodeSection* consts_section = __ code()->consts();
1052 int consts_size = consts_section->align_at_start(consts_section->size());
1053 assert(constant_table.size() == consts_size, err_msg("must be: %d == %d", constant_table.size(), consts_size));
1054
1055 if (UseRDPCForConstantTableBase) {
1056 // For the following RDPC logic to work correctly the consts
1057 // section must be allocated right before the insts section. This
1058 // assert checks for that. The layout and the SECT_* constants
1059 // are defined in src/share/vm/asm/codeBuffer.hpp.
1060 assert(CodeBuffer::SECT_CONSTS + 1 == CodeBuffer::SECT_INSTS, "must be");
1061 int insts_offset = __ offset();
1062
1063 // Layout:
1064 //
1065 // |----------- consts section ------------|----------- insts section -----------...
1066 // |------ constant table -----|- padding -|------------------x----
1067 // \ current PC (RDPC instruction)
1068 // |<------------- consts_size ----------->|<- insts_offset ->|
1069 // \ table base
1070 // The table base offset is later added to the load displacement
1071 // so it has to be negative.
1072 int table_base_offset = -(consts_size + insts_offset);
1073 int disp;
1074
1075 // If the displacement from the current PC to the constant table
1076 // base fits into simm13 we set the constant table base to the
1077 // current PC.
1078 if (Assembler::is_simm13(table_base_offset)) {
1079 constant_table.set_table_base_offset(table_base_offset);
1080 disp = 0;
1081 } else {
1082 // Otherwise we set the constant table base offset to the
1083 // maximum negative displacement of load instructions to keep
1084 // the disp as small as possible:
1085 //
1086 // |<------------- consts_size ----------->|<- insts_offset ->|
1087 // |<--------- min_simm13 --------->|<-------- disp --------->|
1088 // \ table base
1089 table_base_offset = Assembler::min_simm13();
1090 constant_table.set_table_base_offset(table_base_offset);
1091 disp = (consts_size + insts_offset) + table_base_offset;
1092 }
1093
1094 __ rdpc(r);
1095
1096 if (disp != 0) {
1097 assert(r != O7, "need temporary");
1098 __ sub(r, __ ensure_simm13_or_reg(disp, O7), r);
1099 }
1100 }
1101 else {
1102 // Materialize the constant table base.
1103 address baseaddr = consts_section->start() + -(constant_table.table_base_offset());
1104 RelocationHolder rspec = internal_word_Relocation::spec(baseaddr);
1105 AddressLiteral base(baseaddr, rspec);
1106 __ set(base, r);
1107 }
1108 }
1109
1110 uint MachConstantBaseNode::size(PhaseRegAlloc*) const {
1111 if (UseRDPCForConstantTableBase) {
1112 // This is really the worst case but generally it's only 1 instruction.
1113 return (1 /*rdpc*/ + 1 /*sub*/ + MacroAssembler::worst_case_insts_for_set()) * BytesPerInstWord;
1114 } else {
1115 return MacroAssembler::worst_case_insts_for_set() * BytesPerInstWord;
1116 }
1117 }
1118
1119 #ifndef PRODUCT
1120 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
1121 char reg[128];
1122 ra_->dump_register(this, reg);
1123 if (UseRDPCForConstantTableBase) {
1124 st->print("RDPC %s\t! constant table base", reg);
1125 } else {
1126 st->print("SET &constanttable,%s\t! constant table base", reg);
1127 }
1128 }
1129 #endif
1130
1131
1132 //=============================================================================
1133
1134 #ifndef PRODUCT
1135 void MachPrologNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1136 Compile* C = ra_->C;
1137
1138 for (int i = 0; i < OptoPrologueNops; i++) {
1139 st->print_cr("NOP"); st->print("\t");
1140 }
1141
1142 if( VerifyThread ) {
1143 st->print_cr("Verify_Thread"); st->print("\t");
1144 }
1145
1146 size_t framesize = C->frame_slots() << LogBytesPerInt;
1147
1148 // Calls to C2R adapters often do not accept exceptional returns.
1149 // We require that their callers must bang for them. But be careful, because
1150 // some VM calls (such as call site linkage) can use several kilobytes of
1151 // stack. But the stack safety zone should account for that.
1152 // See bugs 4446381, 4468289, 4497237.
1153 if (C->need_stack_bang(framesize)) {
1154 st->print_cr("! stack bang"); st->print("\t");
1155 }
1156
1157 if (Assembler::is_simm13(-framesize)) {
1158 st->print ("SAVE R_SP,-%d,R_SP",framesize);
1159 } else {
1160 st->print_cr("SETHI R_SP,hi%%(-%d),R_G3",framesize); st->print("\t");
1161 st->print_cr("ADD R_G3,lo%%(-%d),R_G3",framesize); st->print("\t");
1162 st->print ("SAVE R_SP,R_G3,R_SP");
1163 }
1164
1165 }
1166 #endif
1167
1168 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1169 Compile* C = ra_->C;
1170 MacroAssembler _masm(&cbuf);
1171
1172 for (int i = 0; i < OptoPrologueNops; i++) {
1173 __ nop();
1174 }
1175
1176 __ verify_thread();
1177
1178 size_t framesize = C->frame_slots() << LogBytesPerInt;
1179 assert(framesize >= 16*wordSize, "must have room for reg. save area");
1180 assert(framesize%(2*wordSize) == 0, "must preserve 2*wordSize alignment");
1181
1182 // Calls to C2R adapters often do not accept exceptional returns.
1183 // We require that their callers must bang for them. But be careful, because
1184 // some VM calls (such as call site linkage) can use several kilobytes of
1185 // stack. But the stack safety zone should account for that.
1186 // See bugs 4446381, 4468289, 4497237.
1187 if (C->need_stack_bang(framesize)) {
1188 __ generate_stack_overflow_check(framesize);
1189 }
1190
1191 if (Assembler::is_simm13(-framesize)) {
1192 __ save(SP, -framesize, SP);
1193 } else {
1194 __ sethi(-framesize & ~0x3ff, G3);
1195 __ add(G3, -framesize & 0x3ff, G3);
1196 __ save(SP, G3, SP);
1197 }
1198 C->set_frame_complete( __ offset() );
1199
1200 if (!UseRDPCForConstantTableBase && C->has_mach_constant_base_node()) {
1201 // NOTE: We set the table base offset here because users might be
1202 // emitted before MachConstantBaseNode.
1203 Compile::ConstantTable& constant_table = C->constant_table();
1204 constant_table.set_table_base_offset(constant_table.calculate_table_base_offset());
1205 }
1206 }
1207
1208 uint MachPrologNode::size(PhaseRegAlloc *ra_) const {
1209 return MachNode::size(ra_);
1210 }
1211
1212 int MachPrologNode::reloc() const {
1213 return 10; // a large enough number
1214 }
1215
1216 //=============================================================================
1217 #ifndef PRODUCT
1218 void MachEpilogNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1219 Compile* C = ra_->C;
1220
1221 if( do_polling() && ra_->C->is_method_compilation() ) {
1222 st->print("SETHI #PollAddr,L0\t! Load Polling address\n\t");
1223 #ifdef _LP64
1224 st->print("LDX [L0],G0\t!Poll for Safepointing\n\t");
1225 #else
1226 st->print("LDUW [L0],G0\t!Poll for Safepointing\n\t");
1227 #endif
1228 }
1229
1230 if( do_polling() )
1231 st->print("RET\n\t");
1232
1233 st->print("RESTORE");
1234 }
1235 #endif
1236
1237 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1238 MacroAssembler _masm(&cbuf);
1239 Compile* C = ra_->C;
1240
1241 __ verify_thread();
1242
1243 // If this does safepoint polling, then do it here
1244 if( do_polling() && ra_->C->is_method_compilation() ) {
1245 AddressLiteral polling_page(os::get_polling_page());
1246 __ sethi(polling_page, L0);
1247 __ relocate(relocInfo::poll_return_type);
1248 __ ld_ptr( L0, 0, G0 );
1249 }
1250
1251 // If this is a return, then stuff the restore in the delay slot
1252 if( do_polling() ) {
1253 __ ret();
1254 __ delayed()->restore();
1255 } else {
1256 __ restore();
1257 }
1258 }
1259
1260 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const {
1261 return MachNode::size(ra_);
1262 }
1263
1264 int MachEpilogNode::reloc() const {
1265 return 16; // a large enough number
1266 }
1267
1268 const Pipeline * MachEpilogNode::pipeline() const {
1269 return MachNode::pipeline_class();
1270 }
1271
1272 int MachEpilogNode::safepoint_offset() const {
1273 assert( do_polling(), "no return for this epilog node");
1274 return MacroAssembler::insts_for_sethi(os::get_polling_page()) * BytesPerInstWord;
1275 }
1276
1277 //=============================================================================
1278
1279 // Figure out which register class each belongs in: rc_int, rc_float, rc_stack
1280 enum RC { rc_bad, rc_int, rc_float, rc_stack };
1281 static enum RC rc_class( OptoReg::Name reg ) {
1282 if( !OptoReg::is_valid(reg) ) return rc_bad;
1283 if (OptoReg::is_stack(reg)) return rc_stack;
1284 VMReg r = OptoReg::as_VMReg(reg);
1285 if (r->is_Register()) return rc_int;
1286 assert(r->is_FloatRegister(), "must be");
1287 return rc_float;
1288 }
1289
1290 static int impl_helper( const MachNode *mach, CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, bool is_load, int offset, int reg, int opcode, const char *op_str, int size, outputStream* st ) {
1291 if( cbuf ) {
1292 // Better yet would be some mechanism to handle variable-size matches correctly
1293 if (!Assembler::is_simm13(offset + STACK_BIAS)) {
1294 ra_->C->record_method_not_compilable("unable to handle large constant offsets");
1295 } else {
1296 emit_form3_mem_reg(*cbuf, mach, opcode, -1, R_SP_enc, offset, 0, Matcher::_regEncode[reg]);
1297 }
1298 }
1299 #ifndef PRODUCT
1300 else if( !do_size ) {
1301 if( size != 0 ) st->print("\n\t");
1302 if( is_load ) st->print("%s [R_SP + #%d],R_%s\t! spill",op_str,offset,OptoReg::regname(reg));
1303 else st->print("%s R_%s,[R_SP + #%d]\t! spill",op_str,OptoReg::regname(reg),offset);
1304 }
1305 #endif
1306 return size+4;
1307 }
1308
1309 static int impl_mov_helper( CodeBuffer *cbuf, bool do_size, int src, int dst, int op1, int op2, const char *op_str, int size, outputStream* st ) {
1310 if( cbuf ) emit3( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst], op1, 0, op2, Matcher::_regEncode[src] );
1311 #ifndef PRODUCT
1312 else if( !do_size ) {
1313 if( size != 0 ) st->print("\n\t");
1314 st->print("%s R_%s,R_%s\t! spill",op_str,OptoReg::regname(src),OptoReg::regname(dst));
1315 }
1316 #endif
1317 return size+4;
1318 }
1319
1320 uint MachSpillCopyNode::implementation( CodeBuffer *cbuf,
1321 PhaseRegAlloc *ra_,
1322 bool do_size,
1323 outputStream* st ) const {
1324 // Get registers to move
1325 OptoReg::Name src_second = ra_->get_reg_second(in(1));
1326 OptoReg::Name src_first = ra_->get_reg_first(in(1));
1327 OptoReg::Name dst_second = ra_->get_reg_second(this );
1328 OptoReg::Name dst_first = ra_->get_reg_first(this );
1329
1330 enum RC src_second_rc = rc_class(src_second);
1331 enum RC src_first_rc = rc_class(src_first);
1332 enum RC dst_second_rc = rc_class(dst_second);
1333 enum RC dst_first_rc = rc_class(dst_first);
1334
1335 assert( OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), "must move at least 1 register" );
1336
1337 // Generate spill code!
1338 int size = 0;
1339
1340 if( src_first == dst_first && src_second == dst_second )
1341 return size; // Self copy, no move
1342
1343 // --------------------------------------
1344 // Check for mem-mem move. Load into unused float registers and fall into
1345 // the float-store case.
1346 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) {
1347 int offset = ra_->reg2offset(src_first);
1348 // Further check for aligned-adjacent pair, so we can use a double load
1349 if( (src_first&1)==0 && src_first+1 == src_second ) {
1350 src_second = OptoReg::Name(R_F31_num);
1351 src_second_rc = rc_float;
1352 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F30_num,Assembler::lddf_op3,"LDDF",size, st);
1353 } else {
1354 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F30_num,Assembler::ldf_op3 ,"LDF ",size, st);
1355 }
1356 src_first = OptoReg::Name(R_F30_num);
1357 src_first_rc = rc_float;
1358 }
1359
1360 if( src_second_rc == rc_stack && dst_second_rc == rc_stack ) {
1361 int offset = ra_->reg2offset(src_second);
1362 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F31_num,Assembler::ldf_op3,"LDF ",size, st);
1363 src_second = OptoReg::Name(R_F31_num);
1364 src_second_rc = rc_float;
1365 }
1366
1367 // --------------------------------------
1368 // Check for float->int copy; requires a trip through memory
1369 if (src_first_rc == rc_float && dst_first_rc == rc_int && UseVIS < 3) {
1370 int offset = frame::register_save_words*wordSize;
1371 if (cbuf) {
1372 emit3_simm13( *cbuf, Assembler::arith_op, R_SP_enc, Assembler::sub_op3, R_SP_enc, 16 );
1373 impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st);
1374 impl_helper(this,cbuf,ra_,do_size,true ,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st);
1375 emit3_simm13( *cbuf, Assembler::arith_op, R_SP_enc, Assembler::add_op3, R_SP_enc, 16 );
1376 }
1377 #ifndef PRODUCT
1378 else if (!do_size) {
1379 if (size != 0) st->print("\n\t");
1380 st->print( "SUB R_SP,16,R_SP\n");
1381 impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st);
1382 impl_helper(this,cbuf,ra_,do_size,true ,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st);
1383 st->print("\tADD R_SP,16,R_SP\n");
1384 }
1385 #endif
1386 size += 16;
1387 }
1388
1389 // Check for float->int copy on T4
1390 if (src_first_rc == rc_float && dst_first_rc == rc_int && UseVIS >= 3) {
1391 // Further check for aligned-adjacent pair, so we can use a double move
1392 if ((src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second)
1393 return impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mdtox_opf,"MOVDTOX",size, st);
1394 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mstouw_opf,"MOVSTOUW",size, st);
1395 }
1396 // Check for int->float copy on T4
1397 if (src_first_rc == rc_int && dst_first_rc == rc_float && UseVIS >= 3) {
1398 // Further check for aligned-adjacent pair, so we can use a double move
1399 if ((src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second)
1400 return impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mxtod_opf,"MOVXTOD",size, st);
1401 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mwtos_opf,"MOVWTOS",size, st);
1402 }
1403
1404 // --------------------------------------
1405 // In the 32-bit 1-reg-longs build ONLY, I see mis-aligned long destinations.
1406 // In such cases, I have to do the big-endian swap. For aligned targets, the
1407 // hardware does the flop for me. Doubles are always aligned, so no problem
1408 // there. Misaligned sources only come from native-long-returns (handled
1409 // special below).
1410 #ifndef _LP64
1411 if( src_first_rc == rc_int && // source is already big-endian
1412 src_second_rc != rc_bad && // 64-bit move
1413 ((dst_first&1)!=0 || dst_second != dst_first+1) ) { // misaligned dst
1414 assert( (src_first&1)==0 && src_second == src_first+1, "source must be aligned" );
1415 // Do the big-endian flop.
1416 OptoReg::Name tmp = dst_first ; dst_first = dst_second ; dst_second = tmp ;
1417 enum RC tmp_rc = dst_first_rc; dst_first_rc = dst_second_rc; dst_second_rc = tmp_rc;
1418 }
1419 #endif
1420
1421 // --------------------------------------
1422 // Check for integer reg-reg copy
1423 if( src_first_rc == rc_int && dst_first_rc == rc_int ) {
1424 #ifndef _LP64
1425 if( src_first == R_O0_num && src_second == R_O1_num ) { // Check for the evil O0/O1 native long-return case
1426 // Note: The _first and _second suffixes refer to the addresses of the the 2 halves of the 64-bit value
1427 // as stored in memory. On a big-endian machine like SPARC, this means that the _second
1428 // operand contains the least significant word of the 64-bit value and vice versa.
1429 OptoReg::Name tmp = OptoReg::Name(R_O7_num);
1430 assert( (dst_first&1)==0 && dst_second == dst_first+1, "return a native O0/O1 long to an aligned-adjacent 64-bit reg" );
1431 // Shift O0 left in-place, zero-extend O1, then OR them into the dst
1432 if( cbuf ) {
1433 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[tmp], Assembler::sllx_op3, Matcher::_regEncode[src_first], 0x1020 );
1434 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[src_second], Assembler::srl_op3, Matcher::_regEncode[src_second], 0x0000 );
1435 emit3 ( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_first], Assembler:: or_op3, Matcher::_regEncode[tmp], 0, Matcher::_regEncode[src_second] );
1436 #ifndef PRODUCT
1437 } else if( !do_size ) {
1438 if( size != 0 ) st->print("\n\t");
1439 st->print("SLLX R_%s,32,R_%s\t! Move O0-first to O7-high\n\t", OptoReg::regname(src_first), OptoReg::regname(tmp));
1440 st->print("SRL R_%s, 0,R_%s\t! Zero-extend O1\n\t", OptoReg::regname(src_second), OptoReg::regname(src_second));
1441 st->print("OR R_%s,R_%s,R_%s\t! spill",OptoReg::regname(tmp), OptoReg::regname(src_second), OptoReg::regname(dst_first));
1442 #endif
1443 }
1444 return size+12;
1445 }
1446 else if( dst_first == R_I0_num && dst_second == R_I1_num ) {
1447 // returning a long value in I0/I1
1448 // a SpillCopy must be able to target a return instruction's reg_class
1449 // Note: The _first and _second suffixes refer to the addresses of the the 2 halves of the 64-bit value
1450 // as stored in memory. On a big-endian machine like SPARC, this means that the _second
1451 // operand contains the least significant word of the 64-bit value and vice versa.
1452 OptoReg::Name tdest = dst_first;
1453
1454 if (src_first == dst_first) {
1455 tdest = OptoReg::Name(R_O7_num);
1456 size += 4;
1457 }
1458
1459 if( cbuf ) {
1460 assert( (src_first&1) == 0 && (src_first+1) == src_second, "return value was in an aligned-adjacent 64-bit reg");
1461 // Shift value in upper 32-bits of src to lower 32-bits of I0; move lower 32-bits to I1
1462 // ShrL_reg_imm6
1463 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[tdest], Assembler::srlx_op3, Matcher::_regEncode[src_second], 32 | 0x1000 );
1464 // ShrR_reg_imm6 src, 0, dst
1465 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_second], Assembler::srl_op3, Matcher::_regEncode[src_first], 0x0000 );
1466 if (tdest != dst_first) {
1467 emit3 ( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_first], Assembler::or_op3, 0/*G0*/, 0/*op2*/, Matcher::_regEncode[tdest] );
1468 }
1469 }
1470 #ifndef PRODUCT
1471 else if( !do_size ) {
1472 if( size != 0 ) st->print("\n\t"); // %%%%% !!!!!
1473 st->print("SRLX R_%s,32,R_%s\t! Extract MSW\n\t",OptoReg::regname(src_second),OptoReg::regname(tdest));
1474 st->print("SRL R_%s, 0,R_%s\t! Extract LSW\n\t",OptoReg::regname(src_first),OptoReg::regname(dst_second));
1475 if (tdest != dst_first) {
1476 st->print("MOV R_%s,R_%s\t! spill\n\t", OptoReg::regname(tdest), OptoReg::regname(dst_first));
1477 }
1478 }
1479 #endif // PRODUCT
1480 return size+8;
1481 }
1482 #endif // !_LP64
1483 // Else normal reg-reg copy
1484 assert( src_second != dst_first, "smashed second before evacuating it" );
1485 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::or_op3,0,"MOV ",size, st);
1486 assert( (src_first&1) == 0 && (dst_first&1) == 0, "never move second-halves of int registers" );
1487 // This moves an aligned adjacent pair.
1488 // See if we are done.
1489 if( src_first+1 == src_second && dst_first+1 == dst_second )
1490 return size;
1491 }
1492
1493 // Check for integer store
1494 if( src_first_rc == rc_int && dst_first_rc == rc_stack ) {
1495 int offset = ra_->reg2offset(dst_first);
1496 // Further check for aligned-adjacent pair, so we can use a double store
1497 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1498 return impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stx_op3,"STX ",size, st);
1499 size = impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stw_op3,"STW ",size, st);
1500 }
1501
1502 // Check for integer load
1503 if( dst_first_rc == rc_int && src_first_rc == rc_stack ) {
1504 int offset = ra_->reg2offset(src_first);
1505 // Further check for aligned-adjacent pair, so we can use a double load
1506 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1507 return impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::ldx_op3 ,"LDX ",size, st);
1508 size = impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st);
1509 }
1510
1511 // Check for float reg-reg copy
1512 if( src_first_rc == rc_float && dst_first_rc == rc_float ) {
1513 // Further check for aligned-adjacent pair, so we can use a double move
1514 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1515 return impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::fpop1_op3,Assembler::fmovd_opf,"FMOVD",size, st);
1516 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::fpop1_op3,Assembler::fmovs_opf,"FMOVS",size, st);
1517 }
1518
1519 // Check for float store
1520 if( src_first_rc == rc_float && dst_first_rc == rc_stack ) {
1521 int offset = ra_->reg2offset(dst_first);
1522 // Further check for aligned-adjacent pair, so we can use a double store
1523 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1524 return impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stdf_op3,"STDF",size, st);
1525 size = impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st);
1526 }
1527
1528 // Check for float load
1529 if( dst_first_rc == rc_float && src_first_rc == rc_stack ) {
1530 int offset = ra_->reg2offset(src_first);
1531 // Further check for aligned-adjacent pair, so we can use a double load
1532 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1533 return impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::lddf_op3,"LDDF",size, st);
1534 size = impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::ldf_op3 ,"LDF ",size, st);
1535 }
1536
1537 // --------------------------------------------------------------------
1538 // Check for hi bits still needing moving. Only happens for misaligned
1539 // arguments to native calls.
1540 if( src_second == dst_second )
1541 return size; // Self copy; no move
1542 assert( src_second_rc != rc_bad && dst_second_rc != rc_bad, "src_second & dst_second cannot be Bad" );
1543
1544 #ifndef _LP64
1545 // In the LP64 build, all registers can be moved as aligned/adjacent
1546 // pairs, so there's never any need to move the high bits separately.
1547 // The 32-bit builds have to deal with the 32-bit ABI which can force
1548 // all sorts of silly alignment problems.
1549
1550 // Check for integer reg-reg copy. Hi bits are stuck up in the top
1551 // 32-bits of a 64-bit register, but are needed in low bits of another
1552 // register (else it's a hi-bits-to-hi-bits copy which should have
1553 // happened already as part of a 64-bit move)
1554 if( src_second_rc == rc_int && dst_second_rc == rc_int ) {
1555 assert( (src_second&1)==1, "its the evil O0/O1 native return case" );
1556 assert( (dst_second&1)==0, "should have moved with 1 64-bit move" );
1557 // Shift src_second down to dst_second's low bits.
1558 if( cbuf ) {
1559 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_second], Assembler::srlx_op3, Matcher::_regEncode[src_second-1], 0x1020 );
1560 #ifndef PRODUCT
1561 } else if( !do_size ) {
1562 if( size != 0 ) st->print("\n\t");
1563 st->print("SRLX R_%s,32,R_%s\t! spill: Move high bits down low",OptoReg::regname(src_second-1),OptoReg::regname(dst_second));
1564 #endif
1565 }
1566 return size+4;
1567 }
1568
1569 // Check for high word integer store. Must down-shift the hi bits
1570 // into a temp register, then fall into the case of storing int bits.
1571 if( src_second_rc == rc_int && dst_second_rc == rc_stack && (src_second&1)==1 ) {
1572 // Shift src_second down to dst_second's low bits.
1573 if( cbuf ) {
1574 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[R_O7_num], Assembler::srlx_op3, Matcher::_regEncode[src_second-1], 0x1020 );
1575 #ifndef PRODUCT
1576 } else if( !do_size ) {
1577 if( size != 0 ) st->print("\n\t");
1578 st->print("SRLX R_%s,32,R_%s\t! spill: Move high bits down low",OptoReg::regname(src_second-1),OptoReg::regname(R_O7_num));
1579 #endif
1580 }
1581 size+=4;
1582 src_second = OptoReg::Name(R_O7_num); // Not R_O7H_num!
1583 }
1584
1585 // Check for high word integer load
1586 if( dst_second_rc == rc_int && src_second_rc == rc_stack )
1587 return impl_helper(this,cbuf,ra_,do_size,true ,ra_->reg2offset(src_second),dst_second,Assembler::lduw_op3,"LDUW",size, st);
1588
1589 // Check for high word integer store
1590 if( src_second_rc == rc_int && dst_second_rc == rc_stack )
1591 return impl_helper(this,cbuf,ra_,do_size,false,ra_->reg2offset(dst_second),src_second,Assembler::stw_op3 ,"STW ",size, st);
1592
1593 // Check for high word float store
1594 if( src_second_rc == rc_float && dst_second_rc == rc_stack )
1595 return impl_helper(this,cbuf,ra_,do_size,false,ra_->reg2offset(dst_second),src_second,Assembler::stf_op3 ,"STF ",size, st);
1596
1597 #endif // !_LP64
1598
1599 Unimplemented();
1600 }
1601
1602 #ifndef PRODUCT
1603 void MachSpillCopyNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1604 implementation( NULL, ra_, false, st );
1605 }
1606 #endif
1607
1608 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1609 implementation( &cbuf, ra_, false, NULL );
1610 }
1611
1612 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1613 return implementation( NULL, ra_, true, NULL );
1614 }
1615
1616 //=============================================================================
1617 #ifndef PRODUCT
1618 void MachNopNode::format( PhaseRegAlloc *, outputStream *st ) const {
1619 st->print("NOP \t# %d bytes pad for loops and calls", 4 * _count);
1620 }
1621 #endif
1622
1623 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc * ) const {
1624 MacroAssembler _masm(&cbuf);
1625 for(int i = 0; i < _count; i += 1) {
1626 __ nop();
1627 }
1628 }
1629
1630 uint MachNopNode::size(PhaseRegAlloc *ra_) const {
1631 return 4 * _count;
1632 }
1633
1634
1635 //=============================================================================
1636 #ifndef PRODUCT
1637 void BoxLockNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1638 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1639 int reg = ra_->get_reg_first(this);
1640 st->print("LEA [R_SP+#%d+BIAS],%s",offset,Matcher::regName[reg]);
1641 }
1642 #endif
1643
1644 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1645 MacroAssembler _masm(&cbuf);
1646 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()) + STACK_BIAS;
1647 int reg = ra_->get_encode(this);
1648
1649 if (Assembler::is_simm13(offset)) {
1650 __ add(SP, offset, reg_to_register_object(reg));
1651 } else {
1652 __ set(offset, O7);
1653 __ add(SP, O7, reg_to_register_object(reg));
1654 }
1655 }
1656
1657 uint BoxLockNode::size(PhaseRegAlloc *ra_) const {
1658 // BoxLockNode is not a MachNode, so we can't just call MachNode::size(ra_)
1659 assert(ra_ == ra_->C->regalloc(), "sanity");
1660 return ra_->C->scratch_emit_size(this);
1661 }
1662
1663 //=============================================================================
1664
1665 // Offset from start of compiled java to interpreter stub to the load
1666 // constant that loads the inline cache (IC) (0 on sparc).
1667 const int CompiledStaticCall::comp_to_int_load_offset = 0;
1668
1669 // emit call stub, compiled java to interpretor
1670 void emit_java_to_interp(CodeBuffer &cbuf ) {
1671
1672 // Stub is fixed up when the corresponding call is converted from calling
1673 // compiled code to calling interpreted code.
1674 // set (empty), G5
1675 // jmp -1
1676
1677 address mark = cbuf.insts_mark(); // get mark within main instrs section
1678
1679 MacroAssembler _masm(&cbuf);
1680
1681 address base =
1682 __ start_a_stub(Compile::MAX_stubs_size);
1683 if (base == NULL) return; // CodeBuffer::expand failed
1684
1685 // static stub relocation stores the instruction address of the call
1686 __ relocate(static_stub_Relocation::spec(mark));
1687
1688 __ set_oop(NULL, reg_to_register_object(Matcher::inline_cache_reg_encode()));
1689
1690 __ set_inst_mark();
1691 AddressLiteral addrlit(-1);
1692 __ JUMP(addrlit, G3, 0);
1693
1694 __ delayed()->nop();
1695
1696 // Update current stubs pointer and restore code_end.
1697 __ end_a_stub();
1698 }
1699
1700 // size of call stub, compiled java to interpretor
1701 uint size_java_to_interp() {
1702 // This doesn't need to be accurate but it must be larger or equal to
1703 // the real size of the stub.
1704 return (NativeMovConstReg::instruction_size + // sethi/setlo;
1705 NativeJump::instruction_size + // sethi; jmp; nop
1706 (TraceJumps ? 20 * BytesPerInstWord : 0) );
1707 }
1708 // relocation entries for call stub, compiled java to interpretor
1709 uint reloc_java_to_interp() {
1710 return 10; // 4 in emit_java_to_interp + 1 in Java_Static_Call
1711 }
1712
1713
1714 //=============================================================================
1715 #ifndef PRODUCT
1716 void MachUEPNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1717 st->print_cr("\nUEP:");
1718 #ifdef _LP64
1719 if (UseCompressedOops) {
1720 assert(Universe::heap() != NULL, "java heap should be initialized");
1721 st->print_cr("\tLDUW [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check - compressed klass");
1722 st->print_cr("\tSLL R_G5,3,R_G5");
1723 if (Universe::narrow_oop_base() != NULL)
1724 st->print_cr("\tADD R_G5,R_G6_heap_base,R_G5");
1725 } else {
1726 st->print_cr("\tLDX [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check");
1727 }
1728 st->print_cr("\tCMP R_G5,R_G3" );
1729 st->print ("\tTne xcc,R_G0+ST_RESERVED_FOR_USER_0+2");
1730 #else // _LP64
1731 st->print_cr("\tLDUW [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check");
1732 st->print_cr("\tCMP R_G5,R_G3" );
1733 st->print ("\tTne icc,R_G0+ST_RESERVED_FOR_USER_0+2");
1734 #endif // _LP64
1735 }
1736 #endif
1737
1738 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1739 MacroAssembler _masm(&cbuf);
1740 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode());
1741 Register temp_reg = G3;
1742 assert( G5_ic_reg != temp_reg, "conflicting registers" );
1743
1744 // Load klass from receiver
1745 __ load_klass(O0, temp_reg);
1746 // Compare against expected klass
1747 __ cmp(temp_reg, G5_ic_reg);
1748 // Branch to miss code, checks xcc or icc depending
1749 __ trap(Assembler::notEqual, Assembler::ptr_cc, G0, ST_RESERVED_FOR_USER_0+2);
1750 }
1751
1752 uint MachUEPNode::size(PhaseRegAlloc *ra_) const {
1753 return MachNode::size(ra_);
1754 }
1755
1756
1757 //=============================================================================
1758
1759 uint size_exception_handler() {
1760 if (TraceJumps) {
1761 return (400); // just a guess
1762 }
1763 return ( NativeJump::instruction_size ); // sethi;jmp;nop
1764 }
1765
1766 uint size_deopt_handler() {
1767 if (TraceJumps) {
1768 return (400); // just a guess
1769 }
1770 return ( 4+ NativeJump::instruction_size ); // save;sethi;jmp;restore
1771 }
1772
1773 // Emit exception handler code.
1774 int emit_exception_handler(CodeBuffer& cbuf) {
1775 Register temp_reg = G3;
1776 AddressLiteral exception_blob(OptoRuntime::exception_blob()->entry_point());
1777 MacroAssembler _masm(&cbuf);
1778
1779 address base =
1780 __ start_a_stub(size_exception_handler());
1781 if (base == NULL) return 0; // CodeBuffer::expand failed
1782
1783 int offset = __ offset();
1784
1785 __ JUMP(exception_blob, temp_reg, 0); // sethi;jmp
1786 __ delayed()->nop();
1787
1788 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow");
1789
1790 __ end_a_stub();
1791
1792 return offset;
1793 }
1794
1795 int emit_deopt_handler(CodeBuffer& cbuf) {
1796 // Can't use any of the current frame's registers as we may have deopted
1797 // at a poll and everything (including G3) can be live.
1798 Register temp_reg = L0;
1799 AddressLiteral deopt_blob(SharedRuntime::deopt_blob()->unpack());
1800 MacroAssembler _masm(&cbuf);
1801
1802 address base =
1803 __ start_a_stub(size_deopt_handler());
1804 if (base == NULL) return 0; // CodeBuffer::expand failed
1805
1806 int offset = __ offset();
1807 __ save_frame(0);
1808 __ JUMP(deopt_blob, temp_reg, 0); // sethi;jmp
1809 __ delayed()->restore();
1810
1811 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow");
1812
1813 __ end_a_stub();
1814 return offset;
1815
1816 }
1817
1818 // Given a register encoding, produce a Integer Register object
1819 static Register reg_to_register_object(int register_encoding) {
1820 assert(L5->encoding() == R_L5_enc && G1->encoding() == R_G1_enc, "right coding");
1821 return as_Register(register_encoding);
1822 }
1823
1824 // Given a register encoding, produce a single-precision Float Register object
1825 static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding) {
1826 assert(F5->encoding(FloatRegisterImpl::S) == R_F5_enc && F12->encoding(FloatRegisterImpl::S) == R_F12_enc, "right coding");
1827 return as_SingleFloatRegister(register_encoding);
1828 }
1829
1830 // Given a register encoding, produce a double-precision Float Register object
1831 static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding) {
1832 assert(F4->encoding(FloatRegisterImpl::D) == R_F4_enc, "right coding");
1833 assert(F32->encoding(FloatRegisterImpl::D) == R_D32_enc, "right coding");
1834 return as_DoubleFloatRegister(register_encoding);
1835 }
1836
1837 const bool Matcher::match_rule_supported(int opcode) {
1838 if (!has_match_rule(opcode))
1839 return false;
1840
1841 switch (opcode) {
1842 case Op_CountLeadingZerosI:
1843 case Op_CountLeadingZerosL:
1844 case Op_CountTrailingZerosI:
1845 case Op_CountTrailingZerosL:
1846 case Op_PopCountI:
1847 case Op_PopCountL:
1848 if (!UsePopCountInstruction)
1849 return false;
1850 case Op_CompareAndSwapL:
1851 #ifdef _LP64
1852 case Op_CompareAndSwapP:
1853 #endif
1854 if (!VM_Version::supports_cx8())
1855 return false;
1856 break;
1857 }
1858
1859 return true; // Per default match rules are supported.
1860 }
1861
1862 int Matcher::regnum_to_fpu_offset(int regnum) {
1863 return regnum - 32; // The FP registers are in the second chunk
1864 }
1865
1866 #ifdef ASSERT
1867 address last_rethrow = NULL; // debugging aid for Rethrow encoding
1868 #endif
1869
1870 // Map Types to machine register types
1871 const int Matcher::base2reg[Type::lastype] = {
1872 Node::NotAMachineReg,0,0, Op_RegI, Op_RegL, 0, Op_RegN,
1873 Node::NotAMachineReg, Node::NotAMachineReg, /* tuple, array */
1874 0, Op_RegD, 0, 0, /* Vectors */
1875 Op_RegP, Op_RegP, Op_RegP, Op_RegP, Op_RegP, Op_RegP, /* the pointers */
1876 0, 0/*abio*/,
1877 Op_RegP /* Return address */, 0, /* the memories */
1878 Op_RegF, Op_RegF, Op_RegF, Op_RegD, Op_RegD, Op_RegD,
1879 0 /*bottom*/
1880 };
1881
1882 // Vector width in bytes
1883 const int Matcher::vector_width_in_bytes(BasicType bt) {
1884 assert(MaxVectorSize == 8, "");
1885 return 8;
1886 }
1887
1888 // Vector ideal reg
1889 const int Matcher::vector_ideal_reg(int size) {
1890 assert(MaxVectorSize == 8, "");
1891 return Op_RegD;
1892 }
1893
1894 const int Matcher::vector_shift_count_ideal_reg(int size) {
1895 fatal("vector shift is not supported");
1896 return Node::NotAMachineReg;
1897 }
1898
1899 // Limits on vector size (number of elements) loaded into vector.
1900 const int Matcher::max_vector_size(const BasicType bt) {
1901 assert(is_java_primitive(bt), "only primitive type vectors");
1902 return vector_width_in_bytes(bt)/type2aelembytes(bt);
1903 }
1904
1905 const int Matcher::min_vector_size(const BasicType bt) {
1906 return max_vector_size(bt); // Same as max.
1907 }
1908
1909 // SPARC doesn't support misaligned vectors store/load.
1910 const bool Matcher::misaligned_vectors_ok() {
1911 return false;
1912 }
1913
1914 // USII supports fxtof through the whole range of number, USIII doesn't
1915 const bool Matcher::convL2FSupported(void) {
1916 return VM_Version::has_fast_fxtof();
1917 }
1918
1919 // Is this branch offset short enough that a short branch can be used?
1920 //
1921 // NOTE: If the platform does not provide any short branch variants, then
1922 // this method should return false for offset 0.
1923 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
1924 // The passed offset is relative to address of the branch.
1925 // Don't need to adjust the offset.
1926 return UseCBCond && Assembler::is_simm12(offset);
1927 }
1928
1929 const bool Matcher::isSimpleConstant64(jlong value) {
1930 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?.
1931 // Depends on optimizations in MacroAssembler::setx.
1932 int hi = (int)(value >> 32);
1933 int lo = (int)(value & ~0);
1934 return (hi == 0) || (hi == -1) || (lo == 0);
1935 }
1936
1937 // No scaling for the parameter the ClearArray node.
1938 const bool Matcher::init_array_count_is_in_bytes = true;
1939
1940 // Threshold size for cleararray.
1941 const int Matcher::init_array_short_size = 8 * BytesPerLong;
1942
1943 // No additional cost for CMOVL.
1944 const int Matcher::long_cmove_cost() { return 0; }
1945
1946 // CMOVF/CMOVD are expensive on T4 and on SPARC64.
1947 const int Matcher::float_cmove_cost() {
1948 return (VM_Version::is_T4() || VM_Version::is_sparc64()) ? ConditionalMoveLimit : 0;
1949 }
1950
1951 // Does the CPU require late expand (see block.cpp for description of late expand)?
1952 const bool Matcher::require_late_expand = false;
1953
1954 // Should the Matcher clone shifts on addressing modes, expecting them to
1955 // be subsumed into complex addressing expressions or compute them into
1956 // registers? True for Intel but false for most RISCs
1957 const bool Matcher::clone_shift_expressions = false;
1958
1959 // Do we need to mask the count passed to shift instructions or does
1960 // the cpu only look at the lower 5/6 bits anyway?
1961 const bool Matcher::need_masked_shift_count = false;
1962
1963 bool Matcher::narrow_oop_use_complex_address() {
1964 NOT_LP64(ShouldNotCallThis());
1965 assert(UseCompressedOops, "only for compressed oops code");
1966 return false;
1967 }
1968
1969 // Is it better to copy float constants, or load them directly from memory?
1970 // Intel can load a float constant from a direct address, requiring no
1971 // extra registers. Most RISCs will have to materialize an address into a
1972 // register first, so they would do better to copy the constant from stack.
1973 const bool Matcher::rematerialize_float_constants = false;
1974
1975 // If CPU can load and store mis-aligned doubles directly then no fixup is
1976 // needed. Else we split the double into 2 integer pieces and move it
1977 // piece-by-piece. Only happens when passing doubles into C code as the
1978 // Java calling convention forces doubles to be aligned.
1979 #ifdef _LP64
1980 const bool Matcher::misaligned_doubles_ok = true;
1981 #else
1982 const bool Matcher::misaligned_doubles_ok = false;
1983 #endif
1984
1985 // No-op on SPARC.
1986 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {
1987 }
1988
1989 // Advertise here if the CPU requires explicit rounding operations
1990 // to implement the UseStrictFP mode.
1991 const bool Matcher::strict_fp_requires_explicit_rounding = false;
1992
1993 // Are floats converted to double when stored to stack during deoptimization?
1994 // Sparc does not handle callee-save floats.
1995 bool Matcher::float_in_double() { return false; }
1996
1997 // Do ints take an entire long register or just half?
1998 // Note that we if-def off of _LP64.
1999 // The relevant question is how the int is callee-saved. In _LP64
2000 // the whole long is written but de-opt'ing will have to extract
2001 // the relevant 32 bits, in not-_LP64 only the low 32 bits is written.
2002 #ifdef _LP64
2003 const bool Matcher::int_in_long = true;
2004 #else
2005 const bool Matcher::int_in_long = false;
2006 #endif
2007
2008 // Return whether or not this register is ever used as an argument. This
2009 // function is used on startup to build the trampoline stubs in generateOptoStub.
2010 // Registers not mentioned will be killed by the VM call in the trampoline, and
2011 // arguments in those registers not be available to the callee.
2012 bool Matcher::can_be_java_arg( int reg ) {
2013 // Standard sparc 6 args in registers
2014 if( reg == R_I0_num ||
2015 reg == R_I1_num ||
2016 reg == R_I2_num ||
2017 reg == R_I3_num ||
2018 reg == R_I4_num ||
2019 reg == R_I5_num ) return true;
2020 #ifdef _LP64
2021 // 64-bit builds can pass 64-bit pointers and longs in
2022 // the high I registers
2023 if( reg == R_I0H_num ||
2024 reg == R_I1H_num ||
2025 reg == R_I2H_num ||
2026 reg == R_I3H_num ||
2027 reg == R_I4H_num ||
2028 reg == R_I5H_num ) return true;
2029
2030 if ((UseCompressedOops) && (reg == R_G6_num || reg == R_G6H_num)) {
2031 return true;
2032 }
2033
2034 #else
2035 // 32-bit builds with longs-in-one-entry pass longs in G1 & G4.
2036 // Longs cannot be passed in O regs, because O regs become I regs
2037 // after a 'save' and I regs get their high bits chopped off on
2038 // interrupt.
2039 if( reg == R_G1H_num || reg == R_G1_num ) return true;
2040 if( reg == R_G4H_num || reg == R_G4_num ) return true;
2041 #endif
2042 // A few float args in registers
2043 if( reg >= R_F0_num && reg <= R_F7_num ) return true;
2044
2045 return false;
2046 }
2047
2048 bool Matcher::is_spillable_arg( int reg ) {
2049 return can_be_java_arg(reg);
2050 }
2051
2052 bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) {
2053 // Use hardware SDIVX instruction when it is
2054 // faster than a code which use multiply.
2055 return VM_Version::has_fast_idiv();
2056 }
2057
2058 // Register for DIVI projection of divmodI
2059 RegMask Matcher::divI_proj_mask() {
2060 ShouldNotReachHere();
2061 return RegMask();
2062 }
2063
2064 // Register for MODI projection of divmodI
2065 RegMask Matcher::modI_proj_mask() {
2066 ShouldNotReachHere();
2067 return RegMask();
2068 }
2069
2070 // Register for DIVL projection of divmodL
2071 RegMask Matcher::divL_proj_mask() {
2072 ShouldNotReachHere();
2073 return RegMask();
2074 }
2075
2076 // Register for MODL projection of divmodL
2077 RegMask Matcher::modL_proj_mask() {
2078 ShouldNotReachHere();
2079 return RegMask();
2080 }
2081
2082 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
2083 return L7_REGP_mask();
2084 }
2085
2086 %}
2087
2088
2089 // The intptr_t operand types, defined by textual substitution.
2090 // (Cf. opto/type.hpp. This lets us avoid many, many other ifdefs.)
2091 #ifdef _LP64
2092 #define immX immL
2093 #define immX13 immL13
2094 #define immX13m7 immL13m7
2095 #define iRegX iRegL
2096 #define g1RegX g1RegL
2097 #else
2098 #define immX immI
2099 #define immX13 immI13
2100 #define immX13m7 immI13m7
2101 #define iRegX iRegI
2102 #define g1RegX g1RegI
2103 #endif
2104
2105 //----------ENCODING BLOCK-----------------------------------------------------
2106 // This block specifies the encoding classes used by the compiler to output
2107 // byte streams. Encoding classes are parameterized macros used by
2108 // Machine Instruction Nodes in order to generate the bit encoding of the
2109 // instruction. Operands specify their base encoding interface with the
2110 // interface keyword. There are currently supported four interfaces,
2111 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an
2112 // operand to generate a function which returns its register number when
2113 // queried. CONST_INTER causes an operand to generate a function which
2114 // returns the value of the constant when queried. MEMORY_INTER causes an
2115 // operand to generate four functions which return the Base Register, the
2116 // Index Register, the Scale Value, and the Offset Value of the operand when
2117 // queried. COND_INTER causes an operand to generate six functions which
2118 // return the encoding code (ie - encoding bits for the instruction)
2119 // associated with each basic boolean condition for a conditional instruction.
2120 //
2121 // Instructions specify two basic values for encoding. Again, a function
2122 // is available to check if the constant displacement is an oop. They use the
2123 // ins_encode keyword to specify their encoding classes (which must be
2124 // a sequence of enc_class names, and their parameters, specified in
2125 // the encoding block), and they use the
2126 // opcode keyword to specify, in order, their primary, secondary, and
2127 // tertiary opcode. Only the opcode sections which a particular instruction
2128 // needs for encoding need to be specified.
2129 encode %{
2130 enc_class enc_untested %{
2131 #ifdef ASSERT
2132 MacroAssembler _masm(&cbuf);
2133 __ untested("encoding");
2134 #endif
2135 %}
2136
2137 enc_class form3_mem_reg( memory mem, iRegI dst ) %{
2138 emit_form3_mem_reg(cbuf, this, $primary, $tertiary,
2139 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg);
2140 %}
2141
2142 enc_class simple_form3_mem_reg( memory mem, iRegI dst ) %{
2143 emit_form3_mem_reg(cbuf, this, $primary, -1,
2144 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg);
2145 %}
2146
2147 enc_class form3_mem_prefetch_read( memory mem ) %{
2148 emit_form3_mem_reg(cbuf, this, $primary, -1,
2149 $mem$$base, $mem$$disp, $mem$$index, 0/*prefetch function many-reads*/);
2150 %}
2151
2152 enc_class form3_mem_prefetch_write( memory mem ) %{
2153 emit_form3_mem_reg(cbuf, this, $primary, -1,
2154 $mem$$base, $mem$$disp, $mem$$index, 2/*prefetch function many-writes*/);
2155 %}
2156
2157 enc_class form3_mem_reg_long_unaligned_marshal( memory mem, iRegL reg ) %{
2158 assert(Assembler::is_simm13($mem$$disp ), "need disp and disp+4");
2159 assert(Assembler::is_simm13($mem$$disp+4), "need disp and disp+4");
2160 guarantee($mem$$index == R_G0_enc, "double index?");
2161 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, R_O7_enc );
2162 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg );
2163 emit3_simm13( cbuf, Assembler::arith_op, $reg$$reg, Assembler::sllx_op3, $reg$$reg, 0x1020 );
2164 emit3( cbuf, Assembler::arith_op, $reg$$reg, Assembler::or_op3, $reg$$reg, 0, R_O7_enc );
2165 %}
2166
2167 enc_class form3_mem_reg_double_unaligned( memory mem, RegD_low reg ) %{
2168 assert(Assembler::is_simm13($mem$$disp ), "need disp and disp+4");
2169 assert(Assembler::is_simm13($mem$$disp+4), "need disp and disp+4");
2170 guarantee($mem$$index == R_G0_enc, "double index?");
2171 // Load long with 2 instructions
2172 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg+0 );
2173 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, $reg$$reg+1 );
2174 %}
2175
2176 //%%% form3_mem_plus_4_reg is a hack--get rid of it
2177 enc_class form3_mem_plus_4_reg( memory mem, iRegI dst ) %{
2178 guarantee($mem$$disp, "cannot offset a reg-reg operand by 4");
2179 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp + 4, $mem$$index, $dst$$reg);
2180 %}
2181
2182 enc_class form3_g0_rs2_rd_move( iRegI rs2, iRegI rd ) %{
2183 // Encode a reg-reg copy. If it is useless, then empty encoding.
2184 if( $rs2$$reg != $rd$$reg )
2185 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, $rs2$$reg );
2186 %}
2187
2188 // Target lo half of long
2189 enc_class form3_g0_rs2_rd_move_lo( iRegI rs2, iRegL rd ) %{
2190 // Encode a reg-reg copy. If it is useless, then empty encoding.
2191 if( $rs2$$reg != LONG_LO_REG($rd$$reg) )
2192 emit3( cbuf, Assembler::arith_op, LONG_LO_REG($rd$$reg), Assembler::or_op3, 0, 0, $rs2$$reg );
2193 %}
2194
2195 // Source lo half of long
2196 enc_class form3_g0_rs2_rd_move_lo2( iRegL rs2, iRegI rd ) %{
2197 // Encode a reg-reg copy. If it is useless, then empty encoding.
2198 if( LONG_LO_REG($rs2$$reg) != $rd$$reg )
2199 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_LO_REG($rs2$$reg) );
2200 %}
2201
2202 // Target hi half of long
2203 enc_class form3_rs1_rd_copysign_hi( iRegI rs1, iRegL rd ) %{
2204 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 31 );
2205 %}
2206
2207 // Source lo half of long, and leave it sign extended.
2208 enc_class form3_rs1_rd_signextend_lo1( iRegL rs1, iRegI rd ) %{
2209 // Sign extend low half
2210 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 0, 0 );
2211 %}
2212
2213 // Source hi half of long, and leave it sign extended.
2214 enc_class form3_rs1_rd_copy_hi1( iRegL rs1, iRegI rd ) %{
2215 // Shift high half to low half
2216 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::srlx_op3, $rs1$$reg, 32 );
2217 %}
2218
2219 // Source hi half of long
2220 enc_class form3_g0_rs2_rd_move_hi2( iRegL rs2, iRegI rd ) %{
2221 // Encode a reg-reg copy. If it is useless, then empty encoding.
2222 if( LONG_HI_REG($rs2$$reg) != $rd$$reg )
2223 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_HI_REG($rs2$$reg) );
2224 %}
2225
2226 enc_class form3_rs1_rs2_rd( iRegI rs1, iRegI rs2, iRegI rd ) %{
2227 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0, $rs2$$reg );
2228 %}
2229
2230 enc_class enc_to_bool( iRegI src, iRegI dst ) %{
2231 emit3 ( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, 0, 0, $src$$reg );
2232 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::addc_op3 , 0, 0 );
2233 %}
2234
2235 enc_class enc_ltmask( iRegI p, iRegI q, iRegI dst ) %{
2236 emit3 ( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, $p$$reg, 0, $q$$reg );
2237 // clear if nothing else is happening
2238 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, 0 );
2239 // blt,a,pn done
2240 emit2_19 ( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less, Assembler::bp_op2, Assembler::icc, 0/*predict not taken*/, 2 );
2241 // mov dst,-1 in delay slot
2242 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 );
2243 %}
2244
2245 enc_class form3_rs1_imm5_rd( iRegI rs1, immU5 imm5, iRegI rd ) %{
2246 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $imm5$$constant & 0x1F );
2247 %}
2248
2249 enc_class form3_sd_rs1_imm6_rd( iRegL rs1, immU6 imm6, iRegL rd ) %{
2250 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, ($imm6$$constant & 0x3F) | 0x1000 );
2251 %}
2252
2253 enc_class form3_sd_rs1_rs2_rd( iRegL rs1, iRegI rs2, iRegL rd ) %{
2254 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0x80, $rs2$$reg );
2255 %}
2256
2257 enc_class form3_rs1_simm13_rd( iRegI rs1, immI13 simm13, iRegI rd ) %{
2258 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $simm13$$constant );
2259 %}
2260
2261 enc_class move_return_pc_to_o1() %{
2262 emit3_simm13( cbuf, Assembler::arith_op, R_O1_enc, Assembler::add_op3, R_O7_enc, frame::pc_return_offset );
2263 %}
2264
2265 #ifdef _LP64
2266 /* %%% merge with enc_to_bool */
2267 enc_class enc_convP2B( iRegI dst, iRegP src ) %{
2268 MacroAssembler _masm(&cbuf);
2269
2270 Register src_reg = reg_to_register_object($src$$reg);
2271 Register dst_reg = reg_to_register_object($dst$$reg);
2272 __ movr(Assembler::rc_nz, src_reg, 1, dst_reg);
2273 %}
2274 #endif
2275
2276 enc_class enc_cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp ) %{
2277 // (Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)))
2278 MacroAssembler _masm(&cbuf);
2279
2280 Register p_reg = reg_to_register_object($p$$reg);
2281 Register q_reg = reg_to_register_object($q$$reg);
2282 Register y_reg = reg_to_register_object($y$$reg);
2283 Register tmp_reg = reg_to_register_object($tmp$$reg);
2284
2285 __ subcc( p_reg, q_reg, p_reg );
2286 __ add ( p_reg, y_reg, tmp_reg );
2287 __ movcc( Assembler::less, false, Assembler::icc, tmp_reg, p_reg );
2288 %}
2289
2290 enc_class form_d2i_helper(regD src, regF dst) %{
2291 // fcmp %fcc0,$src,$src
2292 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg );
2293 // branch %fcc0 not-nan, predict taken
2294 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2295 // fdtoi $src,$dst
2296 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fdtoi_opf, $src$$reg );
2297 // fitos $dst,$dst (if nan)
2298 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fitos_opf, $dst$$reg );
2299 // clear $dst (if nan)
2300 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg );
2301 // carry on here...
2302 %}
2303
2304 enc_class form_d2l_helper(regD src, regD dst) %{
2305 // fcmp %fcc0,$src,$src check for NAN
2306 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg );
2307 // branch %fcc0 not-nan, predict taken
2308 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2309 // fdtox $src,$dst convert in delay slot
2310 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fdtox_opf, $src$$reg );
2311 // fxtod $dst,$dst (if nan)
2312 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fxtod_opf, $dst$$reg );
2313 // clear $dst (if nan)
2314 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg );
2315 // carry on here...
2316 %}
2317
2318 enc_class form_f2i_helper(regF src, regF dst) %{
2319 // fcmps %fcc0,$src,$src
2320 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg );
2321 // branch %fcc0 not-nan, predict taken
2322 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2323 // fstoi $src,$dst
2324 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fstoi_opf, $src$$reg );
2325 // fitos $dst,$dst (if nan)
2326 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fitos_opf, $dst$$reg );
2327 // clear $dst (if nan)
2328 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg );
2329 // carry on here...
2330 %}
2331
2332 enc_class form_f2l_helper(regF src, regD dst) %{
2333 // fcmps %fcc0,$src,$src
2334 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg );
2335 // branch %fcc0 not-nan, predict taken
2336 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2337 // fstox $src,$dst
2338 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fstox_opf, $src$$reg );
2339 // fxtod $dst,$dst (if nan)
2340 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fxtod_opf, $dst$$reg );
2341 // clear $dst (if nan)
2342 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg );
2343 // carry on here...
2344 %}
2345
2346 enc_class form3_opf_rs2F_rdF(regF rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2347 enc_class form3_opf_rs2F_rdD(regF rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2348 enc_class form3_opf_rs2D_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2349 enc_class form3_opf_rs2D_rdD(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2350
2351 enc_class form3_opf_rs2D_lo_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg+1); %}
2352
2353 enc_class form3_opf_rs2D_hi_rdD_hi(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2354 enc_class form3_opf_rs2D_lo_rdD_lo(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg+1,$primary,0,$tertiary,$rs2$$reg+1); %}
2355
2356 enc_class form3_opf_rs1F_rs2F_rdF( regF rs1, regF rs2, regF rd ) %{
2357 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2358 %}
2359
2360 enc_class form3_opf_rs1D_rs2D_rdD( regD rs1, regD rs2, regD rd ) %{
2361 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2362 %}
2363
2364 enc_class form3_opf_rs1F_rs2F_fcc( regF rs1, regF rs2, flagsRegF fcc ) %{
2365 emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2366 %}
2367
2368 enc_class form3_opf_rs1D_rs2D_fcc( regD rs1, regD rs2, flagsRegF fcc ) %{
2369 emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2370 %}
2371
2372 enc_class form3_convI2F(regF rs2, regF rd) %{
2373 emit3(cbuf,Assembler::arith_op,$rd$$reg,Assembler::fpop1_op3,0,$secondary,$rs2$$reg);
2374 %}
2375
2376 // Encloding class for traceable jumps
2377 enc_class form_jmpl(g3RegP dest) %{
2378 emit_jmpl(cbuf, $dest$$reg);
2379 %}
2380
2381 enc_class form_jmpl_set_exception_pc(g1RegP dest) %{
2382 emit_jmpl_set_exception_pc(cbuf, $dest$$reg);
2383 %}
2384
2385 enc_class form2_nop() %{
2386 emit_nop(cbuf);
2387 %}
2388
2389 enc_class form2_illtrap() %{
2390 emit_illtrap(cbuf);
2391 %}
2392
2393
2394 // Compare longs and convert into -1, 0, 1.
2395 enc_class cmpl_flag( iRegL src1, iRegL src2, iRegI dst ) %{
2396 // CMP $src1,$src2
2397 emit3( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, $src1$$reg, 0, $src2$$reg );
2398 // blt,a,pn done
2399 emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less , Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 5 );
2400 // mov dst,-1 in delay slot
2401 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 );
2402 // bgt,a,pn done
2403 emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::greater, Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 3 );
2404 // mov dst,1 in delay slot
2405 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, 1 );
2406 // CLR $dst
2407 emit3( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3 , 0, 0, 0 );
2408 %}
2409
2410 enc_class enc_PartialSubtypeCheck() %{
2411 MacroAssembler _masm(&cbuf);
2412 __ call(StubRoutines::Sparc::partial_subtype_check(), relocInfo::runtime_call_type);
2413 __ delayed()->nop();
2414 %}
2415
2416 enc_class enc_bp( label labl, cmpOp cmp, flagsReg cc ) %{
2417 MacroAssembler _masm(&cbuf);
2418 Label* L = $labl$$label;
2419 Assembler::Predict predict_taken =
2420 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
2421
2422 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
2423 __ delayed()->nop();
2424 %}
2425
2426 enc_class enc_bpr( label labl, cmpOp_reg cmp, iRegI op1 ) %{
2427 MacroAssembler _masm(&cbuf);
2428 Label* L = $labl$$label;
2429 Assembler::Predict predict_taken =
2430 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
2431
2432 __ bpr( (Assembler::RCondition)($cmp$$cmpcode), false, predict_taken, as_Register($op1$$reg), *L);
2433 __ delayed()->nop();
2434 %}
2435
2436 enc_class enc_cmov_reg( cmpOp cmp, iRegI dst, iRegI src, immI pcc) %{
2437 int op = (Assembler::arith_op << 30) |
2438 ($dst$$reg << 25) |
2439 (Assembler::movcc_op3 << 19) |
2440 (1 << 18) | // cc2 bit for 'icc'
2441 ($cmp$$cmpcode << 14) |
2442 (0 << 13) | // select register move
2443 ($pcc$$constant << 11) | // cc1, cc0 bits for 'icc' or 'xcc'
2444 ($src$$reg << 0);
2445 cbuf.insts()->emit_int32(op);
2446 %}
2447
2448 enc_class enc_cmov_imm( cmpOp cmp, iRegI dst, immI11 src, immI pcc ) %{
2449 int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits
2450 int op = (Assembler::arith_op << 30) |
2451 ($dst$$reg << 25) |
2452 (Assembler::movcc_op3 << 19) |
2453 (1 << 18) | // cc2 bit for 'icc'
2454 ($cmp$$cmpcode << 14) |
2455 (1 << 13) | // select immediate move
2456 ($pcc$$constant << 11) | // cc1, cc0 bits for 'icc'
2457 (simm11 << 0);
2458 cbuf.insts()->emit_int32(op);
2459 %}
2460
2461 enc_class enc_cmov_reg_f( cmpOpF cmp, iRegI dst, iRegI src, flagsRegF fcc ) %{
2462 int op = (Assembler::arith_op << 30) |
2463 ($dst$$reg << 25) |
2464 (Assembler::movcc_op3 << 19) |
2465 (0 << 18) | // cc2 bit for 'fccX'
2466 ($cmp$$cmpcode << 14) |
2467 (0 << 13) | // select register move
2468 ($fcc$$reg << 11) | // cc1, cc0 bits for fcc0-fcc3
2469 ($src$$reg << 0);
2470 cbuf.insts()->emit_int32(op);
2471 %}
2472
2473 enc_class enc_cmov_imm_f( cmpOp cmp, iRegI dst, immI11 src, flagsRegF fcc ) %{
2474 int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits
2475 int op = (Assembler::arith_op << 30) |
2476 ($dst$$reg << 25) |
2477 (Assembler::movcc_op3 << 19) |
2478 (0 << 18) | // cc2 bit for 'fccX'
2479 ($cmp$$cmpcode << 14) |
2480 (1 << 13) | // select immediate move
2481 ($fcc$$reg << 11) | // cc1, cc0 bits for fcc0-fcc3
2482 (simm11 << 0);
2483 cbuf.insts()->emit_int32(op);
2484 %}
2485
2486 enc_class enc_cmovf_reg( cmpOp cmp, regD dst, regD src, immI pcc ) %{
2487 int op = (Assembler::arith_op << 30) |
2488 ($dst$$reg << 25) |
2489 (Assembler::fpop2_op3 << 19) |
2490 (0 << 18) |
2491 ($cmp$$cmpcode << 14) |
2492 (1 << 13) | // select register move
2493 ($pcc$$constant << 11) | // cc1-cc0 bits for 'icc' or 'xcc'
2494 ($primary << 5) | // select single, double or quad
2495 ($src$$reg << 0);
2496 cbuf.insts()->emit_int32(op);
2497 %}
2498
2499 enc_class enc_cmovff_reg( cmpOpF cmp, flagsRegF fcc, regD dst, regD src ) %{
2500 int op = (Assembler::arith_op << 30) |
2501 ($dst$$reg << 25) |
2502 (Assembler::fpop2_op3 << 19) |
2503 (0 << 18) |
2504 ($cmp$$cmpcode << 14) |
2505 ($fcc$$reg << 11) | // cc2-cc0 bits for 'fccX'
2506 ($primary << 5) | // select single, double or quad
2507 ($src$$reg << 0);
2508 cbuf.insts()->emit_int32(op);
2509 %}
2510
2511 // Used by the MIN/MAX encodings. Same as a CMOV, but
2512 // the condition comes from opcode-field instead of an argument.
2513 enc_class enc_cmov_reg_minmax( iRegI dst, iRegI src ) %{
2514 int op = (Assembler::arith_op << 30) |
2515 ($dst$$reg << 25) |
2516 (Assembler::movcc_op3 << 19) |
2517 (1 << 18) | // cc2 bit for 'icc'
2518 ($primary << 14) |
2519 (0 << 13) | // select register move
2520 (0 << 11) | // cc1, cc0 bits for 'icc'
2521 ($src$$reg << 0);
2522 cbuf.insts()->emit_int32(op);
2523 %}
2524
2525 enc_class enc_cmov_reg_minmax_long( iRegL dst, iRegL src ) %{
2526 int op = (Assembler::arith_op << 30) |
2527 ($dst$$reg << 25) |
2528 (Assembler::movcc_op3 << 19) |
2529 (6 << 16) | // cc2 bit for 'xcc'
2530 ($primary << 14) |
2531 (0 << 13) | // select register move
2532 (0 << 11) | // cc1, cc0 bits for 'icc'
2533 ($src$$reg << 0);
2534 cbuf.insts()->emit_int32(op);
2535 %}
2536
2537 enc_class Set13( immI13 src, iRegI rd ) %{
2538 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, $src$$constant );
2539 %}
2540
2541 enc_class SetHi22( immI src, iRegI rd ) %{
2542 emit2_22( cbuf, Assembler::branch_op, $rd$$reg, Assembler::sethi_op2, $src$$constant );
2543 %}
2544
2545 enc_class Set32( immI src, iRegI rd ) %{
2546 MacroAssembler _masm(&cbuf);
2547 __ set($src$$constant, reg_to_register_object($rd$$reg));
2548 %}
2549
2550 enc_class call_epilog %{
2551 if( VerifyStackAtCalls ) {
2552 MacroAssembler _masm(&cbuf);
2553 int framesize = ra_->C->frame_slots() << LogBytesPerInt;
2554 Register temp_reg = G3;
2555 __ add(SP, framesize, temp_reg);
2556 __ cmp(temp_reg, FP);
2557 __ breakpoint_trap(Assembler::notEqual, Assembler::ptr_cc);
2558 }
2559 %}
2560
2561 // Long values come back from native calls in O0:O1 in the 32-bit VM, copy the value
2562 // to G1 so the register allocator will not have to deal with the misaligned register
2563 // pair.
2564 enc_class adjust_long_from_native_call %{
2565 #ifndef _LP64
2566 if (returns_long()) {
2567 // sllx O0,32,O0
2568 emit3_simm13( cbuf, Assembler::arith_op, R_O0_enc, Assembler::sllx_op3, R_O0_enc, 0x1020 );
2569 // srl O1,0,O1
2570 emit3_simm13( cbuf, Assembler::arith_op, R_O1_enc, Assembler::srl_op3, R_O1_enc, 0x0000 );
2571 // or O0,O1,G1
2572 emit3 ( cbuf, Assembler::arith_op, R_G1_enc, Assembler:: or_op3, R_O0_enc, 0, R_O1_enc );
2573 }
2574 #endif
2575 %}
2576
2577 enc_class Java_To_Runtime (method meth) %{ // CALL Java_To_Runtime
2578 // CALL directly to the runtime
2579 // The user of this is responsible for ensuring that R_L7 is empty (killed).
2580 emit_call_reloc(cbuf, $meth$$method, relocInfo::runtime_call_type,
2581 /*preserve_g2=*/true);
2582 %}
2583
2584 enc_class preserve_SP %{
2585 MacroAssembler _masm(&cbuf);
2586 __ mov(SP, L7_mh_SP_save);
2587 %}
2588
2589 enc_class restore_SP %{
2590 MacroAssembler _masm(&cbuf);
2591 __ mov(L7_mh_SP_save, SP);
2592 %}
2593
2594 enc_class Java_Static_Call (method meth) %{ // JAVA STATIC CALL
2595 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine
2596 // who we intended to call.
2597 if ( !_method ) {
2598 emit_call_reloc(cbuf, $meth$$method, relocInfo::runtime_call_type);
2599 } else if (_optimized_virtual) {
2600 emit_call_reloc(cbuf, $meth$$method, relocInfo::opt_virtual_call_type);
2601 } else {
2602 emit_call_reloc(cbuf, $meth$$method, relocInfo::static_call_type);
2603 }
2604 if( _method ) { // Emit stub for static call
2605 emit_java_to_interp(cbuf);
2606 }
2607 %}
2608
2609 enc_class Java_Dynamic_Call (method meth) %{ // JAVA DYNAMIC CALL
2610 MacroAssembler _masm(&cbuf);
2611 __ set_inst_mark();
2612 int vtable_index = this->_vtable_index;
2613 // MachCallDynamicJavaNode::ret_addr_offset uses this same test
2614 if (vtable_index < 0) {
2615 // must be invalid_vtable_index, not nonvirtual_vtable_index
2616 assert(vtable_index == methodOopDesc::invalid_vtable_index, "correct sentinel value");
2617 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode());
2618 assert(G5_ic_reg == G5_inline_cache_reg, "G5_inline_cache_reg used in assemble_ic_buffer_code()");
2619 assert(G5_ic_reg == G5_megamorphic_method, "G5_megamorphic_method used in megamorphic call stub");
2620 // !!!!!
2621 // Generate "set 0x01, R_G5", placeholder instruction to load oop-info
2622 // emit_call_dynamic_prologue( cbuf );
2623 __ set_oop((jobject)Universe::non_oop_word(), G5_ic_reg);
2624
2625 address virtual_call_oop_addr = __ inst_mark();
2626 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine
2627 // who we intended to call.
2628 __ relocate(virtual_call_Relocation::spec(virtual_call_oop_addr));
2629 emit_call_reloc(cbuf, $meth$$method, relocInfo::none);
2630 } else {
2631 assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
2632 // Just go thru the vtable
2633 // get receiver klass (receiver already checked for non-null)
2634 // If we end up going thru a c2i adapter interpreter expects method in G5
2635 int off = __ offset();
2636 __ load_klass(O0, G3_scratch);
2637 int klass_load_size;
2638 if (UseCompressedOops) {
2639 assert(Universe::heap() != NULL, "java heap should be initialized");
2640 if (Universe::narrow_oop_base() == NULL)
2641 klass_load_size = 2*BytesPerInstWord;
2642 else
2643 klass_load_size = 3*BytesPerInstWord;
2644 } else {
2645 klass_load_size = 1*BytesPerInstWord;
2646 }
2647 int entry_offset = instanceKlass::vtable_start_offset() + vtable_index*vtableEntry::size();
2648 int v_off = entry_offset*wordSize + vtableEntry::method_offset_in_bytes();
2649 if (Assembler::is_simm13(v_off)) {
2650 __ ld_ptr(G3, v_off, G5_method);
2651 } else {
2652 // Generate 2 instructions
2653 __ Assembler::sethi(v_off & ~0x3ff, G5_method);
2654 __ or3(G5_method, v_off & 0x3ff, G5_method);
2655 // ld_ptr, set_hi, set
2656 assert(__ offset() - off == klass_load_size + 2*BytesPerInstWord,
2657 "Unexpected instruction size(s)");
2658 __ ld_ptr(G3, G5_method, G5_method);
2659 }
2660 // NOTE: for vtable dispatches, the vtable entry will never be null.
2661 // However it may very well end up in handle_wrong_method if the
2662 // method is abstract for the particular class.
2663 __ ld_ptr(G5_method, in_bytes(methodOopDesc::from_compiled_offset()), G3_scratch);
2664 // jump to target (either compiled code or c2iadapter)
2665 __ jmpl(G3_scratch, G0, O7);
2666 __ delayed()->nop();
2667 }
2668 %}
2669
2670 enc_class Java_Compiled_Call (method meth) %{ // JAVA COMPILED CALL
2671 MacroAssembler _masm(&cbuf);
2672
2673 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode());
2674 Register temp_reg = G3; // caller must kill G3! We cannot reuse G5_ic_reg here because
2675 // we might be calling a C2I adapter which needs it.
2676
2677 assert(temp_reg != G5_ic_reg, "conflicting registers");
2678 // Load nmethod
2679 __ ld_ptr(G5_ic_reg, in_bytes(methodOopDesc::from_compiled_offset()), temp_reg);
2680
2681 // CALL to compiled java, indirect the contents of G3
2682 __ set_inst_mark();
2683 __ callr(temp_reg, G0);
2684 __ delayed()->nop();
2685 %}
2686
2687 enc_class idiv_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst) %{
2688 MacroAssembler _masm(&cbuf);
2689 Register Rdividend = reg_to_register_object($src1$$reg);
2690 Register Rdivisor = reg_to_register_object($src2$$reg);
2691 Register Rresult = reg_to_register_object($dst$$reg);
2692
2693 __ sra(Rdivisor, 0, Rdivisor);
2694 __ sra(Rdividend, 0, Rdividend);
2695 __ sdivx(Rdividend, Rdivisor, Rresult);
2696 %}
2697
2698 enc_class idiv_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst) %{
2699 MacroAssembler _masm(&cbuf);
2700
2701 Register Rdividend = reg_to_register_object($src1$$reg);
2702 int divisor = $imm$$constant;
2703 Register Rresult = reg_to_register_object($dst$$reg);
2704
2705 __ sra(Rdividend, 0, Rdividend);
2706 __ sdivx(Rdividend, divisor, Rresult);
2707 %}
2708
2709 enc_class enc_mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2) %{
2710 MacroAssembler _masm(&cbuf);
2711 Register Rsrc1 = reg_to_register_object($src1$$reg);
2712 Register Rsrc2 = reg_to_register_object($src2$$reg);
2713 Register Rdst = reg_to_register_object($dst$$reg);
2714
2715 __ sra( Rsrc1, 0, Rsrc1 );
2716 __ sra( Rsrc2, 0, Rsrc2 );
2717 __ mulx( Rsrc1, Rsrc2, Rdst );
2718 __ srlx( Rdst, 32, Rdst );
2719 %}
2720
2721 enc_class irem_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst, o7RegL scratch) %{
2722 MacroAssembler _masm(&cbuf);
2723 Register Rdividend = reg_to_register_object($src1$$reg);
2724 Register Rdivisor = reg_to_register_object($src2$$reg);
2725 Register Rresult = reg_to_register_object($dst$$reg);
2726 Register Rscratch = reg_to_register_object($scratch$$reg);
2727
2728 assert(Rdividend != Rscratch, "");
2729 assert(Rdivisor != Rscratch, "");
2730
2731 __ sra(Rdividend, 0, Rdividend);
2732 __ sra(Rdivisor, 0, Rdivisor);
2733 __ sdivx(Rdividend, Rdivisor, Rscratch);
2734 __ mulx(Rscratch, Rdivisor, Rscratch);
2735 __ sub(Rdividend, Rscratch, Rresult);
2736 %}
2737
2738 enc_class irem_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst, o7RegL scratch) %{
2739 MacroAssembler _masm(&cbuf);
2740
2741 Register Rdividend = reg_to_register_object($src1$$reg);
2742 int divisor = $imm$$constant;
2743 Register Rresult = reg_to_register_object($dst$$reg);
2744 Register Rscratch = reg_to_register_object($scratch$$reg);
2745
2746 assert(Rdividend != Rscratch, "");
2747
2748 __ sra(Rdividend, 0, Rdividend);
2749 __ sdivx(Rdividend, divisor, Rscratch);
2750 __ mulx(Rscratch, divisor, Rscratch);
2751 __ sub(Rdividend, Rscratch, Rresult);
2752 %}
2753
2754 enc_class fabss (sflt_reg dst, sflt_reg src) %{
2755 MacroAssembler _masm(&cbuf);
2756
2757 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg);
2758 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg);
2759
2760 __ fabs(FloatRegisterImpl::S, Fsrc, Fdst);
2761 %}
2762
2763 enc_class fabsd (dflt_reg dst, dflt_reg src) %{
2764 MacroAssembler _masm(&cbuf);
2765
2766 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2767 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2768
2769 __ fabs(FloatRegisterImpl::D, Fsrc, Fdst);
2770 %}
2771
2772 enc_class fnegd (dflt_reg dst, dflt_reg src) %{
2773 MacroAssembler _masm(&cbuf);
2774
2775 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2776 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2777
2778 __ fneg(FloatRegisterImpl::D, Fsrc, Fdst);
2779 %}
2780
2781 enc_class fsqrts (sflt_reg dst, sflt_reg src) %{
2782 MacroAssembler _masm(&cbuf);
2783
2784 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg);
2785 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg);
2786
2787 __ fsqrt(FloatRegisterImpl::S, Fsrc, Fdst);
2788 %}
2789
2790 enc_class fsqrtd (dflt_reg dst, dflt_reg src) %{
2791 MacroAssembler _masm(&cbuf);
2792
2793 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2794 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2795
2796 __ fsqrt(FloatRegisterImpl::D, Fsrc, Fdst);
2797 %}
2798
2799 enc_class fmovs (dflt_reg dst, dflt_reg src) %{
2800 MacroAssembler _masm(&cbuf);
2801
2802 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg);
2803 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg);
2804
2805 __ fmov(FloatRegisterImpl::S, Fsrc, Fdst);
2806 %}
2807
2808 enc_class fmovd (dflt_reg dst, dflt_reg src) %{
2809 MacroAssembler _masm(&cbuf);
2810
2811 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2812 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2813
2814 __ fmov(FloatRegisterImpl::D, Fsrc, Fdst);
2815 %}
2816
2817 enc_class Fast_Lock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{
2818 MacroAssembler _masm(&cbuf);
2819
2820 Register Roop = reg_to_register_object($oop$$reg);
2821 Register Rbox = reg_to_register_object($box$$reg);
2822 Register Rscratch = reg_to_register_object($scratch$$reg);
2823 Register Rmark = reg_to_register_object($scratch2$$reg);
2824
2825 assert(Roop != Rscratch, "");
2826 assert(Roop != Rmark, "");
2827 assert(Rbox != Rscratch, "");
2828 assert(Rbox != Rmark, "");
2829
2830 __ compiler_lock_object(Roop, Rmark, Rbox, Rscratch, _counters, UseBiasedLocking && !UseOptoBiasInlining);
2831 %}
2832
2833 enc_class Fast_Unlock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{
2834 MacroAssembler _masm(&cbuf);
2835
2836 Register Roop = reg_to_register_object($oop$$reg);
2837 Register Rbox = reg_to_register_object($box$$reg);
2838 Register Rscratch = reg_to_register_object($scratch$$reg);
2839 Register Rmark = reg_to_register_object($scratch2$$reg);
2840
2841 assert(Roop != Rscratch, "");
2842 assert(Roop != Rmark, "");
2843 assert(Rbox != Rscratch, "");
2844 assert(Rbox != Rmark, "");
2845
2846 __ compiler_unlock_object(Roop, Rmark, Rbox, Rscratch, UseBiasedLocking && !UseOptoBiasInlining);
2847 %}
2848
2849 enc_class enc_cas( iRegP mem, iRegP old, iRegP new ) %{
2850 MacroAssembler _masm(&cbuf);
2851 Register Rmem = reg_to_register_object($mem$$reg);
2852 Register Rold = reg_to_register_object($old$$reg);
2853 Register Rnew = reg_to_register_object($new$$reg);
2854
2855 // casx_under_lock picks 1 of 3 encodings:
2856 // For 32-bit pointers you get a 32-bit CAS
2857 // For 64-bit pointers you get a 64-bit CASX
2858 __ casn(Rmem, Rold, Rnew); // Swap(*Rmem,Rnew) if *Rmem == Rold
2859 __ cmp( Rold, Rnew );
2860 %}
2861
2862 enc_class enc_casx( iRegP mem, iRegL old, iRegL new) %{
2863 Register Rmem = reg_to_register_object($mem$$reg);
2864 Register Rold = reg_to_register_object($old$$reg);
2865 Register Rnew = reg_to_register_object($new$$reg);
2866
2867 MacroAssembler _masm(&cbuf);
2868 __ mov(Rnew, O7);
2869 __ casx(Rmem, Rold, O7);
2870 __ cmp( Rold, O7 );
2871 %}
2872
2873 // raw int cas, used for compareAndSwap
2874 enc_class enc_casi( iRegP mem, iRegL old, iRegL new) %{
2875 Register Rmem = reg_to_register_object($mem$$reg);
2876 Register Rold = reg_to_register_object($old$$reg);
2877 Register Rnew = reg_to_register_object($new$$reg);
2878
2879 MacroAssembler _masm(&cbuf);
2880 __ mov(Rnew, O7);
2881 __ cas(Rmem, Rold, O7);
2882 __ cmp( Rold, O7 );
2883 %}
2884
2885 enc_class enc_lflags_ne_to_boolean( iRegI res ) %{
2886 Register Rres = reg_to_register_object($res$$reg);
2887
2888 MacroAssembler _masm(&cbuf);
2889 __ mov(1, Rres);
2890 __ movcc( Assembler::notEqual, false, Assembler::xcc, G0, Rres );
2891 %}
2892
2893 enc_class enc_iflags_ne_to_boolean( iRegI res ) %{
2894 Register Rres = reg_to_register_object($res$$reg);
2895
2896 MacroAssembler _masm(&cbuf);
2897 __ mov(1, Rres);
2898 __ movcc( Assembler::notEqual, false, Assembler::icc, G0, Rres );
2899 %}
2900
2901 enc_class floating_cmp ( iRegP dst, regF src1, regF src2 ) %{
2902 MacroAssembler _masm(&cbuf);
2903 Register Rdst = reg_to_register_object($dst$$reg);
2904 FloatRegister Fsrc1 = $primary ? reg_to_SingleFloatRegister_object($src1$$reg)
2905 : reg_to_DoubleFloatRegister_object($src1$$reg);
2906 FloatRegister Fsrc2 = $primary ? reg_to_SingleFloatRegister_object($src2$$reg)
2907 : reg_to_DoubleFloatRegister_object($src2$$reg);
2908
2909 // Convert condition code fcc0 into -1,0,1; unordered reports less-than (-1)
2910 __ float_cmp( $primary, -1, Fsrc1, Fsrc2, Rdst);
2911 %}
2912
2913
2914 enc_class enc_String_Compare(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result) %{
2915 Label Ldone, Lloop;
2916 MacroAssembler _masm(&cbuf);
2917
2918 Register str1_reg = reg_to_register_object($str1$$reg);
2919 Register str2_reg = reg_to_register_object($str2$$reg);
2920 Register cnt1_reg = reg_to_register_object($cnt1$$reg);
2921 Register cnt2_reg = reg_to_register_object($cnt2$$reg);
2922 Register result_reg = reg_to_register_object($result$$reg);
2923
2924 assert(result_reg != str1_reg &&
2925 result_reg != str2_reg &&
2926 result_reg != cnt1_reg &&
2927 result_reg != cnt2_reg ,
2928 "need different registers");
2929
2930 // Compute the minimum of the string lengths(str1_reg) and the
2931 // difference of the string lengths (stack)
2932
2933 // See if the lengths are different, and calculate min in str1_reg.
2934 // Stash diff in O7 in case we need it for a tie-breaker.
2935 Label Lskip;
2936 __ subcc(cnt1_reg, cnt2_reg, O7);
2937 __ sll(cnt1_reg, exact_log2(sizeof(jchar)), cnt1_reg); // scale the limit
2938 __ br(Assembler::greater, true, Assembler::pt, Lskip);
2939 // cnt2 is shorter, so use its count:
2940 __ delayed()->sll(cnt2_reg, exact_log2(sizeof(jchar)), cnt1_reg); // scale the limit
2941 __ bind(Lskip);
2942
2943 // reallocate cnt1_reg, cnt2_reg, result_reg
2944 // Note: limit_reg holds the string length pre-scaled by 2
2945 Register limit_reg = cnt1_reg;
2946 Register chr2_reg = cnt2_reg;
2947 Register chr1_reg = result_reg;
2948 // str{12} are the base pointers
2949
2950 // Is the minimum length zero?
2951 __ cmp(limit_reg, (int)(0 * sizeof(jchar))); // use cast to resolve overloading ambiguity
2952 __ br(Assembler::equal, true, Assembler::pn, Ldone);
2953 __ delayed()->mov(O7, result_reg); // result is difference in lengths
2954
2955 // Load first characters
2956 __ lduh(str1_reg, 0, chr1_reg);
2957 __ lduh(str2_reg, 0, chr2_reg);
2958
2959 // Compare first characters
2960 __ subcc(chr1_reg, chr2_reg, chr1_reg);
2961 __ br(Assembler::notZero, false, Assembler::pt, Ldone);
2962 assert(chr1_reg == result_reg, "result must be pre-placed");
2963 __ delayed()->nop();
2964
2965 {
2966 // Check after comparing first character to see if strings are equivalent
2967 Label LSkip2;
2968 // Check if the strings start at same location
2969 __ cmp(str1_reg, str2_reg);
2970 __ brx(Assembler::notEqual, true, Assembler::pt, LSkip2);
2971 __ delayed()->nop();
2972
2973 // Check if the length difference is zero (in O7)
2974 __ cmp(G0, O7);
2975 __ br(Assembler::equal, true, Assembler::pn, Ldone);
2976 __ delayed()->mov(G0, result_reg); // result is zero
2977
2978 // Strings might not be equal
2979 __ bind(LSkip2);
2980 }
2981
2982 __ subcc(limit_reg, 1 * sizeof(jchar), chr1_reg);
2983 __ br(Assembler::equal, true, Assembler::pn, Ldone);
2984 __ delayed()->mov(O7, result_reg); // result is difference in lengths
2985
2986 // Shift str1_reg and str2_reg to the end of the arrays, negate limit
2987 __ add(str1_reg, limit_reg, str1_reg);
2988 __ add(str2_reg, limit_reg, str2_reg);
2989 __ neg(chr1_reg, limit_reg); // limit = -(limit-2)
2990
2991 // Compare the rest of the characters
2992 __ lduh(str1_reg, limit_reg, chr1_reg);
2993 __ bind(Lloop);
2994 // __ lduh(str1_reg, limit_reg, chr1_reg); // hoisted
2995 __ lduh(str2_reg, limit_reg, chr2_reg);
2996 __ subcc(chr1_reg, chr2_reg, chr1_reg);
2997 __ br(Assembler::notZero, false, Assembler::pt, Ldone);
2998 assert(chr1_reg == result_reg, "result must be pre-placed");
2999 __ delayed()->inccc(limit_reg, sizeof(jchar));
3000 // annul LDUH if branch is not taken to prevent access past end of string
3001 __ br(Assembler::notZero, true, Assembler::pt, Lloop);
3002 __ delayed()->lduh(str1_reg, limit_reg, chr1_reg); // hoisted
3003
3004 // If strings are equal up to min length, return the length difference.
3005 __ mov(O7, result_reg);
3006
3007 // Otherwise, return the difference between the first mismatched chars.
3008 __ bind(Ldone);
3009 %}
3010
3011 enc_class enc_String_Equals(o0RegP str1, o1RegP str2, g3RegI cnt, notemp_iRegI result) %{
3012 Label Lword_loop, Lpost_word, Lchar, Lchar_loop, Ldone;
3013 MacroAssembler _masm(&cbuf);
3014
3015 Register str1_reg = reg_to_register_object($str1$$reg);
3016 Register str2_reg = reg_to_register_object($str2$$reg);
3017 Register cnt_reg = reg_to_register_object($cnt$$reg);
3018 Register tmp1_reg = O7;
3019 Register result_reg = reg_to_register_object($result$$reg);
3020
3021 assert(result_reg != str1_reg &&
3022 result_reg != str2_reg &&
3023 result_reg != cnt_reg &&
3024 result_reg != tmp1_reg ,
3025 "need different registers");
3026
3027 __ cmp(str1_reg, str2_reg); //same char[] ?
3028 __ brx(Assembler::equal, true, Assembler::pn, Ldone);
3029 __ delayed()->add(G0, 1, result_reg);
3030
3031 __ cmp_zero_and_br(Assembler::zero, cnt_reg, Ldone, true, Assembler::pn);
3032 __ delayed()->add(G0, 1, result_reg); // count == 0
3033
3034 //rename registers
3035 Register limit_reg = cnt_reg;
3036 Register chr1_reg = result_reg;
3037 Register chr2_reg = tmp1_reg;
3038
3039 //check for alignment and position the pointers to the ends
3040 __ or3(str1_reg, str2_reg, chr1_reg);
3041 __ andcc(chr1_reg, 0x3, chr1_reg);
3042 // notZero means at least one not 4-byte aligned.
3043 // We could optimize the case when both arrays are not aligned
3044 // but it is not frequent case and it requires additional checks.
3045 __ br(Assembler::notZero, false, Assembler::pn, Lchar); // char by char compare
3046 __ delayed()->sll(limit_reg, exact_log2(sizeof(jchar)), limit_reg); // set byte count
3047
3048 // Compare char[] arrays aligned to 4 bytes.
3049 __ char_arrays_equals(str1_reg, str2_reg, limit_reg, result_reg,
3050 chr1_reg, chr2_reg, Ldone);
3051 __ ba(Ldone);
3052 __ delayed()->add(G0, 1, result_reg);
3053
3054 // char by char compare
3055 __ bind(Lchar);
3056 __ add(str1_reg, limit_reg, str1_reg);
3057 __ add(str2_reg, limit_reg, str2_reg);
3058 __ neg(limit_reg); //negate count
3059
3060 __ lduh(str1_reg, limit_reg, chr1_reg);
3061 // Lchar_loop
3062 __ bind(Lchar_loop);
3063 __ lduh(str2_reg, limit_reg, chr2_reg);
3064 __ cmp(chr1_reg, chr2_reg);
3065 __ br(Assembler::notEqual, true, Assembler::pt, Ldone);
3066 __ delayed()->mov(G0, result_reg); //not equal
3067 __ inccc(limit_reg, sizeof(jchar));
3068 // annul LDUH if branch is not taken to prevent access past end of string
3069 __ br(Assembler::notZero, true, Assembler::pt, Lchar_loop);
3070 __ delayed()->lduh(str1_reg, limit_reg, chr1_reg); // hoisted
3071
3072 __ add(G0, 1, result_reg); //equal
3073
3074 __ bind(Ldone);
3075 %}
3076
3077 enc_class enc_Array_Equals(o0RegP ary1, o1RegP ary2, g3RegP tmp1, notemp_iRegI result) %{
3078 Label Lvector, Ldone, Lloop;
3079 MacroAssembler _masm(&cbuf);
3080
3081 Register ary1_reg = reg_to_register_object($ary1$$reg);
3082 Register ary2_reg = reg_to_register_object($ary2$$reg);
3083 Register tmp1_reg = reg_to_register_object($tmp1$$reg);
3084 Register tmp2_reg = O7;
3085 Register result_reg = reg_to_register_object($result$$reg);
3086
3087 int length_offset = arrayOopDesc::length_offset_in_bytes();
3088 int base_offset = arrayOopDesc::base_offset_in_bytes(T_CHAR);
3089
3090 // return true if the same array
3091 __ cmp(ary1_reg, ary2_reg);
3092 __ brx(Assembler::equal, true, Assembler::pn, Ldone);
3093 __ delayed()->add(G0, 1, result_reg); // equal
3094
3095 __ br_null(ary1_reg, true, Assembler::pn, Ldone);
3096 __ delayed()->mov(G0, result_reg); // not equal
3097
3098 __ br_null(ary2_reg, true, Assembler::pn, Ldone);
3099 __ delayed()->mov(G0, result_reg); // not equal
3100
3101 //load the lengths of arrays
3102 __ ld(Address(ary1_reg, length_offset), tmp1_reg);
3103 __ ld(Address(ary2_reg, length_offset), tmp2_reg);
3104
3105 // return false if the two arrays are not equal length
3106 __ cmp(tmp1_reg, tmp2_reg);
3107 __ br(Assembler::notEqual, true, Assembler::pn, Ldone);
3108 __ delayed()->mov(G0, result_reg); // not equal
3109
3110 __ cmp_zero_and_br(Assembler::zero, tmp1_reg, Ldone, true, Assembler::pn);
3111 __ delayed()->add(G0, 1, result_reg); // zero-length arrays are equal
3112
3113 // load array addresses
3114 __ add(ary1_reg, base_offset, ary1_reg);
3115 __ add(ary2_reg, base_offset, ary2_reg);
3116
3117 // renaming registers
3118 Register chr1_reg = result_reg; // for characters in ary1
3119 Register chr2_reg = tmp2_reg; // for characters in ary2
3120 Register limit_reg = tmp1_reg; // length
3121
3122 // set byte count
3123 __ sll(limit_reg, exact_log2(sizeof(jchar)), limit_reg);
3124
3125 // Compare char[] arrays aligned to 4 bytes.
3126 __ char_arrays_equals(ary1_reg, ary2_reg, limit_reg, result_reg,
3127 chr1_reg, chr2_reg, Ldone);
3128 __ add(G0, 1, result_reg); // equals
3129
3130 __ bind(Ldone);
3131 %}
3132
3133 enc_class enc_rethrow() %{
3134 cbuf.set_insts_mark();
3135 Register temp_reg = G3;
3136 AddressLiteral rethrow_stub(OptoRuntime::rethrow_stub());
3137 assert(temp_reg != reg_to_register_object(R_I0_num), "temp must not break oop_reg");
3138 MacroAssembler _masm(&cbuf);
3139 #ifdef ASSERT
3140 __ save_frame(0);
3141 AddressLiteral last_rethrow_addrlit(&last_rethrow);
3142 __ sethi(last_rethrow_addrlit, L1);
3143 Address addr(L1, last_rethrow_addrlit.low10());
3144 __ get_pc(L2);
3145 __ inc(L2, 3 * BytesPerInstWord); // skip this & 2 more insns to point at jump_to
3146 __ st_ptr(L2, addr);
3147 __ restore();
3148 #endif
3149 __ JUMP(rethrow_stub, temp_reg, 0); // sethi;jmp
3150 __ delayed()->nop();
3151 %}
3152
3153 enc_class emit_mem_nop() %{
3154 // Generates the instruction LDUXA [o6,g0],#0x82,g0
3155 cbuf.insts()->emit_int32((unsigned int) 0xc0839040);
3156 %}
3157
3158 enc_class emit_fadd_nop() %{
3159 // Generates the instruction FMOVS f31,f31
3160 cbuf.insts()->emit_int32((unsigned int) 0xbfa0003f);
3161 %}
3162
3163 enc_class emit_br_nop() %{
3164 // Generates the instruction BPN,PN .
3165 cbuf.insts()->emit_int32((unsigned int) 0x00400000);
3166 %}
3167
3168 enc_class enc_membar_acquire %{
3169 MacroAssembler _masm(&cbuf);
3170 __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::LoadLoad) );
3171 %}
3172
3173 enc_class enc_membar_release %{
3174 MacroAssembler _masm(&cbuf);
3175 __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::StoreStore) );
3176 %}
3177
3178 enc_class enc_membar_volatile %{
3179 MacroAssembler _masm(&cbuf);
3180 __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad) );
3181 %}
3182
3183 %}
3184
3185 //----------FRAME--------------------------------------------------------------
3186 // Definition of frame structure and management information.
3187 //
3188 // S T A C K L A Y O U T Allocators stack-slot number
3189 // | (to get allocators register number
3190 // G Owned by | | v add VMRegImpl::stack0)
3191 // r CALLER | |
3192 // o | +--------+ pad to even-align allocators stack-slot
3193 // w V | pad0 | numbers; owned by CALLER
3194 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned
3195 // h ^ | in | 5
3196 // | | args | 4 Holes in incoming args owned by SELF
3197 // | | | | 3
3198 // | | +--------+
3199 // V | | old out| Empty on Intel, window on Sparc
3200 // | old |preserve| Must be even aligned.
3201 // | SP-+--------+----> Matcher::_old_SP, 8 (or 16 in LP64)-byte aligned
3202 // | | in | 3 area for Intel ret address
3203 // Owned by |preserve| Empty on Sparc.
3204 // SELF +--------+
3205 // | | pad2 | 2 pad to align old SP
3206 // | +--------+ 1
3207 // | | locks | 0
3208 // | +--------+----> VMRegImpl::stack0, 8 (or 16 in LP64)-byte aligned
3209 // | | pad1 | 11 pad to align new SP
3210 // | +--------+
3211 // | | | 10
3212 // | | spills | 9 spills
3213 // V | | 8 (pad0 slot for callee)
3214 // -----------+--------+----> Matcher::_out_arg_limit, unaligned
3215 // ^ | out | 7
3216 // | | args | 6 Holes in outgoing args owned by CALLEE
3217 // Owned by +--------+
3218 // CALLEE | new out| 6 Empty on Intel, window on Sparc
3219 // | new |preserve| Must be even-aligned.
3220 // | SP-+--------+----> Matcher::_new_SP, even aligned
3221 // | | |
3222 //
3223 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is
3224 // known from SELF's arguments and the Java calling convention.
3225 // Region 6-7 is determined per call site.
3226 // Note 2: If the calling convention leaves holes in the incoming argument
3227 // area, those holes are owned by SELF. Holes in the outgoing area
3228 // are owned by the CALLEE. Holes should not be nessecary in the
3229 // incoming area, as the Java calling convention is completely under
3230 // the control of the AD file. Doubles can be sorted and packed to
3231 // avoid holes. Holes in the outgoing arguments may be necessary for
3232 // varargs C calling conventions.
3233 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is
3234 // even aligned with pad0 as needed.
3235 // Region 6 is even aligned. Region 6-7 is NOT even aligned;
3236 // region 6-11 is even aligned; it may be padded out more so that
3237 // the region from SP to FP meets the minimum stack alignment.
3238
3239 frame %{
3240 // What direction does stack grow in (assumed to be same for native & Java)
3241 stack_direction(TOWARDS_LOW);
3242
3243 // These two registers define part of the calling convention
3244 // between compiled code and the interpreter.
3245 inline_cache_reg(R_G5); // Inline Cache Register or methodOop for I2C
3246 interpreter_method_oop_reg(R_G5); // Method Oop Register when calling interpreter
3247
3248 // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset]
3249 cisc_spilling_operand_name(indOffset);
3250
3251 // Number of stack slots consumed by a Monitor enter
3252 #ifdef _LP64
3253 sync_stack_slots(2);
3254 #else
3255 sync_stack_slots(1);
3256 #endif
3257
3258 // Compiled code's Frame Pointer
3259 frame_pointer(R_SP);
3260
3261 // Stack alignment requirement
3262 stack_alignment(StackAlignmentInBytes);
3263 // LP64: Alignment size in bytes (128-bit -> 16 bytes)
3264 // !LP64: Alignment size in bytes (64-bit -> 8 bytes)
3265
3266 // Number of stack slots between incoming argument block and the start of
3267 // a new frame. The PROLOG must add this many slots to the stack. The
3268 // EPILOG must remove this many slots.
3269 in_preserve_stack_slots(0);
3270
3271 // Number of outgoing stack slots killed above the out_preserve_stack_slots
3272 // for calls to C. Supports the var-args backing area for register parms.
3273 // ADLC doesn't support parsing expressions, so I folded the math by hand.
3274 #ifdef _LP64
3275 // (callee_register_argument_save_area_words (6) + callee_aggregate_return_pointer_words (0)) * 2-stack-slots-per-word
3276 varargs_C_out_slots_killed(12);
3277 #else
3278 // (callee_register_argument_save_area_words (6) + callee_aggregate_return_pointer_words (1)) * 1-stack-slots-per-word
3279 varargs_C_out_slots_killed( 7);
3280 #endif
3281
3282 // The after-PROLOG location of the return address. Location of
3283 // return address specifies a type (REG or STACK) and a number
3284 // representing the register number (i.e. - use a register name) or
3285 // stack slot.
3286 return_addr(REG R_I7); // Ret Addr is in register I7
3287
3288 // Body of function which returns an OptoRegs array locating
3289 // arguments either in registers or in stack slots for calling
3290 // java
3291 calling_convention %{
3292 (void) SharedRuntime::java_calling_convention(sig_bt, regs, length, is_outgoing);
3293
3294 %}
3295
3296 // Body of function which returns an OptoRegs array locating
3297 // arguments either in registers or in stack slots for calling
3298 // C.
3299 c_calling_convention %{
3300 // This is obviously always outgoing
3301 (void) SharedRuntime::c_calling_convention(sig_bt, regs, /*regs2=*/NULL, length);
3302 %}
3303
3304 // Location of native (C/C++) and interpreter return values. This is specified to
3305 // be the same as Java. In the 32-bit VM, long values are actually returned from
3306 // native calls in O0:O1 and returned to the interpreter in I0:I1. The copying
3307 // to and from the register pairs is done by the appropriate call and epilog
3308 // opcodes. This simplifies the register allocator.
3309 c_return_value %{
3310 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
3311 #ifdef _LP64
3312 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_O0_num };
3313 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num, OptoReg::Bad, R_F1_num, R_O0H_num};
3314 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_I0_num };
3315 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num, OptoReg::Bad, R_F1_num, R_I0H_num};
3316 #else // !_LP64
3317 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_G1_num };
3318 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num };
3319 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_G1_num };
3320 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num };
3321 #endif
3322 return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg],
3323 (is_outgoing?lo_out:lo_in)[ideal_reg] );
3324 %}
3325
3326 // Location of compiled Java return values. Same as C
3327 return_value %{
3328 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
3329 #ifdef _LP64
3330 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_O0_num };
3331 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num, OptoReg::Bad, R_F1_num, R_O0H_num};
3332 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_I0_num };
3333 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num, OptoReg::Bad, R_F1_num, R_I0H_num};
3334 #else // !_LP64
3335 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_G1_num };
3336 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num};
3337 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_G1_num };
3338 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num};
3339 #endif
3340 return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg],
3341 (is_outgoing?lo_out:lo_in)[ideal_reg] );
3342 %}
3343
3344 %}
3345
3346
3347 //----------ATTRIBUTES---------------------------------------------------------
3348 //----------Operand Attributes-------------------------------------------------
3349 op_attrib op_cost(1); // Required cost attribute
3350
3351 //----------Instruction Attributes---------------------------------------------
3352 ins_attrib ins_cost(DEFAULT_COST); // Required cost attribute
3353 ins_attrib ins_size(32); // Required size attribute (in bits)
3354 ins_attrib ins_avoid_back_to_back(0); // instruction should not be generated back to back
3355 ins_attrib ins_short_branch(0); // Required flag: is this instruction a
3356 // non-matching short branch variant of some
3357 // long branch?
3358
3359 //----------OPERANDS-----------------------------------------------------------
3360 // Operand definitions must precede instruction definitions for correct parsing
3361 // in the ADLC because operands constitute user defined types which are used in
3362 // instruction definitions.
3363
3364 //----------Simple Operands----------------------------------------------------
3365 // Immediate Operands
3366 // Integer Immediate: 32-bit
3367 operand immI() %{
3368 match(ConI);
3369
3370 op_cost(0);
3371 // formats are generated automatically for constants and base registers
3372 format %{ %}
3373 interface(CONST_INTER);
3374 %}
3375
3376 // Integer Immediate: 8-bit
3377 operand immI8() %{
3378 predicate(Assembler::is_simm8(n->get_int()));
3379 match(ConI);
3380 op_cost(0);
3381 format %{ %}
3382 interface(CONST_INTER);
3383 %}
3384
3385 // Integer Immediate: 13-bit
3386 operand immI13() %{
3387 predicate(Assembler::is_simm13(n->get_int()));
3388 match(ConI);
3389 op_cost(0);
3390
3391 format %{ %}
3392 interface(CONST_INTER);
3393 %}
3394
3395 // Integer Immediate: 13-bit minus 7
3396 operand immI13m7() %{
3397 predicate((-4096 < n->get_int()) && ((n->get_int() + 7) <= 4095));
3398 match(ConI);
3399 op_cost(0);
3400
3401 format %{ %}
3402 interface(CONST_INTER);
3403 %}
3404
3405 // Integer Immediate: 16-bit
3406 operand immI16() %{
3407 predicate(Assembler::is_simm16(n->get_int()));
3408 match(ConI);
3409 op_cost(0);
3410 format %{ %}
3411 interface(CONST_INTER);
3412 %}
3413
3414 // Unsigned Integer Immediate: 12-bit (non-negative that fits in simm13)
3415 operand immU12() %{
3416 predicate((0 <= n->get_int()) && Assembler::is_simm13(n->get_int()));
3417 match(ConI);
3418 op_cost(0);
3419
3420 format %{ %}
3421 interface(CONST_INTER);
3422 %}
3423
3424 // Integer Immediate: 6-bit
3425 operand immU6() %{
3426 predicate(n->get_int() >= 0 && n->get_int() <= 63);
3427 match(ConI);
3428 op_cost(0);
3429 format %{ %}
3430 interface(CONST_INTER);
3431 %}
3432
3433 // Integer Immediate: 11-bit
3434 operand immI11() %{
3435 predicate(Assembler::is_simm11(n->get_int()));
3436 match(ConI);
3437 op_cost(0);
3438 format %{ %}
3439 interface(CONST_INTER);
3440 %}
3441
3442 // Integer Immediate: 5-bit
3443 operand immI5() %{
3444 predicate(Assembler::is_simm5(n->get_int()));
3445 match(ConI);
3446 op_cost(0);
3447 format %{ %}
3448 interface(CONST_INTER);
3449 %}
3450
3451 // Unsigned Long Immediate: 12-bit (non-negative that fits in simm13)
3452 operand immUL12() %{
3453 predicate((0 <= n->get_long()) && (n->get_long() == (int)n->get_long()) && Assembler::is_simm13((int)n->get_long()));
3454 match(ConL);
3455 op_cost(0);
3456
3457 format %{ %}
3458 interface(CONST_INTER);
3459 %}
3460
3461 // Int Immediate non-negative
3462 operand immU31()
3463 %{
3464 predicate(n->get_int() >= 0);
3465 match(ConI);
3466
3467 op_cost(0);
3468 format %{ %}
3469 interface(CONST_INTER);
3470 %}
3471
3472 // Integer Immediate: 0-bit
3473 operand immI0() %{
3474 predicate(n->get_int() == 0);
3475 match(ConI);
3476 op_cost(0);
3477
3478 format %{ %}
3479 interface(CONST_INTER);
3480 %}
3481
3482 // Integer Immediate: the value 10
3483 operand immI10() %{
3484 predicate(n->get_int() == 10);
3485 match(ConI);
3486 op_cost(0);
3487
3488 format %{ %}
3489 interface(CONST_INTER);
3490 %}
3491
3492 // Integer Immediate: the values 0-31
3493 operand immU5() %{
3494 predicate(n->get_int() >= 0 && n->get_int() <= 31);
3495 match(ConI);
3496 op_cost(0);
3497
3498 format %{ %}
3499 interface(CONST_INTER);
3500 %}
3501
3502 // Integer Immediate: the values 1-31
3503 operand immI_1_31() %{
3504 predicate(n->get_int() >= 1 && n->get_int() <= 31);
3505 match(ConI);
3506 op_cost(0);
3507
3508 format %{ %}
3509 interface(CONST_INTER);
3510 %}
3511
3512 // Integer Immediate: the values 32-63
3513 operand immI_32_63() %{
3514 predicate(n->get_int() >= 32 && n->get_int() <= 63);
3515 match(ConI);
3516 op_cost(0);
3517
3518 format %{ %}
3519 interface(CONST_INTER);
3520 %}
3521
3522 // Immediates for special shifts (sign extend)
3523
3524 // Integer Immediate: the value 16
3525 operand immI_16() %{
3526 predicate(n->get_int() == 16);
3527 match(ConI);
3528 op_cost(0);
3529
3530 format %{ %}
3531 interface(CONST_INTER);
3532 %}
3533
3534 // Integer Immediate: the value 24
3535 operand immI_24() %{
3536 predicate(n->get_int() == 24);
3537 match(ConI);
3538 op_cost(0);
3539
3540 format %{ %}
3541 interface(CONST_INTER);
3542 %}
3543
3544 // Integer Immediate: the value 255
3545 operand immI_255() %{
3546 predicate( n->get_int() == 255 );
3547 match(ConI);
3548 op_cost(0);
3549
3550 format %{ %}
3551 interface(CONST_INTER);
3552 %}
3553
3554 // Integer Immediate: the value 65535
3555 operand immI_65535() %{
3556 predicate(n->get_int() == 65535);
3557 match(ConI);
3558 op_cost(0);
3559
3560 format %{ %}
3561 interface(CONST_INTER);
3562 %}
3563
3564 // Long Immediate: the value FF
3565 operand immL_FF() %{
3566 predicate( n->get_long() == 0xFFL );
3567 match(ConL);
3568 op_cost(0);
3569
3570 format %{ %}
3571 interface(CONST_INTER);
3572 %}
3573
3574 // Long Immediate: the value FFFF
3575 operand immL_FFFF() %{
3576 predicate( n->get_long() == 0xFFFFL );
3577 match(ConL);
3578 op_cost(0);
3579
3580 format %{ %}
3581 interface(CONST_INTER);
3582 %}
3583
3584 // Pointer Immediate: 32 or 64-bit
3585 operand immP() %{
3586 match(ConP);
3587
3588 op_cost(5);
3589 // formats are generated automatically for constants and base registers
3590 format %{ %}
3591 interface(CONST_INTER);
3592 %}
3593
3594 #ifdef _LP64
3595 // Pointer Immediate: 64-bit
3596 operand immP_set() %{
3597 predicate(!VM_Version::is_niagara_plus());
3598 match(ConP);
3599
3600 op_cost(5);
3601 // formats are generated automatically for constants and base registers
3602 format %{ %}
3603 interface(CONST_INTER);
3604 %}
3605
3606 // Pointer Immediate: 64-bit
3607 // From Niagara2 processors on a load should be better than materializing.
3608 operand immP_load() %{
3609 predicate(VM_Version::is_niagara_plus() && (n->bottom_type()->isa_oop_ptr() || (MacroAssembler::insts_for_set(n->get_ptr()) > 3)));
3610 match(ConP);
3611
3612 op_cost(5);
3613 // formats are generated automatically for constants and base registers
3614 format %{ %}
3615 interface(CONST_INTER);
3616 %}
3617
3618 // Pointer Immediate: 64-bit
3619 operand immP_no_oop_cheap() %{
3620 predicate(VM_Version::is_niagara_plus() && !n->bottom_type()->isa_oop_ptr() && (MacroAssembler::insts_for_set(n->get_ptr()) <= 3));
3621 match(ConP);
3622
3623 op_cost(5);
3624 // formats are generated automatically for constants and base registers
3625 format %{ %}
3626 interface(CONST_INTER);
3627 %}
3628 #endif
3629
3630 operand immP13() %{
3631 predicate((-4096 < n->get_ptr()) && (n->get_ptr() <= 4095));
3632 match(ConP);
3633 op_cost(0);
3634
3635 format %{ %}
3636 interface(CONST_INTER);
3637 %}
3638
3639 operand immP0() %{
3640 predicate(n->get_ptr() == 0);
3641 match(ConP);
3642 op_cost(0);
3643
3644 format %{ %}
3645 interface(CONST_INTER);
3646 %}
3647
3648 operand immP_poll() %{
3649 predicate(n->get_ptr() != 0 && n->get_ptr() == (intptr_t)os::get_polling_page());
3650 match(ConP);
3651
3652 // formats are generated automatically for constants and base registers
3653 format %{ %}
3654 interface(CONST_INTER);
3655 %}
3656
3657 // Pointer Immediate
3658 operand immN()
3659 %{
3660 match(ConN);
3661
3662 op_cost(10);
3663 format %{ %}
3664 interface(CONST_INTER);
3665 %}
3666
3667 // NULL Pointer Immediate
3668 operand immN0()
3669 %{
3670 predicate(n->get_narrowcon() == 0);
3671 match(ConN);
3672
3673 op_cost(0);
3674 format %{ %}
3675 interface(CONST_INTER);
3676 %}
3677
3678 operand immL() %{
3679 match(ConL);
3680 op_cost(40);
3681 // formats are generated automatically for constants and base registers
3682 format %{ %}
3683 interface(CONST_INTER);
3684 %}
3685
3686 operand immL0() %{
3687 predicate(n->get_long() == 0L);
3688 match(ConL);
3689 op_cost(0);
3690 // formats are generated automatically for constants and base registers
3691 format %{ %}
3692 interface(CONST_INTER);
3693 %}
3694
3695 // Integer Immediate: 5-bit
3696 operand immL5() %{
3697 predicate(n->get_long() == (int)n->get_long() && Assembler::is_simm5((int)n->get_long()));
3698 match(ConL);
3699 op_cost(0);
3700 format %{ %}
3701 interface(CONST_INTER);
3702 %}
3703
3704 // Long Immediate: 13-bit
3705 operand immL13() %{
3706 predicate((-4096L < n->get_long()) && (n->get_long() <= 4095L));
3707 match(ConL);
3708 op_cost(0);
3709
3710 format %{ %}
3711 interface(CONST_INTER);
3712 %}
3713
3714 // Long Immediate: 13-bit minus 7
3715 operand immL13m7() %{
3716 predicate((-4096L < n->get_long()) && ((n->get_long() + 7L) <= 4095L));
3717 match(ConL);
3718 op_cost(0);
3719
3720 format %{ %}
3721 interface(CONST_INTER);
3722 %}
3723
3724 // Long Immediate: low 32-bit mask
3725 operand immL_32bits() %{
3726 predicate(n->get_long() == 0xFFFFFFFFL);
3727 match(ConL);
3728 op_cost(0);
3729
3730 format %{ %}
3731 interface(CONST_INTER);
3732 %}
3733
3734 // Long Immediate: cheap (materialize in <= 3 instructions)
3735 operand immL_cheap() %{
3736 predicate(!VM_Version::is_niagara_plus() || MacroAssembler::insts_for_set64(n->get_long()) <= 3);
3737 match(ConL);
3738 op_cost(0);
3739
3740 format %{ %}
3741 interface(CONST_INTER);
3742 %}
3743
3744 // Long Immediate: expensive (materialize in > 3 instructions)
3745 operand immL_expensive() %{
3746 predicate(VM_Version::is_niagara_plus() && MacroAssembler::insts_for_set64(n->get_long()) > 3);
3747 match(ConL);
3748 op_cost(0);
3749
3750 format %{ %}
3751 interface(CONST_INTER);
3752 %}
3753
3754 // Double Immediate
3755 operand immD() %{
3756 match(ConD);
3757
3758 op_cost(40);
3759 format %{ %}
3760 interface(CONST_INTER);
3761 %}
3762
3763 operand immD0() %{
3764 #ifdef _LP64
3765 // on 64-bit architectures this comparision is faster
3766 predicate(jlong_cast(n->getd()) == 0);
3767 #else
3768 predicate((n->getd() == 0) && (fpclass(n->getd()) == FP_PZERO));
3769 #endif
3770 match(ConD);
3771
3772 op_cost(0);
3773 format %{ %}
3774 interface(CONST_INTER);
3775 %}
3776
3777 // Float Immediate
3778 operand immF() %{
3779 match(ConF);
3780
3781 op_cost(20);
3782 format %{ %}
3783 interface(CONST_INTER);
3784 %}
3785
3786 // Float Immediate: 0
3787 operand immF0() %{
3788 predicate((n->getf() == 0) && (fpclass(n->getf()) == FP_PZERO));
3789 match(ConF);
3790
3791 op_cost(0);
3792 format %{ %}
3793 interface(CONST_INTER);
3794 %}
3795
3796 // Integer Register Operands
3797 // Integer Register
3798 operand iRegI() %{
3799 constraint(ALLOC_IN_RC(int_reg));
3800 match(RegI);
3801
3802 match(notemp_iRegI);
3803 match(g1RegI);
3804 match(o0RegI);
3805 match(iRegIsafe);
3806
3807 format %{ %}
3808 interface(REG_INTER);
3809 %}
3810
3811 operand notemp_iRegI() %{
3812 constraint(ALLOC_IN_RC(notemp_int_reg));
3813 match(RegI);
3814
3815 match(o0RegI);
3816
3817 format %{ %}
3818 interface(REG_INTER);
3819 %}
3820
3821 operand o0RegI() %{
3822 constraint(ALLOC_IN_RC(o0_regI));
3823 match(iRegI);
3824
3825 format %{ %}
3826 interface(REG_INTER);
3827 %}
3828
3829 // Pointer Register
3830 operand iRegP() %{
3831 constraint(ALLOC_IN_RC(ptr_reg));
3832 match(RegP);
3833
3834 match(lock_ptr_RegP);
3835 match(g1RegP);
3836 match(g2RegP);
3837 match(g3RegP);
3838 match(g4RegP);
3839 match(i0RegP);
3840 match(o0RegP);
3841 match(o1RegP);
3842 match(l7RegP);
3843
3844 format %{ %}
3845 interface(REG_INTER);
3846 %}
3847
3848 operand sp_ptr_RegP() %{
3849 constraint(ALLOC_IN_RC(sp_ptr_reg));
3850 match(RegP);
3851 match(iRegP);
3852
3853 format %{ %}
3854 interface(REG_INTER);
3855 %}
3856
3857 operand lock_ptr_RegP() %{
3858 constraint(ALLOC_IN_RC(lock_ptr_reg));
3859 match(RegP);
3860 match(i0RegP);
3861 match(o0RegP);
3862 match(o1RegP);
3863 match(l7RegP);
3864
3865 format %{ %}
3866 interface(REG_INTER);
3867 %}
3868
3869 operand g1RegP() %{
3870 constraint(ALLOC_IN_RC(g1_regP));
3871 match(iRegP);
3872
3873 format %{ %}
3874 interface(REG_INTER);
3875 %}
3876
3877 operand g2RegP() %{
3878 constraint(ALLOC_IN_RC(g2_regP));
3879 match(iRegP);
3880
3881 format %{ %}
3882 interface(REG_INTER);
3883 %}
3884
3885 operand g3RegP() %{
3886 constraint(ALLOC_IN_RC(g3_regP));
3887 match(iRegP);
3888
3889 format %{ %}
3890 interface(REG_INTER);
3891 %}
3892
3893 operand g1RegI() %{
3894 constraint(ALLOC_IN_RC(g1_regI));
3895 match(iRegI);
3896
3897 format %{ %}
3898 interface(REG_INTER);
3899 %}
3900
3901 operand g3RegI() %{
3902 constraint(ALLOC_IN_RC(g3_regI));
3903 match(iRegI);
3904
3905 format %{ %}
3906 interface(REG_INTER);
3907 %}
3908
3909 operand g4RegI() %{
3910 constraint(ALLOC_IN_RC(g4_regI));
3911 match(iRegI);
3912
3913 format %{ %}
3914 interface(REG_INTER);
3915 %}
3916
3917 operand g4RegP() %{
3918 constraint(ALLOC_IN_RC(g4_regP));
3919 match(iRegP);
3920
3921 format %{ %}
3922 interface(REG_INTER);
3923 %}
3924
3925 operand i0RegP() %{
3926 constraint(ALLOC_IN_RC(i0_regP));
3927 match(iRegP);
3928
3929 format %{ %}
3930 interface(REG_INTER);
3931 %}
3932
3933 operand o0RegP() %{
3934 constraint(ALLOC_IN_RC(o0_regP));
3935 match(iRegP);
3936
3937 format %{ %}
3938 interface(REG_INTER);
3939 %}
3940
3941 operand o1RegP() %{
3942 constraint(ALLOC_IN_RC(o1_regP));
3943 match(iRegP);
3944
3945 format %{ %}
3946 interface(REG_INTER);
3947 %}
3948
3949 operand o2RegP() %{
3950 constraint(ALLOC_IN_RC(o2_regP));
3951 match(iRegP);
3952
3953 format %{ %}
3954 interface(REG_INTER);
3955 %}
3956
3957 operand o7RegP() %{
3958 constraint(ALLOC_IN_RC(o7_regP));
3959 match(iRegP);
3960
3961 format %{ %}
3962 interface(REG_INTER);
3963 %}
3964
3965 operand l7RegP() %{
3966 constraint(ALLOC_IN_RC(l7_regP));
3967 match(iRegP);
3968
3969 format %{ %}
3970 interface(REG_INTER);
3971 %}
3972
3973 operand o7RegI() %{
3974 constraint(ALLOC_IN_RC(o7_regI));
3975 match(iRegI);
3976
3977 format %{ %}
3978 interface(REG_INTER);
3979 %}
3980
3981 operand iRegN() %{
3982 constraint(ALLOC_IN_RC(int_reg));
3983 match(RegN);
3984
3985 format %{ %}
3986 interface(REG_INTER);
3987 %}
3988
3989 // Long Register
3990 operand iRegL() %{
3991 constraint(ALLOC_IN_RC(long_reg));
3992 match(RegL);
3993
3994 format %{ %}
3995 interface(REG_INTER);
3996 %}
3997
3998 operand o2RegL() %{
3999 constraint(ALLOC_IN_RC(o2_regL));
4000 match(iRegL);
4001
4002 format %{ %}
4003 interface(REG_INTER);
4004 %}
4005
4006 operand o7RegL() %{
4007 constraint(ALLOC_IN_RC(o7_regL));
4008 match(iRegL);
4009
4010 format %{ %}
4011 interface(REG_INTER);
4012 %}
4013
4014 operand g1RegL() %{
4015 constraint(ALLOC_IN_RC(g1_regL));
4016 match(iRegL);
4017
4018 format %{ %}
4019 interface(REG_INTER);
4020 %}
4021
4022 operand g3RegL() %{
4023 constraint(ALLOC_IN_RC(g3_regL));
4024 match(iRegL);
4025
4026 format %{ %}
4027 interface(REG_INTER);
4028 %}
4029
4030 // Int Register safe
4031 // This is 64bit safe
4032 operand iRegIsafe() %{
4033 constraint(ALLOC_IN_RC(long_reg));
4034
4035 match(iRegI);
4036
4037 format %{ %}
4038 interface(REG_INTER);
4039 %}
4040
4041 // Condition Code Flag Register
4042 operand flagsReg() %{
4043 constraint(ALLOC_IN_RC(int_flags));
4044 match(RegFlags);
4045
4046 format %{ "ccr" %} // both ICC and XCC
4047 interface(REG_INTER);
4048 %}
4049
4050 // Condition Code Register, unsigned comparisons.
4051 operand flagsRegU() %{
4052 constraint(ALLOC_IN_RC(int_flags));
4053 match(RegFlags);
4054
4055 format %{ "icc_U" %}
4056 interface(REG_INTER);
4057 %}
4058
4059 // Condition Code Register, pointer comparisons.
4060 operand flagsRegP() %{
4061 constraint(ALLOC_IN_RC(int_flags));
4062 match(RegFlags);
4063
4064 #ifdef _LP64
4065 format %{ "xcc_P" %}
4066 #else
4067 format %{ "icc_P" %}
4068 #endif
4069 interface(REG_INTER);
4070 %}
4071
4072 // Condition Code Register, long comparisons.
4073 operand flagsRegL() %{
4074 constraint(ALLOC_IN_RC(int_flags));
4075 match(RegFlags);
4076
4077 format %{ "xcc_L" %}
4078 interface(REG_INTER);
4079 %}
4080
4081 // Condition Code Register, unsigned long comparisons.
4082 operand flagsRegUL() %{
4083 constraint(ALLOC_IN_RC(int_flags));
4084 match(RegFlags);
4085
4086 format %{ "xcc_UL" %}
4087 interface(REG_INTER);
4088 %}
4089
4090 // Condition Code Register, floating comparisons, unordered same as "less".
4091 operand flagsRegF() %{
4092 constraint(ALLOC_IN_RC(float_flags));
4093 match(RegFlags);
4094 match(flagsRegF0);
4095
4096 format %{ %}
4097 interface(REG_INTER);
4098 %}
4099
4100 operand flagsRegF0() %{
4101 constraint(ALLOC_IN_RC(float_flag0));
4102 match(RegFlags);
4103
4104 format %{ %}
4105 interface(REG_INTER);
4106 %}
4107
4108
4109 // Condition Code Flag Register used by long compare
4110 operand flagsReg_long_LTGE() %{
4111 constraint(ALLOC_IN_RC(int_flags));
4112 match(RegFlags);
4113 format %{ "icc_LTGE" %}
4114 interface(REG_INTER);
4115 %}
4116 operand flagsReg_long_EQNE() %{
4117 constraint(ALLOC_IN_RC(int_flags));
4118 match(RegFlags);
4119 format %{ "icc_EQNE" %}
4120 interface(REG_INTER);
4121 %}
4122 operand flagsReg_long_LEGT() %{
4123 constraint(ALLOC_IN_RC(int_flags));
4124 match(RegFlags);
4125 format %{ "icc_LEGT" %}
4126 interface(REG_INTER);
4127 %}
4128
4129
4130 operand regD() %{
4131 constraint(ALLOC_IN_RC(dflt_reg));
4132 match(RegD);
4133
4134 match(regD_low);
4135
4136 format %{ %}
4137 interface(REG_INTER);
4138 %}
4139
4140 operand regF() %{
4141 constraint(ALLOC_IN_RC(sflt_reg));
4142 match(RegF);
4143
4144 format %{ %}
4145 interface(REG_INTER);
4146 %}
4147
4148 operand regD_low() %{
4149 constraint(ALLOC_IN_RC(dflt_low_reg));
4150 match(regD);
4151
4152 format %{ %}
4153 interface(REG_INTER);
4154 %}
4155
4156 // Special Registers
4157
4158 // Method Register
4159 operand inline_cache_regP(iRegP reg) %{
4160 constraint(ALLOC_IN_RC(g5_regP)); // G5=inline_cache_reg but uses 2 bits instead of 1
4161 match(reg);
4162 format %{ %}
4163 interface(REG_INTER);
4164 %}
4165
4166 operand interpreter_method_oop_regP(iRegP reg) %{
4167 constraint(ALLOC_IN_RC(g5_regP)); // G5=interpreter_method_oop_reg but uses 2 bits instead of 1
4168 match(reg);
4169 format %{ %}
4170 interface(REG_INTER);
4171 %}
4172
4173
4174 //----------Complex Operands---------------------------------------------------
4175 // Indirect Memory Reference
4176 operand indirect(sp_ptr_RegP reg) %{
4177 constraint(ALLOC_IN_RC(sp_ptr_reg));
4178 match(reg);
4179
4180 op_cost(100);
4181 format %{ "[$reg]" %}
4182 interface(MEMORY_INTER) %{
4183 base($reg);
4184 index(0x0);
4185 scale(0x0);
4186 disp(0x0);
4187 %}
4188 %}
4189
4190 // Indirect with simm13 Offset
4191 operand indOffset13(sp_ptr_RegP reg, immX13 offset) %{
4192 constraint(ALLOC_IN_RC(sp_ptr_reg));
4193 match(AddP reg offset);
4194
4195 op_cost(100);
4196 format %{ "[$reg + $offset]" %}
4197 interface(MEMORY_INTER) %{
4198 base($reg);
4199 index(0x0);
4200 scale(0x0);
4201 disp($offset);
4202 %}
4203 %}
4204
4205 // Indirect with simm13 Offset minus 7
4206 operand indOffset13m7(sp_ptr_RegP reg, immX13m7 offset) %{
4207 constraint(ALLOC_IN_RC(sp_ptr_reg));
4208 match(AddP reg offset);
4209
4210 op_cost(100);
4211 format %{ "[$reg + $offset]" %}
4212 interface(MEMORY_INTER) %{
4213 base($reg);
4214 index(0x0);
4215 scale(0x0);
4216 disp($offset);
4217 %}
4218 %}
4219
4220 // Note: Intel has a swapped version also, like this:
4221 //operand indOffsetX(iRegI reg, immP offset) %{
4222 // constraint(ALLOC_IN_RC(int_reg));
4223 // match(AddP offset reg);
4224 //
4225 // op_cost(100);
4226 // format %{ "[$reg + $offset]" %}
4227 // interface(MEMORY_INTER) %{
4228 // base($reg);
4229 // index(0x0);
4230 // scale(0x0);
4231 // disp($offset);
4232 // %}
4233 //%}
4234 //// However, it doesn't make sense for SPARC, since
4235 // we have no particularly good way to embed oops in
4236 // single instructions.
4237
4238 // Indirect with Register Index
4239 operand indIndex(iRegP addr, iRegX index) %{
4240 constraint(ALLOC_IN_RC(ptr_reg));
4241 match(AddP addr index);
4242
4243 op_cost(100);
4244 format %{ "[$addr + $index]" %}
4245 interface(MEMORY_INTER) %{
4246 base($addr);
4247 index($index);
4248 scale(0x0);
4249 disp(0x0);
4250 %}
4251 %}
4252
4253 //----------Special Memory Operands--------------------------------------------
4254 // Stack Slot Operand - This operand is used for loading and storing temporary
4255 // values on the stack where a match requires a value to
4256 // flow through memory.
4257 operand stackSlotI(sRegI reg) %{
4258 constraint(ALLOC_IN_RC(stack_slots));
4259 op_cost(100);
4260 //match(RegI);
4261 format %{ "[$reg]" %}
4262 interface(MEMORY_INTER) %{
4263 base(0xE); // R_SP
4264 index(0x0);
4265 scale(0x0);
4266 disp($reg); // Stack Offset
4267 %}
4268 %}
4269
4270 operand stackSlotP(sRegP reg) %{
4271 constraint(ALLOC_IN_RC(stack_slots));
4272 op_cost(100);
4273 //match(RegP);
4274 format %{ "[$reg]" %}
4275 interface(MEMORY_INTER) %{
4276 base(0xE); // R_SP
4277 index(0x0);
4278 scale(0x0);
4279 disp($reg); // Stack Offset
4280 %}
4281 %}
4282
4283 operand stackSlotF(sRegF reg) %{
4284 constraint(ALLOC_IN_RC(stack_slots));
4285 op_cost(100);
4286 //match(RegF);
4287 format %{ "[$reg]" %}
4288 interface(MEMORY_INTER) %{
4289 base(0xE); // R_SP
4290 index(0x0);
4291 scale(0x0);
4292 disp($reg); // Stack Offset
4293 %}
4294 %}
4295 operand stackSlotD(sRegD reg) %{
4296 constraint(ALLOC_IN_RC(stack_slots));
4297 op_cost(100);
4298 //match(RegD);
4299 format %{ "[$reg]" %}
4300 interface(MEMORY_INTER) %{
4301 base(0xE); // R_SP
4302 index(0x0);
4303 scale(0x0);
4304 disp($reg); // Stack Offset
4305 %}
4306 %}
4307 operand stackSlotL(sRegL reg) %{
4308 constraint(ALLOC_IN_RC(stack_slots));
4309 op_cost(100);
4310 //match(RegL);
4311 format %{ "[$reg]" %}
4312 interface(MEMORY_INTER) %{
4313 base(0xE); // R_SP
4314 index(0x0);
4315 scale(0x0);
4316 disp($reg); // Stack Offset
4317 %}
4318 %}
4319
4320 // Operands for expressing Control Flow
4321 // NOTE: Label is a predefined operand which should not be redefined in
4322 // the AD file. It is generically handled within the ADLC.
4323
4324 //----------Conditional Branch Operands----------------------------------------
4325 // Comparison Op - This is the operation of the comparison, and is limited to
4326 // the following set of codes:
4327 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
4328 //
4329 // Other attributes of the comparison, such as unsignedness, are specified
4330 // by the comparison instruction that sets a condition code flags register.
4331 // That result is represented by a flags operand whose subtype is appropriate
4332 // to the unsignedness (etc.) of the comparison.
4333 //
4334 // Later, the instruction which matches both the Comparison Op (a Bool) and
4335 // the flags (produced by the Cmp) specifies the coding of the comparison op
4336 // by matching a specific subtype of Bool operand below, such as cmpOpU.
4337
4338 operand cmpOp() %{
4339 match(Bool);
4340
4341 format %{ "" %}
4342 interface(COND_INTER) %{
4343 equal(0x1);
4344 not_equal(0x9);
4345 less(0x3);
4346 greater_equal(0xB);
4347 less_equal(0x2);
4348 greater(0xA);
4349 %}
4350 %}
4351
4352 // Comparison Op, unsigned
4353 operand cmpOpU() %{
4354 match(Bool);
4355
4356 format %{ "u" %}
4357 interface(COND_INTER) %{
4358 equal(0x1);
4359 not_equal(0x9);
4360 less(0x5);
4361 greater_equal(0xD);
4362 less_equal(0x4);
4363 greater(0xC);
4364 %}
4365 %}
4366
4367 // Comparison Op, pointer (same as unsigned)
4368 operand cmpOpP() %{
4369 match(Bool);
4370
4371 format %{ "p" %}
4372 interface(COND_INTER) %{
4373 equal(0x1);
4374 not_equal(0x9);
4375 less(0x5);
4376 greater_equal(0xD);
4377 less_equal(0x4);
4378 greater(0xC);
4379 %}
4380 %}
4381
4382 // Comparison Op, branch-register encoding
4383 operand cmpOp_reg() %{
4384 match(Bool);
4385
4386 format %{ "" %}
4387 interface(COND_INTER) %{
4388 equal (0x1);
4389 not_equal (0x5);
4390 less (0x3);
4391 greater_equal(0x7);
4392 less_equal (0x2);
4393 greater (0x6);
4394 %}
4395 %}
4396
4397 // Comparison Code, floating, unordered same as less
4398 operand cmpOpF() %{
4399 match(Bool);
4400
4401 format %{ "fl" %}
4402 interface(COND_INTER) %{
4403 equal(0x9);
4404 not_equal(0x1);
4405 less(0x3);
4406 greater_equal(0xB);
4407 less_equal(0xE);
4408 greater(0x6);
4409 %}
4410 %}
4411
4412 // Used by long compare
4413 operand cmpOp_commute() %{
4414 match(Bool);
4415
4416 format %{ "" %}
4417 interface(COND_INTER) %{
4418 equal(0x1);
4419 not_equal(0x9);
4420 less(0xA);
4421 greater_equal(0x2);
4422 less_equal(0xB);
4423 greater(0x3);
4424 %}
4425 %}
4426
4427 //----------OPERAND CLASSES----------------------------------------------------
4428 // Operand Classes are groups of operands that are used to simplify
4429 // instruction definitions by not requiring the AD writer to specify separate
4430 // instructions for every form of operand when the instruction accepts
4431 // multiple operand types with the same basic encoding and format. The classic
4432 // case of this is memory operands.
4433 opclass memory( indirect, indOffset13, indIndex );
4434 opclass indIndexMemory( indIndex );
4435
4436 //----------PIPELINE-----------------------------------------------------------
4437 pipeline %{
4438
4439 //----------ATTRIBUTES---------------------------------------------------------
4440 attributes %{
4441 fixed_size_instructions; // Fixed size instructions
4442 branch_has_delay_slot; // Branch has delay slot following
4443 max_instructions_per_bundle = 4; // Up to 4 instructions per bundle
4444 instruction_unit_size = 4; // An instruction is 4 bytes long
4445 instruction_fetch_unit_size = 16; // The processor fetches one line
4446 instruction_fetch_units = 1; // of 16 bytes
4447
4448 // List of nop instructions
4449 nops( Nop_A0, Nop_A1, Nop_MS, Nop_FA, Nop_BR );
4450 %}
4451
4452 //----------RESOURCES----------------------------------------------------------
4453 // Resources are the functional units available to the machine
4454 resources(A0, A1, MS, BR, FA, FM, IDIV, FDIV, IALU = A0 | A1);
4455
4456 //----------PIPELINE DESCRIPTION-----------------------------------------------
4457 // Pipeline Description specifies the stages in the machine's pipeline
4458
4459 pipe_desc(A, P, F, B, I, J, S, R, E, C, M, W, X, T, D);
4460
4461 //----------PIPELINE CLASSES---------------------------------------------------
4462 // Pipeline Classes describe the stages in which input and output are
4463 // referenced by the hardware pipeline.
4464
4465 // Integer ALU reg-reg operation
4466 pipe_class ialu_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
4467 single_instruction;
4468 dst : E(write);
4469 src1 : R(read);
4470 src2 : R(read);
4471 IALU : R;
4472 %}
4473
4474 // Integer ALU reg-reg long operation
4475 pipe_class ialu_reg_reg_2(iRegL dst, iRegL src1, iRegL src2) %{
4476 instruction_count(2);
4477 dst : E(write);
4478 src1 : R(read);
4479 src2 : R(read);
4480 IALU : R;
4481 IALU : R;
4482 %}
4483
4484 // Integer ALU reg-reg long dependent operation
4485 pipe_class ialu_reg_reg_2_dep(iRegL dst, iRegL src1, iRegL src2, flagsReg cr) %{
4486 instruction_count(1); multiple_bundles;
4487 dst : E(write);
4488 src1 : R(read);
4489 src2 : R(read);
4490 cr : E(write);
4491 IALU : R(2);
4492 %}
4493
4494 // Integer ALU reg-imm operaion
4495 pipe_class ialu_reg_imm(iRegI dst, iRegI src1, immI13 src2) %{
4496 single_instruction;
4497 dst : E(write);
4498 src1 : R(read);
4499 IALU : R;
4500 %}
4501
4502 // Integer ALU reg-reg operation with condition code
4503 pipe_class ialu_cc_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{
4504 single_instruction;
4505 dst : E(write);
4506 cr : E(write);
4507 src1 : R(read);
4508 src2 : R(read);
4509 IALU : R;
4510 %}
4511
4512 // Integer ALU reg-imm operation with condition code
4513 pipe_class ialu_cc_reg_imm(iRegI dst, iRegI src1, immI13 src2, flagsReg cr) %{
4514 single_instruction;
4515 dst : E(write);
4516 cr : E(write);
4517 src1 : R(read);
4518 IALU : R;
4519 %}
4520
4521 // Integer ALU zero-reg operation
4522 pipe_class ialu_zero_reg(iRegI dst, immI0 zero, iRegI src2) %{
4523 single_instruction;
4524 dst : E(write);
4525 src2 : R(read);
4526 IALU : R;
4527 %}
4528
4529 // Integer ALU zero-reg operation with condition code only
4530 pipe_class ialu_cconly_zero_reg(flagsReg cr, iRegI src) %{
4531 single_instruction;
4532 cr : E(write);
4533 src : R(read);
4534 IALU : R;
4535 %}
4536
4537 // Integer ALU reg-reg operation with condition code only
4538 pipe_class ialu_cconly_reg_reg(flagsReg cr, iRegI src1, iRegI src2) %{
4539 single_instruction;
4540 cr : E(write);
4541 src1 : R(read);
4542 src2 : R(read);
4543 IALU : R;
4544 %}
4545
4546 // Integer ALU reg-imm operation with condition code only
4547 pipe_class ialu_cconly_reg_imm(flagsReg cr, iRegI src1, immI13 src2) %{
4548 single_instruction;
4549 cr : E(write);
4550 src1 : R(read);
4551 IALU : R;
4552 %}
4553
4554 // Integer ALU reg-reg-zero operation with condition code only
4555 pipe_class ialu_cconly_reg_reg_zero(flagsReg cr, iRegI src1, iRegI src2, immI0 zero) %{
4556 single_instruction;
4557 cr : E(write);
4558 src1 : R(read);
4559 src2 : R(read);
4560 IALU : R;
4561 %}
4562
4563 // Integer ALU reg-imm-zero operation with condition code only
4564 pipe_class ialu_cconly_reg_imm_zero(flagsReg cr, iRegI src1, immI13 src2, immI0 zero) %{
4565 single_instruction;
4566 cr : E(write);
4567 src1 : R(read);
4568 IALU : R;
4569 %}
4570
4571 // Integer ALU reg-reg operation with condition code, src1 modified
4572 pipe_class ialu_cc_rwreg_reg(flagsReg cr, iRegI src1, iRegI src2) %{
4573 single_instruction;
4574 cr : E(write);
4575 src1 : E(write);
4576 src1 : R(read);
4577 src2 : R(read);
4578 IALU : R;
4579 %}
4580
4581 // Integer ALU reg-imm operation with condition code, src1 modified
4582 pipe_class ialu_cc_rwreg_imm(flagsReg cr, iRegI src1, immI13 src2) %{
4583 single_instruction;
4584 cr : E(write);
4585 src1 : E(write);
4586 src1 : R(read);
4587 IALU : R;
4588 %}
4589
4590 pipe_class cmpL_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg cr ) %{
4591 multiple_bundles;
4592 dst : E(write)+4;
4593 cr : E(write);
4594 src1 : R(read);
4595 src2 : R(read);
4596 IALU : R(3);
4597 BR : R(2);
4598 %}
4599
4600 // Integer ALU operation
4601 pipe_class ialu_none(iRegI dst) %{
4602 single_instruction;
4603 dst : E(write);
4604 IALU : R;
4605 %}
4606
4607 // Integer ALU reg operation
4608 pipe_class ialu_reg(iRegI dst, iRegI src) %{
4609 single_instruction; may_have_no_code;
4610 dst : E(write);
4611 src : R(read);
4612 IALU : R;
4613 %}
4614
4615 // Integer ALU reg conditional operation
4616 // This instruction has a 1 cycle stall, and cannot execute
4617 // in the same cycle as the instruction setting the condition
4618 // code. We kludge this by pretending to read the condition code
4619 // 1 cycle earlier, and by marking the functional units as busy
4620 // for 2 cycles with the result available 1 cycle later than
4621 // is really the case.
4622 pipe_class ialu_reg_flags( iRegI op2_out, iRegI op2_in, iRegI op1, flagsReg cr ) %{
4623 single_instruction;
4624 op2_out : C(write);
4625 op1 : R(read);
4626 cr : R(read); // This is really E, with a 1 cycle stall
4627 BR : R(2);
4628 MS : R(2);
4629 %}
4630
4631 #ifdef _LP64
4632 pipe_class ialu_clr_and_mover( iRegI dst, iRegP src ) %{
4633 instruction_count(1); multiple_bundles;
4634 dst : C(write)+1;
4635 src : R(read)+1;
4636 IALU : R(1);
4637 BR : E(2);
4638 MS : E(2);
4639 %}
4640 #endif
4641
4642 // Integer ALU reg operation
4643 pipe_class ialu_move_reg_L_to_I(iRegI dst, iRegL src) %{
4644 single_instruction; may_have_no_code;
4645 dst : E(write);
4646 src : R(read);
4647 IALU : R;
4648 %}
4649 pipe_class ialu_move_reg_I_to_L(iRegL dst, iRegI src) %{
4650 single_instruction; may_have_no_code;
4651 dst : E(write);
4652 src : R(read);
4653 IALU : R;
4654 %}
4655
4656 // Two integer ALU reg operations
4657 pipe_class ialu_reg_2(iRegL dst, iRegL src) %{
4658 instruction_count(2);
4659 dst : E(write);
4660 src : R(read);
4661 A0 : R;
4662 A1 : R;
4663 %}
4664
4665 // Two integer ALU reg operations
4666 pipe_class ialu_move_reg_L_to_L(iRegL dst, iRegL src) %{
4667 instruction_count(2); may_have_no_code;
4668 dst : E(write);
4669 src : R(read);
4670 A0 : R;
4671 A1 : R;
4672 %}
4673
4674 // Integer ALU imm operation
4675 pipe_class ialu_imm(iRegI dst, immI13 src) %{
4676 single_instruction;
4677 dst : E(write);
4678 IALU : R;
4679 %}
4680
4681 // Integer ALU reg-reg with carry operation
4682 pipe_class ialu_reg_reg_cy(iRegI dst, iRegI src1, iRegI src2, iRegI cy) %{
4683 single_instruction;
4684 dst : E(write);
4685 src1 : R(read);
4686 src2 : R(read);
4687 IALU : R;
4688 %}
4689
4690 // Integer ALU cc operation
4691 pipe_class ialu_cc(iRegI dst, flagsReg cc) %{
4692 single_instruction;
4693 dst : E(write);
4694 cc : R(read);
4695 IALU : R;
4696 %}
4697
4698 // Integer ALU cc / second IALU operation
4699 pipe_class ialu_reg_ialu( iRegI dst, iRegI src ) %{
4700 instruction_count(1); multiple_bundles;
4701 dst : E(write)+1;
4702 src : R(read);
4703 IALU : R;
4704 %}
4705
4706 // Integer ALU cc / second IALU operation
4707 pipe_class ialu_reg_reg_ialu( iRegI dst, iRegI p, iRegI q ) %{
4708 instruction_count(1); multiple_bundles;
4709 dst : E(write)+1;
4710 p : R(read);
4711 q : R(read);
4712 IALU : R;
4713 %}
4714
4715 // Integer ALU hi-lo-reg operation
4716 pipe_class ialu_hi_lo_reg(iRegI dst, immI src) %{
4717 instruction_count(1); multiple_bundles;
4718 dst : E(write)+1;
4719 IALU : R(2);
4720 %}
4721
4722 // Float ALU hi-lo-reg operation (with temp)
4723 pipe_class ialu_hi_lo_reg_temp(regF dst, immF src, g3RegP tmp) %{
4724 instruction_count(1); multiple_bundles;
4725 dst : E(write)+1;
4726 IALU : R(2);
4727 %}
4728
4729 // Long Constant
4730 pipe_class loadConL( iRegL dst, immL src ) %{
4731 instruction_count(2); multiple_bundles;
4732 dst : E(write)+1;
4733 IALU : R(2);
4734 IALU : R(2);
4735 %}
4736
4737 // Pointer Constant
4738 pipe_class loadConP( iRegP dst, immP src ) %{
4739 instruction_count(0); multiple_bundles;
4740 fixed_latency(6);
4741 %}
4742
4743 // Polling Address
4744 pipe_class loadConP_poll( iRegP dst, immP_poll src ) %{
4745 #ifdef _LP64
4746 instruction_count(0); multiple_bundles;
4747 fixed_latency(6);
4748 #else
4749 dst : E(write);
4750 IALU : R;
4751 #endif
4752 %}
4753
4754 // Long Constant small
4755 pipe_class loadConLlo( iRegL dst, immL src ) %{
4756 instruction_count(2);
4757 dst : E(write);
4758 IALU : R;
4759 IALU : R;
4760 %}
4761
4762 // [PHH] This is wrong for 64-bit. See LdImmF/D.
4763 pipe_class loadConFD(regF dst, immF src, g3RegP tmp) %{
4764 instruction_count(1); multiple_bundles;
4765 src : R(read);
4766 dst : M(write)+1;
4767 IALU : R;
4768 MS : E;
4769 %}
4770
4771 // Integer ALU nop operation
4772 pipe_class ialu_nop() %{
4773 single_instruction;
4774 IALU : R;
4775 %}
4776
4777 // Integer ALU nop operation
4778 pipe_class ialu_nop_A0() %{
4779 single_instruction;
4780 A0 : R;
4781 %}
4782
4783 // Integer ALU nop operation
4784 pipe_class ialu_nop_A1() %{
4785 single_instruction;
4786 A1 : R;
4787 %}
4788
4789 // Integer Multiply reg-reg operation
4790 pipe_class imul_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
4791 single_instruction;
4792 dst : E(write);
4793 src1 : R(read);
4794 src2 : R(read);
4795 MS : R(5);
4796 %}
4797
4798 // Integer Multiply reg-imm operation
4799 pipe_class imul_reg_imm(iRegI dst, iRegI src1, immI13 src2) %{
4800 single_instruction;
4801 dst : E(write);
4802 src1 : R(read);
4803 MS : R(5);
4804 %}
4805
4806 pipe_class mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
4807 single_instruction;
4808 dst : E(write)+4;
4809 src1 : R(read);
4810 src2 : R(read);
4811 MS : R(6);
4812 %}
4813
4814 pipe_class mulL_reg_imm(iRegL dst, iRegL src1, immL13 src2) %{
4815 single_instruction;
4816 dst : E(write)+4;
4817 src1 : R(read);
4818 MS : R(6);
4819 %}
4820
4821 // Integer Divide reg-reg
4822 pipe_class sdiv_reg_reg(iRegI dst, iRegI src1, iRegI src2, iRegI temp, flagsReg cr) %{
4823 instruction_count(1); multiple_bundles;
4824 dst : E(write);
4825 temp : E(write);
4826 src1 : R(read);
4827 src2 : R(read);
4828 temp : R(read);
4829 MS : R(38);
4830 %}
4831
4832 // Integer Divide reg-imm
4833 pipe_class sdiv_reg_imm(iRegI dst, iRegI src1, immI13 src2, iRegI temp, flagsReg cr) %{
4834 instruction_count(1); multiple_bundles;
4835 dst : E(write);
4836 temp : E(write);
4837 src1 : R(read);
4838 temp : R(read);
4839 MS : R(38);
4840 %}
4841
4842 // Long Divide
4843 pipe_class divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
4844 dst : E(write)+71;
4845 src1 : R(read);
4846 src2 : R(read)+1;
4847 MS : R(70);
4848 %}
4849
4850 pipe_class divL_reg_imm(iRegL dst, iRegL src1, immL13 src2) %{
4851 dst : E(write)+71;
4852 src1 : R(read);
4853 MS : R(70);
4854 %}
4855
4856 // Floating Point Add Float
4857 pipe_class faddF_reg_reg(regF dst, regF src1, regF src2) %{
4858 single_instruction;
4859 dst : X(write);
4860 src1 : E(read);
4861 src2 : E(read);
4862 FA : R;
4863 %}
4864
4865 // Floating Point Add Double
4866 pipe_class faddD_reg_reg(regD dst, regD src1, regD src2) %{
4867 single_instruction;
4868 dst : X(write);
4869 src1 : E(read);
4870 src2 : E(read);
4871 FA : R;
4872 %}
4873
4874 // Floating Point Conditional Move based on integer flags
4875 pipe_class int_conditional_float_move (cmpOp cmp, flagsReg cr, regF dst, regF src) %{
4876 single_instruction;
4877 dst : X(write);
4878 src : E(read);
4879 cr : R(read);
4880 FA : R(2);
4881 BR : R(2);
4882 %}
4883
4884 // Floating Point Conditional Move based on integer flags
4885 pipe_class int_conditional_double_move (cmpOp cmp, flagsReg cr, regD dst, regD src) %{
4886 single_instruction;
4887 dst : X(write);
4888 src : E(read);
4889 cr : R(read);
4890 FA : R(2);
4891 BR : R(2);
4892 %}
4893
4894 // Floating Point Multiply Float
4895 pipe_class fmulF_reg_reg(regF dst, regF src1, regF src2) %{
4896 single_instruction;
4897 dst : X(write);
4898 src1 : E(read);
4899 src2 : E(read);
4900 FM : R;
4901 %}
4902
4903 // Floating Point Multiply Double
4904 pipe_class fmulD_reg_reg(regD dst, regD src1, regD src2) %{
4905 single_instruction;
4906 dst : X(write);
4907 src1 : E(read);
4908 src2 : E(read);
4909 FM : R;
4910 %}
4911
4912 // Floating Point Divide Float
4913 pipe_class fdivF_reg_reg(regF dst, regF src1, regF src2) %{
4914 single_instruction;
4915 dst : X(write);
4916 src1 : E(read);
4917 src2 : E(read);
4918 FM : R;
4919 FDIV : C(14);
4920 %}
4921
4922 // Floating Point Divide Double
4923 pipe_class fdivD_reg_reg(regD dst, regD src1, regD src2) %{
4924 single_instruction;
4925 dst : X(write);
4926 src1 : E(read);
4927 src2 : E(read);
4928 FM : R;
4929 FDIV : C(17);
4930 %}
4931
4932 // Floating Point Move/Negate/Abs Float
4933 pipe_class faddF_reg(regF dst, regF src) %{
4934 single_instruction;
4935 dst : W(write);
4936 src : E(read);
4937 FA : R(1);
4938 %}
4939
4940 // Floating Point Move/Negate/Abs Double
4941 pipe_class faddD_reg(regD dst, regD src) %{
4942 single_instruction;
4943 dst : W(write);
4944 src : E(read);
4945 FA : R;
4946 %}
4947
4948 // Floating Point Convert F->D
4949 pipe_class fcvtF2D(regD dst, regF src) %{
4950 single_instruction;
4951 dst : X(write);
4952 src : E(read);
4953 FA : R;
4954 %}
4955
4956 // Floating Point Convert I->D
4957 pipe_class fcvtI2D(regD dst, regF src) %{
4958 single_instruction;
4959 dst : X(write);
4960 src : E(read);
4961 FA : R;
4962 %}
4963
4964 // Floating Point Convert LHi->D
4965 pipe_class fcvtLHi2D(regD dst, regD src) %{
4966 single_instruction;
4967 dst : X(write);
4968 src : E(read);
4969 FA : R;
4970 %}
4971
4972 // Floating Point Convert L->D
4973 pipe_class fcvtL2D(regD dst, regF src) %{
4974 single_instruction;
4975 dst : X(write);
4976 src : E(read);
4977 FA : R;
4978 %}
4979
4980 // Floating Point Convert L->F
4981 pipe_class fcvtL2F(regD dst, regF src) %{
4982 single_instruction;
4983 dst : X(write);
4984 src : E(read);
4985 FA : R;
4986 %}
4987
4988 // Floating Point Convert D->F
4989 pipe_class fcvtD2F(regD dst, regF src) %{
4990 single_instruction;
4991 dst : X(write);
4992 src : E(read);
4993 FA : R;
4994 %}
4995
4996 // Floating Point Convert I->L
4997 pipe_class fcvtI2L(regD dst, regF src) %{
4998 single_instruction;
4999 dst : X(write);
5000 src : E(read);
5001 FA : R;
5002 %}
5003
5004 // Floating Point Convert D->F
5005 pipe_class fcvtD2I(regF dst, regD src, flagsReg cr) %{
5006 instruction_count(1); multiple_bundles;
5007 dst : X(write)+6;
5008 src : E(read);
5009 FA : R;
5010 %}
5011
5012 // Floating Point Convert D->L
5013 pipe_class fcvtD2L(regD dst, regD src, flagsReg cr) %{
5014 instruction_count(1); multiple_bundles;
5015 dst : X(write)+6;
5016 src : E(read);
5017 FA : R;
5018 %}
5019
5020 // Floating Point Convert F->I
5021 pipe_class fcvtF2I(regF dst, regF src, flagsReg cr) %{
5022 instruction_count(1); multiple_bundles;
5023 dst : X(write)+6;
5024 src : E(read);
5025 FA : R;
5026 %}
5027
5028 // Floating Point Convert F->L
5029 pipe_class fcvtF2L(regD dst, regF src, flagsReg cr) %{
5030 instruction_count(1); multiple_bundles;
5031 dst : X(write)+6;
5032 src : E(read);
5033 FA : R;
5034 %}
5035
5036 // Floating Point Convert I->F
5037 pipe_class fcvtI2F(regF dst, regF src) %{
5038 single_instruction;
5039 dst : X(write);
5040 src : E(read);
5041 FA : R;
5042 %}
5043
5044 // Floating Point Compare
5045 pipe_class faddF_fcc_reg_reg_zero(flagsRegF cr, regF src1, regF src2, immI0 zero) %{
5046 single_instruction;
5047 cr : X(write);
5048 src1 : E(read);
5049 src2 : E(read);
5050 FA : R;
5051 %}
5052
5053 // Floating Point Compare
5054 pipe_class faddD_fcc_reg_reg_zero(flagsRegF cr, regD src1, regD src2, immI0 zero) %{
5055 single_instruction;
5056 cr : X(write);
5057 src1 : E(read);
5058 src2 : E(read);
5059 FA : R;
5060 %}
5061
5062 // Floating Add Nop
5063 pipe_class fadd_nop() %{
5064 single_instruction;
5065 FA : R;
5066 %}
5067
5068 // Integer Store to Memory
5069 pipe_class istore_mem_reg(memory mem, iRegI src) %{
5070 single_instruction;
5071 mem : R(read);
5072 src : C(read);
5073 MS : R;
5074 %}
5075
5076 // Integer Store to Memory
5077 pipe_class istore_mem_spORreg(memory mem, sp_ptr_RegP src) %{
5078 single_instruction;
5079 mem : R(read);
5080 src : C(read);
5081 MS : R;
5082 %}
5083
5084 // Integer Store Zero to Memory
5085 pipe_class istore_mem_zero(memory mem, immI0 src) %{
5086 single_instruction;
5087 mem : R(read);
5088 MS : R;
5089 %}
5090
5091 // Special Stack Slot Store
5092 pipe_class istore_stk_reg(stackSlotI stkSlot, iRegI src) %{
5093 single_instruction;
5094 stkSlot : R(read);
5095 src : C(read);
5096 MS : R;
5097 %}
5098
5099 // Special Stack Slot Store
5100 pipe_class lstoreI_stk_reg(stackSlotL stkSlot, iRegI src) %{
5101 instruction_count(2); multiple_bundles;
5102 stkSlot : R(read);
5103 src : C(read);
5104 MS : R(2);
5105 %}
5106
5107 // Float Store
5108 pipe_class fstoreF_mem_reg(memory mem, RegF src) %{
5109 single_instruction;
5110 mem : R(read);
5111 src : C(read);
5112 MS : R;
5113 %}
5114
5115 // Float Store
5116 pipe_class fstoreF_mem_zero(memory mem, immF0 src) %{
5117 single_instruction;
5118 mem : R(read);
5119 MS : R;
5120 %}
5121
5122 // Double Store
5123 pipe_class fstoreD_mem_reg(memory mem, RegD src) %{
5124 instruction_count(1);
5125 mem : R(read);
5126 src : C(read);
5127 MS : R;
5128 %}
5129
5130 // Double Store
5131 pipe_class fstoreD_mem_zero(memory mem, immD0 src) %{
5132 single_instruction;
5133 mem : R(read);
5134 MS : R;
5135 %}
5136
5137 // Special Stack Slot Float Store
5138 pipe_class fstoreF_stk_reg(stackSlotI stkSlot, RegF src) %{
5139 single_instruction;
5140 stkSlot : R(read);
5141 src : C(read);
5142 MS : R;
5143 %}
5144
5145 // Special Stack Slot Double Store
5146 pipe_class fstoreD_stk_reg(stackSlotI stkSlot, RegD src) %{
5147 single_instruction;
5148 stkSlot : R(read);
5149 src : C(read);
5150 MS : R;
5151 %}
5152
5153 // Integer Load (when sign bit propagation not needed)
5154 pipe_class iload_mem(iRegI dst, memory mem) %{
5155 single_instruction;
5156 mem : R(read);
5157 dst : C(write);
5158 MS : R;
5159 %}
5160
5161 // Integer Load from stack operand
5162 pipe_class iload_stkD(iRegI dst, stackSlotD mem ) %{
5163 single_instruction;
5164 mem : R(read);
5165 dst : C(write);
5166 MS : R;
5167 %}
5168
5169 // Integer Load (when sign bit propagation or masking is needed)
5170 pipe_class iload_mask_mem(iRegI dst, memory mem) %{
5171 single_instruction;
5172 mem : R(read);
5173 dst : M(write);
5174 MS : R;
5175 %}
5176
5177 // Float Load
5178 pipe_class floadF_mem(regF dst, memory mem) %{
5179 single_instruction;
5180 mem : R(read);
5181 dst : M(write);
5182 MS : R;
5183 %}
5184
5185 // Float Load
5186 pipe_class floadD_mem(regD dst, memory mem) %{
5187 instruction_count(1); multiple_bundles; // Again, unaligned argument is only multiple case
5188 mem : R(read);
5189 dst : M(write);
5190 MS : R;
5191 %}
5192
5193 // Float Load
5194 pipe_class floadF_stk(regF dst, stackSlotI stkSlot) %{
5195 single_instruction;
5196 stkSlot : R(read);
5197 dst : M(write);
5198 MS : R;
5199 %}
5200
5201 // Float Load
5202 pipe_class floadD_stk(regD dst, stackSlotI stkSlot) %{
5203 single_instruction;
5204 stkSlot : R(read);
5205 dst : M(write);
5206 MS : R;
5207 %}
5208
5209 // Memory Nop
5210 pipe_class mem_nop() %{
5211 single_instruction;
5212 MS : R;
5213 %}
5214
5215 pipe_class sethi(iRegP dst, immI src) %{
5216 single_instruction;
5217 dst : E(write);
5218 IALU : R;
5219 %}
5220
5221 pipe_class loadPollP(iRegP poll) %{
5222 single_instruction;
5223 poll : R(read);
5224 MS : R;
5225 %}
5226
5227 pipe_class br(Universe br, label labl) %{
5228 single_instruction_with_delay_slot;
5229 BR : R;
5230 %}
5231
5232 pipe_class br_cc(Universe br, cmpOp cmp, flagsReg cr, label labl) %{
5233 single_instruction_with_delay_slot;
5234 cr : E(read);
5235 BR : R;
5236 %}
5237
5238 pipe_class br_reg(Universe br, cmpOp cmp, iRegI op1, label labl) %{
5239 single_instruction_with_delay_slot;
5240 op1 : E(read);
5241 BR : R;
5242 MS : R;
5243 %}
5244
5245 // Compare and branch
5246 pipe_class cmp_br_reg_reg(Universe br, cmpOp cmp, iRegI src1, iRegI src2, label labl, flagsReg cr) %{
5247 instruction_count(2); has_delay_slot;
5248 cr : E(write);
5249 src1 : R(read);
5250 src2 : R(read);
5251 IALU : R;
5252 BR : R;
5253 %}
5254
5255 // Compare and branch
5256 pipe_class cmp_br_reg_imm(Universe br, cmpOp cmp, iRegI src1, immI13 src2, label labl, flagsReg cr) %{
5257 instruction_count(2); has_delay_slot;
5258 cr : E(write);
5259 src1 : R(read);
5260 IALU : R;
5261 BR : R;
5262 %}
5263
5264 // Compare and branch using cbcond
5265 pipe_class cbcond_reg_reg(Universe br, cmpOp cmp, iRegI src1, iRegI src2, label labl) %{
5266 single_instruction;
5267 src1 : E(read);
5268 src2 : E(read);
5269 IALU : R;
5270 BR : R;
5271 %}
5272
5273 // Compare and branch using cbcond
5274 pipe_class cbcond_reg_imm(Universe br, cmpOp cmp, iRegI src1, immI5 src2, label labl) %{
5275 single_instruction;
5276 src1 : E(read);
5277 IALU : R;
5278 BR : R;
5279 %}
5280
5281 pipe_class br_fcc(Universe br, cmpOpF cc, flagsReg cr, label labl) %{
5282 single_instruction_with_delay_slot;
5283 cr : E(read);
5284 BR : R;
5285 %}
5286
5287 pipe_class br_nop() %{
5288 single_instruction;
5289 BR : R;
5290 %}
5291
5292 pipe_class simple_call(method meth) %{
5293 instruction_count(2); multiple_bundles; force_serialization;
5294 fixed_latency(100);
5295 BR : R(1);
5296 MS : R(1);
5297 A0 : R(1);
5298 %}
5299
5300 pipe_class compiled_call(method meth) %{
5301 instruction_count(1); multiple_bundles; force_serialization;
5302 fixed_latency(100);
5303 MS : R(1);
5304 %}
5305
5306 pipe_class call(method meth) %{
5307 instruction_count(0); multiple_bundles; force_serialization;
5308 fixed_latency(100);
5309 %}
5310
5311 pipe_class tail_call(Universe ignore, label labl) %{
5312 single_instruction; has_delay_slot;
5313 fixed_latency(100);
5314 BR : R(1);
5315 MS : R(1);
5316 %}
5317
5318 pipe_class ret(Universe ignore) %{
5319 single_instruction; has_delay_slot;
5320 BR : R(1);
5321 MS : R(1);
5322 %}
5323
5324 pipe_class ret_poll(g3RegP poll) %{
5325 instruction_count(3); has_delay_slot;
5326 poll : E(read);
5327 MS : R;
5328 %}
5329
5330 // The real do-nothing guy
5331 pipe_class empty( ) %{
5332 instruction_count(0);
5333 %}
5334
5335 pipe_class long_memory_op() %{
5336 instruction_count(0); multiple_bundles; force_serialization;
5337 fixed_latency(25);
5338 MS : R(1);
5339 %}
5340
5341 // Check-cast
5342 pipe_class partial_subtype_check_pipe(Universe ignore, iRegP array, iRegP match ) %{
5343 array : R(read);
5344 match : R(read);
5345 IALU : R(2);
5346 BR : R(2);
5347 MS : R;
5348 %}
5349
5350 // Convert FPU flags into +1,0,-1
5351 pipe_class floating_cmp( iRegI dst, regF src1, regF src2 ) %{
5352 src1 : E(read);
5353 src2 : E(read);
5354 dst : E(write);
5355 FA : R;
5356 MS : R(2);
5357 BR : R(2);
5358 %}
5359
5360 // Compare for p < q, and conditionally add y
5361 pipe_class cadd_cmpltmask( iRegI p, iRegI q, iRegI y ) %{
5362 p : E(read);
5363 q : E(read);
5364 y : E(read);
5365 IALU : R(3)
5366 %}
5367
5368 // Perform a compare, then move conditionally in a branch delay slot.
5369 pipe_class min_max( iRegI src2, iRegI srcdst ) %{
5370 src2 : E(read);
5371 srcdst : E(read);
5372 IALU : R;
5373 BR : R;
5374 %}
5375
5376 // Define the class for the Nop node
5377 define %{
5378 MachNop = ialu_nop;
5379 %}
5380
5381 %}
5382
5383 //----------INSTRUCTIONS-------------------------------------------------------
5384
5385 //------------Special Stack Slot instructions - no match rules-----------------
5386 instruct stkI_to_regF(regF dst, stackSlotI src) %{
5387 // No match rule to avoid chain rule match.
5388 effect(DEF dst, USE src);
5389 ins_cost(MEMORY_REF_COST);
5390 size(4);
5391 format %{ "LDF $src,$dst\t! stkI to regF" %}
5392 opcode(Assembler::ldf_op3);
5393 ins_encode(simple_form3_mem_reg(src, dst));
5394 ins_pipe(floadF_stk);
5395 %}
5396
5397 instruct stkL_to_regD(regD dst, stackSlotL src) %{
5398 // No match rule to avoid chain rule match.
5399 effect(DEF dst, USE src);
5400 ins_cost(MEMORY_REF_COST);
5401 size(4);
5402 format %{ "LDDF $src,$dst\t! stkL to regD" %}
5403 opcode(Assembler::lddf_op3);
5404 ins_encode(simple_form3_mem_reg(src, dst));
5405 ins_pipe(floadD_stk);
5406 %}
5407
5408 instruct regF_to_stkI(stackSlotI dst, regF src) %{
5409 // No match rule to avoid chain rule match.
5410 effect(DEF dst, USE src);
5411 ins_cost(MEMORY_REF_COST);
5412 size(4);
5413 format %{ "STF $src,$dst\t! regF to stkI" %}
5414 opcode(Assembler::stf_op3);
5415 ins_encode(simple_form3_mem_reg(dst, src));
5416 ins_pipe(fstoreF_stk_reg);
5417 %}
5418
5419 instruct regD_to_stkL(stackSlotL dst, regD src) %{
5420 // No match rule to avoid chain rule match.
5421 effect(DEF dst, USE src);
5422 ins_cost(MEMORY_REF_COST);
5423 size(4);
5424 format %{ "STDF $src,$dst\t! regD to stkL" %}
5425 opcode(Assembler::stdf_op3);
5426 ins_encode(simple_form3_mem_reg(dst, src));
5427 ins_pipe(fstoreD_stk_reg);
5428 %}
5429
5430 instruct regI_to_stkLHi(stackSlotL dst, iRegI src) %{
5431 effect(DEF dst, USE src);
5432 ins_cost(MEMORY_REF_COST*2);
5433 size(8);
5434 format %{ "STW $src,$dst.hi\t! long\n\t"
5435 "STW R_G0,$dst.lo" %}
5436 opcode(Assembler::stw_op3);
5437 ins_encode(simple_form3_mem_reg(dst, src), form3_mem_plus_4_reg(dst, R_G0));
5438 ins_pipe(lstoreI_stk_reg);
5439 %}
5440
5441 instruct regL_to_stkD(stackSlotD dst, iRegL src) %{
5442 // No match rule to avoid chain rule match.
5443 effect(DEF dst, USE src);
5444 ins_cost(MEMORY_REF_COST);
5445 size(4);
5446 format %{ "STX $src,$dst\t! regL to stkD" %}
5447 opcode(Assembler::stx_op3);
5448 ins_encode(simple_form3_mem_reg( dst, src ) );
5449 ins_pipe(istore_stk_reg);
5450 %}
5451
5452 //---------- Chain stack slots between similar types --------
5453
5454 // Load integer from stack slot
5455 instruct stkI_to_regI( iRegI dst, stackSlotI src ) %{
5456 match(Set dst src);
5457 ins_cost(MEMORY_REF_COST);
5458
5459 size(4);
5460 format %{ "LDUW $src,$dst\t!stk" %}
5461 opcode(Assembler::lduw_op3);
5462 ins_encode(simple_form3_mem_reg( src, dst ) );
5463 ins_pipe(iload_mem);
5464 %}
5465
5466 // Store integer to stack slot
5467 instruct regI_to_stkI( stackSlotI dst, iRegI src ) %{
5468 match(Set dst src);
5469 ins_cost(MEMORY_REF_COST);
5470
5471 size(4);
5472 format %{ "STW $src,$dst\t!stk" %}
5473 opcode(Assembler::stw_op3);
5474 ins_encode(simple_form3_mem_reg( dst, src ) );
5475 ins_pipe(istore_mem_reg);
5476 %}
5477
5478 // Load long from stack slot
5479 instruct stkL_to_regL( iRegL dst, stackSlotL src ) %{
5480 match(Set dst src);
5481
5482 ins_cost(MEMORY_REF_COST);
5483 size(4);
5484 format %{ "LDX $src,$dst\t! long" %}
5485 opcode(Assembler::ldx_op3);
5486 ins_encode(simple_form3_mem_reg( src, dst ) );
5487 ins_pipe(iload_mem);
5488 %}
5489
5490 // Store long to stack slot
5491 instruct regL_to_stkL(stackSlotL dst, iRegL src) %{
5492 match(Set dst src);
5493
5494 ins_cost(MEMORY_REF_COST);
5495 size(4);
5496 format %{ "STX $src,$dst\t! long" %}
5497 opcode(Assembler::stx_op3);
5498 ins_encode(simple_form3_mem_reg( dst, src ) );
5499 ins_pipe(istore_mem_reg);
5500 %}
5501
5502 #ifdef _LP64
5503 // Load pointer from stack slot, 64-bit encoding
5504 instruct stkP_to_regP( iRegP dst, stackSlotP src ) %{
5505 match(Set dst src);
5506 ins_cost(MEMORY_REF_COST);
5507 size(4);
5508 format %{ "LDX $src,$dst\t!ptr" %}
5509 opcode(Assembler::ldx_op3);
5510 ins_encode(simple_form3_mem_reg( src, dst ) );
5511 ins_pipe(iload_mem);
5512 %}
5513
5514 // Store pointer to stack slot
5515 instruct regP_to_stkP(stackSlotP dst, iRegP src) %{
5516 match(Set dst src);
5517 ins_cost(MEMORY_REF_COST);
5518 size(4);
5519 format %{ "STX $src,$dst\t!ptr" %}
5520 opcode(Assembler::stx_op3);
5521 ins_encode(simple_form3_mem_reg( dst, src ) );
5522 ins_pipe(istore_mem_reg);
5523 %}
5524 #else // _LP64
5525 // Load pointer from stack slot, 32-bit encoding
5526 instruct stkP_to_regP( iRegP dst, stackSlotP src ) %{
5527 match(Set dst src);
5528 ins_cost(MEMORY_REF_COST);
5529 format %{ "LDUW $src,$dst\t!ptr" %}
5530 opcode(Assembler::lduw_op3, Assembler::ldst_op);
5531 ins_encode(simple_form3_mem_reg( src, dst ) );
5532 ins_pipe(iload_mem);
5533 %}
5534
5535 // Store pointer to stack slot
5536 instruct regP_to_stkP(stackSlotP dst, iRegP src) %{
5537 match(Set dst src);
5538 ins_cost(MEMORY_REF_COST);
5539 format %{ "STW $src,$dst\t!ptr" %}
5540 opcode(Assembler::stw_op3, Assembler::ldst_op);
5541 ins_encode(simple_form3_mem_reg( dst, src ) );
5542 ins_pipe(istore_mem_reg);
5543 %}
5544 #endif // _LP64
5545
5546 //------------Special Nop instructions for bundling - no match rules-----------
5547 // Nop using the A0 functional unit
5548 instruct Nop_A0() %{
5549 ins_cost(0);
5550
5551 format %{ "NOP ! Alu Pipeline" %}
5552 opcode(Assembler::or_op3, Assembler::arith_op);
5553 ins_encode( form2_nop() );
5554 ins_pipe(ialu_nop_A0);
5555 %}
5556
5557 // Nop using the A1 functional unit
5558 instruct Nop_A1( ) %{
5559 ins_cost(0);
5560
5561 format %{ "NOP ! Alu Pipeline" %}
5562 opcode(Assembler::or_op3, Assembler::arith_op);
5563 ins_encode( form2_nop() );
5564 ins_pipe(ialu_nop_A1);
5565 %}
5566
5567 // Nop using the memory functional unit
5568 instruct Nop_MS( ) %{
5569 ins_cost(0);
5570
5571 format %{ "NOP ! Memory Pipeline" %}
5572 ins_encode( emit_mem_nop );
5573 ins_pipe(mem_nop);
5574 %}
5575
5576 // Nop using the floating add functional unit
5577 instruct Nop_FA( ) %{
5578 ins_cost(0);
5579
5580 format %{ "NOP ! Floating Add Pipeline" %}
5581 ins_encode( emit_fadd_nop );
5582 ins_pipe(fadd_nop);
5583 %}
5584
5585 // Nop using the branch functional unit
5586 instruct Nop_BR( ) %{
5587 ins_cost(0);
5588
5589 format %{ "NOP ! Branch Pipeline" %}
5590 ins_encode( emit_br_nop );
5591 ins_pipe(br_nop);
5592 %}
5593
5594 //----------Load/Store/Move Instructions---------------------------------------
5595 //----------Load Instructions--------------------------------------------------
5596 // Load Byte (8bit signed)
5597 instruct loadB(iRegI dst, memory mem) %{
5598 match(Set dst (LoadB mem));
5599 ins_cost(MEMORY_REF_COST);
5600
5601 size(4);
5602 format %{ "LDSB $mem,$dst\t! byte" %}
5603 ins_encode %{
5604 __ ldsb($mem$$Address, $dst$$Register);
5605 %}
5606 ins_pipe(iload_mask_mem);
5607 %}
5608
5609 // Load Byte (8bit signed) into a Long Register
5610 instruct loadB2L(iRegL dst, memory mem) %{
5611 match(Set dst (ConvI2L (LoadB mem)));
5612 ins_cost(MEMORY_REF_COST);
5613
5614 size(4);
5615 format %{ "LDSB $mem,$dst\t! byte -> long" %}
5616 ins_encode %{
5617 __ ldsb($mem$$Address, $dst$$Register);
5618 %}
5619 ins_pipe(iload_mask_mem);
5620 %}
5621
5622 // Load Unsigned Byte (8bit UNsigned) into an int reg
5623 instruct loadUB(iRegI dst, memory mem) %{
5624 match(Set dst (LoadUB mem));
5625 ins_cost(MEMORY_REF_COST);
5626
5627 size(4);
5628 format %{ "LDUB $mem,$dst\t! ubyte" %}
5629 ins_encode %{
5630 __ ldub($mem$$Address, $dst$$Register);
5631 %}
5632 ins_pipe(iload_mem);
5633 %}
5634
5635 // Load Unsigned Byte (8bit UNsigned) into a Long Register
5636 instruct loadUB2L(iRegL dst, memory mem) %{
5637 match(Set dst (ConvI2L (LoadUB mem)));
5638 ins_cost(MEMORY_REF_COST);
5639
5640 size(4);
5641 format %{ "LDUB $mem,$dst\t! ubyte -> long" %}
5642 ins_encode %{
5643 __ ldub($mem$$Address, $dst$$Register);
5644 %}
5645 ins_pipe(iload_mem);
5646 %}
5647
5648 // Load Unsigned Byte (8 bit UNsigned) with 8-bit mask into Long Register
5649 instruct loadUB2L_immI8(iRegL dst, memory mem, immI8 mask) %{
5650 match(Set dst (ConvI2L (AndI (LoadUB mem) mask)));
5651 ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5652
5653 size(2*4);
5654 format %{ "LDUB $mem,$dst\t# ubyte & 8-bit mask -> long\n\t"
5655 "AND $dst,$mask,$dst" %}
5656 ins_encode %{
5657 __ ldub($mem$$Address, $dst$$Register);
5658 __ and3($dst$$Register, $mask$$constant, $dst$$Register);
5659 %}
5660 ins_pipe(iload_mem);
5661 %}
5662
5663 // Load Short (16bit signed)
5664 instruct loadS(iRegI dst, memory mem) %{
5665 match(Set dst (LoadS mem));
5666 ins_cost(MEMORY_REF_COST);
5667
5668 size(4);
5669 format %{ "LDSH $mem,$dst\t! short" %}
5670 ins_encode %{
5671 __ ldsh($mem$$Address, $dst$$Register);
5672 %}
5673 ins_pipe(iload_mask_mem);
5674 %}
5675
5676 // Load Short (16 bit signed) to Byte (8 bit signed)
5677 instruct loadS2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{
5678 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour));
5679 ins_cost(MEMORY_REF_COST);
5680
5681 size(4);
5682
5683 format %{ "LDSB $mem+1,$dst\t! short -> byte" %}
5684 ins_encode %{
5685 __ ldsb($mem$$Address, $dst$$Register, 1);
5686 %}
5687 ins_pipe(iload_mask_mem);
5688 %}
5689
5690 // Load Short (16bit signed) into a Long Register
5691 instruct loadS2L(iRegL dst, memory mem) %{
5692 match(Set dst (ConvI2L (LoadS mem)));
5693 ins_cost(MEMORY_REF_COST);
5694
5695 size(4);
5696 format %{ "LDSH $mem,$dst\t! short -> long" %}
5697 ins_encode %{
5698 __ ldsh($mem$$Address, $dst$$Register);
5699 %}
5700 ins_pipe(iload_mask_mem);
5701 %}
5702
5703 // Load Unsigned Short/Char (16bit UNsigned)
5704 instruct loadUS(iRegI dst, memory mem) %{
5705 match(Set dst (LoadUS mem));
5706 ins_cost(MEMORY_REF_COST);
5707
5708 size(4);
5709 format %{ "LDUH $mem,$dst\t! ushort/char" %}
5710 ins_encode %{
5711 __ lduh($mem$$Address, $dst$$Register);
5712 %}
5713 ins_pipe(iload_mem);
5714 %}
5715
5716 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed)
5717 instruct loadUS2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{
5718 match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour));
5719 ins_cost(MEMORY_REF_COST);
5720
5721 size(4);
5722 format %{ "LDSB $mem+1,$dst\t! ushort -> byte" %}
5723 ins_encode %{
5724 __ ldsb($mem$$Address, $dst$$Register, 1);
5725 %}
5726 ins_pipe(iload_mask_mem);
5727 %}
5728
5729 // Load Unsigned Short/Char (16bit UNsigned) into a Long Register
5730 instruct loadUS2L(iRegL dst, memory mem) %{
5731 match(Set dst (ConvI2L (LoadUS mem)));
5732 ins_cost(MEMORY_REF_COST);
5733
5734 size(4);
5735 format %{ "LDUH $mem,$dst\t! ushort/char -> long" %}
5736 ins_encode %{
5737 __ lduh($mem$$Address, $dst$$Register);
5738 %}
5739 ins_pipe(iload_mem);
5740 %}
5741
5742 // Load Unsigned Short/Char (16bit UNsigned) with mask 0xFF into a Long Register
5743 instruct loadUS2L_immI_255(iRegL dst, indOffset13m7 mem, immI_255 mask) %{
5744 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5745 ins_cost(MEMORY_REF_COST);
5746
5747 size(4);
5748 format %{ "LDUB $mem+1,$dst\t! ushort/char & 0xFF -> long" %}
5749 ins_encode %{
5750 __ ldub($mem$$Address, $dst$$Register, 1); // LSB is index+1 on BE
5751 %}
5752 ins_pipe(iload_mem);
5753 %}
5754
5755 // Load Unsigned Short/Char (16bit UNsigned) with a 13-bit mask into a Long Register
5756 instruct loadUS2L_immI13(iRegL dst, memory mem, immI13 mask) %{
5757 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5758 ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5759
5760 size(2*4);
5761 format %{ "LDUH $mem,$dst\t! ushort/char & 13-bit mask -> long\n\t"
5762 "AND $dst,$mask,$dst" %}
5763 ins_encode %{
5764 Register Rdst = $dst$$Register;
5765 __ lduh($mem$$Address, Rdst);
5766 __ and3(Rdst, $mask$$constant, Rdst);
5767 %}
5768 ins_pipe(iload_mem);
5769 %}
5770
5771 // Load Unsigned Short/Char (16bit UNsigned) with a 16-bit mask into a Long Register
5772 instruct loadUS2L_immI16(iRegL dst, memory mem, immI16 mask, iRegL tmp) %{
5773 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5774 effect(TEMP dst, TEMP tmp);
5775 ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST);
5776
5777 format %{ "LDUH $mem,$dst\t! ushort/char & 16-bit mask -> long\n\t"
5778 "SET $mask,$tmp\n\t"
5779 "AND $dst,$tmp,$dst" %}
5780 ins_encode %{
5781 Register Rdst = $dst$$Register;
5782 Register Rtmp = $tmp$$Register;
5783 __ lduh($mem$$Address, Rdst);
5784 __ set($mask$$constant, Rtmp);
5785 __ and3(Rdst, Rtmp, Rdst);
5786 %}
5787 ins_pipe(iload_mem);
5788 %}
5789
5790 // Load Integer
5791 instruct loadI(iRegI dst, memory mem) %{
5792 match(Set dst (LoadI mem));
5793 ins_cost(MEMORY_REF_COST);
5794
5795 size(4);
5796 format %{ "LDUW $mem,$dst\t! int" %}
5797 ins_encode %{
5798 __ lduw($mem$$Address, $dst$$Register);
5799 %}
5800 ins_pipe(iload_mem);
5801 %}
5802
5803 // Load Integer to Byte (8 bit signed)
5804 instruct loadI2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{
5805 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour));
5806 ins_cost(MEMORY_REF_COST);
5807
5808 size(4);
5809
5810 format %{ "LDSB $mem+3,$dst\t! int -> byte" %}
5811 ins_encode %{
5812 __ ldsb($mem$$Address, $dst$$Register, 3);
5813 %}
5814 ins_pipe(iload_mask_mem);
5815 %}
5816
5817 // Load Integer to Unsigned Byte (8 bit UNsigned)
5818 instruct loadI2UB(iRegI dst, indOffset13m7 mem, immI_255 mask) %{
5819 match(Set dst (AndI (LoadI mem) mask));
5820 ins_cost(MEMORY_REF_COST);
5821
5822 size(4);
5823
5824 format %{ "LDUB $mem+3,$dst\t! int -> ubyte" %}
5825 ins_encode %{
5826 __ ldub($mem$$Address, $dst$$Register, 3);
5827 %}
5828 ins_pipe(iload_mask_mem);
5829 %}
5830
5831 // Load Integer to Short (16 bit signed)
5832 instruct loadI2S(iRegI dst, indOffset13m7 mem, immI_16 sixteen) %{
5833 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen));
5834 ins_cost(MEMORY_REF_COST);
5835
5836 size(4);
5837
5838 format %{ "LDSH $mem+2,$dst\t! int -> short" %}
5839 ins_encode %{
5840 __ ldsh($mem$$Address, $dst$$Register, 2);
5841 %}
5842 ins_pipe(iload_mask_mem);
5843 %}
5844
5845 // Load Integer to Unsigned Short (16 bit UNsigned)
5846 instruct loadI2US(iRegI dst, indOffset13m7 mem, immI_65535 mask) %{
5847 match(Set dst (AndI (LoadI mem) mask));
5848 ins_cost(MEMORY_REF_COST);
5849
5850 size(4);
5851
5852 format %{ "LDUH $mem+2,$dst\t! int -> ushort/char" %}
5853 ins_encode %{
5854 __ lduh($mem$$Address, $dst$$Register, 2);
5855 %}
5856 ins_pipe(iload_mask_mem);
5857 %}
5858
5859 // Load Integer into a Long Register
5860 instruct loadI2L(iRegL dst, memory mem) %{
5861 match(Set dst (ConvI2L (LoadI mem)));
5862 ins_cost(MEMORY_REF_COST);
5863
5864 size(4);
5865 format %{ "LDSW $mem,$dst\t! int -> long" %}
5866 ins_encode %{
5867 __ ldsw($mem$$Address, $dst$$Register);
5868 %}
5869 ins_pipe(iload_mask_mem);
5870 %}
5871
5872 // Load Integer with mask 0xFF into a Long Register
5873 instruct loadI2L_immI_255(iRegL dst, indOffset13m7 mem, immI_255 mask) %{
5874 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5875 ins_cost(MEMORY_REF_COST);
5876
5877 size(4);
5878 format %{ "LDUB $mem+3,$dst\t! int & 0xFF -> long" %}
5879 ins_encode %{
5880 __ ldub($mem$$Address, $dst$$Register, 3); // LSB is index+3 on BE
5881 %}
5882 ins_pipe(iload_mem);
5883 %}
5884
5885 // Load Integer with mask 0xFFFF into a Long Register
5886 instruct loadI2L_immI_65535(iRegL dst, indOffset13m7 mem, immI_65535 mask) %{
5887 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5888 ins_cost(MEMORY_REF_COST);
5889
5890 size(4);
5891 format %{ "LDUH $mem+2,$dst\t! int & 0xFFFF -> long" %}
5892 ins_encode %{
5893 __ lduh($mem$$Address, $dst$$Register, 2); // LSW is index+2 on BE
5894 %}
5895 ins_pipe(iload_mem);
5896 %}
5897
5898 // Load Integer with a 12-bit mask into a Long Register
5899 instruct loadI2L_immU12(iRegL dst, memory mem, immU12 mask) %{
5900 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5901 ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5902
5903 size(2*4);
5904 format %{ "LDUW $mem,$dst\t! int & 12-bit mask -> long\n\t"
5905 "AND $dst,$mask,$dst" %}
5906 ins_encode %{
5907 Register Rdst = $dst$$Register;
5908 __ lduw($mem$$Address, Rdst);
5909 __ and3(Rdst, $mask$$constant, Rdst);
5910 %}
5911 ins_pipe(iload_mem);
5912 %}
5913
5914 // Load Integer with a 31-bit mask into a Long Register
5915 instruct loadI2L_immU31(iRegL dst, memory mem, immU31 mask, iRegL tmp) %{
5916 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5917 effect(TEMP dst, TEMP tmp);
5918 ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST);
5919
5920 format %{ "LDUW $mem,$dst\t! int & 31-bit mask -> long\n\t"
5921 "SET $mask,$tmp\n\t"
5922 "AND $dst,$tmp,$dst" %}
5923 ins_encode %{
5924 Register Rdst = $dst$$Register;
5925 Register Rtmp = $tmp$$Register;
5926 __ lduw($mem$$Address, Rdst);
5927 __ set($mask$$constant, Rtmp);
5928 __ and3(Rdst, Rtmp, Rdst);
5929 %}
5930 ins_pipe(iload_mem);
5931 %}
5932
5933 // Load Unsigned Integer into a Long Register
5934 instruct loadUI2L(iRegL dst, memory mem, immL_32bits mask) %{
5935 match(Set dst (AndL (ConvI2L (LoadI mem)) mask));
5936 ins_cost(MEMORY_REF_COST);
5937
5938 size(4);
5939 format %{ "LDUW $mem,$dst\t! uint -> long" %}
5940 ins_encode %{
5941 __ lduw($mem$$Address, $dst$$Register);
5942 %}
5943 ins_pipe(iload_mem);
5944 %}
5945
5946 // Load Long - aligned
5947 instruct loadL(iRegL dst, memory mem ) %{
5948 match(Set dst (LoadL mem));
5949 ins_cost(MEMORY_REF_COST);
5950
5951 size(4);
5952 format %{ "LDX $mem,$dst\t! long" %}
5953 ins_encode %{
5954 __ ldx($mem$$Address, $dst$$Register);
5955 %}
5956 ins_pipe(iload_mem);
5957 %}
5958
5959 // Load Long - UNaligned
5960 instruct loadL_unaligned(iRegL dst, memory mem, o7RegI tmp) %{
5961 match(Set dst (LoadL_unaligned mem));
5962 effect(KILL tmp);
5963 ins_cost(MEMORY_REF_COST*2+DEFAULT_COST);
5964 size(16);
5965 format %{ "LDUW $mem+4,R_O7\t! misaligned long\n"
5966 "\tLDUW $mem ,$dst\n"
5967 "\tSLLX #32, $dst, $dst\n"
5968 "\tOR $dst, R_O7, $dst" %}
5969 opcode(Assembler::lduw_op3);
5970 ins_encode(form3_mem_reg_long_unaligned_marshal( mem, dst ));
5971 ins_pipe(iload_mem);
5972 %}
5973
5974 // Load Range
5975 instruct loadRange(iRegI dst, memory mem) %{
5976 match(Set dst (LoadRange mem));
5977 ins_cost(MEMORY_REF_COST);
5978
5979 size(4);
5980 format %{ "LDUW $mem,$dst\t! range" %}
5981 opcode(Assembler::lduw_op3);
5982 ins_encode(simple_form3_mem_reg( mem, dst ) );
5983 ins_pipe(iload_mem);
5984 %}
5985
5986 // Load Integer into %f register (for fitos/fitod)
5987 instruct loadI_freg(regF dst, memory mem) %{
5988 match(Set dst (LoadI mem));
5989 ins_cost(MEMORY_REF_COST);
5990 size(4);
5991
5992 format %{ "LDF $mem,$dst\t! for fitos/fitod" %}
5993 opcode(Assembler::ldf_op3);
5994 ins_encode(simple_form3_mem_reg( mem, dst ) );
5995 ins_pipe(floadF_mem);
5996 %}
5997
5998 // Load Pointer
5999 instruct loadP(iRegP dst, memory mem) %{
6000 match(Set dst (LoadP mem));
6001 ins_cost(MEMORY_REF_COST);
6002 size(4);
6003
6004 #ifndef _LP64
6005 format %{ "LDUW $mem,$dst\t! ptr" %}
6006 ins_encode %{
6007 __ lduw($mem$$Address, $dst$$Register);
6008 %}
6009 #else
6010 format %{ "LDX $mem,$dst\t! ptr" %}
6011 ins_encode %{
6012 __ ldx($mem$$Address, $dst$$Register);
6013 %}
6014 #endif
6015 ins_pipe(iload_mem);
6016 %}
6017
6018 // Load Compressed Pointer
6019 instruct loadN(iRegN dst, memory mem) %{
6020 match(Set dst (LoadN mem));
6021 ins_cost(MEMORY_REF_COST);
6022 size(4);
6023
6024 format %{ "LDUW $mem,$dst\t! compressed ptr" %}
6025 ins_encode %{
6026 __ lduw($mem$$Address, $dst$$Register);
6027 %}
6028 ins_pipe(iload_mem);
6029 %}
6030
6031 // Load Klass Pointer
6032 instruct loadKlass(iRegP dst, memory mem) %{
6033 match(Set dst (LoadKlass mem));
6034 ins_cost(MEMORY_REF_COST);
6035 size(4);
6036
6037 #ifndef _LP64
6038 format %{ "LDUW $mem,$dst\t! klass ptr" %}
6039 ins_encode %{
6040 __ lduw($mem$$Address, $dst$$Register);
6041 %}
6042 #else
6043 format %{ "LDX $mem,$dst\t! klass ptr" %}
6044 ins_encode %{
6045 __ ldx($mem$$Address, $dst$$Register);
6046 %}
6047 #endif
6048 ins_pipe(iload_mem);
6049 %}
6050
6051 // Load narrow Klass Pointer
6052 instruct loadNKlass(iRegN dst, memory mem) %{
6053 match(Set dst (LoadNKlass mem));
6054 ins_cost(MEMORY_REF_COST);
6055 size(4);
6056
6057 format %{ "LDUW $mem,$dst\t! compressed klass ptr" %}
6058 ins_encode %{
6059 __ lduw($mem$$Address, $dst$$Register);
6060 %}
6061 ins_pipe(iload_mem);
6062 %}
6063
6064 // Load Double
6065 instruct loadD(regD dst, memory mem) %{
6066 match(Set dst (LoadD mem));
6067 ins_cost(MEMORY_REF_COST);
6068
6069 size(4);
6070 format %{ "LDDF $mem,$dst" %}
6071 opcode(Assembler::lddf_op3);
6072 ins_encode(simple_form3_mem_reg( mem, dst ) );
6073 ins_pipe(floadD_mem);
6074 %}
6075
6076 // Load Double - UNaligned
6077 instruct loadD_unaligned(regD_low dst, memory mem ) %{
6078 match(Set dst (LoadD_unaligned mem));
6079 ins_cost(MEMORY_REF_COST*2+DEFAULT_COST);
6080 size(8);
6081 format %{ "LDF $mem ,$dst.hi\t! misaligned double\n"
6082 "\tLDF $mem+4,$dst.lo\t!" %}
6083 opcode(Assembler::ldf_op3);
6084 ins_encode( form3_mem_reg_double_unaligned( mem, dst ));
6085 ins_pipe(iload_mem);
6086 %}
6087
6088 // Load Float
6089 instruct loadF(regF dst, memory mem) %{
6090 match(Set dst (LoadF mem));
6091 ins_cost(MEMORY_REF_COST);
6092
6093 size(4);
6094 format %{ "LDF $mem,$dst" %}
6095 opcode(Assembler::ldf_op3);
6096 ins_encode(simple_form3_mem_reg( mem, dst ) );
6097 ins_pipe(floadF_mem);
6098 %}
6099
6100 // Load Constant
6101 instruct loadConI( iRegI dst, immI src ) %{
6102 match(Set dst src);
6103 ins_cost(DEFAULT_COST * 3/2);
6104 format %{ "SET $src,$dst" %}
6105 ins_encode( Set32(src, dst) );
6106 ins_pipe(ialu_hi_lo_reg);
6107 %}
6108
6109 instruct loadConI13( iRegI dst, immI13 src ) %{
6110 match(Set dst src);
6111
6112 size(4);
6113 format %{ "MOV $src,$dst" %}
6114 ins_encode( Set13( src, dst ) );
6115 ins_pipe(ialu_imm);
6116 %}
6117
6118 #ifndef _LP64
6119 instruct loadConP(iRegP dst, immP con) %{
6120 match(Set dst con);
6121 ins_cost(DEFAULT_COST * 3/2);
6122 format %{ "SET $con,$dst\t!ptr" %}
6123 ins_encode %{
6124 // [RGV] This next line should be generated from ADLC
6125 if (_opnds[1]->constant_is_oop()) {
6126 intptr_t val = $con$$constant;
6127 __ set_oop_constant((jobject) val, $dst$$Register);
6128 } else { // non-oop pointers, e.g. card mark base, heap top
6129 __ set($con$$constant, $dst$$Register);
6130 }
6131 %}
6132 ins_pipe(loadConP);
6133 %}
6134 #else
6135 instruct loadConP_set(iRegP dst, immP_set con) %{
6136 match(Set dst con);
6137 ins_cost(DEFAULT_COST * 3/2);
6138 format %{ "SET $con,$dst\t! ptr" %}
6139 ins_encode %{
6140 // [RGV] This next line should be generated from ADLC
6141 if (_opnds[1]->constant_is_oop()) {
6142 intptr_t val = $con$$constant;
6143 __ set_oop_constant((jobject) val, $dst$$Register);
6144 } else { // non-oop pointers, e.g. card mark base, heap top
6145 __ set($con$$constant, $dst$$Register);
6146 }
6147 %}
6148 ins_pipe(loadConP);
6149 %}
6150
6151 instruct loadConP_load(iRegP dst, immP_load con) %{
6152 match(Set dst con);
6153 ins_cost(MEMORY_REF_COST);
6154 format %{ "LD [$constanttablebase + $constantoffset],$dst\t! load from constant table: ptr=$con" %}
6155 ins_encode %{
6156 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $dst$$Register);
6157 __ ld_ptr($constanttablebase, con_offset, $dst$$Register);
6158 %}
6159 ins_pipe(loadConP);
6160 %}
6161
6162 instruct loadConP_no_oop_cheap(iRegP dst, immP_no_oop_cheap con) %{
6163 match(Set dst con);
6164 ins_cost(DEFAULT_COST * 3/2);
6165 format %{ "SET $con,$dst\t! non-oop ptr" %}
6166 ins_encode %{
6167 __ set($con$$constant, $dst$$Register);
6168 %}
6169 ins_pipe(loadConP);
6170 %}
6171 #endif // _LP64
6172
6173 instruct loadConP0(iRegP dst, immP0 src) %{
6174 match(Set dst src);
6175
6176 size(4);
6177 format %{ "CLR $dst\t!ptr" %}
6178 ins_encode %{
6179 __ clr($dst$$Register);
6180 %}
6181 ins_pipe(ialu_imm);
6182 %}
6183
6184 instruct loadConP_poll(iRegP dst, immP_poll src) %{
6185 match(Set dst src);
6186 ins_cost(DEFAULT_COST);
6187 format %{ "SET $src,$dst\t!ptr" %}
6188 ins_encode %{
6189 AddressLiteral polling_page(os::get_polling_page());
6190 __ sethi(polling_page, reg_to_register_object($dst$$reg));
6191 %}
6192 ins_pipe(loadConP_poll);
6193 %}
6194
6195 instruct loadConN0(iRegN dst, immN0 src) %{
6196 match(Set dst src);
6197
6198 size(4);
6199 format %{ "CLR $dst\t! compressed NULL ptr" %}
6200 ins_encode %{
6201 __ clr($dst$$Register);
6202 %}
6203 ins_pipe(ialu_imm);
6204 %}
6205
6206 instruct loadConN(iRegN dst, immN src) %{
6207 match(Set dst src);
6208 ins_cost(DEFAULT_COST * 3/2);
6209 format %{ "SET $src,$dst\t! compressed ptr" %}
6210 ins_encode %{
6211 Register dst = $dst$$Register;
6212 __ set_narrow_oop((jobject)$src$$constant, dst);
6213 %}
6214 ins_pipe(ialu_hi_lo_reg);
6215 %}
6216
6217 // Materialize long value (predicated by immL_cheap).
6218 instruct loadConL_set64(iRegL dst, immL_cheap con, o7RegL tmp) %{
6219 match(Set dst con);
6220 effect(KILL tmp);
6221 ins_cost(DEFAULT_COST * 3);
6222 format %{ "SET64 $con,$dst KILL $tmp\t! cheap long" %}
6223 ins_encode %{
6224 __ set64($con$$constant, $dst$$Register, $tmp$$Register);
6225 %}
6226 ins_pipe(loadConL);
6227 %}
6228
6229 // Load long value from constant table (predicated by immL_expensive).
6230 instruct loadConL_ldx(iRegL dst, immL_expensive con) %{
6231 match(Set dst con);
6232 ins_cost(MEMORY_REF_COST);
6233 format %{ "LDX [$constanttablebase + $constantoffset],$dst\t! load from constant table: long=$con" %}
6234 ins_encode %{
6235 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $dst$$Register);
6236 __ ldx($constanttablebase, con_offset, $dst$$Register);
6237 %}
6238 ins_pipe(loadConL);
6239 %}
6240
6241 instruct loadConL0( iRegL dst, immL0 src ) %{
6242 match(Set dst src);
6243 ins_cost(DEFAULT_COST);
6244 size(4);
6245 format %{ "CLR $dst\t! long" %}
6246 ins_encode( Set13( src, dst ) );
6247 ins_pipe(ialu_imm);
6248 %}
6249
6250 instruct loadConL13( iRegL dst, immL13 src ) %{
6251 match(Set dst src);
6252 ins_cost(DEFAULT_COST * 2);
6253
6254 size(4);
6255 format %{ "MOV $src,$dst\t! long" %}
6256 ins_encode( Set13( src, dst ) );
6257 ins_pipe(ialu_imm);
6258 %}
6259
6260 instruct loadConF(regF dst, immF con, o7RegI tmp) %{
6261 match(Set dst con);
6262 effect(KILL tmp);
6263 format %{ "LDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: float=$con" %}
6264 ins_encode %{
6265 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $tmp$$Register);
6266 __ ldf(FloatRegisterImpl::S, $constanttablebase, con_offset, $dst$$FloatRegister);
6267 %}
6268 ins_pipe(loadConFD);
6269 %}
6270
6271 instruct loadConD(regD dst, immD con, o7RegI tmp) %{
6272 match(Set dst con);
6273 effect(KILL tmp);
6274 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: double=$con" %}
6275 ins_encode %{
6276 // XXX This is a quick fix for 6833573.
6277 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset($con), $dst$$FloatRegister);
6278 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $tmp$$Register);
6279 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
6280 %}
6281 ins_pipe(loadConFD);
6282 %}
6283
6284 // Prefetch instructions.
6285 // Must be safe to execute with invalid address (cannot fault).
6286
6287 instruct prefetchr( memory mem ) %{
6288 match( PrefetchRead mem );
6289 ins_cost(MEMORY_REF_COST);
6290 size(4);
6291
6292 format %{ "PREFETCH $mem,0\t! Prefetch read-many" %}
6293 opcode(Assembler::prefetch_op3);
6294 ins_encode( form3_mem_prefetch_read( mem ) );
6295 ins_pipe(iload_mem);
6296 %}
6297
6298 instruct prefetchw( memory mem ) %{
6299 match( PrefetchWrite mem );
6300 ins_cost(MEMORY_REF_COST);
6301 size(4);
6302
6303 format %{ "PREFETCH $mem,2\t! Prefetch write-many (and read)" %}
6304 opcode(Assembler::prefetch_op3);
6305 ins_encode( form3_mem_prefetch_write( mem ) );
6306 ins_pipe(iload_mem);
6307 %}
6308
6309 // Prefetch instructions for allocation.
6310
6311 instruct prefetchAlloc( memory mem ) %{
6312 predicate(AllocatePrefetchInstr == 0);
6313 match( PrefetchAllocation mem );
6314 ins_cost(MEMORY_REF_COST);
6315 size(4);
6316
6317 format %{ "PREFETCH $mem,2\t! Prefetch allocation" %}
6318 opcode(Assembler::prefetch_op3);
6319 ins_encode( form3_mem_prefetch_write( mem ) );
6320 ins_pipe(iload_mem);
6321 %}
6322
6323 // Use BIS instruction to prefetch for allocation.
6324 // Could fault, need space at the end of TLAB.
6325 instruct prefetchAlloc_bis( iRegP dst ) %{
6326 predicate(AllocatePrefetchInstr == 1);
6327 match( PrefetchAllocation dst );
6328 ins_cost(MEMORY_REF_COST);
6329 size(4);
6330
6331 format %{ "STXA [$dst]\t! // Prefetch allocation using BIS" %}
6332 ins_encode %{
6333 __ stxa(G0, $dst$$Register, G0, Assembler::ASI_ST_BLKINIT_PRIMARY);
6334 %}
6335 ins_pipe(istore_mem_reg);
6336 %}
6337
6338 // Next code is used for finding next cache line address to prefetch.
6339 #ifndef _LP64
6340 instruct cacheLineAdr( iRegP dst, iRegP src, immI13 mask ) %{
6341 match(Set dst (CastX2P (AndI (CastP2X src) mask)));
6342 ins_cost(DEFAULT_COST);
6343 size(4);
6344
6345 format %{ "AND $src,$mask,$dst\t! next cache line address" %}
6346 ins_encode %{
6347 __ and3($src$$Register, $mask$$constant, $dst$$Register);
6348 %}
6349 ins_pipe(ialu_reg_imm);
6350 %}
6351 #else
6352 instruct cacheLineAdr( iRegP dst, iRegP src, immL13 mask ) %{
6353 match(Set dst (CastX2P (AndL (CastP2X src) mask)));
6354 ins_cost(DEFAULT_COST);
6355 size(4);
6356
6357 format %{ "AND $src,$mask,$dst\t! next cache line address" %}
6358 ins_encode %{
6359 __ and3($src$$Register, $mask$$constant, $dst$$Register);
6360 %}
6361 ins_pipe(ialu_reg_imm);
6362 %}
6363 #endif
6364
6365 //----------Store Instructions-------------------------------------------------
6366 // Store Byte
6367 instruct storeB(memory mem, iRegI src) %{
6368 match(Set mem (StoreB mem src));
6369 ins_cost(MEMORY_REF_COST);
6370
6371 size(4);
6372 format %{ "STB $src,$mem\t! byte" %}
6373 opcode(Assembler::stb_op3);
6374 ins_encode(simple_form3_mem_reg( mem, src ) );
6375 ins_pipe(istore_mem_reg);
6376 %}
6377
6378 instruct storeB0(memory mem, immI0 src) %{
6379 match(Set mem (StoreB mem src));
6380 ins_cost(MEMORY_REF_COST);
6381
6382 size(4);
6383 format %{ "STB $src,$mem\t! byte" %}
6384 opcode(Assembler::stb_op3);
6385 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6386 ins_pipe(istore_mem_zero);
6387 %}
6388
6389 instruct storeCM0(memory mem, immI0 src) %{
6390 match(Set mem (StoreCM mem src));
6391 ins_cost(MEMORY_REF_COST);
6392
6393 size(4);
6394 format %{ "STB $src,$mem\t! CMS card-mark byte 0" %}
6395 opcode(Assembler::stb_op3);
6396 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6397 ins_pipe(istore_mem_zero);
6398 %}
6399
6400 // Store Char/Short
6401 instruct storeC(memory mem, iRegI src) %{
6402 match(Set mem (StoreC mem src));
6403 ins_cost(MEMORY_REF_COST);
6404
6405 size(4);
6406 format %{ "STH $src,$mem\t! short" %}
6407 opcode(Assembler::sth_op3);
6408 ins_encode(simple_form3_mem_reg( mem, src ) );
6409 ins_pipe(istore_mem_reg);
6410 %}
6411
6412 instruct storeC0(memory mem, immI0 src) %{
6413 match(Set mem (StoreC mem src));
6414 ins_cost(MEMORY_REF_COST);
6415
6416 size(4);
6417 format %{ "STH $src,$mem\t! short" %}
6418 opcode(Assembler::sth_op3);
6419 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6420 ins_pipe(istore_mem_zero);
6421 %}
6422
6423 // Store Integer
6424 instruct storeI(memory mem, iRegI src) %{
6425 match(Set mem (StoreI mem src));
6426 ins_cost(MEMORY_REF_COST);
6427
6428 size(4);
6429 format %{ "STW $src,$mem" %}
6430 opcode(Assembler::stw_op3);
6431 ins_encode(simple_form3_mem_reg( mem, src ) );
6432 ins_pipe(istore_mem_reg);
6433 %}
6434
6435 // Store Long
6436 instruct storeL(memory mem, iRegL src) %{
6437 match(Set mem (StoreL mem src));
6438 ins_cost(MEMORY_REF_COST);
6439 size(4);
6440 format %{ "STX $src,$mem\t! long" %}
6441 opcode(Assembler::stx_op3);
6442 ins_encode(simple_form3_mem_reg( mem, src ) );
6443 ins_pipe(istore_mem_reg);
6444 %}
6445
6446 instruct storeI0(memory mem, immI0 src) %{
6447 match(Set mem (StoreI mem src));
6448 ins_cost(MEMORY_REF_COST);
6449
6450 size(4);
6451 format %{ "STW $src,$mem" %}
6452 opcode(Assembler::stw_op3);
6453 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6454 ins_pipe(istore_mem_zero);
6455 %}
6456
6457 instruct storeL0(memory mem, immL0 src) %{
6458 match(Set mem (StoreL mem src));
6459 ins_cost(MEMORY_REF_COST);
6460
6461 size(4);
6462 format %{ "STX $src,$mem" %}
6463 opcode(Assembler::stx_op3);
6464 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6465 ins_pipe(istore_mem_zero);
6466 %}
6467
6468 // Store Integer from float register (used after fstoi)
6469 instruct storeI_Freg(memory mem, regF src) %{
6470 match(Set mem (StoreI mem src));
6471 ins_cost(MEMORY_REF_COST);
6472
6473 size(4);
6474 format %{ "STF $src,$mem\t! after fstoi/fdtoi" %}
6475 opcode(Assembler::stf_op3);
6476 ins_encode(simple_form3_mem_reg( mem, src ) );
6477 ins_pipe(fstoreF_mem_reg);
6478 %}
6479
6480 // Store Pointer
6481 instruct storeP(memory dst, sp_ptr_RegP src) %{
6482 match(Set dst (StoreP dst src));
6483 ins_cost(MEMORY_REF_COST);
6484 size(4);
6485
6486 #ifndef _LP64
6487 format %{ "STW $src,$dst\t! ptr" %}
6488 opcode(Assembler::stw_op3, 0, REGP_OP);
6489 #else
6490 format %{ "STX $src,$dst\t! ptr" %}
6491 opcode(Assembler::stx_op3, 0, REGP_OP);
6492 #endif
6493 ins_encode( form3_mem_reg( dst, src ) );
6494 ins_pipe(istore_mem_spORreg);
6495 %}
6496
6497 instruct storeP0(memory dst, immP0 src) %{
6498 match(Set dst (StoreP dst src));
6499 ins_cost(MEMORY_REF_COST);
6500 size(4);
6501
6502 #ifndef _LP64
6503 format %{ "STW $src,$dst\t! ptr" %}
6504 opcode(Assembler::stw_op3, 0, REGP_OP);
6505 #else
6506 format %{ "STX $src,$dst\t! ptr" %}
6507 opcode(Assembler::stx_op3, 0, REGP_OP);
6508 #endif
6509 ins_encode( form3_mem_reg( dst, R_G0 ) );
6510 ins_pipe(istore_mem_zero);
6511 %}
6512
6513 // Store Compressed Pointer
6514 instruct storeN(memory dst, iRegN src) %{
6515 match(Set dst (StoreN dst src));
6516 ins_cost(MEMORY_REF_COST);
6517 size(4);
6518
6519 format %{ "STW $src,$dst\t! compressed ptr" %}
6520 ins_encode %{
6521 Register base = as_Register($dst$$base);
6522 Register index = as_Register($dst$$index);
6523 Register src = $src$$Register;
6524 if (index != G0) {
6525 __ stw(src, base, index);
6526 } else {
6527 __ stw(src, base, $dst$$disp);
6528 }
6529 %}
6530 ins_pipe(istore_mem_spORreg);
6531 %}
6532
6533 instruct storeN0(memory dst, immN0 src) %{
6534 match(Set dst (StoreN dst src));
6535 ins_cost(MEMORY_REF_COST);
6536 size(4);
6537
6538 format %{ "STW $src,$dst\t! compressed ptr" %}
6539 ins_encode %{
6540 Register base = as_Register($dst$$base);
6541 Register index = as_Register($dst$$index);
6542 if (index != G0) {
6543 __ stw(0, base, index);
6544 } else {
6545 __ stw(0, base, $dst$$disp);
6546 }
6547 %}
6548 ins_pipe(istore_mem_zero);
6549 %}
6550
6551 // Store Double
6552 instruct storeD( memory mem, regD src) %{
6553 match(Set mem (StoreD mem src));
6554 ins_cost(MEMORY_REF_COST);
6555
6556 size(4);
6557 format %{ "STDF $src,$mem" %}
6558 opcode(Assembler::stdf_op3);
6559 ins_encode(simple_form3_mem_reg( mem, src ) );
6560 ins_pipe(fstoreD_mem_reg);
6561 %}
6562
6563 instruct storeD0( memory mem, immD0 src) %{
6564 match(Set mem (StoreD mem src));
6565 ins_cost(MEMORY_REF_COST);
6566
6567 size(4);
6568 format %{ "STX $src,$mem" %}
6569 opcode(Assembler::stx_op3);
6570 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6571 ins_pipe(fstoreD_mem_zero);
6572 %}
6573
6574 // Store Float
6575 instruct storeF( memory mem, regF src) %{
6576 match(Set mem (StoreF mem src));
6577 ins_cost(MEMORY_REF_COST);
6578
6579 size(4);
6580 format %{ "STF $src,$mem" %}
6581 opcode(Assembler::stf_op3);
6582 ins_encode(simple_form3_mem_reg( mem, src ) );
6583 ins_pipe(fstoreF_mem_reg);
6584 %}
6585
6586 instruct storeF0( memory mem, immF0 src) %{
6587 match(Set mem (StoreF mem src));
6588 ins_cost(MEMORY_REF_COST);
6589
6590 size(4);
6591 format %{ "STW $src,$mem\t! storeF0" %}
6592 opcode(Assembler::stw_op3);
6593 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6594 ins_pipe(fstoreF_mem_zero);
6595 %}
6596
6597 // Convert oop pointer into compressed form
6598 instruct encodeHeapOop(iRegN dst, iRegP src) %{
6599 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull);
6600 match(Set dst (EncodeP src));
6601 format %{ "encode_heap_oop $src, $dst" %}
6602 ins_encode %{
6603 __ encode_heap_oop($src$$Register, $dst$$Register);
6604 %}
6605 ins_pipe(ialu_reg);
6606 %}
6607
6608 instruct encodeHeapOop_not_null(iRegN dst, iRegP src) %{
6609 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull);
6610 match(Set dst (EncodeP src));
6611 format %{ "encode_heap_oop_not_null $src, $dst" %}
6612 ins_encode %{
6613 __ encode_heap_oop_not_null($src$$Register, $dst$$Register);
6614 %}
6615 ins_pipe(ialu_reg);
6616 %}
6617
6618 instruct decodeHeapOop(iRegP dst, iRegN src) %{
6619 predicate(n->bottom_type()->is_oopptr()->ptr() != TypePtr::NotNull &&
6620 n->bottom_type()->is_oopptr()->ptr() != TypePtr::Constant);
6621 match(Set dst (DecodeN src));
6622 format %{ "decode_heap_oop $src, $dst" %}
6623 ins_encode %{
6624 __ decode_heap_oop($src$$Register, $dst$$Register);
6625 %}
6626 ins_pipe(ialu_reg);
6627 %}
6628
6629 instruct decodeHeapOop_not_null(iRegP dst, iRegN src) %{
6630 predicate(n->bottom_type()->is_oopptr()->ptr() == TypePtr::NotNull ||
6631 n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant);
6632 match(Set dst (DecodeN src));
6633 format %{ "decode_heap_oop_not_null $src, $dst" %}
6634 ins_encode %{
6635 __ decode_heap_oop_not_null($src$$Register, $dst$$Register);
6636 %}
6637 ins_pipe(ialu_reg);
6638 %}
6639
6640
6641 //----------MemBar Instructions-----------------------------------------------
6642 // Memory barrier flavors
6643
6644 instruct membar_acquire() %{
6645 match(MemBarAcquire);
6646 ins_cost(4*MEMORY_REF_COST);
6647
6648 size(0);
6649 format %{ "MEMBAR-acquire" %}
6650 ins_encode( enc_membar_acquire );
6651 ins_pipe(long_memory_op);
6652 %}
6653
6654 instruct membar_acquire_lock() %{
6655 match(MemBarAcquireLock);
6656 ins_cost(0);
6657
6658 size(0);
6659 format %{ "!MEMBAR-acquire (CAS in prior FastLock so empty encoding)" %}
6660 ins_encode( );
6661 ins_pipe(empty);
6662 %}
6663
6664 instruct membar_release() %{
6665 match(MemBarRelease);
6666 ins_cost(4*MEMORY_REF_COST);
6667
6668 size(0);
6669 format %{ "MEMBAR-release" %}
6670 ins_encode( enc_membar_release );
6671 ins_pipe(long_memory_op);
6672 %}
6673
6674 instruct membar_release_lock() %{
6675 match(MemBarReleaseLock);
6676 ins_cost(0);
6677
6678 size(0);
6679 format %{ "!MEMBAR-release (CAS in succeeding FastUnlock so empty encoding)" %}
6680 ins_encode( );
6681 ins_pipe(empty);
6682 %}
6683
6684 instruct membar_volatile() %{
6685 match(MemBarVolatile);
6686 ins_cost(4*MEMORY_REF_COST);
6687
6688 size(4);
6689 format %{ "MEMBAR-volatile" %}
6690 ins_encode( enc_membar_volatile );
6691 ins_pipe(long_memory_op);
6692 %}
6693
6694 instruct unnecessary_membar_volatile() %{
6695 match(MemBarVolatile);
6696 predicate(Matcher::post_store_load_barrier(n));
6697 ins_cost(0);
6698
6699 size(0);
6700 format %{ "!MEMBAR-volatile (unnecessary so empty encoding)" %}
6701 ins_encode( );
6702 ins_pipe(empty);
6703 %}
6704
6705 instruct membar_storestore() %{
6706 match(MemBarStoreStore);
6707 ins_cost(0);
6708
6709 size(0);
6710 format %{ "!MEMBAR-storestore (empty encoding)" %}
6711 ins_encode( );
6712 ins_pipe(empty);
6713 %}
6714
6715 //----------Register Move Instructions-----------------------------------------
6716 instruct roundDouble_nop(regD dst) %{
6717 match(Set dst (RoundDouble dst));
6718 ins_cost(0);
6719 // SPARC results are already "rounded" (i.e., normal-format IEEE)
6720 ins_encode( );
6721 ins_pipe(empty);
6722 %}
6723
6724
6725 instruct roundFloat_nop(regF dst) %{
6726 match(Set dst (RoundFloat dst));
6727 ins_cost(0);
6728 // SPARC results are already "rounded" (i.e., normal-format IEEE)
6729 ins_encode( );
6730 ins_pipe(empty);
6731 %}
6732
6733
6734 // Cast Index to Pointer for unsafe natives
6735 instruct castX2P(iRegX src, iRegP dst) %{
6736 match(Set dst (CastX2P src));
6737
6738 format %{ "MOV $src,$dst\t! IntX->Ptr" %}
6739 ins_encode( form3_g0_rs2_rd_move( src, dst ) );
6740 ins_pipe(ialu_reg);
6741 %}
6742
6743 // Cast Pointer to Index for unsafe natives
6744 instruct castP2X(iRegP src, iRegX dst) %{
6745 match(Set dst (CastP2X src));
6746
6747 format %{ "MOV $src,$dst\t! Ptr->IntX" %}
6748 ins_encode( form3_g0_rs2_rd_move( src, dst ) );
6749 ins_pipe(ialu_reg);
6750 %}
6751
6752 instruct stfSSD(stackSlotD stkSlot, regD src) %{
6753 // %%%% TO DO: Tell the coalescer that this kind of node is a copy!
6754 match(Set stkSlot src); // chain rule
6755 ins_cost(MEMORY_REF_COST);
6756 format %{ "STDF $src,$stkSlot\t!stk" %}
6757 opcode(Assembler::stdf_op3);
6758 ins_encode(simple_form3_mem_reg(stkSlot, src));
6759 ins_pipe(fstoreD_stk_reg);
6760 %}
6761
6762 instruct ldfSSD(regD dst, stackSlotD stkSlot) %{
6763 // %%%% TO DO: Tell the coalescer that this kind of node is a copy!
6764 match(Set dst stkSlot); // chain rule
6765 ins_cost(MEMORY_REF_COST);
6766 format %{ "LDDF $stkSlot,$dst\t!stk" %}
6767 opcode(Assembler::lddf_op3);
6768 ins_encode(simple_form3_mem_reg(stkSlot, dst));
6769 ins_pipe(floadD_stk);
6770 %}
6771
6772 instruct stfSSF(stackSlotF stkSlot, regF src) %{
6773 // %%%% TO DO: Tell the coalescer that this kind of node is a copy!
6774 match(Set stkSlot src); // chain rule
6775 ins_cost(MEMORY_REF_COST);
6776 format %{ "STF $src,$stkSlot\t!stk" %}
6777 opcode(Assembler::stf_op3);
6778 ins_encode(simple_form3_mem_reg(stkSlot, src));
6779 ins_pipe(fstoreF_stk_reg);
6780 %}
6781
6782 //----------Conditional Move---------------------------------------------------
6783 // Conditional move
6784 instruct cmovIP_reg(cmpOpP cmp, flagsRegP pcc, iRegI dst, iRegI src) %{
6785 match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src)));
6786 ins_cost(150);
6787 format %{ "MOV$cmp $pcc,$src,$dst" %}
6788 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6789 ins_pipe(ialu_reg);
6790 %}
6791
6792 instruct cmovIP_imm(cmpOpP cmp, flagsRegP pcc, iRegI dst, immI11 src) %{
6793 match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src)));
6794 ins_cost(140);
6795 format %{ "MOV$cmp $pcc,$src,$dst" %}
6796 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) );
6797 ins_pipe(ialu_imm);
6798 %}
6799
6800 instruct cmovII_reg(cmpOp cmp, flagsReg icc, iRegI dst, iRegI src) %{
6801 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6802 ins_cost(150);
6803 size(4);
6804 format %{ "MOV$cmp $icc,$src,$dst" %}
6805 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6806 ins_pipe(ialu_reg);
6807 %}
6808
6809 instruct cmovII_imm(cmpOp cmp, flagsReg icc, iRegI dst, immI11 src) %{
6810 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6811 ins_cost(140);
6812 size(4);
6813 format %{ "MOV$cmp $icc,$src,$dst" %}
6814 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6815 ins_pipe(ialu_imm);
6816 %}
6817
6818 instruct cmovIIu_reg(cmpOpU cmp, flagsRegU icc, iRegI dst, iRegI src) %{
6819 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6820 ins_cost(150);
6821 size(4);
6822 format %{ "MOV$cmp $icc,$src,$dst" %}
6823 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6824 ins_pipe(ialu_reg);
6825 %}
6826
6827 instruct cmovIIu_imm(cmpOpU cmp, flagsRegU icc, iRegI dst, immI11 src) %{
6828 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6829 ins_cost(140);
6830 size(4);
6831 format %{ "MOV$cmp $icc,$src,$dst" %}
6832 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6833 ins_pipe(ialu_imm);
6834 %}
6835
6836 instruct cmovIF_reg(cmpOpF cmp, flagsRegF fcc, iRegI dst, iRegI src) %{
6837 match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src)));
6838 ins_cost(150);
6839 size(4);
6840 format %{ "MOV$cmp $fcc,$src,$dst" %}
6841 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6842 ins_pipe(ialu_reg);
6843 %}
6844
6845 instruct cmovIF_imm(cmpOpF cmp, flagsRegF fcc, iRegI dst, immI11 src) %{
6846 match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src)));
6847 ins_cost(140);
6848 size(4);
6849 format %{ "MOV$cmp $fcc,$src,$dst" %}
6850 ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) );
6851 ins_pipe(ialu_imm);
6852 %}
6853
6854 // Conditional move for RegN. Only cmov(reg,reg).
6855 instruct cmovNP_reg(cmpOpP cmp, flagsRegP pcc, iRegN dst, iRegN src) %{
6856 match(Set dst (CMoveN (Binary cmp pcc) (Binary dst src)));
6857 ins_cost(150);
6858 format %{ "MOV$cmp $pcc,$src,$dst" %}
6859 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6860 ins_pipe(ialu_reg);
6861 %}
6862
6863 // This instruction also works with CmpN so we don't need cmovNN_reg.
6864 instruct cmovNI_reg(cmpOp cmp, flagsReg icc, iRegN dst, iRegN src) %{
6865 match(Set dst (CMoveN (Binary cmp icc) (Binary dst src)));
6866 ins_cost(150);
6867 size(4);
6868 format %{ "MOV$cmp $icc,$src,$dst" %}
6869 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6870 ins_pipe(ialu_reg);
6871 %}
6872
6873 // This instruction also works with CmpN so we don't need cmovNN_reg.
6874 instruct cmovNIu_reg(cmpOpU cmp, flagsRegU icc, iRegN dst, iRegN src) %{
6875 match(Set dst (CMoveN (Binary cmp icc) (Binary dst src)));
6876 ins_cost(150);
6877 size(4);
6878 format %{ "MOV$cmp $icc,$src,$dst" %}
6879 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6880 ins_pipe(ialu_reg);
6881 %}
6882
6883 instruct cmovNF_reg(cmpOpF cmp, flagsRegF fcc, iRegN dst, iRegN src) %{
6884 match(Set dst (CMoveN (Binary cmp fcc) (Binary dst src)));
6885 ins_cost(150);
6886 size(4);
6887 format %{ "MOV$cmp $fcc,$src,$dst" %}
6888 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6889 ins_pipe(ialu_reg);
6890 %}
6891
6892 // Conditional move
6893 instruct cmovPP_reg(cmpOpP cmp, flagsRegP pcc, iRegP dst, iRegP src) %{
6894 match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src)));
6895 ins_cost(150);
6896 format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %}
6897 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6898 ins_pipe(ialu_reg);
6899 %}
6900
6901 instruct cmovPP_imm(cmpOpP cmp, flagsRegP pcc, iRegP dst, immP0 src) %{
6902 match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src)));
6903 ins_cost(140);
6904 format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %}
6905 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) );
6906 ins_pipe(ialu_imm);
6907 %}
6908
6909 // This instruction also works with CmpN so we don't need cmovPN_reg.
6910 instruct cmovPI_reg(cmpOp cmp, flagsReg icc, iRegP dst, iRegP src) %{
6911 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6912 ins_cost(150);
6913
6914 size(4);
6915 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %}
6916 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6917 ins_pipe(ialu_reg);
6918 %}
6919
6920 instruct cmovPIu_reg(cmpOpU cmp, flagsRegU icc, iRegP dst, iRegP src) %{
6921 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6922 ins_cost(150);
6923
6924 size(4);
6925 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %}
6926 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6927 ins_pipe(ialu_reg);
6928 %}
6929
6930 instruct cmovPI_imm(cmpOp cmp, flagsReg icc, iRegP dst, immP0 src) %{
6931 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6932 ins_cost(140);
6933
6934 size(4);
6935 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %}
6936 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6937 ins_pipe(ialu_imm);
6938 %}
6939
6940 instruct cmovPIu_imm(cmpOpU cmp, flagsRegU icc, iRegP dst, immP0 src) %{
6941 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6942 ins_cost(140);
6943
6944 size(4);
6945 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %}
6946 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6947 ins_pipe(ialu_imm);
6948 %}
6949
6950 instruct cmovPF_reg(cmpOpF cmp, flagsRegF fcc, iRegP dst, iRegP src) %{
6951 match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src)));
6952 ins_cost(150);
6953 size(4);
6954 format %{ "MOV$cmp $fcc,$src,$dst" %}
6955 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6956 ins_pipe(ialu_imm);
6957 %}
6958
6959 instruct cmovPF_imm(cmpOpF cmp, flagsRegF fcc, iRegP dst, immP0 src) %{
6960 match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src)));
6961 ins_cost(140);
6962 size(4);
6963 format %{ "MOV$cmp $fcc,$src,$dst" %}
6964 ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) );
6965 ins_pipe(ialu_imm);
6966 %}
6967
6968 // Conditional move
6969 instruct cmovFP_reg(cmpOpP cmp, flagsRegP pcc, regF dst, regF src) %{
6970 match(Set dst (CMoveF (Binary cmp pcc) (Binary dst src)));
6971 ins_cost(150);
6972 opcode(0x101);
6973 format %{ "FMOVD$cmp $pcc,$src,$dst" %}
6974 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6975 ins_pipe(int_conditional_float_move);
6976 %}
6977
6978 instruct cmovFI_reg(cmpOp cmp, flagsReg icc, regF dst, regF src) %{
6979 match(Set dst (CMoveF (Binary cmp icc) (Binary dst src)));
6980 ins_cost(150);
6981
6982 size(4);
6983 format %{ "FMOVS$cmp $icc,$src,$dst" %}
6984 opcode(0x101);
6985 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
6986 ins_pipe(int_conditional_float_move);
6987 %}
6988
6989 instruct cmovFIu_reg(cmpOpU cmp, flagsRegU icc, regF dst, regF src) %{
6990 match(Set dst (CMoveF (Binary cmp icc) (Binary dst src)));
6991 ins_cost(150);
6992
6993 size(4);
6994 format %{ "FMOVS$cmp $icc,$src,$dst" %}
6995 opcode(0x101);
6996 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
6997 ins_pipe(int_conditional_float_move);
6998 %}
6999
7000 // Conditional move,
7001 instruct cmovFF_reg(cmpOpF cmp, flagsRegF fcc, regF dst, regF src) %{
7002 match(Set dst (CMoveF (Binary cmp fcc) (Binary dst src)));
7003 ins_cost(150);
7004 size(4);
7005 format %{ "FMOVF$cmp $fcc,$src,$dst" %}
7006 opcode(0x1);
7007 ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) );
7008 ins_pipe(int_conditional_double_move);
7009 %}
7010
7011 // Conditional move
7012 instruct cmovDP_reg(cmpOpP cmp, flagsRegP pcc, regD dst, regD src) %{
7013 match(Set dst (CMoveD (Binary cmp pcc) (Binary dst src)));
7014 ins_cost(150);
7015 size(4);
7016 opcode(0x102);
7017 format %{ "FMOVD$cmp $pcc,$src,$dst" %}
7018 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) );
7019 ins_pipe(int_conditional_double_move);
7020 %}
7021
7022 instruct cmovDI_reg(cmpOp cmp, flagsReg icc, regD dst, regD src) %{
7023 match(Set dst (CMoveD (Binary cmp icc) (Binary dst src)));
7024 ins_cost(150);
7025
7026 size(4);
7027 format %{ "FMOVD$cmp $icc,$src,$dst" %}
7028 opcode(0x102);
7029 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
7030 ins_pipe(int_conditional_double_move);
7031 %}
7032
7033 instruct cmovDIu_reg(cmpOpU cmp, flagsRegU icc, regD dst, regD src) %{
7034 match(Set dst (CMoveD (Binary cmp icc) (Binary dst src)));
7035 ins_cost(150);
7036
7037 size(4);
7038 format %{ "FMOVD$cmp $icc,$src,$dst" %}
7039 opcode(0x102);
7040 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
7041 ins_pipe(int_conditional_double_move);
7042 %}
7043
7044 // Conditional move,
7045 instruct cmovDF_reg(cmpOpF cmp, flagsRegF fcc, regD dst, regD src) %{
7046 match(Set dst (CMoveD (Binary cmp fcc) (Binary dst src)));
7047 ins_cost(150);
7048 size(4);
7049 format %{ "FMOVD$cmp $fcc,$src,$dst" %}
7050 opcode(0x2);
7051 ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) );
7052 ins_pipe(int_conditional_double_move);
7053 %}
7054
7055 // Conditional move
7056 instruct cmovLP_reg(cmpOpP cmp, flagsRegP pcc, iRegL dst, iRegL src) %{
7057 match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src)));
7058 ins_cost(150);
7059 format %{ "MOV$cmp $pcc,$src,$dst\t! long" %}
7060 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
7061 ins_pipe(ialu_reg);
7062 %}
7063
7064 instruct cmovLP_imm(cmpOpP cmp, flagsRegP pcc, iRegL dst, immI11 src) %{
7065 match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src)));
7066 ins_cost(140);
7067 format %{ "MOV$cmp $pcc,$src,$dst\t! long" %}
7068 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) );
7069 ins_pipe(ialu_imm);
7070 %}
7071
7072 instruct cmovLI_reg(cmpOp cmp, flagsReg icc, iRegL dst, iRegL src) %{
7073 match(Set dst (CMoveL (Binary cmp icc) (Binary dst src)));
7074 ins_cost(150);
7075
7076 size(4);
7077 format %{ "MOV$cmp $icc,$src,$dst\t! long" %}
7078 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
7079 ins_pipe(ialu_reg);
7080 %}
7081
7082
7083 instruct cmovLIu_reg(cmpOpU cmp, flagsRegU icc, iRegL dst, iRegL src) %{
7084 match(Set dst (CMoveL (Binary cmp icc) (Binary dst src)));
7085 ins_cost(150);
7086
7087 size(4);
7088 format %{ "MOV$cmp $icc,$src,$dst\t! long" %}
7089 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
7090 ins_pipe(ialu_reg);
7091 %}
7092
7093
7094 instruct cmovLF_reg(cmpOpF cmp, flagsRegF fcc, iRegL dst, iRegL src) %{
7095 match(Set dst (CMoveL (Binary cmp fcc) (Binary dst src)));
7096 ins_cost(150);
7097
7098 size(4);
7099 format %{ "MOV$cmp $fcc,$src,$dst\t! long" %}
7100 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
7101 ins_pipe(ialu_reg);
7102 %}
7103
7104
7105
7106 //----------OS and Locking Instructions----------------------------------------
7107
7108 // This name is KNOWN by the ADLC and cannot be changed.
7109 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type
7110 // for this guy.
7111 instruct tlsLoadP(g2RegP dst) %{
7112 match(Set dst (ThreadLocal));
7113
7114 size(0);
7115 ins_cost(0);
7116 format %{ "# TLS is in G2" %}
7117 ins_encode( /*empty encoding*/ );
7118 ins_pipe(ialu_none);
7119 %}
7120
7121 instruct checkCastPP( iRegP dst ) %{
7122 match(Set dst (CheckCastPP dst));
7123
7124 size(0);
7125 format %{ "# checkcastPP of $dst" %}
7126 ins_encode( /*empty encoding*/ );
7127 ins_pipe(empty);
7128 %}
7129
7130
7131 instruct castPP( iRegP dst ) %{
7132 match(Set dst (CastPP dst));
7133 format %{ "# castPP of $dst" %}
7134 ins_encode( /*empty encoding*/ );
7135 ins_pipe(empty);
7136 %}
7137
7138 instruct castII( iRegI dst ) %{
7139 match(Set dst (CastII dst));
7140 format %{ "# castII of $dst" %}
7141 ins_encode( /*empty encoding*/ );
7142 ins_cost(0);
7143 ins_pipe(empty);
7144 %}
7145
7146 //----------Arithmetic Instructions--------------------------------------------
7147 // Addition Instructions
7148 // Register Addition
7149 instruct addI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7150 match(Set dst (AddI src1 src2));
7151
7152 size(4);
7153 format %{ "ADD $src1,$src2,$dst" %}
7154 ins_encode %{
7155 __ add($src1$$Register, $src2$$Register, $dst$$Register);
7156 %}
7157 ins_pipe(ialu_reg_reg);
7158 %}
7159
7160 // Immediate Addition
7161 instruct addI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7162 match(Set dst (AddI src1 src2));
7163
7164 size(4);
7165 format %{ "ADD $src1,$src2,$dst" %}
7166 opcode(Assembler::add_op3, Assembler::arith_op);
7167 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7168 ins_pipe(ialu_reg_imm);
7169 %}
7170
7171 // Pointer Register Addition
7172 instruct addP_reg_reg(iRegP dst, iRegP src1, iRegX src2) %{
7173 match(Set dst (AddP src1 src2));
7174
7175 size(4);
7176 format %{ "ADD $src1,$src2,$dst" %}
7177 opcode(Assembler::add_op3, Assembler::arith_op);
7178 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7179 ins_pipe(ialu_reg_reg);
7180 %}
7181
7182 // Pointer Immediate Addition
7183 instruct addP_reg_imm13(iRegP dst, iRegP src1, immX13 src2) %{
7184 match(Set dst (AddP src1 src2));
7185
7186 size(4);
7187 format %{ "ADD $src1,$src2,$dst" %}
7188 opcode(Assembler::add_op3, Assembler::arith_op);
7189 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7190 ins_pipe(ialu_reg_imm);
7191 %}
7192
7193 // Long Addition
7194 instruct addL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7195 match(Set dst (AddL src1 src2));
7196
7197 size(4);
7198 format %{ "ADD $src1,$src2,$dst\t! long" %}
7199 opcode(Assembler::add_op3, Assembler::arith_op);
7200 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7201 ins_pipe(ialu_reg_reg);
7202 %}
7203
7204 instruct addL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
7205 match(Set dst (AddL src1 con));
7206
7207 size(4);
7208 format %{ "ADD $src1,$con,$dst" %}
7209 opcode(Assembler::add_op3, Assembler::arith_op);
7210 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
7211 ins_pipe(ialu_reg_imm);
7212 %}
7213
7214 //----------Conditional_store--------------------------------------------------
7215 // Conditional-store of the updated heap-top.
7216 // Used during allocation of the shared heap.
7217 // Sets flags (EQ) on success. Implemented with a CASA on Sparc.
7218
7219 // LoadP-locked. Same as a regular pointer load when used with a compare-swap
7220 instruct loadPLocked(iRegP dst, memory mem) %{
7221 match(Set dst (LoadPLocked mem));
7222 ins_cost(MEMORY_REF_COST);
7223
7224 #ifndef _LP64
7225 size(4);
7226 format %{ "LDUW $mem,$dst\t! ptr" %}
7227 opcode(Assembler::lduw_op3, 0, REGP_OP);
7228 #else
7229 format %{ "LDX $mem,$dst\t! ptr" %}
7230 opcode(Assembler::ldx_op3, 0, REGP_OP);
7231 #endif
7232 ins_encode( form3_mem_reg( mem, dst ) );
7233 ins_pipe(iload_mem);
7234 %}
7235
7236 instruct storePConditional( iRegP heap_top_ptr, iRegP oldval, g3RegP newval, flagsRegP pcc ) %{
7237 match(Set pcc (StorePConditional heap_top_ptr (Binary oldval newval)));
7238 effect( KILL newval );
7239 format %{ "CASA [$heap_top_ptr],$oldval,R_G3\t! If $oldval==[$heap_top_ptr] Then store R_G3 into [$heap_top_ptr], set R_G3=[$heap_top_ptr] in any case\n\t"
7240 "CMP R_G3,$oldval\t\t! See if we made progress" %}
7241 ins_encode( enc_cas(heap_top_ptr,oldval,newval) );
7242 ins_pipe( long_memory_op );
7243 %}
7244
7245 // Conditional-store of an int value.
7246 instruct storeIConditional( iRegP mem_ptr, iRegI oldval, g3RegI newval, flagsReg icc ) %{
7247 match(Set icc (StoreIConditional mem_ptr (Binary oldval newval)));
7248 effect( KILL newval );
7249 format %{ "CASA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr], set $newval=[$mem_ptr] in any case\n\t"
7250 "CMP $oldval,$newval\t\t! See if we made progress" %}
7251 ins_encode( enc_cas(mem_ptr,oldval,newval) );
7252 ins_pipe( long_memory_op );
7253 %}
7254
7255 // Conditional-store of a long value.
7256 instruct storeLConditional( iRegP mem_ptr, iRegL oldval, g3RegL newval, flagsRegL xcc ) %{
7257 match(Set xcc (StoreLConditional mem_ptr (Binary oldval newval)));
7258 effect( KILL newval );
7259 format %{ "CASXA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr], set $newval=[$mem_ptr] in any case\n\t"
7260 "CMP $oldval,$newval\t\t! See if we made progress" %}
7261 ins_encode( enc_cas(mem_ptr,oldval,newval) );
7262 ins_pipe( long_memory_op );
7263 %}
7264
7265 // No flag versions for CompareAndSwap{P,I,L} because matcher can't match them
7266
7267 instruct compareAndSwapL_bool(iRegP mem_ptr, iRegL oldval, iRegL newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
7268 predicate(VM_Version::supports_cx8());
7269 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval)));
7270 effect( USE mem_ptr, KILL ccr, KILL tmp1);
7271 format %{
7272 "MOV $newval,O7\n\t"
7273 "CASXA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
7274 "CMP $oldval,O7\t\t! See if we made progress\n\t"
7275 "MOV 1,$res\n\t"
7276 "MOVne xcc,R_G0,$res"
7277 %}
7278 ins_encode( enc_casx(mem_ptr, oldval, newval),
7279 enc_lflags_ne_to_boolean(res) );
7280 ins_pipe( long_memory_op );
7281 %}
7282
7283
7284 instruct compareAndSwapI_bool(iRegP mem_ptr, iRegI oldval, iRegI newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
7285 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval)));
7286 effect( USE mem_ptr, KILL ccr, KILL tmp1);
7287 format %{
7288 "MOV $newval,O7\n\t"
7289 "CASA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
7290 "CMP $oldval,O7\t\t! See if we made progress\n\t"
7291 "MOV 1,$res\n\t"
7292 "MOVne icc,R_G0,$res"
7293 %}
7294 ins_encode( enc_casi(mem_ptr, oldval, newval),
7295 enc_iflags_ne_to_boolean(res) );
7296 ins_pipe( long_memory_op );
7297 %}
7298
7299 instruct compareAndSwapP_bool(iRegP mem_ptr, iRegP oldval, iRegP newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
7300 #ifdef _LP64
7301 predicate(VM_Version::supports_cx8());
7302 #endif
7303 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval)));
7304 effect( USE mem_ptr, KILL ccr, KILL tmp1);
7305 format %{
7306 "MOV $newval,O7\n\t"
7307 "CASA_PTR [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
7308 "CMP $oldval,O7\t\t! See if we made progress\n\t"
7309 "MOV 1,$res\n\t"
7310 "MOVne xcc,R_G0,$res"
7311 %}
7312 #ifdef _LP64
7313 ins_encode( enc_casx(mem_ptr, oldval, newval),
7314 enc_lflags_ne_to_boolean(res) );
7315 #else
7316 ins_encode( enc_casi(mem_ptr, oldval, newval),
7317 enc_iflags_ne_to_boolean(res) );
7318 #endif
7319 ins_pipe( long_memory_op );
7320 %}
7321
7322 instruct compareAndSwapN_bool(iRegP mem_ptr, iRegN oldval, iRegN newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
7323 match(Set res (CompareAndSwapN mem_ptr (Binary oldval newval)));
7324 effect( USE mem_ptr, KILL ccr, KILL tmp1);
7325 format %{
7326 "MOV $newval,O7\n\t"
7327 "CASA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
7328 "CMP $oldval,O7\t\t! See if we made progress\n\t"
7329 "MOV 1,$res\n\t"
7330 "MOVne icc,R_G0,$res"
7331 %}
7332 ins_encode( enc_casi(mem_ptr, oldval, newval),
7333 enc_iflags_ne_to_boolean(res) );
7334 ins_pipe( long_memory_op );
7335 %}
7336
7337 instruct xchgI( memory mem, iRegI newval) %{
7338 match(Set newval (GetAndSetI mem newval));
7339 format %{ "SWAP [$mem],$newval" %}
7340 size(4);
7341 ins_encode %{
7342 __ swap($mem$$Address, $newval$$Register);
7343 %}
7344 ins_pipe( long_memory_op );
7345 %}
7346
7347 #ifndef _LP64
7348 instruct xchgP( memory mem, iRegP newval) %{
7349 match(Set newval (GetAndSetP mem newval));
7350 format %{ "SWAP [$mem],$newval" %}
7351 size(4);
7352 ins_encode %{
7353 __ swap($mem$$Address, $newval$$Register);
7354 %}
7355 ins_pipe( long_memory_op );
7356 %}
7357 #endif
7358
7359 instruct xchgN( memory mem, iRegN newval) %{
7360 match(Set newval (GetAndSetN mem newval));
7361 format %{ "SWAP [$mem],$newval" %}
7362 size(4);
7363 ins_encode %{
7364 __ swap($mem$$Address, $newval$$Register);
7365 %}
7366 ins_pipe( long_memory_op );
7367 %}
7368
7369 //---------------------
7370 // Subtraction Instructions
7371 // Register Subtraction
7372 instruct subI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7373 match(Set dst (SubI src1 src2));
7374
7375 size(4);
7376 format %{ "SUB $src1,$src2,$dst" %}
7377 opcode(Assembler::sub_op3, Assembler::arith_op);
7378 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7379 ins_pipe(ialu_reg_reg);
7380 %}
7381
7382 // Immediate Subtraction
7383 instruct subI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7384 match(Set dst (SubI src1 src2));
7385
7386 size(4);
7387 format %{ "SUB $src1,$src2,$dst" %}
7388 opcode(Assembler::sub_op3, Assembler::arith_op);
7389 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7390 ins_pipe(ialu_reg_imm);
7391 %}
7392
7393 instruct subI_zero_reg(iRegI dst, immI0 zero, iRegI src2) %{
7394 match(Set dst (SubI zero src2));
7395
7396 size(4);
7397 format %{ "NEG $src2,$dst" %}
7398 opcode(Assembler::sub_op3, Assembler::arith_op);
7399 ins_encode( form3_rs1_rs2_rd( R_G0, src2, dst ) );
7400 ins_pipe(ialu_zero_reg);
7401 %}
7402
7403 // Long subtraction
7404 instruct subL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7405 match(Set dst (SubL src1 src2));
7406
7407 size(4);
7408 format %{ "SUB $src1,$src2,$dst\t! long" %}
7409 opcode(Assembler::sub_op3, Assembler::arith_op);
7410 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7411 ins_pipe(ialu_reg_reg);
7412 %}
7413
7414 // Immediate Subtraction
7415 instruct subL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
7416 match(Set dst (SubL src1 con));
7417
7418 size(4);
7419 format %{ "SUB $src1,$con,$dst\t! long" %}
7420 opcode(Assembler::sub_op3, Assembler::arith_op);
7421 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
7422 ins_pipe(ialu_reg_imm);
7423 %}
7424
7425 // Long negation
7426 instruct negL_reg_reg(iRegL dst, immL0 zero, iRegL src2) %{
7427 match(Set dst (SubL zero src2));
7428
7429 size(4);
7430 format %{ "NEG $src2,$dst\t! long" %}
7431 opcode(Assembler::sub_op3, Assembler::arith_op);
7432 ins_encode( form3_rs1_rs2_rd( R_G0, src2, dst ) );
7433 ins_pipe(ialu_zero_reg);
7434 %}
7435
7436 // Multiplication Instructions
7437 // Integer Multiplication
7438 // Register Multiplication
7439 instruct mulI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7440 match(Set dst (MulI src1 src2));
7441
7442 size(4);
7443 format %{ "MULX $src1,$src2,$dst" %}
7444 opcode(Assembler::mulx_op3, Assembler::arith_op);
7445 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7446 ins_pipe(imul_reg_reg);
7447 %}
7448
7449 // Immediate Multiplication
7450 instruct mulI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7451 match(Set dst (MulI src1 src2));
7452
7453 size(4);
7454 format %{ "MULX $src1,$src2,$dst" %}
7455 opcode(Assembler::mulx_op3, Assembler::arith_op);
7456 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7457 ins_pipe(imul_reg_imm);
7458 %}
7459
7460 instruct mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7461 match(Set dst (MulL src1 src2));
7462 ins_cost(DEFAULT_COST * 5);
7463 size(4);
7464 format %{ "MULX $src1,$src2,$dst\t! long" %}
7465 opcode(Assembler::mulx_op3, Assembler::arith_op);
7466 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7467 ins_pipe(mulL_reg_reg);
7468 %}
7469
7470 // Immediate Multiplication
7471 instruct mulL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{
7472 match(Set dst (MulL src1 src2));
7473 ins_cost(DEFAULT_COST * 5);
7474 size(4);
7475 format %{ "MULX $src1,$src2,$dst" %}
7476 opcode(Assembler::mulx_op3, Assembler::arith_op);
7477 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7478 ins_pipe(mulL_reg_imm);
7479 %}
7480
7481 // Integer Division
7482 // Register Division
7483 instruct divI_reg_reg(iRegI dst, iRegIsafe src1, iRegIsafe src2) %{
7484 match(Set dst (DivI src1 src2));
7485 ins_cost((2+71)*DEFAULT_COST);
7486
7487 format %{ "SRA $src2,0,$src2\n\t"
7488 "SRA $src1,0,$src1\n\t"
7489 "SDIVX $src1,$src2,$dst" %}
7490 ins_encode( idiv_reg( src1, src2, dst ) );
7491 ins_pipe(sdiv_reg_reg);
7492 %}
7493
7494 // Immediate Division
7495 instruct divI_reg_imm13(iRegI dst, iRegIsafe src1, immI13 src2) %{
7496 match(Set dst (DivI src1 src2));
7497 ins_cost((2+71)*DEFAULT_COST);
7498
7499 format %{ "SRA $src1,0,$src1\n\t"
7500 "SDIVX $src1,$src2,$dst" %}
7501 ins_encode( idiv_imm( src1, src2, dst ) );
7502 ins_pipe(sdiv_reg_imm);
7503 %}
7504
7505 //----------Div-By-10-Expansion------------------------------------------------
7506 // Extract hi bits of a 32x32->64 bit multiply.
7507 // Expand rule only, not matched
7508 instruct mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2 ) %{
7509 effect( DEF dst, USE src1, USE src2 );
7510 format %{ "MULX $src1,$src2,$dst\t! Used in div-by-10\n\t"
7511 "SRLX $dst,#32,$dst\t\t! Extract only hi word of result" %}
7512 ins_encode( enc_mul_hi(dst,src1,src2));
7513 ins_pipe(sdiv_reg_reg);
7514 %}
7515
7516 // Magic constant, reciprocal of 10
7517 instruct loadConI_x66666667(iRegIsafe dst) %{
7518 effect( DEF dst );
7519
7520 size(8);
7521 format %{ "SET 0x66666667,$dst\t! Used in div-by-10" %}
7522 ins_encode( Set32(0x66666667, dst) );
7523 ins_pipe(ialu_hi_lo_reg);
7524 %}
7525
7526 // Register Shift Right Arithmetic Long by 32-63
7527 instruct sra_31( iRegI dst, iRegI src ) %{
7528 effect( DEF dst, USE src );
7529 format %{ "SRA $src,31,$dst\t! Used in div-by-10" %}
7530 ins_encode( form3_rs1_rd_copysign_hi(src,dst) );
7531 ins_pipe(ialu_reg_reg);
7532 %}
7533
7534 // Arithmetic Shift Right by 8-bit immediate
7535 instruct sra_reg_2( iRegI dst, iRegI src ) %{
7536 effect( DEF dst, USE src );
7537 format %{ "SRA $src,2,$dst\t! Used in div-by-10" %}
7538 opcode(Assembler::sra_op3, Assembler::arith_op);
7539 ins_encode( form3_rs1_simm13_rd( src, 0x2, dst ) );
7540 ins_pipe(ialu_reg_imm);
7541 %}
7542
7543 // Integer DIV with 10
7544 instruct divI_10( iRegI dst, iRegIsafe src, immI10 div ) %{
7545 match(Set dst (DivI src div));
7546 ins_cost((6+6)*DEFAULT_COST);
7547 expand %{
7548 iRegIsafe tmp1; // Killed temps;
7549 iRegIsafe tmp2; // Killed temps;
7550 iRegI tmp3; // Killed temps;
7551 iRegI tmp4; // Killed temps;
7552 loadConI_x66666667( tmp1 ); // SET 0x66666667 -> tmp1
7553 mul_hi( tmp2, src, tmp1 ); // MUL hibits(src * tmp1) -> tmp2
7554 sra_31( tmp3, src ); // SRA src,31 -> tmp3
7555 sra_reg_2( tmp4, tmp2 ); // SRA tmp2,2 -> tmp4
7556 subI_reg_reg( dst,tmp4,tmp3); // SUB tmp4 - tmp3 -> dst
7557 %}
7558 %}
7559
7560 // Register Long Division
7561 instruct divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7562 match(Set dst (DivL src1 src2));
7563 ins_cost(DEFAULT_COST*71);
7564 size(4);
7565 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
7566 opcode(Assembler::sdivx_op3, Assembler::arith_op);
7567 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7568 ins_pipe(divL_reg_reg);
7569 %}
7570
7571 // Register Long Division
7572 instruct divL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{
7573 match(Set dst (DivL src1 src2));
7574 ins_cost(DEFAULT_COST*71);
7575 size(4);
7576 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
7577 opcode(Assembler::sdivx_op3, Assembler::arith_op);
7578 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7579 ins_pipe(divL_reg_imm);
7580 %}
7581
7582 // Integer Remainder
7583 // Register Remainder
7584 instruct modI_reg_reg(iRegI dst, iRegIsafe src1, iRegIsafe src2, o7RegP temp, flagsReg ccr ) %{
7585 match(Set dst (ModI src1 src2));
7586 effect( KILL ccr, KILL temp);
7587
7588 format %{ "SREM $src1,$src2,$dst" %}
7589 ins_encode( irem_reg(src1, src2, dst, temp) );
7590 ins_pipe(sdiv_reg_reg);
7591 %}
7592
7593 // Immediate Remainder
7594 instruct modI_reg_imm13(iRegI dst, iRegIsafe src1, immI13 src2, o7RegP temp, flagsReg ccr ) %{
7595 match(Set dst (ModI src1 src2));
7596 effect( KILL ccr, KILL temp);
7597
7598 format %{ "SREM $src1,$src2,$dst" %}
7599 ins_encode( irem_imm(src1, src2, dst, temp) );
7600 ins_pipe(sdiv_reg_imm);
7601 %}
7602
7603 // Register Long Remainder
7604 instruct divL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{
7605 effect(DEF dst, USE src1, USE src2);
7606 size(4);
7607 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
7608 opcode(Assembler::sdivx_op3, Assembler::arith_op);
7609 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7610 ins_pipe(divL_reg_reg);
7611 %}
7612
7613 // Register Long Division
7614 instruct divL_reg_imm13_1(iRegL dst, iRegL src1, immL13 src2) %{
7615 effect(DEF dst, USE src1, USE src2);
7616 size(4);
7617 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
7618 opcode(Assembler::sdivx_op3, Assembler::arith_op);
7619 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7620 ins_pipe(divL_reg_imm);
7621 %}
7622
7623 instruct mulL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{
7624 effect(DEF dst, USE src1, USE src2);
7625 size(4);
7626 format %{ "MULX $src1,$src2,$dst\t! long" %}
7627 opcode(Assembler::mulx_op3, Assembler::arith_op);
7628 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7629 ins_pipe(mulL_reg_reg);
7630 %}
7631
7632 // Immediate Multiplication
7633 instruct mulL_reg_imm13_1(iRegL dst, iRegL src1, immL13 src2) %{
7634 effect(DEF dst, USE src1, USE src2);
7635 size(4);
7636 format %{ "MULX $src1,$src2,$dst" %}
7637 opcode(Assembler::mulx_op3, Assembler::arith_op);
7638 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7639 ins_pipe(mulL_reg_imm);
7640 %}
7641
7642 instruct subL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{
7643 effect(DEF dst, USE src1, USE src2);
7644 size(4);
7645 format %{ "SUB $src1,$src2,$dst\t! long" %}
7646 opcode(Assembler::sub_op3, Assembler::arith_op);
7647 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7648 ins_pipe(ialu_reg_reg);
7649 %}
7650
7651 instruct subL_reg_reg_2(iRegL dst, iRegL src1, iRegL src2) %{
7652 effect(DEF dst, USE src1, USE src2);
7653 size(4);
7654 format %{ "SUB $src1,$src2,$dst\t! long" %}
7655 opcode(Assembler::sub_op3, Assembler::arith_op);
7656 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7657 ins_pipe(ialu_reg_reg);
7658 %}
7659
7660 // Register Long Remainder
7661 instruct modL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7662 match(Set dst (ModL src1 src2));
7663 ins_cost(DEFAULT_COST*(71 + 6 + 1));
7664 expand %{
7665 iRegL tmp1;
7666 iRegL tmp2;
7667 divL_reg_reg_1(tmp1, src1, src2);
7668 mulL_reg_reg_1(tmp2, tmp1, src2);
7669 subL_reg_reg_1(dst, src1, tmp2);
7670 %}
7671 %}
7672
7673 // Register Long Remainder
7674 instruct modL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{
7675 match(Set dst (ModL src1 src2));
7676 ins_cost(DEFAULT_COST*(71 + 6 + 1));
7677 expand %{
7678 iRegL tmp1;
7679 iRegL tmp2;
7680 divL_reg_imm13_1(tmp1, src1, src2);
7681 mulL_reg_imm13_1(tmp2, tmp1, src2);
7682 subL_reg_reg_2 (dst, src1, tmp2);
7683 %}
7684 %}
7685
7686 // Integer Shift Instructions
7687 // Register Shift Left
7688 instruct shlI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7689 match(Set dst (LShiftI src1 src2));
7690
7691 size(4);
7692 format %{ "SLL $src1,$src2,$dst" %}
7693 opcode(Assembler::sll_op3, Assembler::arith_op);
7694 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7695 ins_pipe(ialu_reg_reg);
7696 %}
7697
7698 // Register Shift Left Immediate
7699 instruct shlI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{
7700 match(Set dst (LShiftI src1 src2));
7701
7702 size(4);
7703 format %{ "SLL $src1,$src2,$dst" %}
7704 opcode(Assembler::sll_op3, Assembler::arith_op);
7705 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7706 ins_pipe(ialu_reg_imm);
7707 %}
7708
7709 // Register Shift Left
7710 instruct shlL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
7711 match(Set dst (LShiftL src1 src2));
7712
7713 size(4);
7714 format %{ "SLLX $src1,$src2,$dst" %}
7715 opcode(Assembler::sllx_op3, Assembler::arith_op);
7716 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) );
7717 ins_pipe(ialu_reg_reg);
7718 %}
7719
7720 // Register Shift Left Immediate
7721 instruct shlL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{
7722 match(Set dst (LShiftL src1 src2));
7723
7724 size(4);
7725 format %{ "SLLX $src1,$src2,$dst" %}
7726 opcode(Assembler::sllx_op3, Assembler::arith_op);
7727 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7728 ins_pipe(ialu_reg_imm);
7729 %}
7730
7731 // Register Arithmetic Shift Right
7732 instruct sarI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7733 match(Set dst (RShiftI src1 src2));
7734 size(4);
7735 format %{ "SRA $src1,$src2,$dst" %}
7736 opcode(Assembler::sra_op3, Assembler::arith_op);
7737 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7738 ins_pipe(ialu_reg_reg);
7739 %}
7740
7741 // Register Arithmetic Shift Right Immediate
7742 instruct sarI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{
7743 match(Set dst (RShiftI src1 src2));
7744
7745 size(4);
7746 format %{ "SRA $src1,$src2,$dst" %}
7747 opcode(Assembler::sra_op3, Assembler::arith_op);
7748 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7749 ins_pipe(ialu_reg_imm);
7750 %}
7751
7752 // Register Shift Right Arithmatic Long
7753 instruct sarL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
7754 match(Set dst (RShiftL src1 src2));
7755
7756 size(4);
7757 format %{ "SRAX $src1,$src2,$dst" %}
7758 opcode(Assembler::srax_op3, Assembler::arith_op);
7759 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) );
7760 ins_pipe(ialu_reg_reg);
7761 %}
7762
7763 // Register Shift Left Immediate
7764 instruct sarL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{
7765 match(Set dst (RShiftL src1 src2));
7766
7767 size(4);
7768 format %{ "SRAX $src1,$src2,$dst" %}
7769 opcode(Assembler::srax_op3, Assembler::arith_op);
7770 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7771 ins_pipe(ialu_reg_imm);
7772 %}
7773
7774 // Register Shift Right
7775 instruct shrI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7776 match(Set dst (URShiftI src1 src2));
7777
7778 size(4);
7779 format %{ "SRL $src1,$src2,$dst" %}
7780 opcode(Assembler::srl_op3, Assembler::arith_op);
7781 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7782 ins_pipe(ialu_reg_reg);
7783 %}
7784
7785 // Register Shift Right Immediate
7786 instruct shrI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{
7787 match(Set dst (URShiftI src1 src2));
7788
7789 size(4);
7790 format %{ "SRL $src1,$src2,$dst" %}
7791 opcode(Assembler::srl_op3, Assembler::arith_op);
7792 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7793 ins_pipe(ialu_reg_imm);
7794 %}
7795
7796 // Register Shift Right
7797 instruct shrL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
7798 match(Set dst (URShiftL src1 src2));
7799
7800 size(4);
7801 format %{ "SRLX $src1,$src2,$dst" %}
7802 opcode(Assembler::srlx_op3, Assembler::arith_op);
7803 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) );
7804 ins_pipe(ialu_reg_reg);
7805 %}
7806
7807 // Register Shift Right Immediate
7808 instruct shrL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{
7809 match(Set dst (URShiftL src1 src2));
7810
7811 size(4);
7812 format %{ "SRLX $src1,$src2,$dst" %}
7813 opcode(Assembler::srlx_op3, Assembler::arith_op);
7814 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7815 ins_pipe(ialu_reg_imm);
7816 %}
7817
7818 // Register Shift Right Immediate with a CastP2X
7819 #ifdef _LP64
7820 instruct shrP_reg_imm6(iRegL dst, iRegP src1, immU6 src2) %{
7821 match(Set dst (URShiftL (CastP2X src1) src2));
7822 size(4);
7823 format %{ "SRLX $src1,$src2,$dst\t! Cast ptr $src1 to long and shift" %}
7824 opcode(Assembler::srlx_op3, Assembler::arith_op);
7825 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7826 ins_pipe(ialu_reg_imm);
7827 %}
7828 #else
7829 instruct shrP_reg_imm5(iRegI dst, iRegP src1, immU5 src2) %{
7830 match(Set dst (URShiftI (CastP2X src1) src2));
7831 size(4);
7832 format %{ "SRL $src1,$src2,$dst\t! Cast ptr $src1 to int and shift" %}
7833 opcode(Assembler::srl_op3, Assembler::arith_op);
7834 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7835 ins_pipe(ialu_reg_imm);
7836 %}
7837 #endif
7838
7839
7840 //----------Floating Point Arithmetic Instructions-----------------------------
7841
7842 // Add float single precision
7843 instruct addF_reg_reg(regF dst, regF src1, regF src2) %{
7844 match(Set dst (AddF src1 src2));
7845
7846 size(4);
7847 format %{ "FADDS $src1,$src2,$dst" %}
7848 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fadds_opf);
7849 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7850 ins_pipe(faddF_reg_reg);
7851 %}
7852
7853 // Add float double precision
7854 instruct addD_reg_reg(regD dst, regD src1, regD src2) %{
7855 match(Set dst (AddD src1 src2));
7856
7857 size(4);
7858 format %{ "FADDD $src1,$src2,$dst" %}
7859 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::faddd_opf);
7860 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7861 ins_pipe(faddD_reg_reg);
7862 %}
7863
7864 // Sub float single precision
7865 instruct subF_reg_reg(regF dst, regF src1, regF src2) %{
7866 match(Set dst (SubF src1 src2));
7867
7868 size(4);
7869 format %{ "FSUBS $src1,$src2,$dst" %}
7870 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubs_opf);
7871 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7872 ins_pipe(faddF_reg_reg);
7873 %}
7874
7875 // Sub float double precision
7876 instruct subD_reg_reg(regD dst, regD src1, regD src2) %{
7877 match(Set dst (SubD src1 src2));
7878
7879 size(4);
7880 format %{ "FSUBD $src1,$src2,$dst" %}
7881 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubd_opf);
7882 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7883 ins_pipe(faddD_reg_reg);
7884 %}
7885
7886 // Mul float single precision
7887 instruct mulF_reg_reg(regF dst, regF src1, regF src2) %{
7888 match(Set dst (MulF src1 src2));
7889
7890 size(4);
7891 format %{ "FMULS $src1,$src2,$dst" %}
7892 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuls_opf);
7893 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7894 ins_pipe(fmulF_reg_reg);
7895 %}
7896
7897 // Mul float double precision
7898 instruct mulD_reg_reg(regD dst, regD src1, regD src2) %{
7899 match(Set dst (MulD src1 src2));
7900
7901 size(4);
7902 format %{ "FMULD $src1,$src2,$dst" %}
7903 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuld_opf);
7904 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7905 ins_pipe(fmulD_reg_reg);
7906 %}
7907
7908 // Div float single precision
7909 instruct divF_reg_reg(regF dst, regF src1, regF src2) %{
7910 match(Set dst (DivF src1 src2));
7911
7912 size(4);
7913 format %{ "FDIVS $src1,$src2,$dst" %}
7914 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdivs_opf);
7915 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7916 ins_pipe(fdivF_reg_reg);
7917 %}
7918
7919 // Div float double precision
7920 instruct divD_reg_reg(regD dst, regD src1, regD src2) %{
7921 match(Set dst (DivD src1 src2));
7922
7923 size(4);
7924 format %{ "FDIVD $src1,$src2,$dst" %}
7925 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdivd_opf);
7926 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7927 ins_pipe(fdivD_reg_reg);
7928 %}
7929
7930 // Absolute float double precision
7931 instruct absD_reg(regD dst, regD src) %{
7932 match(Set dst (AbsD src));
7933
7934 format %{ "FABSd $src,$dst" %}
7935 ins_encode(fabsd(dst, src));
7936 ins_pipe(faddD_reg);
7937 %}
7938
7939 // Absolute float single precision
7940 instruct absF_reg(regF dst, regF src) %{
7941 match(Set dst (AbsF src));
7942
7943 format %{ "FABSs $src,$dst" %}
7944 ins_encode(fabss(dst, src));
7945 ins_pipe(faddF_reg);
7946 %}
7947
7948 instruct negF_reg(regF dst, regF src) %{
7949 match(Set dst (NegF src));
7950
7951 size(4);
7952 format %{ "FNEGs $src,$dst" %}
7953 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fnegs_opf);
7954 ins_encode(form3_opf_rs2F_rdF(src, dst));
7955 ins_pipe(faddF_reg);
7956 %}
7957
7958 instruct negD_reg(regD dst, regD src) %{
7959 match(Set dst (NegD src));
7960
7961 format %{ "FNEGd $src,$dst" %}
7962 ins_encode(fnegd(dst, src));
7963 ins_pipe(faddD_reg);
7964 %}
7965
7966 // Sqrt float double precision
7967 instruct sqrtF_reg_reg(regF dst, regF src) %{
7968 match(Set dst (ConvD2F (SqrtD (ConvF2D src))));
7969
7970 size(4);
7971 format %{ "FSQRTS $src,$dst" %}
7972 ins_encode(fsqrts(dst, src));
7973 ins_pipe(fdivF_reg_reg);
7974 %}
7975
7976 // Sqrt float double precision
7977 instruct sqrtD_reg_reg(regD dst, regD src) %{
7978 match(Set dst (SqrtD src));
7979
7980 size(4);
7981 format %{ "FSQRTD $src,$dst" %}
7982 ins_encode(fsqrtd(dst, src));
7983 ins_pipe(fdivD_reg_reg);
7984 %}
7985
7986 //----------Logical Instructions-----------------------------------------------
7987 // And Instructions
7988 // Register And
7989 instruct andI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7990 match(Set dst (AndI src1 src2));
7991
7992 size(4);
7993 format %{ "AND $src1,$src2,$dst" %}
7994 opcode(Assembler::and_op3, Assembler::arith_op);
7995 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7996 ins_pipe(ialu_reg_reg);
7997 %}
7998
7999 // Immediate And
8000 instruct andI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
8001 match(Set dst (AndI src1 src2));
8002
8003 size(4);
8004 format %{ "AND $src1,$src2,$dst" %}
8005 opcode(Assembler::and_op3, Assembler::arith_op);
8006 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
8007 ins_pipe(ialu_reg_imm);
8008 %}
8009
8010 // Register And Long
8011 instruct andL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
8012 match(Set dst (AndL src1 src2));
8013
8014 ins_cost(DEFAULT_COST);
8015 size(4);
8016 format %{ "AND $src1,$src2,$dst\t! long" %}
8017 opcode(Assembler::and_op3, Assembler::arith_op);
8018 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
8019 ins_pipe(ialu_reg_reg);
8020 %}
8021
8022 instruct andL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
8023 match(Set dst (AndL src1 con));
8024
8025 ins_cost(DEFAULT_COST);
8026 size(4);
8027 format %{ "AND $src1,$con,$dst\t! long" %}
8028 opcode(Assembler::and_op3, Assembler::arith_op);
8029 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
8030 ins_pipe(ialu_reg_imm);
8031 %}
8032
8033 // Or Instructions
8034 // Register Or
8035 instruct orI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
8036 match(Set dst (OrI src1 src2));
8037
8038 size(4);
8039 format %{ "OR $src1,$src2,$dst" %}
8040 opcode(Assembler::or_op3, Assembler::arith_op);
8041 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
8042 ins_pipe(ialu_reg_reg);
8043 %}
8044
8045 // Immediate Or
8046 instruct orI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
8047 match(Set dst (OrI src1 src2));
8048
8049 size(4);
8050 format %{ "OR $src1,$src2,$dst" %}
8051 opcode(Assembler::or_op3, Assembler::arith_op);
8052 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
8053 ins_pipe(ialu_reg_imm);
8054 %}
8055
8056 // Register Or Long
8057 instruct orL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
8058 match(Set dst (OrL src1 src2));
8059
8060 ins_cost(DEFAULT_COST);
8061 size(4);
8062 format %{ "OR $src1,$src2,$dst\t! long" %}
8063 opcode(Assembler::or_op3, Assembler::arith_op);
8064 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
8065 ins_pipe(ialu_reg_reg);
8066 %}
8067
8068 instruct orL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
8069 match(Set dst (OrL src1 con));
8070 ins_cost(DEFAULT_COST*2);
8071
8072 ins_cost(DEFAULT_COST);
8073 size(4);
8074 format %{ "OR $src1,$con,$dst\t! long" %}
8075 opcode(Assembler::or_op3, Assembler::arith_op);
8076 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
8077 ins_pipe(ialu_reg_imm);
8078 %}
8079
8080 #ifndef _LP64
8081
8082 // Use sp_ptr_RegP to match G2 (TLS register) without spilling.
8083 instruct orI_reg_castP2X(iRegI dst, iRegI src1, sp_ptr_RegP src2) %{
8084 match(Set dst (OrI src1 (CastP2X src2)));
8085
8086 size(4);
8087 format %{ "OR $src1,$src2,$dst" %}
8088 opcode(Assembler::or_op3, Assembler::arith_op);
8089 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
8090 ins_pipe(ialu_reg_reg);
8091 %}
8092
8093 #else
8094
8095 instruct orL_reg_castP2X(iRegL dst, iRegL src1, sp_ptr_RegP src2) %{
8096 match(Set dst (OrL src1 (CastP2X src2)));
8097
8098 ins_cost(DEFAULT_COST);
8099 size(4);
8100 format %{ "OR $src1,$src2,$dst\t! long" %}
8101 opcode(Assembler::or_op3, Assembler::arith_op);
8102 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
8103 ins_pipe(ialu_reg_reg);
8104 %}
8105
8106 #endif
8107
8108 // Xor Instructions
8109 // Register Xor
8110 instruct xorI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
8111 match(Set dst (XorI src1 src2));
8112
8113 size(4);
8114 format %{ "XOR $src1,$src2,$dst" %}
8115 opcode(Assembler::xor_op3, Assembler::arith_op);
8116 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
8117 ins_pipe(ialu_reg_reg);
8118 %}
8119
8120 // Immediate Xor
8121 instruct xorI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
8122 match(Set dst (XorI src1 src2));
8123
8124 size(4);
8125 format %{ "XOR $src1,$src2,$dst" %}
8126 opcode(Assembler::xor_op3, Assembler::arith_op);
8127 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
8128 ins_pipe(ialu_reg_imm);
8129 %}
8130
8131 // Register Xor Long
8132 instruct xorL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
8133 match(Set dst (XorL src1 src2));
8134
8135 ins_cost(DEFAULT_COST);
8136 size(4);
8137 format %{ "XOR $src1,$src2,$dst\t! long" %}
8138 opcode(Assembler::xor_op3, Assembler::arith_op);
8139 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
8140 ins_pipe(ialu_reg_reg);
8141 %}
8142
8143 instruct xorL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
8144 match(Set dst (XorL src1 con));
8145
8146 ins_cost(DEFAULT_COST);
8147 size(4);
8148 format %{ "XOR $src1,$con,$dst\t! long" %}
8149 opcode(Assembler::xor_op3, Assembler::arith_op);
8150 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
8151 ins_pipe(ialu_reg_imm);
8152 %}
8153
8154 //----------Convert to Boolean-------------------------------------------------
8155 // Nice hack for 32-bit tests but doesn't work for
8156 // 64-bit pointers.
8157 instruct convI2B( iRegI dst, iRegI src, flagsReg ccr ) %{
8158 match(Set dst (Conv2B src));
8159 effect( KILL ccr );
8160 ins_cost(DEFAULT_COST*2);
8161 format %{ "CMP R_G0,$src\n\t"
8162 "ADDX R_G0,0,$dst" %}
8163 ins_encode( enc_to_bool( src, dst ) );
8164 ins_pipe(ialu_reg_ialu);
8165 %}
8166
8167 #ifndef _LP64
8168 instruct convP2B( iRegI dst, iRegP src, flagsReg ccr ) %{
8169 match(Set dst (Conv2B src));
8170 effect( KILL ccr );
8171 ins_cost(DEFAULT_COST*2);
8172 format %{ "CMP R_G0,$src\n\t"
8173 "ADDX R_G0,0,$dst" %}
8174 ins_encode( enc_to_bool( src, dst ) );
8175 ins_pipe(ialu_reg_ialu);
8176 %}
8177 #else
8178 instruct convP2B( iRegI dst, iRegP src ) %{
8179 match(Set dst (Conv2B src));
8180 ins_cost(DEFAULT_COST*2);
8181 format %{ "MOV $src,$dst\n\t"
8182 "MOVRNZ $src,1,$dst" %}
8183 ins_encode( form3_g0_rs2_rd_move( src, dst ), enc_convP2B( dst, src ) );
8184 ins_pipe(ialu_clr_and_mover);
8185 %}
8186 #endif
8187
8188 instruct cmpLTMask0( iRegI dst, iRegI src, immI0 zero, flagsReg ccr ) %{
8189 match(Set dst (CmpLTMask src zero));
8190 effect(KILL ccr);
8191 size(4);
8192 format %{ "SRA $src,#31,$dst\t# cmpLTMask0" %}
8193 ins_encode %{
8194 __ sra($src$$Register, 31, $dst$$Register);
8195 %}
8196 ins_pipe(ialu_reg_imm);
8197 %}
8198
8199 instruct cmpLTMask_reg_reg( iRegI dst, iRegI p, iRegI q, flagsReg ccr ) %{
8200 match(Set dst (CmpLTMask p q));
8201 effect( KILL ccr );
8202 ins_cost(DEFAULT_COST*4);
8203 format %{ "CMP $p,$q\n\t"
8204 "MOV #0,$dst\n\t"
8205 "BLT,a .+8\n\t"
8206 "MOV #-1,$dst" %}
8207 ins_encode( enc_ltmask(p,q,dst) );
8208 ins_pipe(ialu_reg_reg_ialu);
8209 %}
8210
8211 instruct cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp, flagsReg ccr ) %{
8212 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)));
8213 effect(KILL ccr, TEMP tmp);
8214 ins_cost(DEFAULT_COST*3);
8215
8216 format %{ "SUBcc $p,$q,$p\t! p' = p-q\n\t"
8217 "ADD $p,$y,$tmp\t! g3=p-q+y\n\t"
8218 "MOVlt $tmp,$p\t! p' < 0 ? p'+y : p'" %}
8219 ins_encode(enc_cadd_cmpLTMask(p, q, y, tmp));
8220 ins_pipe(cadd_cmpltmask);
8221 %}
8222
8223 instruct and_cmpLTMask(iRegI p, iRegI q, iRegI y, flagsReg ccr) %{
8224 match(Set p (AndI (CmpLTMask p q) y));
8225 effect(KILL ccr);
8226 ins_cost(DEFAULT_COST*3);
8227
8228 format %{ "CMP $p,$q\n\t"
8229 "MOV $y,$p\n\t"
8230 "MOVge G0,$p" %}
8231 ins_encode %{
8232 __ cmp($p$$Register, $q$$Register);
8233 __ mov($y$$Register, $p$$Register);
8234 __ movcc(Assembler::greaterEqual, false, Assembler::icc, G0, $p$$Register);
8235 %}
8236 ins_pipe(ialu_reg_reg_ialu);
8237 %}
8238
8239 //-----------------------------------------------------------------
8240 // Direct raw moves between float and general registers using VIS3.
8241
8242 // ins_pipe(faddF_reg);
8243 instruct MoveF2I_reg_reg(iRegI dst, regF src) %{
8244 predicate(UseVIS >= 3);
8245 match(Set dst (MoveF2I src));
8246
8247 format %{ "MOVSTOUW $src,$dst\t! MoveF2I" %}
8248 ins_encode %{
8249 __ movstouw($src$$FloatRegister, $dst$$Register);
8250 %}
8251 ins_pipe(ialu_reg_reg);
8252 %}
8253
8254 instruct MoveI2F_reg_reg(regF dst, iRegI src) %{
8255 predicate(UseVIS >= 3);
8256 match(Set dst (MoveI2F src));
8257
8258 format %{ "MOVWTOS $src,$dst\t! MoveI2F" %}
8259 ins_encode %{
8260 __ movwtos($src$$Register, $dst$$FloatRegister);
8261 %}
8262 ins_pipe(ialu_reg_reg);
8263 %}
8264
8265 instruct MoveD2L_reg_reg(iRegL dst, regD src) %{
8266 predicate(UseVIS >= 3);
8267 match(Set dst (MoveD2L src));
8268
8269 format %{ "MOVDTOX $src,$dst\t! MoveD2L" %}
8270 ins_encode %{
8271 __ movdtox(as_DoubleFloatRegister($src$$reg), $dst$$Register);
8272 %}
8273 ins_pipe(ialu_reg_reg);
8274 %}
8275
8276 instruct MoveL2D_reg_reg(regD dst, iRegL src) %{
8277 predicate(UseVIS >= 3);
8278 match(Set dst (MoveL2D src));
8279
8280 format %{ "MOVXTOD $src,$dst\t! MoveL2D" %}
8281 ins_encode %{
8282 __ movxtod($src$$Register, as_DoubleFloatRegister($dst$$reg));
8283 %}
8284 ins_pipe(ialu_reg_reg);
8285 %}
8286
8287
8288 // Raw moves between float and general registers using stack.
8289
8290 instruct MoveF2I_stack_reg(iRegI dst, stackSlotF src) %{
8291 match(Set dst (MoveF2I src));
8292 effect(DEF dst, USE src);
8293 ins_cost(MEMORY_REF_COST);
8294
8295 size(4);
8296 format %{ "LDUW $src,$dst\t! MoveF2I" %}
8297 opcode(Assembler::lduw_op3);
8298 ins_encode(simple_form3_mem_reg( src, dst ) );
8299 ins_pipe(iload_mem);
8300 %}
8301
8302 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{
8303 match(Set dst (MoveI2F src));
8304 effect(DEF dst, USE src);
8305 ins_cost(MEMORY_REF_COST);
8306
8307 size(4);
8308 format %{ "LDF $src,$dst\t! MoveI2F" %}
8309 opcode(Assembler::ldf_op3);
8310 ins_encode(simple_form3_mem_reg(src, dst));
8311 ins_pipe(floadF_stk);
8312 %}
8313
8314 instruct MoveD2L_stack_reg(iRegL dst, stackSlotD src) %{
8315 match(Set dst (MoveD2L src));
8316 effect(DEF dst, USE src);
8317 ins_cost(MEMORY_REF_COST);
8318
8319 size(4);
8320 format %{ "LDX $src,$dst\t! MoveD2L" %}
8321 opcode(Assembler::ldx_op3);
8322 ins_encode(simple_form3_mem_reg( src, dst ) );
8323 ins_pipe(iload_mem);
8324 %}
8325
8326 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{
8327 match(Set dst (MoveL2D src));
8328 effect(DEF dst, USE src);
8329 ins_cost(MEMORY_REF_COST);
8330
8331 size(4);
8332 format %{ "LDDF $src,$dst\t! MoveL2D" %}
8333 opcode(Assembler::lddf_op3);
8334 ins_encode(simple_form3_mem_reg(src, dst));
8335 ins_pipe(floadD_stk);
8336 %}
8337
8338 instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{
8339 match(Set dst (MoveF2I src));
8340 effect(DEF dst, USE src);
8341 ins_cost(MEMORY_REF_COST);
8342
8343 size(4);
8344 format %{ "STF $src,$dst\t! MoveF2I" %}
8345 opcode(Assembler::stf_op3);
8346 ins_encode(simple_form3_mem_reg(dst, src));
8347 ins_pipe(fstoreF_stk_reg);
8348 %}
8349
8350 instruct MoveI2F_reg_stack(stackSlotF dst, iRegI src) %{
8351 match(Set dst (MoveI2F src));
8352 effect(DEF dst, USE src);
8353 ins_cost(MEMORY_REF_COST);
8354
8355 size(4);
8356 format %{ "STW $src,$dst\t! MoveI2F" %}
8357 opcode(Assembler::stw_op3);
8358 ins_encode(simple_form3_mem_reg( dst, src ) );
8359 ins_pipe(istore_mem_reg);
8360 %}
8361
8362 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{
8363 match(Set dst (MoveD2L src));
8364 effect(DEF dst, USE src);
8365 ins_cost(MEMORY_REF_COST);
8366
8367 size(4);
8368 format %{ "STDF $src,$dst\t! MoveD2L" %}
8369 opcode(Assembler::stdf_op3);
8370 ins_encode(simple_form3_mem_reg(dst, src));
8371 ins_pipe(fstoreD_stk_reg);
8372 %}
8373
8374 instruct MoveL2D_reg_stack(stackSlotD dst, iRegL src) %{
8375 match(Set dst (MoveL2D src));
8376 effect(DEF dst, USE src);
8377 ins_cost(MEMORY_REF_COST);
8378
8379 size(4);
8380 format %{ "STX $src,$dst\t! MoveL2D" %}
8381 opcode(Assembler::stx_op3);
8382 ins_encode(simple_form3_mem_reg( dst, src ) );
8383 ins_pipe(istore_mem_reg);
8384 %}
8385
8386
8387 //----------Arithmetic Conversion Instructions---------------------------------
8388 // The conversions operations are all Alpha sorted. Please keep it that way!
8389
8390 instruct convD2F_reg(regF dst, regD src) %{
8391 match(Set dst (ConvD2F src));
8392 size(4);
8393 format %{ "FDTOS $src,$dst" %}
8394 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdtos_opf);
8395 ins_encode(form3_opf_rs2D_rdF(src, dst));
8396 ins_pipe(fcvtD2F);
8397 %}
8398
8399
8400 // Convert a double to an int in a float register.
8401 // If the double is a NAN, stuff a zero in instead.
8402 instruct convD2I_helper(regF dst, regD src, flagsRegF0 fcc0) %{
8403 effect(DEF dst, USE src, KILL fcc0);
8404 format %{ "FCMPd fcc0,$src,$src\t! check for NAN\n\t"
8405 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
8406 "FDTOI $src,$dst\t! convert in delay slot\n\t"
8407 "FITOS $dst,$dst\t! change NaN/max-int to valid float\n\t"
8408 "FSUBs $dst,$dst,$dst\t! cleared only if nan\n"
8409 "skip:" %}
8410 ins_encode(form_d2i_helper(src,dst));
8411 ins_pipe(fcvtD2I);
8412 %}
8413
8414 instruct convD2I_stk(stackSlotI dst, regD src) %{
8415 match(Set dst (ConvD2I src));
8416 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
8417 expand %{
8418 regF tmp;
8419 convD2I_helper(tmp, src);
8420 regF_to_stkI(dst, tmp);
8421 %}
8422 %}
8423
8424 instruct convD2I_reg(iRegI dst, regD src) %{
8425 predicate(UseVIS >= 3);
8426 match(Set dst (ConvD2I src));
8427 ins_cost(DEFAULT_COST*2 + BRANCH_COST);
8428 expand %{
8429 regF tmp;
8430 convD2I_helper(tmp, src);
8431 MoveF2I_reg_reg(dst, tmp);
8432 %}
8433 %}
8434
8435
8436 // Convert a double to a long in a double register.
8437 // If the double is a NAN, stuff a zero in instead.
8438 instruct convD2L_helper(regD dst, regD src, flagsRegF0 fcc0) %{
8439 effect(DEF dst, USE src, KILL fcc0);
8440 format %{ "FCMPd fcc0,$src,$src\t! check for NAN\n\t"
8441 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
8442 "FDTOX $src,$dst\t! convert in delay slot\n\t"
8443 "FXTOD $dst,$dst\t! change NaN/max-long to valid double\n\t"
8444 "FSUBd $dst,$dst,$dst\t! cleared only if nan\n"
8445 "skip:" %}
8446 ins_encode(form_d2l_helper(src,dst));
8447 ins_pipe(fcvtD2L);
8448 %}
8449
8450 instruct convD2L_stk(stackSlotL dst, regD src) %{
8451 match(Set dst (ConvD2L src));
8452 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
8453 expand %{
8454 regD tmp;
8455 convD2L_helper(tmp, src);
8456 regD_to_stkL(dst, tmp);
8457 %}
8458 %}
8459
8460 instruct convD2L_reg(iRegL dst, regD src) %{
8461 predicate(UseVIS >= 3);
8462 match(Set dst (ConvD2L src));
8463 ins_cost(DEFAULT_COST*2 + BRANCH_COST);
8464 expand %{
8465 regD tmp;
8466 convD2L_helper(tmp, src);
8467 MoveD2L_reg_reg(dst, tmp);
8468 %}
8469 %}
8470
8471
8472 instruct convF2D_reg(regD dst, regF src) %{
8473 match(Set dst (ConvF2D src));
8474 format %{ "FSTOD $src,$dst" %}
8475 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fstod_opf);
8476 ins_encode(form3_opf_rs2F_rdD(src, dst));
8477 ins_pipe(fcvtF2D);
8478 %}
8479
8480
8481 // Convert a float to an int in a float register.
8482 // If the float is a NAN, stuff a zero in instead.
8483 instruct convF2I_helper(regF dst, regF src, flagsRegF0 fcc0) %{
8484 effect(DEF dst, USE src, KILL fcc0);
8485 format %{ "FCMPs fcc0,$src,$src\t! check for NAN\n\t"
8486 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
8487 "FSTOI $src,$dst\t! convert in delay slot\n\t"
8488 "FITOS $dst,$dst\t! change NaN/max-int to valid float\n\t"
8489 "FSUBs $dst,$dst,$dst\t! cleared only if nan\n"
8490 "skip:" %}
8491 ins_encode(form_f2i_helper(src,dst));
8492 ins_pipe(fcvtF2I);
8493 %}
8494
8495 instruct convF2I_stk(stackSlotI dst, regF src) %{
8496 match(Set dst (ConvF2I src));
8497 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
8498 expand %{
8499 regF tmp;
8500 convF2I_helper(tmp, src);
8501 regF_to_stkI(dst, tmp);
8502 %}
8503 %}
8504
8505 instruct convF2I_reg(iRegI dst, regF src) %{
8506 predicate(UseVIS >= 3);
8507 match(Set dst (ConvF2I src));
8508 ins_cost(DEFAULT_COST*2 + BRANCH_COST);
8509 expand %{
8510 regF tmp;
8511 convF2I_helper(tmp, src);
8512 MoveF2I_reg_reg(dst, tmp);
8513 %}
8514 %}
8515
8516
8517 // Convert a float to a long in a float register.
8518 // If the float is a NAN, stuff a zero in instead.
8519 instruct convF2L_helper(regD dst, regF src, flagsRegF0 fcc0) %{
8520 effect(DEF dst, USE src, KILL fcc0);
8521 format %{ "FCMPs fcc0,$src,$src\t! check for NAN\n\t"
8522 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
8523 "FSTOX $src,$dst\t! convert in delay slot\n\t"
8524 "FXTOD $dst,$dst\t! change NaN/max-long to valid double\n\t"
8525 "FSUBd $dst,$dst,$dst\t! cleared only if nan\n"
8526 "skip:" %}
8527 ins_encode(form_f2l_helper(src,dst));
8528 ins_pipe(fcvtF2L);
8529 %}
8530
8531 instruct convF2L_stk(stackSlotL dst, regF src) %{
8532 match(Set dst (ConvF2L src));
8533 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
8534 expand %{
8535 regD tmp;
8536 convF2L_helper(tmp, src);
8537 regD_to_stkL(dst, tmp);
8538 %}
8539 %}
8540
8541 instruct convF2L_reg(iRegL dst, regF src) %{
8542 predicate(UseVIS >= 3);
8543 match(Set dst (ConvF2L src));
8544 ins_cost(DEFAULT_COST*2 + BRANCH_COST);
8545 expand %{
8546 regD tmp;
8547 convF2L_helper(tmp, src);
8548 MoveD2L_reg_reg(dst, tmp);
8549 %}
8550 %}
8551
8552
8553 instruct convI2D_helper(regD dst, regF tmp) %{
8554 effect(USE tmp, DEF dst);
8555 format %{ "FITOD $tmp,$dst" %}
8556 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf);
8557 ins_encode(form3_opf_rs2F_rdD(tmp, dst));
8558 ins_pipe(fcvtI2D);
8559 %}
8560
8561 instruct convI2D_stk(stackSlotI src, regD dst) %{
8562 match(Set dst (ConvI2D src));
8563 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8564 expand %{
8565 regF tmp;
8566 stkI_to_regF(tmp, src);
8567 convI2D_helper(dst, tmp);
8568 %}
8569 %}
8570
8571 instruct convI2D_reg(regD_low dst, iRegI src) %{
8572 predicate(UseVIS >= 3);
8573 match(Set dst (ConvI2D src));
8574 expand %{
8575 regF tmp;
8576 MoveI2F_reg_reg(tmp, src);
8577 convI2D_helper(dst, tmp);
8578 %}
8579 %}
8580
8581 instruct convI2D_mem(regD_low dst, memory mem) %{
8582 match(Set dst (ConvI2D (LoadI mem)));
8583 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8584 size(8);
8585 format %{ "LDF $mem,$dst\n\t"
8586 "FITOD $dst,$dst" %}
8587 opcode(Assembler::ldf_op3, Assembler::fitod_opf);
8588 ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst));
8589 ins_pipe(floadF_mem);
8590 %}
8591
8592
8593 instruct convI2F_helper(regF dst, regF tmp) %{
8594 effect(DEF dst, USE tmp);
8595 format %{ "FITOS $tmp,$dst" %}
8596 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitos_opf);
8597 ins_encode(form3_opf_rs2F_rdF(tmp, dst));
8598 ins_pipe(fcvtI2F);
8599 %}
8600
8601 instruct convI2F_stk(regF dst, stackSlotI src) %{
8602 match(Set dst (ConvI2F src));
8603 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8604 expand %{
8605 regF tmp;
8606 stkI_to_regF(tmp,src);
8607 convI2F_helper(dst, tmp);
8608 %}
8609 %}
8610
8611 instruct convI2F_reg(regF dst, iRegI src) %{
8612 predicate(UseVIS >= 3);
8613 match(Set dst (ConvI2F src));
8614 ins_cost(DEFAULT_COST);
8615 expand %{
8616 regF tmp;
8617 MoveI2F_reg_reg(tmp, src);
8618 convI2F_helper(dst, tmp);
8619 %}
8620 %}
8621
8622 instruct convI2F_mem( regF dst, memory mem ) %{
8623 match(Set dst (ConvI2F (LoadI mem)));
8624 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8625 size(8);
8626 format %{ "LDF $mem,$dst\n\t"
8627 "FITOS $dst,$dst" %}
8628 opcode(Assembler::ldf_op3, Assembler::fitos_opf);
8629 ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst));
8630 ins_pipe(floadF_mem);
8631 %}
8632
8633
8634 instruct convI2L_reg(iRegL dst, iRegI src) %{
8635 match(Set dst (ConvI2L src));
8636 size(4);
8637 format %{ "SRA $src,0,$dst\t! int->long" %}
8638 opcode(Assembler::sra_op3, Assembler::arith_op);
8639 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) );
8640 ins_pipe(ialu_reg_reg);
8641 %}
8642
8643 // Zero-extend convert int to long
8644 instruct convI2L_reg_zex(iRegL dst, iRegI src, immL_32bits mask ) %{
8645 match(Set dst (AndL (ConvI2L src) mask) );
8646 size(4);
8647 format %{ "SRL $src,0,$dst\t! zero-extend int to long" %}
8648 opcode(Assembler::srl_op3, Assembler::arith_op);
8649 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) );
8650 ins_pipe(ialu_reg_reg);
8651 %}
8652
8653 // Zero-extend long
8654 instruct zerox_long(iRegL dst, iRegL src, immL_32bits mask ) %{
8655 match(Set dst (AndL src mask) );
8656 size(4);
8657 format %{ "SRL $src,0,$dst\t! zero-extend long" %}
8658 opcode(Assembler::srl_op3, Assembler::arith_op);
8659 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) );
8660 ins_pipe(ialu_reg_reg);
8661 %}
8662
8663
8664 //-----------
8665 // Long to Double conversion using V8 opcodes.
8666 // Still useful because cheetah traps and becomes
8667 // amazingly slow for some common numbers.
8668
8669 // Magic constant, 0x43300000
8670 instruct loadConI_x43300000(iRegI dst) %{
8671 effect(DEF dst);
8672 size(4);
8673 format %{ "SETHI HI(0x43300000),$dst\t! 2^52" %}
8674 ins_encode(SetHi22(0x43300000, dst));
8675 ins_pipe(ialu_none);
8676 %}
8677
8678 // Magic constant, 0x41f00000
8679 instruct loadConI_x41f00000(iRegI dst) %{
8680 effect(DEF dst);
8681 size(4);
8682 format %{ "SETHI HI(0x41f00000),$dst\t! 2^32" %}
8683 ins_encode(SetHi22(0x41f00000, dst));
8684 ins_pipe(ialu_none);
8685 %}
8686
8687 // Construct a double from two float halves
8688 instruct regDHi_regDLo_to_regD(regD_low dst, regD_low src1, regD_low src2) %{
8689 effect(DEF dst, USE src1, USE src2);
8690 size(8);
8691 format %{ "FMOVS $src1.hi,$dst.hi\n\t"
8692 "FMOVS $src2.lo,$dst.lo" %}
8693 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmovs_opf);
8694 ins_encode(form3_opf_rs2D_hi_rdD_hi(src1, dst), form3_opf_rs2D_lo_rdD_lo(src2, dst));
8695 ins_pipe(faddD_reg_reg);
8696 %}
8697
8698 // Convert integer in high half of a double register (in the lower half of
8699 // the double register file) to double
8700 instruct convI2D_regDHi_regD(regD dst, regD_low src) %{
8701 effect(DEF dst, USE src);
8702 size(4);
8703 format %{ "FITOD $src,$dst" %}
8704 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf);
8705 ins_encode(form3_opf_rs2D_rdD(src, dst));
8706 ins_pipe(fcvtLHi2D);
8707 %}
8708
8709 // Add float double precision
8710 instruct addD_regD_regD(regD dst, regD src1, regD src2) %{
8711 effect(DEF dst, USE src1, USE src2);
8712 size(4);
8713 format %{ "FADDD $src1,$src2,$dst" %}
8714 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::faddd_opf);
8715 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
8716 ins_pipe(faddD_reg_reg);
8717 %}
8718
8719 // Sub float double precision
8720 instruct subD_regD_regD(regD dst, regD src1, regD src2) %{
8721 effect(DEF dst, USE src1, USE src2);
8722 size(4);
8723 format %{ "FSUBD $src1,$src2,$dst" %}
8724 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubd_opf);
8725 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
8726 ins_pipe(faddD_reg_reg);
8727 %}
8728
8729 // Mul float double precision
8730 instruct mulD_regD_regD(regD dst, regD src1, regD src2) %{
8731 effect(DEF dst, USE src1, USE src2);
8732 size(4);
8733 format %{ "FMULD $src1,$src2,$dst" %}
8734 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuld_opf);
8735 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
8736 ins_pipe(fmulD_reg_reg);
8737 %}
8738
8739 instruct convL2D_reg_slow_fxtof(regD dst, stackSlotL src) %{
8740 match(Set dst (ConvL2D src));
8741 ins_cost(DEFAULT_COST*8 + MEMORY_REF_COST*6);
8742
8743 expand %{
8744 regD_low tmpsrc;
8745 iRegI ix43300000;
8746 iRegI ix41f00000;
8747 stackSlotL lx43300000;
8748 stackSlotL lx41f00000;
8749 regD_low dx43300000;
8750 regD dx41f00000;
8751 regD tmp1;
8752 regD_low tmp2;
8753 regD tmp3;
8754 regD tmp4;
8755
8756 stkL_to_regD(tmpsrc, src);
8757
8758 loadConI_x43300000(ix43300000);
8759 loadConI_x41f00000(ix41f00000);
8760 regI_to_stkLHi(lx43300000, ix43300000);
8761 regI_to_stkLHi(lx41f00000, ix41f00000);
8762 stkL_to_regD(dx43300000, lx43300000);
8763 stkL_to_regD(dx41f00000, lx41f00000);
8764
8765 convI2D_regDHi_regD(tmp1, tmpsrc);
8766 regDHi_regDLo_to_regD(tmp2, dx43300000, tmpsrc);
8767 subD_regD_regD(tmp3, tmp2, dx43300000);
8768 mulD_regD_regD(tmp4, tmp1, dx41f00000);
8769 addD_regD_regD(dst, tmp3, tmp4);
8770 %}
8771 %}
8772
8773 // Long to Double conversion using fast fxtof
8774 instruct convL2D_helper(regD dst, regD tmp) %{
8775 effect(DEF dst, USE tmp);
8776 size(4);
8777 format %{ "FXTOD $tmp,$dst" %}
8778 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtod_opf);
8779 ins_encode(form3_opf_rs2D_rdD(tmp, dst));
8780 ins_pipe(fcvtL2D);
8781 %}
8782
8783 instruct convL2D_stk_fast_fxtof(regD dst, stackSlotL src) %{
8784 predicate(VM_Version::has_fast_fxtof());
8785 match(Set dst (ConvL2D src));
8786 ins_cost(DEFAULT_COST + 3 * MEMORY_REF_COST);
8787 expand %{
8788 regD tmp;
8789 stkL_to_regD(tmp, src);
8790 convL2D_helper(dst, tmp);
8791 %}
8792 %}
8793
8794 instruct convL2D_reg(regD dst, iRegL src) %{
8795 predicate(UseVIS >= 3);
8796 match(Set dst (ConvL2D src));
8797 expand %{
8798 regD tmp;
8799 MoveL2D_reg_reg(tmp, src);
8800 convL2D_helper(dst, tmp);
8801 %}
8802 %}
8803
8804 // Long to Float conversion using fast fxtof
8805 instruct convL2F_helper(regF dst, regD tmp) %{
8806 effect(DEF dst, USE tmp);
8807 size(4);
8808 format %{ "FXTOS $tmp,$dst" %}
8809 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtos_opf);
8810 ins_encode(form3_opf_rs2D_rdF(tmp, dst));
8811 ins_pipe(fcvtL2F);
8812 %}
8813
8814 instruct convL2F_stk_fast_fxtof(regF dst, stackSlotL src) %{
8815 match(Set dst (ConvL2F src));
8816 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8817 expand %{
8818 regD tmp;
8819 stkL_to_regD(tmp, src);
8820 convL2F_helper(dst, tmp);
8821 %}
8822 %}
8823
8824 instruct convL2F_reg(regF dst, iRegL src) %{
8825 predicate(UseVIS >= 3);
8826 match(Set dst (ConvL2F src));
8827 ins_cost(DEFAULT_COST);
8828 expand %{
8829 regD tmp;
8830 MoveL2D_reg_reg(tmp, src);
8831 convL2F_helper(dst, tmp);
8832 %}
8833 %}
8834
8835 //-----------
8836
8837 instruct convL2I_reg(iRegI dst, iRegL src) %{
8838 match(Set dst (ConvL2I src));
8839 #ifndef _LP64
8840 format %{ "MOV $src.lo,$dst\t! long->int" %}
8841 ins_encode( form3_g0_rs2_rd_move_lo2( src, dst ) );
8842 ins_pipe(ialu_move_reg_I_to_L);
8843 #else
8844 size(4);
8845 format %{ "SRA $src,R_G0,$dst\t! long->int" %}
8846 ins_encode( form3_rs1_rd_signextend_lo1( src, dst ) );
8847 ins_pipe(ialu_reg);
8848 #endif
8849 %}
8850
8851 // Register Shift Right Immediate
8852 instruct shrL_reg_imm6_L2I(iRegI dst, iRegL src, immI_32_63 cnt) %{
8853 match(Set dst (ConvL2I (RShiftL src cnt)));
8854
8855 size(4);
8856 format %{ "SRAX $src,$cnt,$dst" %}
8857 opcode(Assembler::srax_op3, Assembler::arith_op);
8858 ins_encode( form3_sd_rs1_imm6_rd( src, cnt, dst ) );
8859 ins_pipe(ialu_reg_imm);
8860 %}
8861
8862 //----------Control Flow Instructions------------------------------------------
8863 // Compare Instructions
8864 // Compare Integers
8865 instruct compI_iReg(flagsReg icc, iRegI op1, iRegI op2) %{
8866 match(Set icc (CmpI op1 op2));
8867 effect( DEF icc, USE op1, USE op2 );
8868
8869 size(4);
8870 format %{ "CMP $op1,$op2" %}
8871 opcode(Assembler::subcc_op3, Assembler::arith_op);
8872 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8873 ins_pipe(ialu_cconly_reg_reg);
8874 %}
8875
8876 instruct compU_iReg(flagsRegU icc, iRegI op1, iRegI op2) %{
8877 match(Set icc (CmpU op1 op2));
8878
8879 size(4);
8880 format %{ "CMP $op1,$op2\t! unsigned" %}
8881 opcode(Assembler::subcc_op3, Assembler::arith_op);
8882 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8883 ins_pipe(ialu_cconly_reg_reg);
8884 %}
8885
8886 instruct compUL_iReg(flagsRegUL xcc, iRegL op1, iRegL op2) %{
8887 match(Set xcc (CmpUL op1 op2));
8888 effect(DEF xcc, USE op1, USE op2);
8889
8890 size(4);
8891 format %{ "CMP $op1,$op2\t! unsigned long" %}
8892 opcode(Assembler::subcc_op3, Assembler::arith_op);
8893 ins_encode(form3_rs1_rs2_rd(op1, op2, R_G0));
8894 ins_pipe(ialu_cconly_reg_reg);
8895 %}
8896
8897 instruct compI_iReg_imm13(flagsReg icc, iRegI op1, immI13 op2) %{
8898 match(Set icc (CmpI op1 op2));
8899 effect( DEF icc, USE op1 );
8900
8901 size(4);
8902 format %{ "CMP $op1,$op2" %}
8903 opcode(Assembler::subcc_op3, Assembler::arith_op);
8904 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8905 ins_pipe(ialu_cconly_reg_imm);
8906 %}
8907
8908 instruct testI_reg_reg( flagsReg icc, iRegI op1, iRegI op2, immI0 zero ) %{
8909 match(Set icc (CmpI (AndI op1 op2) zero));
8910
8911 size(4);
8912 format %{ "BTST $op2,$op1" %}
8913 opcode(Assembler::andcc_op3, Assembler::arith_op);
8914 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8915 ins_pipe(ialu_cconly_reg_reg_zero);
8916 %}
8917
8918 instruct testI_reg_imm( flagsReg icc, iRegI op1, immI13 op2, immI0 zero ) %{
8919 match(Set icc (CmpI (AndI op1 op2) zero));
8920
8921 size(4);
8922 format %{ "BTST $op2,$op1" %}
8923 opcode(Assembler::andcc_op3, Assembler::arith_op);
8924 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8925 ins_pipe(ialu_cconly_reg_imm_zero);
8926 %}
8927
8928 instruct compL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2 ) %{
8929 match(Set xcc (CmpL op1 op2));
8930 effect( DEF xcc, USE op1, USE op2 );
8931
8932 size(4);
8933 format %{ "CMP $op1,$op2\t\t! long" %}
8934 opcode(Assembler::subcc_op3, Assembler::arith_op);
8935 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8936 ins_pipe(ialu_cconly_reg_reg);
8937 %}
8938
8939 instruct compL_reg_con(flagsRegL xcc, iRegL op1, immL13 con) %{
8940 match(Set xcc (CmpL op1 con));
8941 effect( DEF xcc, USE op1, USE con );
8942
8943 size(4);
8944 format %{ "CMP $op1,$con\t\t! long" %}
8945 opcode(Assembler::subcc_op3, Assembler::arith_op);
8946 ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) );
8947 ins_pipe(ialu_cconly_reg_reg);
8948 %}
8949
8950 instruct testL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2, immL0 zero) %{
8951 match(Set xcc (CmpL (AndL op1 op2) zero));
8952 effect( DEF xcc, USE op1, USE op2 );
8953
8954 size(4);
8955 format %{ "BTST $op1,$op2\t\t! long" %}
8956 opcode(Assembler::andcc_op3, Assembler::arith_op);
8957 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8958 ins_pipe(ialu_cconly_reg_reg);
8959 %}
8960
8961 // useful for checking the alignment of a pointer:
8962 instruct testL_reg_con(flagsRegL xcc, iRegL op1, immL13 con, immL0 zero) %{
8963 match(Set xcc (CmpL (AndL op1 con) zero));
8964 effect( DEF xcc, USE op1, USE con );
8965
8966 size(4);
8967 format %{ "BTST $op1,$con\t\t! long" %}
8968 opcode(Assembler::andcc_op3, Assembler::arith_op);
8969 ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) );
8970 ins_pipe(ialu_cconly_reg_reg);
8971 %}
8972
8973 instruct compU_iReg_imm13(flagsRegU icc, iRegI op1, immU12 op2 ) %{
8974 match(Set icc (CmpU op1 op2));
8975
8976 size(4);
8977 format %{ "CMP $op1,$op2\t! unsigned" %}
8978 opcode(Assembler::subcc_op3, Assembler::arith_op);
8979 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8980 ins_pipe(ialu_cconly_reg_imm);
8981 %}
8982
8983 instruct compUL_iReg_imm13(flagsRegUL xcc, iRegL op1, immUL12 op2) %{
8984 match(Set xcc (CmpUL op1 op2));
8985 effect(DEF xcc, USE op1, USE op2);
8986
8987 size(4);
8988 format %{ "CMP $op1,$op2\t! unsigned long" %}
8989 opcode(Assembler::subcc_op3, Assembler::arith_op);
8990 ins_encode(form3_rs1_simm13_rd(op1, op2, R_G0));
8991 ins_pipe(ialu_cconly_reg_imm);
8992 %}
8993
8994 // Compare Pointers
8995 instruct compP_iRegP(flagsRegP pcc, iRegP op1, iRegP op2 ) %{
8996 match(Set pcc (CmpP op1 op2));
8997
8998 size(4);
8999 format %{ "CMP $op1,$op2\t! ptr" %}
9000 opcode(Assembler::subcc_op3, Assembler::arith_op);
9001 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
9002 ins_pipe(ialu_cconly_reg_reg);
9003 %}
9004
9005 instruct compP_iRegP_imm13(flagsRegP pcc, iRegP op1, immP13 op2 ) %{
9006 match(Set pcc (CmpP op1 op2));
9007
9008 size(4);
9009 format %{ "CMP $op1,$op2\t! ptr" %}
9010 opcode(Assembler::subcc_op3, Assembler::arith_op);
9011 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
9012 ins_pipe(ialu_cconly_reg_imm);
9013 %}
9014
9015 // Compare Narrow oops
9016 instruct compN_iRegN(flagsReg icc, iRegN op1, iRegN op2 ) %{
9017 match(Set icc (CmpN op1 op2));
9018
9019 size(4);
9020 format %{ "CMP $op1,$op2\t! compressed ptr" %}
9021 opcode(Assembler::subcc_op3, Assembler::arith_op);
9022 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
9023 ins_pipe(ialu_cconly_reg_reg);
9024 %}
9025
9026 instruct compN_iRegN_immN0(flagsReg icc, iRegN op1, immN0 op2 ) %{
9027 match(Set icc (CmpN op1 op2));
9028
9029 size(4);
9030 format %{ "CMP $op1,$op2\t! compressed ptr" %}
9031 opcode(Assembler::subcc_op3, Assembler::arith_op);
9032 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
9033 ins_pipe(ialu_cconly_reg_imm);
9034 %}
9035
9036 //----------Max and Min--------------------------------------------------------
9037 // Min Instructions
9038 // Conditional move for min
9039 instruct cmovI_reg_lt( iRegI op2, iRegI op1, flagsReg icc ) %{
9040 effect( USE_DEF op2, USE op1, USE icc );
9041
9042 size(4);
9043 format %{ "MOVlt icc,$op1,$op2\t! min" %}
9044 opcode(Assembler::less);
9045 ins_encode( enc_cmov_reg_minmax(op2,op1) );
9046 ins_pipe(ialu_reg_flags);
9047 %}
9048
9049 // Min Register with Register.
9050 instruct minI_eReg(iRegI op1, iRegI op2) %{
9051 match(Set op2 (MinI op1 op2));
9052 ins_cost(DEFAULT_COST*2);
9053 expand %{
9054 flagsReg icc;
9055 compI_iReg(icc,op1,op2);
9056 cmovI_reg_lt(op2,op1,icc);
9057 %}
9058 %}
9059
9060 // Max Instructions
9061 // Conditional move for max
9062 instruct cmovI_reg_gt( iRegI op2, iRegI op1, flagsReg icc ) %{
9063 effect( USE_DEF op2, USE op1, USE icc );
9064 format %{ "MOVgt icc,$op1,$op2\t! max" %}
9065 opcode(Assembler::greater);
9066 ins_encode( enc_cmov_reg_minmax(op2,op1) );
9067 ins_pipe(ialu_reg_flags);
9068 %}
9069
9070 // Max Register with Register
9071 instruct maxI_eReg(iRegI op1, iRegI op2) %{
9072 match(Set op2 (MaxI op1 op2));
9073 ins_cost(DEFAULT_COST*2);
9074 expand %{
9075 flagsReg icc;
9076 compI_iReg(icc,op1,op2);
9077 cmovI_reg_gt(op2,op1,icc);
9078 %}
9079 %}
9080
9081
9082 //----------Float Compares----------------------------------------------------
9083 // Compare floating, generate condition code
9084 instruct cmpF_cc(flagsRegF fcc, regF src1, regF src2) %{
9085 match(Set fcc (CmpF src1 src2));
9086
9087 size(4);
9088 format %{ "FCMPs $fcc,$src1,$src2" %}
9089 opcode(Assembler::fpop2_op3, Assembler::arith_op, Assembler::fcmps_opf);
9090 ins_encode( form3_opf_rs1F_rs2F_fcc( src1, src2, fcc ) );
9091 ins_pipe(faddF_fcc_reg_reg_zero);
9092 %}
9093
9094 instruct cmpD_cc(flagsRegF fcc, regD src1, regD src2) %{
9095 match(Set fcc (CmpD src1 src2));
9096
9097 size(4);
9098 format %{ "FCMPd $fcc,$src1,$src2" %}
9099 opcode(Assembler::fpop2_op3, Assembler::arith_op, Assembler::fcmpd_opf);
9100 ins_encode( form3_opf_rs1D_rs2D_fcc( src1, src2, fcc ) );
9101 ins_pipe(faddD_fcc_reg_reg_zero);
9102 %}
9103
9104
9105 // Compare floating, generate -1,0,1
9106 instruct cmpF_reg(iRegI dst, regF src1, regF src2, flagsRegF0 fcc0) %{
9107 match(Set dst (CmpF3 src1 src2));
9108 effect(KILL fcc0);
9109 ins_cost(DEFAULT_COST*3+BRANCH_COST*3);
9110 format %{ "fcmpl $dst,$src1,$src2" %}
9111 // Primary = float
9112 opcode( true );
9113 ins_encode( floating_cmp( dst, src1, src2 ) );
9114 ins_pipe( floating_cmp );
9115 %}
9116
9117 instruct cmpD_reg(iRegI dst, regD src1, regD src2, flagsRegF0 fcc0) %{
9118 match(Set dst (CmpD3 src1 src2));
9119 effect(KILL fcc0);
9120 ins_cost(DEFAULT_COST*3+BRANCH_COST*3);
9121 format %{ "dcmpl $dst,$src1,$src2" %}
9122 // Primary = double (not float)
9123 opcode( false );
9124 ins_encode( floating_cmp( dst, src1, src2 ) );
9125 ins_pipe( floating_cmp );
9126 %}
9127
9128 //----------Branches---------------------------------------------------------
9129 // Jump
9130 // (compare 'operand indIndex' and 'instruct addP_reg_reg' above)
9131 instruct jumpXtnd(iRegX switch_val, o7RegI table) %{
9132 match(Jump switch_val);
9133 effect(TEMP table);
9134
9135 ins_cost(350);
9136
9137 format %{ "ADD $constanttablebase, $constantoffset, O7\n\t"
9138 "LD [O7 + $switch_val], O7\n\t"
9139 "JUMP O7" %}
9140 ins_encode %{
9141 // Calculate table address into a register.
9142 Register table_reg;
9143 Register label_reg = O7;
9144 // If we are calculating the size of this instruction don't trust
9145 // zero offsets because they might change when
9146 // MachConstantBaseNode decides to optimize the constant table
9147 // base.
9148 if ((constant_offset() == 0) && !Compile::current()->in_scratch_emit_size()) {
9149 table_reg = $constanttablebase;
9150 } else {
9151 table_reg = O7;
9152 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset, O7);
9153 __ add($constanttablebase, con_offset, table_reg);
9154 }
9155
9156 // Jump to base address + switch value
9157 __ ld_ptr(table_reg, $switch_val$$Register, label_reg);
9158 __ jmp(label_reg, G0);
9159 __ delayed()->nop();
9160 %}
9161 ins_pipe(ialu_reg_reg);
9162 %}
9163
9164 // Direct Branch. Use V8 version with longer range.
9165 instruct branch(label labl) %{
9166 match(Goto);
9167 effect(USE labl);
9168
9169 size(8);
9170 ins_cost(BRANCH_COST);
9171 format %{ "BA $labl" %}
9172 ins_encode %{
9173 Label* L = $labl$$label;
9174 __ ba(*L);
9175 __ delayed()->nop();
9176 %}
9177 ins_pipe(br);
9178 %}
9179
9180 // Direct Branch, short with no delay slot
9181 instruct branch_short(label labl) %{
9182 match(Goto);
9183 predicate(UseCBCond);
9184 effect(USE labl);
9185
9186 size(4);
9187 ins_cost(BRANCH_COST);
9188 format %{ "BA $labl\t! short branch" %}
9189 ins_encode %{
9190 Label* L = $labl$$label;
9191 assert(__ use_cbcond(*L), "back to back cbcond");
9192 __ ba_short(*L);
9193 %}
9194 ins_short_branch(1);
9195 ins_avoid_back_to_back(1);
9196 ins_pipe(cbcond_reg_imm);
9197 %}
9198
9199 // Conditional Direct Branch
9200 instruct branchCon(cmpOp cmp, flagsReg icc, label labl) %{
9201 match(If cmp icc);
9202 effect(USE labl);
9203
9204 size(8);
9205 ins_cost(BRANCH_COST);
9206 format %{ "BP$cmp $icc,$labl" %}
9207 // Prim = bits 24-22, Secnd = bits 31-30
9208 ins_encode( enc_bp( labl, cmp, icc ) );
9209 ins_pipe(br_cc);
9210 %}
9211
9212 instruct branchConU(cmpOpU cmp, flagsRegU icc, label labl) %{
9213 match(If cmp icc);
9214 effect(USE labl);
9215
9216 ins_cost(BRANCH_COST);
9217 format %{ "BP$cmp $icc,$labl" %}
9218 // Prim = bits 24-22, Secnd = bits 31-30
9219 ins_encode( enc_bp( labl, cmp, icc ) );
9220 ins_pipe(br_cc);
9221 %}
9222
9223 instruct branchConP(cmpOpP cmp, flagsRegP pcc, label labl) %{
9224 match(If cmp pcc);
9225 effect(USE labl);
9226
9227 size(8);
9228 ins_cost(BRANCH_COST);
9229 format %{ "BP$cmp $pcc,$labl" %}
9230 ins_encode %{
9231 Label* L = $labl$$label;
9232 Assembler::Predict predict_taken =
9233 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9234
9235 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, *L);
9236 __ delayed()->nop();
9237 %}
9238 ins_pipe(br_cc);
9239 %}
9240
9241 instruct branchConF(cmpOpF cmp, flagsRegF fcc, label labl) %{
9242 match(If cmp fcc);
9243 effect(USE labl);
9244
9245 size(8);
9246 ins_cost(BRANCH_COST);
9247 format %{ "FBP$cmp $fcc,$labl" %}
9248 ins_encode %{
9249 Label* L = $labl$$label;
9250 Assembler::Predict predict_taken =
9251 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9252
9253 __ fbp( (Assembler::Condition)($cmp$$cmpcode), false, (Assembler::CC)($fcc$$reg), predict_taken, *L);
9254 __ delayed()->nop();
9255 %}
9256 ins_pipe(br_fcc);
9257 %}
9258
9259 instruct branchLoopEnd(cmpOp cmp, flagsReg icc, label labl) %{
9260 match(CountedLoopEnd cmp icc);
9261 effect(USE labl);
9262
9263 size(8);
9264 ins_cost(BRANCH_COST);
9265 format %{ "BP$cmp $icc,$labl\t! Loop end" %}
9266 // Prim = bits 24-22, Secnd = bits 31-30
9267 ins_encode( enc_bp( labl, cmp, icc ) );
9268 ins_pipe(br_cc);
9269 %}
9270
9271 instruct branchLoopEndU(cmpOpU cmp, flagsRegU icc, label labl) %{
9272 match(CountedLoopEnd cmp icc);
9273 effect(USE labl);
9274
9275 size(8);
9276 ins_cost(BRANCH_COST);
9277 format %{ "BP$cmp $icc,$labl\t! Loop end" %}
9278 // Prim = bits 24-22, Secnd = bits 31-30
9279 ins_encode( enc_bp( labl, cmp, icc ) );
9280 ins_pipe(br_cc);
9281 %}
9282
9283 // Compare and branch instructions
9284 instruct cmpI_reg_branch(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{
9285 match(If cmp (CmpI op1 op2));
9286 effect(USE labl, KILL icc);
9287
9288 size(12);
9289 ins_cost(BRANCH_COST);
9290 format %{ "CMP $op1,$op2\t! int\n\t"
9291 "BP$cmp $labl" %}
9292 ins_encode %{
9293 Label* L = $labl$$label;
9294 Assembler::Predict predict_taken =
9295 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9296 __ cmp($op1$$Register, $op2$$Register);
9297 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9298 __ delayed()->nop();
9299 %}
9300 ins_pipe(cmp_br_reg_reg);
9301 %}
9302
9303 instruct cmpI_imm_branch(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{
9304 match(If cmp (CmpI op1 op2));
9305 effect(USE labl, KILL icc);
9306
9307 size(12);
9308 ins_cost(BRANCH_COST);
9309 format %{ "CMP $op1,$op2\t! int\n\t"
9310 "BP$cmp $labl" %}
9311 ins_encode %{
9312 Label* L = $labl$$label;
9313 Assembler::Predict predict_taken =
9314 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9315 __ cmp($op1$$Register, $op2$$constant);
9316 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9317 __ delayed()->nop();
9318 %}
9319 ins_pipe(cmp_br_reg_imm);
9320 %}
9321
9322 instruct cmpU_reg_branch(cmpOpU cmp, iRegI op1, iRegI op2, label labl, flagsRegU icc) %{
9323 match(If cmp (CmpU op1 op2));
9324 effect(USE labl, KILL icc);
9325
9326 size(12);
9327 ins_cost(BRANCH_COST);
9328 format %{ "CMP $op1,$op2\t! unsigned\n\t"
9329 "BP$cmp $labl" %}
9330 ins_encode %{
9331 Label* L = $labl$$label;
9332 Assembler::Predict predict_taken =
9333 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9334 __ cmp($op1$$Register, $op2$$Register);
9335 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9336 __ delayed()->nop();
9337 %}
9338 ins_pipe(cmp_br_reg_reg);
9339 %}
9340
9341 instruct cmpU_imm_branch(cmpOpU cmp, iRegI op1, immI5 op2, label labl, flagsRegU icc) %{
9342 match(If cmp (CmpU op1 op2));
9343 effect(USE labl, KILL icc);
9344
9345 size(12);
9346 ins_cost(BRANCH_COST);
9347 format %{ "CMP $op1,$op2\t! unsigned\n\t"
9348 "BP$cmp $labl" %}
9349 ins_encode %{
9350 Label* L = $labl$$label;
9351 Assembler::Predict predict_taken =
9352 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9353 __ cmp($op1$$Register, $op2$$constant);
9354 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9355 __ delayed()->nop();
9356 %}
9357 ins_pipe(cmp_br_reg_imm);
9358 %}
9359
9360 instruct cmpUL_reg_branch(cmpOpU cmp, iRegL op1, iRegL op2, label labl, flagsRegUL xcc) %{
9361 match(If cmp (CmpUL op1 op2));
9362 effect(USE labl, KILL xcc);
9363
9364 size(12);
9365 ins_cost(BRANCH_COST);
9366 format %{ "CMP $op1,$op2\t! unsigned long\n\t"
9367 "BP$cmp $labl" %}
9368 ins_encode %{
9369 Label* L = $labl$$label;
9370 Assembler::Predict predict_taken =
9371 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9372 __ cmp($op1$$Register, $op2$$Register);
9373 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L);
9374 __ delayed()->nop();
9375 %}
9376 ins_pipe(cmp_br_reg_reg);
9377 %}
9378
9379 instruct cmpUL_imm_branch(cmpOpU cmp, iRegL op1, immL5 op2, label labl, flagsRegUL xcc) %{
9380 match(If cmp (CmpUL op1 op2));
9381 effect(USE labl, KILL xcc);
9382
9383 size(12);
9384 ins_cost(BRANCH_COST);
9385 format %{ "CMP $op1,$op2\t! unsigned long\n\t"
9386 "BP$cmp $labl" %}
9387 ins_encode %{
9388 Label* L = $labl$$label;
9389 Assembler::Predict predict_taken =
9390 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9391 __ cmp($op1$$Register, $op2$$constant);
9392 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L);
9393 __ delayed()->nop();
9394 %}
9395 ins_pipe(cmp_br_reg_imm);
9396 %}
9397
9398 instruct cmpL_reg_branch(cmpOp cmp, iRegL op1, iRegL op2, label labl, flagsRegL xcc) %{
9399 match(If cmp (CmpL op1 op2));
9400 effect(USE labl, KILL xcc);
9401
9402 size(12);
9403 ins_cost(BRANCH_COST);
9404 format %{ "CMP $op1,$op2\t! long\n\t"
9405 "BP$cmp $labl" %}
9406 ins_encode %{
9407 Label* L = $labl$$label;
9408 Assembler::Predict predict_taken =
9409 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9410 __ cmp($op1$$Register, $op2$$Register);
9411 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L);
9412 __ delayed()->nop();
9413 %}
9414 ins_pipe(cmp_br_reg_reg);
9415 %}
9416
9417 instruct cmpL_imm_branch(cmpOp cmp, iRegL op1, immL5 op2, label labl, flagsRegL xcc) %{
9418 match(If cmp (CmpL op1 op2));
9419 effect(USE labl, KILL xcc);
9420
9421 size(12);
9422 ins_cost(BRANCH_COST);
9423 format %{ "CMP $op1,$op2\t! long\n\t"
9424 "BP$cmp $labl" %}
9425 ins_encode %{
9426 Label* L = $labl$$label;
9427 Assembler::Predict predict_taken =
9428 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9429 __ cmp($op1$$Register, $op2$$constant);
9430 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L);
9431 __ delayed()->nop();
9432 %}
9433 ins_pipe(cmp_br_reg_imm);
9434 %}
9435
9436 // Compare Pointers and branch
9437 instruct cmpP_reg_branch(cmpOpP cmp, iRegP op1, iRegP op2, label labl, flagsRegP pcc) %{
9438 match(If cmp (CmpP op1 op2));
9439 effect(USE labl, KILL pcc);
9440
9441 size(12);
9442 ins_cost(BRANCH_COST);
9443 format %{ "CMP $op1,$op2\t! ptr\n\t"
9444 "B$cmp $labl" %}
9445 ins_encode %{
9446 Label* L = $labl$$label;
9447 Assembler::Predict predict_taken =
9448 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9449 __ cmp($op1$$Register, $op2$$Register);
9450 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, *L);
9451 __ delayed()->nop();
9452 %}
9453 ins_pipe(cmp_br_reg_reg);
9454 %}
9455
9456 instruct cmpP_null_branch(cmpOpP cmp, iRegP op1, immP0 null, label labl, flagsRegP pcc) %{
9457 match(If cmp (CmpP op1 null));
9458 effect(USE labl, KILL pcc);
9459
9460 size(12);
9461 ins_cost(BRANCH_COST);
9462 format %{ "CMP $op1,0\t! ptr\n\t"
9463 "B$cmp $labl" %}
9464 ins_encode %{
9465 Label* L = $labl$$label;
9466 Assembler::Predict predict_taken =
9467 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9468 __ cmp($op1$$Register, G0);
9469 // bpr() is not used here since it has shorter distance.
9470 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, *L);
9471 __ delayed()->nop();
9472 %}
9473 ins_pipe(cmp_br_reg_reg);
9474 %}
9475
9476 instruct cmpN_reg_branch(cmpOp cmp, iRegN op1, iRegN op2, label labl, flagsReg icc) %{
9477 match(If cmp (CmpN op1 op2));
9478 effect(USE labl, KILL icc);
9479
9480 size(12);
9481 ins_cost(BRANCH_COST);
9482 format %{ "CMP $op1,$op2\t! compressed ptr\n\t"
9483 "BP$cmp $labl" %}
9484 ins_encode %{
9485 Label* L = $labl$$label;
9486 Assembler::Predict predict_taken =
9487 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9488 __ cmp($op1$$Register, $op2$$Register);
9489 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9490 __ delayed()->nop();
9491 %}
9492 ins_pipe(cmp_br_reg_reg);
9493 %}
9494
9495 instruct cmpN_null_branch(cmpOp cmp, iRegN op1, immN0 null, label labl, flagsReg icc) %{
9496 match(If cmp (CmpN op1 null));
9497 effect(USE labl, KILL icc);
9498
9499 size(12);
9500 ins_cost(BRANCH_COST);
9501 format %{ "CMP $op1,0\t! compressed ptr\n\t"
9502 "BP$cmp $labl" %}
9503 ins_encode %{
9504 Label* L = $labl$$label;
9505 Assembler::Predict predict_taken =
9506 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9507 __ cmp($op1$$Register, G0);
9508 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9509 __ delayed()->nop();
9510 %}
9511 ins_pipe(cmp_br_reg_reg);
9512 %}
9513
9514 // Loop back branch
9515 instruct cmpI_reg_branchLoopEnd(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{
9516 match(CountedLoopEnd cmp (CmpI op1 op2));
9517 effect(USE labl, KILL icc);
9518
9519 size(12);
9520 ins_cost(BRANCH_COST);
9521 format %{ "CMP $op1,$op2\t! int\n\t"
9522 "BP$cmp $labl\t! Loop end" %}
9523 ins_encode %{
9524 Label* L = $labl$$label;
9525 Assembler::Predict predict_taken =
9526 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9527 __ cmp($op1$$Register, $op2$$Register);
9528 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9529 __ delayed()->nop();
9530 %}
9531 ins_pipe(cmp_br_reg_reg);
9532 %}
9533
9534 instruct cmpI_imm_branchLoopEnd(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{
9535 match(CountedLoopEnd cmp (CmpI op1 op2));
9536 effect(USE labl, KILL icc);
9537
9538 size(12);
9539 ins_cost(BRANCH_COST);
9540 format %{ "CMP $op1,$op2\t! int\n\t"
9541 "BP$cmp $labl\t! Loop end" %}
9542 ins_encode %{
9543 Label* L = $labl$$label;
9544 Assembler::Predict predict_taken =
9545 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9546 __ cmp($op1$$Register, $op2$$constant);
9547 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9548 __ delayed()->nop();
9549 %}
9550 ins_pipe(cmp_br_reg_imm);
9551 %}
9552
9553 // Short compare and branch instructions
9554 instruct cmpI_reg_branch_short(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{
9555 match(If cmp (CmpI op1 op2));
9556 predicate(UseCBCond);
9557 effect(USE labl, KILL icc);
9558
9559 size(4);
9560 ins_cost(BRANCH_COST);
9561 format %{ "CWB$cmp $op1,$op2,$labl\t! int" %}
9562 ins_encode %{
9563 Label* L = $labl$$label;
9564 assert(__ use_cbcond(*L), "back to back cbcond");
9565 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L);
9566 %}
9567 ins_short_branch(1);
9568 ins_avoid_back_to_back(1);
9569 ins_pipe(cbcond_reg_reg);
9570 %}
9571
9572 instruct cmpI_imm_branch_short(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{
9573 match(If cmp (CmpI op1 op2));
9574 predicate(UseCBCond);
9575 effect(USE labl, KILL icc);
9576
9577 size(4);
9578 ins_cost(BRANCH_COST);
9579 format %{ "CWB$cmp $op1,$op2,$labl\t! int" %}
9580 ins_encode %{
9581 Label* L = $labl$$label;
9582 assert(__ use_cbcond(*L), "back to back cbcond");
9583 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$constant, *L);
9584 %}
9585 ins_short_branch(1);
9586 ins_avoid_back_to_back(1);
9587 ins_pipe(cbcond_reg_imm);
9588 %}
9589
9590 instruct cmpU_reg_branch_short(cmpOpU cmp, iRegI op1, iRegI op2, label labl, flagsRegU icc) %{
9591 match(If cmp (CmpU op1 op2));
9592 predicate(UseCBCond);
9593 effect(USE labl, KILL icc);
9594
9595 size(4);
9596 ins_cost(BRANCH_COST);
9597 format %{ "CWB$cmp $op1,$op2,$labl\t! unsigned" %}
9598 ins_encode %{
9599 Label* L = $labl$$label;
9600 assert(__ use_cbcond(*L), "back to back cbcond");
9601 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L);
9602 %}
9603 ins_short_branch(1);
9604 ins_avoid_back_to_back(1);
9605 ins_pipe(cbcond_reg_reg);
9606 %}
9607
9608 instruct cmpU_imm_branch_short(cmpOpU cmp, iRegI op1, immI5 op2, label labl, flagsRegU icc) %{
9609 match(If cmp (CmpU op1 op2));
9610 predicate(UseCBCond);
9611 effect(USE labl, KILL icc);
9612
9613 size(4);
9614 ins_cost(BRANCH_COST);
9615 format %{ "CWB$cmp $op1,$op2,$labl\t! unsigned" %}
9616 ins_encode %{
9617 Label* L = $labl$$label;
9618 assert(__ use_cbcond(*L), "back to back cbcond");
9619 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$constant, *L);
9620 %}
9621 ins_short_branch(1);
9622 ins_avoid_back_to_back(1);
9623 ins_pipe(cbcond_reg_imm);
9624 %}
9625
9626 instruct cmpUL_reg_branch_short(cmpOpU cmp, iRegL op1, iRegL op2, label labl, flagsRegUL xcc) %{
9627 match(If cmp (CmpUL op1 op2));
9628 predicate(UseCBCond);
9629 effect(USE labl, KILL xcc);
9630
9631 size(4);
9632 ins_cost(BRANCH_COST);
9633 format %{ "CXB$cmp $op1,$op2,$labl\t! unsigned long" %}
9634 ins_encode %{
9635 Label* L = $labl$$label;
9636 assert(__ use_cbcond(*L), "back to back cbcond");
9637 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::xcc, $op1$$Register, $op2$$Register, *L);
9638 %}
9639 ins_short_branch(1);
9640 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9641 ins_pipe(cbcond_reg_reg);
9642 %}
9643
9644 instruct cmpUL_imm_branch_short(cmpOpU cmp, iRegL op1, immL5 op2, label labl, flagsRegUL xcc) %{
9645 match(If cmp (CmpUL op1 op2));
9646 predicate(UseCBCond);
9647 effect(USE labl, KILL xcc);
9648
9649 size(4);
9650 ins_cost(BRANCH_COST);
9651 format %{ "CXB$cmp $op1,$op2,$labl\t! unsigned long" %}
9652 ins_encode %{
9653 Label* L = $labl$$label;
9654 assert(__ use_cbcond(*L), "back to back cbcond");
9655 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::xcc, $op1$$Register, $op2$$constant, *L);
9656 %}
9657 ins_short_branch(1);
9658 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9659 ins_pipe(cbcond_reg_imm);
9660 %}
9661
9662 instruct cmpL_reg_branch_short(cmpOp cmp, iRegL op1, iRegL op2, label labl, flagsRegL xcc) %{
9663 match(If cmp (CmpL op1 op2));
9664 predicate(UseCBCond);
9665 effect(USE labl, KILL xcc);
9666
9667 size(4);
9668 ins_cost(BRANCH_COST);
9669 format %{ "CXB$cmp $op1,$op2,$labl\t! long" %}
9670 ins_encode %{
9671 Label* L = $labl$$label;
9672 assert(__ use_cbcond(*L), "back to back cbcond");
9673 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::xcc, $op1$$Register, $op2$$Register, *L);
9674 %}
9675 ins_short_branch(1);
9676 ins_avoid_back_to_back(1);
9677 ins_pipe(cbcond_reg_reg);
9678 %}
9679
9680 instruct cmpL_imm_branch_short(cmpOp cmp, iRegL op1, immL5 op2, label labl, flagsRegL xcc) %{
9681 match(If cmp (CmpL op1 op2));
9682 predicate(UseCBCond);
9683 effect(USE labl, KILL xcc);
9684
9685 size(4);
9686 ins_cost(BRANCH_COST);
9687 format %{ "CXB$cmp $op1,$op2,$labl\t! long" %}
9688 ins_encode %{
9689 Label* L = $labl$$label;
9690 assert(__ use_cbcond(*L), "back to back cbcond");
9691 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::xcc, $op1$$Register, $op2$$constant, *L);
9692 %}
9693 ins_short_branch(1);
9694 ins_avoid_back_to_back(1);
9695 ins_pipe(cbcond_reg_imm);
9696 %}
9697
9698 // Compare Pointers and branch
9699 instruct cmpP_reg_branch_short(cmpOpP cmp, iRegP op1, iRegP op2, label labl, flagsRegP pcc) %{
9700 match(If cmp (CmpP op1 op2));
9701 predicate(UseCBCond);
9702 effect(USE labl, KILL pcc);
9703
9704 size(4);
9705 ins_cost(BRANCH_COST);
9706 #ifdef _LP64
9707 format %{ "CXB$cmp $op1,$op2,$labl\t! ptr" %}
9708 #else
9709 format %{ "CWB$cmp $op1,$op2,$labl\t! ptr" %}
9710 #endif
9711 ins_encode %{
9712 Label* L = $labl$$label;
9713 assert(__ use_cbcond(*L), "back to back cbcond");
9714 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::ptr_cc, $op1$$Register, $op2$$Register, *L);
9715 %}
9716 ins_short_branch(1);
9717 ins_avoid_back_to_back(1);
9718 ins_pipe(cbcond_reg_reg);
9719 %}
9720
9721 instruct cmpP_null_branch_short(cmpOpP cmp, iRegP op1, immP0 null, label labl, flagsRegP pcc) %{
9722 match(If cmp (CmpP op1 null));
9723 predicate(UseCBCond);
9724 effect(USE labl, KILL pcc);
9725
9726 size(4);
9727 ins_cost(BRANCH_COST);
9728 #ifdef _LP64
9729 format %{ "CXB$cmp $op1,0,$labl\t! ptr" %}
9730 #else
9731 format %{ "CWB$cmp $op1,0,$labl\t! ptr" %}
9732 #endif
9733 ins_encode %{
9734 Label* L = $labl$$label;
9735 assert(__ use_cbcond(*L), "back to back cbcond");
9736 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::ptr_cc, $op1$$Register, G0, *L);
9737 %}
9738 ins_short_branch(1);
9739 ins_avoid_back_to_back(1);
9740 ins_pipe(cbcond_reg_reg);
9741 %}
9742
9743 instruct cmpN_reg_branch_short(cmpOp cmp, iRegN op1, iRegN op2, label labl, flagsReg icc) %{
9744 match(If cmp (CmpN op1 op2));
9745 predicate(UseCBCond);
9746 effect(USE labl, KILL icc);
9747
9748 size(4);
9749 ins_cost(BRANCH_COST);
9750 format %{ "CWB$cmp $op1,op2,$labl\t! compressed ptr" %}
9751 ins_encode %{
9752 Label* L = $labl$$label;
9753 assert(__ use_cbcond(*L), "back to back cbcond");
9754 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L);
9755 %}
9756 ins_short_branch(1);
9757 ins_avoid_back_to_back(1);
9758 ins_pipe(cbcond_reg_reg);
9759 %}
9760
9761 instruct cmpN_null_branch_short(cmpOp cmp, iRegN op1, immN0 null, label labl, flagsReg icc) %{
9762 match(If cmp (CmpN op1 null));
9763 predicate(UseCBCond);
9764 effect(USE labl, KILL icc);
9765
9766 size(4);
9767 ins_cost(BRANCH_COST);
9768 format %{ "CWB$cmp $op1,0,$labl\t! compressed ptr" %}
9769 ins_encode %{
9770 Label* L = $labl$$label;
9771 assert(__ use_cbcond(*L), "back to back cbcond");
9772 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, G0, *L);
9773 %}
9774 ins_short_branch(1);
9775 ins_avoid_back_to_back(1);
9776 ins_pipe(cbcond_reg_reg);
9777 %}
9778
9779 // Loop back branch
9780 instruct cmpI_reg_branchLoopEnd_short(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{
9781 match(CountedLoopEnd cmp (CmpI op1 op2));
9782 predicate(UseCBCond);
9783 effect(USE labl, KILL icc);
9784
9785 size(4);
9786 ins_cost(BRANCH_COST);
9787 format %{ "CWB$cmp $op1,$op2,$labl\t! Loop end" %}
9788 ins_encode %{
9789 Label* L = $labl$$label;
9790 assert(__ use_cbcond(*L), "back to back cbcond");
9791 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L);
9792 %}
9793 ins_short_branch(1);
9794 ins_avoid_back_to_back(1);
9795 ins_pipe(cbcond_reg_reg);
9796 %}
9797
9798 instruct cmpI_imm_branchLoopEnd_short(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{
9799 match(CountedLoopEnd cmp (CmpI op1 op2));
9800 predicate(UseCBCond);
9801 effect(USE labl, KILL icc);
9802
9803 size(4);
9804 ins_cost(BRANCH_COST);
9805 format %{ "CWB$cmp $op1,$op2,$labl\t! Loop end" %}
9806 ins_encode %{
9807 Label* L = $labl$$label;
9808 assert(__ use_cbcond(*L), "back to back cbcond");
9809 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$constant, *L);
9810 %}
9811 ins_short_branch(1);
9812 ins_avoid_back_to_back(1);
9813 ins_pipe(cbcond_reg_imm);
9814 %}
9815
9816 // Branch-on-register tests all 64 bits. We assume that values
9817 // in 64-bit registers always remains zero or sign extended
9818 // unless our code munges the high bits. Interrupts can chop
9819 // the high order bits to zero or sign at any time.
9820 instruct branchCon_regI(cmpOp_reg cmp, iRegI op1, immI0 zero, label labl) %{
9821 match(If cmp (CmpI op1 zero));
9822 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf));
9823 effect(USE labl);
9824
9825 size(8);
9826 ins_cost(BRANCH_COST);
9827 format %{ "BR$cmp $op1,$labl" %}
9828 ins_encode( enc_bpr( labl, cmp, op1 ) );
9829 ins_pipe(br_reg);
9830 %}
9831
9832 instruct branchCon_regP(cmpOp_reg cmp, iRegP op1, immP0 null, label labl) %{
9833 match(If cmp (CmpP op1 null));
9834 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf));
9835 effect(USE labl);
9836
9837 size(8);
9838 ins_cost(BRANCH_COST);
9839 format %{ "BR$cmp $op1,$labl" %}
9840 ins_encode( enc_bpr( labl, cmp, op1 ) );
9841 ins_pipe(br_reg);
9842 %}
9843
9844 instruct branchCon_regL(cmpOp_reg cmp, iRegL op1, immL0 zero, label labl) %{
9845 match(If cmp (CmpL op1 zero));
9846 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf));
9847 effect(USE labl);
9848
9849 size(8);
9850 ins_cost(BRANCH_COST);
9851 format %{ "BR$cmp $op1,$labl" %}
9852 ins_encode( enc_bpr( labl, cmp, op1 ) );
9853 ins_pipe(br_reg);
9854 %}
9855
9856
9857 // ============================================================================
9858 // Long Compare
9859 //
9860 // Currently we hold longs in 2 registers. Comparing such values efficiently
9861 // is tricky. The flavor of compare used depends on whether we are testing
9862 // for LT, LE, or EQ. For a simple LT test we can check just the sign bit.
9863 // The GE test is the negated LT test. The LE test can be had by commuting
9864 // the operands (yielding a GE test) and then negating; negate again for the
9865 // GT test. The EQ test is done by ORcc'ing the high and low halves, and the
9866 // NE test is negated from that.
9867
9868 // Due to a shortcoming in the ADLC, it mixes up expressions like:
9869 // (foo (CmpI (CmpL X Y) 0)) and (bar (CmpI (CmpL X 0L) 0)). Note the
9870 // difference between 'Y' and '0L'. The tree-matches for the CmpI sections
9871 // are collapsed internally in the ADLC's dfa-gen code. The match for
9872 // (CmpI (CmpL X Y) 0) is silently replaced with (CmpI (CmpL X 0L) 0) and the
9873 // foo match ends up with the wrong leaf. One fix is to not match both
9874 // reg-reg and reg-zero forms of long-compare. This is unfortunate because
9875 // both forms beat the trinary form of long-compare and both are very useful
9876 // on Intel which has so few registers.
9877
9878 instruct branchCon_long(cmpOp cmp, flagsRegL xcc, label labl) %{
9879 match(If cmp xcc);
9880 effect(USE labl);
9881
9882 size(8);
9883 ins_cost(BRANCH_COST);
9884 format %{ "BP$cmp $xcc,$labl" %}
9885 ins_encode %{
9886 Label* L = $labl$$label;
9887 Assembler::Predict predict_taken =
9888 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9889
9890 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L);
9891 __ delayed()->nop();
9892 %}
9893 ins_pipe(br_cc);
9894 %}
9895
9896 instruct branchConU_long(cmpOpU cmp, flagsRegUL xcc, label labl) %{
9897 match(If cmp xcc);
9898 effect(USE labl);
9899
9900 size(8);
9901 ins_cost(BRANCH_COST);
9902 format %{ "BP$cmp $xcc,$labl" %}
9903 ins_encode %{
9904 Label* L = $labl$$label;
9905 Assembler::Predict predict_taken =
9906 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9907
9908 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L);
9909 __ delayed()->nop();
9910 %}
9911 ins_avoid_back_to_back(AVOID_BEFORE);
9912 ins_pipe(br_cc);
9913 %}
9914
9915 // Manifest a CmpL3 result in an integer register. Very painful.
9916 // This is the test to avoid.
9917 instruct cmpL3_reg_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg ccr ) %{
9918 match(Set dst (CmpL3 src1 src2) );
9919 effect( KILL ccr );
9920 ins_cost(6*DEFAULT_COST);
9921 size(24);
9922 format %{ "CMP $src1,$src2\t\t! long\n"
9923 "\tBLT,a,pn done\n"
9924 "\tMOV -1,$dst\t! delay slot\n"
9925 "\tBGT,a,pn done\n"
9926 "\tMOV 1,$dst\t! delay slot\n"
9927 "\tCLR $dst\n"
9928 "done:" %}
9929 ins_encode( cmpl_flag(src1,src2,dst) );
9930 ins_pipe(cmpL_reg);
9931 %}
9932
9933 // Conditional move
9934 instruct cmovLL_reg(cmpOp cmp, flagsRegL xcc, iRegL dst, iRegL src) %{
9935 match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src)));
9936 ins_cost(150);
9937 format %{ "MOV$cmp $xcc,$src,$dst\t! long" %}
9938 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
9939 ins_pipe(ialu_reg);
9940 %}
9941
9942 instruct cmovLL_imm(cmpOp cmp, flagsRegL xcc, iRegL dst, immL0 src) %{
9943 match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src)));
9944 ins_cost(140);
9945 format %{ "MOV$cmp $xcc,$src,$dst\t! long" %}
9946 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) );
9947 ins_pipe(ialu_imm);
9948 %}
9949
9950 instruct cmovIL_reg(cmpOp cmp, flagsRegL xcc, iRegI dst, iRegI src) %{
9951 match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src)));
9952 ins_cost(150);
9953 format %{ "MOV$cmp $xcc,$src,$dst" %}
9954 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
9955 ins_pipe(ialu_reg);
9956 %}
9957
9958 instruct cmovIL_imm(cmpOp cmp, flagsRegL xcc, iRegI dst, immI11 src) %{
9959 match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src)));
9960 ins_cost(140);
9961 format %{ "MOV$cmp $xcc,$src,$dst" %}
9962 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) );
9963 ins_pipe(ialu_imm);
9964 %}
9965
9966 instruct cmovNL_reg(cmpOp cmp, flagsRegL xcc, iRegN dst, iRegN src) %{
9967 match(Set dst (CMoveN (Binary cmp xcc) (Binary dst src)));
9968 ins_cost(150);
9969 format %{ "MOV$cmp $xcc,$src,$dst" %}
9970 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
9971 ins_pipe(ialu_reg);
9972 %}
9973
9974 instruct cmovPL_reg(cmpOp cmp, flagsRegL xcc, iRegP dst, iRegP src) %{
9975 match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src)));
9976 ins_cost(150);
9977 format %{ "MOV$cmp $xcc,$src,$dst" %}
9978 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
9979 ins_pipe(ialu_reg);
9980 %}
9981
9982 instruct cmovPL_imm(cmpOp cmp, flagsRegL xcc, iRegP dst, immP0 src) %{
9983 match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src)));
9984 ins_cost(140);
9985 format %{ "MOV$cmp $xcc,$src,$dst" %}
9986 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) );
9987 ins_pipe(ialu_imm);
9988 %}
9989
9990 instruct cmovFL_reg(cmpOp cmp, flagsRegL xcc, regF dst, regF src) %{
9991 match(Set dst (CMoveF (Binary cmp xcc) (Binary dst src)));
9992 ins_cost(150);
9993 opcode(0x101);
9994 format %{ "FMOVS$cmp $xcc,$src,$dst" %}
9995 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::xcc)) );
9996 ins_pipe(int_conditional_float_move);
9997 %}
9998
9999 instruct cmovDL_reg(cmpOp cmp, flagsRegL xcc, regD dst, regD src) %{
10000 match(Set dst (CMoveD (Binary cmp xcc) (Binary dst src)));
10001 ins_cost(150);
10002 opcode(0x102);
10003 format %{ "FMOVD$cmp $xcc,$src,$dst" %}
10004 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::xcc)) );
10005 ins_pipe(int_conditional_float_move);
10006 %}
10007
10008 // ============================================================================
10009 // Safepoint Instruction
10010 instruct safePoint_poll(iRegP poll) %{
10011 match(SafePoint poll);
10012 effect(USE poll);
10013
10014 size(4);
10015 #ifdef _LP64
10016 format %{ "LDX [$poll],R_G0\t! Safepoint: poll for GC" %}
10017 #else
10018 format %{ "LDUW [$poll],R_G0\t! Safepoint: poll for GC" %}
10019 #endif
10020 ins_encode %{
10021 __ relocate(relocInfo::poll_type);
10022 __ ld_ptr($poll$$Register, 0, G0);
10023 %}
10024 ins_pipe(loadPollP);
10025 %}
10026
10027 // ============================================================================
10028 // Call Instructions
10029 // Call Java Static Instruction
10030 instruct CallStaticJavaDirect( method meth ) %{
10031 match(CallStaticJava);
10032 predicate(! ((CallStaticJavaNode*)n)->is_method_handle_invoke());
10033 effect(USE meth);
10034
10035 size(8);
10036 ins_cost(CALL_COST);
10037 format %{ "CALL,static ; NOP ==> " %}
10038 ins_encode( Java_Static_Call( meth ), call_epilog );
10039 ins_pipe(simple_call);
10040 %}
10041
10042 // Call Java Static Instruction (method handle version)
10043 instruct CallStaticJavaHandle(method meth, l7RegP l7_mh_SP_save) %{
10044 match(CallStaticJava);
10045 predicate(((CallStaticJavaNode*)n)->is_method_handle_invoke());
10046 effect(USE meth, KILL l7_mh_SP_save);
10047
10048 size(16);
10049 ins_cost(CALL_COST);
10050 format %{ "CALL,static/MethodHandle" %}
10051 ins_encode(preserve_SP, Java_Static_Call(meth), restore_SP, call_epilog);
10052 ins_pipe(simple_call);
10053 %}
10054
10055 // Call Java Dynamic Instruction
10056 instruct CallDynamicJavaDirect( method meth ) %{
10057 match(CallDynamicJava);
10058 effect(USE meth);
10059
10060 ins_cost(CALL_COST);
10061 format %{ "SET (empty),R_G5\n\t"
10062 "CALL,dynamic ; NOP ==> " %}
10063 ins_encode( Java_Dynamic_Call( meth ), call_epilog );
10064 ins_pipe(call);
10065 %}
10066
10067 // Call Runtime Instruction
10068 instruct CallRuntimeDirect(method meth, l7RegP l7) %{
10069 match(CallRuntime);
10070 effect(USE meth, KILL l7);
10071 ins_cost(CALL_COST);
10072 format %{ "CALL,runtime" %}
10073 ins_encode( Java_To_Runtime( meth ),
10074 call_epilog, adjust_long_from_native_call );
10075 ins_pipe(simple_call);
10076 %}
10077
10078 // Call runtime without safepoint - same as CallRuntime
10079 instruct CallLeafDirect(method meth, l7RegP l7) %{
10080 match(CallLeaf);
10081 effect(USE meth, KILL l7);
10082 ins_cost(CALL_COST);
10083 format %{ "CALL,runtime leaf" %}
10084 ins_encode( Java_To_Runtime( meth ),
10085 call_epilog,
10086 adjust_long_from_native_call );
10087 ins_pipe(simple_call);
10088 %}
10089
10090 // Call runtime without safepoint - same as CallLeaf
10091 instruct CallLeafNoFPDirect(method meth, l7RegP l7) %{
10092 match(CallLeafNoFP);
10093 effect(USE meth, KILL l7);
10094 ins_cost(CALL_COST);
10095 format %{ "CALL,runtime leaf nofp" %}
10096 ins_encode( Java_To_Runtime( meth ),
10097 call_epilog,
10098 adjust_long_from_native_call );
10099 ins_pipe(simple_call);
10100 %}
10101
10102 // Tail Call; Jump from runtime stub to Java code.
10103 // Also known as an 'interprocedural jump'.
10104 // Target of jump will eventually return to caller.
10105 // TailJump below removes the return address.
10106 instruct TailCalljmpInd(g3RegP jump_target, inline_cache_regP method_oop) %{
10107 match(TailCall jump_target method_oop );
10108
10109 ins_cost(CALL_COST);
10110 format %{ "Jmp $jump_target ; NOP \t! $method_oop holds method oop" %}
10111 ins_encode(form_jmpl(jump_target));
10112 ins_pipe(tail_call);
10113 %}
10114
10115
10116 // Return Instruction
10117 instruct Ret() %{
10118 match(Return);
10119
10120 // The epilogue node did the ret already.
10121 size(0);
10122 format %{ "! return" %}
10123 ins_encode();
10124 ins_pipe(empty);
10125 %}
10126
10127
10128 // Tail Jump; remove the return address; jump to target.
10129 // TailCall above leaves the return address around.
10130 // TailJump is used in only one place, the rethrow_Java stub (fancy_jump=2).
10131 // ex_oop (Exception Oop) is needed in %o0 at the jump. As there would be a
10132 // "restore" before this instruction (in Epilogue), we need to materialize it
10133 // in %i0.
10134 instruct tailjmpInd(g1RegP jump_target, i0RegP ex_oop) %{
10135 match( TailJump jump_target ex_oop );
10136 ins_cost(CALL_COST);
10137 format %{ "! discard R_O7\n\t"
10138 "Jmp $jump_target ; ADD O7,8,O1 \t! $ex_oop holds exc. oop" %}
10139 ins_encode(form_jmpl_set_exception_pc(jump_target));
10140 // opcode(Assembler::jmpl_op3, Assembler::arith_op);
10141 // The hack duplicates the exception oop into G3, so that CreateEx can use it there.
10142 // ins_encode( form3_rs1_simm13_rd( jump_target, 0x00, R_G0 ), move_return_pc_to_o1() );
10143 ins_pipe(tail_call);
10144 %}
10145
10146 // Create exception oop: created by stack-crawling runtime code.
10147 // Created exception is now available to this handler, and is setup
10148 // just prior to jumping to this handler. No code emitted.
10149 instruct CreateException( o0RegP ex_oop )
10150 %{
10151 match(Set ex_oop (CreateEx));
10152 ins_cost(0);
10153
10154 size(0);
10155 // use the following format syntax
10156 format %{ "! exception oop is in R_O0; no code emitted" %}
10157 ins_encode();
10158 ins_pipe(empty);
10159 %}
10160
10161
10162 // Rethrow exception:
10163 // The exception oop will come in the first argument position.
10164 // Then JUMP (not call) to the rethrow stub code.
10165 instruct RethrowException()
10166 %{
10167 match(Rethrow);
10168 ins_cost(CALL_COST);
10169
10170 // use the following format syntax
10171 format %{ "Jmp rethrow_stub" %}
10172 ins_encode(enc_rethrow);
10173 ins_pipe(tail_call);
10174 %}
10175
10176
10177 // Die now
10178 instruct ShouldNotReachHere( )
10179 %{
10180 match(Halt);
10181 ins_cost(CALL_COST);
10182
10183 size(4);
10184 // Use the following format syntax
10185 format %{ "ILLTRAP ; ShouldNotReachHere" %}
10186 ins_encode( form2_illtrap() );
10187 ins_pipe(tail_call);
10188 %}
10189
10190 // ============================================================================
10191 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass
10192 // array for an instance of the superklass. Set a hidden internal cache on a
10193 // hit (cache is checked with exposed code in gen_subtype_check()). Return
10194 // not zero for a miss or zero for a hit. The encoding ALSO sets flags.
10195 instruct partialSubtypeCheck( o0RegP index, o1RegP sub, o2RegP super, flagsRegP pcc, o7RegP o7 ) %{
10196 match(Set index (PartialSubtypeCheck sub super));
10197 effect( KILL pcc, KILL o7 );
10198 ins_cost(DEFAULT_COST*10);
10199 format %{ "CALL PartialSubtypeCheck\n\tNOP" %}
10200 ins_encode( enc_PartialSubtypeCheck() );
10201 ins_pipe(partial_subtype_check_pipe);
10202 %}
10203
10204 instruct partialSubtypeCheck_vs_zero( flagsRegP pcc, o1RegP sub, o2RegP super, immP0 zero, o0RegP idx, o7RegP o7 ) %{
10205 match(Set pcc (CmpP (PartialSubtypeCheck sub super) zero));
10206 effect( KILL idx, KILL o7 );
10207 ins_cost(DEFAULT_COST*10);
10208 format %{ "CALL PartialSubtypeCheck\n\tNOP\t# (sets condition codes)" %}
10209 ins_encode( enc_PartialSubtypeCheck() );
10210 ins_pipe(partial_subtype_check_pipe);
10211 %}
10212
10213
10214 // ============================================================================
10215 // inlined locking and unlocking
10216
10217 instruct cmpFastLock(flagsRegP pcc, iRegP object, o1RegP box, iRegP scratch2, o7RegP scratch ) %{
10218 match(Set pcc (FastLock object box));
10219
10220 effect(TEMP scratch2, USE_KILL box, KILL scratch);
10221 ins_cost(100);
10222
10223 format %{ "FASTLOCK $object,$box\t! kills $box,$scratch,$scratch2" %}
10224 ins_encode( Fast_Lock(object, box, scratch, scratch2) );
10225 ins_pipe(long_memory_op);
10226 %}
10227
10228
10229 instruct cmpFastUnlock(flagsRegP pcc, iRegP object, o1RegP box, iRegP scratch2, o7RegP scratch ) %{
10230 match(Set pcc (FastUnlock object box));
10231 effect(TEMP scratch2, USE_KILL box, KILL scratch);
10232 ins_cost(100);
10233
10234 format %{ "FASTUNLOCK $object,$box\t! kills $box,$scratch,$scratch2" %}
10235 ins_encode( Fast_Unlock(object, box, scratch, scratch2) );
10236 ins_pipe(long_memory_op);
10237 %}
10238
10239 // The encodings are generic.
10240 instruct clear_array(iRegX cnt, iRegP base, iRegX temp, Universe dummy, flagsReg ccr) %{
10241 predicate(!use_block_zeroing(n->in(2)) );
10242 match(Set dummy (ClearArray cnt base));
10243 effect(TEMP temp, KILL ccr);
10244 ins_cost(300);
10245 format %{ "MOV $cnt,$temp\n"
10246 "loop: SUBcc $temp,8,$temp\t! Count down a dword of bytes\n"
10247 " BRge loop\t\t! Clearing loop\n"
10248 " STX G0,[$base+$temp]\t! delay slot" %}
10249
10250 ins_encode %{
10251 // Compiler ensures base is doubleword aligned and cnt is count of doublewords
10252 Register nof_bytes_arg = $cnt$$Register;
10253 Register nof_bytes_tmp = $temp$$Register;
10254 Register base_pointer_arg = $base$$Register;
10255
10256 Label loop;
10257 __ mov(nof_bytes_arg, nof_bytes_tmp);
10258
10259 // Loop and clear, walking backwards through the array.
10260 // nof_bytes_tmp (if >0) is always the number of bytes to zero
10261 __ bind(loop);
10262 __ deccc(nof_bytes_tmp, 8);
10263 __ br(Assembler::greaterEqual, true, Assembler::pt, loop);
10264 __ delayed()-> stx(G0, base_pointer_arg, nof_bytes_tmp);
10265 // %%%% this mini-loop must not cross a cache boundary!
10266 %}
10267 ins_pipe(long_memory_op);
10268 %}
10269
10270 instruct clear_array_bis(g1RegX cnt, o0RegP base, Universe dummy, flagsReg ccr) %{
10271 predicate(use_block_zeroing(n->in(2)));
10272 match(Set dummy (ClearArray cnt base));
10273 effect(USE_KILL cnt, USE_KILL base, KILL ccr);
10274 ins_cost(300);
10275 format %{ "CLEAR [$base, $cnt]\t! ClearArray" %}
10276
10277 ins_encode %{
10278
10279 assert(MinObjAlignmentInBytes >= BytesPerLong, "need alternate implementation");
10280 Register to = $base$$Register;
10281 Register count = $cnt$$Register;
10282
10283 Label Ldone;
10284 __ nop(); // Separate short branches
10285 // Use BIS for zeroing (temp is not used).
10286 __ bis_zeroing(to, count, G0, Ldone);
10287 __ bind(Ldone);
10288
10289 %}
10290 ins_pipe(long_memory_op);
10291 %}
10292
10293 instruct clear_array_bis_2(g1RegX cnt, o0RegP base, iRegX tmp, Universe dummy, flagsReg ccr) %{
10294 predicate(use_block_zeroing(n->in(2)) && !Assembler::is_simm13((int)BlockZeroingLowLimit));
10295 match(Set dummy (ClearArray cnt base));
10296 effect(TEMP tmp, USE_KILL cnt, USE_KILL base, KILL ccr);
10297 ins_cost(300);
10298 format %{ "CLEAR [$base, $cnt]\t! ClearArray" %}
10299
10300 ins_encode %{
10301
10302 assert(MinObjAlignmentInBytes >= BytesPerLong, "need alternate implementation");
10303 Register to = $base$$Register;
10304 Register count = $cnt$$Register;
10305 Register temp = $tmp$$Register;
10306
10307 Label Ldone;
10308 __ nop(); // Separate short branches
10309 // Use BIS for zeroing
10310 __ bis_zeroing(to, count, temp, Ldone);
10311 __ bind(Ldone);
10312
10313 %}
10314 ins_pipe(long_memory_op);
10315 %}
10316
10317 instruct string_compare(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result,
10318 o7RegI tmp, flagsReg ccr) %{
10319 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10320 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL ccr, KILL tmp);
10321 ins_cost(300);
10322 format %{ "String Compare $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp" %}
10323 ins_encode( enc_String_Compare(str1, str2, cnt1, cnt2, result) );
10324 ins_pipe(long_memory_op);
10325 %}
10326
10327 instruct string_equals(o0RegP str1, o1RegP str2, g3RegI cnt, notemp_iRegI result,
10328 o7RegI tmp, flagsReg ccr) %{
10329 match(Set result (StrEquals (Binary str1 str2) cnt));
10330 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp, KILL ccr);
10331 ins_cost(300);
10332 format %{ "String Equals $str1,$str2,$cnt -> $result // KILL $tmp" %}
10333 ins_encode( enc_String_Equals(str1, str2, cnt, result) );
10334 ins_pipe(long_memory_op);
10335 %}
10336
10337 instruct array_equals(o0RegP ary1, o1RegP ary2, g3RegI tmp1, notemp_iRegI result,
10338 o7RegI tmp2, flagsReg ccr) %{
10339 match(Set result (AryEq ary1 ary2));
10340 effect(USE_KILL ary1, USE_KILL ary2, KILL tmp1, KILL tmp2, KILL ccr);
10341 ins_cost(300);
10342 format %{ "Array Equals $ary1,$ary2 -> $result // KILL $tmp1,$tmp2" %}
10343 ins_encode( enc_Array_Equals(ary1, ary2, tmp1, result));
10344 ins_pipe(long_memory_op);
10345 %}
10346
10347
10348 //---------- Zeros Count Instructions ------------------------------------------
10349
10350 instruct countLeadingZerosI(iRegIsafe dst, iRegI src, iRegI tmp, flagsReg cr) %{
10351 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported
10352 match(Set dst (CountLeadingZerosI src));
10353 effect(TEMP dst, TEMP tmp, KILL cr);
10354
10355 // x |= (x >> 1);
10356 // x |= (x >> 2);
10357 // x |= (x >> 4);
10358 // x |= (x >> 8);
10359 // x |= (x >> 16);
10360 // return (WORDBITS - popc(x));
10361 format %{ "SRL $src,1,$tmp\t! count leading zeros (int)\n\t"
10362 "SRL $src,0,$dst\t! 32-bit zero extend\n\t"
10363 "OR $dst,$tmp,$dst\n\t"
10364 "SRL $dst,2,$tmp\n\t"
10365 "OR $dst,$tmp,$dst\n\t"
10366 "SRL $dst,4,$tmp\n\t"
10367 "OR $dst,$tmp,$dst\n\t"
10368 "SRL $dst,8,$tmp\n\t"
10369 "OR $dst,$tmp,$dst\n\t"
10370 "SRL $dst,16,$tmp\n\t"
10371 "OR $dst,$tmp,$dst\n\t"
10372 "POPC $dst,$dst\n\t"
10373 "MOV 32,$tmp\n\t"
10374 "SUB $tmp,$dst,$dst" %}
10375 ins_encode %{
10376 Register Rdst = $dst$$Register;
10377 Register Rsrc = $src$$Register;
10378 Register Rtmp = $tmp$$Register;
10379 __ srl(Rsrc, 1, Rtmp);
10380 __ srl(Rsrc, 0, Rdst);
10381 __ or3(Rdst, Rtmp, Rdst);
10382 __ srl(Rdst, 2, Rtmp);
10383 __ or3(Rdst, Rtmp, Rdst);
10384 __ srl(Rdst, 4, Rtmp);
10385 __ or3(Rdst, Rtmp, Rdst);
10386 __ srl(Rdst, 8, Rtmp);
10387 __ or3(Rdst, Rtmp, Rdst);
10388 __ srl(Rdst, 16, Rtmp);
10389 __ or3(Rdst, Rtmp, Rdst);
10390 __ popc(Rdst, Rdst);
10391 __ mov(BitsPerInt, Rtmp);
10392 __ sub(Rtmp, Rdst, Rdst);
10393 %}
10394 ins_pipe(ialu_reg);
10395 %}
10396
10397 instruct countLeadingZerosL(iRegIsafe dst, iRegL src, iRegL tmp, flagsReg cr) %{
10398 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported
10399 match(Set dst (CountLeadingZerosL src));
10400 effect(TEMP dst, TEMP tmp, KILL cr);
10401
10402 // x |= (x >> 1);
10403 // x |= (x >> 2);
10404 // x |= (x >> 4);
10405 // x |= (x >> 8);
10406 // x |= (x >> 16);
10407 // x |= (x >> 32);
10408 // return (WORDBITS - popc(x));
10409 format %{ "SRLX $src,1,$tmp\t! count leading zeros (long)\n\t"
10410 "OR $src,$tmp,$dst\n\t"
10411 "SRLX $dst,2,$tmp\n\t"
10412 "OR $dst,$tmp,$dst\n\t"
10413 "SRLX $dst,4,$tmp\n\t"
10414 "OR $dst,$tmp,$dst\n\t"
10415 "SRLX $dst,8,$tmp\n\t"
10416 "OR $dst,$tmp,$dst\n\t"
10417 "SRLX $dst,16,$tmp\n\t"
10418 "OR $dst,$tmp,$dst\n\t"
10419 "SRLX $dst,32,$tmp\n\t"
10420 "OR $dst,$tmp,$dst\n\t"
10421 "POPC $dst,$dst\n\t"
10422 "MOV 64,$tmp\n\t"
10423 "SUB $tmp,$dst,$dst" %}
10424 ins_encode %{
10425 Register Rdst = $dst$$Register;
10426 Register Rsrc = $src$$Register;
10427 Register Rtmp = $tmp$$Register;
10428 __ srlx(Rsrc, 1, Rtmp);
10429 __ or3( Rsrc, Rtmp, Rdst);
10430 __ srlx(Rdst, 2, Rtmp);
10431 __ or3( Rdst, Rtmp, Rdst);
10432 __ srlx(Rdst, 4, Rtmp);
10433 __ or3( Rdst, Rtmp, Rdst);
10434 __ srlx(Rdst, 8, Rtmp);
10435 __ or3( Rdst, Rtmp, Rdst);
10436 __ srlx(Rdst, 16, Rtmp);
10437 __ or3( Rdst, Rtmp, Rdst);
10438 __ srlx(Rdst, 32, Rtmp);
10439 __ or3( Rdst, Rtmp, Rdst);
10440 __ popc(Rdst, Rdst);
10441 __ mov(BitsPerLong, Rtmp);
10442 __ sub(Rtmp, Rdst, Rdst);
10443 %}
10444 ins_pipe(ialu_reg);
10445 %}
10446
10447 instruct countTrailingZerosI(iRegIsafe dst, iRegI src, flagsReg cr) %{
10448 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported
10449 match(Set dst (CountTrailingZerosI src));
10450 effect(TEMP dst, KILL cr);
10451
10452 // return popc(~x & (x - 1));
10453 format %{ "SUB $src,1,$dst\t! count trailing zeros (int)\n\t"
10454 "ANDN $dst,$src,$dst\n\t"
10455 "SRL $dst,R_G0,$dst\n\t"
10456 "POPC $dst,$dst" %}
10457 ins_encode %{
10458 Register Rdst = $dst$$Register;
10459 Register Rsrc = $src$$Register;
10460 __ sub(Rsrc, 1, Rdst);
10461 __ andn(Rdst, Rsrc, Rdst);
10462 __ srl(Rdst, G0, Rdst);
10463 __ popc(Rdst, Rdst);
10464 %}
10465 ins_pipe(ialu_reg);
10466 %}
10467
10468 instruct countTrailingZerosL(iRegIsafe dst, iRegL src, flagsReg cr) %{
10469 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported
10470 match(Set dst (CountTrailingZerosL src));
10471 effect(TEMP dst, KILL cr);
10472
10473 // return popc(~x & (x - 1));
10474 format %{ "SUB $src,1,$dst\t! count trailing zeros (long)\n\t"
10475 "ANDN $dst,$src,$dst\n\t"
10476 "POPC $dst,$dst" %}
10477 ins_encode %{
10478 Register Rdst = $dst$$Register;
10479 Register Rsrc = $src$$Register;
10480 __ sub(Rsrc, 1, Rdst);
10481 __ andn(Rdst, Rsrc, Rdst);
10482 __ popc(Rdst, Rdst);
10483 %}
10484 ins_pipe(ialu_reg);
10485 %}
10486
10487
10488 //---------- Population Count Instructions -------------------------------------
10489
10490 instruct popCountI(iRegIsafe dst, iRegI src) %{
10491 predicate(UsePopCountInstruction);
10492 match(Set dst (PopCountI src));
10493
10494 format %{ "SRL $src, G0, $dst\t! clear upper word for 64 bit POPC\n\t"
10495 "POPC $dst, $dst" %}
10496 ins_encode %{
10497 __ srl($src$$Register, G0, $dst$$Register);
10498 __ popc($dst$$Register, $dst$$Register);
10499 %}
10500 ins_pipe(ialu_reg);
10501 %}
10502
10503 // Note: Long.bitCount(long) returns an int.
10504 instruct popCountL(iRegIsafe dst, iRegL src) %{
10505 predicate(UsePopCountInstruction);
10506 match(Set dst (PopCountL src));
10507
10508 format %{ "POPC $src, $dst" %}
10509 ins_encode %{
10510 __ popc($src$$Register, $dst$$Register);
10511 %}
10512 ins_pipe(ialu_reg);
10513 %}
10514
10515
10516 // ============================================================================
10517 //------------Bytes reverse--------------------------------------------------
10518
10519 instruct bytes_reverse_int(iRegI dst, stackSlotI src) %{
10520 match(Set dst (ReverseBytesI src));
10521
10522 // Op cost is artificially doubled to make sure that load or store
10523 // instructions are preferred over this one which requires a spill
10524 // onto a stack slot.
10525 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
10526 format %{ "LDUWA $src, $dst\t!asi=primary_little" %}
10527
10528 ins_encode %{
10529 __ set($src$$disp + STACK_BIAS, O7);
10530 __ lduwa($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10531 %}
10532 ins_pipe( iload_mem );
10533 %}
10534
10535 instruct bytes_reverse_long(iRegL dst, stackSlotL src) %{
10536 match(Set dst (ReverseBytesL src));
10537
10538 // Op cost is artificially doubled to make sure that load or store
10539 // instructions are preferred over this one which requires a spill
10540 // onto a stack slot.
10541 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
10542 format %{ "LDXA $src, $dst\t!asi=primary_little" %}
10543
10544 ins_encode %{
10545 __ set($src$$disp + STACK_BIAS, O7);
10546 __ ldxa($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10547 %}
10548 ins_pipe( iload_mem );
10549 %}
10550
10551 instruct bytes_reverse_unsigned_short(iRegI dst, stackSlotI src) %{
10552 match(Set dst (ReverseBytesUS src));
10553
10554 // Op cost is artificially doubled to make sure that load or store
10555 // instructions are preferred over this one which requires a spill
10556 // onto a stack slot.
10557 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
10558 format %{ "LDUHA $src, $dst\t!asi=primary_little\n\t" %}
10559
10560 ins_encode %{
10561 // the value was spilled as an int so bias the load
10562 __ set($src$$disp + STACK_BIAS + 2, O7);
10563 __ lduha($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10564 %}
10565 ins_pipe( iload_mem );
10566 %}
10567
10568 instruct bytes_reverse_short(iRegI dst, stackSlotI src) %{
10569 match(Set dst (ReverseBytesS src));
10570
10571 // Op cost is artificially doubled to make sure that load or store
10572 // instructions are preferred over this one which requires a spill
10573 // onto a stack slot.
10574 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
10575 format %{ "LDSHA $src, $dst\t!asi=primary_little\n\t" %}
10576
10577 ins_encode %{
10578 // the value was spilled as an int so bias the load
10579 __ set($src$$disp + STACK_BIAS + 2, O7);
10580 __ ldsha($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10581 %}
10582 ins_pipe( iload_mem );
10583 %}
10584
10585 // Load Integer reversed byte order
10586 instruct loadI_reversed(iRegI dst, indIndexMemory src) %{
10587 match(Set dst (ReverseBytesI (LoadI src)));
10588
10589 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
10590 size(4);
10591 format %{ "LDUWA $src, $dst\t!asi=primary_little" %}
10592
10593 ins_encode %{
10594 __ lduwa($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10595 %}
10596 ins_pipe(iload_mem);
10597 %}
10598
10599 // Load Long - aligned and reversed
10600 instruct loadL_reversed(iRegL dst, indIndexMemory src) %{
10601 match(Set dst (ReverseBytesL (LoadL src)));
10602
10603 ins_cost(MEMORY_REF_COST);
10604 size(4);
10605 format %{ "LDXA $src, $dst\t!asi=primary_little" %}
10606
10607 ins_encode %{
10608 __ ldxa($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10609 %}
10610 ins_pipe(iload_mem);
10611 %}
10612
10613 // Load unsigned short / char reversed byte order
10614 instruct loadUS_reversed(iRegI dst, indIndexMemory src) %{
10615 match(Set dst (ReverseBytesUS (LoadUS src)));
10616
10617 ins_cost(MEMORY_REF_COST);
10618 size(4);
10619 format %{ "LDUHA $src, $dst\t!asi=primary_little" %}
10620
10621 ins_encode %{
10622 __ lduha($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10623 %}
10624 ins_pipe(iload_mem);
10625 %}
10626
10627 // Load short reversed byte order
10628 instruct loadS_reversed(iRegI dst, indIndexMemory src) %{
10629 match(Set dst (ReverseBytesS (LoadS src)));
10630
10631 ins_cost(MEMORY_REF_COST);
10632 size(4);
10633 format %{ "LDSHA $src, $dst\t!asi=primary_little" %}
10634
10635 ins_encode %{
10636 __ ldsha($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10637 %}
10638 ins_pipe(iload_mem);
10639 %}
10640
10641 // Store Integer reversed byte order
10642 instruct storeI_reversed(indIndexMemory dst, iRegI src) %{
10643 match(Set dst (StoreI dst (ReverseBytesI src)));
10644
10645 ins_cost(MEMORY_REF_COST);
10646 size(4);
10647 format %{ "STWA $src, $dst\t!asi=primary_little" %}
10648
10649 ins_encode %{
10650 __ stwa($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE);
10651 %}
10652 ins_pipe(istore_mem_reg);
10653 %}
10654
10655 // Store Long reversed byte order
10656 instruct storeL_reversed(indIndexMemory dst, iRegL src) %{
10657 match(Set dst (StoreL dst (ReverseBytesL src)));
10658
10659 ins_cost(MEMORY_REF_COST);
10660 size(4);
10661 format %{ "STXA $src, $dst\t!asi=primary_little" %}
10662
10663 ins_encode %{
10664 __ stxa($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE);
10665 %}
10666 ins_pipe(istore_mem_reg);
10667 %}
10668
10669 // Store unsighed short/char reversed byte order
10670 instruct storeUS_reversed(indIndexMemory dst, iRegI src) %{
10671 match(Set dst (StoreC dst (ReverseBytesUS src)));
10672
10673 ins_cost(MEMORY_REF_COST);
10674 size(4);
10675 format %{ "STHA $src, $dst\t!asi=primary_little" %}
10676
10677 ins_encode %{
10678 __ stha($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE);
10679 %}
10680 ins_pipe(istore_mem_reg);
10681 %}
10682
10683 // Store short reversed byte order
10684 instruct storeS_reversed(indIndexMemory dst, iRegI src) %{
10685 match(Set dst (StoreC dst (ReverseBytesS src)));
10686
10687 ins_cost(MEMORY_REF_COST);
10688 size(4);
10689 format %{ "STHA $src, $dst\t!asi=primary_little" %}
10690
10691 ins_encode %{
10692 __ stha($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE);
10693 %}
10694 ins_pipe(istore_mem_reg);
10695 %}
10696
10697 // ====================VECTOR INSTRUCTIONS=====================================
10698
10699 // Load Aligned Packed values into a Double Register
10700 instruct loadV8(regD dst, memory mem) %{
10701 predicate(n->as_LoadVector()->memory_size() == 8);
10702 match(Set dst (LoadVector mem));
10703 ins_cost(MEMORY_REF_COST);
10704 size(4);
10705 format %{ "LDDF $mem,$dst\t! load vector (8 bytes)" %}
10706 ins_encode %{
10707 __ ldf(FloatRegisterImpl::D, $mem$$Address, as_DoubleFloatRegister($dst$$reg));
10708 %}
10709 ins_pipe(floadD_mem);
10710 %}
10711
10712 // Store Vector in Double register to memory
10713 instruct storeV8(memory mem, regD src) %{
10714 predicate(n->as_StoreVector()->memory_size() == 8);
10715 match(Set mem (StoreVector mem src));
10716 ins_cost(MEMORY_REF_COST);
10717 size(4);
10718 format %{ "STDF $src,$mem\t! store vector (8 bytes)" %}
10719 ins_encode %{
10720 __ stf(FloatRegisterImpl::D, as_DoubleFloatRegister($src$$reg), $mem$$Address);
10721 %}
10722 ins_pipe(fstoreD_mem_reg);
10723 %}
10724
10725 // Store Zero into vector in memory
10726 instruct storeV8B_zero(memory mem, immI0 zero) %{
10727 predicate(n->as_StoreVector()->memory_size() == 8);
10728 match(Set mem (StoreVector mem (ReplicateB zero)));
10729 ins_cost(MEMORY_REF_COST);
10730 size(4);
10731 format %{ "STX $zero,$mem\t! store zero vector (8 bytes)" %}
10732 ins_encode %{
10733 __ stx(G0, $mem$$Address);
10734 %}
10735 ins_pipe(fstoreD_mem_zero);
10736 %}
10737
10738 instruct storeV4S_zero(memory mem, immI0 zero) %{
10739 predicate(n->as_StoreVector()->memory_size() == 8);
10740 match(Set mem (StoreVector mem (ReplicateS zero)));
10741 ins_cost(MEMORY_REF_COST);
10742 size(4);
10743 format %{ "STX $zero,$mem\t! store zero vector (4 shorts)" %}
10744 ins_encode %{
10745 __ stx(G0, $mem$$Address);
10746 %}
10747 ins_pipe(fstoreD_mem_zero);
10748 %}
10749
10750 instruct storeV2I_zero(memory mem, immI0 zero) %{
10751 predicate(n->as_StoreVector()->memory_size() == 8);
10752 match(Set mem (StoreVector mem (ReplicateI zero)));
10753 ins_cost(MEMORY_REF_COST);
10754 size(4);
10755 format %{ "STX $zero,$mem\t! store zero vector (2 ints)" %}
10756 ins_encode %{
10757 __ stx(G0, $mem$$Address);
10758 %}
10759 ins_pipe(fstoreD_mem_zero);
10760 %}
10761
10762 instruct storeV2F_zero(memory mem, immF0 zero) %{
10763 predicate(n->as_StoreVector()->memory_size() == 8);
10764 match(Set mem (StoreVector mem (ReplicateF zero)));
10765 ins_cost(MEMORY_REF_COST);
10766 size(4);
10767 format %{ "STX $zero,$mem\t! store zero vector (2 floats)" %}
10768 ins_encode %{
10769 __ stx(G0, $mem$$Address);
10770 %}
10771 ins_pipe(fstoreD_mem_zero);
10772 %}
10773
10774 // Replicate scalar to packed byte values into Double register
10775 instruct Repl8B_reg(regD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
10776 predicate(n->as_Vector()->length() == 8 && UseVIS >= 3);
10777 match(Set dst (ReplicateB src));
10778 effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
10779 format %{ "SLLX $src,56,$tmp\n\t"
10780 "SRLX $tmp, 8,$tmp2\n\t"
10781 "OR $tmp,$tmp2,$tmp\n\t"
10782 "SRLX $tmp,16,$tmp2\n\t"
10783 "OR $tmp,$tmp2,$tmp\n\t"
10784 "SRLX $tmp,32,$tmp2\n\t"
10785 "OR $tmp,$tmp2,$tmp\t! replicate8B\n\t"
10786 "MOVXTOD $tmp,$dst\t! MoveL2D" %}
10787 ins_encode %{
10788 Register Rsrc = $src$$Register;
10789 Register Rtmp = $tmp$$Register;
10790 Register Rtmp2 = $tmp2$$Register;
10791 __ sllx(Rsrc, 56, Rtmp);
10792 __ srlx(Rtmp, 8, Rtmp2);
10793 __ or3 (Rtmp, Rtmp2, Rtmp);
10794 __ srlx(Rtmp, 16, Rtmp2);
10795 __ or3 (Rtmp, Rtmp2, Rtmp);
10796 __ srlx(Rtmp, 32, Rtmp2);
10797 __ or3 (Rtmp, Rtmp2, Rtmp);
10798 __ movxtod(Rtmp, as_DoubleFloatRegister($dst$$reg));
10799 %}
10800 ins_pipe(ialu_reg);
10801 %}
10802
10803 // Replicate scalar to packed byte values into Double stack
10804 instruct Repl8B_stk(stackSlotD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
10805 predicate(n->as_Vector()->length() == 8 && UseVIS < 3);
10806 match(Set dst (ReplicateB src));
10807 effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
10808 format %{ "SLLX $src,56,$tmp\n\t"
10809 "SRLX $tmp, 8,$tmp2\n\t"
10810 "OR $tmp,$tmp2,$tmp\n\t"
10811 "SRLX $tmp,16,$tmp2\n\t"
10812 "OR $tmp,$tmp2,$tmp\n\t"
10813 "SRLX $tmp,32,$tmp2\n\t"
10814 "OR $tmp,$tmp2,$tmp\t! replicate8B\n\t"
10815 "STX $tmp,$dst\t! regL to stkD" %}
10816 ins_encode %{
10817 Register Rsrc = $src$$Register;
10818 Register Rtmp = $tmp$$Register;
10819 Register Rtmp2 = $tmp2$$Register;
10820 __ sllx(Rsrc, 56, Rtmp);
10821 __ srlx(Rtmp, 8, Rtmp2);
10822 __ or3 (Rtmp, Rtmp2, Rtmp);
10823 __ srlx(Rtmp, 16, Rtmp2);
10824 __ or3 (Rtmp, Rtmp2, Rtmp);
10825 __ srlx(Rtmp, 32, Rtmp2);
10826 __ or3 (Rtmp, Rtmp2, Rtmp);
10827 __ set ($dst$$disp + STACK_BIAS, Rtmp2);
10828 __ stx (Rtmp, Rtmp2, $dst$$base$$Register);
10829 %}
10830 ins_pipe(ialu_reg);
10831 %}
10832
10833 // Replicate scalar constant to packed byte values in Double register
10834 instruct Repl8B_immI(regD dst, immI13 con, o7RegI tmp) %{
10835 predicate(n->as_Vector()->length() == 8);
10836 match(Set dst (ReplicateB con));
10837 effect(KILL tmp);
10838 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl8B($con)" %}
10839 ins_encode %{
10840 // XXX This is a quick fix for 6833573.
10841 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 8, 1)), $dst$$FloatRegister);
10842 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 8, 1)), $tmp$$Register);
10843 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
10844 %}
10845 ins_pipe(loadConFD);
10846 %}
10847
10848 // Replicate scalar to packed char/short values into Double register
10849 instruct Repl4S_reg(regD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
10850 predicate(n->as_Vector()->length() == 4 && UseVIS >= 3);
10851 match(Set dst (ReplicateS src));
10852 effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
10853 format %{ "SLLX $src,48,$tmp\n\t"
10854 "SRLX $tmp,16,$tmp2\n\t"
10855 "OR $tmp,$tmp2,$tmp\n\t"
10856 "SRLX $tmp,32,$tmp2\n\t"
10857 "OR $tmp,$tmp2,$tmp\t! replicate4S\n\t"
10858 "MOVXTOD $tmp,$dst\t! MoveL2D" %}
10859 ins_encode %{
10860 Register Rsrc = $src$$Register;
10861 Register Rtmp = $tmp$$Register;
10862 Register Rtmp2 = $tmp2$$Register;
10863 __ sllx(Rsrc, 48, Rtmp);
10864 __ srlx(Rtmp, 16, Rtmp2);
10865 __ or3 (Rtmp, Rtmp2, Rtmp);
10866 __ srlx(Rtmp, 32, Rtmp2);
10867 __ or3 (Rtmp, Rtmp2, Rtmp);
10868 __ movxtod(Rtmp, as_DoubleFloatRegister($dst$$reg));
10869 %}
10870 ins_pipe(ialu_reg);
10871 %}
10872
10873 // Replicate scalar to packed char/short values into Double stack
10874 instruct Repl4S_stk(stackSlotD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
10875 predicate(n->as_Vector()->length() == 4 && UseVIS < 3);
10876 match(Set dst (ReplicateS src));
10877 effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
10878 format %{ "SLLX $src,48,$tmp\n\t"
10879 "SRLX $tmp,16,$tmp2\n\t"
10880 "OR $tmp,$tmp2,$tmp\n\t"
10881 "SRLX $tmp,32,$tmp2\n\t"
10882 "OR $tmp,$tmp2,$tmp\t! replicate4S\n\t"
10883 "STX $tmp,$dst\t! regL to stkD" %}
10884 ins_encode %{
10885 Register Rsrc = $src$$Register;
10886 Register Rtmp = $tmp$$Register;
10887 Register Rtmp2 = $tmp2$$Register;
10888 __ sllx(Rsrc, 48, Rtmp);
10889 __ srlx(Rtmp, 16, Rtmp2);
10890 __ or3 (Rtmp, Rtmp2, Rtmp);
10891 __ srlx(Rtmp, 32, Rtmp2);
10892 __ or3 (Rtmp, Rtmp2, Rtmp);
10893 __ set ($dst$$disp + STACK_BIAS, Rtmp2);
10894 __ stx (Rtmp, Rtmp2, $dst$$base$$Register);
10895 %}
10896 ins_pipe(ialu_reg);
10897 %}
10898
10899 // Replicate scalar constant to packed char/short values in Double register
10900 instruct Repl4S_immI(regD dst, immI con, o7RegI tmp) %{
10901 predicate(n->as_Vector()->length() == 4);
10902 match(Set dst (ReplicateS con));
10903 effect(KILL tmp);
10904 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl4S($con)" %}
10905 ins_encode %{
10906 // XXX This is a quick fix for 6833573.
10907 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 4, 2)), $dst$$FloatRegister);
10908 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 4, 2)), $tmp$$Register);
10909 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
10910 %}
10911 ins_pipe(loadConFD);
10912 %}
10913
10914 // Replicate scalar to packed int values into Double register
10915 instruct Repl2I_reg(regD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
10916 predicate(n->as_Vector()->length() == 2 && UseVIS >= 3);
10917 match(Set dst (ReplicateI src));
10918 effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
10919 format %{ "SLLX $src,32,$tmp\n\t"
10920 "SRLX $tmp,32,$tmp2\n\t"
10921 "OR $tmp,$tmp2,$tmp\t! replicate2I\n\t"
10922 "MOVXTOD $tmp,$dst\t! MoveL2D" %}
10923 ins_encode %{
10924 Register Rsrc = $src$$Register;
10925 Register Rtmp = $tmp$$Register;
10926 Register Rtmp2 = $tmp2$$Register;
10927 __ sllx(Rsrc, 32, Rtmp);
10928 __ srlx(Rtmp, 32, Rtmp2);
10929 __ or3 (Rtmp, Rtmp2, Rtmp);
10930 __ movxtod(Rtmp, as_DoubleFloatRegister($dst$$reg));
10931 %}
10932 ins_pipe(ialu_reg);
10933 %}
10934
10935 // Replicate scalar to packed int values into Double stack
10936 instruct Repl2I_stk(stackSlotD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
10937 predicate(n->as_Vector()->length() == 2 && UseVIS < 3);
10938 match(Set dst (ReplicateI src));
10939 effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
10940 format %{ "SLLX $src,32,$tmp\n\t"
10941 "SRLX $tmp,32,$tmp2\n\t"
10942 "OR $tmp,$tmp2,$tmp\t! replicate2I\n\t"
10943 "STX $tmp,$dst\t! regL to stkD" %}
10944 ins_encode %{
10945 Register Rsrc = $src$$Register;
10946 Register Rtmp = $tmp$$Register;
10947 Register Rtmp2 = $tmp2$$Register;
10948 __ sllx(Rsrc, 32, Rtmp);
10949 __ srlx(Rtmp, 32, Rtmp2);
10950 __ or3 (Rtmp, Rtmp2, Rtmp);
10951 __ set ($dst$$disp + STACK_BIAS, Rtmp2);
10952 __ stx (Rtmp, Rtmp2, $dst$$base$$Register);
10953 %}
10954 ins_pipe(ialu_reg);
10955 %}
10956
10957 // Replicate scalar zero constant to packed int values in Double register
10958 instruct Repl2I_immI(regD dst, immI con, o7RegI tmp) %{
10959 predicate(n->as_Vector()->length() == 2);
10960 match(Set dst (ReplicateI con));
10961 effect(KILL tmp);
10962 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl2I($con)" %}
10963 ins_encode %{
10964 // XXX This is a quick fix for 6833573.
10965 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 2, 4)), $dst$$FloatRegister);
10966 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 2, 4)), $tmp$$Register);
10967 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
10968 %}
10969 ins_pipe(loadConFD);
10970 %}
10971
10972 // Replicate scalar to packed float values into Double stack
10973 instruct Repl2F_stk(stackSlotD dst, regF src) %{
10974 predicate(n->as_Vector()->length() == 2);
10975 match(Set dst (ReplicateF src));
10976 ins_cost(MEMORY_REF_COST*2);
10977 format %{ "STF $src,$dst.hi\t! packed2F\n\t"
10978 "STF $src,$dst.lo" %}
10979 opcode(Assembler::stf_op3);
10980 ins_encode(simple_form3_mem_reg(dst, src), form3_mem_plus_4_reg(dst, src));
10981 ins_pipe(fstoreF_stk_reg);
10982 %}
10983
10984 // Replicate scalar zero constant to packed float values in Double register
10985 instruct Repl2F_immF(regD dst, immF con, o7RegI tmp) %{
10986 predicate(n->as_Vector()->length() == 2);
10987 match(Set dst (ReplicateF con));
10988 effect(KILL tmp);
10989 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl2F($con)" %}
10990 ins_encode %{
10991 // XXX This is a quick fix for 6833573.
10992 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immF($con$$constant)), $dst$$FloatRegister);
10993 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immF($con$$constant)), $tmp$$Register);
10994 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
10995 %}
10996 ins_pipe(loadConFD);
10997 %}
10998
10999 //----------PEEPHOLE RULES-----------------------------------------------------
11000 // These must follow all instruction definitions as they use the names
11001 // defined in the instructions definitions.
11002 //
11003 // peepmatch ( root_instr_name [preceding_instruction]* );
11004 //
11005 // peepconstraint %{
11006 // (instruction_number.operand_name relational_op instruction_number.operand_name
11007 // [, ...] );
11008 // // instruction numbers are zero-based using left to right order in peepmatch
11009 //
11010 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
11011 // // provide an instruction_number.operand_name for each operand that appears
11012 // // in the replacement instruction's match rule
11013 //
11014 // ---------VM FLAGS---------------------------------------------------------
11015 //
11016 // All peephole optimizations can be turned off using -XX:-OptoPeephole
11017 //
11018 // Each peephole rule is given an identifying number starting with zero and
11019 // increasing by one in the order seen by the parser. An individual peephole
11020 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
11021 // on the command-line.
11022 //
11023 // ---------CURRENT LIMITATIONS----------------------------------------------
11024 //
11025 // Only match adjacent instructions in same basic block
11026 // Only equality constraints
11027 // Only constraints between operands, not (0.dest_reg == EAX_enc)
11028 // Only one replacement instruction
11029 //
11030 // ---------EXAMPLE----------------------------------------------------------
11031 //
11032 // // pertinent parts of existing instructions in architecture description
11033 // instruct movI(eRegI dst, eRegI src) %{
11034 // match(Set dst (CopyI src));
11035 // %}
11036 //
11037 // instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{
11038 // match(Set dst (AddI dst src));
11039 // effect(KILL cr);
11040 // %}
11041 //
11042 // // Change (inc mov) to lea
11043 // peephole %{
11044 // // increment preceeded by register-register move
11045 // peepmatch ( incI_eReg movI );
11046 // // require that the destination register of the increment
11047 // // match the destination register of the move
11048 // peepconstraint ( 0.dst == 1.dst );
11049 // // construct a replacement instruction that sets
11050 // // the destination to ( move's source register + one )
11051 // peepreplace ( incI_eReg_immI1( 0.dst 1.src 0.src ) );
11052 // %}
11053 //
11054
11055 // // Change load of spilled value to only a spill
11056 // instruct storeI(memory mem, eRegI src) %{
11057 // match(Set mem (StoreI mem src));
11058 // %}
11059 //
11060 // instruct loadI(eRegI dst, memory mem) %{
11061 // match(Set dst (LoadI mem));
11062 // %}
11063 //
11064 // peephole %{
11065 // peepmatch ( loadI storeI );
11066 // peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem );
11067 // peepreplace ( storeI( 1.mem 1.mem 1.src ) );
11068 // %}
11069
11070 //----------SMARTSPILL RULES---------------------------------------------------
11071 // These must follow all instruction definitions as they use the names
11072 // defined in the instructions definitions.
11073 //
11074 // SPARC will probably not have any of these rules due to RISC instruction set.
11075
11076 //----------PIPELINE-----------------------------------------------------------
11077 // Rules which define the behavior of the target architectures pipeline.