1 //
2 // Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved.
3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 //
5 // This code is free software; you can redistribute it and/or modify it
6 // under the terms of the GNU General Public License version 2 only, as
7 // published by the Free Software Foundation.
8 //
9 // This code is distributed in the hope that it will be useful, but WITHOUT
10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 // version 2 for more details (a copy is included in the LICENSE file that
13 // accompanied this code).
14 //
15 // You should have received a copy of the GNU General Public License version
16 // 2 along with this work; if not, write to the Free Software Foundation,
17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 //
19 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 // or visit www.oracle.com if you need additional information or have any
21 // questions.
22 //
23 //
24
25 // X86 Architecture Description File
26
27 //----------REGISTER DEFINITION BLOCK------------------------------------------
28 // This information is used by the matcher and the register allocator to
29 // describe individual registers and classes of registers within the target
30 // archtecture.
31
32 register %{
33 //----------Architecture Description Register Definitions----------------------
34 // General Registers
35 // "reg_def" name ( register save type, C convention save type,
36 // ideal register type, encoding );
37 // Register Save Types:
38 //
39 // NS = No-Save: The register allocator assumes that these registers
40 // can be used without saving upon entry to the method, &
41 // that they do not need to be saved at call sites.
42 //
43 // SOC = Save-On-Call: The register allocator assumes that these registers
44 // can be used without saving upon entry to the method,
45 // but that they must be saved at call sites.
46 //
47 // SOE = Save-On-Entry: The register allocator assumes that these registers
48 // must be saved before using them upon entry to the
49 // method, but they do not need to be saved at call
50 // sites.
51 //
52 // AS = Always-Save: The register allocator assumes that these registers
53 // must be saved before using them upon entry to the
54 // method, & that they must be saved at call sites.
55 //
56 // Ideal Register Type is used to determine how to save & restore a
57 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
58 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
59 //
60 // The encoding number is the actual bit-pattern placed into the opcodes.
61
62 // General Registers
63 // Previously set EBX, ESI, and EDI as save-on-entry for java code
64 // Turn off SOE in java-code due to frequent use of uncommon-traps.
65 // Now that allocator is better, turn on ESI and EDI as SOE registers.
66
67 reg_def EBX(SOC, SOE, Op_RegI, 3, rbx->as_VMReg());
68 reg_def ECX(SOC, SOC, Op_RegI, 1, rcx->as_VMReg());
69 reg_def ESI(SOC, SOE, Op_RegI, 6, rsi->as_VMReg());
70 reg_def EDI(SOC, SOE, Op_RegI, 7, rdi->as_VMReg());
71 // now that adapter frames are gone EBP is always saved and restored by the prolog/epilog code
72 reg_def EBP(NS, SOE, Op_RegI, 5, rbp->as_VMReg());
73 reg_def EDX(SOC, SOC, Op_RegI, 2, rdx->as_VMReg());
74 reg_def EAX(SOC, SOC, Op_RegI, 0, rax->as_VMReg());
75 reg_def ESP( NS, NS, Op_RegI, 4, rsp->as_VMReg());
76
77 // Float registers. We treat TOS/FPR0 special. It is invisible to the
78 // allocator, and only shows up in the encodings.
79 reg_def FPR0L( SOC, SOC, Op_RegF, 0, VMRegImpl::Bad());
80 reg_def FPR0H( SOC, SOC, Op_RegF, 0, VMRegImpl::Bad());
81 // Ok so here's the trick FPR1 is really st(0) except in the midst
82 // of emission of assembly for a machnode. During the emission the fpu stack
83 // is pushed making FPR1 == st(1) temporarily. However at any safepoint
84 // the stack will not have this element so FPR1 == st(0) from the
85 // oopMap viewpoint. This same weirdness with numbering causes
86 // instruction encoding to have to play games with the register
87 // encode to correct for this 0/1 issue. See MachSpillCopyNode::implementation
88 // where it does flt->flt moves to see an example
89 //
90 reg_def FPR1L( SOC, SOC, Op_RegF, 1, as_FloatRegister(0)->as_VMReg());
91 reg_def FPR1H( SOC, SOC, Op_RegF, 1, as_FloatRegister(0)->as_VMReg()->next());
92 reg_def FPR2L( SOC, SOC, Op_RegF, 2, as_FloatRegister(1)->as_VMReg());
93 reg_def FPR2H( SOC, SOC, Op_RegF, 2, as_FloatRegister(1)->as_VMReg()->next());
94 reg_def FPR3L( SOC, SOC, Op_RegF, 3, as_FloatRegister(2)->as_VMReg());
95 reg_def FPR3H( SOC, SOC, Op_RegF, 3, as_FloatRegister(2)->as_VMReg()->next());
96 reg_def FPR4L( SOC, SOC, Op_RegF, 4, as_FloatRegister(3)->as_VMReg());
97 reg_def FPR4H( SOC, SOC, Op_RegF, 4, as_FloatRegister(3)->as_VMReg()->next());
98 reg_def FPR5L( SOC, SOC, Op_RegF, 5, as_FloatRegister(4)->as_VMReg());
99 reg_def FPR5H( SOC, SOC, Op_RegF, 5, as_FloatRegister(4)->as_VMReg()->next());
100 reg_def FPR6L( SOC, SOC, Op_RegF, 6, as_FloatRegister(5)->as_VMReg());
101 reg_def FPR6H( SOC, SOC, Op_RegF, 6, as_FloatRegister(5)->as_VMReg()->next());
102 reg_def FPR7L( SOC, SOC, Op_RegF, 7, as_FloatRegister(6)->as_VMReg());
103 reg_def FPR7H( SOC, SOC, Op_RegF, 7, as_FloatRegister(6)->as_VMReg()->next());
104
105 // Specify priority of register selection within phases of register
106 // allocation. Highest priority is first. A useful heuristic is to
107 // give registers a low priority when they are required by machine
108 // instructions, like EAX and EDX. Registers which are used as
109 // pairs must fall on an even boundary (witness the FPR#L's in this list).
110 // For the Intel integer registers, the equivalent Long pairs are
111 // EDX:EAX, EBX:ECX, and EDI:EBP.
112 alloc_class chunk0( ECX, EBX, EBP, EDI, EAX, EDX, ESI, ESP,
113 FPR0L, FPR0H, FPR1L, FPR1H, FPR2L, FPR2H,
114 FPR3L, FPR3H, FPR4L, FPR4H, FPR5L, FPR5H,
115 FPR6L, FPR6H, FPR7L, FPR7H );
116
117
118 //----------Architecture Description Register Classes--------------------------
119 // Several register classes are automatically defined based upon information in
120 // this architecture description.
121 // 1) reg_class inline_cache_reg ( /* as def'd in frame section */ )
122 // 2) reg_class compiler_method_oop_reg ( /* as def'd in frame section */ )
123 // 2) reg_class interpreter_method_oop_reg ( /* as def'd in frame section */ )
124 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
125 //
126 // Class for all registers
127 reg_class any_reg(EAX, EDX, EBP, EDI, ESI, ECX, EBX, ESP);
128 // Class for general registers
129 reg_class int_reg(EAX, EDX, EBP, EDI, ESI, ECX, EBX);
130 // Class for general registers which may be used for implicit null checks on win95
131 // Also safe for use by tailjump. We don't want to allocate in rbp,
132 reg_class int_reg_no_rbp(EAX, EDX, EDI, ESI, ECX, EBX);
133 // Class of "X" registers
134 reg_class int_x_reg(EBX, ECX, EDX, EAX);
135 // Class of registers that can appear in an address with no offset.
136 // EBP and ESP require an extra instruction byte for zero offset.
137 // Used in fast-unlock
138 reg_class p_reg(EDX, EDI, ESI, EBX);
139 // Class for general registers not including ECX
140 reg_class ncx_reg(EAX, EDX, EBP, EDI, ESI, EBX);
141 // Class for general registers not including EAX
142 reg_class nax_reg(EDX, EDI, ESI, ECX, EBX);
143 // Class for general registers not including EAX or EBX.
144 reg_class nabx_reg(EDX, EDI, ESI, ECX, EBP);
145 // Class of EAX (for multiply and divide operations)
146 reg_class eax_reg(EAX);
147 // Class of EBX (for atomic add)
148 reg_class ebx_reg(EBX);
149 // Class of ECX (for shift and JCXZ operations and cmpLTMask)
150 reg_class ecx_reg(ECX);
151 // Class of EDX (for multiply and divide operations)
152 reg_class edx_reg(EDX);
153 // Class of EDI (for synchronization)
154 reg_class edi_reg(EDI);
155 // Class of ESI (for synchronization)
156 reg_class esi_reg(ESI);
157 // Singleton class for interpreter's stack pointer
158 reg_class ebp_reg(EBP);
159 // Singleton class for stack pointer
160 reg_class sp_reg(ESP);
161 // Singleton class for instruction pointer
162 // reg_class ip_reg(EIP);
163 // Class of integer register pairs
164 reg_class long_reg( EAX,EDX, ECX,EBX, EBP,EDI );
165 // Class of integer register pairs that aligns with calling convention
166 reg_class eadx_reg( EAX,EDX );
167 reg_class ebcx_reg( ECX,EBX );
168 // Not AX or DX, used in divides
169 reg_class nadx_reg( EBX,ECX,ESI,EDI,EBP );
170
171 // Floating point registers. Notice FPR0 is not a choice.
172 // FPR0 is not ever allocated; we use clever encodings to fake
173 // a 2-address instructions out of Intels FP stack.
174 reg_class fp_flt_reg( FPR1L,FPR2L,FPR3L,FPR4L,FPR5L,FPR6L,FPR7L );
175
176 reg_class fp_dbl_reg( FPR1L,FPR1H, FPR2L,FPR2H, FPR3L,FPR3H,
177 FPR4L,FPR4H, FPR5L,FPR5H, FPR6L,FPR6H,
178 FPR7L,FPR7H );
179
180 reg_class fp_flt_reg0( FPR1L );
181 reg_class fp_dbl_reg0( FPR1L,FPR1H );
182 reg_class fp_dbl_reg1( FPR2L,FPR2H );
183 reg_class fp_dbl_notreg0( FPR2L,FPR2H, FPR3L,FPR3H, FPR4L,FPR4H,
184 FPR5L,FPR5H, FPR6L,FPR6H, FPR7L,FPR7H );
185
186 %}
187
188
189 //----------SOURCE BLOCK-------------------------------------------------------
190 // This is a block of C++ code which provides values, functions, and
191 // definitions necessary in the rest of the architecture description
192 source_hpp %{
193 // Must be visible to the DFA in dfa_x86_32.cpp
194 extern bool is_operand_hi32_zero(Node* n);
195 %}
196
197 source %{
198 #define RELOC_IMM32 Assembler::imm_operand
199 #define RELOC_DISP32 Assembler::disp32_operand
200
201 #define __ _masm.
202
203 // How to find the high register of a Long pair, given the low register
204 #define HIGH_FROM_LOW(x) ((x)+2)
205
206 // These masks are used to provide 128-bit aligned bitmasks to the XMM
207 // instructions, to allow sign-masking or sign-bit flipping. They allow
208 // fast versions of NegF/NegD and AbsF/AbsD.
209
210 // Note: 'double' and 'long long' have 32-bits alignment on x86.
211 static jlong* double_quadword(jlong *adr, jlong lo, jlong hi) {
212 // Use the expression (adr)&(~0xF) to provide 128-bits aligned address
213 // of 128-bits operands for SSE instructions.
214 jlong *operand = (jlong*)(((uintptr_t)adr)&((uintptr_t)(~0xF)));
215 // Store the value to a 128-bits operand.
216 operand[0] = lo;
217 operand[1] = hi;
218 return operand;
219 }
220
221 // Buffer for 128-bits masks used by SSE instructions.
222 static jlong fp_signmask_pool[(4+1)*2]; // 4*128bits(data) + 128bits(alignment)
223
224 // Static initialization during VM startup.
225 static jlong *float_signmask_pool = double_quadword(&fp_signmask_pool[1*2], CONST64(0x7FFFFFFF7FFFFFFF), CONST64(0x7FFFFFFF7FFFFFFF));
226 static jlong *double_signmask_pool = double_quadword(&fp_signmask_pool[2*2], CONST64(0x7FFFFFFFFFFFFFFF), CONST64(0x7FFFFFFFFFFFFFFF));
227 static jlong *float_signflip_pool = double_quadword(&fp_signmask_pool[3*2], CONST64(0x8000000080000000), CONST64(0x8000000080000000));
228 static jlong *double_signflip_pool = double_quadword(&fp_signmask_pool[4*2], CONST64(0x8000000000000000), CONST64(0x8000000000000000));
229
230 // Offset hacking within calls.
231 static int pre_call_resets_size() {
232 int size = 0;
233 Compile* C = Compile::current();
234 if (C->in_24_bit_fp_mode()) {
235 size += 6; // fldcw
236 }
237 if (C->max_vector_size() > 16) {
238 size += 3; // vzeroupper
239 }
240 return size;
241 }
242
243 static int preserve_SP_size() {
244 return 2; // op, rm(reg/reg)
245 }
246
247 // !!!!! Special hack to get all type of calls to specify the byte offset
248 // from the start of the call to the point where the return address
249 // will point.
250 int MachCallStaticJavaNode::ret_addr_offset() {
251 int offset = 5 + pre_call_resets_size(); // 5 bytes from start of call to where return address points
252 if (_method_handle_invoke)
253 offset += preserve_SP_size();
254 return offset;
255 }
256
257 int MachCallDynamicJavaNode::ret_addr_offset() {
258 return 10 + pre_call_resets_size(); // 10 bytes from start of call to where return address points
259 }
260
261 static int sizeof_FFree_Float_Stack_All = -1;
262
263 int MachCallRuntimeNode::ret_addr_offset() {
264 assert(sizeof_FFree_Float_Stack_All != -1, "must have been emitted already");
265 return sizeof_FFree_Float_Stack_All + 5 + pre_call_resets_size();
266 }
267
268 // Indicate if the safepoint node needs the polling page as an input.
269 // Since x86 does have absolute addressing, it doesn't.
270 bool SafePointNode::needs_polling_address_input() {
271 return false;
272 }
273
274 //
275 // Compute padding required for nodes which need alignment
276 //
277
278 // The address of the call instruction needs to be 4-byte aligned to
279 // ensure that it does not span a cache line so that it can be patched.
280 int CallStaticJavaDirectNode::compute_padding(int current_offset) const {
281 current_offset += pre_call_resets_size(); // skip fldcw, if any
282 current_offset += 1; // skip call opcode byte
283 return round_to(current_offset, alignment_required()) - current_offset;
284 }
285
286 // The address of the call instruction needs to be 4-byte aligned to
287 // ensure that it does not span a cache line so that it can be patched.
288 int CallStaticJavaHandleNode::compute_padding(int current_offset) const {
289 current_offset += pre_call_resets_size(); // skip fldcw, if any
290 current_offset += preserve_SP_size(); // skip mov rbp, rsp
291 current_offset += 1; // skip call opcode byte
292 return round_to(current_offset, alignment_required()) - current_offset;
293 }
294
295 // The address of the call instruction needs to be 4-byte aligned to
296 // ensure that it does not span a cache line so that it can be patched.
297 int CallDynamicJavaDirectNode::compute_padding(int current_offset) const {
298 current_offset += pre_call_resets_size(); // skip fldcw, if any
299 current_offset += 5; // skip MOV instruction
300 current_offset += 1; // skip call opcode byte
301 return round_to(current_offset, alignment_required()) - current_offset;
302 }
303
304 // EMIT_RM()
305 void emit_rm(CodeBuffer &cbuf, int f1, int f2, int f3) {
306 unsigned char c = (unsigned char)((f1 << 6) | (f2 << 3) | f3);
307 cbuf.insts()->emit_int8(c);
308 }
309
310 // EMIT_CC()
311 void emit_cc(CodeBuffer &cbuf, int f1, int f2) {
312 unsigned char c = (unsigned char)( f1 | f2 );
313 cbuf.insts()->emit_int8(c);
314 }
315
316 // EMIT_OPCODE()
317 void emit_opcode(CodeBuffer &cbuf, int code) {
318 cbuf.insts()->emit_int8((unsigned char) code);
319 }
320
321 // EMIT_OPCODE() w/ relocation information
322 void emit_opcode(CodeBuffer &cbuf, int code, relocInfo::relocType reloc, int offset = 0) {
323 cbuf.relocate(cbuf.insts_mark() + offset, reloc);
324 emit_opcode(cbuf, code);
325 }
326
327 // EMIT_D8()
328 void emit_d8(CodeBuffer &cbuf, int d8) {
329 cbuf.insts()->emit_int8((unsigned char) d8);
330 }
331
332 // EMIT_D16()
333 void emit_d16(CodeBuffer &cbuf, int d16) {
334 cbuf.insts()->emit_int16(d16);
335 }
336
337 // EMIT_D32()
338 void emit_d32(CodeBuffer &cbuf, int d32) {
339 cbuf.insts()->emit_int32(d32);
340 }
341
342 // emit 32 bit value and construct relocation entry from relocInfo::relocType
343 void emit_d32_reloc(CodeBuffer &cbuf, int d32, relocInfo::relocType reloc,
344 int format) {
345 cbuf.relocate(cbuf.insts_mark(), reloc, format);
346 cbuf.insts()->emit_int32(d32);
347 }
348
349 // emit 32 bit value and construct relocation entry from RelocationHolder
350 void emit_d32_reloc(CodeBuffer &cbuf, int d32, RelocationHolder const& rspec,
351 int format) {
352 #ifdef ASSERT
353 if (rspec.reloc()->type() == relocInfo::oop_type && d32 != 0 && d32 != (int)Universe::non_oop_word()) {
354 assert(oop(d32)->is_oop() && (ScavengeRootsInCode || !oop(d32)->is_scavengable()), "cannot embed scavengable oops in code");
355 }
356 #endif
357 cbuf.relocate(cbuf.insts_mark(), rspec, format);
358 cbuf.insts()->emit_int32(d32);
359 }
360
361 // Access stack slot for load or store
362 void store_to_stackslot(CodeBuffer &cbuf, int opcode, int rm_field, int disp) {
363 emit_opcode( cbuf, opcode ); // (e.g., FILD [ESP+src])
364 if( -128 <= disp && disp <= 127 ) {
365 emit_rm( cbuf, 0x01, rm_field, ESP_enc ); // R/M byte
366 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte
367 emit_d8 (cbuf, disp); // Displacement // R/M byte
368 } else {
369 emit_rm( cbuf, 0x02, rm_field, ESP_enc ); // R/M byte
370 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte
371 emit_d32(cbuf, disp); // Displacement // R/M byte
372 }
373 }
374
375 // rRegI ereg, memory mem) %{ // emit_reg_mem
376 void encode_RegMem( CodeBuffer &cbuf, int reg_encoding, int base, int index, int scale, int displace, bool displace_is_oop ) {
377 // There is no index & no scale, use form without SIB byte
378 if ((index == 0x4) &&
379 (scale == 0) && (base != ESP_enc)) {
380 // If no displacement, mode is 0x0; unless base is [EBP]
381 if ( (displace == 0) && (base != EBP_enc) ) {
382 emit_rm(cbuf, 0x0, reg_encoding, base);
383 }
384 else { // If 8-bit displacement, mode 0x1
385 if ((displace >= -128) && (displace <= 127)
386 && !(displace_is_oop) ) {
387 emit_rm(cbuf, 0x1, reg_encoding, base);
388 emit_d8(cbuf, displace);
389 }
390 else { // If 32-bit displacement
391 if (base == -1) { // Special flag for absolute address
392 emit_rm(cbuf, 0x0, reg_encoding, 0x5);
393 // (manual lies; no SIB needed here)
394 if ( displace_is_oop ) {
395 emit_d32_reloc(cbuf, displace, relocInfo::oop_type, 1);
396 } else {
397 emit_d32 (cbuf, displace);
398 }
399 }
400 else { // Normal base + offset
401 emit_rm(cbuf, 0x2, reg_encoding, base);
402 if ( displace_is_oop ) {
403 emit_d32_reloc(cbuf, displace, relocInfo::oop_type, 1);
404 } else {
405 emit_d32 (cbuf, displace);
406 }
407 }
408 }
409 }
410 }
411 else { // Else, encode with the SIB byte
412 // If no displacement, mode is 0x0; unless base is [EBP]
413 if (displace == 0 && (base != EBP_enc)) { // If no displacement
414 emit_rm(cbuf, 0x0, reg_encoding, 0x4);
415 emit_rm(cbuf, scale, index, base);
416 }
417 else { // If 8-bit displacement, mode 0x1
418 if ((displace >= -128) && (displace <= 127)
419 && !(displace_is_oop) ) {
420 emit_rm(cbuf, 0x1, reg_encoding, 0x4);
421 emit_rm(cbuf, scale, index, base);
422 emit_d8(cbuf, displace);
423 }
424 else { // If 32-bit displacement
425 if (base == 0x04 ) {
426 emit_rm(cbuf, 0x2, reg_encoding, 0x4);
427 emit_rm(cbuf, scale, index, 0x04);
428 } else {
429 emit_rm(cbuf, 0x2, reg_encoding, 0x4);
430 emit_rm(cbuf, scale, index, base);
431 }
432 if ( displace_is_oop ) {
433 emit_d32_reloc(cbuf, displace, relocInfo::oop_type, 1);
434 } else {
435 emit_d32 (cbuf, displace);
436 }
437 }
438 }
439 }
440 }
441
442
443 void encode_Copy( CodeBuffer &cbuf, int dst_encoding, int src_encoding ) {
444 if( dst_encoding == src_encoding ) {
445 // reg-reg copy, use an empty encoding
446 } else {
447 emit_opcode( cbuf, 0x8B );
448 emit_rm(cbuf, 0x3, dst_encoding, src_encoding );
449 }
450 }
451
452 void emit_cmpfp_fixup(MacroAssembler& _masm) {
453 Label exit;
454 __ jccb(Assembler::noParity, exit);
455 __ pushf();
456 //
457 // comiss/ucomiss instructions set ZF,PF,CF flags and
458 // zero OF,AF,SF for NaN values.
459 // Fixup flags by zeroing ZF,PF so that compare of NaN
460 // values returns 'less than' result (CF is set).
461 // Leave the rest of flags unchanged.
462 //
463 // 7 6 5 4 3 2 1 0
464 // |S|Z|r|A|r|P|r|C| (r - reserved bit)
465 // 0 0 1 0 1 0 1 1 (0x2B)
466 //
467 __ andl(Address(rsp, 0), 0xffffff2b);
468 __ popf();
469 __ bind(exit);
470 }
471
472 void emit_cmpfp3(MacroAssembler& _masm, Register dst) {
473 Label done;
474 __ movl(dst, -1);
475 __ jcc(Assembler::parity, done);
476 __ jcc(Assembler::below, done);
477 __ setb(Assembler::notEqual, dst);
478 __ movzbl(dst, dst);
479 __ bind(done);
480 }
481
482
483 //=============================================================================
484 const RegMask& MachConstantBaseNode::_out_RegMask = RegMask::Empty;
485
486 int Compile::ConstantTable::calculate_table_base_offset() const {
487 return 0; // absolute addressing, no offset
488 }
489
490 bool MachConstantBaseNode::requires_late_expand() const { return false; }
491 void MachConstantBaseNode::lateExpand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) {
492 ShouldNotReachHere();
493 }
494
495 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
496 // Empty encoding
497 }
498
499 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const {
500 return 0;
501 }
502
503 #ifndef PRODUCT
504 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
505 st->print("# MachConstantBaseNode (empty encoding)");
506 }
507 #endif
508
509
510 //=============================================================================
511 #ifndef PRODUCT
512 void MachPrologNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
513 Compile* C = ra_->C;
514
515 int framesize = C->frame_slots() << LogBytesPerInt;
516 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
517 // Remove wordSize for return addr which is already pushed.
518 framesize -= wordSize;
519
520 if (C->need_stack_bang(framesize)) {
521 framesize -= wordSize;
522 st->print("# stack bang");
523 st->print("\n\t");
524 st->print("PUSH EBP\t# Save EBP");
525 if (framesize) {
526 st->print("\n\t");
527 st->print("SUB ESP, #%d\t# Create frame",framesize);
528 }
529 } else {
530 st->print("SUB ESP, #%d\t# Create frame",framesize);
531 st->print("\n\t");
532 framesize -= wordSize;
533 st->print("MOV [ESP + #%d], EBP\t# Save EBP",framesize);
534 }
535
536 if (VerifyStackAtCalls) {
537 st->print("\n\t");
538 framesize -= wordSize;
539 st->print("MOV [ESP + #%d], 0xBADB100D\t# Majik cookie for stack depth check",framesize);
540 }
541
542 if( C->in_24_bit_fp_mode() ) {
543 st->print("\n\t");
544 st->print("FLDCW \t# load 24 bit fpu control word");
545 }
546 if (UseSSE >= 2 && VerifyFPU) {
547 st->print("\n\t");
548 st->print("# verify FPU stack (must be clean on entry)");
549 }
550
551 #ifdef ASSERT
552 if (VerifyStackAtCalls) {
553 st->print("\n\t");
554 st->print("# stack alignment check");
555 }
556 #endif
557 st->cr();
558 }
559 #endif
560
561
562 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
563 Compile* C = ra_->C;
564 MacroAssembler _masm(&cbuf);
565
566 int framesize = C->frame_slots() << LogBytesPerInt;
567
568 __ verified_entry(framesize, C->need_stack_bang(framesize), C->in_24_bit_fp_mode());
569
570 C->set_frame_complete(cbuf.insts_size());
571
572 if (C->has_mach_constant_base_node()) {
573 // NOTE: We set the table base offset here because users might be
574 // emitted before MachConstantBaseNode.
575 Compile::ConstantTable& constant_table = C->constant_table();
576 constant_table.set_table_base_offset(constant_table.calculate_table_base_offset());
577 }
578 }
579
580 uint MachPrologNode::size(PhaseRegAlloc *ra_) const {
581 return MachNode::size(ra_); // too many variables; just compute it the hard way
582 }
583
584 int MachPrologNode::reloc() const {
585 return 0; // a large enough number
586 }
587
588 //=============================================================================
589 #ifndef PRODUCT
590 void MachEpilogNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
591 Compile *C = ra_->C;
592 int framesize = C->frame_slots() << LogBytesPerInt;
593 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
594 // Remove two words for return addr and rbp,
595 framesize -= 2*wordSize;
596
597 if (C->max_vector_size() > 16) {
598 st->print("VZEROUPPER");
599 st->cr(); st->print("\t");
600 }
601 if (C->in_24_bit_fp_mode()) {
602 st->print("FLDCW standard control word");
603 st->cr(); st->print("\t");
604 }
605 if (framesize) {
606 st->print("ADD ESP,%d\t# Destroy frame",framesize);
607 st->cr(); st->print("\t");
608 }
609 st->print_cr("POPL EBP"); st->print("\t");
610 if (do_polling() && C->is_method_compilation()) {
611 st->print("TEST PollPage,EAX\t! Poll Safepoint");
612 st->cr(); st->print("\t");
613 }
614 }
615 #endif
616
617 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
618 Compile *C = ra_->C;
619
620 if (C->max_vector_size() > 16) {
621 // Clear upper bits of YMM registers when current compiled code uses
622 // wide vectors to avoid AVX <-> SSE transition penalty during call.
623 MacroAssembler masm(&cbuf);
624 masm.vzeroupper();
625 }
626 // If method set FPU control word, restore to standard control word
627 if (C->in_24_bit_fp_mode()) {
628 MacroAssembler masm(&cbuf);
629 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
630 }
631
632 int framesize = C->frame_slots() << LogBytesPerInt;
633 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
634 // Remove two words for return addr and rbp,
635 framesize -= 2*wordSize;
636
637 // Note that VerifyStackAtCalls' Majik cookie does not change the frame size popped here
638
639 if (framesize >= 128) {
640 emit_opcode(cbuf, 0x81); // add SP, #framesize
641 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
642 emit_d32(cbuf, framesize);
643 } else if (framesize) {
644 emit_opcode(cbuf, 0x83); // add SP, #framesize
645 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
646 emit_d8(cbuf, framesize);
647 }
648
649 emit_opcode(cbuf, 0x58 | EBP_enc);
650
651 if (do_polling() && C->is_method_compilation()) {
652 cbuf.relocate(cbuf.insts_end(), relocInfo::poll_return_type, 0);
653 emit_opcode(cbuf,0x85);
654 emit_rm(cbuf, 0x0, EAX_enc, 0x5); // EAX
655 emit_d32(cbuf, (intptr_t)os::get_polling_page());
656 }
657 }
658
659 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const {
660 Compile *C = ra_->C;
661 // If method set FPU control word, restore to standard control word
662 int size = C->in_24_bit_fp_mode() ? 6 : 0;
663 if (C->max_vector_size() > 16) size += 3; // vzeroupper
664 if (do_polling() && C->is_method_compilation()) size += 6;
665
666 int framesize = C->frame_slots() << LogBytesPerInt;
667 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
668 // Remove two words for return addr and rbp,
669 framesize -= 2*wordSize;
670
671 size++; // popl rbp,
672
673 if (framesize >= 128) {
674 size += 6;
675 } else {
676 size += framesize ? 3 : 0;
677 }
678 return size;
679 }
680
681 int MachEpilogNode::reloc() const {
682 return 0; // a large enough number
683 }
684
685 const Pipeline * MachEpilogNode::pipeline() const {
686 return MachNode::pipeline_class();
687 }
688
689 int MachEpilogNode::safepoint_offset() const { return 0; }
690
691 //=============================================================================
692
693 enum RC { rc_bad, rc_int, rc_float, rc_xmm, rc_stack };
694 static enum RC rc_class( OptoReg::Name reg ) {
695
696 if( !OptoReg::is_valid(reg) ) return rc_bad;
697 if (OptoReg::is_stack(reg)) return rc_stack;
698
699 VMReg r = OptoReg::as_VMReg(reg);
700 if (r->is_Register()) return rc_int;
701 if (r->is_FloatRegister()) {
702 assert(UseSSE < 2, "shouldn't be used in SSE2+ mode");
703 return rc_float;
704 }
705 assert(r->is_XMMRegister(), "must be");
706 return rc_xmm;
707 }
708
709 static int impl_helper( CodeBuffer *cbuf, bool do_size, bool is_load, int offset, int reg,
710 int opcode, const char *op_str, int size, outputStream* st ) {
711 if( cbuf ) {
712 emit_opcode (*cbuf, opcode );
713 encode_RegMem(*cbuf, Matcher::_regEncode[reg], ESP_enc, 0x4, 0, offset, false);
714 #ifndef PRODUCT
715 } else if( !do_size ) {
716 if( size != 0 ) st->print("\n\t");
717 if( opcode == 0x8B || opcode == 0x89 ) { // MOV
718 if( is_load ) st->print("%s %s,[ESP + #%d]",op_str,Matcher::regName[reg],offset);
719 else st->print("%s [ESP + #%d],%s",op_str,offset,Matcher::regName[reg]);
720 } else { // FLD, FST, PUSH, POP
721 st->print("%s [ESP + #%d]",op_str,offset);
722 }
723 #endif
724 }
725 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4);
726 return size+3+offset_size;
727 }
728
729 // Helper for XMM registers. Extra opcode bits, limited syntax.
730 static int impl_x_helper( CodeBuffer *cbuf, bool do_size, bool is_load,
731 int offset, int reg_lo, int reg_hi, int size, outputStream* st ) {
732 if (cbuf) {
733 MacroAssembler _masm(cbuf);
734 if (reg_lo+1 == reg_hi) { // double move?
735 if (is_load) {
736 __ movdbl(as_XMMRegister(Matcher::_regEncode[reg_lo]), Address(rsp, offset));
737 } else {
738 __ movdbl(Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[reg_lo]));
739 }
740 } else {
741 if (is_load) {
742 __ movflt(as_XMMRegister(Matcher::_regEncode[reg_lo]), Address(rsp, offset));
743 } else {
744 __ movflt(Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[reg_lo]));
745 }
746 }
747 #ifndef PRODUCT
748 } else if (!do_size) {
749 if (size != 0) st->print("\n\t");
750 if (reg_lo+1 == reg_hi) { // double move?
751 if (is_load) st->print("%s %s,[ESP + #%d]",
752 UseXmmLoadAndClearUpper ? "MOVSD " : "MOVLPD",
753 Matcher::regName[reg_lo], offset);
754 else st->print("MOVSD [ESP + #%d],%s",
755 offset, Matcher::regName[reg_lo]);
756 } else {
757 if (is_load) st->print("MOVSS %s,[ESP + #%d]",
758 Matcher::regName[reg_lo], offset);
759 else st->print("MOVSS [ESP + #%d],%s",
760 offset, Matcher::regName[reg_lo]);
761 }
762 #endif
763 }
764 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4);
765 // VEX_2bytes prefix is used if UseAVX > 0, so it takes the same 2 bytes as SIMD prefix.
766 return size+5+offset_size;
767 }
768
769
770 static int impl_movx_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
771 int src_hi, int dst_hi, int size, outputStream* st ) {
772 if (cbuf) {
773 MacroAssembler _masm(cbuf);
774 if (src_lo+1 == src_hi && dst_lo+1 == dst_hi) { // double move?
775 __ movdbl(as_XMMRegister(Matcher::_regEncode[dst_lo]),
776 as_XMMRegister(Matcher::_regEncode[src_lo]));
777 } else {
778 __ movflt(as_XMMRegister(Matcher::_regEncode[dst_lo]),
779 as_XMMRegister(Matcher::_regEncode[src_lo]));
780 }
781 #ifndef PRODUCT
782 } else if (!do_size) {
783 if (size != 0) st->print("\n\t");
784 if (UseXmmRegToRegMoveAll) {//Use movaps,movapd to move between xmm registers
785 if (src_lo+1 == src_hi && dst_lo+1 == dst_hi) { // double move?
786 st->print("MOVAPD %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
787 } else {
788 st->print("MOVAPS %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
789 }
790 } else {
791 if( src_lo+1 == src_hi && dst_lo+1 == dst_hi ) { // double move?
792 st->print("MOVSD %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
793 } else {
794 st->print("MOVSS %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]);
795 }
796 }
797 #endif
798 }
799 // VEX_2bytes prefix is used if UseAVX > 0, and it takes the same 2 bytes as SIMD prefix.
800 // Only MOVAPS SSE prefix uses 1 byte.
801 int sz = 4;
802 if (!(src_lo+1 == src_hi && dst_lo+1 == dst_hi) &&
803 UseXmmRegToRegMoveAll && (UseAVX == 0)) sz = 3;
804 return size + sz;
805 }
806
807 static int impl_movgpr2x_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
808 int src_hi, int dst_hi, int size, outputStream* st ) {
809 // 32-bit
810 if (cbuf) {
811 MacroAssembler _masm(cbuf);
812 __ movdl(as_XMMRegister(Matcher::_regEncode[dst_lo]),
813 as_Register(Matcher::_regEncode[src_lo]));
814 #ifndef PRODUCT
815 } else if (!do_size) {
816 st->print("movdl %s, %s\t# spill", Matcher::regName[dst_lo], Matcher::regName[src_lo]);
817 #endif
818 }
819 return 4;
820 }
821
822
823 static int impl_movx2gpr_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
824 int src_hi, int dst_hi, int size, outputStream* st ) {
825 // 32-bit
826 if (cbuf) {
827 MacroAssembler _masm(cbuf);
828 __ movdl(as_Register(Matcher::_regEncode[dst_lo]),
829 as_XMMRegister(Matcher::_regEncode[src_lo]));
830 #ifndef PRODUCT
831 } else if (!do_size) {
832 st->print("movdl %s, %s\t# spill", Matcher::regName[dst_lo], Matcher::regName[src_lo]);
833 #endif
834 }
835 return 4;
836 }
837
838 static int impl_mov_helper( CodeBuffer *cbuf, bool do_size, int src, int dst, int size, outputStream* st ) {
839 if( cbuf ) {
840 emit_opcode(*cbuf, 0x8B );
841 emit_rm (*cbuf, 0x3, Matcher::_regEncode[dst], Matcher::_regEncode[src] );
842 #ifndef PRODUCT
843 } else if( !do_size ) {
844 if( size != 0 ) st->print("\n\t");
845 st->print("MOV %s,%s",Matcher::regName[dst],Matcher::regName[src]);
846 #endif
847 }
848 return size+2;
849 }
850
851 static int impl_fp_store_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int src_hi, int dst_lo, int dst_hi,
852 int offset, int size, outputStream* st ) {
853 if( src_lo != FPR1L_num ) { // Move value to top of FP stack, if not already there
854 if( cbuf ) {
855 emit_opcode( *cbuf, 0xD9 ); // FLD (i.e., push it)
856 emit_d8( *cbuf, 0xC0-1+Matcher::_regEncode[src_lo] );
857 #ifndef PRODUCT
858 } else if( !do_size ) {
859 if( size != 0 ) st->print("\n\t");
860 st->print("FLD %s",Matcher::regName[src_lo]);
861 #endif
862 }
863 size += 2;
864 }
865
866 int st_op = (src_lo != FPR1L_num) ? EBX_num /*store & pop*/ : EDX_num /*store no pop*/;
867 const char *op_str;
868 int op;
869 if( src_lo+1 == src_hi && dst_lo+1 == dst_hi ) { // double store?
870 op_str = (src_lo != FPR1L_num) ? "FSTP_D" : "FST_D ";
871 op = 0xDD;
872 } else { // 32-bit store
873 op_str = (src_lo != FPR1L_num) ? "FSTP_S" : "FST_S ";
874 op = 0xD9;
875 assert( !OptoReg::is_valid(src_hi) && !OptoReg::is_valid(dst_hi), "no non-adjacent float-stores" );
876 }
877
878 return impl_helper(cbuf,do_size,false,offset,st_op,op,op_str,size, st);
879 }
880
881 // Next two methods are shared by 32- and 64-bit VM. They are defined in x86.ad.
882 static int vec_mov_helper(CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
883 int src_hi, int dst_hi, uint ireg, outputStream* st);
884
885 static int vec_spill_helper(CodeBuffer *cbuf, bool do_size, bool is_load,
886 int stack_offset, int reg, uint ireg, outputStream* st);
887
888 static int vec_stack_to_stack_helper(CodeBuffer *cbuf, bool do_size, int src_offset,
889 int dst_offset, uint ireg, outputStream* st) {
890 int calc_size = 0;
891 int src_offset_size = (src_offset == 0) ? 0 : ((src_offset < 0x80) ? 1 : 4);
892 int dst_offset_size = (dst_offset == 0) ? 0 : ((dst_offset < 0x80) ? 1 : 4);
893 switch (ireg) {
894 case Op_VecS:
895 calc_size = 3+src_offset_size + 3+dst_offset_size;
896 break;
897 case Op_VecD:
898 calc_size = 3+src_offset_size + 3+dst_offset_size;
899 src_offset += 4;
900 dst_offset += 4;
901 src_offset_size = (src_offset == 0) ? 0 : ((src_offset < 0x80) ? 1 : 4);
902 dst_offset_size = (dst_offset == 0) ? 0 : ((dst_offset < 0x80) ? 1 : 4);
903 calc_size += 3+src_offset_size + 3+dst_offset_size;
904 break;
905 case Op_VecX:
906 calc_size = 6 + 6 + 5+src_offset_size + 5+dst_offset_size;
907 break;
908 case Op_VecY:
909 calc_size = 6 + 6 + 5+src_offset_size + 5+dst_offset_size;
910 break;
911 default:
912 ShouldNotReachHere();
913 }
914 if (cbuf) {
915 MacroAssembler _masm(cbuf);
916 int offset = __ offset();
917 switch (ireg) {
918 case Op_VecS:
919 __ pushl(Address(rsp, src_offset));
920 __ popl (Address(rsp, dst_offset));
921 break;
922 case Op_VecD:
923 __ pushl(Address(rsp, src_offset));
924 __ popl (Address(rsp, dst_offset));
925 __ pushl(Address(rsp, src_offset+4));
926 __ popl (Address(rsp, dst_offset+4));
927 break;
928 case Op_VecX:
929 __ movdqu(Address(rsp, -16), xmm0);
930 __ movdqu(xmm0, Address(rsp, src_offset));
931 __ movdqu(Address(rsp, dst_offset), xmm0);
932 __ movdqu(xmm0, Address(rsp, -16));
933 break;
934 case Op_VecY:
935 __ vmovdqu(Address(rsp, -32), xmm0);
936 __ vmovdqu(xmm0, Address(rsp, src_offset));
937 __ vmovdqu(Address(rsp, dst_offset), xmm0);
938 __ vmovdqu(xmm0, Address(rsp, -32));
939 break;
940 default:
941 ShouldNotReachHere();
942 }
943 int size = __ offset() - offset;
944 assert(size == calc_size, "incorrect size calculattion");
945 return size;
946 #ifndef PRODUCT
947 } else if (!do_size) {
948 switch (ireg) {
949 case Op_VecS:
950 st->print("pushl [rsp + #%d]\t# 32-bit mem-mem spill\n\t"
951 "popl [rsp + #%d]",
952 src_offset, dst_offset);
953 break;
954 case Op_VecD:
955 st->print("pushl [rsp + #%d]\t# 64-bit mem-mem spill\n\t"
956 "popq [rsp + #%d]\n\t"
957 "pushl [rsp + #%d]\n\t"
958 "popq [rsp + #%d]",
959 src_offset, dst_offset, src_offset+4, dst_offset+4);
960 break;
961 case Op_VecX:
962 st->print("movdqu [rsp - #16], xmm0\t# 128-bit mem-mem spill\n\t"
963 "movdqu xmm0, [rsp + #%d]\n\t"
964 "movdqu [rsp + #%d], xmm0\n\t"
965 "movdqu xmm0, [rsp - #16]",
966 src_offset, dst_offset);
967 break;
968 case Op_VecY:
969 st->print("vmovdqu [rsp - #32], xmm0\t# 256-bit mem-mem spill\n\t"
970 "vmovdqu xmm0, [rsp + #%d]\n\t"
971 "vmovdqu [rsp + #%d], xmm0\n\t"
972 "vmovdqu xmm0, [rsp - #32]",
973 src_offset, dst_offset);
974 break;
975 default:
976 ShouldNotReachHere();
977 }
978 #endif
979 }
980 return calc_size;
981 }
982
983 uint MachSpillCopyNode::implementation( CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, outputStream* st ) const {
984 // Get registers to move
985 OptoReg::Name src_second = ra_->get_reg_second(in(1));
986 OptoReg::Name src_first = ra_->get_reg_first(in(1));
987 OptoReg::Name dst_second = ra_->get_reg_second(this );
988 OptoReg::Name dst_first = ra_->get_reg_first(this );
989
990 enum RC src_second_rc = rc_class(src_second);
991 enum RC src_first_rc = rc_class(src_first);
992 enum RC dst_second_rc = rc_class(dst_second);
993 enum RC dst_first_rc = rc_class(dst_first);
994
995 assert( OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), "must move at least 1 register" );
996
997 // Generate spill code!
998 int size = 0;
999
1000 if( src_first == dst_first && src_second == dst_second )
1001 return size; // Self copy, no move
1002
1003 if (bottom_type()->isa_vect() != NULL) {
1004 uint ireg = ideal_reg();
1005 assert((src_first_rc != rc_int && dst_first_rc != rc_int), "sanity");
1006 assert((src_first_rc != rc_float && dst_first_rc != rc_float), "sanity");
1007 assert((ireg == Op_VecS || ireg == Op_VecD || ireg == Op_VecX || ireg == Op_VecY), "sanity");
1008 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) {
1009 // mem -> mem
1010 int src_offset = ra_->reg2offset(src_first);
1011 int dst_offset = ra_->reg2offset(dst_first);
1012 return vec_stack_to_stack_helper(cbuf, do_size, src_offset, dst_offset, ireg, st);
1013 } else if (src_first_rc == rc_xmm && dst_first_rc == rc_xmm ) {
1014 return vec_mov_helper(cbuf, do_size, src_first, dst_first, src_second, dst_second, ireg, st);
1015 } else if (src_first_rc == rc_xmm && dst_first_rc == rc_stack ) {
1016 int stack_offset = ra_->reg2offset(dst_first);
1017 return vec_spill_helper(cbuf, do_size, false, stack_offset, src_first, ireg, st);
1018 } else if (src_first_rc == rc_stack && dst_first_rc == rc_xmm ) {
1019 int stack_offset = ra_->reg2offset(src_first);
1020 return vec_spill_helper(cbuf, do_size, true, stack_offset, dst_first, ireg, st);
1021 } else {
1022 ShouldNotReachHere();
1023 }
1024 }
1025
1026 // --------------------------------------
1027 // Check for mem-mem move. push/pop to move.
1028 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) {
1029 if( src_second == dst_first ) { // overlapping stack copy ranges
1030 assert( src_second_rc == rc_stack && dst_second_rc == rc_stack, "we only expect a stk-stk copy here" );
1031 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),ESI_num,0xFF,"PUSH ",size, st);
1032 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),EAX_num,0x8F,"POP ",size, st);
1033 src_second_rc = dst_second_rc = rc_bad; // flag as already moved the second bits
1034 }
1035 // move low bits
1036 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),ESI_num,0xFF,"PUSH ",size, st);
1037 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),EAX_num,0x8F,"POP ",size, st);
1038 if( src_second_rc == rc_stack && dst_second_rc == rc_stack ) { // mov second bits
1039 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),ESI_num,0xFF,"PUSH ",size, st);
1040 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),EAX_num,0x8F,"POP ",size, st);
1041 }
1042 return size;
1043 }
1044
1045 // --------------------------------------
1046 // Check for integer reg-reg copy
1047 if( src_first_rc == rc_int && dst_first_rc == rc_int )
1048 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,size, st);
1049
1050 // Check for integer store
1051 if( src_first_rc == rc_int && dst_first_rc == rc_stack )
1052 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),src_first,0x89,"MOV ",size, st);
1053
1054 // Check for integer load
1055 if( dst_first_rc == rc_int && src_first_rc == rc_stack )
1056 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),dst_first,0x8B,"MOV ",size, st);
1057
1058 // Check for integer reg-xmm reg copy
1059 if( src_first_rc == rc_int && dst_first_rc == rc_xmm ) {
1060 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad),
1061 "no 64 bit integer-float reg moves" );
1062 return impl_movgpr2x_helper(cbuf,do_size,src_first,dst_first,src_second, dst_second, size, st);
1063 }
1064 // --------------------------------------
1065 // Check for float reg-reg copy
1066 if( src_first_rc == rc_float && dst_first_rc == rc_float ) {
1067 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad) ||
1068 (src_first+1 == src_second && dst_first+1 == dst_second), "no non-adjacent float-moves" );
1069 if( cbuf ) {
1070
1071 // Note the mucking with the register encode to compensate for the 0/1
1072 // indexing issue mentioned in a comment in the reg_def sections
1073 // for FPR registers many lines above here.
1074
1075 if( src_first != FPR1L_num ) {
1076 emit_opcode (*cbuf, 0xD9 ); // FLD ST(i)
1077 emit_d8 (*cbuf, 0xC0+Matcher::_regEncode[src_first]-1 );
1078 emit_opcode (*cbuf, 0xDD ); // FSTP ST(i)
1079 emit_d8 (*cbuf, 0xD8+Matcher::_regEncode[dst_first] );
1080 } else {
1081 emit_opcode (*cbuf, 0xDD ); // FST ST(i)
1082 emit_d8 (*cbuf, 0xD0+Matcher::_regEncode[dst_first]-1 );
1083 }
1084 #ifndef PRODUCT
1085 } else if( !do_size ) {
1086 if( size != 0 ) st->print("\n\t");
1087 if( src_first != FPR1L_num ) st->print("FLD %s\n\tFSTP %s",Matcher::regName[src_first],Matcher::regName[dst_first]);
1088 else st->print( "FST %s", Matcher::regName[dst_first]);
1089 #endif
1090 }
1091 return size + ((src_first != FPR1L_num) ? 2+2 : 2);
1092 }
1093
1094 // Check for float store
1095 if( src_first_rc == rc_float && dst_first_rc == rc_stack ) {
1096 return impl_fp_store_helper(cbuf,do_size,src_first,src_second,dst_first,dst_second,ra_->reg2offset(dst_first),size, st);
1097 }
1098
1099 // Check for float load
1100 if( dst_first_rc == rc_float && src_first_rc == rc_stack ) {
1101 int offset = ra_->reg2offset(src_first);
1102 const char *op_str;
1103 int op;
1104 if( src_first+1 == src_second && dst_first+1 == dst_second ) { // double load?
1105 op_str = "FLD_D";
1106 op = 0xDD;
1107 } else { // 32-bit load
1108 op_str = "FLD_S";
1109 op = 0xD9;
1110 assert( src_second_rc == rc_bad && dst_second_rc == rc_bad, "no non-adjacent float-loads" );
1111 }
1112 if( cbuf ) {
1113 emit_opcode (*cbuf, op );
1114 encode_RegMem(*cbuf, 0x0, ESP_enc, 0x4, 0, offset, false);
1115 emit_opcode (*cbuf, 0xDD ); // FSTP ST(i)
1116 emit_d8 (*cbuf, 0xD8+Matcher::_regEncode[dst_first] );
1117 #ifndef PRODUCT
1118 } else if( !do_size ) {
1119 if( size != 0 ) st->print("\n\t");
1120 st->print("%s ST,[ESP + #%d]\n\tFSTP %s",op_str, offset,Matcher::regName[dst_first]);
1121 #endif
1122 }
1123 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4);
1124 return size + 3+offset_size+2;
1125 }
1126
1127 // Check for xmm reg-reg copy
1128 if( src_first_rc == rc_xmm && dst_first_rc == rc_xmm ) {
1129 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad) ||
1130 (src_first+1 == src_second && dst_first+1 == dst_second),
1131 "no non-adjacent float-moves" );
1132 return impl_movx_helper(cbuf,do_size,src_first,dst_first,src_second, dst_second, size, st);
1133 }
1134
1135 // Check for xmm reg-integer reg copy
1136 if( src_first_rc == rc_xmm && dst_first_rc == rc_int ) {
1137 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad),
1138 "no 64 bit float-integer reg moves" );
1139 return impl_movx2gpr_helper(cbuf,do_size,src_first,dst_first,src_second, dst_second, size, st);
1140 }
1141
1142 // Check for xmm store
1143 if( src_first_rc == rc_xmm && dst_first_rc == rc_stack ) {
1144 return impl_x_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),src_first, src_second, size, st);
1145 }
1146
1147 // Check for float xmm load
1148 if( dst_first_rc == rc_xmm && src_first_rc == rc_stack ) {
1149 return impl_x_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),dst_first, dst_second, size, st);
1150 }
1151
1152 // Copy from float reg to xmm reg
1153 if( dst_first_rc == rc_xmm && src_first_rc == rc_float ) {
1154 // copy to the top of stack from floating point reg
1155 // and use LEA to preserve flags
1156 if( cbuf ) {
1157 emit_opcode(*cbuf,0x8D); // LEA ESP,[ESP-8]
1158 emit_rm(*cbuf, 0x1, ESP_enc, 0x04);
1159 emit_rm(*cbuf, 0x0, 0x04, ESP_enc);
1160 emit_d8(*cbuf,0xF8);
1161 #ifndef PRODUCT
1162 } else if( !do_size ) {
1163 if( size != 0 ) st->print("\n\t");
1164 st->print("LEA ESP,[ESP-8]");
1165 #endif
1166 }
1167 size += 4;
1168
1169 size = impl_fp_store_helper(cbuf,do_size,src_first,src_second,dst_first,dst_second,0,size, st);
1170
1171 // Copy from the temp memory to the xmm reg.
1172 size = impl_x_helper(cbuf,do_size,true ,0,dst_first, dst_second, size, st);
1173
1174 if( cbuf ) {
1175 emit_opcode(*cbuf,0x8D); // LEA ESP,[ESP+8]
1176 emit_rm(*cbuf, 0x1, ESP_enc, 0x04);
1177 emit_rm(*cbuf, 0x0, 0x04, ESP_enc);
1178 emit_d8(*cbuf,0x08);
1179 #ifndef PRODUCT
1180 } else if( !do_size ) {
1181 if( size != 0 ) st->print("\n\t");
1182 st->print("LEA ESP,[ESP+8]");
1183 #endif
1184 }
1185 size += 4;
1186 return size;
1187 }
1188
1189 assert( size > 0, "missed a case" );
1190
1191 // --------------------------------------------------------------------
1192 // Check for second bits still needing moving.
1193 if( src_second == dst_second )
1194 return size; // Self copy; no move
1195 assert( src_second_rc != rc_bad && dst_second_rc != rc_bad, "src_second & dst_second cannot be Bad" );
1196
1197 // Check for second word int-int move
1198 if( src_second_rc == rc_int && dst_second_rc == rc_int )
1199 return impl_mov_helper(cbuf,do_size,src_second,dst_second,size, st);
1200
1201 // Check for second word integer store
1202 if( src_second_rc == rc_int && dst_second_rc == rc_stack )
1203 return impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),src_second,0x89,"MOV ",size, st);
1204
1205 // Check for second word integer load
1206 if( dst_second_rc == rc_int && src_second_rc == rc_stack )
1207 return impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),dst_second,0x8B,"MOV ",size, st);
1208
1209
1210 Unimplemented();
1211 }
1212
1213 #ifndef PRODUCT
1214 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream* st) const {
1215 implementation( NULL, ra_, false, st );
1216 }
1217 #endif
1218
1219 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1220 implementation( &cbuf, ra_, false, NULL );
1221 }
1222
1223 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1224 return implementation( NULL, ra_, true, NULL );
1225 }
1226
1227
1228 //=============================================================================
1229 #ifndef PRODUCT
1230 void BoxLockNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
1231 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1232 int reg = ra_->get_reg_first(this);
1233 st->print("LEA %s,[ESP + #%d]",Matcher::regName[reg],offset);
1234 }
1235 #endif
1236
1237 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1238 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1239 int reg = ra_->get_encode(this);
1240 if( offset >= 128 ) {
1241 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
1242 emit_rm(cbuf, 0x2, reg, 0x04);
1243 emit_rm(cbuf, 0x0, 0x04, ESP_enc);
1244 emit_d32(cbuf, offset);
1245 }
1246 else {
1247 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
1248 emit_rm(cbuf, 0x1, reg, 0x04);
1249 emit_rm(cbuf, 0x0, 0x04, ESP_enc);
1250 emit_d8(cbuf, offset);
1251 }
1252 }
1253
1254 uint BoxLockNode::size(PhaseRegAlloc *ra_) const {
1255 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1256 if( offset >= 128 ) {
1257 return 7;
1258 }
1259 else {
1260 return 4;
1261 }
1262 }
1263
1264 //=============================================================================
1265
1266 // Offset from start of compiled java to interpreter stub to the load
1267 // constant that loads the inline cache (IC) (0 on i486).
1268 const int CompiledStaticCall::comp_to_int_load_offset = 0;
1269
1270 // emit call stub, compiled java to interpreter
1271 void emit_java_to_interp(CodeBuffer &cbuf ) {
1272 // Stub is fixed up when the corresponding call is converted from calling
1273 // compiled code to calling interpreted code.
1274 // mov rbx,0
1275 // jmp -1
1276
1277 address mark = cbuf.insts_mark(); // get mark within main instrs section
1278
1279 // Note that the code buffer's insts_mark is always relative to insts.
1280 // That's why we must use the macroassembler to generate a stub.
1281 MacroAssembler _masm(&cbuf);
1282
1283 address base =
1284 __ start_a_stub(Compile::MAX_stubs_size);
1285 if (base == NULL) return; // CodeBuffer::expand failed
1286 // static stub relocation stores the instruction address of the call
1287 __ relocate(static_stub_Relocation::spec(mark), RELOC_IMM32);
1288 // static stub relocation also tags the methodOop in the code-stream.
1289 __ movoop(rbx, (jobject)NULL); // method is zapped till fixup time
1290 // This is recognized as unresolved by relocs/nativeInst/ic code
1291 __ jump(RuntimeAddress(__ pc()));
1292
1293 __ end_a_stub();
1294 // Update current stubs pointer and restore insts_end.
1295 }
1296 // size of call stub, compiled java to interpretor
1297 uint size_java_to_interp() {
1298 return 10; // movl; jmp
1299 }
1300 // relocation entries for call stub, compiled java to interpretor
1301 uint reloc_java_to_interp() {
1302 return 4; // 3 in emit_java_to_interp + 1 in Java_Static_Call
1303 }
1304
1305 //=============================================================================
1306 #ifndef PRODUCT
1307 void MachUEPNode::format( PhaseRegAlloc *ra_, outputStream* st ) const {
1308 st->print_cr( "CMP EAX,[ECX+4]\t# Inline cache check");
1309 st->print_cr("\tJNE SharedRuntime::handle_ic_miss_stub");
1310 st->print_cr("\tNOP");
1311 st->print_cr("\tNOP");
1312 if( !OptoBreakpoint )
1313 st->print_cr("\tNOP");
1314 }
1315 #endif
1316
1317 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1318 MacroAssembler masm(&cbuf);
1319 #ifdef ASSERT
1320 uint insts_size = cbuf.insts_size();
1321 #endif
1322 masm.cmpptr(rax, Address(rcx, oopDesc::klass_offset_in_bytes()));
1323 masm.jump_cc(Assembler::notEqual,
1324 RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
1325 /* WARNING these NOPs are critical so that verified entry point is properly
1326 aligned for patching by NativeJump::patch_verified_entry() */
1327 int nops_cnt = 2;
1328 if( !OptoBreakpoint ) // Leave space for int3
1329 nops_cnt += 1;
1330 masm.nop(nops_cnt);
1331
1332 assert(cbuf.insts_size() - insts_size == size(ra_), "checking code size of inline cache node");
1333 }
1334
1335 uint MachUEPNode::size(PhaseRegAlloc *ra_) const {
1336 return OptoBreakpoint ? 11 : 12;
1337 }
1338
1339
1340 //=============================================================================
1341 uint size_exception_handler() {
1342 // NativeCall instruction size is the same as NativeJump.
1343 // exception handler starts out as jump and can be patched to
1344 // a call be deoptimization. (4932387)
1345 // Note that this value is also credited (in output.cpp) to
1346 // the size of the code section.
1347 return NativeJump::instruction_size;
1348 }
1349
1350 // Emit exception handler code. Stuff framesize into a register
1351 // and call a VM stub routine.
1352 int emit_exception_handler(CodeBuffer& cbuf) {
1353
1354 // Note that the code buffer's insts_mark is always relative to insts.
1355 // That's why we must use the macroassembler to generate a handler.
1356 MacroAssembler _masm(&cbuf);
1357 address base =
1358 __ start_a_stub(size_exception_handler());
1359 if (base == NULL) return 0; // CodeBuffer::expand failed
1360 int offset = __ offset();
1361 __ jump(RuntimeAddress(OptoRuntime::exception_blob()->entry_point()));
1362 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow");
1363 __ end_a_stub();
1364 return offset;
1365 }
1366
1367 uint size_deopt_handler() {
1368 // NativeCall instruction size is the same as NativeJump.
1369 // exception handler starts out as jump and can be patched to
1370 // a call be deoptimization. (4932387)
1371 // Note that this value is also credited (in output.cpp) to
1372 // the size of the code section.
1373 return 5 + NativeJump::instruction_size; // pushl(); jmp;
1374 }
1375
1376 // Emit deopt handler code.
1377 int emit_deopt_handler(CodeBuffer& cbuf) {
1378
1379 // Note that the code buffer's insts_mark is always relative to insts.
1380 // That's why we must use the macroassembler to generate a handler.
1381 MacroAssembler _masm(&cbuf);
1382 address base =
1383 __ start_a_stub(size_exception_handler());
1384 if (base == NULL) return 0; // CodeBuffer::expand failed
1385 int offset = __ offset();
1386 InternalAddress here(__ pc());
1387 __ pushptr(here.addr());
1388
1389 __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
1390 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow");
1391 __ end_a_stub();
1392 return offset;
1393 }
1394
1395 int Matcher::regnum_to_fpu_offset(int regnum) {
1396 return regnum - 32; // The FP registers are in the second chunk
1397 }
1398
1399 // This is UltraSparc specific, true just means we have fast l2f conversion
1400 const bool Matcher::convL2FSupported(void) {
1401 return true;
1402 }
1403
1404 // Is this branch offset short enough that a short branch can be used?
1405 //
1406 // NOTE: If the platform does not provide any short branch variants, then
1407 // this method should return false for offset 0.
1408 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
1409 // The passed offset is relative to address of the branch.
1410 // On 86 a branch displacement is calculated relative to address
1411 // of a next instruction.
1412 offset -= br_size;
1413
1414 // the short version of jmpConUCF2 contains multiple branches,
1415 // making the reach slightly less
1416 if (rule == jmpConUCF2_rule)
1417 return (-126 <= offset && offset <= 125);
1418 return (-128 <= offset && offset <= 127);
1419 }
1420
1421 const bool Matcher::isSimpleConstant64(jlong value) {
1422 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?.
1423 return false;
1424 }
1425
1426 // The ecx parameter to rep stos for the ClearArray node is in dwords.
1427 const bool Matcher::init_array_count_is_in_bytes = false;
1428
1429 // Threshold size for cleararray.
1430 const int Matcher::init_array_short_size = 8 * BytesPerLong;
1431
1432 // Needs 2 CMOV's for longs.
1433 const int Matcher::long_cmove_cost() { return 1; }
1434
1435 // No CMOVF/CMOVD with SSE/SSE2
1436 const int Matcher::float_cmove_cost() { return (UseSSE>=1) ? ConditionalMoveLimit : 0; }
1437
1438 // Does the CPU require late expand (see block.cpp for description of late expand)?
1439 const bool Matcher::require_late_expand = false;
1440
1441 // Should the Matcher clone shifts on addressing modes, expecting them to
1442 // be subsumed into complex addressing expressions or compute them into
1443 // registers? True for Intel but false for most RISCs
1444 const bool Matcher::clone_shift_expressions = true;
1445
1446 // Do we need to mask the count passed to shift instructions or does
1447 // the cpu only look at the lower 5/6 bits anyway?
1448 const bool Matcher::need_masked_shift_count = false;
1449
1450 bool Matcher::narrow_oop_use_complex_address() {
1451 ShouldNotCallThis();
1452 return true;
1453 }
1454
1455
1456 // Is it better to copy float constants, or load them directly from memory?
1457 // Intel can load a float constant from a direct address, requiring no
1458 // extra registers. Most RISCs will have to materialize an address into a
1459 // register first, so they would do better to copy the constant from stack.
1460 const bool Matcher::rematerialize_float_constants = true;
1461
1462 // If CPU can load and store mis-aligned doubles directly then no fixup is
1463 // needed. Else we split the double into 2 integer pieces and move it
1464 // piece-by-piece. Only happens when passing doubles into C code as the
1465 // Java calling convention forces doubles to be aligned.
1466 const bool Matcher::misaligned_doubles_ok = true;
1467
1468
1469 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {
1470 // Get the memory operand from the node
1471 uint numopnds = node->num_opnds(); // Virtual call for number of operands
1472 uint skipped = node->oper_input_base(); // Sum of leaves skipped so far
1473 assert( idx >= skipped, "idx too low in pd_implicit_null_fixup" );
1474 uint opcnt = 1; // First operand
1475 uint num_edges = node->_opnds[1]->num_edges(); // leaves for first operand
1476 while( idx >= skipped+num_edges ) {
1477 skipped += num_edges;
1478 opcnt++; // Bump operand count
1479 assert( opcnt < numopnds, "Accessing non-existent operand" );
1480 num_edges = node->_opnds[opcnt]->num_edges(); // leaves for next operand
1481 }
1482
1483 MachOper *memory = node->_opnds[opcnt];
1484 MachOper *new_memory = NULL;
1485 switch (memory->opcode()) {
1486 case DIRECT:
1487 case INDOFFSET32X:
1488 // No transformation necessary.
1489 return;
1490 case INDIRECT:
1491 new_memory = new (C) indirect_win95_safeOper( );
1492 break;
1493 case INDOFFSET8:
1494 new_memory = new (C) indOffset8_win95_safeOper(memory->disp(NULL, NULL, 0));
1495 break;
1496 case INDOFFSET32:
1497 new_memory = new (C) indOffset32_win95_safeOper(memory->disp(NULL, NULL, 0));
1498 break;
1499 case INDINDEXOFFSET:
1500 new_memory = new (C) indIndexOffset_win95_safeOper(memory->disp(NULL, NULL, 0));
1501 break;
1502 case INDINDEXSCALE:
1503 new_memory = new (C) indIndexScale_win95_safeOper(memory->scale());
1504 break;
1505 case INDINDEXSCALEOFFSET:
1506 new_memory = new (C) indIndexScaleOffset_win95_safeOper(memory->scale(), memory->disp(NULL, NULL, 0));
1507 break;
1508 case LOAD_LONG_INDIRECT:
1509 case LOAD_LONG_INDOFFSET32:
1510 // Does not use EBP as address register, use { EDX, EBX, EDI, ESI}
1511 return;
1512 default:
1513 assert(false, "unexpected memory operand in pd_implicit_null_fixup()");
1514 return;
1515 }
1516 node->_opnds[opcnt] = new_memory;
1517 }
1518
1519 // Advertise here if the CPU requires explicit rounding operations
1520 // to implement the UseStrictFP mode.
1521 const bool Matcher::strict_fp_requires_explicit_rounding = true;
1522
1523 // Are floats conerted to double when stored to stack during deoptimization?
1524 // On x32 it is stored with convertion only when FPU is used for floats.
1525 bool Matcher::float_in_double() { return (UseSSE == 0); }
1526
1527 // Do ints take an entire long register or just half?
1528 const bool Matcher::int_in_long = false;
1529
1530 // Return whether or not this register is ever used as an argument. This
1531 // function is used on startup to build the trampoline stubs in generateOptoStub.
1532 // Registers not mentioned will be killed by the VM call in the trampoline, and
1533 // arguments in those registers not be available to the callee.
1534 bool Matcher::can_be_java_arg( int reg ) {
1535 if( reg == ECX_num || reg == EDX_num ) return true;
1536 if( (reg == XMM0_num || reg == XMM1_num ) && UseSSE>=1 ) return true;
1537 if( (reg == XMM0b_num || reg == XMM1b_num) && UseSSE>=2 ) return true;
1538 return false;
1539 }
1540
1541 bool Matcher::is_spillable_arg( int reg ) {
1542 return can_be_java_arg(reg);
1543 }
1544
1545 bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) {
1546 // Use hardware integer DIV instruction when
1547 // it is faster than a code which use multiply.
1548 // Only when constant divisor fits into 32 bit
1549 // (min_jint is excluded to get only correct
1550 // positive 32 bit values from negative).
1551 return VM_Version::has_fast_idiv() &&
1552 (divisor == (int)divisor && divisor != min_jint);
1553 }
1554
1555 // Register for DIVI projection of divmodI
1556 RegMask Matcher::divI_proj_mask() {
1557 return EAX_REG_mask();
1558 }
1559
1560 // Register for MODI projection of divmodI
1561 RegMask Matcher::modI_proj_mask() {
1562 return EDX_REG_mask();
1563 }
1564
1565 // Register for DIVL projection of divmodL
1566 RegMask Matcher::divL_proj_mask() {
1567 ShouldNotReachHere();
1568 return RegMask();
1569 }
1570
1571 // Register for MODL projection of divmodL
1572 RegMask Matcher::modL_proj_mask() {
1573 ShouldNotReachHere();
1574 return RegMask();
1575 }
1576
1577 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
1578 return EBP_REG_mask();
1579 }
1580
1581 // Returns true if the high 32 bits of the value is known to be zero.
1582 bool is_operand_hi32_zero(Node* n) {
1583 int opc = n->Opcode();
1584 if (opc == Op_AndL) {
1585 Node* o2 = n->in(2);
1586 if (o2->is_Con() && (o2->get_long() & 0xFFFFFFFF00000000LL) == 0LL) {
1587 return true;
1588 }
1589 }
1590 if (opc == Op_ConL && (n->get_long() & 0xFFFFFFFF00000000LL) == 0LL) {
1591 return true;
1592 }
1593 return false;
1594 }
1595
1596 %}
1597
1598 //----------ENCODING BLOCK-----------------------------------------------------
1599 // This block specifies the encoding classes used by the compiler to output
1600 // byte streams. Encoding classes generate functions which are called by
1601 // Machine Instruction Nodes in order to generate the bit encoding of the
1602 // instruction. Operands specify their base encoding interface with the
1603 // interface keyword. There are currently supported four interfaces,
1604 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an
1605 // operand to generate a function which returns its register number when
1606 // queried. CONST_INTER causes an operand to generate a function which
1607 // returns the value of the constant when queried. MEMORY_INTER causes an
1608 // operand to generate four functions which return the Base Register, the
1609 // Index Register, the Scale Value, and the Offset Value of the operand when
1610 // queried. COND_INTER causes an operand to generate six functions which
1611 // return the encoding code (ie - encoding bits for the instruction)
1612 // associated with each basic boolean condition for a conditional instruction.
1613 // Instructions specify two basic values for encoding. They use the
1614 // ins_encode keyword to specify their encoding class (which must be one of
1615 // the class names specified in the encoding block), and they use the
1616 // opcode keyword to specify, in order, their primary, secondary, and
1617 // tertiary opcode. Only the opcode sections which a particular instruction
1618 // needs for encoding need to be specified.
1619 encode %{
1620 // Build emit functions for each basic byte or larger field in the intel
1621 // encoding scheme (opcode, rm, sib, immediate), and call them from C++
1622 // code in the enc_class source block. Emit functions will live in the
1623 // main source block for now. In future, we can generalize this by
1624 // adding a syntax that specifies the sizes of fields in an order,
1625 // so that the adlc can build the emit functions automagically
1626
1627 // Emit primary opcode
1628 enc_class OpcP %{
1629 emit_opcode(cbuf, $primary);
1630 %}
1631
1632 // Emit secondary opcode
1633 enc_class OpcS %{
1634 emit_opcode(cbuf, $secondary);
1635 %}
1636
1637 // Emit opcode directly
1638 enc_class Opcode(immI d8) %{
1639 emit_opcode(cbuf, $d8$$constant);
1640 %}
1641
1642 enc_class SizePrefix %{
1643 emit_opcode(cbuf,0x66);
1644 %}
1645
1646 enc_class RegReg (rRegI dst, rRegI src) %{ // RegReg(Many)
1647 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
1648 %}
1649
1650 enc_class OpcRegReg (immI opcode, rRegI dst, rRegI src) %{ // OpcRegReg(Many)
1651 emit_opcode(cbuf,$opcode$$constant);
1652 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
1653 %}
1654
1655 enc_class mov_r32_imm0( rRegI dst ) %{
1656 emit_opcode( cbuf, 0xB8 + $dst$$reg ); // 0xB8+ rd -- MOV r32 ,imm32
1657 emit_d32 ( cbuf, 0x0 ); // imm32==0x0
1658 %}
1659
1660 enc_class cdq_enc %{
1661 // Full implementation of Java idiv and irem; checks for
1662 // special case as described in JVM spec., p.243 & p.271.
1663 //
1664 // normal case special case
1665 //
1666 // input : rax,: dividend min_int
1667 // reg: divisor -1
1668 //
1669 // output: rax,: quotient (= rax, idiv reg) min_int
1670 // rdx: remainder (= rax, irem reg) 0
1671 //
1672 // Code sequnce:
1673 //
1674 // 81 F8 00 00 00 80 cmp rax,80000000h
1675 // 0F 85 0B 00 00 00 jne normal_case
1676 // 33 D2 xor rdx,edx
1677 // 83 F9 FF cmp rcx,0FFh
1678 // 0F 84 03 00 00 00 je done
1679 // normal_case:
1680 // 99 cdq
1681 // F7 F9 idiv rax,ecx
1682 // done:
1683 //
1684 emit_opcode(cbuf,0x81); emit_d8(cbuf,0xF8);
1685 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00);
1686 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x80); // cmp rax,80000000h
1687 emit_opcode(cbuf,0x0F); emit_d8(cbuf,0x85);
1688 emit_opcode(cbuf,0x0B); emit_d8(cbuf,0x00);
1689 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00); // jne normal_case
1690 emit_opcode(cbuf,0x33); emit_d8(cbuf,0xD2); // xor rdx,edx
1691 emit_opcode(cbuf,0x83); emit_d8(cbuf,0xF9); emit_d8(cbuf,0xFF); // cmp rcx,0FFh
1692 emit_opcode(cbuf,0x0F); emit_d8(cbuf,0x84);
1693 emit_opcode(cbuf,0x03); emit_d8(cbuf,0x00);
1694 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00); // je done
1695 // normal_case:
1696 emit_opcode(cbuf,0x99); // cdq
1697 // idiv (note: must be emitted by the user of this rule)
1698 // normal:
1699 %}
1700
1701 // Dense encoding for older common ops
1702 enc_class Opc_plus(immI opcode, rRegI reg) %{
1703 emit_opcode(cbuf, $opcode$$constant + $reg$$reg);
1704 %}
1705
1706
1707 // Opcde enc_class for 8/32 bit immediate instructions with sign-extension
1708 enc_class OpcSE (immI imm) %{ // Emit primary opcode and set sign-extend bit
1709 // Check for 8-bit immediate, and set sign extend bit in opcode
1710 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) {
1711 emit_opcode(cbuf, $primary | 0x02);
1712 }
1713 else { // If 32-bit immediate
1714 emit_opcode(cbuf, $primary);
1715 }
1716 %}
1717
1718 enc_class OpcSErm (rRegI dst, immI imm) %{ // OpcSEr/m
1719 // Emit primary opcode and set sign-extend bit
1720 // Check for 8-bit immediate, and set sign extend bit in opcode
1721 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) {
1722 emit_opcode(cbuf, $primary | 0x02); }
1723 else { // If 32-bit immediate
1724 emit_opcode(cbuf, $primary);
1725 }
1726 // Emit r/m byte with secondary opcode, after primary opcode.
1727 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
1728 %}
1729
1730 enc_class Con8or32 (immI imm) %{ // Con8or32(storeImmI), 8 or 32 bits
1731 // Check for 8-bit immediate, and set sign extend bit in opcode
1732 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) {
1733 $$$emit8$imm$$constant;
1734 }
1735 else { // If 32-bit immediate
1736 // Output immediate
1737 $$$emit32$imm$$constant;
1738 }
1739 %}
1740
1741 enc_class Long_OpcSErm_Lo(eRegL dst, immL imm) %{
1742 // Emit primary opcode and set sign-extend bit
1743 // Check for 8-bit immediate, and set sign extend bit in opcode
1744 int con = (int)$imm$$constant; // Throw away top bits
1745 emit_opcode(cbuf, ((con >= -128) && (con <= 127)) ? ($primary | 0x02) : $primary);
1746 // Emit r/m byte with secondary opcode, after primary opcode.
1747 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
1748 if ((con >= -128) && (con <= 127)) emit_d8 (cbuf,con);
1749 else emit_d32(cbuf,con);
1750 %}
1751
1752 enc_class Long_OpcSErm_Hi(eRegL dst, immL imm) %{
1753 // Emit primary opcode and set sign-extend bit
1754 // Check for 8-bit immediate, and set sign extend bit in opcode
1755 int con = (int)($imm$$constant >> 32); // Throw away bottom bits
1756 emit_opcode(cbuf, ((con >= -128) && (con <= 127)) ? ($primary | 0x02) : $primary);
1757 // Emit r/m byte with tertiary opcode, after primary opcode.
1758 emit_rm(cbuf, 0x3, $tertiary, HIGH_FROM_LOW($dst$$reg));
1759 if ((con >= -128) && (con <= 127)) emit_d8 (cbuf,con);
1760 else emit_d32(cbuf,con);
1761 %}
1762
1763 enc_class OpcSReg (rRegI dst) %{ // BSWAP
1764 emit_cc(cbuf, $secondary, $dst$$reg );
1765 %}
1766
1767 enc_class bswap_long_bytes(eRegL dst) %{ // BSWAP
1768 int destlo = $dst$$reg;
1769 int desthi = HIGH_FROM_LOW(destlo);
1770 // bswap lo
1771 emit_opcode(cbuf, 0x0F);
1772 emit_cc(cbuf, 0xC8, destlo);
1773 // bswap hi
1774 emit_opcode(cbuf, 0x0F);
1775 emit_cc(cbuf, 0xC8, desthi);
1776 // xchg lo and hi
1777 emit_opcode(cbuf, 0x87);
1778 emit_rm(cbuf, 0x3, destlo, desthi);
1779 %}
1780
1781 enc_class RegOpc (rRegI div) %{ // IDIV, IMOD, JMP indirect, ...
1782 emit_rm(cbuf, 0x3, $secondary, $div$$reg );
1783 %}
1784
1785 enc_class enc_cmov(cmpOp cop ) %{ // CMOV
1786 $$$emit8$primary;
1787 emit_cc(cbuf, $secondary, $cop$$cmpcode);
1788 %}
1789
1790 enc_class enc_cmov_dpr(cmpOp cop, regDPR src ) %{ // CMOV
1791 int op = 0xDA00 + $cop$$cmpcode + ($src$$reg-1);
1792 emit_d8(cbuf, op >> 8 );
1793 emit_d8(cbuf, op & 255);
1794 %}
1795
1796 // emulate a CMOV with a conditional branch around a MOV
1797 enc_class enc_cmov_branch( cmpOp cop, immI brOffs ) %{ // CMOV
1798 // Invert sense of branch from sense of CMOV
1799 emit_cc( cbuf, 0x70, ($cop$$cmpcode^1) );
1800 emit_d8( cbuf, $brOffs$$constant );
1801 %}
1802
1803 enc_class enc_PartialSubtypeCheck( ) %{
1804 Register Redi = as_Register(EDI_enc); // result register
1805 Register Reax = as_Register(EAX_enc); // super class
1806 Register Recx = as_Register(ECX_enc); // killed
1807 Register Resi = as_Register(ESI_enc); // sub class
1808 Label miss;
1809
1810 MacroAssembler _masm(&cbuf);
1811 __ check_klass_subtype_slow_path(Resi, Reax, Recx, Redi,
1812 NULL, &miss,
1813 /*set_cond_codes:*/ true);
1814 if ($primary) {
1815 __ xorptr(Redi, Redi);
1816 }
1817 __ bind(miss);
1818 %}
1819
1820 enc_class FFree_Float_Stack_All %{ // Free_Float_Stack_All
1821 MacroAssembler masm(&cbuf);
1822 int start = masm.offset();
1823 if (UseSSE >= 2) {
1824 if (VerifyFPU) {
1825 masm.verify_FPU(0, "must be empty in SSE2+ mode");
1826 }
1827 } else {
1828 // External c_calling_convention expects the FPU stack to be 'clean'.
1829 // Compiled code leaves it dirty. Do cleanup now.
1830 masm.empty_FPU_stack();
1831 }
1832 if (sizeof_FFree_Float_Stack_All == -1) {
1833 sizeof_FFree_Float_Stack_All = masm.offset() - start;
1834 } else {
1835 assert(masm.offset() - start == sizeof_FFree_Float_Stack_All, "wrong size");
1836 }
1837 %}
1838
1839 enc_class Verify_FPU_For_Leaf %{
1840 if( VerifyFPU ) {
1841 MacroAssembler masm(&cbuf);
1842 masm.verify_FPU( -3, "Returning from Runtime Leaf call");
1843 }
1844 %}
1845
1846 enc_class Java_To_Runtime (method meth) %{ // CALL Java_To_Runtime, Java_To_Runtime_Leaf
1847 // This is the instruction starting address for relocation info.
1848 cbuf.set_insts_mark();
1849 $$$emit8$primary;
1850 // CALL directly to the runtime
1851 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4),
1852 runtime_call_Relocation::spec(), RELOC_IMM32 );
1853
1854 if (UseSSE >= 2) {
1855 MacroAssembler _masm(&cbuf);
1856 BasicType rt = tf()->return_type();
1857
1858 if ((rt == T_FLOAT || rt == T_DOUBLE) && !return_value_is_used()) {
1859 // A C runtime call where the return value is unused. In SSE2+
1860 // mode the result needs to be removed from the FPU stack. It's
1861 // likely that this function call could be removed by the
1862 // optimizer if the C function is a pure function.
1863 __ ffree(0);
1864 } else if (rt == T_FLOAT) {
1865 __ lea(rsp, Address(rsp, -4));
1866 __ fstp_s(Address(rsp, 0));
1867 __ movflt(xmm0, Address(rsp, 0));
1868 __ lea(rsp, Address(rsp, 4));
1869 } else if (rt == T_DOUBLE) {
1870 __ lea(rsp, Address(rsp, -8));
1871 __ fstp_d(Address(rsp, 0));
1872 __ movdbl(xmm0, Address(rsp, 0));
1873 __ lea(rsp, Address(rsp, 8));
1874 }
1875 }
1876 %}
1877
1878
1879 enc_class pre_call_resets %{
1880 // If method sets FPU control word restore it here
1881 debug_only(int off0 = cbuf.insts_size());
1882 if (ra_->C->in_24_bit_fp_mode()) {
1883 MacroAssembler _masm(&cbuf);
1884 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
1885 }
1886 if (ra_->C->max_vector_size() > 16) {
1887 // Clear upper bits of YMM registers when current compiled code uses
1888 // wide vectors to avoid AVX <-> SSE transition penalty during call.
1889 MacroAssembler _masm(&cbuf);
1890 __ vzeroupper();
1891 }
1892 debug_only(int off1 = cbuf.insts_size());
1893 assert(off1 - off0 == pre_call_resets_size(), "correct size prediction");
1894 %}
1895
1896 enc_class post_call_FPU %{
1897 // If method sets FPU control word do it here also
1898 if (Compile::current()->in_24_bit_fp_mode()) {
1899 MacroAssembler masm(&cbuf);
1900 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
1901 }
1902 %}
1903
1904 enc_class Java_Static_Call (method meth) %{ // JAVA STATIC CALL
1905 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine
1906 // who we intended to call.
1907 cbuf.set_insts_mark();
1908 $$$emit8$primary;
1909 if (!_method) {
1910 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4),
1911 runtime_call_Relocation::spec(), RELOC_IMM32 );
1912 } else if (_optimized_virtual) {
1913 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4),
1914 opt_virtual_call_Relocation::spec(), RELOC_IMM32 );
1915 } else {
1916 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4),
1917 static_call_Relocation::spec(), RELOC_IMM32 );
1918 }
1919 if (_method) { // Emit stub for static call
1920 emit_java_to_interp(cbuf);
1921 }
1922 %}
1923
1924 enc_class Java_Dynamic_Call (method meth) %{ // JAVA DYNAMIC CALL
1925 // !!!!!
1926 // Generate "Mov EAX,0x00", placeholder instruction to load oop-info
1927 // emit_call_dynamic_prologue( cbuf );
1928 cbuf.set_insts_mark();
1929 emit_opcode(cbuf, 0xB8 + EAX_enc); // mov EAX,-1
1930 emit_d32_reloc(cbuf, (int)Universe::non_oop_word(), oop_Relocation::spec_for_immediate(), RELOC_IMM32);
1931 address virtual_call_oop_addr = cbuf.insts_mark();
1932 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine
1933 // who we intended to call.
1934 cbuf.set_insts_mark();
1935 $$$emit8$primary;
1936 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4),
1937 virtual_call_Relocation::spec(virtual_call_oop_addr), RELOC_IMM32 );
1938 %}
1939
1940 enc_class Java_Compiled_Call (method meth) %{ // JAVA COMPILED CALL
1941 int disp = in_bytes(methodOopDesc::from_compiled_offset());
1942 assert( -128 <= disp && disp <= 127, "compiled_code_offset isn't small");
1943
1944 // CALL *[EAX+in_bytes(methodOopDesc::from_compiled_code_entry_point_offset())]
1945 cbuf.set_insts_mark();
1946 $$$emit8$primary;
1947 emit_rm(cbuf, 0x01, $secondary, EAX_enc ); // R/M byte
1948 emit_d8(cbuf, disp); // Displacement
1949
1950 %}
1951
1952 // Following encoding is no longer used, but may be restored if calling
1953 // convention changes significantly.
1954 // Became: Xor_Reg(EBP), Java_To_Runtime( labl )
1955 //
1956 // enc_class Java_Interpreter_Call (label labl) %{ // JAVA INTERPRETER CALL
1957 // // int ic_reg = Matcher::inline_cache_reg();
1958 // // int ic_encode = Matcher::_regEncode[ic_reg];
1959 // // int imo_reg = Matcher::interpreter_method_oop_reg();
1960 // // int imo_encode = Matcher::_regEncode[imo_reg];
1961 //
1962 // // // Interpreter expects method_oop in EBX, currently a callee-saved register,
1963 // // // so we load it immediately before the call
1964 // // emit_opcode(cbuf, 0x8B); // MOV imo_reg,ic_reg # method_oop
1965 // // emit_rm(cbuf, 0x03, imo_encode, ic_encode ); // R/M byte
1966 //
1967 // // xor rbp,ebp
1968 // emit_opcode(cbuf, 0x33);
1969 // emit_rm(cbuf, 0x3, EBP_enc, EBP_enc);
1970 //
1971 // // CALL to interpreter.
1972 // cbuf.set_insts_mark();
1973 // $$$emit8$primary;
1974 // emit_d32_reloc(cbuf, ($labl$$label - (int)(cbuf.insts_end()) - 4),
1975 // runtime_call_Relocation::spec(), RELOC_IMM32 );
1976 // %}
1977
1978 enc_class RegOpcImm (rRegI dst, immI8 shift) %{ // SHL, SAR, SHR
1979 $$$emit8$primary;
1980 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
1981 $$$emit8$shift$$constant;
1982 %}
1983
1984 enc_class LdImmI (rRegI dst, immI src) %{ // Load Immediate
1985 // Load immediate does not have a zero or sign extended version
1986 // for 8-bit immediates
1987 emit_opcode(cbuf, 0xB8 + $dst$$reg);
1988 $$$emit32$src$$constant;
1989 %}
1990
1991 enc_class LdImmP (rRegI dst, immI src) %{ // Load Immediate
1992 // Load immediate does not have a zero or sign extended version
1993 // for 8-bit immediates
1994 emit_opcode(cbuf, $primary + $dst$$reg);
1995 $$$emit32$src$$constant;
1996 %}
1997
1998 enc_class LdImmL_Lo( eRegL dst, immL src) %{ // Load Immediate
1999 // Load immediate does not have a zero or sign extended version
2000 // for 8-bit immediates
2001 int dst_enc = $dst$$reg;
2002 int src_con = $src$$constant & 0x0FFFFFFFFL;
2003 if (src_con == 0) {
2004 // xor dst, dst
2005 emit_opcode(cbuf, 0x33);
2006 emit_rm(cbuf, 0x3, dst_enc, dst_enc);
2007 } else {
2008 emit_opcode(cbuf, $primary + dst_enc);
2009 emit_d32(cbuf, src_con);
2010 }
2011 %}
2012
2013 enc_class LdImmL_Hi( eRegL dst, immL src) %{ // Load Immediate
2014 // Load immediate does not have a zero or sign extended version
2015 // for 8-bit immediates
2016 int dst_enc = $dst$$reg + 2;
2017 int src_con = ((julong)($src$$constant)) >> 32;
2018 if (src_con == 0) {
2019 // xor dst, dst
2020 emit_opcode(cbuf, 0x33);
2021 emit_rm(cbuf, 0x3, dst_enc, dst_enc);
2022 } else {
2023 emit_opcode(cbuf, $primary + dst_enc);
2024 emit_d32(cbuf, src_con);
2025 }
2026 %}
2027
2028
2029 // Encode a reg-reg copy. If it is useless, then empty encoding.
2030 enc_class enc_Copy( rRegI dst, rRegI src ) %{
2031 encode_Copy( cbuf, $dst$$reg, $src$$reg );
2032 %}
2033
2034 enc_class enc_CopyL_Lo( rRegI dst, eRegL src ) %{
2035 encode_Copy( cbuf, $dst$$reg, $src$$reg );
2036 %}
2037
2038 enc_class RegReg (rRegI dst, rRegI src) %{ // RegReg(Many)
2039 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2040 %}
2041
2042 enc_class RegReg_Lo(eRegL dst, eRegL src) %{ // RegReg(Many)
2043 $$$emit8$primary;
2044 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2045 %}
2046
2047 enc_class RegReg_Hi(eRegL dst, eRegL src) %{ // RegReg(Many)
2048 $$$emit8$secondary;
2049 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg));
2050 %}
2051
2052 enc_class RegReg_Lo2(eRegL dst, eRegL src) %{ // RegReg(Many)
2053 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2054 %}
2055
2056 enc_class RegReg_Hi2(eRegL dst, eRegL src) %{ // RegReg(Many)
2057 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg));
2058 %}
2059
2060 enc_class RegReg_HiLo( eRegL src, rRegI dst ) %{
2061 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($src$$reg));
2062 %}
2063
2064 enc_class Con32 (immI src) %{ // Con32(storeImmI)
2065 // Output immediate
2066 $$$emit32$src$$constant;
2067 %}
2068
2069 enc_class Con32FPR_as_bits(immFPR src) %{ // storeF_imm
2070 // Output Float immediate bits
2071 jfloat jf = $src$$constant;
2072 int jf_as_bits = jint_cast( jf );
2073 emit_d32(cbuf, jf_as_bits);
2074 %}
2075
2076 enc_class Con32F_as_bits(immF src) %{ // storeX_imm
2077 // Output Float immediate bits
2078 jfloat jf = $src$$constant;
2079 int jf_as_bits = jint_cast( jf );
2080 emit_d32(cbuf, jf_as_bits);
2081 %}
2082
2083 enc_class Con16 (immI src) %{ // Con16(storeImmI)
2084 // Output immediate
2085 $$$emit16$src$$constant;
2086 %}
2087
2088 enc_class Con_d32(immI src) %{
2089 emit_d32(cbuf,$src$$constant);
2090 %}
2091
2092 enc_class conmemref (eRegP t1) %{ // Con32(storeImmI)
2093 // Output immediate memory reference
2094 emit_rm(cbuf, 0x00, $t1$$reg, 0x05 );
2095 emit_d32(cbuf, 0x00);
2096 %}
2097
2098 enc_class lock_prefix( ) %{
2099 if( os::is_MP() )
2100 emit_opcode(cbuf,0xF0); // [Lock]
2101 %}
2102
2103 // Cmp-xchg long value.
2104 // Note: we need to swap rbx, and rcx before and after the
2105 // cmpxchg8 instruction because the instruction uses
2106 // rcx as the high order word of the new value to store but
2107 // our register encoding uses rbx,.
2108 enc_class enc_cmpxchg8(eSIRegP mem_ptr) %{
2109
2110 // XCHG rbx,ecx
2111 emit_opcode(cbuf,0x87);
2112 emit_opcode(cbuf,0xD9);
2113 // [Lock]
2114 if( os::is_MP() )
2115 emit_opcode(cbuf,0xF0);
2116 // CMPXCHG8 [Eptr]
2117 emit_opcode(cbuf,0x0F);
2118 emit_opcode(cbuf,0xC7);
2119 emit_rm( cbuf, 0x0, 1, $mem_ptr$$reg );
2120 // XCHG rbx,ecx
2121 emit_opcode(cbuf,0x87);
2122 emit_opcode(cbuf,0xD9);
2123 %}
2124
2125 enc_class enc_cmpxchg(eSIRegP mem_ptr) %{
2126 // [Lock]
2127 if( os::is_MP() )
2128 emit_opcode(cbuf,0xF0);
2129
2130 // CMPXCHG [Eptr]
2131 emit_opcode(cbuf,0x0F);
2132 emit_opcode(cbuf,0xB1);
2133 emit_rm( cbuf, 0x0, 1, $mem_ptr$$reg );
2134 %}
2135
2136 enc_class enc_flags_ne_to_boolean( iRegI res ) %{
2137 int res_encoding = $res$$reg;
2138
2139 // MOV res,0
2140 emit_opcode( cbuf, 0xB8 + res_encoding);
2141 emit_d32( cbuf, 0 );
2142 // JNE,s fail
2143 emit_opcode(cbuf,0x75);
2144 emit_d8(cbuf, 5 );
2145 // MOV res,1
2146 emit_opcode( cbuf, 0xB8 + res_encoding);
2147 emit_d32( cbuf, 1 );
2148 // fail:
2149 %}
2150
2151 enc_class set_instruction_start( ) %{
2152 cbuf.set_insts_mark(); // Mark start of opcode for reloc info in mem operand
2153 %}
2154
2155 enc_class RegMem (rRegI ereg, memory mem) %{ // emit_reg_mem
2156 int reg_encoding = $ereg$$reg;
2157 int base = $mem$$base;
2158 int index = $mem$$index;
2159 int scale = $mem$$scale;
2160 int displace = $mem$$disp;
2161 bool disp_is_oop = $mem->disp_is_oop();
2162 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop);
2163 %}
2164
2165 enc_class RegMem_Hi(eRegL ereg, memory mem) %{ // emit_reg_mem
2166 int reg_encoding = HIGH_FROM_LOW($ereg$$reg); // Hi register of pair, computed from lo
2167 int base = $mem$$base;
2168 int index = $mem$$index;
2169 int scale = $mem$$scale;
2170 int displace = $mem$$disp + 4; // Offset is 4 further in memory
2171 assert( !$mem->disp_is_oop(), "Cannot add 4 to oop" );
2172 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, false/*disp_is_oop*/);
2173 %}
2174
2175 enc_class move_long_small_shift( eRegL dst, immI_1_31 cnt ) %{
2176 int r1, r2;
2177 if( $tertiary == 0xA4 ) { r1 = $dst$$reg; r2 = HIGH_FROM_LOW($dst$$reg); }
2178 else { r2 = $dst$$reg; r1 = HIGH_FROM_LOW($dst$$reg); }
2179 emit_opcode(cbuf,0x0F);
2180 emit_opcode(cbuf,$tertiary);
2181 emit_rm(cbuf, 0x3, r1, r2);
2182 emit_d8(cbuf,$cnt$$constant);
2183 emit_d8(cbuf,$primary);
2184 emit_rm(cbuf, 0x3, $secondary, r1);
2185 emit_d8(cbuf,$cnt$$constant);
2186 %}
2187
2188 enc_class move_long_big_shift_sign( eRegL dst, immI_32_63 cnt ) %{
2189 emit_opcode( cbuf, 0x8B ); // Move
2190 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg));
2191 if( $cnt$$constant > 32 ) { // Shift, if not by zero
2192 emit_d8(cbuf,$primary);
2193 emit_rm(cbuf, 0x3, $secondary, $dst$$reg);
2194 emit_d8(cbuf,$cnt$$constant-32);
2195 }
2196 emit_d8(cbuf,$primary);
2197 emit_rm(cbuf, 0x3, $secondary, HIGH_FROM_LOW($dst$$reg));
2198 emit_d8(cbuf,31);
2199 %}
2200
2201 enc_class move_long_big_shift_clr( eRegL dst, immI_32_63 cnt ) %{
2202 int r1, r2;
2203 if( $secondary == 0x5 ) { r1 = $dst$$reg; r2 = HIGH_FROM_LOW($dst$$reg); }
2204 else { r2 = $dst$$reg; r1 = HIGH_FROM_LOW($dst$$reg); }
2205
2206 emit_opcode( cbuf, 0x8B ); // Move r1,r2
2207 emit_rm(cbuf, 0x3, r1, r2);
2208 if( $cnt$$constant > 32 ) { // Shift, if not by zero
2209 emit_opcode(cbuf,$primary);
2210 emit_rm(cbuf, 0x3, $secondary, r1);
2211 emit_d8(cbuf,$cnt$$constant-32);
2212 }
2213 emit_opcode(cbuf,0x33); // XOR r2,r2
2214 emit_rm(cbuf, 0x3, r2, r2);
2215 %}
2216
2217 // Clone of RegMem but accepts an extra parameter to access each
2218 // half of a double in memory; it never needs relocation info.
2219 enc_class Mov_MemD_half_to_Reg (immI opcode, memory mem, immI disp_for_half, rRegI rm_reg) %{
2220 emit_opcode(cbuf,$opcode$$constant);
2221 int reg_encoding = $rm_reg$$reg;
2222 int base = $mem$$base;
2223 int index = $mem$$index;
2224 int scale = $mem$$scale;
2225 int displace = $mem$$disp + $disp_for_half$$constant;
2226 bool disp_is_oop = false;
2227 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop);
2228 %}
2229
2230 // !!!!! Special Custom Code used by MemMove, and stack access instructions !!!!!
2231 //
2232 // Clone of RegMem except the RM-byte's reg/opcode field is an ADLC-time constant
2233 // and it never needs relocation information.
2234 // Frequently used to move data between FPU's Stack Top and memory.
2235 enc_class RMopc_Mem_no_oop (immI rm_opcode, memory mem) %{
2236 int rm_byte_opcode = $rm_opcode$$constant;
2237 int base = $mem$$base;
2238 int index = $mem$$index;
2239 int scale = $mem$$scale;
2240 int displace = $mem$$disp;
2241 assert( !$mem->disp_is_oop(), "No oops here because no relo info allowed" );
2242 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, false);
2243 %}
2244
2245 enc_class RMopc_Mem (immI rm_opcode, memory mem) %{
2246 int rm_byte_opcode = $rm_opcode$$constant;
2247 int base = $mem$$base;
2248 int index = $mem$$index;
2249 int scale = $mem$$scale;
2250 int displace = $mem$$disp;
2251 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
2252 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_is_oop);
2253 %}
2254
2255 enc_class RegLea (rRegI dst, rRegI src0, immI src1 ) %{ // emit_reg_lea
2256 int reg_encoding = $dst$$reg;
2257 int base = $src0$$reg; // 0xFFFFFFFF indicates no base
2258 int index = 0x04; // 0x04 indicates no index
2259 int scale = 0x00; // 0x00 indicates no scale
2260 int displace = $src1$$constant; // 0x00 indicates no displacement
2261 bool disp_is_oop = false;
2262 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop);
2263 %}
2264
2265 enc_class min_enc (rRegI dst, rRegI src) %{ // MIN
2266 // Compare dst,src
2267 emit_opcode(cbuf,0x3B);
2268 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2269 // jmp dst < src around move
2270 emit_opcode(cbuf,0x7C);
2271 emit_d8(cbuf,2);
2272 // move dst,src
2273 emit_opcode(cbuf,0x8B);
2274 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2275 %}
2276
2277 enc_class max_enc (rRegI dst, rRegI src) %{ // MAX
2278 // Compare dst,src
2279 emit_opcode(cbuf,0x3B);
2280 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2281 // jmp dst > src around move
2282 emit_opcode(cbuf,0x7F);
2283 emit_d8(cbuf,2);
2284 // move dst,src
2285 emit_opcode(cbuf,0x8B);
2286 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg);
2287 %}
2288
2289 enc_class enc_FPR_store(memory mem, regDPR src) %{
2290 // If src is FPR1, we can just FST to store it.
2291 // Else we need to FLD it to FPR1, then FSTP to store/pop it.
2292 int reg_encoding = 0x2; // Just store
2293 int base = $mem$$base;
2294 int index = $mem$$index;
2295 int scale = $mem$$scale;
2296 int displace = $mem$$disp;
2297 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
2298 if( $src$$reg != FPR1L_enc ) {
2299 reg_encoding = 0x3; // Store & pop
2300 emit_opcode( cbuf, 0xD9 ); // FLD (i.e., push it)
2301 emit_d8( cbuf, 0xC0-1+$src$$reg );
2302 }
2303 cbuf.set_insts_mark(); // Mark start of opcode for reloc info in mem operand
2304 emit_opcode(cbuf,$primary);
2305 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop);
2306 %}
2307
2308 enc_class neg_reg(rRegI dst) %{
2309 // NEG $dst
2310 emit_opcode(cbuf,0xF7);
2311 emit_rm(cbuf, 0x3, 0x03, $dst$$reg );
2312 %}
2313
2314 enc_class setLT_reg(eCXRegI dst) %{
2315 // SETLT $dst
2316 emit_opcode(cbuf,0x0F);
2317 emit_opcode(cbuf,0x9C);
2318 emit_rm( cbuf, 0x3, 0x4, $dst$$reg );
2319 %}
2320
2321 enc_class enc_cmpLTP(ncxRegI p, ncxRegI q, ncxRegI y, eCXRegI tmp) %{ // cadd_cmpLT
2322 int tmpReg = $tmp$$reg;
2323
2324 // SUB $p,$q
2325 emit_opcode(cbuf,0x2B);
2326 emit_rm(cbuf, 0x3, $p$$reg, $q$$reg);
2327 // SBB $tmp,$tmp
2328 emit_opcode(cbuf,0x1B);
2329 emit_rm(cbuf, 0x3, tmpReg, tmpReg);
2330 // AND $tmp,$y
2331 emit_opcode(cbuf,0x23);
2332 emit_rm(cbuf, 0x3, tmpReg, $y$$reg);
2333 // ADD $p,$tmp
2334 emit_opcode(cbuf,0x03);
2335 emit_rm(cbuf, 0x3, $p$$reg, tmpReg);
2336 %}
2337
2338 enc_class shift_left_long( eRegL dst, eCXRegI shift ) %{
2339 // TEST shift,32
2340 emit_opcode(cbuf,0xF7);
2341 emit_rm(cbuf, 0x3, 0, ECX_enc);
2342 emit_d32(cbuf,0x20);
2343 // JEQ,s small
2344 emit_opcode(cbuf, 0x74);
2345 emit_d8(cbuf, 0x04);
2346 // MOV $dst.hi,$dst.lo
2347 emit_opcode( cbuf, 0x8B );
2348 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg );
2349 // CLR $dst.lo
2350 emit_opcode(cbuf, 0x33);
2351 emit_rm(cbuf, 0x3, $dst$$reg, $dst$$reg);
2352 // small:
2353 // SHLD $dst.hi,$dst.lo,$shift
2354 emit_opcode(cbuf,0x0F);
2355 emit_opcode(cbuf,0xA5);
2356 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg));
2357 // SHL $dst.lo,$shift"
2358 emit_opcode(cbuf,0xD3);
2359 emit_rm(cbuf, 0x3, 0x4, $dst$$reg );
2360 %}
2361
2362 enc_class shift_right_long( eRegL dst, eCXRegI shift ) %{
2363 // TEST shift,32
2364 emit_opcode(cbuf,0xF7);
2365 emit_rm(cbuf, 0x3, 0, ECX_enc);
2366 emit_d32(cbuf,0x20);
2367 // JEQ,s small
2368 emit_opcode(cbuf, 0x74);
2369 emit_d8(cbuf, 0x04);
2370 // MOV $dst.lo,$dst.hi
2371 emit_opcode( cbuf, 0x8B );
2372 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg) );
2373 // CLR $dst.hi
2374 emit_opcode(cbuf, 0x33);
2375 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($dst$$reg));
2376 // small:
2377 // SHRD $dst.lo,$dst.hi,$shift
2378 emit_opcode(cbuf,0x0F);
2379 emit_opcode(cbuf,0xAD);
2380 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg);
2381 // SHR $dst.hi,$shift"
2382 emit_opcode(cbuf,0xD3);
2383 emit_rm(cbuf, 0x3, 0x5, HIGH_FROM_LOW($dst$$reg) );
2384 %}
2385
2386 enc_class shift_right_arith_long( eRegL dst, eCXRegI shift ) %{
2387 // TEST shift,32
2388 emit_opcode(cbuf,0xF7);
2389 emit_rm(cbuf, 0x3, 0, ECX_enc);
2390 emit_d32(cbuf,0x20);
2391 // JEQ,s small
2392 emit_opcode(cbuf, 0x74);
2393 emit_d8(cbuf, 0x05);
2394 // MOV $dst.lo,$dst.hi
2395 emit_opcode( cbuf, 0x8B );
2396 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg) );
2397 // SAR $dst.hi,31
2398 emit_opcode(cbuf, 0xC1);
2399 emit_rm(cbuf, 0x3, 7, HIGH_FROM_LOW($dst$$reg) );
2400 emit_d8(cbuf, 0x1F );
2401 // small:
2402 // SHRD $dst.lo,$dst.hi,$shift
2403 emit_opcode(cbuf,0x0F);
2404 emit_opcode(cbuf,0xAD);
2405 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg);
2406 // SAR $dst.hi,$shift"
2407 emit_opcode(cbuf,0xD3);
2408 emit_rm(cbuf, 0x3, 0x7, HIGH_FROM_LOW($dst$$reg) );
2409 %}
2410
2411
2412 // ----------------- Encodings for floating point unit -----------------
2413 // May leave result in FPU-TOS or FPU reg depending on opcodes
2414 enc_class OpcReg_FPR(regFPR src) %{ // FMUL, FDIV
2415 $$$emit8$primary;
2416 emit_rm(cbuf, 0x3, $secondary, $src$$reg );
2417 %}
2418
2419 // Pop argument in FPR0 with FSTP ST(0)
2420 enc_class PopFPU() %{
2421 emit_opcode( cbuf, 0xDD );
2422 emit_d8( cbuf, 0xD8 );
2423 %}
2424
2425 // !!!!! equivalent to Pop_Reg_F
2426 enc_class Pop_Reg_DPR( regDPR dst ) %{
2427 emit_opcode( cbuf, 0xDD ); // FSTP ST(i)
2428 emit_d8( cbuf, 0xD8+$dst$$reg );
2429 %}
2430
2431 enc_class Push_Reg_DPR( regDPR dst ) %{
2432 emit_opcode( cbuf, 0xD9 );
2433 emit_d8( cbuf, 0xC0-1+$dst$$reg ); // FLD ST(i-1)
2434 %}
2435
2436 enc_class strictfp_bias1( regDPR dst ) %{
2437 emit_opcode( cbuf, 0xDB ); // FLD m80real
2438 emit_opcode( cbuf, 0x2D );
2439 emit_d32( cbuf, (int)StubRoutines::addr_fpu_subnormal_bias1() );
2440 emit_opcode( cbuf, 0xDE ); // FMULP ST(dst), ST0
2441 emit_opcode( cbuf, 0xC8+$dst$$reg );
2442 %}
2443
2444 enc_class strictfp_bias2( regDPR dst ) %{
2445 emit_opcode( cbuf, 0xDB ); // FLD m80real
2446 emit_opcode( cbuf, 0x2D );
2447 emit_d32( cbuf, (int)StubRoutines::addr_fpu_subnormal_bias2() );
2448 emit_opcode( cbuf, 0xDE ); // FMULP ST(dst), ST0
2449 emit_opcode( cbuf, 0xC8+$dst$$reg );
2450 %}
2451
2452 // Special case for moving an integer register to a stack slot.
2453 enc_class OpcPRegSS( stackSlotI dst, rRegI src ) %{ // RegSS
2454 store_to_stackslot( cbuf, $primary, $src$$reg, $dst$$disp );
2455 %}
2456
2457 // Special case for moving a register to a stack slot.
2458 enc_class RegSS( stackSlotI dst, rRegI src ) %{ // RegSS
2459 // Opcode already emitted
2460 emit_rm( cbuf, 0x02, $src$$reg, ESP_enc ); // R/M byte
2461 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte
2462 emit_d32(cbuf, $dst$$disp); // Displacement
2463 %}
2464
2465 // Push the integer in stackSlot 'src' onto FP-stack
2466 enc_class Push_Mem_I( memory src ) %{ // FILD [ESP+src]
2467 store_to_stackslot( cbuf, $primary, $secondary, $src$$disp );
2468 %}
2469
2470 // Push FPU's TOS float to a stack-slot, and pop FPU-stack
2471 enc_class Pop_Mem_FPR( stackSlotF dst ) %{ // FSTP_S [ESP+dst]
2472 store_to_stackslot( cbuf, 0xD9, 0x03, $dst$$disp );
2473 %}
2474
2475 // Same as Pop_Mem_F except for opcode
2476 // Push FPU's TOS double to a stack-slot, and pop FPU-stack
2477 enc_class Pop_Mem_DPR( stackSlotD dst ) %{ // FSTP_D [ESP+dst]
2478 store_to_stackslot( cbuf, 0xDD, 0x03, $dst$$disp );
2479 %}
2480
2481 enc_class Pop_Reg_FPR( regFPR dst ) %{
2482 emit_opcode( cbuf, 0xDD ); // FSTP ST(i)
2483 emit_d8( cbuf, 0xD8+$dst$$reg );
2484 %}
2485
2486 enc_class Push_Reg_FPR( regFPR dst ) %{
2487 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1)
2488 emit_d8( cbuf, 0xC0-1+$dst$$reg );
2489 %}
2490
2491 // Push FPU's float to a stack-slot, and pop FPU-stack
2492 enc_class Pop_Mem_Reg_FPR( stackSlotF dst, regFPR src ) %{
2493 int pop = 0x02;
2494 if ($src$$reg != FPR1L_enc) {
2495 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1)
2496 emit_d8( cbuf, 0xC0-1+$src$$reg );
2497 pop = 0x03;
2498 }
2499 store_to_stackslot( cbuf, 0xD9, pop, $dst$$disp ); // FST<P>_S [ESP+dst]
2500 %}
2501
2502 // Push FPU's double to a stack-slot, and pop FPU-stack
2503 enc_class Pop_Mem_Reg_DPR( stackSlotD dst, regDPR src ) %{
2504 int pop = 0x02;
2505 if ($src$$reg != FPR1L_enc) {
2506 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1)
2507 emit_d8( cbuf, 0xC0-1+$src$$reg );
2508 pop = 0x03;
2509 }
2510 store_to_stackslot( cbuf, 0xDD, pop, $dst$$disp ); // FST<P>_D [ESP+dst]
2511 %}
2512
2513 // Push FPU's double to a FPU-stack-slot, and pop FPU-stack
2514 enc_class Pop_Reg_Reg_DPR( regDPR dst, regFPR src ) %{
2515 int pop = 0xD0 - 1; // -1 since we skip FLD
2516 if ($src$$reg != FPR1L_enc) {
2517 emit_opcode( cbuf, 0xD9 ); // FLD ST(src-1)
2518 emit_d8( cbuf, 0xC0-1+$src$$reg );
2519 pop = 0xD8;
2520 }
2521 emit_opcode( cbuf, 0xDD );
2522 emit_d8( cbuf, pop+$dst$$reg ); // FST<P> ST(i)
2523 %}
2524
2525
2526 enc_class Push_Reg_Mod_DPR( regDPR dst, regDPR src) %{
2527 // load dst in FPR0
2528 emit_opcode( cbuf, 0xD9 );
2529 emit_d8( cbuf, 0xC0-1+$dst$$reg );
2530 if ($src$$reg != FPR1L_enc) {
2531 // fincstp
2532 emit_opcode (cbuf, 0xD9);
2533 emit_opcode (cbuf, 0xF7);
2534 // swap src with FPR1:
2535 // FXCH FPR1 with src
2536 emit_opcode(cbuf, 0xD9);
2537 emit_d8(cbuf, 0xC8-1+$src$$reg );
2538 // fdecstp
2539 emit_opcode (cbuf, 0xD9);
2540 emit_opcode (cbuf, 0xF6);
2541 }
2542 %}
2543
2544 enc_class Push_ModD_encoding(regD src0, regD src1) %{
2545 MacroAssembler _masm(&cbuf);
2546 __ subptr(rsp, 8);
2547 __ movdbl(Address(rsp, 0), $src1$$XMMRegister);
2548 __ fld_d(Address(rsp, 0));
2549 __ movdbl(Address(rsp, 0), $src0$$XMMRegister);
2550 __ fld_d(Address(rsp, 0));
2551 %}
2552
2553 enc_class Push_ModF_encoding(regF src0, regF src1) %{
2554 MacroAssembler _masm(&cbuf);
2555 __ subptr(rsp, 4);
2556 __ movflt(Address(rsp, 0), $src1$$XMMRegister);
2557 __ fld_s(Address(rsp, 0));
2558 __ movflt(Address(rsp, 0), $src0$$XMMRegister);
2559 __ fld_s(Address(rsp, 0));
2560 %}
2561
2562 enc_class Push_ResultD(regD dst) %{
2563 MacroAssembler _masm(&cbuf);
2564 __ fstp_d(Address(rsp, 0));
2565 __ movdbl($dst$$XMMRegister, Address(rsp, 0));
2566 __ addptr(rsp, 8);
2567 %}
2568
2569 enc_class Push_ResultF(regF dst, immI d8) %{
2570 MacroAssembler _masm(&cbuf);
2571 __ fstp_s(Address(rsp, 0));
2572 __ movflt($dst$$XMMRegister, Address(rsp, 0));
2573 __ addptr(rsp, $d8$$constant);
2574 %}
2575
2576 enc_class Push_SrcD(regD src) %{
2577 MacroAssembler _masm(&cbuf);
2578 __ subptr(rsp, 8);
2579 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
2580 __ fld_d(Address(rsp, 0));
2581 %}
2582
2583 enc_class push_stack_temp_qword() %{
2584 MacroAssembler _masm(&cbuf);
2585 __ subptr(rsp, 8);
2586 %}
2587
2588 enc_class pop_stack_temp_qword() %{
2589 MacroAssembler _masm(&cbuf);
2590 __ addptr(rsp, 8);
2591 %}
2592
2593 enc_class push_xmm_to_fpr1(regD src) %{
2594 MacroAssembler _masm(&cbuf);
2595 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
2596 __ fld_d(Address(rsp, 0));
2597 %}
2598
2599 enc_class Push_Result_Mod_DPR( regDPR src) %{
2600 if ($src$$reg != FPR1L_enc) {
2601 // fincstp
2602 emit_opcode (cbuf, 0xD9);
2603 emit_opcode (cbuf, 0xF7);
2604 // FXCH FPR1 with src
2605 emit_opcode(cbuf, 0xD9);
2606 emit_d8(cbuf, 0xC8-1+$src$$reg );
2607 // fdecstp
2608 emit_opcode (cbuf, 0xD9);
2609 emit_opcode (cbuf, 0xF6);
2610 }
2611 // // following asm replaced with Pop_Reg_F or Pop_Mem_F
2612 // // FSTP FPR$dst$$reg
2613 // emit_opcode( cbuf, 0xDD );
2614 // emit_d8( cbuf, 0xD8+$dst$$reg );
2615 %}
2616
2617 enc_class fnstsw_sahf_skip_parity() %{
2618 // fnstsw ax
2619 emit_opcode( cbuf, 0xDF );
2620 emit_opcode( cbuf, 0xE0 );
2621 // sahf
2622 emit_opcode( cbuf, 0x9E );
2623 // jnp ::skip
2624 emit_opcode( cbuf, 0x7B );
2625 emit_opcode( cbuf, 0x05 );
2626 %}
2627
2628 enc_class emitModDPR() %{
2629 // fprem must be iterative
2630 // :: loop
2631 // fprem
2632 emit_opcode( cbuf, 0xD9 );
2633 emit_opcode( cbuf, 0xF8 );
2634 // wait
2635 emit_opcode( cbuf, 0x9b );
2636 // fnstsw ax
2637 emit_opcode( cbuf, 0xDF );
2638 emit_opcode( cbuf, 0xE0 );
2639 // sahf
2640 emit_opcode( cbuf, 0x9E );
2641 // jp ::loop
2642 emit_opcode( cbuf, 0x0F );
2643 emit_opcode( cbuf, 0x8A );
2644 emit_opcode( cbuf, 0xF4 );
2645 emit_opcode( cbuf, 0xFF );
2646 emit_opcode( cbuf, 0xFF );
2647 emit_opcode( cbuf, 0xFF );
2648 %}
2649
2650 enc_class fpu_flags() %{
2651 // fnstsw_ax
2652 emit_opcode( cbuf, 0xDF);
2653 emit_opcode( cbuf, 0xE0);
2654 // test ax,0x0400
2655 emit_opcode( cbuf, 0x66 ); // operand-size prefix for 16-bit immediate
2656 emit_opcode( cbuf, 0xA9 );
2657 emit_d16 ( cbuf, 0x0400 );
2658 // // // This sequence works, but stalls for 12-16 cycles on PPro
2659 // // test rax,0x0400
2660 // emit_opcode( cbuf, 0xA9 );
2661 // emit_d32 ( cbuf, 0x00000400 );
2662 //
2663 // jz exit (no unordered comparison)
2664 emit_opcode( cbuf, 0x74 );
2665 emit_d8 ( cbuf, 0x02 );
2666 // mov ah,1 - treat as LT case (set carry flag)
2667 emit_opcode( cbuf, 0xB4 );
2668 emit_d8 ( cbuf, 0x01 );
2669 // sahf
2670 emit_opcode( cbuf, 0x9E);
2671 %}
2672
2673 enc_class cmpF_P6_fixup() %{
2674 // Fixup the integer flags in case comparison involved a NaN
2675 //
2676 // JNP exit (no unordered comparison, P-flag is set by NaN)
2677 emit_opcode( cbuf, 0x7B );
2678 emit_d8 ( cbuf, 0x03 );
2679 // MOV AH,1 - treat as LT case (set carry flag)
2680 emit_opcode( cbuf, 0xB4 );
2681 emit_d8 ( cbuf, 0x01 );
2682 // SAHF
2683 emit_opcode( cbuf, 0x9E);
2684 // NOP // target for branch to avoid branch to branch
2685 emit_opcode( cbuf, 0x90);
2686 %}
2687
2688 // fnstsw_ax();
2689 // sahf();
2690 // movl(dst, nan_result);
2691 // jcc(Assembler::parity, exit);
2692 // movl(dst, less_result);
2693 // jcc(Assembler::below, exit);
2694 // movl(dst, equal_result);
2695 // jcc(Assembler::equal, exit);
2696 // movl(dst, greater_result);
2697
2698 // less_result = 1;
2699 // greater_result = -1;
2700 // equal_result = 0;
2701 // nan_result = -1;
2702
2703 enc_class CmpF_Result(rRegI dst) %{
2704 // fnstsw_ax();
2705 emit_opcode( cbuf, 0xDF);
2706 emit_opcode( cbuf, 0xE0);
2707 // sahf
2708 emit_opcode( cbuf, 0x9E);
2709 // movl(dst, nan_result);
2710 emit_opcode( cbuf, 0xB8 + $dst$$reg);
2711 emit_d32( cbuf, -1 );
2712 // jcc(Assembler::parity, exit);
2713 emit_opcode( cbuf, 0x7A );
2714 emit_d8 ( cbuf, 0x13 );
2715 // movl(dst, less_result);
2716 emit_opcode( cbuf, 0xB8 + $dst$$reg);
2717 emit_d32( cbuf, -1 );
2718 // jcc(Assembler::below, exit);
2719 emit_opcode( cbuf, 0x72 );
2720 emit_d8 ( cbuf, 0x0C );
2721 // movl(dst, equal_result);
2722 emit_opcode( cbuf, 0xB8 + $dst$$reg);
2723 emit_d32( cbuf, 0 );
2724 // jcc(Assembler::equal, exit);
2725 emit_opcode( cbuf, 0x74 );
2726 emit_d8 ( cbuf, 0x05 );
2727 // movl(dst, greater_result);
2728 emit_opcode( cbuf, 0xB8 + $dst$$reg);
2729 emit_d32( cbuf, 1 );
2730 %}
2731
2732
2733 // Compare the longs and set flags
2734 // BROKEN! Do Not use as-is
2735 enc_class cmpl_test( eRegL src1, eRegL src2 ) %{
2736 // CMP $src1.hi,$src2.hi
2737 emit_opcode( cbuf, 0x3B );
2738 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($src1$$reg), HIGH_FROM_LOW($src2$$reg) );
2739 // JNE,s done
2740 emit_opcode(cbuf,0x75);
2741 emit_d8(cbuf, 2 );
2742 // CMP $src1.lo,$src2.lo
2743 emit_opcode( cbuf, 0x3B );
2744 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg );
2745 // done:
2746 %}
2747
2748 enc_class convert_int_long( regL dst, rRegI src ) %{
2749 // mov $dst.lo,$src
2750 int dst_encoding = $dst$$reg;
2751 int src_encoding = $src$$reg;
2752 encode_Copy( cbuf, dst_encoding , src_encoding );
2753 // mov $dst.hi,$src
2754 encode_Copy( cbuf, HIGH_FROM_LOW(dst_encoding), src_encoding );
2755 // sar $dst.hi,31
2756 emit_opcode( cbuf, 0xC1 );
2757 emit_rm(cbuf, 0x3, 7, HIGH_FROM_LOW(dst_encoding) );
2758 emit_d8(cbuf, 0x1F );
2759 %}
2760
2761 enc_class convert_long_double( eRegL src ) %{
2762 // push $src.hi
2763 emit_opcode(cbuf, 0x50+HIGH_FROM_LOW($src$$reg));
2764 // push $src.lo
2765 emit_opcode(cbuf, 0x50+$src$$reg );
2766 // fild 64-bits at [SP]
2767 emit_opcode(cbuf,0xdf);
2768 emit_d8(cbuf, 0x6C);
2769 emit_d8(cbuf, 0x24);
2770 emit_d8(cbuf, 0x00);
2771 // pop stack
2772 emit_opcode(cbuf, 0x83); // add SP, #8
2773 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
2774 emit_d8(cbuf, 0x8);
2775 %}
2776
2777 enc_class multiply_con_and_shift_high( eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32_63 cnt, eFlagsReg cr ) %{
2778 // IMUL EDX:EAX,$src1
2779 emit_opcode( cbuf, 0xF7 );
2780 emit_rm( cbuf, 0x3, 0x5, $src1$$reg );
2781 // SAR EDX,$cnt-32
2782 int shift_count = ((int)$cnt$$constant) - 32;
2783 if (shift_count > 0) {
2784 emit_opcode(cbuf, 0xC1);
2785 emit_rm(cbuf, 0x3, 7, $dst$$reg );
2786 emit_d8(cbuf, shift_count);
2787 }
2788 %}
2789
2790 // this version doesn't have add sp, 8
2791 enc_class convert_long_double2( eRegL src ) %{
2792 // push $src.hi
2793 emit_opcode(cbuf, 0x50+HIGH_FROM_LOW($src$$reg));
2794 // push $src.lo
2795 emit_opcode(cbuf, 0x50+$src$$reg );
2796 // fild 64-bits at [SP]
2797 emit_opcode(cbuf,0xdf);
2798 emit_d8(cbuf, 0x6C);
2799 emit_d8(cbuf, 0x24);
2800 emit_d8(cbuf, 0x00);
2801 %}
2802
2803 enc_class long_int_multiply( eADXRegL dst, nadxRegI src) %{
2804 // Basic idea: long = (long)int * (long)int
2805 // IMUL EDX:EAX, src
2806 emit_opcode( cbuf, 0xF7 );
2807 emit_rm( cbuf, 0x3, 0x5, $src$$reg);
2808 %}
2809
2810 enc_class long_uint_multiply( eADXRegL dst, nadxRegI src) %{
2811 // Basic Idea: long = (int & 0xffffffffL) * (int & 0xffffffffL)
2812 // MUL EDX:EAX, src
2813 emit_opcode( cbuf, 0xF7 );
2814 emit_rm( cbuf, 0x3, 0x4, $src$$reg);
2815 %}
2816
2817 enc_class long_multiply( eADXRegL dst, eRegL src, rRegI tmp ) %{
2818 // Basic idea: lo(result) = lo(x_lo * y_lo)
2819 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi)
2820 // MOV $tmp,$src.lo
2821 encode_Copy( cbuf, $tmp$$reg, $src$$reg );
2822 // IMUL $tmp,EDX
2823 emit_opcode( cbuf, 0x0F );
2824 emit_opcode( cbuf, 0xAF );
2825 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) );
2826 // MOV EDX,$src.hi
2827 encode_Copy( cbuf, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg) );
2828 // IMUL EDX,EAX
2829 emit_opcode( cbuf, 0x0F );
2830 emit_opcode( cbuf, 0xAF );
2831 emit_rm( cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg );
2832 // ADD $tmp,EDX
2833 emit_opcode( cbuf, 0x03 );
2834 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) );
2835 // MUL EDX:EAX,$src.lo
2836 emit_opcode( cbuf, 0xF7 );
2837 emit_rm( cbuf, 0x3, 0x4, $src$$reg );
2838 // ADD EDX,ESI
2839 emit_opcode( cbuf, 0x03 );
2840 emit_rm( cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $tmp$$reg );
2841 %}
2842
2843 enc_class long_multiply_con( eADXRegL dst, immL_127 src, rRegI tmp ) %{
2844 // Basic idea: lo(result) = lo(src * y_lo)
2845 // hi(result) = hi(src * y_lo) + lo(src * y_hi)
2846 // IMUL $tmp,EDX,$src
2847 emit_opcode( cbuf, 0x6B );
2848 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) );
2849 emit_d8( cbuf, (int)$src$$constant );
2850 // MOV EDX,$src
2851 emit_opcode(cbuf, 0xB8 + EDX_enc);
2852 emit_d32( cbuf, (int)$src$$constant );
2853 // MUL EDX:EAX,EDX
2854 emit_opcode( cbuf, 0xF7 );
2855 emit_rm( cbuf, 0x3, 0x4, EDX_enc );
2856 // ADD EDX,ESI
2857 emit_opcode( cbuf, 0x03 );
2858 emit_rm( cbuf, 0x3, EDX_enc, $tmp$$reg );
2859 %}
2860
2861 enc_class long_div( eRegL src1, eRegL src2 ) %{
2862 // PUSH src1.hi
2863 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src1$$reg) );
2864 // PUSH src1.lo
2865 emit_opcode(cbuf, 0x50+$src1$$reg );
2866 // PUSH src2.hi
2867 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src2$$reg) );
2868 // PUSH src2.lo
2869 emit_opcode(cbuf, 0x50+$src2$$reg );
2870 // CALL directly to the runtime
2871 cbuf.set_insts_mark();
2872 emit_opcode(cbuf,0xE8); // Call into runtime
2873 emit_d32_reloc(cbuf, (CAST_FROM_FN_PTR(address, SharedRuntime::ldiv) - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
2874 // Restore stack
2875 emit_opcode(cbuf, 0x83); // add SP, #framesize
2876 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
2877 emit_d8(cbuf, 4*4);
2878 %}
2879
2880 enc_class long_mod( eRegL src1, eRegL src2 ) %{
2881 // PUSH src1.hi
2882 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src1$$reg) );
2883 // PUSH src1.lo
2884 emit_opcode(cbuf, 0x50+$src1$$reg );
2885 // PUSH src2.hi
2886 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src2$$reg) );
2887 // PUSH src2.lo
2888 emit_opcode(cbuf, 0x50+$src2$$reg );
2889 // CALL directly to the runtime
2890 cbuf.set_insts_mark();
2891 emit_opcode(cbuf,0xE8); // Call into runtime
2892 emit_d32_reloc(cbuf, (CAST_FROM_FN_PTR(address, SharedRuntime::lrem ) - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
2893 // Restore stack
2894 emit_opcode(cbuf, 0x83); // add SP, #framesize
2895 emit_rm(cbuf, 0x3, 0x00, ESP_enc);
2896 emit_d8(cbuf, 4*4);
2897 %}
2898
2899 enc_class long_cmp_flags0( eRegL src, rRegI tmp ) %{
2900 // MOV $tmp,$src.lo
2901 emit_opcode(cbuf, 0x8B);
2902 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg);
2903 // OR $tmp,$src.hi
2904 emit_opcode(cbuf, 0x0B);
2905 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src$$reg));
2906 %}
2907
2908 enc_class long_cmp_flags1( eRegL src1, eRegL src2 ) %{
2909 // CMP $src1.lo,$src2.lo
2910 emit_opcode( cbuf, 0x3B );
2911 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg );
2912 // JNE,s skip
2913 emit_cc(cbuf, 0x70, 0x5);
2914 emit_d8(cbuf,2);
2915 // CMP $src1.hi,$src2.hi
2916 emit_opcode( cbuf, 0x3B );
2917 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($src1$$reg), HIGH_FROM_LOW($src2$$reg) );
2918 %}
2919
2920 enc_class long_cmp_flags2( eRegL src1, eRegL src2, rRegI tmp ) %{
2921 // CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits
2922 emit_opcode( cbuf, 0x3B );
2923 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg );
2924 // MOV $tmp,$src1.hi
2925 emit_opcode( cbuf, 0x8B );
2926 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src1$$reg) );
2927 // SBB $tmp,$src2.hi\t! Compute flags for long compare
2928 emit_opcode( cbuf, 0x1B );
2929 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src2$$reg) );
2930 %}
2931
2932 enc_class long_cmp_flags3( eRegL src, rRegI tmp ) %{
2933 // XOR $tmp,$tmp
2934 emit_opcode(cbuf,0x33); // XOR
2935 emit_rm(cbuf,0x3, $tmp$$reg, $tmp$$reg);
2936 // CMP $tmp,$src.lo
2937 emit_opcode( cbuf, 0x3B );
2938 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg );
2939 // SBB $tmp,$src.hi
2940 emit_opcode( cbuf, 0x1B );
2941 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src$$reg) );
2942 %}
2943
2944 // Sniff, sniff... smells like Gnu Superoptimizer
2945 enc_class neg_long( eRegL dst ) %{
2946 emit_opcode(cbuf,0xF7); // NEG hi
2947 emit_rm (cbuf,0x3, 0x3, HIGH_FROM_LOW($dst$$reg));
2948 emit_opcode(cbuf,0xF7); // NEG lo
2949 emit_rm (cbuf,0x3, 0x3, $dst$$reg );
2950 emit_opcode(cbuf,0x83); // SBB hi,0
2951 emit_rm (cbuf,0x3, 0x3, HIGH_FROM_LOW($dst$$reg));
2952 emit_d8 (cbuf,0 );
2953 %}
2954
2955
2956 // Because the transitions from emitted code to the runtime
2957 // monitorenter/exit helper stubs are so slow it's critical that
2958 // we inline both the stack-locking fast-path and the inflated fast path.
2959 //
2960 // See also: cmpFastLock and cmpFastUnlock.
2961 //
2962 // What follows is a specialized inline transliteration of the code
2963 // in slow_enter() and slow_exit(). If we're concerned about I$ bloat
2964 // another option would be to emit TrySlowEnter and TrySlowExit methods
2965 // at startup-time. These methods would accept arguments as
2966 // (rax,=Obj, rbx=Self, rcx=box, rdx=Scratch) and return success-failure
2967 // indications in the icc.ZFlag. Fast_Lock and Fast_Unlock would simply
2968 // marshal the arguments and emit calls to TrySlowEnter and TrySlowExit.
2969 // In practice, however, the # of lock sites is bounded and is usually small.
2970 // Besides the call overhead, TrySlowEnter and TrySlowExit might suffer
2971 // if the processor uses simple bimodal branch predictors keyed by EIP
2972 // Since the helper routines would be called from multiple synchronization
2973 // sites.
2974 //
2975 // An even better approach would be write "MonitorEnter()" and "MonitorExit()"
2976 // in java - using j.u.c and unsafe - and just bind the lock and unlock sites
2977 // to those specialized methods. That'd give us a mostly platform-independent
2978 // implementation that the JITs could optimize and inline at their pleasure.
2979 // Done correctly, the only time we'd need to cross to native could would be
2980 // to park() or unpark() threads. We'd also need a few more unsafe operators
2981 // to (a) prevent compiler-JIT reordering of non-volatile accesses, and
2982 // (b) explicit barriers or fence operations.
2983 //
2984 // TODO:
2985 //
2986 // * Arrange for C2 to pass "Self" into Fast_Lock and Fast_Unlock in one of the registers (scr).
2987 // This avoids manifesting the Self pointer in the Fast_Lock and Fast_Unlock terminals.
2988 // Given TLAB allocation, Self is usually manifested in a register, so passing it into
2989 // the lock operators would typically be faster than reifying Self.
2990 //
2991 // * Ideally I'd define the primitives as:
2992 // fast_lock (nax Obj, nax box, EAX tmp, nax scr) where box, tmp and scr are KILLED.
2993 // fast_unlock (nax Obj, EAX box, nax tmp) where box and tmp are KILLED
2994 // Unfortunately ADLC bugs prevent us from expressing the ideal form.
2995 // Instead, we're stuck with a rather awkward and brittle register assignments below.
2996 // Furthermore the register assignments are overconstrained, possibly resulting in
2997 // sub-optimal code near the synchronization site.
2998 //
2999 // * Eliminate the sp-proximity tests and just use "== Self" tests instead.
3000 // Alternately, use a better sp-proximity test.
3001 //
3002 // * Currently ObjectMonitor._Owner can hold either an sp value or a (THREAD *) value.
3003 // Either one is sufficient to uniquely identify a thread.
3004 // TODO: eliminate use of sp in _owner and use get_thread(tr) instead.
3005 //
3006 // * Intrinsify notify() and notifyAll() for the common cases where the
3007 // object is locked by the calling thread but the waitlist is empty.
3008 // avoid the expensive JNI call to JVM_Notify() and JVM_NotifyAll().
3009 //
3010 // * use jccb and jmpb instead of jcc and jmp to improve code density.
3011 // But beware of excessive branch density on AMD Opterons.
3012 //
3013 // * Both Fast_Lock and Fast_Unlock set the ICC.ZF to indicate success
3014 // or failure of the fast-path. If the fast-path fails then we pass
3015 // control to the slow-path, typically in C. In Fast_Lock and
3016 // Fast_Unlock we often branch to DONE_LABEL, just to find that C2
3017 // will emit a conditional branch immediately after the node.
3018 // So we have branches to branches and lots of ICC.ZF games.
3019 // Instead, it might be better to have C2 pass a "FailureLabel"
3020 // into Fast_Lock and Fast_Unlock. In the case of success, control
3021 // will drop through the node. ICC.ZF is undefined at exit.
3022 // In the case of failure, the node will branch directly to the
3023 // FailureLabel
3024
3025
3026 // obj: object to lock
3027 // box: on-stack box address (displaced header location) - KILLED
3028 // rax,: tmp -- KILLED
3029 // scr: tmp -- KILLED
3030 enc_class Fast_Lock( eRegP obj, eRegP box, eAXRegI tmp, eRegP scr ) %{
3031
3032 Register objReg = as_Register($obj$$reg);
3033 Register boxReg = as_Register($box$$reg);
3034 Register tmpReg = as_Register($tmp$$reg);
3035 Register scrReg = as_Register($scr$$reg);
3036
3037 // Ensure the register assignents are disjoint
3038 guarantee (objReg != boxReg, "") ;
3039 guarantee (objReg != tmpReg, "") ;
3040 guarantee (objReg != scrReg, "") ;
3041 guarantee (boxReg != tmpReg, "") ;
3042 guarantee (boxReg != scrReg, "") ;
3043 guarantee (tmpReg == as_Register(EAX_enc), "") ;
3044
3045 MacroAssembler masm(&cbuf);
3046
3047 if (_counters != NULL) {
3048 masm.atomic_incl(ExternalAddress((address) _counters->total_entry_count_addr()));
3049 }
3050 if (EmitSync & 1) {
3051 // set box->dhw = unused_mark (3)
3052 // Force all sync thru slow-path: slow_enter() and slow_exit()
3053 masm.movptr (Address(boxReg, 0), int32_t(markOopDesc::unused_mark())) ;
3054 masm.cmpptr (rsp, (int32_t)0) ;
3055 } else
3056 if (EmitSync & 2) {
3057 Label DONE_LABEL ;
3058 if (UseBiasedLocking) {
3059 // Note: tmpReg maps to the swap_reg argument and scrReg to the tmp_reg argument.
3060 masm.biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, _counters);
3061 }
3062
3063 masm.movptr(tmpReg, Address(objReg, 0)) ; // fetch markword
3064 masm.orptr (tmpReg, 0x1);
3065 masm.movptr(Address(boxReg, 0), tmpReg); // Anticipate successful CAS
3066 if (os::is_MP()) { masm.lock(); }
3067 masm.cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg
3068 masm.jcc(Assembler::equal, DONE_LABEL);
3069 // Recursive locking
3070 masm.subptr(tmpReg, rsp);
3071 masm.andptr(tmpReg, (int32_t) 0xFFFFF003 );
3072 masm.movptr(Address(boxReg, 0), tmpReg);
3073 masm.bind(DONE_LABEL) ;
3074 } else {
3075 // Possible cases that we'll encounter in fast_lock
3076 // ------------------------------------------------
3077 // * Inflated
3078 // -- unlocked
3079 // -- Locked
3080 // = by self
3081 // = by other
3082 // * biased
3083 // -- by Self
3084 // -- by other
3085 // * neutral
3086 // * stack-locked
3087 // -- by self
3088 // = sp-proximity test hits
3089 // = sp-proximity test generates false-negative
3090 // -- by other
3091 //
3092
3093 Label IsInflated, DONE_LABEL, PopDone ;
3094
3095 // TODO: optimize away redundant LDs of obj->mark and improve the markword triage
3096 // order to reduce the number of conditional branches in the most common cases.
3097 // Beware -- there's a subtle invariant that fetch of the markword
3098 // at [FETCH], below, will never observe a biased encoding (*101b).
3099 // If this invariant is not held we risk exclusion (safety) failure.
3100 if (UseBiasedLocking && !UseOptoBiasInlining) {
3101 masm.biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, _counters);
3102 }
3103
3104 masm.movptr(tmpReg, Address(objReg, 0)) ; // [FETCH]
3105 masm.testptr(tmpReg, 0x02) ; // Inflated v (Stack-locked or neutral)
3106 masm.jccb (Assembler::notZero, IsInflated) ;
3107
3108 // Attempt stack-locking ...
3109 masm.orptr (tmpReg, 0x1);
3110 masm.movptr(Address(boxReg, 0), tmpReg); // Anticipate successful CAS
3111 if (os::is_MP()) { masm.lock(); }
3112 masm.cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg
3113 if (_counters != NULL) {
3114 masm.cond_inc32(Assembler::equal,
3115 ExternalAddress((address)_counters->fast_path_entry_count_addr()));
3116 }
3117 masm.jccb (Assembler::equal, DONE_LABEL);
3118
3119 // Recursive locking
3120 masm.subptr(tmpReg, rsp);
3121 masm.andptr(tmpReg, 0xFFFFF003 );
3122 masm.movptr(Address(boxReg, 0), tmpReg);
3123 if (_counters != NULL) {
3124 masm.cond_inc32(Assembler::equal,
3125 ExternalAddress((address)_counters->fast_path_entry_count_addr()));
3126 }
3127 masm.jmp (DONE_LABEL) ;
3128
3129 masm.bind (IsInflated) ;
3130
3131 // The object is inflated.
3132 //
3133 // TODO-FIXME: eliminate the ugly use of manifest constants:
3134 // Use markOopDesc::monitor_value instead of "2".
3135 // use markOop::unused_mark() instead of "3".
3136 // The tmpReg value is an objectMonitor reference ORed with
3137 // markOopDesc::monitor_value (2). We can either convert tmpReg to an
3138 // objectmonitor pointer by masking off the "2" bit or we can just
3139 // use tmpReg as an objectmonitor pointer but bias the objectmonitor
3140 // field offsets with "-2" to compensate for and annul the low-order tag bit.
3141 //
3142 // I use the latter as it avoids AGI stalls.
3143 // As such, we write "mov r, [tmpReg+OFFSETOF(Owner)-2]"
3144 // instead of "mov r, [tmpReg+OFFSETOF(Owner)]".
3145 //
3146 #define OFFSET_SKEWED(f) ((ObjectMonitor::f ## _offset_in_bytes())-2)
3147
3148 // boxReg refers to the on-stack BasicLock in the current frame.
3149 // We'd like to write:
3150 // set box->_displaced_header = markOop::unused_mark(). Any non-0 value suffices.
3151 // This is convenient but results a ST-before-CAS penalty. The following CAS suffers
3152 // additional latency as we have another ST in the store buffer that must drain.
3153
3154 if (EmitSync & 8192) {
3155 masm.movptr(Address(boxReg, 0), 3) ; // results in ST-before-CAS penalty
3156 masm.get_thread (scrReg) ;
3157 masm.movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2]
3158 masm.movptr(tmpReg, NULL_WORD); // consider: xor vs mov
3159 if (os::is_MP()) { masm.lock(); }
3160 masm.cmpxchgptr(scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3161 } else
3162 if ((EmitSync & 128) == 0) { // avoid ST-before-CAS
3163 masm.movptr(scrReg, boxReg) ;
3164 masm.movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2]
3165
3166 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes
3167 if ((EmitSync & 2048) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) {
3168 // prefetchw [eax + Offset(_owner)-2]
3169 masm.prefetchw(Address(rax, ObjectMonitor::owner_offset_in_bytes()-2));
3170 }
3171
3172 if ((EmitSync & 64) == 0) {
3173 // Optimistic form: consider XORL tmpReg,tmpReg
3174 masm.movptr(tmpReg, NULL_WORD) ;
3175 } else {
3176 // Can suffer RTS->RTO upgrades on shared or cold $ lines
3177 // Test-And-CAS instead of CAS
3178 masm.movptr(tmpReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; // rax, = m->_owner
3179 masm.testptr(tmpReg, tmpReg) ; // Locked ?
3180 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3181 }
3182
3183 // Appears unlocked - try to swing _owner from null to non-null.
3184 // Ideally, I'd manifest "Self" with get_thread and then attempt
3185 // to CAS the register containing Self into m->Owner.
3186 // But we don't have enough registers, so instead we can either try to CAS
3187 // rsp or the address of the box (in scr) into &m->owner. If the CAS succeeds
3188 // we later store "Self" into m->Owner. Transiently storing a stack address
3189 // (rsp or the address of the box) into m->owner is harmless.
3190 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand.
3191 if (os::is_MP()) { masm.lock(); }
3192 masm.cmpxchgptr(scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3193 masm.movptr(Address(scrReg, 0), 3) ; // box->_displaced_header = 3
3194 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3195 masm.get_thread (scrReg) ; // beware: clobbers ICCs
3196 masm.movptr(Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2), scrReg) ;
3197 masm.xorptr(boxReg, boxReg) ; // set icc.ZFlag = 1 to indicate success
3198
3199 // If the CAS fails we can either retry or pass control to the slow-path.
3200 // We use the latter tactic.
3201 // Pass the CAS result in the icc.ZFlag into DONE_LABEL
3202 // If the CAS was successful ...
3203 // Self has acquired the lock
3204 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it.
3205 // Intentional fall-through into DONE_LABEL ...
3206 } else {
3207 masm.movptr(Address(boxReg, 0), 3) ; // results in ST-before-CAS penalty
3208 masm.movptr(boxReg, tmpReg) ;
3209
3210 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes
3211 if ((EmitSync & 2048) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) {
3212 // prefetchw [eax + Offset(_owner)-2]
3213 masm.prefetchw(Address(rax, ObjectMonitor::owner_offset_in_bytes()-2));
3214 }
3215
3216 if ((EmitSync & 64) == 0) {
3217 // Optimistic form
3218 masm.xorptr (tmpReg, tmpReg) ;
3219 } else {
3220 // Can suffer RTS->RTO upgrades on shared or cold $ lines
3221 masm.movptr(tmpReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; // rax, = m->_owner
3222 masm.testptr(tmpReg, tmpReg) ; // Locked ?
3223 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3224 }
3225
3226 // Appears unlocked - try to swing _owner from null to non-null.
3227 // Use either "Self" (in scr) or rsp as thread identity in _owner.
3228 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand.
3229 masm.get_thread (scrReg) ;
3230 if (os::is_MP()) { masm.lock(); }
3231 masm.cmpxchgptr(scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3232
3233 // If the CAS fails we can either retry or pass control to the slow-path.
3234 // We use the latter tactic.
3235 // Pass the CAS result in the icc.ZFlag into DONE_LABEL
3236 // If the CAS was successful ...
3237 // Self has acquired the lock
3238 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it.
3239 // Intentional fall-through into DONE_LABEL ...
3240 }
3241
3242 // DONE_LABEL is a hot target - we'd really like to place it at the
3243 // start of cache line by padding with NOPs.
3244 // See the AMD and Intel software optimization manuals for the
3245 // most efficient "long" NOP encodings.
3246 // Unfortunately none of our alignment mechanisms suffice.
3247 masm.bind(DONE_LABEL);
3248
3249 // Avoid branch-to-branch on AMD processors
3250 // This appears to be superstition.
3251 if (EmitSync & 32) masm.nop() ;
3252
3253
3254 // At DONE_LABEL the icc ZFlag is set as follows ...
3255 // Fast_Unlock uses the same protocol.
3256 // ZFlag == 1 -> Success
3257 // ZFlag == 0 -> Failure - force control through the slow-path
3258 }
3259 %}
3260
3261 // obj: object to unlock
3262 // box: box address (displaced header location), killed. Must be EAX.
3263 // rbx,: killed tmp; cannot be obj nor box.
3264 //
3265 // Some commentary on balanced locking:
3266 //
3267 // Fast_Lock and Fast_Unlock are emitted only for provably balanced lock sites.
3268 // Methods that don't have provably balanced locking are forced to run in the
3269 // interpreter - such methods won't be compiled to use fast_lock and fast_unlock.
3270 // The interpreter provides two properties:
3271 // I1: At return-time the interpreter automatically and quietly unlocks any
3272 // objects acquired the current activation (frame). Recall that the
3273 // interpreter maintains an on-stack list of locks currently held by
3274 // a frame.
3275 // I2: If a method attempts to unlock an object that is not held by the
3276 // the frame the interpreter throws IMSX.
3277 //
3278 // Lets say A(), which has provably balanced locking, acquires O and then calls B().
3279 // B() doesn't have provably balanced locking so it runs in the interpreter.
3280 // Control returns to A() and A() unlocks O. By I1 and I2, above, we know that O
3281 // is still locked by A().
3282 //
3283 // The only other source of unbalanced locking would be JNI. The "Java Native Interface:
3284 // Programmer's Guide and Specification" claims that an object locked by jni_monitorenter
3285 // should not be unlocked by "normal" java-level locking and vice-versa. The specification
3286 // doesn't specify what will occur if a program engages in such mixed-mode locking, however.
3287
3288 enc_class Fast_Unlock( nabxRegP obj, eAXRegP box, eRegP tmp) %{
3289
3290 Register objReg = as_Register($obj$$reg);
3291 Register boxReg = as_Register($box$$reg);
3292 Register tmpReg = as_Register($tmp$$reg);
3293
3294 guarantee (objReg != boxReg, "") ;
3295 guarantee (objReg != tmpReg, "") ;
3296 guarantee (boxReg != tmpReg, "") ;
3297 guarantee (boxReg == as_Register(EAX_enc), "") ;
3298 MacroAssembler masm(&cbuf);
3299
3300 if (EmitSync & 4) {
3301 // Disable - inhibit all inlining. Force control through the slow-path
3302 masm.cmpptr (rsp, 0) ;
3303 } else
3304 if (EmitSync & 8) {
3305 Label DONE_LABEL ;
3306 if (UseBiasedLocking) {
3307 masm.biased_locking_exit(objReg, tmpReg, DONE_LABEL);
3308 }
3309 // classic stack-locking code ...
3310 masm.movptr(tmpReg, Address(boxReg, 0)) ;
3311 masm.testptr(tmpReg, tmpReg) ;
3312 masm.jcc (Assembler::zero, DONE_LABEL) ;
3313 if (os::is_MP()) { masm.lock(); }
3314 masm.cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses EAX which is box
3315 masm.bind(DONE_LABEL);
3316 } else {
3317 Label DONE_LABEL, Stacked, CheckSucc, Inflated ;
3318
3319 // Critically, the biased locking test must have precedence over
3320 // and appear before the (box->dhw == 0) recursive stack-lock test.
3321 if (UseBiasedLocking && !UseOptoBiasInlining) {
3322 masm.biased_locking_exit(objReg, tmpReg, DONE_LABEL);
3323 }
3324
3325 masm.cmpptr(Address(boxReg, 0), 0) ; // Examine the displaced header
3326 masm.movptr(tmpReg, Address(objReg, 0)) ; // Examine the object's markword
3327 masm.jccb (Assembler::zero, DONE_LABEL) ; // 0 indicates recursive stack-lock
3328
3329 masm.testptr(tmpReg, 0x02) ; // Inflated?
3330 masm.jccb (Assembler::zero, Stacked) ;
3331
3332 masm.bind (Inflated) ;
3333 // It's inflated.
3334 // Despite our balanced locking property we still check that m->_owner == Self
3335 // as java routines or native JNI code called by this thread might
3336 // have released the lock.
3337 // Refer to the comments in synchronizer.cpp for how we might encode extra
3338 // state in _succ so we can avoid fetching EntryList|cxq.
3339 //
3340 // I'd like to add more cases in fast_lock() and fast_unlock() --
3341 // such as recursive enter and exit -- but we have to be wary of
3342 // I$ bloat, T$ effects and BP$ effects.
3343 //
3344 // If there's no contention try a 1-0 exit. That is, exit without
3345 // a costly MEMBAR or CAS. See synchronizer.cpp for details on how
3346 // we detect and recover from the race that the 1-0 exit admits.
3347 //
3348 // Conceptually Fast_Unlock() must execute a STST|LDST "release" barrier
3349 // before it STs null into _owner, releasing the lock. Updates
3350 // to data protected by the critical section must be visible before
3351 // we drop the lock (and thus before any other thread could acquire
3352 // the lock and observe the fields protected by the lock).
3353 // IA32's memory-model is SPO, so STs are ordered with respect to
3354 // each other and there's no need for an explicit barrier (fence).
3355 // See also http://gee.cs.oswego.edu/dl/jmm/cookbook.html.
3356
3357 masm.get_thread (boxReg) ;
3358 if ((EmitSync & 4096) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) {
3359 // prefetchw [ebx + Offset(_owner)-2]
3360 masm.prefetchw(Address(rbx, ObjectMonitor::owner_offset_in_bytes()-2));
3361 }
3362
3363 // Note that we could employ various encoding schemes to reduce
3364 // the number of loads below (currently 4) to just 2 or 3.
3365 // Refer to the comments in synchronizer.cpp.
3366 // In practice the chain of fetches doesn't seem to impact performance, however.
3367 if ((EmitSync & 65536) == 0 && (EmitSync & 256)) {
3368 // Attempt to reduce branch density - AMD's branch predictor.
3369 masm.xorptr(boxReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3370 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::recursions_offset_in_bytes()-2)) ;
3371 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::EntryList_offset_in_bytes()-2)) ;
3372 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::cxq_offset_in_bytes()-2)) ;
3373 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3374 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), NULL_WORD) ;
3375 masm.jmpb (DONE_LABEL) ;
3376 } else {
3377 masm.xorptr(boxReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ;
3378 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::recursions_offset_in_bytes()-2)) ;
3379 masm.jccb (Assembler::notZero, DONE_LABEL) ;
3380 masm.movptr(boxReg, Address (tmpReg, ObjectMonitor::EntryList_offset_in_bytes()-2)) ;
3381 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::cxq_offset_in_bytes()-2)) ;
3382 masm.jccb (Assembler::notZero, CheckSucc) ;
3383 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), NULL_WORD) ;
3384 masm.jmpb (DONE_LABEL) ;
3385 }
3386
3387 // The Following code fragment (EmitSync & 65536) improves the performance of
3388 // contended applications and contended synchronization microbenchmarks.
3389 // Unfortunately the emission of the code - even though not executed - causes regressions
3390 // in scimark and jetstream, evidently because of $ effects. Replacing the code
3391 // with an equal number of never-executed NOPs results in the same regression.
3392 // We leave it off by default.
3393
3394 if ((EmitSync & 65536) != 0) {
3395 Label LSuccess, LGoSlowPath ;
3396
3397 masm.bind (CheckSucc) ;
3398
3399 // Optional pre-test ... it's safe to elide this
3400 if ((EmitSync & 16) == 0) {
3401 masm.cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), 0) ;
3402 masm.jccb (Assembler::zero, LGoSlowPath) ;
3403 }
3404
3405 // We have a classic Dekker-style idiom:
3406 // ST m->_owner = 0 ; MEMBAR; LD m->_succ
3407 // There are a number of ways to implement the barrier:
3408 // (1) lock:andl &m->_owner, 0
3409 // is fast, but mask doesn't currently support the "ANDL M,IMM32" form.
3410 // LOCK: ANDL [ebx+Offset(_Owner)-2], 0
3411 // Encodes as 81 31 OFF32 IMM32 or 83 63 OFF8 IMM8
3412 // (2) If supported, an explicit MFENCE is appealing.
3413 // In older IA32 processors MFENCE is slower than lock:add or xchg
3414 // particularly if the write-buffer is full as might be the case if
3415 // if stores closely precede the fence or fence-equivalent instruction.
3416 // In more modern implementations MFENCE appears faster, however.
3417 // (3) In lieu of an explicit fence, use lock:addl to the top-of-stack
3418 // The $lines underlying the top-of-stack should be in M-state.
3419 // The locked add instruction is serializing, of course.
3420 // (4) Use xchg, which is serializing
3421 // mov boxReg, 0; xchgl boxReg, [tmpReg + Offset(_owner)-2] also works
3422 // (5) ST m->_owner = 0 and then execute lock:orl &m->_succ, 0.
3423 // The integer condition codes will tell us if succ was 0.
3424 // Since _succ and _owner should reside in the same $line and
3425 // we just stored into _owner, it's likely that the $line
3426 // remains in M-state for the lock:orl.
3427 //
3428 // We currently use (3), although it's likely that switching to (2)
3429 // is correct for the future.
3430
3431 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), NULL_WORD) ;
3432 if (os::is_MP()) {
3433 if (VM_Version::supports_sse2() && 1 == FenceInstruction) {
3434 masm.mfence();
3435 } else {
3436 masm.lock () ; masm.addptr(Address(rsp, 0), 0) ;
3437 }
3438 }
3439 // Ratify _succ remains non-null
3440 masm.cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), 0) ;
3441 masm.jccb (Assembler::notZero, LSuccess) ;
3442
3443 masm.xorptr(boxReg, boxReg) ; // box is really EAX
3444 if (os::is_MP()) { masm.lock(); }
3445 masm.cmpxchgptr(rsp, Address(tmpReg, ObjectMonitor::owner_offset_in_bytes()-2));
3446 masm.jccb (Assembler::notEqual, LSuccess) ;
3447 // Since we're low on registers we installed rsp as a placeholding in _owner.
3448 // Now install Self over rsp. This is safe as we're transitioning from
3449 // non-null to non=null
3450 masm.get_thread (boxReg) ;
3451 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), boxReg) ;
3452 // Intentional fall-through into LGoSlowPath ...
3453
3454 masm.bind (LGoSlowPath) ;
3455 masm.orptr(boxReg, 1) ; // set ICC.ZF=0 to indicate failure
3456 masm.jmpb (DONE_LABEL) ;
3457
3458 masm.bind (LSuccess) ;
3459 masm.xorptr(boxReg, boxReg) ; // set ICC.ZF=1 to indicate success
3460 masm.jmpb (DONE_LABEL) ;
3461 }
3462
3463 masm.bind (Stacked) ;
3464 // It's not inflated and it's not recursively stack-locked and it's not biased.
3465 // It must be stack-locked.
3466 // Try to reset the header to displaced header.
3467 // The "box" value on the stack is stable, so we can reload
3468 // and be assured we observe the same value as above.
3469 masm.movptr(tmpReg, Address(boxReg, 0)) ;
3470 if (os::is_MP()) { masm.lock(); }
3471 masm.cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses EAX which is box
3472 // Intention fall-thru into DONE_LABEL
3473
3474
3475 // DONE_LABEL is a hot target - we'd really like to place it at the
3476 // start of cache line by padding with NOPs.
3477 // See the AMD and Intel software optimization manuals for the
3478 // most efficient "long" NOP encodings.
3479 // Unfortunately none of our alignment mechanisms suffice.
3480 if ((EmitSync & 65536) == 0) {
3481 masm.bind (CheckSucc) ;
3482 }
3483 masm.bind(DONE_LABEL);
3484
3485 // Avoid branch to branch on AMD processors
3486 if (EmitSync & 32768) { masm.nop() ; }
3487 }
3488 %}
3489
3490
3491 enc_class enc_pop_rdx() %{
3492 emit_opcode(cbuf,0x5A);
3493 %}
3494
3495 enc_class enc_rethrow() %{
3496 cbuf.set_insts_mark();
3497 emit_opcode(cbuf, 0xE9); // jmp entry
3498 emit_d32_reloc(cbuf, (int)OptoRuntime::rethrow_stub() - ((int)cbuf.insts_end())-4,
3499 runtime_call_Relocation::spec(), RELOC_IMM32 );
3500 %}
3501
3502
3503 // Convert a double to an int. Java semantics require we do complex
3504 // manglelations in the corner cases. So we set the rounding mode to
3505 // 'zero', store the darned double down as an int, and reset the
3506 // rounding mode to 'nearest'. The hardware throws an exception which
3507 // patches up the correct value directly to the stack.
3508 enc_class DPR2I_encoding( regDPR src ) %{
3509 // Flip to round-to-zero mode. We attempted to allow invalid-op
3510 // exceptions here, so that a NAN or other corner-case value will
3511 // thrown an exception (but normal values get converted at full speed).
3512 // However, I2C adapters and other float-stack manglers leave pending
3513 // invalid-op exceptions hanging. We would have to clear them before
3514 // enabling them and that is more expensive than just testing for the
3515 // invalid value Intel stores down in the corner cases.
3516 emit_opcode(cbuf,0xD9); // FLDCW trunc
3517 emit_opcode(cbuf,0x2D);
3518 emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc());
3519 // Allocate a word
3520 emit_opcode(cbuf,0x83); // SUB ESP,4
3521 emit_opcode(cbuf,0xEC);
3522 emit_d8(cbuf,0x04);
3523 // Encoding assumes a double has been pushed into FPR0.
3524 // Store down the double as an int, popping the FPU stack
3525 emit_opcode(cbuf,0xDB); // FISTP [ESP]
3526 emit_opcode(cbuf,0x1C);
3527 emit_d8(cbuf,0x24);
3528 // Restore the rounding mode; mask the exception
3529 emit_opcode(cbuf,0xD9); // FLDCW std/24-bit mode
3530 emit_opcode(cbuf,0x2D);
3531 emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode()
3532 ? (int)StubRoutines::addr_fpu_cntrl_wrd_24()
3533 : (int)StubRoutines::addr_fpu_cntrl_wrd_std());
3534
3535 // Load the converted int; adjust CPU stack
3536 emit_opcode(cbuf,0x58); // POP EAX
3537 emit_opcode(cbuf,0x3D); // CMP EAX,imm
3538 emit_d32 (cbuf,0x80000000); // 0x80000000
3539 emit_opcode(cbuf,0x75); // JNE around_slow_call
3540 emit_d8 (cbuf,0x07); // Size of slow_call
3541 // Push src onto stack slow-path
3542 emit_opcode(cbuf,0xD9 ); // FLD ST(i)
3543 emit_d8 (cbuf,0xC0-1+$src$$reg );
3544 // CALL directly to the runtime
3545 cbuf.set_insts_mark();
3546 emit_opcode(cbuf,0xE8); // Call into runtime
3547 emit_d32_reloc(cbuf, (StubRoutines::d2i_wrapper() - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
3548 // Carry on here...
3549 %}
3550
3551 enc_class DPR2L_encoding( regDPR src ) %{
3552 emit_opcode(cbuf,0xD9); // FLDCW trunc
3553 emit_opcode(cbuf,0x2D);
3554 emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc());
3555 // Allocate a word
3556 emit_opcode(cbuf,0x83); // SUB ESP,8
3557 emit_opcode(cbuf,0xEC);
3558 emit_d8(cbuf,0x08);
3559 // Encoding assumes a double has been pushed into FPR0.
3560 // Store down the double as a long, popping the FPU stack
3561 emit_opcode(cbuf,0xDF); // FISTP [ESP]
3562 emit_opcode(cbuf,0x3C);
3563 emit_d8(cbuf,0x24);
3564 // Restore the rounding mode; mask the exception
3565 emit_opcode(cbuf,0xD9); // FLDCW std/24-bit mode
3566 emit_opcode(cbuf,0x2D);
3567 emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode()
3568 ? (int)StubRoutines::addr_fpu_cntrl_wrd_24()
3569 : (int)StubRoutines::addr_fpu_cntrl_wrd_std());
3570
3571 // Load the converted int; adjust CPU stack
3572 emit_opcode(cbuf,0x58); // POP EAX
3573 emit_opcode(cbuf,0x5A); // POP EDX
3574 emit_opcode(cbuf,0x81); // CMP EDX,imm
3575 emit_d8 (cbuf,0xFA); // rdx
3576 emit_d32 (cbuf,0x80000000); // 0x80000000
3577 emit_opcode(cbuf,0x75); // JNE around_slow_call
3578 emit_d8 (cbuf,0x07+4); // Size of slow_call
3579 emit_opcode(cbuf,0x85); // TEST EAX,EAX
3580 emit_opcode(cbuf,0xC0); // 2/rax,/rax,
3581 emit_opcode(cbuf,0x75); // JNE around_slow_call
3582 emit_d8 (cbuf,0x07); // Size of slow_call
3583 // Push src onto stack slow-path
3584 emit_opcode(cbuf,0xD9 ); // FLD ST(i)
3585 emit_d8 (cbuf,0xC0-1+$src$$reg );
3586 // CALL directly to the runtime
3587 cbuf.set_insts_mark();
3588 emit_opcode(cbuf,0xE8); // Call into runtime
3589 emit_d32_reloc(cbuf, (StubRoutines::d2l_wrapper() - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 );
3590 // Carry on here...
3591 %}
3592
3593 enc_class FMul_ST_reg( eRegFPR src1 ) %{
3594 // Operand was loaded from memory into fp ST (stack top)
3595 // FMUL ST,$src /* D8 C8+i */
3596 emit_opcode(cbuf, 0xD8);
3597 emit_opcode(cbuf, 0xC8 + $src1$$reg);
3598 %}
3599
3600 enc_class FAdd_ST_reg( eRegFPR src2 ) %{
3601 // FADDP ST,src2 /* D8 C0+i */
3602 emit_opcode(cbuf, 0xD8);
3603 emit_opcode(cbuf, 0xC0 + $src2$$reg);
3604 //could use FADDP src2,fpST /* DE C0+i */
3605 %}
3606
3607 enc_class FAddP_reg_ST( eRegFPR src2 ) %{
3608 // FADDP src2,ST /* DE C0+i */
3609 emit_opcode(cbuf, 0xDE);
3610 emit_opcode(cbuf, 0xC0 + $src2$$reg);
3611 %}
3612
3613 enc_class subFPR_divFPR_encode( eRegFPR src1, eRegFPR src2) %{
3614 // Operand has been loaded into fp ST (stack top)
3615 // FSUB ST,$src1
3616 emit_opcode(cbuf, 0xD8);
3617 emit_opcode(cbuf, 0xE0 + $src1$$reg);
3618
3619 // FDIV
3620 emit_opcode(cbuf, 0xD8);
3621 emit_opcode(cbuf, 0xF0 + $src2$$reg);
3622 %}
3623
3624 enc_class MulFAddF (eRegFPR src1, eRegFPR src2) %{
3625 // Operand was loaded from memory into fp ST (stack top)
3626 // FADD ST,$src /* D8 C0+i */
3627 emit_opcode(cbuf, 0xD8);
3628 emit_opcode(cbuf, 0xC0 + $src1$$reg);
3629
3630 // FMUL ST,src2 /* D8 C*+i */
3631 emit_opcode(cbuf, 0xD8);
3632 emit_opcode(cbuf, 0xC8 + $src2$$reg);
3633 %}
3634
3635
3636 enc_class MulFAddFreverse (eRegFPR src1, eRegFPR src2) %{
3637 // Operand was loaded from memory into fp ST (stack top)
3638 // FADD ST,$src /* D8 C0+i */
3639 emit_opcode(cbuf, 0xD8);
3640 emit_opcode(cbuf, 0xC0 + $src1$$reg);
3641
3642 // FMULP src2,ST /* DE C8+i */
3643 emit_opcode(cbuf, 0xDE);
3644 emit_opcode(cbuf, 0xC8 + $src2$$reg);
3645 %}
3646
3647 // Atomically load the volatile long
3648 enc_class enc_loadL_volatile( memory mem, stackSlotL dst ) %{
3649 emit_opcode(cbuf,0xDF);
3650 int rm_byte_opcode = 0x05;
3651 int base = $mem$$base;
3652 int index = $mem$$index;
3653 int scale = $mem$$scale;
3654 int displace = $mem$$disp;
3655 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
3656 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_is_oop);
3657 store_to_stackslot( cbuf, 0x0DF, 0x07, $dst$$disp );
3658 %}
3659
3660 // Volatile Store Long. Must be atomic, so move it into
3661 // the FP TOS and then do a 64-bit FIST. Has to probe the
3662 // target address before the store (for null-ptr checks)
3663 // so the memory operand is used twice in the encoding.
3664 enc_class enc_storeL_volatile( memory mem, stackSlotL src ) %{
3665 store_to_stackslot( cbuf, 0x0DF, 0x05, $src$$disp );
3666 cbuf.set_insts_mark(); // Mark start of FIST in case $mem has an oop
3667 emit_opcode(cbuf,0xDF);
3668 int rm_byte_opcode = 0x07;
3669 int base = $mem$$base;
3670 int index = $mem$$index;
3671 int scale = $mem$$scale;
3672 int displace = $mem$$disp;
3673 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals
3674 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_is_oop);
3675 %}
3676
3677 // Safepoint Poll. This polls the safepoint page, and causes an
3678 // exception if it is not readable. Unfortunately, it kills the condition code
3679 // in the process
3680 // We current use TESTL [spp],EDI
3681 // A better choice might be TESTB [spp + pagesize() - CacheLineSize()],0
3682
3683 enc_class Safepoint_Poll() %{
3684 cbuf.relocate(cbuf.insts_mark(), relocInfo::poll_type, 0);
3685 emit_opcode(cbuf,0x85);
3686 emit_rm (cbuf, 0x0, 0x7, 0x5);
3687 emit_d32(cbuf, (intptr_t)os::get_polling_page());
3688 %}
3689 %}
3690
3691
3692 //----------FRAME--------------------------------------------------------------
3693 // Definition of frame structure and management information.
3694 //
3695 // S T A C K L A Y O U T Allocators stack-slot number
3696 // | (to get allocators register number
3697 // G Owned by | | v add OptoReg::stack0())
3698 // r CALLER | |
3699 // o | +--------+ pad to even-align allocators stack-slot
3700 // w V | pad0 | numbers; owned by CALLER
3701 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned
3702 // h ^ | in | 5
3703 // | | args | 4 Holes in incoming args owned by SELF
3704 // | | | | 3
3705 // | | +--------+
3706 // V | | old out| Empty on Intel, window on Sparc
3707 // | old |preserve| Must be even aligned.
3708 // | SP-+--------+----> Matcher::_old_SP, even aligned
3709 // | | in | 3 area for Intel ret address
3710 // Owned by |preserve| Empty on Sparc.
3711 // SELF +--------+
3712 // | | pad2 | 2 pad to align old SP
3713 // | +--------+ 1
3714 // | | locks | 0
3715 // | +--------+----> OptoReg::stack0(), even aligned
3716 // | | pad1 | 11 pad to align new SP
3717 // | +--------+
3718 // | | | 10
3719 // | | spills | 9 spills
3720 // V | | 8 (pad0 slot for callee)
3721 // -----------+--------+----> Matcher::_out_arg_limit, unaligned
3722 // ^ | out | 7
3723 // | | args | 6 Holes in outgoing args owned by CALLEE
3724 // Owned by +--------+
3725 // CALLEE | new out| 6 Empty on Intel, window on Sparc
3726 // | new |preserve| Must be even-aligned.
3727 // | SP-+--------+----> Matcher::_new_SP, even aligned
3728 // | | |
3729 //
3730 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is
3731 // known from SELF's arguments and the Java calling convention.
3732 // Region 6-7 is determined per call site.
3733 // Note 2: If the calling convention leaves holes in the incoming argument
3734 // area, those holes are owned by SELF. Holes in the outgoing area
3735 // are owned by the CALLEE. Holes should not be nessecary in the
3736 // incoming area, as the Java calling convention is completely under
3737 // the control of the AD file. Doubles can be sorted and packed to
3738 // avoid holes. Holes in the outgoing arguments may be nessecary for
3739 // varargs C calling conventions.
3740 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is
3741 // even aligned with pad0 as needed.
3742 // Region 6 is even aligned. Region 6-7 is NOT even aligned;
3743 // region 6-11 is even aligned; it may be padded out more so that
3744 // the region from SP to FP meets the minimum stack alignment.
3745
3746 frame %{
3747 // What direction does stack grow in (assumed to be same for C & Java)
3748 stack_direction(TOWARDS_LOW);
3749
3750 // These three registers define part of the calling convention
3751 // between compiled code and the interpreter.
3752 inline_cache_reg(EAX); // Inline Cache Register
3753 interpreter_method_oop_reg(EBX); // Method Oop Register when calling interpreter
3754
3755 // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset]
3756 cisc_spilling_operand_name(indOffset32);
3757
3758 // Number of stack slots consumed by locking an object
3759 sync_stack_slots(1);
3760
3761 // Compiled code's Frame Pointer
3762 frame_pointer(ESP);
3763 // Interpreter stores its frame pointer in a register which is
3764 // stored to the stack by I2CAdaptors.
3765 // I2CAdaptors convert from interpreted java to compiled java.
3766 interpreter_frame_pointer(EBP);
3767
3768 // Stack alignment requirement
3769 // Alignment size in bytes (128-bit -> 16 bytes)
3770 stack_alignment(StackAlignmentInBytes);
3771
3772 // Number of stack slots between incoming argument block and the start of
3773 // a new frame. The PROLOG must add this many slots to the stack. The
3774 // EPILOG must remove this many slots. Intel needs one slot for
3775 // return address and one for rbp, (must save rbp)
3776 in_preserve_stack_slots(2+VerifyStackAtCalls);
3777
3778 // Number of outgoing stack slots killed above the out_preserve_stack_slots
3779 // for calls to C. Supports the var-args backing area for register parms.
3780 varargs_C_out_slots_killed(0);
3781
3782 // The after-PROLOG location of the return address. Location of
3783 // return address specifies a type (REG or STACK) and a number
3784 // representing the register number (i.e. - use a register name) or
3785 // stack slot.
3786 // Ret Addr is on stack in slot 0 if no locks or verification or alignment.
3787 // Otherwise, it is above the locks and verification slot and alignment word
3788 return_addr(STACK - 1 +
3789 round_to((Compile::current()->in_preserve_stack_slots() +
3790 Compile::current()->fixed_slots()),
3791 stack_alignment_in_slots()));
3792
3793 // Body of function which returns an integer array locating
3794 // arguments either in registers or in stack slots. Passed an array
3795 // of ideal registers called "sig" and a "length" count. Stack-slot
3796 // offsets are based on outgoing arguments, i.e. a CALLER setting up
3797 // arguments for a CALLEE. Incoming stack arguments are
3798 // automatically biased by the preserve_stack_slots field above.
3799 calling_convention %{
3800 // No difference between ingoing/outgoing just pass false
3801 SharedRuntime::java_calling_convention(sig_bt, regs, length, false);
3802 %}
3803
3804
3805 // Body of function which returns an integer array locating
3806 // arguments either in registers or in stack slots. Passed an array
3807 // of ideal registers called "sig" and a "length" count. Stack-slot
3808 // offsets are based on outgoing arguments, i.e. a CALLER setting up
3809 // arguments for a CALLEE. Incoming stack arguments are
3810 // automatically biased by the preserve_stack_slots field above.
3811 c_calling_convention %{
3812 // This is obviously always outgoing
3813 (void) SharedRuntime::c_calling_convention(sig_bt, regs, /*regs2=*/NULL, length);
3814 %}
3815
3816 // Location of C & interpreter return values
3817 c_return_value %{
3818 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
3819 static int lo[Op_RegL+1] = { 0, 0, OptoReg::Bad, EAX_num, EAX_num, FPR1L_num, FPR1L_num, EAX_num };
3820 static int hi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, FPR1H_num, EDX_num };
3821
3822 // in SSE2+ mode we want to keep the FPU stack clean so pretend
3823 // that C functions return float and double results in XMM0.
3824 if( ideal_reg == Op_RegD && UseSSE>=2 )
3825 return OptoRegPair(XMM0b_num,XMM0_num);
3826 if( ideal_reg == Op_RegF && UseSSE>=2 )
3827 return OptoRegPair(OptoReg::Bad,XMM0_num);
3828
3829 return OptoRegPair(hi[ideal_reg],lo[ideal_reg]);
3830 %}
3831
3832 // Location of return values
3833 return_value %{
3834 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
3835 static int lo[Op_RegL+1] = { 0, 0, OptoReg::Bad, EAX_num, EAX_num, FPR1L_num, FPR1L_num, EAX_num };
3836 static int hi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, FPR1H_num, EDX_num };
3837 if( ideal_reg == Op_RegD && UseSSE>=2 )
3838 return OptoRegPair(XMM0b_num,XMM0_num);
3839 if( ideal_reg == Op_RegF && UseSSE>=1 )
3840 return OptoRegPair(OptoReg::Bad,XMM0_num);
3841 return OptoRegPair(hi[ideal_reg],lo[ideal_reg]);
3842 %}
3843
3844 %}
3845
3846 //----------ATTRIBUTES---------------------------------------------------------
3847 //----------Operand Attributes-------------------------------------------------
3848 op_attrib op_cost(0); // Required cost attribute
3849
3850 //----------Instruction Attributes---------------------------------------------
3851 ins_attrib ins_cost(100); // Required cost attribute
3852 ins_attrib ins_size(8); // Required size attribute (in bits)
3853 ins_attrib ins_short_branch(0); // Required flag: is this instruction a
3854 // non-matching short branch variant of some
3855 // long branch?
3856 ins_attrib ins_alignment(1); // Required alignment attribute (must be a power of 2)
3857 // specifies the alignment that some part of the instruction (not
3858 // necessarily the start) requires. If > 1, a compute_padding()
3859 // function must be provided for the instruction
3860
3861 //----------OPERANDS-----------------------------------------------------------
3862 // Operand definitions must precede instruction definitions for correct parsing
3863 // in the ADLC because operands constitute user defined types which are used in
3864 // instruction definitions.
3865
3866 //----------Simple Operands----------------------------------------------------
3867 // Immediate Operands
3868 // Integer Immediate
3869 operand immI() %{
3870 match(ConI);
3871
3872 op_cost(10);
3873 format %{ %}
3874 interface(CONST_INTER);
3875 %}
3876
3877 // Constant for test vs zero
3878 operand immI0() %{
3879 predicate(n->get_int() == 0);
3880 match(ConI);
3881
3882 op_cost(0);
3883 format %{ %}
3884 interface(CONST_INTER);
3885 %}
3886
3887 // Constant for increment
3888 operand immI1() %{
3889 predicate(n->get_int() == 1);
3890 match(ConI);
3891
3892 op_cost(0);
3893 format %{ %}
3894 interface(CONST_INTER);
3895 %}
3896
3897 // Constant for decrement
3898 operand immI_M1() %{
3899 predicate(n->get_int() == -1);
3900 match(ConI);
3901
3902 op_cost(0);
3903 format %{ %}
3904 interface(CONST_INTER);
3905 %}
3906
3907 // Valid scale values for addressing modes
3908 operand immI2() %{
3909 predicate(0 <= n->get_int() && (n->get_int() <= 3));
3910 match(ConI);
3911
3912 format %{ %}
3913 interface(CONST_INTER);
3914 %}
3915
3916 operand immI8() %{
3917 predicate((-128 <= n->get_int()) && (n->get_int() <= 127));
3918 match(ConI);
3919
3920 op_cost(5);
3921 format %{ %}
3922 interface(CONST_INTER);
3923 %}
3924
3925 operand immI16() %{
3926 predicate((-32768 <= n->get_int()) && (n->get_int() <= 32767));
3927 match(ConI);
3928
3929 op_cost(10);
3930 format %{ %}
3931 interface(CONST_INTER);
3932 %}
3933
3934 // Int Immediate non-negative
3935 operand immU31()
3936 %{
3937 predicate(n->get_int() >= 0);
3938 match(ConI);
3939
3940 op_cost(0);
3941 format %{ %}
3942 interface(CONST_INTER);
3943 %}
3944
3945 // Constant for long shifts
3946 operand immI_32() %{
3947 predicate( n->get_int() == 32 );
3948 match(ConI);
3949
3950 op_cost(0);
3951 format %{ %}
3952 interface(CONST_INTER);
3953 %}
3954
3955 operand immI_1_31() %{
3956 predicate( n->get_int() >= 1 && n->get_int() <= 31 );
3957 match(ConI);
3958
3959 op_cost(0);
3960 format %{ %}
3961 interface(CONST_INTER);
3962 %}
3963
3964 operand immI_32_63() %{
3965 predicate( n->get_int() >= 32 && n->get_int() <= 63 );
3966 match(ConI);
3967 op_cost(0);
3968
3969 format %{ %}
3970 interface(CONST_INTER);
3971 %}
3972
3973 operand immI_1() %{
3974 predicate( n->get_int() == 1 );
3975 match(ConI);
3976
3977 op_cost(0);
3978 format %{ %}
3979 interface(CONST_INTER);
3980 %}
3981
3982 operand immI_2() %{
3983 predicate( n->get_int() == 2 );
3984 match(ConI);
3985
3986 op_cost(0);
3987 format %{ %}
3988 interface(CONST_INTER);
3989 %}
3990
3991 operand immI_3() %{
3992 predicate( n->get_int() == 3 );
3993 match(ConI);
3994
3995 op_cost(0);
3996 format %{ %}
3997 interface(CONST_INTER);
3998 %}
3999
4000 // Pointer Immediate
4001 operand immP() %{
4002 match(ConP);
4003
4004 op_cost(10);
4005 format %{ %}
4006 interface(CONST_INTER);
4007 %}
4008
4009 // NULL Pointer Immediate
4010 operand immP0() %{
4011 predicate( n->get_ptr() == 0 );
4012 match(ConP);
4013 op_cost(0);
4014
4015 format %{ %}
4016 interface(CONST_INTER);
4017 %}
4018
4019 // Long Immediate
4020 operand immL() %{
4021 match(ConL);
4022
4023 op_cost(20);
4024 format %{ %}
4025 interface(CONST_INTER);
4026 %}
4027
4028 // Long Immediate zero
4029 operand immL0() %{
4030 predicate( n->get_long() == 0L );
4031 match(ConL);
4032 op_cost(0);
4033
4034 format %{ %}
4035 interface(CONST_INTER);
4036 %}
4037
4038 // Long Immediate zero
4039 operand immL_M1() %{
4040 predicate( n->get_long() == -1L );
4041 match(ConL);
4042 op_cost(0);
4043
4044 format %{ %}
4045 interface(CONST_INTER);
4046 %}
4047
4048 // Long immediate from 0 to 127.
4049 // Used for a shorter form of long mul by 10.
4050 operand immL_127() %{
4051 predicate((0 <= n->get_long()) && (n->get_long() <= 127));
4052 match(ConL);
4053 op_cost(0);
4054
4055 format %{ %}
4056 interface(CONST_INTER);
4057 %}
4058
4059 // Long Immediate: low 32-bit mask
4060 operand immL_32bits() %{
4061 predicate(n->get_long() == 0xFFFFFFFFL);
4062 match(ConL);
4063 op_cost(0);
4064
4065 format %{ %}
4066 interface(CONST_INTER);
4067 %}
4068
4069 // Long Immediate: low 32-bit mask
4070 operand immL32() %{
4071 predicate(n->get_long() == (int)(n->get_long()));
4072 match(ConL);
4073 op_cost(20);
4074
4075 format %{ %}
4076 interface(CONST_INTER);
4077 %}
4078
4079 //Double Immediate zero
4080 operand immDPR0() %{
4081 // Do additional (and counter-intuitive) test against NaN to work around VC++
4082 // bug that generates code such that NaNs compare equal to 0.0
4083 predicate( UseSSE<=1 && n->getd() == 0.0 && !g_isnan(n->getd()) );
4084 match(ConD);
4085
4086 op_cost(5);
4087 format %{ %}
4088 interface(CONST_INTER);
4089 %}
4090
4091 // Double Immediate one
4092 operand immDPR1() %{
4093 predicate( UseSSE<=1 && n->getd() == 1.0 );
4094 match(ConD);
4095
4096 op_cost(5);
4097 format %{ %}
4098 interface(CONST_INTER);
4099 %}
4100
4101 // Double Immediate
4102 operand immDPR() %{
4103 predicate(UseSSE<=1);
4104 match(ConD);
4105
4106 op_cost(5);
4107 format %{ %}
4108 interface(CONST_INTER);
4109 %}
4110
4111 operand immD() %{
4112 predicate(UseSSE>=2);
4113 match(ConD);
4114
4115 op_cost(5);
4116 format %{ %}
4117 interface(CONST_INTER);
4118 %}
4119
4120 // Double Immediate zero
4121 operand immD0() %{
4122 // Do additional (and counter-intuitive) test against NaN to work around VC++
4123 // bug that generates code such that NaNs compare equal to 0.0 AND do not
4124 // compare equal to -0.0.
4125 predicate( UseSSE>=2 && jlong_cast(n->getd()) == 0 );
4126 match(ConD);
4127
4128 format %{ %}
4129 interface(CONST_INTER);
4130 %}
4131
4132 // Float Immediate zero
4133 operand immFPR0() %{
4134 predicate(UseSSE == 0 && n->getf() == 0.0F);
4135 match(ConF);
4136
4137 op_cost(5);
4138 format %{ %}
4139 interface(CONST_INTER);
4140 %}
4141
4142 // Float Immediate one
4143 operand immFPR1() %{
4144 predicate(UseSSE == 0 && n->getf() == 1.0F);
4145 match(ConF);
4146
4147 op_cost(5);
4148 format %{ %}
4149 interface(CONST_INTER);
4150 %}
4151
4152 // Float Immediate
4153 operand immFPR() %{
4154 predicate( UseSSE == 0 );
4155 match(ConF);
4156
4157 op_cost(5);
4158 format %{ %}
4159 interface(CONST_INTER);
4160 %}
4161
4162 // Float Immediate
4163 operand immF() %{
4164 predicate(UseSSE >= 1);
4165 match(ConF);
4166
4167 op_cost(5);
4168 format %{ %}
4169 interface(CONST_INTER);
4170 %}
4171
4172 // Float Immediate zero. Zero and not -0.0
4173 operand immF0() %{
4174 predicate( UseSSE >= 1 && jint_cast(n->getf()) == 0 );
4175 match(ConF);
4176
4177 op_cost(5);
4178 format %{ %}
4179 interface(CONST_INTER);
4180 %}
4181
4182 // Immediates for special shifts (sign extend)
4183
4184 // Constants for increment
4185 operand immI_16() %{
4186 predicate( n->get_int() == 16 );
4187 match(ConI);
4188
4189 format %{ %}
4190 interface(CONST_INTER);
4191 %}
4192
4193 operand immI_24() %{
4194 predicate( n->get_int() == 24 );
4195 match(ConI);
4196
4197 format %{ %}
4198 interface(CONST_INTER);
4199 %}
4200
4201 // Constant for byte-wide masking
4202 operand immI_255() %{
4203 predicate( n->get_int() == 255 );
4204 match(ConI);
4205
4206 format %{ %}
4207 interface(CONST_INTER);
4208 %}
4209
4210 // Constant for short-wide masking
4211 operand immI_65535() %{
4212 predicate(n->get_int() == 65535);
4213 match(ConI);
4214
4215 format %{ %}
4216 interface(CONST_INTER);
4217 %}
4218
4219 // Register Operands
4220 // Integer Register
4221 operand rRegI() %{
4222 constraint(ALLOC_IN_RC(int_reg));
4223 match(RegI);
4224 match(xRegI);
4225 match(eAXRegI);
4226 match(eBXRegI);
4227 match(eCXRegI);
4228 match(eDXRegI);
4229 match(eDIRegI);
4230 match(eSIRegI);
4231
4232 format %{ %}
4233 interface(REG_INTER);
4234 %}
4235
4236 // Subset of Integer Register
4237 operand xRegI(rRegI reg) %{
4238 constraint(ALLOC_IN_RC(int_x_reg));
4239 match(reg);
4240 match(eAXRegI);
4241 match(eBXRegI);
4242 match(eCXRegI);
4243 match(eDXRegI);
4244
4245 format %{ %}
4246 interface(REG_INTER);
4247 %}
4248
4249 // Special Registers
4250 operand eAXRegI(xRegI reg) %{
4251 constraint(ALLOC_IN_RC(eax_reg));
4252 match(reg);
4253 match(rRegI);
4254
4255 format %{ "EAX" %}
4256 interface(REG_INTER);
4257 %}
4258
4259 // Special Registers
4260 operand eBXRegI(xRegI reg) %{
4261 constraint(ALLOC_IN_RC(ebx_reg));
4262 match(reg);
4263 match(rRegI);
4264
4265 format %{ "EBX" %}
4266 interface(REG_INTER);
4267 %}
4268
4269 operand eCXRegI(xRegI reg) %{
4270 constraint(ALLOC_IN_RC(ecx_reg));
4271 match(reg);
4272 match(rRegI);
4273
4274 format %{ "ECX" %}
4275 interface(REG_INTER);
4276 %}
4277
4278 operand eDXRegI(xRegI reg) %{
4279 constraint(ALLOC_IN_RC(edx_reg));
4280 match(reg);
4281 match(rRegI);
4282
4283 format %{ "EDX" %}
4284 interface(REG_INTER);
4285 %}
4286
4287 operand eDIRegI(xRegI reg) %{
4288 constraint(ALLOC_IN_RC(edi_reg));
4289 match(reg);
4290 match(rRegI);
4291
4292 format %{ "EDI" %}
4293 interface(REG_INTER);
4294 %}
4295
4296 operand naxRegI() %{
4297 constraint(ALLOC_IN_RC(nax_reg));
4298 match(RegI);
4299 match(eCXRegI);
4300 match(eDXRegI);
4301 match(eSIRegI);
4302 match(eDIRegI);
4303
4304 format %{ %}
4305 interface(REG_INTER);
4306 %}
4307
4308 operand nadxRegI() %{
4309 constraint(ALLOC_IN_RC(nadx_reg));
4310 match(RegI);
4311 match(eBXRegI);
4312 match(eCXRegI);
4313 match(eSIRegI);
4314 match(eDIRegI);
4315
4316 format %{ %}
4317 interface(REG_INTER);
4318 %}
4319
4320 operand ncxRegI() %{
4321 constraint(ALLOC_IN_RC(ncx_reg));
4322 match(RegI);
4323 match(eAXRegI);
4324 match(eDXRegI);
4325 match(eSIRegI);
4326 match(eDIRegI);
4327
4328 format %{ %}
4329 interface(REG_INTER);
4330 %}
4331
4332 // // This operand was used by cmpFastUnlock, but conflicted with 'object' reg
4333 // //
4334 operand eSIRegI(xRegI reg) %{
4335 constraint(ALLOC_IN_RC(esi_reg));
4336 match(reg);
4337 match(rRegI);
4338
4339 format %{ "ESI" %}
4340 interface(REG_INTER);
4341 %}
4342
4343 // Pointer Register
4344 operand anyRegP() %{
4345 constraint(ALLOC_IN_RC(any_reg));
4346 match(RegP);
4347 match(eAXRegP);
4348 match(eBXRegP);
4349 match(eCXRegP);
4350 match(eDIRegP);
4351 match(eRegP);
4352
4353 format %{ %}
4354 interface(REG_INTER);
4355 %}
4356
4357 operand eRegP() %{
4358 constraint(ALLOC_IN_RC(int_reg));
4359 match(RegP);
4360 match(eAXRegP);
4361 match(eBXRegP);
4362 match(eCXRegP);
4363 match(eDIRegP);
4364
4365 format %{ %}
4366 interface(REG_INTER);
4367 %}
4368
4369 // On windows95, EBP is not safe to use for implicit null tests.
4370 operand eRegP_no_EBP() %{
4371 constraint(ALLOC_IN_RC(int_reg_no_rbp));
4372 match(RegP);
4373 match(eAXRegP);
4374 match(eBXRegP);
4375 match(eCXRegP);
4376 match(eDIRegP);
4377
4378 op_cost(100);
4379 format %{ %}
4380 interface(REG_INTER);
4381 %}
4382
4383 operand naxRegP() %{
4384 constraint(ALLOC_IN_RC(nax_reg));
4385 match(RegP);
4386 match(eBXRegP);
4387 match(eDXRegP);
4388 match(eCXRegP);
4389 match(eSIRegP);
4390 match(eDIRegP);
4391
4392 format %{ %}
4393 interface(REG_INTER);
4394 %}
4395
4396 operand nabxRegP() %{
4397 constraint(ALLOC_IN_RC(nabx_reg));
4398 match(RegP);
4399 match(eCXRegP);
4400 match(eDXRegP);
4401 match(eSIRegP);
4402 match(eDIRegP);
4403
4404 format %{ %}
4405 interface(REG_INTER);
4406 %}
4407
4408 operand pRegP() %{
4409 constraint(ALLOC_IN_RC(p_reg));
4410 match(RegP);
4411 match(eBXRegP);
4412 match(eDXRegP);
4413 match(eSIRegP);
4414 match(eDIRegP);
4415
4416 format %{ %}
4417 interface(REG_INTER);
4418 %}
4419
4420 // Special Registers
4421 // Return a pointer value
4422 operand eAXRegP(eRegP reg) %{
4423 constraint(ALLOC_IN_RC(eax_reg));
4424 match(reg);
4425 format %{ "EAX" %}
4426 interface(REG_INTER);
4427 %}
4428
4429 // Used in AtomicAdd
4430 operand eBXRegP(eRegP reg) %{
4431 constraint(ALLOC_IN_RC(ebx_reg));
4432 match(reg);
4433 format %{ "EBX" %}
4434 interface(REG_INTER);
4435 %}
4436
4437 // Tail-call (interprocedural jump) to interpreter
4438 operand eCXRegP(eRegP reg) %{
4439 constraint(ALLOC_IN_RC(ecx_reg));
4440 match(reg);
4441 format %{ "ECX" %}
4442 interface(REG_INTER);
4443 %}
4444
4445 operand eSIRegP(eRegP reg) %{
4446 constraint(ALLOC_IN_RC(esi_reg));
4447 match(reg);
4448 format %{ "ESI" %}
4449 interface(REG_INTER);
4450 %}
4451
4452 // Used in rep stosw
4453 operand eDIRegP(eRegP reg) %{
4454 constraint(ALLOC_IN_RC(edi_reg));
4455 match(reg);
4456 format %{ "EDI" %}
4457 interface(REG_INTER);
4458 %}
4459
4460 operand eBPRegP() %{
4461 constraint(ALLOC_IN_RC(ebp_reg));
4462 match(RegP);
4463 format %{ "EBP" %}
4464 interface(REG_INTER);
4465 %}
4466
4467 operand eRegL() %{
4468 constraint(ALLOC_IN_RC(long_reg));
4469 match(RegL);
4470 match(eADXRegL);
4471
4472 format %{ %}
4473 interface(REG_INTER);
4474 %}
4475
4476 operand eADXRegL( eRegL reg ) %{
4477 constraint(ALLOC_IN_RC(eadx_reg));
4478 match(reg);
4479
4480 format %{ "EDX:EAX" %}
4481 interface(REG_INTER);
4482 %}
4483
4484 operand eBCXRegL( eRegL reg ) %{
4485 constraint(ALLOC_IN_RC(ebcx_reg));
4486 match(reg);
4487
4488 format %{ "EBX:ECX" %}
4489 interface(REG_INTER);
4490 %}
4491
4492 // Special case for integer high multiply
4493 operand eADXRegL_low_only() %{
4494 constraint(ALLOC_IN_RC(eadx_reg));
4495 match(RegL);
4496
4497 format %{ "EAX" %}
4498 interface(REG_INTER);
4499 %}
4500
4501 // Flags register, used as output of compare instructions
4502 operand eFlagsReg() %{
4503 constraint(ALLOC_IN_RC(int_flags));
4504 match(RegFlags);
4505
4506 format %{ "EFLAGS" %}
4507 interface(REG_INTER);
4508 %}
4509
4510 // Flags register, used as output of FLOATING POINT compare instructions
4511 operand eFlagsRegU() %{
4512 constraint(ALLOC_IN_RC(int_flags));
4513 match(RegFlags);
4514
4515 format %{ "EFLAGS_U" %}
4516 interface(REG_INTER);
4517 %}
4518
4519 operand eFlagsRegUCF() %{
4520 constraint(ALLOC_IN_RC(int_flags));
4521 match(RegFlags);
4522 predicate(false);
4523
4524 format %{ "EFLAGS_U_CF" %}
4525 interface(REG_INTER);
4526 %}
4527
4528 // Condition Code Register used by long compare
4529 operand flagsReg_long_LTGE() %{
4530 constraint(ALLOC_IN_RC(int_flags));
4531 match(RegFlags);
4532 format %{ "FLAGS_LTGE" %}
4533 interface(REG_INTER);
4534 %}
4535 operand flagsReg_long_EQNE() %{
4536 constraint(ALLOC_IN_RC(int_flags));
4537 match(RegFlags);
4538 format %{ "FLAGS_EQNE" %}
4539 interface(REG_INTER);
4540 %}
4541 operand flagsReg_long_LEGT() %{
4542 constraint(ALLOC_IN_RC(int_flags));
4543 match(RegFlags);
4544 format %{ "FLAGS_LEGT" %}
4545 interface(REG_INTER);
4546 %}
4547
4548 // Condition Code Register used by unsigned long compare
4549 operand flagsReg_ulong_LTGE() %{
4550 constraint(ALLOC_IN_RC(int_flags));
4551 match(RegFlags);
4552 format %{ "FLAGS_U_LTGE" %}
4553 interface(REG_INTER);
4554 %}
4555 operand flagsReg_ulong_EQNE() %{
4556 constraint(ALLOC_IN_RC(int_flags));
4557 match(RegFlags);
4558 format %{ "FLAGS_U_EQNE" %}
4559 interface(REG_INTER);
4560 %}
4561 operand flagsReg_ulong_LEGT() %{
4562 constraint(ALLOC_IN_RC(int_flags));
4563 match(RegFlags);
4564 format %{ "FLAGS_U_LEGT" %}
4565 interface(REG_INTER);
4566 %}
4567
4568 // Float register operands
4569 operand regDPR() %{
4570 predicate( UseSSE < 2 );
4571 constraint(ALLOC_IN_RC(fp_dbl_reg));
4572 match(RegD);
4573 match(regDPR1);
4574 match(regDPR2);
4575 format %{ %}
4576 interface(REG_INTER);
4577 %}
4578
4579 operand regDPR1(regDPR reg) %{
4580 predicate( UseSSE < 2 );
4581 constraint(ALLOC_IN_RC(fp_dbl_reg0));
4582 match(reg);
4583 format %{ "FPR1" %}
4584 interface(REG_INTER);
4585 %}
4586
4587 operand regDPR2(regDPR reg) %{
4588 predicate( UseSSE < 2 );
4589 constraint(ALLOC_IN_RC(fp_dbl_reg1));
4590 match(reg);
4591 format %{ "FPR2" %}
4592 interface(REG_INTER);
4593 %}
4594
4595 operand regnotDPR1(regDPR reg) %{
4596 predicate( UseSSE < 2 );
4597 constraint(ALLOC_IN_RC(fp_dbl_notreg0));
4598 match(reg);
4599 format %{ %}
4600 interface(REG_INTER);
4601 %}
4602
4603 // Float register operands
4604 operand regFPR() %{
4605 predicate( UseSSE < 2 );
4606 constraint(ALLOC_IN_RC(fp_flt_reg));
4607 match(RegF);
4608 match(regFPR1);
4609 format %{ %}
4610 interface(REG_INTER);
4611 %}
4612
4613 // Float register operands
4614 operand regFPR1(regFPR reg) %{
4615 predicate( UseSSE < 2 );
4616 constraint(ALLOC_IN_RC(fp_flt_reg0));
4617 match(reg);
4618 format %{ "FPR1" %}
4619 interface(REG_INTER);
4620 %}
4621
4622 // XMM Float register operands
4623 operand regF() %{
4624 predicate( UseSSE>=1 );
4625 constraint(ALLOC_IN_RC(float_reg));
4626 match(RegF);
4627 format %{ %}
4628 interface(REG_INTER);
4629 %}
4630
4631 // XMM Double register operands
4632 operand regD() %{
4633 predicate( UseSSE>=2 );
4634 constraint(ALLOC_IN_RC(double_reg));
4635 match(RegD);
4636 format %{ %}
4637 interface(REG_INTER);
4638 %}
4639
4640
4641 //----------Memory Operands----------------------------------------------------
4642 // Direct Memory Operand
4643 operand direct(immP addr) %{
4644 match(addr);
4645
4646 format %{ "[$addr]" %}
4647 interface(MEMORY_INTER) %{
4648 base(0xFFFFFFFF);
4649 index(0x4);
4650 scale(0x0);
4651 disp($addr);
4652 %}
4653 %}
4654
4655 // Indirect Memory Operand
4656 operand indirect(eRegP reg) %{
4657 constraint(ALLOC_IN_RC(int_reg));
4658 match(reg);
4659
4660 format %{ "[$reg]" %}
4661 interface(MEMORY_INTER) %{
4662 base($reg);
4663 index(0x4);
4664 scale(0x0);
4665 disp(0x0);
4666 %}
4667 %}
4668
4669 // Indirect Memory Plus Short Offset Operand
4670 operand indOffset8(eRegP reg, immI8 off) %{
4671 match(AddP reg off);
4672
4673 format %{ "[$reg + $off]" %}
4674 interface(MEMORY_INTER) %{
4675 base($reg);
4676 index(0x4);
4677 scale(0x0);
4678 disp($off);
4679 %}
4680 %}
4681
4682 // Indirect Memory Plus Long Offset Operand
4683 operand indOffset32(eRegP reg, immI off) %{
4684 match(AddP reg off);
4685
4686 format %{ "[$reg + $off]" %}
4687 interface(MEMORY_INTER) %{
4688 base($reg);
4689 index(0x4);
4690 scale(0x0);
4691 disp($off);
4692 %}
4693 %}
4694
4695 // Indirect Memory Plus Long Offset Operand
4696 operand indOffset32X(rRegI reg, immP off) %{
4697 match(AddP off reg);
4698
4699 format %{ "[$reg + $off]" %}
4700 interface(MEMORY_INTER) %{
4701 base($reg);
4702 index(0x4);
4703 scale(0x0);
4704 disp($off);
4705 %}
4706 %}
4707
4708 // Indirect Memory Plus Index Register Plus Offset Operand
4709 operand indIndexOffset(eRegP reg, rRegI ireg, immI off) %{
4710 match(AddP (AddP reg ireg) off);
4711
4712 op_cost(10);
4713 format %{"[$reg + $off + $ireg]" %}
4714 interface(MEMORY_INTER) %{
4715 base($reg);
4716 index($ireg);
4717 scale(0x0);
4718 disp($off);
4719 %}
4720 %}
4721
4722 // Indirect Memory Plus Index Register Plus Offset Operand
4723 operand indIndex(eRegP reg, rRegI ireg) %{
4724 match(AddP reg ireg);
4725
4726 op_cost(10);
4727 format %{"[$reg + $ireg]" %}
4728 interface(MEMORY_INTER) %{
4729 base($reg);
4730 index($ireg);
4731 scale(0x0);
4732 disp(0x0);
4733 %}
4734 %}
4735
4736 // // -------------------------------------------------------------------------
4737 // // 486 architecture doesn't support "scale * index + offset" with out a base
4738 // // -------------------------------------------------------------------------
4739 // // Scaled Memory Operands
4740 // // Indirect Memory Times Scale Plus Offset Operand
4741 // operand indScaleOffset(immP off, rRegI ireg, immI2 scale) %{
4742 // match(AddP off (LShiftI ireg scale));
4743 //
4744 // op_cost(10);
4745 // format %{"[$off + $ireg << $scale]" %}
4746 // interface(MEMORY_INTER) %{
4747 // base(0x4);
4748 // index($ireg);
4749 // scale($scale);
4750 // disp($off);
4751 // %}
4752 // %}
4753
4754 // Indirect Memory Times Scale Plus Index Register
4755 operand indIndexScale(eRegP reg, rRegI ireg, immI2 scale) %{
4756 match(AddP reg (LShiftI ireg scale));
4757
4758 op_cost(10);
4759 format %{"[$reg + $ireg << $scale]" %}
4760 interface(MEMORY_INTER) %{
4761 base($reg);
4762 index($ireg);
4763 scale($scale);
4764 disp(0x0);
4765 %}
4766 %}
4767
4768 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
4769 operand indIndexScaleOffset(eRegP reg, immI off, rRegI ireg, immI2 scale) %{
4770 match(AddP (AddP reg (LShiftI ireg scale)) off);
4771
4772 op_cost(10);
4773 format %{"[$reg + $off + $ireg << $scale]" %}
4774 interface(MEMORY_INTER) %{
4775 base($reg);
4776 index($ireg);
4777 scale($scale);
4778 disp($off);
4779 %}
4780 %}
4781
4782 //----------Load Long Memory Operands------------------------------------------
4783 // The load-long idiom will use it's address expression again after loading
4784 // the first word of the long. If the load-long destination overlaps with
4785 // registers used in the addressing expression, the 2nd half will be loaded
4786 // from a clobbered address. Fix this by requiring that load-long use
4787 // address registers that do not overlap with the load-long target.
4788
4789 // load-long support
4790 operand load_long_RegP() %{
4791 constraint(ALLOC_IN_RC(esi_reg));
4792 match(RegP);
4793 match(eSIRegP);
4794 op_cost(100);
4795 format %{ %}
4796 interface(REG_INTER);
4797 %}
4798
4799 // Indirect Memory Operand Long
4800 operand load_long_indirect(load_long_RegP reg) %{
4801 constraint(ALLOC_IN_RC(esi_reg));
4802 match(reg);
4803
4804 format %{ "[$reg]" %}
4805 interface(MEMORY_INTER) %{
4806 base($reg);
4807 index(0x4);
4808 scale(0x0);
4809 disp(0x0);
4810 %}
4811 %}
4812
4813 // Indirect Memory Plus Long Offset Operand
4814 operand load_long_indOffset32(load_long_RegP reg, immI off) %{
4815 match(AddP reg off);
4816
4817 format %{ "[$reg + $off]" %}
4818 interface(MEMORY_INTER) %{
4819 base($reg);
4820 index(0x4);
4821 scale(0x0);
4822 disp($off);
4823 %}
4824 %}
4825
4826 opclass load_long_memory(load_long_indirect, load_long_indOffset32);
4827
4828
4829 //----------Special Memory Operands--------------------------------------------
4830 // Stack Slot Operand - This operand is used for loading and storing temporary
4831 // values on the stack where a match requires a value to
4832 // flow through memory.
4833 operand stackSlotP(sRegP reg) %{
4834 constraint(ALLOC_IN_RC(stack_slots));
4835 // No match rule because this operand is only generated in matching
4836 format %{ "[$reg]" %}
4837 interface(MEMORY_INTER) %{
4838 base(0x4); // ESP
4839 index(0x4); // No Index
4840 scale(0x0); // No Scale
4841 disp($reg); // Stack Offset
4842 %}
4843 %}
4844
4845 operand stackSlotI(sRegI reg) %{
4846 constraint(ALLOC_IN_RC(stack_slots));
4847 // No match rule because this operand is only generated in matching
4848 format %{ "[$reg]" %}
4849 interface(MEMORY_INTER) %{
4850 base(0x4); // ESP
4851 index(0x4); // No Index
4852 scale(0x0); // No Scale
4853 disp($reg); // Stack Offset
4854 %}
4855 %}
4856
4857 operand stackSlotF(sRegF reg) %{
4858 constraint(ALLOC_IN_RC(stack_slots));
4859 // No match rule because this operand is only generated in matching
4860 format %{ "[$reg]" %}
4861 interface(MEMORY_INTER) %{
4862 base(0x4); // ESP
4863 index(0x4); // No Index
4864 scale(0x0); // No Scale
4865 disp($reg); // Stack Offset
4866 %}
4867 %}
4868
4869 operand stackSlotD(sRegD reg) %{
4870 constraint(ALLOC_IN_RC(stack_slots));
4871 // No match rule because this operand is only generated in matching
4872 format %{ "[$reg]" %}
4873 interface(MEMORY_INTER) %{
4874 base(0x4); // ESP
4875 index(0x4); // No Index
4876 scale(0x0); // No Scale
4877 disp($reg); // Stack Offset
4878 %}
4879 %}
4880
4881 operand stackSlotL(sRegL reg) %{
4882 constraint(ALLOC_IN_RC(stack_slots));
4883 // No match rule because this operand is only generated in matching
4884 format %{ "[$reg]" %}
4885 interface(MEMORY_INTER) %{
4886 base(0x4); // ESP
4887 index(0x4); // No Index
4888 scale(0x0); // No Scale
4889 disp($reg); // Stack Offset
4890 %}
4891 %}
4892
4893 //----------Memory Operands - Win95 Implicit Null Variants----------------
4894 // Indirect Memory Operand
4895 operand indirect_win95_safe(eRegP_no_EBP reg)
4896 %{
4897 constraint(ALLOC_IN_RC(int_reg));
4898 match(reg);
4899
4900 op_cost(100);
4901 format %{ "[$reg]" %}
4902 interface(MEMORY_INTER) %{
4903 base($reg);
4904 index(0x4);
4905 scale(0x0);
4906 disp(0x0);
4907 %}
4908 %}
4909
4910 // Indirect Memory Plus Short Offset Operand
4911 operand indOffset8_win95_safe(eRegP_no_EBP reg, immI8 off)
4912 %{
4913 match(AddP reg off);
4914
4915 op_cost(100);
4916 format %{ "[$reg + $off]" %}
4917 interface(MEMORY_INTER) %{
4918 base($reg);
4919 index(0x4);
4920 scale(0x0);
4921 disp($off);
4922 %}
4923 %}
4924
4925 // Indirect Memory Plus Long Offset Operand
4926 operand indOffset32_win95_safe(eRegP_no_EBP reg, immI off)
4927 %{
4928 match(AddP reg off);
4929
4930 op_cost(100);
4931 format %{ "[$reg + $off]" %}
4932 interface(MEMORY_INTER) %{
4933 base($reg);
4934 index(0x4);
4935 scale(0x0);
4936 disp($off);
4937 %}
4938 %}
4939
4940 // Indirect Memory Plus Index Register Plus Offset Operand
4941 operand indIndexOffset_win95_safe(eRegP_no_EBP reg, rRegI ireg, immI off)
4942 %{
4943 match(AddP (AddP reg ireg) off);
4944
4945 op_cost(100);
4946 format %{"[$reg + $off + $ireg]" %}
4947 interface(MEMORY_INTER) %{
4948 base($reg);
4949 index($ireg);
4950 scale(0x0);
4951 disp($off);
4952 %}
4953 %}
4954
4955 // Indirect Memory Times Scale Plus Index Register
4956 operand indIndexScale_win95_safe(eRegP_no_EBP reg, rRegI ireg, immI2 scale)
4957 %{
4958 match(AddP reg (LShiftI ireg scale));
4959
4960 op_cost(100);
4961 format %{"[$reg + $ireg << $scale]" %}
4962 interface(MEMORY_INTER) %{
4963 base($reg);
4964 index($ireg);
4965 scale($scale);
4966 disp(0x0);
4967 %}
4968 %}
4969
4970 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
4971 operand indIndexScaleOffset_win95_safe(eRegP_no_EBP reg, immI off, rRegI ireg, immI2 scale)
4972 %{
4973 match(AddP (AddP reg (LShiftI ireg scale)) off);
4974
4975 op_cost(100);
4976 format %{"[$reg + $off + $ireg << $scale]" %}
4977 interface(MEMORY_INTER) %{
4978 base($reg);
4979 index($ireg);
4980 scale($scale);
4981 disp($off);
4982 %}
4983 %}
4984
4985 //----------Conditional Branch Operands----------------------------------------
4986 // Comparison Op - This is the operation of the comparison, and is limited to
4987 // the following set of codes:
4988 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
4989 //
4990 // Other attributes of the comparison, such as unsignedness, are specified
4991 // by the comparison instruction that sets a condition code flags register.
4992 // That result is represented by a flags operand whose subtype is appropriate
4993 // to the unsignedness (etc.) of the comparison.
4994 //
4995 // Later, the instruction which matches both the Comparison Op (a Bool) and
4996 // the flags (produced by the Cmp) specifies the coding of the comparison op
4997 // by matching a specific subtype of Bool operand below, such as cmpOpU.
4998
4999 // Comparision Code
5000 operand cmpOp() %{
5001 match(Bool);
5002
5003 format %{ "" %}
5004 interface(COND_INTER) %{
5005 equal(0x4, "e");
5006 not_equal(0x5, "ne");
5007 less(0xC, "l");
5008 greater_equal(0xD, "ge");
5009 less_equal(0xE, "le");
5010 greater(0xF, "g");
5011 %}
5012 %}
5013
5014 // Comparison Code, unsigned compare. Used by FP also, with
5015 // C2 (unordered) turned into GT or LT already. The other bits
5016 // C0 and C3 are turned into Carry & Zero flags.
5017 operand cmpOpU() %{
5018 match(Bool);
5019
5020 format %{ "" %}
5021 interface(COND_INTER) %{
5022 equal(0x4, "e");
5023 not_equal(0x5, "ne");
5024 less(0x2, "b");
5025 greater_equal(0x3, "nb");
5026 less_equal(0x6, "be");
5027 greater(0x7, "nbe");
5028 %}
5029 %}
5030
5031 // Floating comparisons that don't require any fixup for the unordered case
5032 operand cmpOpUCF() %{
5033 match(Bool);
5034 predicate(n->as_Bool()->_test._test == BoolTest::lt ||
5035 n->as_Bool()->_test._test == BoolTest::ge ||
5036 n->as_Bool()->_test._test == BoolTest::le ||
5037 n->as_Bool()->_test._test == BoolTest::gt);
5038 format %{ "" %}
5039 interface(COND_INTER) %{
5040 equal(0x4, "e");
5041 not_equal(0x5, "ne");
5042 less(0x2, "b");
5043 greater_equal(0x3, "nb");
5044 less_equal(0x6, "be");
5045 greater(0x7, "nbe");
5046 %}
5047 %}
5048
5049
5050 // Floating comparisons that can be fixed up with extra conditional jumps
5051 operand cmpOpUCF2() %{
5052 match(Bool);
5053 predicate(n->as_Bool()->_test._test == BoolTest::ne ||
5054 n->as_Bool()->_test._test == BoolTest::eq);
5055 format %{ "" %}
5056 interface(COND_INTER) %{
5057 equal(0x4, "e");
5058 not_equal(0x5, "ne");
5059 less(0x2, "b");
5060 greater_equal(0x3, "nb");
5061 less_equal(0x6, "be");
5062 greater(0x7, "nbe");
5063 %}
5064 %}
5065
5066 // Comparison Code for FP conditional move
5067 operand cmpOp_fcmov() %{
5068 match(Bool);
5069
5070 format %{ "" %}
5071 interface(COND_INTER) %{
5072 equal (0x0C8);
5073 not_equal (0x1C8);
5074 less (0x0C0);
5075 greater_equal(0x1C0);
5076 less_equal (0x0D0);
5077 greater (0x1D0);
5078 %}
5079 %}
5080
5081 // Comparison Code used in long compares
5082 operand cmpOp_commute() %{
5083 match(Bool);
5084
5085 format %{ "" %}
5086 interface(COND_INTER) %{
5087 equal(0x4, "e");
5088 not_equal(0x5, "ne");
5089 less(0xF, "g");
5090 greater_equal(0xE, "le");
5091 less_equal(0xD, "ge");
5092 greater(0xC, "l");
5093 %}
5094 %}
5095
5096 // Comparison Code used in unsigned long compares
5097 operand cmpOpU_commute() %{
5098 match(Bool);
5099
5100 format %{ "" %}
5101 interface(COND_INTER) %{
5102 equal(0x4, "e");
5103 not_equal(0x5, "ne");
5104 less(0x7, "nbe");
5105 greater_equal(0x6, "be");
5106 less_equal(0x3, "nb");
5107 greater(0x2, "b");
5108 %}
5109 %}
5110
5111 //----------OPERAND CLASSES----------------------------------------------------
5112 // Operand Classes are groups of operands that are used as to simplify
5113 // instruction definitions by not requiring the AD writer to specify separate
5114 // instructions for every form of operand when the instruction accepts
5115 // multiple operand types with the same basic encoding and format. The classic
5116 // case of this is memory operands.
5117
5118 opclass memory(direct, indirect, indOffset8, indOffset32, indOffset32X, indIndexOffset,
5119 indIndex, indIndexScale, indIndexScaleOffset);
5120
5121 // Long memory operations are encoded in 2 instructions and a +4 offset.
5122 // This means some kind of offset is always required and you cannot use
5123 // an oop as the offset (done when working on static globals).
5124 opclass long_memory(direct, indirect, indOffset8, indOffset32, indIndexOffset,
5125 indIndex, indIndexScale, indIndexScaleOffset);
5126
5127
5128 //----------PIPELINE-----------------------------------------------------------
5129 // Rules which define the behavior of the target architectures pipeline.
5130 pipeline %{
5131
5132 //----------ATTRIBUTES---------------------------------------------------------
5133 attributes %{
5134 variable_size_instructions; // Fixed size instructions
5135 max_instructions_per_bundle = 3; // Up to 3 instructions per bundle
5136 instruction_unit_size = 1; // An instruction is 1 bytes long
5137 instruction_fetch_unit_size = 16; // The processor fetches one line
5138 instruction_fetch_units = 1; // of 16 bytes
5139
5140 // List of nop instructions
5141 nops( MachNop );
5142 %}
5143
5144 //----------RESOURCES----------------------------------------------------------
5145 // Resources are the functional units available to the machine
5146
5147 // Generic P2/P3 pipeline
5148 // 3 decoders, only D0 handles big operands; a "bundle" is the limit of
5149 // 3 instructions decoded per cycle.
5150 // 2 load/store ops per cycle, 1 branch, 1 FPU,
5151 // 2 ALU op, only ALU0 handles mul/div instructions.
5152 resources( D0, D1, D2, DECODE = D0 | D1 | D2,
5153 MS0, MS1, MEM = MS0 | MS1,
5154 BR, FPU,
5155 ALU0, ALU1, ALU = ALU0 | ALU1 );
5156
5157 //----------PIPELINE DESCRIPTION-----------------------------------------------
5158 // Pipeline Description specifies the stages in the machine's pipeline
5159
5160 // Generic P2/P3 pipeline
5161 pipe_desc(S0, S1, S2, S3, S4, S5);
5162
5163 //----------PIPELINE CLASSES---------------------------------------------------
5164 // Pipeline Classes describe the stages in which input and output are
5165 // referenced by the hardware pipeline.
5166
5167 // Naming convention: ialu or fpu
5168 // Then: _reg
5169 // Then: _reg if there is a 2nd register
5170 // Then: _long if it's a pair of instructions implementing a long
5171 // Then: _fat if it requires the big decoder
5172 // Or: _mem if it requires the big decoder and a memory unit.
5173
5174 // Integer ALU reg operation
5175 pipe_class ialu_reg(rRegI dst) %{
5176 single_instruction;
5177 dst : S4(write);
5178 dst : S3(read);
5179 DECODE : S0; // any decoder
5180 ALU : S3; // any alu
5181 %}
5182
5183 // Long ALU reg operation
5184 pipe_class ialu_reg_long(eRegL dst) %{
5185 instruction_count(2);
5186 dst : S4(write);
5187 dst : S3(read);
5188 DECODE : S0(2); // any 2 decoders
5189 ALU : S3(2); // both alus
5190 %}
5191
5192 // Integer ALU reg operation using big decoder
5193 pipe_class ialu_reg_fat(rRegI dst) %{
5194 single_instruction;
5195 dst : S4(write);
5196 dst : S3(read);
5197 D0 : S0; // big decoder only
5198 ALU : S3; // any alu
5199 %}
5200
5201 // Long ALU reg operation using big decoder
5202 pipe_class ialu_reg_long_fat(eRegL dst) %{
5203 instruction_count(2);
5204 dst : S4(write);
5205 dst : S3(read);
5206 D0 : S0(2); // big decoder only; twice
5207 ALU : S3(2); // any 2 alus
5208 %}
5209
5210 // Integer ALU reg-reg operation
5211 pipe_class ialu_reg_reg(rRegI dst, rRegI src) %{
5212 single_instruction;
5213 dst : S4(write);
5214 src : S3(read);
5215 DECODE : S0; // any decoder
5216 ALU : S3; // any alu
5217 %}
5218
5219 // Long ALU reg-reg operation
5220 pipe_class ialu_reg_reg_long(eRegL dst, eRegL src) %{
5221 instruction_count(2);
5222 dst : S4(write);
5223 src : S3(read);
5224 DECODE : S0(2); // any 2 decoders
5225 ALU : S3(2); // both alus
5226 %}
5227
5228 // Integer ALU reg-reg operation
5229 pipe_class ialu_reg_reg_fat(rRegI dst, memory src) %{
5230 single_instruction;
5231 dst : S4(write);
5232 src : S3(read);
5233 D0 : S0; // big decoder only
5234 ALU : S3; // any alu
5235 %}
5236
5237 // Long ALU reg-reg operation
5238 pipe_class ialu_reg_reg_long_fat(eRegL dst, eRegL src) %{
5239 instruction_count(2);
5240 dst : S4(write);
5241 src : S3(read);
5242 D0 : S0(2); // big decoder only; twice
5243 ALU : S3(2); // both alus
5244 %}
5245
5246 // Integer ALU reg-mem operation
5247 pipe_class ialu_reg_mem(rRegI dst, memory mem) %{
5248 single_instruction;
5249 dst : S5(write);
5250 mem : S3(read);
5251 D0 : S0; // big decoder only
5252 ALU : S4; // any alu
5253 MEM : S3; // any mem
5254 %}
5255
5256 // Long ALU reg-mem operation
5257 pipe_class ialu_reg_long_mem(eRegL dst, load_long_memory mem) %{
5258 instruction_count(2);
5259 dst : S5(write);
5260 mem : S3(read);
5261 D0 : S0(2); // big decoder only; twice
5262 ALU : S4(2); // any 2 alus
5263 MEM : S3(2); // both mems
5264 %}
5265
5266 // Integer mem operation (prefetch)
5267 pipe_class ialu_mem(memory mem)
5268 %{
5269 single_instruction;
5270 mem : S3(read);
5271 D0 : S0; // big decoder only
5272 MEM : S3; // any mem
5273 %}
5274
5275 // Integer Store to Memory
5276 pipe_class ialu_mem_reg(memory mem, rRegI src) %{
5277 single_instruction;
5278 mem : S3(read);
5279 src : S5(read);
5280 D0 : S0; // big decoder only
5281 ALU : S4; // any alu
5282 MEM : S3;
5283 %}
5284
5285 // Long Store to Memory
5286 pipe_class ialu_mem_long_reg(memory mem, eRegL src) %{
5287 instruction_count(2);
5288 mem : S3(read);
5289 src : S5(read);
5290 D0 : S0(2); // big decoder only; twice
5291 ALU : S4(2); // any 2 alus
5292 MEM : S3(2); // Both mems
5293 %}
5294
5295 // Integer Store to Memory
5296 pipe_class ialu_mem_imm(memory mem) %{
5297 single_instruction;
5298 mem : S3(read);
5299 D0 : S0; // big decoder only
5300 ALU : S4; // any alu
5301 MEM : S3;
5302 %}
5303
5304 // Integer ALU0 reg-reg operation
5305 pipe_class ialu_reg_reg_alu0(rRegI dst, rRegI src) %{
5306 single_instruction;
5307 dst : S4(write);
5308 src : S3(read);
5309 D0 : S0; // Big decoder only
5310 ALU0 : S3; // only alu0
5311 %}
5312
5313 // Integer ALU0 reg-mem operation
5314 pipe_class ialu_reg_mem_alu0(rRegI dst, memory mem) %{
5315 single_instruction;
5316 dst : S5(write);
5317 mem : S3(read);
5318 D0 : S0; // big decoder only
5319 ALU0 : S4; // ALU0 only
5320 MEM : S3; // any mem
5321 %}
5322
5323 // Integer ALU reg-reg operation
5324 pipe_class ialu_cr_reg_reg(eFlagsReg cr, rRegI src1, rRegI src2) %{
5325 single_instruction;
5326 cr : S4(write);
5327 src1 : S3(read);
5328 src2 : S3(read);
5329 DECODE : S0; // any decoder
5330 ALU : S3; // any alu
5331 %}
5332
5333 // Integer ALU reg-imm operation
5334 pipe_class ialu_cr_reg_imm(eFlagsReg cr, rRegI src1) %{
5335 single_instruction;
5336 cr : S4(write);
5337 src1 : S3(read);
5338 DECODE : S0; // any decoder
5339 ALU : S3; // any alu
5340 %}
5341
5342 // Integer ALU reg-mem operation
5343 pipe_class ialu_cr_reg_mem(eFlagsReg cr, rRegI src1, memory src2) %{
5344 single_instruction;
5345 cr : S4(write);
5346 src1 : S3(read);
5347 src2 : S3(read);
5348 D0 : S0; // big decoder only
5349 ALU : S4; // any alu
5350 MEM : S3;
5351 %}
5352
5353 // Conditional move reg-reg
5354 pipe_class pipe_cmplt( rRegI p, rRegI q, rRegI y ) %{
5355 instruction_count(4);
5356 y : S4(read);
5357 q : S3(read);
5358 p : S3(read);
5359 DECODE : S0(4); // any decoder
5360 %}
5361
5362 // Conditional move reg-reg
5363 pipe_class pipe_cmov_reg( rRegI dst, rRegI src, eFlagsReg cr ) %{
5364 single_instruction;
5365 dst : S4(write);
5366 src : S3(read);
5367 cr : S3(read);
5368 DECODE : S0; // any decoder
5369 %}
5370
5371 // Conditional move reg-mem
5372 pipe_class pipe_cmov_mem( eFlagsReg cr, rRegI dst, memory src) %{
5373 single_instruction;
5374 dst : S4(write);
5375 src : S3(read);
5376 cr : S3(read);
5377 DECODE : S0; // any decoder
5378 MEM : S3;
5379 %}
5380
5381 // Conditional move reg-reg long
5382 pipe_class pipe_cmov_reg_long( eFlagsReg cr, eRegL dst, eRegL src) %{
5383 single_instruction;
5384 dst : S4(write);
5385 src : S3(read);
5386 cr : S3(read);
5387 DECODE : S0(2); // any 2 decoders
5388 %}
5389
5390 // Conditional move double reg-reg
5391 pipe_class pipe_cmovDPR_reg( eFlagsReg cr, regDPR1 dst, regDPR src) %{
5392 single_instruction;
5393 dst : S4(write);
5394 src : S3(read);
5395 cr : S3(read);
5396 DECODE : S0; // any decoder
5397 %}
5398
5399 // Float reg-reg operation
5400 pipe_class fpu_reg(regDPR dst) %{
5401 instruction_count(2);
5402 dst : S3(read);
5403 DECODE : S0(2); // any 2 decoders
5404 FPU : S3;
5405 %}
5406
5407 // Float reg-reg operation
5408 pipe_class fpu_reg_reg(regDPR dst, regDPR src) %{
5409 instruction_count(2);
5410 dst : S4(write);
5411 src : S3(read);
5412 DECODE : S0(2); // any 2 decoders
5413 FPU : S3;
5414 %}
5415
5416 // Float reg-reg operation
5417 pipe_class fpu_reg_reg_reg(regDPR dst, regDPR src1, regDPR src2) %{
5418 instruction_count(3);
5419 dst : S4(write);
5420 src1 : S3(read);
5421 src2 : S3(read);
5422 DECODE : S0(3); // any 3 decoders
5423 FPU : S3(2);
5424 %}
5425
5426 // Float reg-reg operation
5427 pipe_class fpu_reg_reg_reg_reg(regDPR dst, regDPR src1, regDPR src2, regDPR src3) %{
5428 instruction_count(4);
5429 dst : S4(write);
5430 src1 : S3(read);
5431 src2 : S3(read);
5432 src3 : S3(read);
5433 DECODE : S0(4); // any 3 decoders
5434 FPU : S3(2);
5435 %}
5436
5437 // Float reg-reg operation
5438 pipe_class fpu_reg_mem_reg_reg(regDPR dst, memory src1, regDPR src2, regDPR src3) %{
5439 instruction_count(4);
5440 dst : S4(write);
5441 src1 : S3(read);
5442 src2 : S3(read);
5443 src3 : S3(read);
5444 DECODE : S1(3); // any 3 decoders
5445 D0 : S0; // Big decoder only
5446 FPU : S3(2);
5447 MEM : S3;
5448 %}
5449
5450 // Float reg-mem operation
5451 pipe_class fpu_reg_mem(regDPR dst, memory mem) %{
5452 instruction_count(2);
5453 dst : S5(write);
5454 mem : S3(read);
5455 D0 : S0; // big decoder only
5456 DECODE : S1; // any decoder for FPU POP
5457 FPU : S4;
5458 MEM : S3; // any mem
5459 %}
5460
5461 // Float reg-mem operation
5462 pipe_class fpu_reg_reg_mem(regDPR dst, regDPR src1, memory mem) %{
5463 instruction_count(3);
5464 dst : S5(write);
5465 src1 : S3(read);
5466 mem : S3(read);
5467 D0 : S0; // big decoder only
5468 DECODE : S1(2); // any decoder for FPU POP
5469 FPU : S4;
5470 MEM : S3; // any mem
5471 %}
5472
5473 // Float mem-reg operation
5474 pipe_class fpu_mem_reg(memory mem, regDPR src) %{
5475 instruction_count(2);
5476 src : S5(read);
5477 mem : S3(read);
5478 DECODE : S0; // any decoder for FPU PUSH
5479 D0 : S1; // big decoder only
5480 FPU : S4;
5481 MEM : S3; // any mem
5482 %}
5483
5484 pipe_class fpu_mem_reg_reg(memory mem, regDPR src1, regDPR src2) %{
5485 instruction_count(3);
5486 src1 : S3(read);
5487 src2 : S3(read);
5488 mem : S3(read);
5489 DECODE : S0(2); // any decoder for FPU PUSH
5490 D0 : S1; // big decoder only
5491 FPU : S4;
5492 MEM : S3; // any mem
5493 %}
5494
5495 pipe_class fpu_mem_reg_mem(memory mem, regDPR src1, memory src2) %{
5496 instruction_count(3);
5497 src1 : S3(read);
5498 src2 : S3(read);
5499 mem : S4(read);
5500 DECODE : S0; // any decoder for FPU PUSH
5501 D0 : S0(2); // big decoder only
5502 FPU : S4;
5503 MEM : S3(2); // any mem
5504 %}
5505
5506 pipe_class fpu_mem_mem(memory dst, memory src1) %{
5507 instruction_count(2);
5508 src1 : S3(read);
5509 dst : S4(read);
5510 D0 : S0(2); // big decoder only
5511 MEM : S3(2); // any mem
5512 %}
5513
5514 pipe_class fpu_mem_mem_mem(memory dst, memory src1, memory src2) %{
5515 instruction_count(3);
5516 src1 : S3(read);
5517 src2 : S3(read);
5518 dst : S4(read);
5519 D0 : S0(3); // big decoder only
5520 FPU : S4;
5521 MEM : S3(3); // any mem
5522 %}
5523
5524 pipe_class fpu_mem_reg_con(memory mem, regDPR src1) %{
5525 instruction_count(3);
5526 src1 : S4(read);
5527 mem : S4(read);
5528 DECODE : S0; // any decoder for FPU PUSH
5529 D0 : S0(2); // big decoder only
5530 FPU : S4;
5531 MEM : S3(2); // any mem
5532 %}
5533
5534 // Float load constant
5535 pipe_class fpu_reg_con(regDPR dst) %{
5536 instruction_count(2);
5537 dst : S5(write);
5538 D0 : S0; // big decoder only for the load
5539 DECODE : S1; // any decoder for FPU POP
5540 FPU : S4;
5541 MEM : S3; // any mem
5542 %}
5543
5544 // Float load constant
5545 pipe_class fpu_reg_reg_con(regDPR dst, regDPR src) %{
5546 instruction_count(3);
5547 dst : S5(write);
5548 src : S3(read);
5549 D0 : S0; // big decoder only for the load
5550 DECODE : S1(2); // any decoder for FPU POP
5551 FPU : S4;
5552 MEM : S3; // any mem
5553 %}
5554
5555 // UnConditional branch
5556 pipe_class pipe_jmp( label labl ) %{
5557 single_instruction;
5558 BR : S3;
5559 %}
5560
5561 // Conditional branch
5562 pipe_class pipe_jcc( cmpOp cmp, eFlagsReg cr, label labl ) %{
5563 single_instruction;
5564 cr : S1(read);
5565 BR : S3;
5566 %}
5567
5568 // Allocation idiom
5569 pipe_class pipe_cmpxchg( eRegP dst, eRegP heap_ptr ) %{
5570 instruction_count(1); force_serialization;
5571 fixed_latency(6);
5572 heap_ptr : S3(read);
5573 DECODE : S0(3);
5574 D0 : S2;
5575 MEM : S3;
5576 ALU : S3(2);
5577 dst : S5(write);
5578 BR : S5;
5579 %}
5580
5581 // Generic big/slow expanded idiom
5582 pipe_class pipe_slow( ) %{
5583 instruction_count(10); multiple_bundles; force_serialization;
5584 fixed_latency(100);
5585 D0 : S0(2);
5586 MEM : S3(2);
5587 %}
5588
5589 // The real do-nothing guy
5590 pipe_class empty( ) %{
5591 instruction_count(0);
5592 %}
5593
5594 // Define the class for the Nop node
5595 define %{
5596 MachNop = empty;
5597 %}
5598
5599 %}
5600
5601 //----------INSTRUCTIONS-------------------------------------------------------
5602 //
5603 // match -- States which machine-independent subtree may be replaced
5604 // by this instruction.
5605 // ins_cost -- The estimated cost of this instruction is used by instruction
5606 // selection to identify a minimum cost tree of machine
5607 // instructions that matches a tree of machine-independent
5608 // instructions.
5609 // format -- A string providing the disassembly for this instruction.
5610 // The value of an instruction's operand may be inserted
5611 // by referring to it with a '$' prefix.
5612 // opcode -- Three instruction opcodes may be provided. These are referred
5613 // to within an encode class as $primary, $secondary, and $tertiary
5614 // respectively. The primary opcode is commonly used to
5615 // indicate the type of machine instruction, while secondary
5616 // and tertiary are often used for prefix options or addressing
5617 // modes.
5618 // ins_encode -- A list of encode classes with parameters. The encode class
5619 // name must have been defined in an 'enc_class' specification
5620 // in the encode section of the architecture description.
5621
5622 //----------BSWAP-Instruction--------------------------------------------------
5623 instruct bytes_reverse_int(rRegI dst) %{
5624 match(Set dst (ReverseBytesI dst));
5625
5626 format %{ "BSWAP $dst" %}
5627 opcode(0x0F, 0xC8);
5628 ins_encode( OpcP, OpcSReg(dst) );
5629 ins_pipe( ialu_reg );
5630 %}
5631
5632 instruct bytes_reverse_long(eRegL dst) %{
5633 match(Set dst (ReverseBytesL dst));
5634
5635 format %{ "BSWAP $dst.lo\n\t"
5636 "BSWAP $dst.hi\n\t"
5637 "XCHG $dst.lo $dst.hi" %}
5638
5639 ins_cost(125);
5640 ins_encode( bswap_long_bytes(dst) );
5641 ins_pipe( ialu_reg_reg);
5642 %}
5643
5644 instruct bytes_reverse_unsigned_short(rRegI dst, eFlagsReg cr) %{
5645 match(Set dst (ReverseBytesUS dst));
5646 effect(KILL cr);
5647
5648 format %{ "BSWAP $dst\n\t"
5649 "SHR $dst,16\n\t" %}
5650 ins_encode %{
5651 __ bswapl($dst$$Register);
5652 __ shrl($dst$$Register, 16);
5653 %}
5654 ins_pipe( ialu_reg );
5655 %}
5656
5657 instruct bytes_reverse_short(rRegI dst, eFlagsReg cr) %{
5658 match(Set dst (ReverseBytesS dst));
5659 effect(KILL cr);
5660
5661 format %{ "BSWAP $dst\n\t"
5662 "SAR $dst,16\n\t" %}
5663 ins_encode %{
5664 __ bswapl($dst$$Register);
5665 __ sarl($dst$$Register, 16);
5666 %}
5667 ins_pipe( ialu_reg );
5668 %}
5669
5670
5671 //---------- Zeros Count Instructions ------------------------------------------
5672
5673 instruct countLeadingZerosI(rRegI dst, rRegI src, eFlagsReg cr) %{
5674 predicate(UseCountLeadingZerosInstruction);
5675 match(Set dst (CountLeadingZerosI src));
5676 effect(KILL cr);
5677
5678 format %{ "LZCNT $dst, $src\t# count leading zeros (int)" %}
5679 ins_encode %{
5680 __ lzcntl($dst$$Register, $src$$Register);
5681 %}
5682 ins_pipe(ialu_reg);
5683 %}
5684
5685 instruct countLeadingZerosI_bsr(rRegI dst, rRegI src, eFlagsReg cr) %{
5686 predicate(!UseCountLeadingZerosInstruction);
5687 match(Set dst (CountLeadingZerosI src));
5688 effect(KILL cr);
5689
5690 format %{ "BSR $dst, $src\t# count leading zeros (int)\n\t"
5691 "JNZ skip\n\t"
5692 "MOV $dst, -1\n"
5693 "skip:\n\t"
5694 "NEG $dst\n\t"
5695 "ADD $dst, 31" %}
5696 ins_encode %{
5697 Register Rdst = $dst$$Register;
5698 Register Rsrc = $src$$Register;
5699 Label skip;
5700 __ bsrl(Rdst, Rsrc);
5701 __ jccb(Assembler::notZero, skip);
5702 __ movl(Rdst, -1);
5703 __ bind(skip);
5704 __ negl(Rdst);
5705 __ addl(Rdst, BitsPerInt - 1);
5706 %}
5707 ins_pipe(ialu_reg);
5708 %}
5709
5710 instruct countLeadingZerosL(rRegI dst, eRegL src, eFlagsReg cr) %{
5711 predicate(UseCountLeadingZerosInstruction);
5712 match(Set dst (CountLeadingZerosL src));
5713 effect(TEMP dst, KILL cr);
5714
5715 format %{ "LZCNT $dst, $src.hi\t# count leading zeros (long)\n\t"
5716 "JNC done\n\t"
5717 "LZCNT $dst, $src.lo\n\t"
5718 "ADD $dst, 32\n"
5719 "done:" %}
5720 ins_encode %{
5721 Register Rdst = $dst$$Register;
5722 Register Rsrc = $src$$Register;
5723 Label done;
5724 __ lzcntl(Rdst, HIGH_FROM_LOW(Rsrc));
5725 __ jccb(Assembler::carryClear, done);
5726 __ lzcntl(Rdst, Rsrc);
5727 __ addl(Rdst, BitsPerInt);
5728 __ bind(done);
5729 %}
5730 ins_pipe(ialu_reg);
5731 %}
5732
5733 instruct countLeadingZerosL_bsr(rRegI dst, eRegL src, eFlagsReg cr) %{
5734 predicate(!UseCountLeadingZerosInstruction);
5735 match(Set dst (CountLeadingZerosL src));
5736 effect(TEMP dst, KILL cr);
5737
5738 format %{ "BSR $dst, $src.hi\t# count leading zeros (long)\n\t"
5739 "JZ msw_is_zero\n\t"
5740 "ADD $dst, 32\n\t"
5741 "JMP not_zero\n"
5742 "msw_is_zero:\n\t"
5743 "BSR $dst, $src.lo\n\t"
5744 "JNZ not_zero\n\t"
5745 "MOV $dst, -1\n"
5746 "not_zero:\n\t"
5747 "NEG $dst\n\t"
5748 "ADD $dst, 63\n" %}
5749 ins_encode %{
5750 Register Rdst = $dst$$Register;
5751 Register Rsrc = $src$$Register;
5752 Label msw_is_zero;
5753 Label not_zero;
5754 __ bsrl(Rdst, HIGH_FROM_LOW(Rsrc));
5755 __ jccb(Assembler::zero, msw_is_zero);
5756 __ addl(Rdst, BitsPerInt);
5757 __ jmpb(not_zero);
5758 __ bind(msw_is_zero);
5759 __ bsrl(Rdst, Rsrc);
5760 __ jccb(Assembler::notZero, not_zero);
5761 __ movl(Rdst, -1);
5762 __ bind(not_zero);
5763 __ negl(Rdst);
5764 __ addl(Rdst, BitsPerLong - 1);
5765 %}
5766 ins_pipe(ialu_reg);
5767 %}
5768
5769 instruct countTrailingZerosI(rRegI dst, rRegI src, eFlagsReg cr) %{
5770 match(Set dst (CountTrailingZerosI src));
5771 effect(KILL cr);
5772
5773 format %{ "BSF $dst, $src\t# count trailing zeros (int)\n\t"
5774 "JNZ done\n\t"
5775 "MOV $dst, 32\n"
5776 "done:" %}
5777 ins_encode %{
5778 Register Rdst = $dst$$Register;
5779 Label done;
5780 __ bsfl(Rdst, $src$$Register);
5781 __ jccb(Assembler::notZero, done);
5782 __ movl(Rdst, BitsPerInt);
5783 __ bind(done);
5784 %}
5785 ins_pipe(ialu_reg);
5786 %}
5787
5788 instruct countTrailingZerosL(rRegI dst, eRegL src, eFlagsReg cr) %{
5789 match(Set dst (CountTrailingZerosL src));
5790 effect(TEMP dst, KILL cr);
5791
5792 format %{ "BSF $dst, $src.lo\t# count trailing zeros (long)\n\t"
5793 "JNZ done\n\t"
5794 "BSF $dst, $src.hi\n\t"
5795 "JNZ msw_not_zero\n\t"
5796 "MOV $dst, 32\n"
5797 "msw_not_zero:\n\t"
5798 "ADD $dst, 32\n"
5799 "done:" %}
5800 ins_encode %{
5801 Register Rdst = $dst$$Register;
5802 Register Rsrc = $src$$Register;
5803 Label msw_not_zero;
5804 Label done;
5805 __ bsfl(Rdst, Rsrc);
5806 __ jccb(Assembler::notZero, done);
5807 __ bsfl(Rdst, HIGH_FROM_LOW(Rsrc));
5808 __ jccb(Assembler::notZero, msw_not_zero);
5809 __ movl(Rdst, BitsPerInt);
5810 __ bind(msw_not_zero);
5811 __ addl(Rdst, BitsPerInt);
5812 __ bind(done);
5813 %}
5814 ins_pipe(ialu_reg);
5815 %}
5816
5817
5818 //---------- Population Count Instructions -------------------------------------
5819
5820 instruct popCountI(rRegI dst, rRegI src, eFlagsReg cr) %{
5821 predicate(UsePopCountInstruction);
5822 match(Set dst (PopCountI src));
5823 effect(KILL cr);
5824
5825 format %{ "POPCNT $dst, $src" %}
5826 ins_encode %{
5827 __ popcntl($dst$$Register, $src$$Register);
5828 %}
5829 ins_pipe(ialu_reg);
5830 %}
5831
5832 instruct popCountI_mem(rRegI dst, memory mem, eFlagsReg cr) %{
5833 predicate(UsePopCountInstruction);
5834 match(Set dst (PopCountI (LoadI mem)));
5835 effect(KILL cr);
5836
5837 format %{ "POPCNT $dst, $mem" %}
5838 ins_encode %{
5839 __ popcntl($dst$$Register, $mem$$Address);
5840 %}
5841 ins_pipe(ialu_reg);
5842 %}
5843
5844 // Note: Long.bitCount(long) returns an int.
5845 instruct popCountL(rRegI dst, eRegL src, rRegI tmp, eFlagsReg cr) %{
5846 predicate(UsePopCountInstruction);
5847 match(Set dst (PopCountL src));
5848 effect(KILL cr, TEMP tmp, TEMP dst);
5849
5850 format %{ "POPCNT $dst, $src.lo\n\t"
5851 "POPCNT $tmp, $src.hi\n\t"
5852 "ADD $dst, $tmp" %}
5853 ins_encode %{
5854 __ popcntl($dst$$Register, $src$$Register);
5855 __ popcntl($tmp$$Register, HIGH_FROM_LOW($src$$Register));
5856 __ addl($dst$$Register, $tmp$$Register);
5857 %}
5858 ins_pipe(ialu_reg);
5859 %}
5860
5861 // Note: Long.bitCount(long) returns an int.
5862 instruct popCountL_mem(rRegI dst, memory mem, rRegI tmp, eFlagsReg cr) %{
5863 predicate(UsePopCountInstruction);
5864 match(Set dst (PopCountL (LoadL mem)));
5865 effect(KILL cr, TEMP tmp, TEMP dst);
5866
5867 format %{ "POPCNT $dst, $mem\n\t"
5868 "POPCNT $tmp, $mem+4\n\t"
5869 "ADD $dst, $tmp" %}
5870 ins_encode %{
5871 //__ popcntl($dst$$Register, $mem$$Address$$first);
5872 //__ popcntl($tmp$$Register, $mem$$Address$$second);
5873 __ popcntl($dst$$Register, Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp, false));
5874 __ popcntl($tmp$$Register, Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp + 4, false));
5875 __ addl($dst$$Register, $tmp$$Register);
5876 %}
5877 ins_pipe(ialu_reg);
5878 %}
5879
5880
5881 //----------Load/Store/Move Instructions---------------------------------------
5882 //----------Load Instructions--------------------------------------------------
5883 // Load Byte (8bit signed)
5884 instruct loadB(xRegI dst, memory mem) %{
5885 match(Set dst (LoadB mem));
5886
5887 ins_cost(125);
5888 format %{ "MOVSX8 $dst,$mem\t# byte" %}
5889
5890 ins_encode %{
5891 __ movsbl($dst$$Register, $mem$$Address);
5892 %}
5893
5894 ins_pipe(ialu_reg_mem);
5895 %}
5896
5897 // Load Byte (8bit signed) into Long Register
5898 instruct loadB2L(eRegL dst, memory mem, eFlagsReg cr) %{
5899 match(Set dst (ConvI2L (LoadB mem)));
5900 effect(KILL cr);
5901
5902 ins_cost(375);
5903 format %{ "MOVSX8 $dst.lo,$mem\t# byte -> long\n\t"
5904 "MOV $dst.hi,$dst.lo\n\t"
5905 "SAR $dst.hi,7" %}
5906
5907 ins_encode %{
5908 __ movsbl($dst$$Register, $mem$$Address);
5909 __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register.
5910 __ sarl(HIGH_FROM_LOW($dst$$Register), 7); // 24+1 MSB are already signed extended.
5911 %}
5912
5913 ins_pipe(ialu_reg_mem);
5914 %}
5915
5916 // Load Unsigned Byte (8bit UNsigned)
5917 instruct loadUB(xRegI dst, memory mem) %{
5918 match(Set dst (LoadUB mem));
5919
5920 ins_cost(125);
5921 format %{ "MOVZX8 $dst,$mem\t# ubyte -> int" %}
5922
5923 ins_encode %{
5924 __ movzbl($dst$$Register, $mem$$Address);
5925 %}
5926
5927 ins_pipe(ialu_reg_mem);
5928 %}
5929
5930 // Load Unsigned Byte (8 bit UNsigned) into Long Register
5931 instruct loadUB2L(eRegL dst, memory mem, eFlagsReg cr) %{
5932 match(Set dst (ConvI2L (LoadUB mem)));
5933 effect(KILL cr);
5934
5935 ins_cost(250);
5936 format %{ "MOVZX8 $dst.lo,$mem\t# ubyte -> long\n\t"
5937 "XOR $dst.hi,$dst.hi" %}
5938
5939 ins_encode %{
5940 Register Rdst = $dst$$Register;
5941 __ movzbl(Rdst, $mem$$Address);
5942 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
5943 %}
5944
5945 ins_pipe(ialu_reg_mem);
5946 %}
5947
5948 // Load Unsigned Byte (8 bit UNsigned) with mask into Long Register
5949 instruct loadUB2L_immI8(eRegL dst, memory mem, immI8 mask, eFlagsReg cr) %{
5950 match(Set dst (ConvI2L (AndI (LoadUB mem) mask)));
5951 effect(KILL cr);
5952
5953 format %{ "MOVZX8 $dst.lo,$mem\t# ubyte & 8-bit mask -> long\n\t"
5954 "XOR $dst.hi,$dst.hi\n\t"
5955 "AND $dst.lo,$mask" %}
5956 ins_encode %{
5957 Register Rdst = $dst$$Register;
5958 __ movzbl(Rdst, $mem$$Address);
5959 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
5960 __ andl(Rdst, $mask$$constant);
5961 %}
5962 ins_pipe(ialu_reg_mem);
5963 %}
5964
5965 // Load Short (16bit signed)
5966 instruct loadS(rRegI dst, memory mem) %{
5967 match(Set dst (LoadS mem));
5968
5969 ins_cost(125);
5970 format %{ "MOVSX $dst,$mem\t# short" %}
5971
5972 ins_encode %{
5973 __ movswl($dst$$Register, $mem$$Address);
5974 %}
5975
5976 ins_pipe(ialu_reg_mem);
5977 %}
5978
5979 // Load Short (16 bit signed) to Byte (8 bit signed)
5980 instruct loadS2B(rRegI dst, memory mem, immI_24 twentyfour) %{
5981 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour));
5982
5983 ins_cost(125);
5984 format %{ "MOVSX $dst, $mem\t# short -> byte" %}
5985 ins_encode %{
5986 __ movsbl($dst$$Register, $mem$$Address);
5987 %}
5988 ins_pipe(ialu_reg_mem);
5989 %}
5990
5991 // Load Short (16bit signed) into Long Register
5992 instruct loadS2L(eRegL dst, memory mem, eFlagsReg cr) %{
5993 match(Set dst (ConvI2L (LoadS mem)));
5994 effect(KILL cr);
5995
5996 ins_cost(375);
5997 format %{ "MOVSX $dst.lo,$mem\t# short -> long\n\t"
5998 "MOV $dst.hi,$dst.lo\n\t"
5999 "SAR $dst.hi,15" %}
6000
6001 ins_encode %{
6002 __ movswl($dst$$Register, $mem$$Address);
6003 __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register.
6004 __ sarl(HIGH_FROM_LOW($dst$$Register), 15); // 16+1 MSB are already signed extended.
6005 %}
6006
6007 ins_pipe(ialu_reg_mem);
6008 %}
6009
6010 // Load Unsigned Short/Char (16bit unsigned)
6011 instruct loadUS(rRegI dst, memory mem) %{
6012 match(Set dst (LoadUS mem));
6013
6014 ins_cost(125);
6015 format %{ "MOVZX $dst,$mem\t# ushort/char -> int" %}
6016
6017 ins_encode %{
6018 __ movzwl($dst$$Register, $mem$$Address);
6019 %}
6020
6021 ins_pipe(ialu_reg_mem);
6022 %}
6023
6024 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed)
6025 instruct loadUS2B(rRegI dst, memory mem, immI_24 twentyfour) %{
6026 match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour));
6027
6028 ins_cost(125);
6029 format %{ "MOVSX $dst, $mem\t# ushort -> byte" %}
6030 ins_encode %{
6031 __ movsbl($dst$$Register, $mem$$Address);
6032 %}
6033 ins_pipe(ialu_reg_mem);
6034 %}
6035
6036 // Load Unsigned Short/Char (16 bit UNsigned) into Long Register
6037 instruct loadUS2L(eRegL dst, memory mem, eFlagsReg cr) %{
6038 match(Set dst (ConvI2L (LoadUS mem)));
6039 effect(KILL cr);
6040
6041 ins_cost(250);
6042 format %{ "MOVZX $dst.lo,$mem\t# ushort/char -> long\n\t"
6043 "XOR $dst.hi,$dst.hi" %}
6044
6045 ins_encode %{
6046 __ movzwl($dst$$Register, $mem$$Address);
6047 __ xorl(HIGH_FROM_LOW($dst$$Register), HIGH_FROM_LOW($dst$$Register));
6048 %}
6049
6050 ins_pipe(ialu_reg_mem);
6051 %}
6052
6053 // Load Unsigned Short/Char (16 bit UNsigned) with mask 0xFF into Long Register
6054 instruct loadUS2L_immI_255(eRegL dst, memory mem, immI_255 mask, eFlagsReg cr) %{
6055 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
6056 effect(KILL cr);
6057
6058 format %{ "MOVZX8 $dst.lo,$mem\t# ushort/char & 0xFF -> long\n\t"
6059 "XOR $dst.hi,$dst.hi" %}
6060 ins_encode %{
6061 Register Rdst = $dst$$Register;
6062 __ movzbl(Rdst, $mem$$Address);
6063 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
6064 %}
6065 ins_pipe(ialu_reg_mem);
6066 %}
6067
6068 // Load Unsigned Short/Char (16 bit UNsigned) with a 16-bit mask into Long Register
6069 instruct loadUS2L_immI16(eRegL dst, memory mem, immI16 mask, eFlagsReg cr) %{
6070 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
6071 effect(KILL cr);
6072
6073 format %{ "MOVZX $dst.lo, $mem\t# ushort/char & 16-bit mask -> long\n\t"
6074 "XOR $dst.hi,$dst.hi\n\t"
6075 "AND $dst.lo,$mask" %}
6076 ins_encode %{
6077 Register Rdst = $dst$$Register;
6078 __ movzwl(Rdst, $mem$$Address);
6079 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
6080 __ andl(Rdst, $mask$$constant);
6081 %}
6082 ins_pipe(ialu_reg_mem);
6083 %}
6084
6085 // Load Integer
6086 instruct loadI(rRegI dst, memory mem) %{
6087 match(Set dst (LoadI mem));
6088
6089 ins_cost(125);
6090 format %{ "MOV $dst,$mem\t# int" %}
6091
6092 ins_encode %{
6093 __ movl($dst$$Register, $mem$$Address);
6094 %}
6095
6096 ins_pipe(ialu_reg_mem);
6097 %}
6098
6099 // Load Integer (32 bit signed) to Byte (8 bit signed)
6100 instruct loadI2B(rRegI dst, memory mem, immI_24 twentyfour) %{
6101 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour));
6102
6103 ins_cost(125);
6104 format %{ "MOVSX $dst, $mem\t# int -> byte" %}
6105 ins_encode %{
6106 __ movsbl($dst$$Register, $mem$$Address);
6107 %}
6108 ins_pipe(ialu_reg_mem);
6109 %}
6110
6111 // Load Integer (32 bit signed) to Unsigned Byte (8 bit UNsigned)
6112 instruct loadI2UB(rRegI dst, memory mem, immI_255 mask) %{
6113 match(Set dst (AndI (LoadI mem) mask));
6114
6115 ins_cost(125);
6116 format %{ "MOVZX $dst, $mem\t# int -> ubyte" %}
6117 ins_encode %{
6118 __ movzbl($dst$$Register, $mem$$Address);
6119 %}
6120 ins_pipe(ialu_reg_mem);
6121 %}
6122
6123 // Load Integer (32 bit signed) to Short (16 bit signed)
6124 instruct loadI2S(rRegI dst, memory mem, immI_16 sixteen) %{
6125 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen));
6126
6127 ins_cost(125);
6128 format %{ "MOVSX $dst, $mem\t# int -> short" %}
6129 ins_encode %{
6130 __ movswl($dst$$Register, $mem$$Address);
6131 %}
6132 ins_pipe(ialu_reg_mem);
6133 %}
6134
6135 // Load Integer (32 bit signed) to Unsigned Short/Char (16 bit UNsigned)
6136 instruct loadI2US(rRegI dst, memory mem, immI_65535 mask) %{
6137 match(Set dst (AndI (LoadI mem) mask));
6138
6139 ins_cost(125);
6140 format %{ "MOVZX $dst, $mem\t# int -> ushort/char" %}
6141 ins_encode %{
6142 __ movzwl($dst$$Register, $mem$$Address);
6143 %}
6144 ins_pipe(ialu_reg_mem);
6145 %}
6146
6147 // Load Integer into Long Register
6148 instruct loadI2L(eRegL dst, memory mem, eFlagsReg cr) %{
6149 match(Set dst (ConvI2L (LoadI mem)));
6150 effect(KILL cr);
6151
6152 ins_cost(375);
6153 format %{ "MOV $dst.lo,$mem\t# int -> long\n\t"
6154 "MOV $dst.hi,$dst.lo\n\t"
6155 "SAR $dst.hi,31" %}
6156
6157 ins_encode %{
6158 __ movl($dst$$Register, $mem$$Address);
6159 __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register.
6160 __ sarl(HIGH_FROM_LOW($dst$$Register), 31);
6161 %}
6162
6163 ins_pipe(ialu_reg_mem);
6164 %}
6165
6166 // Load Integer with mask 0xFF into Long Register
6167 instruct loadI2L_immI_255(eRegL dst, memory mem, immI_255 mask, eFlagsReg cr) %{
6168 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
6169 effect(KILL cr);
6170
6171 format %{ "MOVZX8 $dst.lo,$mem\t# int & 0xFF -> long\n\t"
6172 "XOR $dst.hi,$dst.hi" %}
6173 ins_encode %{
6174 Register Rdst = $dst$$Register;
6175 __ movzbl(Rdst, $mem$$Address);
6176 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
6177 %}
6178 ins_pipe(ialu_reg_mem);
6179 %}
6180
6181 // Load Integer with mask 0xFFFF into Long Register
6182 instruct loadI2L_immI_65535(eRegL dst, memory mem, immI_65535 mask, eFlagsReg cr) %{
6183 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
6184 effect(KILL cr);
6185
6186 format %{ "MOVZX $dst.lo,$mem\t# int & 0xFFFF -> long\n\t"
6187 "XOR $dst.hi,$dst.hi" %}
6188 ins_encode %{
6189 Register Rdst = $dst$$Register;
6190 __ movzwl(Rdst, $mem$$Address);
6191 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
6192 %}
6193 ins_pipe(ialu_reg_mem);
6194 %}
6195
6196 // Load Integer with 31-bit mask into Long Register
6197 instruct loadI2L_immU31(eRegL dst, memory mem, immU31 mask, eFlagsReg cr) %{
6198 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
6199 effect(KILL cr);
6200
6201 format %{ "MOV $dst.lo,$mem\t# int & 31-bit mask -> long\n\t"
6202 "XOR $dst.hi,$dst.hi\n\t"
6203 "AND $dst.lo,$mask" %}
6204 ins_encode %{
6205 Register Rdst = $dst$$Register;
6206 __ movl(Rdst, $mem$$Address);
6207 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst));
6208 __ andl(Rdst, $mask$$constant);
6209 %}
6210 ins_pipe(ialu_reg_mem);
6211 %}
6212
6213 // Load Unsigned Integer into Long Register
6214 instruct loadUI2L(eRegL dst, memory mem, immL_32bits mask, eFlagsReg cr) %{
6215 match(Set dst (AndL (ConvI2L (LoadI mem)) mask));
6216 effect(KILL cr);
6217
6218 ins_cost(250);
6219 format %{ "MOV $dst.lo,$mem\t# uint -> long\n\t"
6220 "XOR $dst.hi,$dst.hi" %}
6221
6222 ins_encode %{
6223 __ movl($dst$$Register, $mem$$Address);
6224 __ xorl(HIGH_FROM_LOW($dst$$Register), HIGH_FROM_LOW($dst$$Register));
6225 %}
6226
6227 ins_pipe(ialu_reg_mem);
6228 %}
6229
6230 // Load Long. Cannot clobber address while loading, so restrict address
6231 // register to ESI
6232 instruct loadL(eRegL dst, load_long_memory mem) %{
6233 predicate(!((LoadLNode*)n)->require_atomic_access());
6234 match(Set dst (LoadL mem));
6235
6236 ins_cost(250);
6237 format %{ "MOV $dst.lo,$mem\t# long\n\t"
6238 "MOV $dst.hi,$mem+4" %}
6239
6240 ins_encode %{
6241 Address Amemlo = Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp, false);
6242 Address Amemhi = Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp + 4, false);
6243 __ movl($dst$$Register, Amemlo);
6244 __ movl(HIGH_FROM_LOW($dst$$Register), Amemhi);
6245 %}
6246
6247 ins_pipe(ialu_reg_long_mem);
6248 %}
6249
6250 // Volatile Load Long. Must be atomic, so do 64-bit FILD
6251 // then store it down to the stack and reload on the int
6252 // side.
6253 instruct loadL_volatile(stackSlotL dst, memory mem) %{
6254 predicate(UseSSE<=1 && ((LoadLNode*)n)->require_atomic_access());
6255 match(Set dst (LoadL mem));
6256
6257 ins_cost(200);
6258 format %{ "FILD $mem\t# Atomic volatile long load\n\t"
6259 "FISTp $dst" %}
6260 ins_encode(enc_loadL_volatile(mem,dst));
6261 ins_pipe( fpu_reg_mem );
6262 %}
6263
6264 instruct loadLX_volatile(stackSlotL dst, memory mem, regD tmp) %{
6265 predicate(UseSSE>=2 && ((LoadLNode*)n)->require_atomic_access());
6266 match(Set dst (LoadL mem));
6267 effect(TEMP tmp);
6268 ins_cost(180);
6269 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t"
6270 "MOVSD $dst,$tmp" %}
6271 ins_encode %{
6272 __ movdbl($tmp$$XMMRegister, $mem$$Address);
6273 __ movdbl(Address(rsp, $dst$$disp), $tmp$$XMMRegister);
6274 %}
6275 ins_pipe( pipe_slow );
6276 %}
6277
6278 instruct loadLX_reg_volatile(eRegL dst, memory mem, regD tmp) %{
6279 predicate(UseSSE>=2 && ((LoadLNode*)n)->require_atomic_access());
6280 match(Set dst (LoadL mem));
6281 effect(TEMP tmp);
6282 ins_cost(160);
6283 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t"
6284 "MOVD $dst.lo,$tmp\n\t"
6285 "PSRLQ $tmp,32\n\t"
6286 "MOVD $dst.hi,$tmp" %}
6287 ins_encode %{
6288 __ movdbl($tmp$$XMMRegister, $mem$$Address);
6289 __ movdl($dst$$Register, $tmp$$XMMRegister);
6290 __ psrlq($tmp$$XMMRegister, 32);
6291 __ movdl(HIGH_FROM_LOW($dst$$Register), $tmp$$XMMRegister);
6292 %}
6293 ins_pipe( pipe_slow );
6294 %}
6295
6296 // Load Range
6297 instruct loadRange(rRegI dst, memory mem) %{
6298 match(Set dst (LoadRange mem));
6299
6300 ins_cost(125);
6301 format %{ "MOV $dst,$mem" %}
6302 opcode(0x8B);
6303 ins_encode( OpcP, RegMem(dst,mem));
6304 ins_pipe( ialu_reg_mem );
6305 %}
6306
6307
6308 // Load Pointer
6309 instruct loadP(eRegP dst, memory mem) %{
6310 match(Set dst (LoadP mem));
6311
6312 ins_cost(125);
6313 format %{ "MOV $dst,$mem" %}
6314 opcode(0x8B);
6315 ins_encode( OpcP, RegMem(dst,mem));
6316 ins_pipe( ialu_reg_mem );
6317 %}
6318
6319 // Load Klass Pointer
6320 instruct loadKlass(eRegP dst, memory mem) %{
6321 match(Set dst (LoadKlass mem));
6322
6323 ins_cost(125);
6324 format %{ "MOV $dst,$mem" %}
6325 opcode(0x8B);
6326 ins_encode( OpcP, RegMem(dst,mem));
6327 ins_pipe( ialu_reg_mem );
6328 %}
6329
6330 // Load Double
6331 instruct loadDPR(regDPR dst, memory mem) %{
6332 predicate(UseSSE<=1);
6333 match(Set dst (LoadD mem));
6334
6335 ins_cost(150);
6336 format %{ "FLD_D ST,$mem\n\t"
6337 "FSTP $dst" %}
6338 opcode(0xDD); /* DD /0 */
6339 ins_encode( OpcP, RMopc_Mem(0x00,mem),
6340 Pop_Reg_DPR(dst) );
6341 ins_pipe( fpu_reg_mem );
6342 %}
6343
6344 // Load Double to XMM
6345 instruct loadD(regD dst, memory mem) %{
6346 predicate(UseSSE>=2 && UseXmmLoadAndClearUpper);
6347 match(Set dst (LoadD mem));
6348 ins_cost(145);
6349 format %{ "MOVSD $dst,$mem" %}
6350 ins_encode %{
6351 __ movdbl ($dst$$XMMRegister, $mem$$Address);
6352 %}
6353 ins_pipe( pipe_slow );
6354 %}
6355
6356 instruct loadD_partial(regD dst, memory mem) %{
6357 predicate(UseSSE>=2 && !UseXmmLoadAndClearUpper);
6358 match(Set dst (LoadD mem));
6359 ins_cost(145);
6360 format %{ "MOVLPD $dst,$mem" %}
6361 ins_encode %{
6362 __ movdbl ($dst$$XMMRegister, $mem$$Address);
6363 %}
6364 ins_pipe( pipe_slow );
6365 %}
6366
6367 // Load to XMM register (single-precision floating point)
6368 // MOVSS instruction
6369 instruct loadF(regF dst, memory mem) %{
6370 predicate(UseSSE>=1);
6371 match(Set dst (LoadF mem));
6372 ins_cost(145);
6373 format %{ "MOVSS $dst,$mem" %}
6374 ins_encode %{
6375 __ movflt ($dst$$XMMRegister, $mem$$Address);
6376 %}
6377 ins_pipe( pipe_slow );
6378 %}
6379
6380 // Load Float
6381 instruct loadFPR(regFPR dst, memory mem) %{
6382 predicate(UseSSE==0);
6383 match(Set dst (LoadF mem));
6384
6385 ins_cost(150);
6386 format %{ "FLD_S ST,$mem\n\t"
6387 "FSTP $dst" %}
6388 opcode(0xD9); /* D9 /0 */
6389 ins_encode( OpcP, RMopc_Mem(0x00,mem),
6390 Pop_Reg_FPR(dst) );
6391 ins_pipe( fpu_reg_mem );
6392 %}
6393
6394 // Load Effective Address
6395 instruct leaP8(eRegP dst, indOffset8 mem) %{
6396 match(Set dst mem);
6397
6398 ins_cost(110);
6399 format %{ "LEA $dst,$mem" %}
6400 opcode(0x8D);
6401 ins_encode( OpcP, RegMem(dst,mem));
6402 ins_pipe( ialu_reg_reg_fat );
6403 %}
6404
6405 instruct leaP32(eRegP dst, indOffset32 mem) %{
6406 match(Set dst mem);
6407
6408 ins_cost(110);
6409 format %{ "LEA $dst,$mem" %}
6410 opcode(0x8D);
6411 ins_encode( OpcP, RegMem(dst,mem));
6412 ins_pipe( ialu_reg_reg_fat );
6413 %}
6414
6415 instruct leaPIdxOff(eRegP dst, indIndexOffset mem) %{
6416 match(Set dst mem);
6417
6418 ins_cost(110);
6419 format %{ "LEA $dst,$mem" %}
6420 opcode(0x8D);
6421 ins_encode( OpcP, RegMem(dst,mem));
6422 ins_pipe( ialu_reg_reg_fat );
6423 %}
6424
6425 instruct leaPIdxScale(eRegP dst, indIndexScale mem) %{
6426 match(Set dst mem);
6427
6428 ins_cost(110);
6429 format %{ "LEA $dst,$mem" %}
6430 opcode(0x8D);
6431 ins_encode( OpcP, RegMem(dst,mem));
6432 ins_pipe( ialu_reg_reg_fat );
6433 %}
6434
6435 instruct leaPIdxScaleOff(eRegP dst, indIndexScaleOffset mem) %{
6436 match(Set dst mem);
6437
6438 ins_cost(110);
6439 format %{ "LEA $dst,$mem" %}
6440 opcode(0x8D);
6441 ins_encode( OpcP, RegMem(dst,mem));
6442 ins_pipe( ialu_reg_reg_fat );
6443 %}
6444
6445 // Load Constant
6446 instruct loadConI(rRegI dst, immI src) %{
6447 match(Set dst src);
6448
6449 format %{ "MOV $dst,$src" %}
6450 ins_encode( LdImmI(dst, src) );
6451 ins_pipe( ialu_reg_fat );
6452 %}
6453
6454 // Load Constant zero
6455 instruct loadConI0(rRegI dst, immI0 src, eFlagsReg cr) %{
6456 match(Set dst src);
6457 effect(KILL cr);
6458
6459 ins_cost(50);
6460 format %{ "XOR $dst,$dst" %}
6461 opcode(0x33); /* + rd */
6462 ins_encode( OpcP, RegReg( dst, dst ) );
6463 ins_pipe( ialu_reg );
6464 %}
6465
6466 instruct loadConP(eRegP dst, immP src) %{
6467 match(Set dst src);
6468
6469 format %{ "MOV $dst,$src" %}
6470 opcode(0xB8); /* + rd */
6471 ins_encode( LdImmP(dst, src) );
6472 ins_pipe( ialu_reg_fat );
6473 %}
6474
6475 instruct loadConL(eRegL dst, immL src, eFlagsReg cr) %{
6476 match(Set dst src);
6477 effect(KILL cr);
6478 ins_cost(200);
6479 format %{ "MOV $dst.lo,$src.lo\n\t"
6480 "MOV $dst.hi,$src.hi" %}
6481 opcode(0xB8);
6482 ins_encode( LdImmL_Lo(dst, src), LdImmL_Hi(dst, src) );
6483 ins_pipe( ialu_reg_long_fat );
6484 %}
6485
6486 instruct loadConL0(eRegL dst, immL0 src, eFlagsReg cr) %{
6487 match(Set dst src);
6488 effect(KILL cr);
6489 ins_cost(150);
6490 format %{ "XOR $dst.lo,$dst.lo\n\t"
6491 "XOR $dst.hi,$dst.hi" %}
6492 opcode(0x33,0x33);
6493 ins_encode( RegReg_Lo(dst,dst), RegReg_Hi(dst, dst) );
6494 ins_pipe( ialu_reg_long );
6495 %}
6496
6497 // The instruction usage is guarded by predicate in operand immFPR().
6498 instruct loadConFPR(regFPR dst, immFPR con) %{
6499 match(Set dst con);
6500 ins_cost(125);
6501 format %{ "FLD_S ST,[$constantaddress]\t# load from constant table: float=$con\n\t"
6502 "FSTP $dst" %}
6503 ins_encode %{
6504 __ fld_s($constantaddress($con));
6505 __ fstp_d($dst$$reg);
6506 %}
6507 ins_pipe(fpu_reg_con);
6508 %}
6509
6510 // The instruction usage is guarded by predicate in operand immFPR0().
6511 instruct loadConFPR0(regFPR dst, immFPR0 con) %{
6512 match(Set dst con);
6513 ins_cost(125);
6514 format %{ "FLDZ ST\n\t"
6515 "FSTP $dst" %}
6516 ins_encode %{
6517 __ fldz();
6518 __ fstp_d($dst$$reg);
6519 %}
6520 ins_pipe(fpu_reg_con);
6521 %}
6522
6523 // The instruction usage is guarded by predicate in operand immFPR1().
6524 instruct loadConFPR1(regFPR dst, immFPR1 con) %{
6525 match(Set dst con);
6526 ins_cost(125);
6527 format %{ "FLD1 ST\n\t"
6528 "FSTP $dst" %}
6529 ins_encode %{
6530 __ fld1();
6531 __ fstp_d($dst$$reg);
6532 %}
6533 ins_pipe(fpu_reg_con);
6534 %}
6535
6536 // The instruction usage is guarded by predicate in operand immF().
6537 instruct loadConF(regF dst, immF con) %{
6538 match(Set dst con);
6539 ins_cost(125);
6540 format %{ "MOVSS $dst,[$constantaddress]\t# load from constant table: float=$con" %}
6541 ins_encode %{
6542 __ movflt($dst$$XMMRegister, $constantaddress($con));
6543 %}
6544 ins_pipe(pipe_slow);
6545 %}
6546
6547 // The instruction usage is guarded by predicate in operand immF0().
6548 instruct loadConF0(regF dst, immF0 src) %{
6549 match(Set dst src);
6550 ins_cost(100);
6551 format %{ "XORPS $dst,$dst\t# float 0.0" %}
6552 ins_encode %{
6553 __ xorps($dst$$XMMRegister, $dst$$XMMRegister);
6554 %}
6555 ins_pipe(pipe_slow);
6556 %}
6557
6558 // The instruction usage is guarded by predicate in operand immDPR().
6559 instruct loadConDPR(regDPR dst, immDPR con) %{
6560 match(Set dst con);
6561 ins_cost(125);
6562
6563 format %{ "FLD_D ST,[$constantaddress]\t# load from constant table: double=$con\n\t"
6564 "FSTP $dst" %}
6565 ins_encode %{
6566 __ fld_d($constantaddress($con));
6567 __ fstp_d($dst$$reg);
6568 %}
6569 ins_pipe(fpu_reg_con);
6570 %}
6571
6572 // The instruction usage is guarded by predicate in operand immDPR0().
6573 instruct loadConDPR0(regDPR dst, immDPR0 con) %{
6574 match(Set dst con);
6575 ins_cost(125);
6576
6577 format %{ "FLDZ ST\n\t"
6578 "FSTP $dst" %}
6579 ins_encode %{
6580 __ fldz();
6581 __ fstp_d($dst$$reg);
6582 %}
6583 ins_pipe(fpu_reg_con);
6584 %}
6585
6586 // The instruction usage is guarded by predicate in operand immDPR1().
6587 instruct loadConDPR1(regDPR dst, immDPR1 con) %{
6588 match(Set dst con);
6589 ins_cost(125);
6590
6591 format %{ "FLD1 ST\n\t"
6592 "FSTP $dst" %}
6593 ins_encode %{
6594 __ fld1();
6595 __ fstp_d($dst$$reg);
6596 %}
6597 ins_pipe(fpu_reg_con);
6598 %}
6599
6600 // The instruction usage is guarded by predicate in operand immD().
6601 instruct loadConD(regD dst, immD con) %{
6602 match(Set dst con);
6603 ins_cost(125);
6604 format %{ "MOVSD $dst,[$constantaddress]\t# load from constant table: double=$con" %}
6605 ins_encode %{
6606 __ movdbl($dst$$XMMRegister, $constantaddress($con));
6607 %}
6608 ins_pipe(pipe_slow);
6609 %}
6610
6611 // The instruction usage is guarded by predicate in operand immD0().
6612 instruct loadConD0(regD dst, immD0 src) %{
6613 match(Set dst src);
6614 ins_cost(100);
6615 format %{ "XORPD $dst,$dst\t# double 0.0" %}
6616 ins_encode %{
6617 __ xorpd ($dst$$XMMRegister, $dst$$XMMRegister);
6618 %}
6619 ins_pipe( pipe_slow );
6620 %}
6621
6622 // Load Stack Slot
6623 instruct loadSSI(rRegI dst, stackSlotI src) %{
6624 match(Set dst src);
6625 ins_cost(125);
6626
6627 format %{ "MOV $dst,$src" %}
6628 opcode(0x8B);
6629 ins_encode( OpcP, RegMem(dst,src));
6630 ins_pipe( ialu_reg_mem );
6631 %}
6632
6633 instruct loadSSL(eRegL dst, stackSlotL src) %{
6634 match(Set dst src);
6635
6636 ins_cost(200);
6637 format %{ "MOV $dst,$src.lo\n\t"
6638 "MOV $dst+4,$src.hi" %}
6639 opcode(0x8B, 0x8B);
6640 ins_encode( OpcP, RegMem( dst, src ), OpcS, RegMem_Hi( dst, src ) );
6641 ins_pipe( ialu_mem_long_reg );
6642 %}
6643
6644 // Load Stack Slot
6645 instruct loadSSP(eRegP dst, stackSlotP src) %{
6646 match(Set dst src);
6647 ins_cost(125);
6648
6649 format %{ "MOV $dst,$src" %}
6650 opcode(0x8B);
6651 ins_encode( OpcP, RegMem(dst,src));
6652 ins_pipe( ialu_reg_mem );
6653 %}
6654
6655 // Load Stack Slot
6656 instruct loadSSF(regFPR dst, stackSlotF src) %{
6657 match(Set dst src);
6658 ins_cost(125);
6659
6660 format %{ "FLD_S $src\n\t"
6661 "FSTP $dst" %}
6662 opcode(0xD9); /* D9 /0, FLD m32real */
6663 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
6664 Pop_Reg_FPR(dst) );
6665 ins_pipe( fpu_reg_mem );
6666 %}
6667
6668 // Load Stack Slot
6669 instruct loadSSD(regDPR dst, stackSlotD src) %{
6670 match(Set dst src);
6671 ins_cost(125);
6672
6673 format %{ "FLD_D $src\n\t"
6674 "FSTP $dst" %}
6675 opcode(0xDD); /* DD /0, FLD m64real */
6676 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
6677 Pop_Reg_DPR(dst) );
6678 ins_pipe( fpu_reg_mem );
6679 %}
6680
6681 // Prefetch instructions.
6682 // Must be safe to execute with invalid address (cannot fault).
6683
6684 instruct prefetchr0( memory mem ) %{
6685 predicate(UseSSE==0 && !VM_Version::supports_3dnow_prefetch());
6686 match(PrefetchRead mem);
6687 ins_cost(0);
6688 size(0);
6689 format %{ "PREFETCHR (non-SSE is empty encoding)" %}
6690 ins_encode();
6691 ins_pipe(empty);
6692 %}
6693
6694 instruct prefetchr( memory mem ) %{
6695 predicate(UseSSE==0 && VM_Version::supports_3dnow_prefetch() || ReadPrefetchInstr==3);
6696 match(PrefetchRead mem);
6697 ins_cost(100);
6698
6699 format %{ "PREFETCHR $mem\t! Prefetch into level 1 cache for read" %}
6700 ins_encode %{
6701 __ prefetchr($mem$$Address);
6702 %}
6703 ins_pipe(ialu_mem);
6704 %}
6705
6706 instruct prefetchrNTA( memory mem ) %{
6707 predicate(UseSSE>=1 && ReadPrefetchInstr==0);
6708 match(PrefetchRead mem);
6709 ins_cost(100);
6710
6711 format %{ "PREFETCHNTA $mem\t! Prefetch into non-temporal cache for read" %}
6712 ins_encode %{
6713 __ prefetchnta($mem$$Address);
6714 %}
6715 ins_pipe(ialu_mem);
6716 %}
6717
6718 instruct prefetchrT0( memory mem ) %{
6719 predicate(UseSSE>=1 && ReadPrefetchInstr==1);
6720 match(PrefetchRead mem);
6721 ins_cost(100);
6722
6723 format %{ "PREFETCHT0 $mem\t! Prefetch into L1 and L2 caches for read" %}
6724 ins_encode %{
6725 __ prefetcht0($mem$$Address);
6726 %}
6727 ins_pipe(ialu_mem);
6728 %}
6729
6730 instruct prefetchrT2( memory mem ) %{
6731 predicate(UseSSE>=1 && ReadPrefetchInstr==2);
6732 match(PrefetchRead mem);
6733 ins_cost(100);
6734
6735 format %{ "PREFETCHT2 $mem\t! Prefetch into L2 cache for read" %}
6736 ins_encode %{
6737 __ prefetcht2($mem$$Address);
6738 %}
6739 ins_pipe(ialu_mem);
6740 %}
6741
6742 instruct prefetchw0( memory mem ) %{
6743 predicate(UseSSE==0 && !VM_Version::supports_3dnow_prefetch());
6744 match(PrefetchWrite mem);
6745 ins_cost(0);
6746 size(0);
6747 format %{ "Prefetch (non-SSE is empty encoding)" %}
6748 ins_encode();
6749 ins_pipe(empty);
6750 %}
6751
6752 instruct prefetchw( memory mem ) %{
6753 predicate(UseSSE==0 && VM_Version::supports_3dnow_prefetch());
6754 match( PrefetchWrite mem );
6755 ins_cost(100);
6756
6757 format %{ "PREFETCHW $mem\t! Prefetch into L1 cache and mark modified" %}
6758 ins_encode %{
6759 __ prefetchw($mem$$Address);
6760 %}
6761 ins_pipe(ialu_mem);
6762 %}
6763
6764 instruct prefetchwNTA( memory mem ) %{
6765 predicate(UseSSE>=1);
6766 match(PrefetchWrite mem);
6767 ins_cost(100);
6768
6769 format %{ "PREFETCHNTA $mem\t! Prefetch into non-temporal cache for write" %}
6770 ins_encode %{
6771 __ prefetchnta($mem$$Address);
6772 %}
6773 ins_pipe(ialu_mem);
6774 %}
6775
6776 // Prefetch instructions for allocation.
6777
6778 instruct prefetchAlloc0( memory mem ) %{
6779 predicate(UseSSE==0 && AllocatePrefetchInstr!=3);
6780 match(PrefetchAllocation mem);
6781 ins_cost(0);
6782 size(0);
6783 format %{ "Prefetch allocation (non-SSE is empty encoding)" %}
6784 ins_encode();
6785 ins_pipe(empty);
6786 %}
6787
6788 instruct prefetchAlloc( memory mem ) %{
6789 predicate(AllocatePrefetchInstr==3);
6790 match( PrefetchAllocation mem );
6791 ins_cost(100);
6792
6793 format %{ "PREFETCHW $mem\t! Prefetch allocation into L1 cache and mark modified" %}
6794 ins_encode %{
6795 __ prefetchw($mem$$Address);
6796 %}
6797 ins_pipe(ialu_mem);
6798 %}
6799
6800 instruct prefetchAllocNTA( memory mem ) %{
6801 predicate(UseSSE>=1 && AllocatePrefetchInstr==0);
6802 match(PrefetchAllocation mem);
6803 ins_cost(100);
6804
6805 format %{ "PREFETCHNTA $mem\t! Prefetch allocation into non-temporal cache for write" %}
6806 ins_encode %{
6807 __ prefetchnta($mem$$Address);
6808 %}
6809 ins_pipe(ialu_mem);
6810 %}
6811
6812 instruct prefetchAllocT0( memory mem ) %{
6813 predicate(UseSSE>=1 && AllocatePrefetchInstr==1);
6814 match(PrefetchAllocation mem);
6815 ins_cost(100);
6816
6817 format %{ "PREFETCHT0 $mem\t! Prefetch allocation into L1 and L2 caches for write" %}
6818 ins_encode %{
6819 __ prefetcht0($mem$$Address);
6820 %}
6821 ins_pipe(ialu_mem);
6822 %}
6823
6824 instruct prefetchAllocT2( memory mem ) %{
6825 predicate(UseSSE>=1 && AllocatePrefetchInstr==2);
6826 match(PrefetchAllocation mem);
6827 ins_cost(100);
6828
6829 format %{ "PREFETCHT2 $mem\t! Prefetch allocation into L2 cache for write" %}
6830 ins_encode %{
6831 __ prefetcht2($mem$$Address);
6832 %}
6833 ins_pipe(ialu_mem);
6834 %}
6835
6836 //----------Store Instructions-------------------------------------------------
6837
6838 // Store Byte
6839 instruct storeB(memory mem, xRegI src) %{
6840 match(Set mem (StoreB mem src));
6841
6842 ins_cost(125);
6843 format %{ "MOV8 $mem,$src" %}
6844 opcode(0x88);
6845 ins_encode( OpcP, RegMem( src, mem ) );
6846 ins_pipe( ialu_mem_reg );
6847 %}
6848
6849 // Store Char/Short
6850 instruct storeC(memory mem, rRegI src) %{
6851 match(Set mem (StoreC mem src));
6852
6853 ins_cost(125);
6854 format %{ "MOV16 $mem,$src" %}
6855 opcode(0x89, 0x66);
6856 ins_encode( OpcS, OpcP, RegMem( src, mem ) );
6857 ins_pipe( ialu_mem_reg );
6858 %}
6859
6860 // Store Integer
6861 instruct storeI(memory mem, rRegI src) %{
6862 match(Set mem (StoreI mem src));
6863
6864 ins_cost(125);
6865 format %{ "MOV $mem,$src" %}
6866 opcode(0x89);
6867 ins_encode( OpcP, RegMem( src, mem ) );
6868 ins_pipe( ialu_mem_reg );
6869 %}
6870
6871 // Store Long
6872 instruct storeL(long_memory mem, eRegL src) %{
6873 predicate(!((StoreLNode*)n)->require_atomic_access());
6874 match(Set mem (StoreL mem src));
6875
6876 ins_cost(200);
6877 format %{ "MOV $mem,$src.lo\n\t"
6878 "MOV $mem+4,$src.hi" %}
6879 opcode(0x89, 0x89);
6880 ins_encode( OpcP, RegMem( src, mem ), OpcS, RegMem_Hi( src, mem ) );
6881 ins_pipe( ialu_mem_long_reg );
6882 %}
6883
6884 // Store Long to Integer
6885 instruct storeL2I(memory mem, eRegL src) %{
6886 match(Set mem (StoreI mem (ConvL2I src)));
6887
6888 format %{ "MOV $mem,$src.lo\t# long -> int" %}
6889 ins_encode %{
6890 __ movl($mem$$Address, $src$$Register);
6891 %}
6892 ins_pipe(ialu_mem_reg);
6893 %}
6894
6895 // Volatile Store Long. Must be atomic, so move it into
6896 // the FP TOS and then do a 64-bit FIST. Has to probe the
6897 // target address before the store (for null-ptr checks)
6898 // so the memory operand is used twice in the encoding.
6899 instruct storeL_volatile(memory mem, stackSlotL src, eFlagsReg cr ) %{
6900 predicate(UseSSE<=1 && ((StoreLNode*)n)->require_atomic_access());
6901 match(Set mem (StoreL mem src));
6902 effect( KILL cr );
6903 ins_cost(400);
6904 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t"
6905 "FILD $src\n\t"
6906 "FISTp $mem\t # 64-bit atomic volatile long store" %}
6907 opcode(0x3B);
6908 ins_encode( OpcP, RegMem( EAX, mem ), enc_storeL_volatile(mem,src));
6909 ins_pipe( fpu_reg_mem );
6910 %}
6911
6912 instruct storeLX_volatile(memory mem, stackSlotL src, regD tmp, eFlagsReg cr) %{
6913 predicate(UseSSE>=2 && ((StoreLNode*)n)->require_atomic_access());
6914 match(Set mem (StoreL mem src));
6915 effect( TEMP tmp, KILL cr );
6916 ins_cost(380);
6917 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t"
6918 "MOVSD $tmp,$src\n\t"
6919 "MOVSD $mem,$tmp\t # 64-bit atomic volatile long store" %}
6920 ins_encode %{
6921 __ cmpl(rax, $mem$$Address);
6922 __ movdbl($tmp$$XMMRegister, Address(rsp, $src$$disp));
6923 __ movdbl($mem$$Address, $tmp$$XMMRegister);
6924 %}
6925 ins_pipe( pipe_slow );
6926 %}
6927
6928 instruct storeLX_reg_volatile(memory mem, eRegL src, regD tmp2, regD tmp, eFlagsReg cr) %{
6929 predicate(UseSSE>=2 && ((StoreLNode*)n)->require_atomic_access());
6930 match(Set mem (StoreL mem src));
6931 effect( TEMP tmp2 , TEMP tmp, KILL cr );
6932 ins_cost(360);
6933 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t"
6934 "MOVD $tmp,$src.lo\n\t"
6935 "MOVD $tmp2,$src.hi\n\t"
6936 "PUNPCKLDQ $tmp,$tmp2\n\t"
6937 "MOVSD $mem,$tmp\t # 64-bit atomic volatile long store" %}
6938 ins_encode %{
6939 __ cmpl(rax, $mem$$Address);
6940 __ movdl($tmp$$XMMRegister, $src$$Register);
6941 __ movdl($tmp2$$XMMRegister, HIGH_FROM_LOW($src$$Register));
6942 __ punpckldq($tmp$$XMMRegister, $tmp2$$XMMRegister);
6943 __ movdbl($mem$$Address, $tmp$$XMMRegister);
6944 %}
6945 ins_pipe( pipe_slow );
6946 %}
6947
6948 // Store Pointer; for storing unknown oops and raw pointers
6949 instruct storeP(memory mem, anyRegP src) %{
6950 match(Set mem (StoreP mem src));
6951
6952 ins_cost(125);
6953 format %{ "MOV $mem,$src" %}
6954 opcode(0x89);
6955 ins_encode( OpcP, RegMem( src, mem ) );
6956 ins_pipe( ialu_mem_reg );
6957 %}
6958
6959 // Store Integer Immediate
6960 instruct storeImmI(memory mem, immI src) %{
6961 match(Set mem (StoreI mem src));
6962
6963 ins_cost(150);
6964 format %{ "MOV $mem,$src" %}
6965 opcode(0xC7); /* C7 /0 */
6966 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32( src ));
6967 ins_pipe( ialu_mem_imm );
6968 %}
6969
6970 // Store Short/Char Immediate
6971 instruct storeImmI16(memory mem, immI16 src) %{
6972 predicate(UseStoreImmI16);
6973 match(Set mem (StoreC mem src));
6974
6975 ins_cost(150);
6976 format %{ "MOV16 $mem,$src" %}
6977 opcode(0xC7); /* C7 /0 Same as 32 store immediate with prefix */
6978 ins_encode( SizePrefix, OpcP, RMopc_Mem(0x00,mem), Con16( src ));
6979 ins_pipe( ialu_mem_imm );
6980 %}
6981
6982 // Store Pointer Immediate; null pointers or constant oops that do not
6983 // need card-mark barriers.
6984 instruct storeImmP(memory mem, immP src) %{
6985 match(Set mem (StoreP mem src));
6986
6987 ins_cost(150);
6988 format %{ "MOV $mem,$src" %}
6989 opcode(0xC7); /* C7 /0 */
6990 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32( src ));
6991 ins_pipe( ialu_mem_imm );
6992 %}
6993
6994 // Store Byte Immediate
6995 instruct storeImmB(memory mem, immI8 src) %{
6996 match(Set mem (StoreB mem src));
6997
6998 ins_cost(150);
6999 format %{ "MOV8 $mem,$src" %}
7000 opcode(0xC6); /* C6 /0 */
7001 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con8or32( src ));
7002 ins_pipe( ialu_mem_imm );
7003 %}
7004
7005 // Store CMS card-mark Immediate
7006 instruct storeImmCM(memory mem, immI8 src) %{
7007 match(Set mem (StoreCM mem src));
7008
7009 ins_cost(150);
7010 format %{ "MOV8 $mem,$src\t! CMS card-mark imm0" %}
7011 opcode(0xC6); /* C6 /0 */
7012 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con8or32( src ));
7013 ins_pipe( ialu_mem_imm );
7014 %}
7015
7016 // Store Double
7017 instruct storeDPR( memory mem, regDPR1 src) %{
7018 predicate(UseSSE<=1);
7019 match(Set mem (StoreD mem src));
7020
7021 ins_cost(100);
7022 format %{ "FST_D $mem,$src" %}
7023 opcode(0xDD); /* DD /2 */
7024 ins_encode( enc_FPR_store(mem,src) );
7025 ins_pipe( fpu_mem_reg );
7026 %}
7027
7028 // Store double does rounding on x86
7029 instruct storeDPR_rounded( memory mem, regDPR1 src) %{
7030 predicate(UseSSE<=1);
7031 match(Set mem (StoreD mem (RoundDouble src)));
7032
7033 ins_cost(100);
7034 format %{ "FST_D $mem,$src\t# round" %}
7035 opcode(0xDD); /* DD /2 */
7036 ins_encode( enc_FPR_store(mem,src) );
7037 ins_pipe( fpu_mem_reg );
7038 %}
7039
7040 // Store XMM register to memory (double-precision floating points)
7041 // MOVSD instruction
7042 instruct storeD(memory mem, regD src) %{
7043 predicate(UseSSE>=2);
7044 match(Set mem (StoreD mem src));
7045 ins_cost(95);
7046 format %{ "MOVSD $mem,$src" %}
7047 ins_encode %{
7048 __ movdbl($mem$$Address, $src$$XMMRegister);
7049 %}
7050 ins_pipe( pipe_slow );
7051 %}
7052
7053 // Store XMM register to memory (single-precision floating point)
7054 // MOVSS instruction
7055 instruct storeF(memory mem, regF src) %{
7056 predicate(UseSSE>=1);
7057 match(Set mem (StoreF mem src));
7058 ins_cost(95);
7059 format %{ "MOVSS $mem,$src" %}
7060 ins_encode %{
7061 __ movflt($mem$$Address, $src$$XMMRegister);
7062 %}
7063 ins_pipe( pipe_slow );
7064 %}
7065
7066 // Store Float
7067 instruct storeFPR( memory mem, regFPR1 src) %{
7068 predicate(UseSSE==0);
7069 match(Set mem (StoreF mem src));
7070
7071 ins_cost(100);
7072 format %{ "FST_S $mem,$src" %}
7073 opcode(0xD9); /* D9 /2 */
7074 ins_encode( enc_FPR_store(mem,src) );
7075 ins_pipe( fpu_mem_reg );
7076 %}
7077
7078 // Store Float does rounding on x86
7079 instruct storeFPR_rounded( memory mem, regFPR1 src) %{
7080 predicate(UseSSE==0);
7081 match(Set mem (StoreF mem (RoundFloat src)));
7082
7083 ins_cost(100);
7084 format %{ "FST_S $mem,$src\t# round" %}
7085 opcode(0xD9); /* D9 /2 */
7086 ins_encode( enc_FPR_store(mem,src) );
7087 ins_pipe( fpu_mem_reg );
7088 %}
7089
7090 // Store Float does rounding on x86
7091 instruct storeFPR_Drounded( memory mem, regDPR1 src) %{
7092 predicate(UseSSE<=1);
7093 match(Set mem (StoreF mem (ConvD2F src)));
7094
7095 ins_cost(100);
7096 format %{ "FST_S $mem,$src\t# D-round" %}
7097 opcode(0xD9); /* D9 /2 */
7098 ins_encode( enc_FPR_store(mem,src) );
7099 ins_pipe( fpu_mem_reg );
7100 %}
7101
7102 // Store immediate Float value (it is faster than store from FPU register)
7103 // The instruction usage is guarded by predicate in operand immFPR().
7104 instruct storeFPR_imm( memory mem, immFPR src) %{
7105 match(Set mem (StoreF mem src));
7106
7107 ins_cost(50);
7108 format %{ "MOV $mem,$src\t# store float" %}
7109 opcode(0xC7); /* C7 /0 */
7110 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32FPR_as_bits( src ));
7111 ins_pipe( ialu_mem_imm );
7112 %}
7113
7114 // Store immediate Float value (it is faster than store from XMM register)
7115 // The instruction usage is guarded by predicate in operand immF().
7116 instruct storeF_imm( memory mem, immF src) %{
7117 match(Set mem (StoreF mem src));
7118
7119 ins_cost(50);
7120 format %{ "MOV $mem,$src\t# store float" %}
7121 opcode(0xC7); /* C7 /0 */
7122 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32F_as_bits( src ));
7123 ins_pipe( ialu_mem_imm );
7124 %}
7125
7126 // Store Integer to stack slot
7127 instruct storeSSI(stackSlotI dst, rRegI src) %{
7128 match(Set dst src);
7129
7130 ins_cost(100);
7131 format %{ "MOV $dst,$src" %}
7132 opcode(0x89);
7133 ins_encode( OpcPRegSS( dst, src ) );
7134 ins_pipe( ialu_mem_reg );
7135 %}
7136
7137 // Store Integer to stack slot
7138 instruct storeSSP(stackSlotP dst, eRegP src) %{
7139 match(Set dst src);
7140
7141 ins_cost(100);
7142 format %{ "MOV $dst,$src" %}
7143 opcode(0x89);
7144 ins_encode( OpcPRegSS( dst, src ) );
7145 ins_pipe( ialu_mem_reg );
7146 %}
7147
7148 // Store Long to stack slot
7149 instruct storeSSL(stackSlotL dst, eRegL src) %{
7150 match(Set dst src);
7151
7152 ins_cost(200);
7153 format %{ "MOV $dst,$src.lo\n\t"
7154 "MOV $dst+4,$src.hi" %}
7155 opcode(0x89, 0x89);
7156 ins_encode( OpcP, RegMem( src, dst ), OpcS, RegMem_Hi( src, dst ) );
7157 ins_pipe( ialu_mem_long_reg );
7158 %}
7159
7160 //----------MemBar Instructions-----------------------------------------------
7161 // Memory barrier flavors
7162
7163 instruct membar_acquire() %{
7164 match(MemBarAcquire);
7165 ins_cost(400);
7166
7167 size(0);
7168 format %{ "MEMBAR-acquire ! (empty encoding)" %}
7169 ins_encode();
7170 ins_pipe(empty);
7171 %}
7172
7173 instruct membar_acquire_lock() %{
7174 match(MemBarAcquireLock);
7175 ins_cost(0);
7176
7177 size(0);
7178 format %{ "MEMBAR-acquire (prior CMPXCHG in FastLock so empty encoding)" %}
7179 ins_encode( );
7180 ins_pipe(empty);
7181 %}
7182
7183 instruct membar_release() %{
7184 match(MemBarRelease);
7185 ins_cost(400);
7186
7187 size(0);
7188 format %{ "MEMBAR-release ! (empty encoding)" %}
7189 ins_encode( );
7190 ins_pipe(empty);
7191 %}
7192
7193 instruct membar_release_lock() %{
7194 match(MemBarReleaseLock);
7195 ins_cost(0);
7196
7197 size(0);
7198 format %{ "MEMBAR-release (a FastUnlock follows so empty encoding)" %}
7199 ins_encode( );
7200 ins_pipe(empty);
7201 %}
7202
7203 instruct membar_volatile(eFlagsReg cr) %{
7204 match(MemBarVolatile);
7205 effect(KILL cr);
7206 ins_cost(400);
7207
7208 format %{
7209 $$template
7210 if (os::is_MP()) {
7211 $$emit$$"LOCK ADDL [ESP + #0], 0\t! membar_volatile"
7212 } else {
7213 $$emit$$"MEMBAR-volatile ! (empty encoding)"
7214 }
7215 %}
7216 ins_encode %{
7217 __ membar(Assembler::StoreLoad);
7218 %}
7219 ins_pipe(pipe_slow);
7220 %}
7221
7222 instruct unnecessary_membar_volatile() %{
7223 match(MemBarVolatile);
7224 predicate(Matcher::post_store_load_barrier(n));
7225 ins_cost(0);
7226
7227 size(0);
7228 format %{ "MEMBAR-volatile (unnecessary so empty encoding)" %}
7229 ins_encode( );
7230 ins_pipe(empty);
7231 %}
7232
7233 instruct membar_storestore() %{
7234 match(MemBarStoreStore);
7235 ins_cost(0);
7236
7237 size(0);
7238 format %{ "MEMBAR-storestore (empty encoding)" %}
7239 ins_encode( );
7240 ins_pipe(empty);
7241 %}
7242
7243 //----------Move Instructions--------------------------------------------------
7244 instruct castX2P(eAXRegP dst, eAXRegI src) %{
7245 match(Set dst (CastX2P src));
7246 format %{ "# X2P $dst, $src" %}
7247 ins_encode( /*empty encoding*/ );
7248 ins_cost(0);
7249 ins_pipe(empty);
7250 %}
7251
7252 instruct castP2X(rRegI dst, eRegP src ) %{
7253 match(Set dst (CastP2X src));
7254 ins_cost(50);
7255 format %{ "MOV $dst, $src\t# CastP2X" %}
7256 ins_encode( enc_Copy( dst, src) );
7257 ins_pipe( ialu_reg_reg );
7258 %}
7259
7260 //----------Conditional Move---------------------------------------------------
7261 // Conditional move
7262 instruct jmovI_reg(cmpOp cop, eFlagsReg cr, rRegI dst, rRegI src) %{
7263 predicate(!VM_Version::supports_cmov() );
7264 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7265 ins_cost(200);
7266 format %{ "J$cop,us skip\t# signed cmove\n\t"
7267 "MOV $dst,$src\n"
7268 "skip:" %}
7269 ins_encode %{
7270 Label Lskip;
7271 // Invert sense of branch from sense of CMOV
7272 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
7273 __ movl($dst$$Register, $src$$Register);
7274 __ bind(Lskip);
7275 %}
7276 ins_pipe( pipe_cmov_reg );
7277 %}
7278
7279 instruct jmovI_regU(cmpOpU cop, eFlagsRegU cr, rRegI dst, rRegI src) %{
7280 predicate(!VM_Version::supports_cmov() );
7281 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7282 ins_cost(200);
7283 format %{ "J$cop,us skip\t# unsigned cmove\n\t"
7284 "MOV $dst,$src\n"
7285 "skip:" %}
7286 ins_encode %{
7287 Label Lskip;
7288 // Invert sense of branch from sense of CMOV
7289 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
7290 __ movl($dst$$Register, $src$$Register);
7291 __ bind(Lskip);
7292 %}
7293 ins_pipe( pipe_cmov_reg );
7294 %}
7295
7296 instruct cmovI_reg(rRegI dst, rRegI src, eFlagsReg cr, cmpOp cop ) %{
7297 predicate(VM_Version::supports_cmov() );
7298 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7299 ins_cost(200);
7300 format %{ "CMOV$cop $dst,$src" %}
7301 opcode(0x0F,0x40);
7302 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
7303 ins_pipe( pipe_cmov_reg );
7304 %}
7305
7306 instruct cmovI_regU( cmpOpU cop, eFlagsRegU cr, rRegI dst, rRegI src ) %{
7307 predicate(VM_Version::supports_cmov() );
7308 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7309 ins_cost(200);
7310 format %{ "CMOV$cop $dst,$src" %}
7311 opcode(0x0F,0x40);
7312 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
7313 ins_pipe( pipe_cmov_reg );
7314 %}
7315
7316 instruct cmovI_regUCF( cmpOpUCF cop, eFlagsRegUCF cr, rRegI dst, rRegI src ) %{
7317 predicate(VM_Version::supports_cmov() );
7318 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7319 ins_cost(200);
7320 expand %{
7321 cmovI_regU(cop, cr, dst, src);
7322 %}
7323 %}
7324
7325 // Conditional move
7326 instruct cmovI_mem(cmpOp cop, eFlagsReg cr, rRegI dst, memory src) %{
7327 predicate(VM_Version::supports_cmov() );
7328 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
7329 ins_cost(250);
7330 format %{ "CMOV$cop $dst,$src" %}
7331 opcode(0x0F,0x40);
7332 ins_encode( enc_cmov(cop), RegMem( dst, src ) );
7333 ins_pipe( pipe_cmov_mem );
7334 %}
7335
7336 // Conditional move
7337 instruct cmovI_memU(cmpOpU cop, eFlagsRegU cr, rRegI dst, memory src) %{
7338 predicate(VM_Version::supports_cmov() );
7339 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
7340 ins_cost(250);
7341 format %{ "CMOV$cop $dst,$src" %}
7342 opcode(0x0F,0x40);
7343 ins_encode( enc_cmov(cop), RegMem( dst, src ) );
7344 ins_pipe( pipe_cmov_mem );
7345 %}
7346
7347 instruct cmovI_memUCF(cmpOpUCF cop, eFlagsRegUCF cr, rRegI dst, memory src) %{
7348 predicate(VM_Version::supports_cmov() );
7349 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
7350 ins_cost(250);
7351 expand %{
7352 cmovI_memU(cop, cr, dst, src);
7353 %}
7354 %}
7355
7356 // Conditional move
7357 instruct cmovP_reg(eRegP dst, eRegP src, eFlagsReg cr, cmpOp cop ) %{
7358 predicate(VM_Version::supports_cmov() );
7359 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7360 ins_cost(200);
7361 format %{ "CMOV$cop $dst,$src\t# ptr" %}
7362 opcode(0x0F,0x40);
7363 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
7364 ins_pipe( pipe_cmov_reg );
7365 %}
7366
7367 // Conditional move (non-P6 version)
7368 // Note: a CMoveP is generated for stubs and native wrappers
7369 // regardless of whether we are on a P6, so we
7370 // emulate a cmov here
7371 instruct cmovP_reg_nonP6(eRegP dst, eRegP src, eFlagsReg cr, cmpOp cop ) %{
7372 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7373 ins_cost(300);
7374 format %{ "Jn$cop skip\n\t"
7375 "MOV $dst,$src\t# pointer\n"
7376 "skip:" %}
7377 opcode(0x8b);
7378 ins_encode( enc_cmov_branch(cop, 0x2), OpcP, RegReg(dst, src));
7379 ins_pipe( pipe_cmov_reg );
7380 %}
7381
7382 // Conditional move
7383 instruct cmovP_regU(cmpOpU cop, eFlagsRegU cr, eRegP dst, eRegP src ) %{
7384 predicate(VM_Version::supports_cmov() );
7385 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7386 ins_cost(200);
7387 format %{ "CMOV$cop $dst,$src\t# ptr" %}
7388 opcode(0x0F,0x40);
7389 ins_encode( enc_cmov(cop), RegReg( dst, src ) );
7390 ins_pipe( pipe_cmov_reg );
7391 %}
7392
7393 instruct cmovP_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, eRegP dst, eRegP src ) %{
7394 predicate(VM_Version::supports_cmov() );
7395 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7396 ins_cost(200);
7397 expand %{
7398 cmovP_regU(cop, cr, dst, src);
7399 %}
7400 %}
7401
7402 // DISABLED: Requires the ADLC to emit a bottom_type call that
7403 // correctly meets the two pointer arguments; one is an incoming
7404 // register but the other is a memory operand. ALSO appears to
7405 // be buggy with implicit null checks.
7406 //
7407 //// Conditional move
7408 //instruct cmovP_mem(cmpOp cop, eFlagsReg cr, eRegP dst, memory src) %{
7409 // predicate(VM_Version::supports_cmov() );
7410 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
7411 // ins_cost(250);
7412 // format %{ "CMOV$cop $dst,$src\t# ptr" %}
7413 // opcode(0x0F,0x40);
7414 // ins_encode( enc_cmov(cop), RegMem( dst, src ) );
7415 // ins_pipe( pipe_cmov_mem );
7416 //%}
7417 //
7418 //// Conditional move
7419 //instruct cmovP_memU(cmpOpU cop, eFlagsRegU cr, eRegP dst, memory src) %{
7420 // predicate(VM_Version::supports_cmov() );
7421 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
7422 // ins_cost(250);
7423 // format %{ "CMOV$cop $dst,$src\t# ptr" %}
7424 // opcode(0x0F,0x40);
7425 // ins_encode( enc_cmov(cop), RegMem( dst, src ) );
7426 // ins_pipe( pipe_cmov_mem );
7427 //%}
7428
7429 // Conditional move
7430 instruct fcmovDPR_regU(cmpOp_fcmov cop, eFlagsRegU cr, regDPR1 dst, regDPR src) %{
7431 predicate(UseSSE<=1);
7432 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7433 ins_cost(200);
7434 format %{ "FCMOV$cop $dst,$src\t# double" %}
7435 opcode(0xDA);
7436 ins_encode( enc_cmov_dpr(cop,src) );
7437 ins_pipe( pipe_cmovDPR_reg );
7438 %}
7439
7440 // Conditional move
7441 instruct fcmovFPR_regU(cmpOp_fcmov cop, eFlagsRegU cr, regFPR1 dst, regFPR src) %{
7442 predicate(UseSSE==0);
7443 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7444 ins_cost(200);
7445 format %{ "FCMOV$cop $dst,$src\t# float" %}
7446 opcode(0xDA);
7447 ins_encode( enc_cmov_dpr(cop,src) );
7448 ins_pipe( pipe_cmovDPR_reg );
7449 %}
7450
7451 // Float CMOV on Intel doesn't handle *signed* compares, only unsigned.
7452 instruct fcmovDPR_regS(cmpOp cop, eFlagsReg cr, regDPR dst, regDPR src) %{
7453 predicate(UseSSE<=1);
7454 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7455 ins_cost(200);
7456 format %{ "Jn$cop skip\n\t"
7457 "MOV $dst,$src\t# double\n"
7458 "skip:" %}
7459 opcode (0xdd, 0x3); /* DD D8+i or DD /3 */
7460 ins_encode( enc_cmov_branch( cop, 0x4 ), Push_Reg_DPR(src), OpcP, RegOpc(dst) );
7461 ins_pipe( pipe_cmovDPR_reg );
7462 %}
7463
7464 // Float CMOV on Intel doesn't handle *signed* compares, only unsigned.
7465 instruct fcmovFPR_regS(cmpOp cop, eFlagsReg cr, regFPR dst, regFPR src) %{
7466 predicate(UseSSE==0);
7467 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7468 ins_cost(200);
7469 format %{ "Jn$cop skip\n\t"
7470 "MOV $dst,$src\t# float\n"
7471 "skip:" %}
7472 opcode (0xdd, 0x3); /* DD D8+i or DD /3 */
7473 ins_encode( enc_cmov_branch( cop, 0x4 ), Push_Reg_FPR(src), OpcP, RegOpc(dst) );
7474 ins_pipe( pipe_cmovDPR_reg );
7475 %}
7476
7477 // No CMOVE with SSE/SSE2
7478 instruct fcmovF_regS(cmpOp cop, eFlagsReg cr, regF dst, regF src) %{
7479 predicate (UseSSE>=1);
7480 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7481 ins_cost(200);
7482 format %{ "Jn$cop skip\n\t"
7483 "MOVSS $dst,$src\t# float\n"
7484 "skip:" %}
7485 ins_encode %{
7486 Label skip;
7487 // Invert sense of branch from sense of CMOV
7488 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
7489 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
7490 __ bind(skip);
7491 %}
7492 ins_pipe( pipe_slow );
7493 %}
7494
7495 // No CMOVE with SSE/SSE2
7496 instruct fcmovD_regS(cmpOp cop, eFlagsReg cr, regD dst, regD src) %{
7497 predicate (UseSSE>=2);
7498 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7499 ins_cost(200);
7500 format %{ "Jn$cop skip\n\t"
7501 "MOVSD $dst,$src\t# float\n"
7502 "skip:" %}
7503 ins_encode %{
7504 Label skip;
7505 // Invert sense of branch from sense of CMOV
7506 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
7507 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
7508 __ bind(skip);
7509 %}
7510 ins_pipe( pipe_slow );
7511 %}
7512
7513 // unsigned version
7514 instruct fcmovF_regU(cmpOpU cop, eFlagsRegU cr, regF dst, regF src) %{
7515 predicate (UseSSE>=1);
7516 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7517 ins_cost(200);
7518 format %{ "Jn$cop skip\n\t"
7519 "MOVSS $dst,$src\t# float\n"
7520 "skip:" %}
7521 ins_encode %{
7522 Label skip;
7523 // Invert sense of branch from sense of CMOV
7524 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
7525 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
7526 __ bind(skip);
7527 %}
7528 ins_pipe( pipe_slow );
7529 %}
7530
7531 instruct fcmovF_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, regF dst, regF src) %{
7532 predicate (UseSSE>=1);
7533 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7534 ins_cost(200);
7535 expand %{
7536 fcmovF_regU(cop, cr, dst, src);
7537 %}
7538 %}
7539
7540 // unsigned version
7541 instruct fcmovD_regU(cmpOpU cop, eFlagsRegU cr, regD dst, regD src) %{
7542 predicate (UseSSE>=2);
7543 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7544 ins_cost(200);
7545 format %{ "Jn$cop skip\n\t"
7546 "MOVSD $dst,$src\t# float\n"
7547 "skip:" %}
7548 ins_encode %{
7549 Label skip;
7550 // Invert sense of branch from sense of CMOV
7551 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip);
7552 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
7553 __ bind(skip);
7554 %}
7555 ins_pipe( pipe_slow );
7556 %}
7557
7558 instruct fcmovD_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, regD dst, regD src) %{
7559 predicate (UseSSE>=2);
7560 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7561 ins_cost(200);
7562 expand %{
7563 fcmovD_regU(cop, cr, dst, src);
7564 %}
7565 %}
7566
7567 instruct cmovL_reg(cmpOp cop, eFlagsReg cr, eRegL dst, eRegL src) %{
7568 predicate(VM_Version::supports_cmov() );
7569 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
7570 ins_cost(200);
7571 format %{ "CMOV$cop $dst.lo,$src.lo\n\t"
7572 "CMOV$cop $dst.hi,$src.hi" %}
7573 opcode(0x0F,0x40);
7574 ins_encode( enc_cmov(cop), RegReg_Lo2( dst, src ), enc_cmov(cop), RegReg_Hi2( dst, src ) );
7575 ins_pipe( pipe_cmov_reg_long );
7576 %}
7577
7578 instruct cmovL_regU(cmpOpU cop, eFlagsRegU cr, eRegL dst, eRegL src) %{
7579 predicate(VM_Version::supports_cmov() );
7580 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
7581 ins_cost(200);
7582 format %{ "CMOV$cop $dst.lo,$src.lo\n\t"
7583 "CMOV$cop $dst.hi,$src.hi" %}
7584 opcode(0x0F,0x40);
7585 ins_encode( enc_cmov(cop), RegReg_Lo2( dst, src ), enc_cmov(cop), RegReg_Hi2( dst, src ) );
7586 ins_pipe( pipe_cmov_reg_long );
7587 %}
7588
7589 instruct cmovL_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, eRegL dst, eRegL src) %{
7590 predicate(VM_Version::supports_cmov() );
7591 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
7592 ins_cost(200);
7593 expand %{
7594 cmovL_regU(cop, cr, dst, src);
7595 %}
7596 %}
7597
7598 //----------Arithmetic Instructions--------------------------------------------
7599 //----------Addition Instructions----------------------------------------------
7600 // Integer Addition Instructions
7601 instruct addI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
7602 match(Set dst (AddI dst src));
7603 effect(KILL cr);
7604
7605 size(2);
7606 format %{ "ADD $dst,$src" %}
7607 opcode(0x03);
7608 ins_encode( OpcP, RegReg( dst, src) );
7609 ins_pipe( ialu_reg_reg );
7610 %}
7611
7612 instruct addI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{
7613 match(Set dst (AddI dst src));
7614 effect(KILL cr);
7615
7616 format %{ "ADD $dst,$src" %}
7617 opcode(0x81, 0x00); /* /0 id */
7618 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
7619 ins_pipe( ialu_reg );
7620 %}
7621
7622 instruct incI_eReg(rRegI dst, immI1 src, eFlagsReg cr) %{
7623 predicate(UseIncDec);
7624 match(Set dst (AddI dst src));
7625 effect(KILL cr);
7626
7627 size(1);
7628 format %{ "INC $dst" %}
7629 opcode(0x40); /* */
7630 ins_encode( Opc_plus( primary, dst ) );
7631 ins_pipe( ialu_reg );
7632 %}
7633
7634 instruct leaI_eReg_immI(rRegI dst, rRegI src0, immI src1) %{
7635 match(Set dst (AddI src0 src1));
7636 ins_cost(110);
7637
7638 format %{ "LEA $dst,[$src0 + $src1]" %}
7639 opcode(0x8D); /* 0x8D /r */
7640 ins_encode( OpcP, RegLea( dst, src0, src1 ) );
7641 ins_pipe( ialu_reg_reg );
7642 %}
7643
7644 instruct leaP_eReg_immI(eRegP dst, eRegP src0, immI src1) %{
7645 match(Set dst (AddP src0 src1));
7646 ins_cost(110);
7647
7648 format %{ "LEA $dst,[$src0 + $src1]\t# ptr" %}
7649 opcode(0x8D); /* 0x8D /r */
7650 ins_encode( OpcP, RegLea( dst, src0, src1 ) );
7651 ins_pipe( ialu_reg_reg );
7652 %}
7653
7654 instruct decI_eReg(rRegI dst, immI_M1 src, eFlagsReg cr) %{
7655 predicate(UseIncDec);
7656 match(Set dst (AddI dst src));
7657 effect(KILL cr);
7658
7659 size(1);
7660 format %{ "DEC $dst" %}
7661 opcode(0x48); /* */
7662 ins_encode( Opc_plus( primary, dst ) );
7663 ins_pipe( ialu_reg );
7664 %}
7665
7666 instruct addP_eReg(eRegP dst, rRegI src, eFlagsReg cr) %{
7667 match(Set dst (AddP dst src));
7668 effect(KILL cr);
7669
7670 size(2);
7671 format %{ "ADD $dst,$src" %}
7672 opcode(0x03);
7673 ins_encode( OpcP, RegReg( dst, src) );
7674 ins_pipe( ialu_reg_reg );
7675 %}
7676
7677 instruct addP_eReg_imm(eRegP dst, immI src, eFlagsReg cr) %{
7678 match(Set dst (AddP dst src));
7679 effect(KILL cr);
7680
7681 format %{ "ADD $dst,$src" %}
7682 opcode(0x81,0x00); /* Opcode 81 /0 id */
7683 // ins_encode( RegImm( dst, src) );
7684 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
7685 ins_pipe( ialu_reg );
7686 %}
7687
7688 instruct addI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{
7689 match(Set dst (AddI dst (LoadI src)));
7690 effect(KILL cr);
7691
7692 ins_cost(125);
7693 format %{ "ADD $dst,$src" %}
7694 opcode(0x03);
7695 ins_encode( OpcP, RegMem( dst, src) );
7696 ins_pipe( ialu_reg_mem );
7697 %}
7698
7699 instruct addI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{
7700 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7701 effect(KILL cr);
7702
7703 ins_cost(150);
7704 format %{ "ADD $dst,$src" %}
7705 opcode(0x01); /* Opcode 01 /r */
7706 ins_encode( OpcP, RegMem( src, dst ) );
7707 ins_pipe( ialu_mem_reg );
7708 %}
7709
7710 // Add Memory with Immediate
7711 instruct addI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
7712 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7713 effect(KILL cr);
7714
7715 ins_cost(125);
7716 format %{ "ADD $dst,$src" %}
7717 opcode(0x81); /* Opcode 81 /0 id */
7718 ins_encode( OpcSE( src ), RMopc_Mem(0x00,dst), Con8or32( src ) );
7719 ins_pipe( ialu_mem_imm );
7720 %}
7721
7722 instruct incI_mem(memory dst, immI1 src, eFlagsReg cr) %{
7723 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7724 effect(KILL cr);
7725
7726 ins_cost(125);
7727 format %{ "INC $dst" %}
7728 opcode(0xFF); /* Opcode FF /0 */
7729 ins_encode( OpcP, RMopc_Mem(0x00,dst));
7730 ins_pipe( ialu_mem_imm );
7731 %}
7732
7733 instruct decI_mem(memory dst, immI_M1 src, eFlagsReg cr) %{
7734 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7735 effect(KILL cr);
7736
7737 ins_cost(125);
7738 format %{ "DEC $dst" %}
7739 opcode(0xFF); /* Opcode FF /1 */
7740 ins_encode( OpcP, RMopc_Mem(0x01,dst));
7741 ins_pipe( ialu_mem_imm );
7742 %}
7743
7744
7745 instruct checkCastPP( eRegP dst ) %{
7746 match(Set dst (CheckCastPP dst));
7747
7748 size(0);
7749 format %{ "#checkcastPP of $dst" %}
7750 ins_encode( /*empty encoding*/ );
7751 ins_pipe( empty );
7752 %}
7753
7754 instruct castPP( eRegP dst ) %{
7755 match(Set dst (CastPP dst));
7756 format %{ "#castPP of $dst" %}
7757 ins_encode( /*empty encoding*/ );
7758 ins_pipe( empty );
7759 %}
7760
7761 instruct castII( rRegI dst ) %{
7762 match(Set dst (CastII dst));
7763 format %{ "#castII of $dst" %}
7764 ins_encode( /*empty encoding*/ );
7765 ins_cost(0);
7766 ins_pipe( empty );
7767 %}
7768
7769
7770 // Load-locked - same as a regular pointer load when used with compare-swap
7771 instruct loadPLocked(eRegP dst, memory mem) %{
7772 match(Set dst (LoadPLocked mem));
7773
7774 ins_cost(125);
7775 format %{ "MOV $dst,$mem\t# Load ptr. locked" %}
7776 opcode(0x8B);
7777 ins_encode( OpcP, RegMem(dst,mem));
7778 ins_pipe( ialu_reg_mem );
7779 %}
7780
7781 // Conditional-store of the updated heap-top.
7782 // Used during allocation of the shared heap.
7783 // Sets flags (EQ) on success. Implemented with a CMPXCHG on Intel.
7784 instruct storePConditional( memory heap_top_ptr, eAXRegP oldval, eRegP newval, eFlagsReg cr ) %{
7785 match(Set cr (StorePConditional heap_top_ptr (Binary oldval newval)));
7786 // EAX is killed if there is contention, but then it's also unused.
7787 // In the common case of no contention, EAX holds the new oop address.
7788 format %{ "CMPXCHG $heap_top_ptr,$newval\t# If EAX==$heap_top_ptr Then store $newval into $heap_top_ptr" %}
7789 ins_encode( lock_prefix, Opcode(0x0F), Opcode(0xB1), RegMem(newval,heap_top_ptr) );
7790 ins_pipe( pipe_cmpxchg );
7791 %}
7792
7793 // Conditional-store of an int value.
7794 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG on Intel.
7795 instruct storeIConditional( memory mem, eAXRegI oldval, rRegI newval, eFlagsReg cr ) %{
7796 match(Set cr (StoreIConditional mem (Binary oldval newval)));
7797 effect(KILL oldval);
7798 format %{ "CMPXCHG $mem,$newval\t# If EAX==$mem Then store $newval into $mem" %}
7799 ins_encode( lock_prefix, Opcode(0x0F), Opcode(0xB1), RegMem(newval, mem) );
7800 ins_pipe( pipe_cmpxchg );
7801 %}
7802
7803 // Conditional-store of a long value.
7804 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG8 on Intel.
7805 instruct storeLConditional( memory mem, eADXRegL oldval, eBCXRegL newval, eFlagsReg cr ) %{
7806 match(Set cr (StoreLConditional mem (Binary oldval newval)));
7807 effect(KILL oldval);
7808 format %{ "XCHG EBX,ECX\t# correct order for CMPXCHG8 instruction\n\t"
7809 "CMPXCHG8 $mem,ECX:EBX\t# If EDX:EAX==$mem Then store ECX:EBX into $mem\n\t"
7810 "XCHG EBX,ECX"
7811 %}
7812 ins_encode %{
7813 // Note: we need to swap rbx, and rcx before and after the
7814 // cmpxchg8 instruction because the instruction uses
7815 // rcx as the high order word of the new value to store but
7816 // our register encoding uses rbx.
7817 __ xchgl(as_Register(EBX_enc), as_Register(ECX_enc));
7818 if( os::is_MP() )
7819 __ lock();
7820 __ cmpxchg8($mem$$Address);
7821 __ xchgl(as_Register(EBX_enc), as_Register(ECX_enc));
7822 %}
7823 ins_pipe( pipe_cmpxchg );
7824 %}
7825
7826 // No flag versions for CompareAndSwap{P,I,L} because matcher can't match them
7827
7828 instruct compareAndSwapL( rRegI res, eSIRegP mem_ptr, eADXRegL oldval, eBCXRegL newval, eFlagsReg cr ) %{
7829 predicate(VM_Version::supports_cx8());
7830 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval)));
7831 effect(KILL cr, KILL oldval);
7832 format %{ "CMPXCHG8 [$mem_ptr],$newval\t# If EDX:EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t"
7833 "MOV $res,0\n\t"
7834 "JNE,s fail\n\t"
7835 "MOV $res,1\n"
7836 "fail:" %}
7837 ins_encode( enc_cmpxchg8(mem_ptr),
7838 enc_flags_ne_to_boolean(res) );
7839 ins_pipe( pipe_cmpxchg );
7840 %}
7841
7842 instruct compareAndSwapP( rRegI res, pRegP mem_ptr, eAXRegP oldval, eCXRegP newval, eFlagsReg cr) %{
7843 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval)));
7844 effect(KILL cr, KILL oldval);
7845 format %{ "CMPXCHG [$mem_ptr],$newval\t# If EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t"
7846 "MOV $res,0\n\t"
7847 "JNE,s fail\n\t"
7848 "MOV $res,1\n"
7849 "fail:" %}
7850 ins_encode( enc_cmpxchg(mem_ptr), enc_flags_ne_to_boolean(res) );
7851 ins_pipe( pipe_cmpxchg );
7852 %}
7853
7854 instruct xaddI_no_res( memory mem, Universe dummy, immI add, eFlagsReg cr) %{
7855 predicate(n->as_LoadStore()->result_not_used());
7856 match(Set dummy (GetAndAddI mem add));
7857 effect(KILL cr);
7858 format %{ "ADDL [$mem],$add" %}
7859 ins_encode %{
7860 if (os::is_MP()) { __ lock(); }
7861 __ addl($mem$$Address, $add$$constant);
7862 %}
7863 ins_pipe( pipe_cmpxchg );
7864 %}
7865
7866 instruct xaddI( memory mem, rRegI newval, eFlagsReg cr) %{
7867 match(Set newval (GetAndAddI mem newval));
7868 effect(KILL cr);
7869 format %{ "XADDL [$mem],$newval" %}
7870 ins_encode %{
7871 if (os::is_MP()) { __ lock(); }
7872 __ xaddl($mem$$Address, $newval$$Register);
7873 %}
7874 ins_pipe( pipe_cmpxchg );
7875 %}
7876
7877 instruct xchgI( memory mem, rRegI newval) %{
7878 match(Set newval (GetAndSetI mem newval));
7879 format %{ "XCHGL $newval,[$mem]" %}
7880 ins_encode %{
7881 __ xchgl($newval$$Register, $mem$$Address);
7882 %}
7883 ins_pipe( pipe_cmpxchg );
7884 %}
7885
7886 instruct xchgP( memory mem, pRegP newval) %{
7887 match(Set newval (GetAndSetP mem newval));
7888 format %{ "XCHGL $newval,[$mem]" %}
7889 ins_encode %{
7890 __ xchgl($newval$$Register, $mem$$Address);
7891 %}
7892 ins_pipe( pipe_cmpxchg );
7893 %}
7894
7895 instruct compareAndSwapI( rRegI res, pRegP mem_ptr, eAXRegI oldval, eCXRegI newval, eFlagsReg cr) %{
7896 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval)));
7897 effect(KILL cr, KILL oldval);
7898 format %{ "CMPXCHG [$mem_ptr],$newval\t# If EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t"
7899 "MOV $res,0\n\t"
7900 "JNE,s fail\n\t"
7901 "MOV $res,1\n"
7902 "fail:" %}
7903 ins_encode( enc_cmpxchg(mem_ptr), enc_flags_ne_to_boolean(res) );
7904 ins_pipe( pipe_cmpxchg );
7905 %}
7906
7907 //----------Subtraction Instructions-------------------------------------------
7908 // Integer Subtraction Instructions
7909 instruct subI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
7910 match(Set dst (SubI dst src));
7911 effect(KILL cr);
7912
7913 size(2);
7914 format %{ "SUB $dst,$src" %}
7915 opcode(0x2B);
7916 ins_encode( OpcP, RegReg( dst, src) );
7917 ins_pipe( ialu_reg_reg );
7918 %}
7919
7920 instruct subI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{
7921 match(Set dst (SubI dst src));
7922 effect(KILL cr);
7923
7924 format %{ "SUB $dst,$src" %}
7925 opcode(0x81,0x05); /* Opcode 81 /5 */
7926 // ins_encode( RegImm( dst, src) );
7927 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
7928 ins_pipe( ialu_reg );
7929 %}
7930
7931 instruct subI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{
7932 match(Set dst (SubI dst (LoadI src)));
7933 effect(KILL cr);
7934
7935 ins_cost(125);
7936 format %{ "SUB $dst,$src" %}
7937 opcode(0x2B);
7938 ins_encode( OpcP, RegMem( dst, src) );
7939 ins_pipe( ialu_reg_mem );
7940 %}
7941
7942 instruct subI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{
7943 match(Set dst (StoreI dst (SubI (LoadI dst) src)));
7944 effect(KILL cr);
7945
7946 ins_cost(150);
7947 format %{ "SUB $dst,$src" %}
7948 opcode(0x29); /* Opcode 29 /r */
7949 ins_encode( OpcP, RegMem( src, dst ) );
7950 ins_pipe( ialu_mem_reg );
7951 %}
7952
7953 // Subtract from a pointer
7954 instruct subP_eReg(eRegP dst, rRegI src, immI0 zero, eFlagsReg cr) %{
7955 match(Set dst (AddP dst (SubI zero src)));
7956 effect(KILL cr);
7957
7958 size(2);
7959 format %{ "SUB $dst,$src" %}
7960 opcode(0x2B);
7961 ins_encode( OpcP, RegReg( dst, src) );
7962 ins_pipe( ialu_reg_reg );
7963 %}
7964
7965 instruct negI_eReg(rRegI dst, immI0 zero, eFlagsReg cr) %{
7966 match(Set dst (SubI zero dst));
7967 effect(KILL cr);
7968
7969 size(2);
7970 format %{ "NEG $dst" %}
7971 opcode(0xF7,0x03); // Opcode F7 /3
7972 ins_encode( OpcP, RegOpc( dst ) );
7973 ins_pipe( ialu_reg );
7974 %}
7975
7976
7977 //----------Multiplication/Division Instructions-------------------------------
7978 // Integer Multiplication Instructions
7979 // Multiply Register
7980 instruct mulI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
7981 match(Set dst (MulI dst src));
7982 effect(KILL cr);
7983
7984 size(3);
7985 ins_cost(300);
7986 format %{ "IMUL $dst,$src" %}
7987 opcode(0xAF, 0x0F);
7988 ins_encode( OpcS, OpcP, RegReg( dst, src) );
7989 ins_pipe( ialu_reg_reg_alu0 );
7990 %}
7991
7992 // Multiply 32-bit Immediate
7993 instruct mulI_eReg_imm(rRegI dst, rRegI src, immI imm, eFlagsReg cr) %{
7994 match(Set dst (MulI src imm));
7995 effect(KILL cr);
7996
7997 ins_cost(300);
7998 format %{ "IMUL $dst,$src,$imm" %}
7999 opcode(0x69); /* 69 /r id */
8000 ins_encode( OpcSE(imm), RegReg( dst, src ), Con8or32( imm ) );
8001 ins_pipe( ialu_reg_reg_alu0 );
8002 %}
8003
8004 instruct loadConL_low_only(eADXRegL_low_only dst, immL32 src, eFlagsReg cr) %{
8005 match(Set dst src);
8006 effect(KILL cr);
8007
8008 // Note that this is artificially increased to make it more expensive than loadConL
8009 ins_cost(250);
8010 format %{ "MOV EAX,$src\t// low word only" %}
8011 opcode(0xB8);
8012 ins_encode( LdImmL_Lo(dst, src) );
8013 ins_pipe( ialu_reg_fat );
8014 %}
8015
8016 // Multiply by 32-bit Immediate, taking the shifted high order results
8017 // (special case for shift by 32)
8018 instruct mulI_imm_high(eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32 cnt, eFlagsReg cr) %{
8019 match(Set dst (ConvL2I (RShiftL (MulL (ConvI2L src1) src2) cnt)));
8020 predicate( _kids[0]->_kids[0]->_kids[1]->_leaf->Opcode() == Op_ConL &&
8021 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() >= min_jint &&
8022 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() <= max_jint );
8023 effect(USE src1, KILL cr);
8024
8025 // Note that this is adjusted by 150 to compensate for the overcosting of loadConL_low_only
8026 ins_cost(0*100 + 1*400 - 150);
8027 format %{ "IMUL EDX:EAX,$src1" %}
8028 ins_encode( multiply_con_and_shift_high( dst, src1, src2, cnt, cr ) );
8029 ins_pipe( pipe_slow );
8030 %}
8031
8032 // Multiply by 32-bit Immediate, taking the shifted high order results
8033 instruct mulI_imm_RShift_high(eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32_63 cnt, eFlagsReg cr) %{
8034 match(Set dst (ConvL2I (RShiftL (MulL (ConvI2L src1) src2) cnt)));
8035 predicate( _kids[0]->_kids[0]->_kids[1]->_leaf->Opcode() == Op_ConL &&
8036 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() >= min_jint &&
8037 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() <= max_jint );
8038 effect(USE src1, KILL cr);
8039
8040 // Note that this is adjusted by 150 to compensate for the overcosting of loadConL_low_only
8041 ins_cost(1*100 + 1*400 - 150);
8042 format %{ "IMUL EDX:EAX,$src1\n\t"
8043 "SAR EDX,$cnt-32" %}
8044 ins_encode( multiply_con_and_shift_high( dst, src1, src2, cnt, cr ) );
8045 ins_pipe( pipe_slow );
8046 %}
8047
8048 // Multiply Memory 32-bit Immediate
8049 instruct mulI_mem_imm(rRegI dst, memory src, immI imm, eFlagsReg cr) %{
8050 match(Set dst (MulI (LoadI src) imm));
8051 effect(KILL cr);
8052
8053 ins_cost(300);
8054 format %{ "IMUL $dst,$src,$imm" %}
8055 opcode(0x69); /* 69 /r id */
8056 ins_encode( OpcSE(imm), RegMem( dst, src ), Con8or32( imm ) );
8057 ins_pipe( ialu_reg_mem_alu0 );
8058 %}
8059
8060 // Multiply Memory
8061 instruct mulI(rRegI dst, memory src, eFlagsReg cr) %{
8062 match(Set dst (MulI dst (LoadI src)));
8063 effect(KILL cr);
8064
8065 ins_cost(350);
8066 format %{ "IMUL $dst,$src" %}
8067 opcode(0xAF, 0x0F);
8068 ins_encode( OpcS, OpcP, RegMem( dst, src) );
8069 ins_pipe( ialu_reg_mem_alu0 );
8070 %}
8071
8072 // Multiply Register Int to Long
8073 instruct mulI2L(eADXRegL dst, eAXRegI src, nadxRegI src1, eFlagsReg flags) %{
8074 // Basic Idea: long = (long)int * (long)int
8075 match(Set dst (MulL (ConvI2L src) (ConvI2L src1)));
8076 effect(DEF dst, USE src, USE src1, KILL flags);
8077
8078 ins_cost(300);
8079 format %{ "IMUL $dst,$src1" %}
8080
8081 ins_encode( long_int_multiply( dst, src1 ) );
8082 ins_pipe( ialu_reg_reg_alu0 );
8083 %}
8084
8085 instruct mulIS_eReg(eADXRegL dst, immL_32bits mask, eFlagsReg flags, eAXRegI src, nadxRegI src1) %{
8086 // Basic Idea: long = (int & 0xffffffffL) * (int & 0xffffffffL)
8087 match(Set dst (MulL (AndL (ConvI2L src) mask) (AndL (ConvI2L src1) mask)));
8088 effect(KILL flags);
8089
8090 ins_cost(300);
8091 format %{ "MUL $dst,$src1" %}
8092
8093 ins_encode( long_uint_multiply(dst, src1) );
8094 ins_pipe( ialu_reg_reg_alu0 );
8095 %}
8096
8097 // Multiply Register Long
8098 instruct mulL_eReg(eADXRegL dst, eRegL src, rRegI tmp, eFlagsReg cr) %{
8099 match(Set dst (MulL dst src));
8100 effect(KILL cr, TEMP tmp);
8101 ins_cost(4*100+3*400);
8102 // Basic idea: lo(result) = lo(x_lo * y_lo)
8103 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi)
8104 format %{ "MOV $tmp,$src.lo\n\t"
8105 "IMUL $tmp,EDX\n\t"
8106 "MOV EDX,$src.hi\n\t"
8107 "IMUL EDX,EAX\n\t"
8108 "ADD $tmp,EDX\n\t"
8109 "MUL EDX:EAX,$src.lo\n\t"
8110 "ADD EDX,$tmp" %}
8111 ins_encode( long_multiply( dst, src, tmp ) );
8112 ins_pipe( pipe_slow );
8113 %}
8114
8115 // Multiply Register Long where the left operand's high 32 bits are zero
8116 instruct mulL_eReg_lhi0(eADXRegL dst, eRegL src, rRegI tmp, eFlagsReg cr) %{
8117 predicate(is_operand_hi32_zero(n->in(1)));
8118 match(Set dst (MulL dst src));
8119 effect(KILL cr, TEMP tmp);
8120 ins_cost(2*100+2*400);
8121 // Basic idea: lo(result) = lo(x_lo * y_lo)
8122 // hi(result) = hi(x_lo * y_lo) + lo(x_lo * y_hi) where lo(x_hi * y_lo) = 0 because x_hi = 0
8123 format %{ "MOV $tmp,$src.hi\n\t"
8124 "IMUL $tmp,EAX\n\t"
8125 "MUL EDX:EAX,$src.lo\n\t"
8126 "ADD EDX,$tmp" %}
8127 ins_encode %{
8128 __ movl($tmp$$Register, HIGH_FROM_LOW($src$$Register));
8129 __ imull($tmp$$Register, rax);
8130 __ mull($src$$Register);
8131 __ addl(rdx, $tmp$$Register);
8132 %}
8133 ins_pipe( pipe_slow );
8134 %}
8135
8136 // Multiply Register Long where the right operand's high 32 bits are zero
8137 instruct mulL_eReg_rhi0(eADXRegL dst, eRegL src, rRegI tmp, eFlagsReg cr) %{
8138 predicate(is_operand_hi32_zero(n->in(2)));
8139 match(Set dst (MulL dst src));
8140 effect(KILL cr, TEMP tmp);
8141 ins_cost(2*100+2*400);
8142 // Basic idea: lo(result) = lo(x_lo * y_lo)
8143 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) where lo(x_lo * y_hi) = 0 because y_hi = 0
8144 format %{ "MOV $tmp,$src.lo\n\t"
8145 "IMUL $tmp,EDX\n\t"
8146 "MUL EDX:EAX,$src.lo\n\t"
8147 "ADD EDX,$tmp" %}
8148 ins_encode %{
8149 __ movl($tmp$$Register, $src$$Register);
8150 __ imull($tmp$$Register, rdx);
8151 __ mull($src$$Register);
8152 __ addl(rdx, $tmp$$Register);
8153 %}
8154 ins_pipe( pipe_slow );
8155 %}
8156
8157 // Multiply Register Long where the left and the right operands' high 32 bits are zero
8158 instruct mulL_eReg_hi0(eADXRegL dst, eRegL src, eFlagsReg cr) %{
8159 predicate(is_operand_hi32_zero(n->in(1)) && is_operand_hi32_zero(n->in(2)));
8160 match(Set dst (MulL dst src));
8161 effect(KILL cr);
8162 ins_cost(1*400);
8163 // Basic idea: lo(result) = lo(x_lo * y_lo)
8164 // hi(result) = hi(x_lo * y_lo) where lo(x_hi * y_lo) = 0 and lo(x_lo * y_hi) = 0 because x_hi = 0 and y_hi = 0
8165 format %{ "MUL EDX:EAX,$src.lo\n\t" %}
8166 ins_encode %{
8167 __ mull($src$$Register);
8168 %}
8169 ins_pipe( pipe_slow );
8170 %}
8171
8172 // Multiply Register Long by small constant
8173 instruct mulL_eReg_con(eADXRegL dst, immL_127 src, rRegI tmp, eFlagsReg cr) %{
8174 match(Set dst (MulL dst src));
8175 effect(KILL cr, TEMP tmp);
8176 ins_cost(2*100+2*400);
8177 size(12);
8178 // Basic idea: lo(result) = lo(src * EAX)
8179 // hi(result) = hi(src * EAX) + lo(src * EDX)
8180 format %{ "IMUL $tmp,EDX,$src\n\t"
8181 "MOV EDX,$src\n\t"
8182 "MUL EDX\t# EDX*EAX -> EDX:EAX\n\t"
8183 "ADD EDX,$tmp" %}
8184 ins_encode( long_multiply_con( dst, src, tmp ) );
8185 ins_pipe( pipe_slow );
8186 %}
8187
8188 // Integer DIV with Register
8189 instruct divI_eReg(eAXRegI rax, eDXRegI rdx, eCXRegI div, eFlagsReg cr) %{
8190 match(Set rax (DivI rax div));
8191 effect(KILL rdx, KILL cr);
8192 size(26);
8193 ins_cost(30*100+10*100);
8194 format %{ "CMP EAX,0x80000000\n\t"
8195 "JNE,s normal\n\t"
8196 "XOR EDX,EDX\n\t"
8197 "CMP ECX,-1\n\t"
8198 "JE,s done\n"
8199 "normal: CDQ\n\t"
8200 "IDIV $div\n\t"
8201 "done:" %}
8202 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8203 ins_encode( cdq_enc, OpcP, RegOpc(div) );
8204 ins_pipe( ialu_reg_reg_alu0 );
8205 %}
8206
8207 // Divide Register Long
8208 instruct divL_eReg( eADXRegL dst, eRegL src1, eRegL src2, eFlagsReg cr, eCXRegI cx, eBXRegI bx ) %{
8209 match(Set dst (DivL src1 src2));
8210 effect( KILL cr, KILL cx, KILL bx );
8211 ins_cost(10000);
8212 format %{ "PUSH $src1.hi\n\t"
8213 "PUSH $src1.lo\n\t"
8214 "PUSH $src2.hi\n\t"
8215 "PUSH $src2.lo\n\t"
8216 "CALL SharedRuntime::ldiv\n\t"
8217 "ADD ESP,16" %}
8218 ins_encode( long_div(src1,src2) );
8219 ins_pipe( pipe_slow );
8220 %}
8221
8222 // Integer DIVMOD with Register, both quotient and mod results
8223 instruct divModI_eReg_divmod(eAXRegI rax, eDXRegI rdx, eCXRegI div, eFlagsReg cr) %{
8224 match(DivModI rax div);
8225 effect(KILL cr);
8226 size(26);
8227 ins_cost(30*100+10*100);
8228 format %{ "CMP EAX,0x80000000\n\t"
8229 "JNE,s normal\n\t"
8230 "XOR EDX,EDX\n\t"
8231 "CMP ECX,-1\n\t"
8232 "JE,s done\n"
8233 "normal: CDQ\n\t"
8234 "IDIV $div\n\t"
8235 "done:" %}
8236 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8237 ins_encode( cdq_enc, OpcP, RegOpc(div) );
8238 ins_pipe( pipe_slow );
8239 %}
8240
8241 // Integer MOD with Register
8242 instruct modI_eReg(eDXRegI rdx, eAXRegI rax, eCXRegI div, eFlagsReg cr) %{
8243 match(Set rdx (ModI rax div));
8244 effect(KILL rax, KILL cr);
8245
8246 size(26);
8247 ins_cost(300);
8248 format %{ "CDQ\n\t"
8249 "IDIV $div" %}
8250 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8251 ins_encode( cdq_enc, OpcP, RegOpc(div) );
8252 ins_pipe( ialu_reg_reg_alu0 );
8253 %}
8254
8255 // Remainder Register Long
8256 instruct modL_eReg( eADXRegL dst, eRegL src1, eRegL src2, eFlagsReg cr, eCXRegI cx, eBXRegI bx ) %{
8257 match(Set dst (ModL src1 src2));
8258 effect( KILL cr, KILL cx, KILL bx );
8259 ins_cost(10000);
8260 format %{ "PUSH $src1.hi\n\t"
8261 "PUSH $src1.lo\n\t"
8262 "PUSH $src2.hi\n\t"
8263 "PUSH $src2.lo\n\t"
8264 "CALL SharedRuntime::lrem\n\t"
8265 "ADD ESP,16" %}
8266 ins_encode( long_mod(src1,src2) );
8267 ins_pipe( pipe_slow );
8268 %}
8269
8270 // Divide Register Long (no special case since divisor != -1)
8271 instruct divL_eReg_imm32( eADXRegL dst, immL32 imm, rRegI tmp, rRegI tmp2, eFlagsReg cr ) %{
8272 match(Set dst (DivL dst imm));
8273 effect( TEMP tmp, TEMP tmp2, KILL cr );
8274 ins_cost(1000);
8275 format %{ "MOV $tmp,abs($imm) # ldiv EDX:EAX,$imm\n\t"
8276 "XOR $tmp2,$tmp2\n\t"
8277 "CMP $tmp,EDX\n\t"
8278 "JA,s fast\n\t"
8279 "MOV $tmp2,EAX\n\t"
8280 "MOV EAX,EDX\n\t"
8281 "MOV EDX,0\n\t"
8282 "JLE,s pos\n\t"
8283 "LNEG EAX : $tmp2\n\t"
8284 "DIV $tmp # unsigned division\n\t"
8285 "XCHG EAX,$tmp2\n\t"
8286 "DIV $tmp\n\t"
8287 "LNEG $tmp2 : EAX\n\t"
8288 "JMP,s done\n"
8289 "pos:\n\t"
8290 "DIV $tmp\n\t"
8291 "XCHG EAX,$tmp2\n"
8292 "fast:\n\t"
8293 "DIV $tmp\n"
8294 "done:\n\t"
8295 "MOV EDX,$tmp2\n\t"
8296 "NEG EDX:EAX # if $imm < 0" %}
8297 ins_encode %{
8298 int con = (int)$imm$$constant;
8299 assert(con != 0 && con != -1 && con != min_jint, "wrong divisor");
8300 int pcon = (con > 0) ? con : -con;
8301 Label Lfast, Lpos, Ldone;
8302
8303 __ movl($tmp$$Register, pcon);
8304 __ xorl($tmp2$$Register,$tmp2$$Register);
8305 __ cmpl($tmp$$Register, HIGH_FROM_LOW($dst$$Register));
8306 __ jccb(Assembler::above, Lfast); // result fits into 32 bit
8307
8308 __ movl($tmp2$$Register, $dst$$Register); // save
8309 __ movl($dst$$Register, HIGH_FROM_LOW($dst$$Register));
8310 __ movl(HIGH_FROM_LOW($dst$$Register),0); // preserve flags
8311 __ jccb(Assembler::lessEqual, Lpos); // result is positive
8312
8313 // Negative dividend.
8314 // convert value to positive to use unsigned division
8315 __ lneg($dst$$Register, $tmp2$$Register);
8316 __ divl($tmp$$Register);
8317 __ xchgl($dst$$Register, $tmp2$$Register);
8318 __ divl($tmp$$Register);
8319 // revert result back to negative
8320 __ lneg($tmp2$$Register, $dst$$Register);
8321 __ jmpb(Ldone);
8322
8323 __ bind(Lpos);
8324 __ divl($tmp$$Register); // Use unsigned division
8325 __ xchgl($dst$$Register, $tmp2$$Register);
8326 // Fallthrow for final divide, tmp2 has 32 bit hi result
8327
8328 __ bind(Lfast);
8329 // fast path: src is positive
8330 __ divl($tmp$$Register); // Use unsigned division
8331
8332 __ bind(Ldone);
8333 __ movl(HIGH_FROM_LOW($dst$$Register),$tmp2$$Register);
8334 if (con < 0) {
8335 __ lneg(HIGH_FROM_LOW($dst$$Register), $dst$$Register);
8336 }
8337 %}
8338 ins_pipe( pipe_slow );
8339 %}
8340
8341 // Remainder Register Long (remainder fit into 32 bits)
8342 instruct modL_eReg_imm32( eADXRegL dst, immL32 imm, rRegI tmp, rRegI tmp2, eFlagsReg cr ) %{
8343 match(Set dst (ModL dst imm));
8344 effect( TEMP tmp, TEMP tmp2, KILL cr );
8345 ins_cost(1000);
8346 format %{ "MOV $tmp,abs($imm) # lrem EDX:EAX,$imm\n\t"
8347 "CMP $tmp,EDX\n\t"
8348 "JA,s fast\n\t"
8349 "MOV $tmp2,EAX\n\t"
8350 "MOV EAX,EDX\n\t"
8351 "MOV EDX,0\n\t"
8352 "JLE,s pos\n\t"
8353 "LNEG EAX : $tmp2\n\t"
8354 "DIV $tmp # unsigned division\n\t"
8355 "MOV EAX,$tmp2\n\t"
8356 "DIV $tmp\n\t"
8357 "NEG EDX\n\t"
8358 "JMP,s done\n"
8359 "pos:\n\t"
8360 "DIV $tmp\n\t"
8361 "MOV EAX,$tmp2\n"
8362 "fast:\n\t"
8363 "DIV $tmp\n"
8364 "done:\n\t"
8365 "MOV EAX,EDX\n\t"
8366 "SAR EDX,31\n\t" %}
8367 ins_encode %{
8368 int con = (int)$imm$$constant;
8369 assert(con != 0 && con != -1 && con != min_jint, "wrong divisor");
8370 int pcon = (con > 0) ? con : -con;
8371 Label Lfast, Lpos, Ldone;
8372
8373 __ movl($tmp$$Register, pcon);
8374 __ cmpl($tmp$$Register, HIGH_FROM_LOW($dst$$Register));
8375 __ jccb(Assembler::above, Lfast); // src is positive and result fits into 32 bit
8376
8377 __ movl($tmp2$$Register, $dst$$Register); // save
8378 __ movl($dst$$Register, HIGH_FROM_LOW($dst$$Register));
8379 __ movl(HIGH_FROM_LOW($dst$$Register),0); // preserve flags
8380 __ jccb(Assembler::lessEqual, Lpos); // result is positive
8381
8382 // Negative dividend.
8383 // convert value to positive to use unsigned division
8384 __ lneg($dst$$Register, $tmp2$$Register);
8385 __ divl($tmp$$Register);
8386 __ movl($dst$$Register, $tmp2$$Register);
8387 __ divl($tmp$$Register);
8388 // revert remainder back to negative
8389 __ negl(HIGH_FROM_LOW($dst$$Register));
8390 __ jmpb(Ldone);
8391
8392 __ bind(Lpos);
8393 __ divl($tmp$$Register);
8394 __ movl($dst$$Register, $tmp2$$Register);
8395
8396 __ bind(Lfast);
8397 // fast path: src is positive
8398 __ divl($tmp$$Register);
8399
8400 __ bind(Ldone);
8401 __ movl($dst$$Register, HIGH_FROM_LOW($dst$$Register));
8402 __ sarl(HIGH_FROM_LOW($dst$$Register), 31); // result sign
8403
8404 %}
8405 ins_pipe( pipe_slow );
8406 %}
8407
8408 // Integer Shift Instructions
8409 // Shift Left by one
8410 instruct shlI_eReg_1(rRegI dst, immI1 shift, eFlagsReg cr) %{
8411 match(Set dst (LShiftI dst shift));
8412 effect(KILL cr);
8413
8414 size(2);
8415 format %{ "SHL $dst,$shift" %}
8416 opcode(0xD1, 0x4); /* D1 /4 */
8417 ins_encode( OpcP, RegOpc( dst ) );
8418 ins_pipe( ialu_reg );
8419 %}
8420
8421 // Shift Left by 8-bit immediate
8422 instruct salI_eReg_imm(rRegI dst, immI8 shift, eFlagsReg cr) %{
8423 match(Set dst (LShiftI dst shift));
8424 effect(KILL cr);
8425
8426 size(3);
8427 format %{ "SHL $dst,$shift" %}
8428 opcode(0xC1, 0x4); /* C1 /4 ib */
8429 ins_encode( RegOpcImm( dst, shift) );
8430 ins_pipe( ialu_reg );
8431 %}
8432
8433 // Shift Left by variable
8434 instruct salI_eReg_CL(rRegI dst, eCXRegI shift, eFlagsReg cr) %{
8435 match(Set dst (LShiftI dst shift));
8436 effect(KILL cr);
8437
8438 size(2);
8439 format %{ "SHL $dst,$shift" %}
8440 opcode(0xD3, 0x4); /* D3 /4 */
8441 ins_encode( OpcP, RegOpc( dst ) );
8442 ins_pipe( ialu_reg_reg );
8443 %}
8444
8445 // Arithmetic shift right by one
8446 instruct sarI_eReg_1(rRegI dst, immI1 shift, eFlagsReg cr) %{
8447 match(Set dst (RShiftI dst shift));
8448 effect(KILL cr);
8449
8450 size(2);
8451 format %{ "SAR $dst,$shift" %}
8452 opcode(0xD1, 0x7); /* D1 /7 */
8453 ins_encode( OpcP, RegOpc( dst ) );
8454 ins_pipe( ialu_reg );
8455 %}
8456
8457 // Arithmetic shift right by one
8458 instruct sarI_mem_1(memory dst, immI1 shift, eFlagsReg cr) %{
8459 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
8460 effect(KILL cr);
8461 format %{ "SAR $dst,$shift" %}
8462 opcode(0xD1, 0x7); /* D1 /7 */
8463 ins_encode( OpcP, RMopc_Mem(secondary,dst) );
8464 ins_pipe( ialu_mem_imm );
8465 %}
8466
8467 // Arithmetic Shift Right by 8-bit immediate
8468 instruct sarI_eReg_imm(rRegI dst, immI8 shift, eFlagsReg cr) %{
8469 match(Set dst (RShiftI dst shift));
8470 effect(KILL cr);
8471
8472 size(3);
8473 format %{ "SAR $dst,$shift" %}
8474 opcode(0xC1, 0x7); /* C1 /7 ib */
8475 ins_encode( RegOpcImm( dst, shift ) );
8476 ins_pipe( ialu_mem_imm );
8477 %}
8478
8479 // Arithmetic Shift Right by 8-bit immediate
8480 instruct sarI_mem_imm(memory dst, immI8 shift, eFlagsReg cr) %{
8481 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
8482 effect(KILL cr);
8483
8484 format %{ "SAR $dst,$shift" %}
8485 opcode(0xC1, 0x7); /* C1 /7 ib */
8486 ins_encode( OpcP, RMopc_Mem(secondary, dst ), Con8or32( shift ) );
8487 ins_pipe( ialu_mem_imm );
8488 %}
8489
8490 // Arithmetic Shift Right by variable
8491 instruct sarI_eReg_CL(rRegI dst, eCXRegI shift, eFlagsReg cr) %{
8492 match(Set dst (RShiftI dst shift));
8493 effect(KILL cr);
8494
8495 size(2);
8496 format %{ "SAR $dst,$shift" %}
8497 opcode(0xD3, 0x7); /* D3 /7 */
8498 ins_encode( OpcP, RegOpc( dst ) );
8499 ins_pipe( ialu_reg_reg );
8500 %}
8501
8502 // Logical shift right by one
8503 instruct shrI_eReg_1(rRegI dst, immI1 shift, eFlagsReg cr) %{
8504 match(Set dst (URShiftI dst shift));
8505 effect(KILL cr);
8506
8507 size(2);
8508 format %{ "SHR $dst,$shift" %}
8509 opcode(0xD1, 0x5); /* D1 /5 */
8510 ins_encode( OpcP, RegOpc( dst ) );
8511 ins_pipe( ialu_reg );
8512 %}
8513
8514 // Logical Shift Right by 8-bit immediate
8515 instruct shrI_eReg_imm(rRegI dst, immI8 shift, eFlagsReg cr) %{
8516 match(Set dst (URShiftI dst shift));
8517 effect(KILL cr);
8518
8519 size(3);
8520 format %{ "SHR $dst,$shift" %}
8521 opcode(0xC1, 0x5); /* C1 /5 ib */
8522 ins_encode( RegOpcImm( dst, shift) );
8523 ins_pipe( ialu_reg );
8524 %}
8525
8526
8527 // Logical Shift Right by 24, followed by Arithmetic Shift Left by 24.
8528 // This idiom is used by the compiler for the i2b bytecode.
8529 instruct i2b(rRegI dst, xRegI src, immI_24 twentyfour) %{
8530 match(Set dst (RShiftI (LShiftI src twentyfour) twentyfour));
8531
8532 size(3);
8533 format %{ "MOVSX $dst,$src :8" %}
8534 ins_encode %{
8535 __ movsbl($dst$$Register, $src$$Register);
8536 %}
8537 ins_pipe(ialu_reg_reg);
8538 %}
8539
8540 // Logical Shift Right by 16, followed by Arithmetic Shift Left by 16.
8541 // This idiom is used by the compiler the i2s bytecode.
8542 instruct i2s(rRegI dst, xRegI src, immI_16 sixteen) %{
8543 match(Set dst (RShiftI (LShiftI src sixteen) sixteen));
8544
8545 size(3);
8546 format %{ "MOVSX $dst,$src :16" %}
8547 ins_encode %{
8548 __ movswl($dst$$Register, $src$$Register);
8549 %}
8550 ins_pipe(ialu_reg_reg);
8551 %}
8552
8553
8554 // Logical Shift Right by variable
8555 instruct shrI_eReg_CL(rRegI dst, eCXRegI shift, eFlagsReg cr) %{
8556 match(Set dst (URShiftI dst shift));
8557 effect(KILL cr);
8558
8559 size(2);
8560 format %{ "SHR $dst,$shift" %}
8561 opcode(0xD3, 0x5); /* D3 /5 */
8562 ins_encode( OpcP, RegOpc( dst ) );
8563 ins_pipe( ialu_reg_reg );
8564 %}
8565
8566
8567 //----------Logical Instructions-----------------------------------------------
8568 //----------Integer Logical Instructions---------------------------------------
8569 // And Instructions
8570 // And Register with Register
8571 instruct andI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
8572 match(Set dst (AndI dst src));
8573 effect(KILL cr);
8574
8575 size(2);
8576 format %{ "AND $dst,$src" %}
8577 opcode(0x23);
8578 ins_encode( OpcP, RegReg( dst, src) );
8579 ins_pipe( ialu_reg_reg );
8580 %}
8581
8582 // And Register with Immediate
8583 instruct andI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{
8584 match(Set dst (AndI dst src));
8585 effect(KILL cr);
8586
8587 format %{ "AND $dst,$src" %}
8588 opcode(0x81,0x04); /* Opcode 81 /4 */
8589 // ins_encode( RegImm( dst, src) );
8590 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
8591 ins_pipe( ialu_reg );
8592 %}
8593
8594 // And Register with Memory
8595 instruct andI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{
8596 match(Set dst (AndI dst (LoadI src)));
8597 effect(KILL cr);
8598
8599 ins_cost(125);
8600 format %{ "AND $dst,$src" %}
8601 opcode(0x23);
8602 ins_encode( OpcP, RegMem( dst, src) );
8603 ins_pipe( ialu_reg_mem );
8604 %}
8605
8606 // And Memory with Register
8607 instruct andI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{
8608 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
8609 effect(KILL cr);
8610
8611 ins_cost(150);
8612 format %{ "AND $dst,$src" %}
8613 opcode(0x21); /* Opcode 21 /r */
8614 ins_encode( OpcP, RegMem( src, dst ) );
8615 ins_pipe( ialu_mem_reg );
8616 %}
8617
8618 // And Memory with Immediate
8619 instruct andI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
8620 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
8621 effect(KILL cr);
8622
8623 ins_cost(125);
8624 format %{ "AND $dst,$src" %}
8625 opcode(0x81, 0x4); /* Opcode 81 /4 id */
8626 // ins_encode( MemImm( dst, src) );
8627 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) );
8628 ins_pipe( ialu_mem_imm );
8629 %}
8630
8631 // Or Instructions
8632 // Or Register with Register
8633 instruct orI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
8634 match(Set dst (OrI dst src));
8635 effect(KILL cr);
8636
8637 size(2);
8638 format %{ "OR $dst,$src" %}
8639 opcode(0x0B);
8640 ins_encode( OpcP, RegReg( dst, src) );
8641 ins_pipe( ialu_reg_reg );
8642 %}
8643
8644 instruct orI_eReg_castP2X(rRegI dst, eRegP src, eFlagsReg cr) %{
8645 match(Set dst (OrI dst (CastP2X src)));
8646 effect(KILL cr);
8647
8648 size(2);
8649 format %{ "OR $dst,$src" %}
8650 opcode(0x0B);
8651 ins_encode( OpcP, RegReg( dst, src) );
8652 ins_pipe( ialu_reg_reg );
8653 %}
8654
8655
8656 // Or Register with Immediate
8657 instruct orI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{
8658 match(Set dst (OrI dst src));
8659 effect(KILL cr);
8660
8661 format %{ "OR $dst,$src" %}
8662 opcode(0x81,0x01); /* Opcode 81 /1 id */
8663 // ins_encode( RegImm( dst, src) );
8664 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
8665 ins_pipe( ialu_reg );
8666 %}
8667
8668 // Or Register with Memory
8669 instruct orI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{
8670 match(Set dst (OrI dst (LoadI src)));
8671 effect(KILL cr);
8672
8673 ins_cost(125);
8674 format %{ "OR $dst,$src" %}
8675 opcode(0x0B);
8676 ins_encode( OpcP, RegMem( dst, src) );
8677 ins_pipe( ialu_reg_mem );
8678 %}
8679
8680 // Or Memory with Register
8681 instruct orI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{
8682 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
8683 effect(KILL cr);
8684
8685 ins_cost(150);
8686 format %{ "OR $dst,$src" %}
8687 opcode(0x09); /* Opcode 09 /r */
8688 ins_encode( OpcP, RegMem( src, dst ) );
8689 ins_pipe( ialu_mem_reg );
8690 %}
8691
8692 // Or Memory with Immediate
8693 instruct orI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
8694 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
8695 effect(KILL cr);
8696
8697 ins_cost(125);
8698 format %{ "OR $dst,$src" %}
8699 opcode(0x81,0x1); /* Opcode 81 /1 id */
8700 // ins_encode( MemImm( dst, src) );
8701 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) );
8702 ins_pipe( ialu_mem_imm );
8703 %}
8704
8705 // ROL/ROR
8706 // ROL expand
8707 instruct rolI_eReg_imm1(rRegI dst, immI1 shift, eFlagsReg cr) %{
8708 effect(USE_DEF dst, USE shift, KILL cr);
8709
8710 format %{ "ROL $dst, $shift" %}
8711 opcode(0xD1, 0x0); /* Opcode D1 /0 */
8712 ins_encode( OpcP, RegOpc( dst ));
8713 ins_pipe( ialu_reg );
8714 %}
8715
8716 instruct rolI_eReg_imm8(rRegI dst, immI8 shift, eFlagsReg cr) %{
8717 effect(USE_DEF dst, USE shift, KILL cr);
8718
8719 format %{ "ROL $dst, $shift" %}
8720 opcode(0xC1, 0x0); /*Opcode /C1 /0 */
8721 ins_encode( RegOpcImm(dst, shift) );
8722 ins_pipe(ialu_reg);
8723 %}
8724
8725 instruct rolI_eReg_CL(ncxRegI dst, eCXRegI shift, eFlagsReg cr) %{
8726 effect(USE_DEF dst, USE shift, KILL cr);
8727
8728 format %{ "ROL $dst, $shift" %}
8729 opcode(0xD3, 0x0); /* Opcode D3 /0 */
8730 ins_encode(OpcP, RegOpc(dst));
8731 ins_pipe( ialu_reg_reg );
8732 %}
8733 // end of ROL expand
8734
8735 // ROL 32bit by one once
8736 instruct rolI_eReg_i1(rRegI dst, immI1 lshift, immI_M1 rshift, eFlagsReg cr) %{
8737 match(Set dst ( OrI (LShiftI dst lshift) (URShiftI dst rshift)));
8738
8739 expand %{
8740 rolI_eReg_imm1(dst, lshift, cr);
8741 %}
8742 %}
8743
8744 // ROL 32bit var by imm8 once
8745 instruct rolI_eReg_i8(rRegI dst, immI8 lshift, immI8 rshift, eFlagsReg cr) %{
8746 predicate( 0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
8747 match(Set dst ( OrI (LShiftI dst lshift) (URShiftI dst rshift)));
8748
8749 expand %{
8750 rolI_eReg_imm8(dst, lshift, cr);
8751 %}
8752 %}
8753
8754 // ROL 32bit var by var once
8755 instruct rolI_eReg_Var_C0(ncxRegI dst, eCXRegI shift, immI0 zero, eFlagsReg cr) %{
8756 match(Set dst ( OrI (LShiftI dst shift) (URShiftI dst (SubI zero shift))));
8757
8758 expand %{
8759 rolI_eReg_CL(dst, shift, cr);
8760 %}
8761 %}
8762
8763 // ROL 32bit var by var once
8764 instruct rolI_eReg_Var_C32(ncxRegI dst, eCXRegI shift, immI_32 c32, eFlagsReg cr) %{
8765 match(Set dst ( OrI (LShiftI dst shift) (URShiftI dst (SubI c32 shift))));
8766
8767 expand %{
8768 rolI_eReg_CL(dst, shift, cr);
8769 %}
8770 %}
8771
8772 // ROR expand
8773 instruct rorI_eReg_imm1(rRegI dst, immI1 shift, eFlagsReg cr) %{
8774 effect(USE_DEF dst, USE shift, KILL cr);
8775
8776 format %{ "ROR $dst, $shift" %}
8777 opcode(0xD1,0x1); /* Opcode D1 /1 */
8778 ins_encode( OpcP, RegOpc( dst ) );
8779 ins_pipe( ialu_reg );
8780 %}
8781
8782 instruct rorI_eReg_imm8(rRegI dst, immI8 shift, eFlagsReg cr) %{
8783 effect (USE_DEF dst, USE shift, KILL cr);
8784
8785 format %{ "ROR $dst, $shift" %}
8786 opcode(0xC1, 0x1); /* Opcode /C1 /1 ib */
8787 ins_encode( RegOpcImm(dst, shift) );
8788 ins_pipe( ialu_reg );
8789 %}
8790
8791 instruct rorI_eReg_CL(ncxRegI dst, eCXRegI shift, eFlagsReg cr)%{
8792 effect(USE_DEF dst, USE shift, KILL cr);
8793
8794 format %{ "ROR $dst, $shift" %}
8795 opcode(0xD3, 0x1); /* Opcode D3 /1 */
8796 ins_encode(OpcP, RegOpc(dst));
8797 ins_pipe( ialu_reg_reg );
8798 %}
8799 // end of ROR expand
8800
8801 // ROR right once
8802 instruct rorI_eReg_i1(rRegI dst, immI1 rshift, immI_M1 lshift, eFlagsReg cr) %{
8803 match(Set dst ( OrI (URShiftI dst rshift) (LShiftI dst lshift)));
8804
8805 expand %{
8806 rorI_eReg_imm1(dst, rshift, cr);
8807 %}
8808 %}
8809
8810 // ROR 32bit by immI8 once
8811 instruct rorI_eReg_i8(rRegI dst, immI8 rshift, immI8 lshift, eFlagsReg cr) %{
8812 predicate( 0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
8813 match(Set dst ( OrI (URShiftI dst rshift) (LShiftI dst lshift)));
8814
8815 expand %{
8816 rorI_eReg_imm8(dst, rshift, cr);
8817 %}
8818 %}
8819
8820 // ROR 32bit var by var once
8821 instruct rorI_eReg_Var_C0(ncxRegI dst, eCXRegI shift, immI0 zero, eFlagsReg cr) %{
8822 match(Set dst ( OrI (URShiftI dst shift) (LShiftI dst (SubI zero shift))));
8823
8824 expand %{
8825 rorI_eReg_CL(dst, shift, cr);
8826 %}
8827 %}
8828
8829 // ROR 32bit var by var once
8830 instruct rorI_eReg_Var_C32(ncxRegI dst, eCXRegI shift, immI_32 c32, eFlagsReg cr) %{
8831 match(Set dst ( OrI (URShiftI dst shift) (LShiftI dst (SubI c32 shift))));
8832
8833 expand %{
8834 rorI_eReg_CL(dst, shift, cr);
8835 %}
8836 %}
8837
8838 // Xor Instructions
8839 // Xor Register with Register
8840 instruct xorI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{
8841 match(Set dst (XorI dst src));
8842 effect(KILL cr);
8843
8844 size(2);
8845 format %{ "XOR $dst,$src" %}
8846 opcode(0x33);
8847 ins_encode( OpcP, RegReg( dst, src) );
8848 ins_pipe( ialu_reg_reg );
8849 %}
8850
8851 // Xor Register with Immediate -1
8852 instruct xorI_eReg_im1(rRegI dst, immI_M1 imm) %{
8853 match(Set dst (XorI dst imm));
8854
8855 size(2);
8856 format %{ "NOT $dst" %}
8857 ins_encode %{
8858 __ notl($dst$$Register);
8859 %}
8860 ins_pipe( ialu_reg );
8861 %}
8862
8863 // Xor Register with Immediate
8864 instruct xorI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{
8865 match(Set dst (XorI dst src));
8866 effect(KILL cr);
8867
8868 format %{ "XOR $dst,$src" %}
8869 opcode(0x81,0x06); /* Opcode 81 /6 id */
8870 // ins_encode( RegImm( dst, src) );
8871 ins_encode( OpcSErm( dst, src ), Con8or32( src ) );
8872 ins_pipe( ialu_reg );
8873 %}
8874
8875 // Xor Register with Memory
8876 instruct xorI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{
8877 match(Set dst (XorI dst (LoadI src)));
8878 effect(KILL cr);
8879
8880 ins_cost(125);
8881 format %{ "XOR $dst,$src" %}
8882 opcode(0x33);
8883 ins_encode( OpcP, RegMem(dst, src) );
8884 ins_pipe( ialu_reg_mem );
8885 %}
8886
8887 // Xor Memory with Register
8888 instruct xorI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{
8889 match(Set dst (StoreI dst (XorI (LoadI dst) src)));
8890 effect(KILL cr);
8891
8892 ins_cost(150);
8893 format %{ "XOR $dst,$src" %}
8894 opcode(0x31); /* Opcode 31 /r */
8895 ins_encode( OpcP, RegMem( src, dst ) );
8896 ins_pipe( ialu_mem_reg );
8897 %}
8898
8899 // Xor Memory with Immediate
8900 instruct xorI_mem_imm(memory dst, immI src, eFlagsReg cr) %{
8901 match(Set dst (StoreI dst (XorI (LoadI dst) src)));
8902 effect(KILL cr);
8903
8904 ins_cost(125);
8905 format %{ "XOR $dst,$src" %}
8906 opcode(0x81,0x6); /* Opcode 81 /6 id */
8907 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) );
8908 ins_pipe( ialu_mem_imm );
8909 %}
8910
8911 //----------Convert Int to Boolean---------------------------------------------
8912
8913 instruct movI_nocopy(rRegI dst, rRegI src) %{
8914 effect( DEF dst, USE src );
8915 format %{ "MOV $dst,$src" %}
8916 ins_encode( enc_Copy( dst, src) );
8917 ins_pipe( ialu_reg_reg );
8918 %}
8919
8920 instruct ci2b( rRegI dst, rRegI src, eFlagsReg cr ) %{
8921 effect( USE_DEF dst, USE src, KILL cr );
8922
8923 size(4);
8924 format %{ "NEG $dst\n\t"
8925 "ADC $dst,$src" %}
8926 ins_encode( neg_reg(dst),
8927 OpcRegReg(0x13,dst,src) );
8928 ins_pipe( ialu_reg_reg_long );
8929 %}
8930
8931 instruct convI2B( rRegI dst, rRegI src, eFlagsReg cr ) %{
8932 match(Set dst (Conv2B src));
8933
8934 expand %{
8935 movI_nocopy(dst,src);
8936 ci2b(dst,src,cr);
8937 %}
8938 %}
8939
8940 instruct movP_nocopy(rRegI dst, eRegP src) %{
8941 effect( DEF dst, USE src );
8942 format %{ "MOV $dst,$src" %}
8943 ins_encode( enc_Copy( dst, src) );
8944 ins_pipe( ialu_reg_reg );
8945 %}
8946
8947 instruct cp2b( rRegI dst, eRegP src, eFlagsReg cr ) %{
8948 effect( USE_DEF dst, USE src, KILL cr );
8949 format %{ "NEG $dst\n\t"
8950 "ADC $dst,$src" %}
8951 ins_encode( neg_reg(dst),
8952 OpcRegReg(0x13,dst,src) );
8953 ins_pipe( ialu_reg_reg_long );
8954 %}
8955
8956 instruct convP2B( rRegI dst, eRegP src, eFlagsReg cr ) %{
8957 match(Set dst (Conv2B src));
8958
8959 expand %{
8960 movP_nocopy(dst,src);
8961 cp2b(dst,src,cr);
8962 %}
8963 %}
8964
8965 instruct cmpLTMask(eCXRegI dst, ncxRegI p, ncxRegI q, eFlagsReg cr) %{
8966 match(Set dst (CmpLTMask p q));
8967 effect(KILL cr);
8968 ins_cost(400);
8969
8970 // SETlt can only use low byte of EAX,EBX, ECX, or EDX as destination
8971 format %{ "XOR $dst,$dst\n\t"
8972 "CMP $p,$q\n\t"
8973 "SETlt $dst\n\t"
8974 "NEG $dst" %}
8975 ins_encode %{
8976 Register Rp = $p$$Register;
8977 Register Rq = $q$$Register;
8978 Register Rd = $dst$$Register;
8979 Label done;
8980 __ xorl(Rd, Rd);
8981 __ cmpl(Rp, Rq);
8982 __ setb(Assembler::less, Rd);
8983 __ negl(Rd);
8984 %}
8985
8986 ins_pipe(pipe_slow);
8987 %}
8988
8989 instruct cmpLTMask0(rRegI dst, immI0 zero, eFlagsReg cr) %{
8990 match(Set dst (CmpLTMask dst zero));
8991 effect(DEF dst, KILL cr);
8992 ins_cost(100);
8993
8994 format %{ "SAR $dst,31\t# cmpLTMask0" %}
8995 ins_encode %{
8996 __ sarl($dst$$Register, 31);
8997 %}
8998 ins_pipe(ialu_reg);
8999 %}
9000
9001 /* better to save a register than avoid a branch */
9002 instruct cadd_cmpLTMask(rRegI p, rRegI q, rRegI y, eFlagsReg cr) %{
9003 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)));
9004 effect(KILL cr);
9005 ins_cost(400);
9006 format %{ "SUB $p,$q\t# cadd_cmpLTMask\n\t"
9007 "JGE done\n\t"
9008 "ADD $p,$y\n"
9009 "done: " %}
9010 ins_encode %{
9011 Register Rp = $p$$Register;
9012 Register Rq = $q$$Register;
9013 Register Ry = $y$$Register;
9014 Label done;
9015 __ subl(Rp, Rq);
9016 __ jccb(Assembler::greaterEqual, done);
9017 __ addl(Rp, Ry);
9018 __ bind(done);
9019 %}
9020
9021 ins_pipe(pipe_cmplt);
9022 %}
9023
9024 /* better to save a register than avoid a branch */
9025 instruct and_cmpLTMask(rRegI p, rRegI q, rRegI y, eFlagsReg cr) %{
9026 match(Set y (AndI (CmpLTMask p q) y));
9027 effect(KILL cr);
9028
9029 ins_cost(300);
9030
9031 format %{ "CMPL $p, $q\t# and_cmpLTMask\n\t"
9032 "JLT done\n\t"
9033 "XORL $y, $y\n"
9034 "done: " %}
9035 ins_encode %{
9036 Register Rp = $p$$Register;
9037 Register Rq = $q$$Register;
9038 Register Ry = $y$$Register;
9039 Label done;
9040 __ cmpl(Rp, Rq);
9041 __ jccb(Assembler::less, done);
9042 __ xorl(Ry, Ry);
9043 __ bind(done);
9044 %}
9045
9046 ins_pipe(pipe_cmplt);
9047 %}
9048
9049 /* If I enable this, I encourage spilling in the inner loop of compress.
9050 instruct cadd_cmpLTMask_mem(ncxRegI p, ncxRegI q, memory y, eCXRegI tmp, eFlagsReg cr) %{
9051 match(Set p (AddI (AndI (CmpLTMask p q) (LoadI y)) (SubI p q)));
9052 */
9053
9054 //----------Long Instructions------------------------------------------------
9055 // Add Long Register with Register
9056 instruct addL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9057 match(Set dst (AddL dst src));
9058 effect(KILL cr);
9059 ins_cost(200);
9060 format %{ "ADD $dst.lo,$src.lo\n\t"
9061 "ADC $dst.hi,$src.hi" %}
9062 opcode(0x03, 0x13);
9063 ins_encode( RegReg_Lo(dst, src), RegReg_Hi(dst,src) );
9064 ins_pipe( ialu_reg_reg_long );
9065 %}
9066
9067 // Add Long Register with Immediate
9068 instruct addL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9069 match(Set dst (AddL dst src));
9070 effect(KILL cr);
9071 format %{ "ADD $dst.lo,$src.lo\n\t"
9072 "ADC $dst.hi,$src.hi" %}
9073 opcode(0x81,0x00,0x02); /* Opcode 81 /0, 81 /2 */
9074 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9075 ins_pipe( ialu_reg_long );
9076 %}
9077
9078 // Add Long Register with Memory
9079 instruct addL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9080 match(Set dst (AddL dst (LoadL mem)));
9081 effect(KILL cr);
9082 ins_cost(125);
9083 format %{ "ADD $dst.lo,$mem\n\t"
9084 "ADC $dst.hi,$mem+4" %}
9085 opcode(0x03, 0x13);
9086 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9087 ins_pipe( ialu_reg_long_mem );
9088 %}
9089
9090 // Subtract Long Register with Register.
9091 instruct subL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9092 match(Set dst (SubL dst src));
9093 effect(KILL cr);
9094 ins_cost(200);
9095 format %{ "SUB $dst.lo,$src.lo\n\t"
9096 "SBB $dst.hi,$src.hi" %}
9097 opcode(0x2B, 0x1B);
9098 ins_encode( RegReg_Lo(dst, src), RegReg_Hi(dst,src) );
9099 ins_pipe( ialu_reg_reg_long );
9100 %}
9101
9102 // Subtract Long Register with Immediate
9103 instruct subL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9104 match(Set dst (SubL dst src));
9105 effect(KILL cr);
9106 format %{ "SUB $dst.lo,$src.lo\n\t"
9107 "SBB $dst.hi,$src.hi" %}
9108 opcode(0x81,0x05,0x03); /* Opcode 81 /5, 81 /3 */
9109 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9110 ins_pipe( ialu_reg_long );
9111 %}
9112
9113 // Subtract Long Register with Memory
9114 instruct subL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9115 match(Set dst (SubL dst (LoadL mem)));
9116 effect(KILL cr);
9117 ins_cost(125);
9118 format %{ "SUB $dst.lo,$mem\n\t"
9119 "SBB $dst.hi,$mem+4" %}
9120 opcode(0x2B, 0x1B);
9121 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9122 ins_pipe( ialu_reg_long_mem );
9123 %}
9124
9125 instruct negL_eReg(eRegL dst, immL0 zero, eFlagsReg cr) %{
9126 match(Set dst (SubL zero dst));
9127 effect(KILL cr);
9128 ins_cost(300);
9129 format %{ "NEG $dst.hi\n\tNEG $dst.lo\n\tSBB $dst.hi,0" %}
9130 ins_encode( neg_long(dst) );
9131 ins_pipe( ialu_reg_reg_long );
9132 %}
9133
9134 // And Long Register with Register
9135 instruct andL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9136 match(Set dst (AndL dst src));
9137 effect(KILL cr);
9138 format %{ "AND $dst.lo,$src.lo\n\t"
9139 "AND $dst.hi,$src.hi" %}
9140 opcode(0x23,0x23);
9141 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) );
9142 ins_pipe( ialu_reg_reg_long );
9143 %}
9144
9145 // And Long Register with Immediate
9146 instruct andL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9147 match(Set dst (AndL dst src));
9148 effect(KILL cr);
9149 format %{ "AND $dst.lo,$src.lo\n\t"
9150 "AND $dst.hi,$src.hi" %}
9151 opcode(0x81,0x04,0x04); /* Opcode 81 /4, 81 /4 */
9152 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9153 ins_pipe( ialu_reg_long );
9154 %}
9155
9156 // And Long Register with Memory
9157 instruct andL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9158 match(Set dst (AndL dst (LoadL mem)));
9159 effect(KILL cr);
9160 ins_cost(125);
9161 format %{ "AND $dst.lo,$mem\n\t"
9162 "AND $dst.hi,$mem+4" %}
9163 opcode(0x23, 0x23);
9164 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9165 ins_pipe( ialu_reg_long_mem );
9166 %}
9167
9168 // Or Long Register with Register
9169 instruct orl_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9170 match(Set dst (OrL dst src));
9171 effect(KILL cr);
9172 format %{ "OR $dst.lo,$src.lo\n\t"
9173 "OR $dst.hi,$src.hi" %}
9174 opcode(0x0B,0x0B);
9175 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) );
9176 ins_pipe( ialu_reg_reg_long );
9177 %}
9178
9179 // Or Long Register with Immediate
9180 instruct orl_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9181 match(Set dst (OrL dst src));
9182 effect(KILL cr);
9183 format %{ "OR $dst.lo,$src.lo\n\t"
9184 "OR $dst.hi,$src.hi" %}
9185 opcode(0x81,0x01,0x01); /* Opcode 81 /1, 81 /1 */
9186 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9187 ins_pipe( ialu_reg_long );
9188 %}
9189
9190 // Or Long Register with Memory
9191 instruct orl_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9192 match(Set dst (OrL dst (LoadL mem)));
9193 effect(KILL cr);
9194 ins_cost(125);
9195 format %{ "OR $dst.lo,$mem\n\t"
9196 "OR $dst.hi,$mem+4" %}
9197 opcode(0x0B,0x0B);
9198 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9199 ins_pipe( ialu_reg_long_mem );
9200 %}
9201
9202 // Xor Long Register with Register
9203 instruct xorl_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{
9204 match(Set dst (XorL dst src));
9205 effect(KILL cr);
9206 format %{ "XOR $dst.lo,$src.lo\n\t"
9207 "XOR $dst.hi,$src.hi" %}
9208 opcode(0x33,0x33);
9209 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) );
9210 ins_pipe( ialu_reg_reg_long );
9211 %}
9212
9213 // Xor Long Register with Immediate -1
9214 instruct xorl_eReg_im1(eRegL dst, immL_M1 imm) %{
9215 match(Set dst (XorL dst imm));
9216 format %{ "NOT $dst.lo\n\t"
9217 "NOT $dst.hi" %}
9218 ins_encode %{
9219 __ notl($dst$$Register);
9220 __ notl(HIGH_FROM_LOW($dst$$Register));
9221 %}
9222 ins_pipe( ialu_reg_long );
9223 %}
9224
9225 // Xor Long Register with Immediate
9226 instruct xorl_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{
9227 match(Set dst (XorL dst src));
9228 effect(KILL cr);
9229 format %{ "XOR $dst.lo,$src.lo\n\t"
9230 "XOR $dst.hi,$src.hi" %}
9231 opcode(0x81,0x06,0x06); /* Opcode 81 /6, 81 /6 */
9232 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) );
9233 ins_pipe( ialu_reg_long );
9234 %}
9235
9236 // Xor Long Register with Memory
9237 instruct xorl_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{
9238 match(Set dst (XorL dst (LoadL mem)));
9239 effect(KILL cr);
9240 ins_cost(125);
9241 format %{ "XOR $dst.lo,$mem\n\t"
9242 "XOR $dst.hi,$mem+4" %}
9243 opcode(0x33,0x33);
9244 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) );
9245 ins_pipe( ialu_reg_long_mem );
9246 %}
9247
9248 // Shift Left Long by 1
9249 instruct shlL_eReg_1(eRegL dst, immI_1 cnt, eFlagsReg cr) %{
9250 predicate(UseNewLongLShift);
9251 match(Set dst (LShiftL dst cnt));
9252 effect(KILL cr);
9253 ins_cost(100);
9254 format %{ "ADD $dst.lo,$dst.lo\n\t"
9255 "ADC $dst.hi,$dst.hi" %}
9256 ins_encode %{
9257 __ addl($dst$$Register,$dst$$Register);
9258 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9259 %}
9260 ins_pipe( ialu_reg_long );
9261 %}
9262
9263 // Shift Left Long by 2
9264 instruct shlL_eReg_2(eRegL dst, immI_2 cnt, eFlagsReg cr) %{
9265 predicate(UseNewLongLShift);
9266 match(Set dst (LShiftL dst cnt));
9267 effect(KILL cr);
9268 ins_cost(100);
9269 format %{ "ADD $dst.lo,$dst.lo\n\t"
9270 "ADC $dst.hi,$dst.hi\n\t"
9271 "ADD $dst.lo,$dst.lo\n\t"
9272 "ADC $dst.hi,$dst.hi" %}
9273 ins_encode %{
9274 __ addl($dst$$Register,$dst$$Register);
9275 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9276 __ addl($dst$$Register,$dst$$Register);
9277 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9278 %}
9279 ins_pipe( ialu_reg_long );
9280 %}
9281
9282 // Shift Left Long by 3
9283 instruct shlL_eReg_3(eRegL dst, immI_3 cnt, eFlagsReg cr) %{
9284 predicate(UseNewLongLShift);
9285 match(Set dst (LShiftL dst cnt));
9286 effect(KILL cr);
9287 ins_cost(100);
9288 format %{ "ADD $dst.lo,$dst.lo\n\t"
9289 "ADC $dst.hi,$dst.hi\n\t"
9290 "ADD $dst.lo,$dst.lo\n\t"
9291 "ADC $dst.hi,$dst.hi\n\t"
9292 "ADD $dst.lo,$dst.lo\n\t"
9293 "ADC $dst.hi,$dst.hi" %}
9294 ins_encode %{
9295 __ addl($dst$$Register,$dst$$Register);
9296 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9297 __ addl($dst$$Register,$dst$$Register);
9298 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9299 __ addl($dst$$Register,$dst$$Register);
9300 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register));
9301 %}
9302 ins_pipe( ialu_reg_long );
9303 %}
9304
9305 // Shift Left Long by 1-31
9306 instruct shlL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{
9307 match(Set dst (LShiftL dst cnt));
9308 effect(KILL cr);
9309 ins_cost(200);
9310 format %{ "SHLD $dst.hi,$dst.lo,$cnt\n\t"
9311 "SHL $dst.lo,$cnt" %}
9312 opcode(0xC1, 0x4, 0xA4); /* 0F/A4, then C1 /4 ib */
9313 ins_encode( move_long_small_shift(dst,cnt) );
9314 ins_pipe( ialu_reg_long );
9315 %}
9316
9317 // Shift Left Long by 32-63
9318 instruct shlL_eReg_32_63(eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{
9319 match(Set dst (LShiftL dst cnt));
9320 effect(KILL cr);
9321 ins_cost(300);
9322 format %{ "MOV $dst.hi,$dst.lo\n"
9323 "\tSHL $dst.hi,$cnt-32\n"
9324 "\tXOR $dst.lo,$dst.lo" %}
9325 opcode(0xC1, 0x4); /* C1 /4 ib */
9326 ins_encode( move_long_big_shift_clr(dst,cnt) );
9327 ins_pipe( ialu_reg_long );
9328 %}
9329
9330 // Shift Left Long by variable
9331 instruct salL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{
9332 match(Set dst (LShiftL dst shift));
9333 effect(KILL cr);
9334 ins_cost(500+200);
9335 size(17);
9336 format %{ "TEST $shift,32\n\t"
9337 "JEQ,s small\n\t"
9338 "MOV $dst.hi,$dst.lo\n\t"
9339 "XOR $dst.lo,$dst.lo\n"
9340 "small:\tSHLD $dst.hi,$dst.lo,$shift\n\t"
9341 "SHL $dst.lo,$shift" %}
9342 ins_encode( shift_left_long( dst, shift ) );
9343 ins_pipe( pipe_slow );
9344 %}
9345
9346 // Shift Right Long by 1-31
9347 instruct shrL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{
9348 match(Set dst (URShiftL dst cnt));
9349 effect(KILL cr);
9350 ins_cost(200);
9351 format %{ "SHRD $dst.lo,$dst.hi,$cnt\n\t"
9352 "SHR $dst.hi,$cnt" %}
9353 opcode(0xC1, 0x5, 0xAC); /* 0F/AC, then C1 /5 ib */
9354 ins_encode( move_long_small_shift(dst,cnt) );
9355 ins_pipe( ialu_reg_long );
9356 %}
9357
9358 // Shift Right Long by 32-63
9359 instruct shrL_eReg_32_63(eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{
9360 match(Set dst (URShiftL dst cnt));
9361 effect(KILL cr);
9362 ins_cost(300);
9363 format %{ "MOV $dst.lo,$dst.hi\n"
9364 "\tSHR $dst.lo,$cnt-32\n"
9365 "\tXOR $dst.hi,$dst.hi" %}
9366 opcode(0xC1, 0x5); /* C1 /5 ib */
9367 ins_encode( move_long_big_shift_clr(dst,cnt) );
9368 ins_pipe( ialu_reg_long );
9369 %}
9370
9371 // Shift Right Long by variable
9372 instruct shrL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{
9373 match(Set dst (URShiftL dst shift));
9374 effect(KILL cr);
9375 ins_cost(600);
9376 size(17);
9377 format %{ "TEST $shift,32\n\t"
9378 "JEQ,s small\n\t"
9379 "MOV $dst.lo,$dst.hi\n\t"
9380 "XOR $dst.hi,$dst.hi\n"
9381 "small:\tSHRD $dst.lo,$dst.hi,$shift\n\t"
9382 "SHR $dst.hi,$shift" %}
9383 ins_encode( shift_right_long( dst, shift ) );
9384 ins_pipe( pipe_slow );
9385 %}
9386
9387 // Shift Right Long by 1-31
9388 instruct sarL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{
9389 match(Set dst (RShiftL dst cnt));
9390 effect(KILL cr);
9391 ins_cost(200);
9392 format %{ "SHRD $dst.lo,$dst.hi,$cnt\n\t"
9393 "SAR $dst.hi,$cnt" %}
9394 opcode(0xC1, 0x7, 0xAC); /* 0F/AC, then C1 /7 ib */
9395 ins_encode( move_long_small_shift(dst,cnt) );
9396 ins_pipe( ialu_reg_long );
9397 %}
9398
9399 // Shift Right Long by 32-63
9400 instruct sarL_eReg_32_63( eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{
9401 match(Set dst (RShiftL dst cnt));
9402 effect(KILL cr);
9403 ins_cost(300);
9404 format %{ "MOV $dst.lo,$dst.hi\n"
9405 "\tSAR $dst.lo,$cnt-32\n"
9406 "\tSAR $dst.hi,31" %}
9407 opcode(0xC1, 0x7); /* C1 /7 ib */
9408 ins_encode( move_long_big_shift_sign(dst,cnt) );
9409 ins_pipe( ialu_reg_long );
9410 %}
9411
9412 // Shift Right arithmetic Long by variable
9413 instruct sarL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{
9414 match(Set dst (RShiftL dst shift));
9415 effect(KILL cr);
9416 ins_cost(600);
9417 size(18);
9418 format %{ "TEST $shift,32\n\t"
9419 "JEQ,s small\n\t"
9420 "MOV $dst.lo,$dst.hi\n\t"
9421 "SAR $dst.hi,31\n"
9422 "small:\tSHRD $dst.lo,$dst.hi,$shift\n\t"
9423 "SAR $dst.hi,$shift" %}
9424 ins_encode( shift_right_arith_long( dst, shift ) );
9425 ins_pipe( pipe_slow );
9426 %}
9427
9428
9429 //----------Double Instructions------------------------------------------------
9430 // Double Math
9431
9432 // Compare & branch
9433
9434 // P6 version of float compare, sets condition codes in EFLAGS
9435 instruct cmpDPR_cc_P6(eFlagsRegU cr, regDPR src1, regDPR src2, eAXRegI rax) %{
9436 predicate(VM_Version::supports_cmov() && UseSSE <=1);
9437 match(Set cr (CmpD src1 src2));
9438 effect(KILL rax);
9439 ins_cost(150);
9440 format %{ "FLD $src1\n\t"
9441 "FUCOMIP ST,$src2 // P6 instruction\n\t"
9442 "JNP exit\n\t"
9443 "MOV ah,1 // saw a NaN, set CF\n\t"
9444 "SAHF\n"
9445 "exit:\tNOP // avoid branch to branch" %}
9446 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
9447 ins_encode( Push_Reg_DPR(src1),
9448 OpcP, RegOpc(src2),
9449 cmpF_P6_fixup );
9450 ins_pipe( pipe_slow );
9451 %}
9452
9453 instruct cmpDPR_cc_P6CF(eFlagsRegUCF cr, regDPR src1, regDPR src2) %{
9454 predicate(VM_Version::supports_cmov() && UseSSE <=1);
9455 match(Set cr (CmpD src1 src2));
9456 ins_cost(150);
9457 format %{ "FLD $src1\n\t"
9458 "FUCOMIP ST,$src2 // P6 instruction" %}
9459 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
9460 ins_encode( Push_Reg_DPR(src1),
9461 OpcP, RegOpc(src2));
9462 ins_pipe( pipe_slow );
9463 %}
9464
9465 // Compare & branch
9466 instruct cmpDPR_cc(eFlagsRegU cr, regDPR src1, regDPR src2, eAXRegI rax) %{
9467 predicate(UseSSE<=1);
9468 match(Set cr (CmpD src1 src2));
9469 effect(KILL rax);
9470 ins_cost(200);
9471 format %{ "FLD $src1\n\t"
9472 "FCOMp $src2\n\t"
9473 "FNSTSW AX\n\t"
9474 "TEST AX,0x400\n\t"
9475 "JZ,s flags\n\t"
9476 "MOV AH,1\t# unordered treat as LT\n"
9477 "flags:\tSAHF" %}
9478 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
9479 ins_encode( Push_Reg_DPR(src1),
9480 OpcP, RegOpc(src2),
9481 fpu_flags);
9482 ins_pipe( pipe_slow );
9483 %}
9484
9485 // Compare vs zero into -1,0,1
9486 instruct cmpDPR_0(rRegI dst, regDPR src1, immDPR0 zero, eAXRegI rax, eFlagsReg cr) %{
9487 predicate(UseSSE<=1);
9488 match(Set dst (CmpD3 src1 zero));
9489 effect(KILL cr, KILL rax);
9490 ins_cost(280);
9491 format %{ "FTSTD $dst,$src1" %}
9492 opcode(0xE4, 0xD9);
9493 ins_encode( Push_Reg_DPR(src1),
9494 OpcS, OpcP, PopFPU,
9495 CmpF_Result(dst));
9496 ins_pipe( pipe_slow );
9497 %}
9498
9499 // Compare into -1,0,1
9500 instruct cmpDPR_reg(rRegI dst, regDPR src1, regDPR src2, eAXRegI rax, eFlagsReg cr) %{
9501 predicate(UseSSE<=1);
9502 match(Set dst (CmpD3 src1 src2));
9503 effect(KILL cr, KILL rax);
9504 ins_cost(300);
9505 format %{ "FCMPD $dst,$src1,$src2" %}
9506 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
9507 ins_encode( Push_Reg_DPR(src1),
9508 OpcP, RegOpc(src2),
9509 CmpF_Result(dst));
9510 ins_pipe( pipe_slow );
9511 %}
9512
9513 // float compare and set condition codes in EFLAGS by XMM regs
9514 instruct cmpD_cc(eFlagsRegU cr, regD src1, regD src2) %{
9515 predicate(UseSSE>=2);
9516 match(Set cr (CmpD src1 src2));
9517 ins_cost(145);
9518 format %{ "UCOMISD $src1,$src2\n\t"
9519 "JNP,s exit\n\t"
9520 "PUSHF\t# saw NaN, set CF\n\t"
9521 "AND [rsp], #0xffffff2b\n\t"
9522 "POPF\n"
9523 "exit:" %}
9524 ins_encode %{
9525 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
9526 emit_cmpfp_fixup(_masm);
9527 %}
9528 ins_pipe( pipe_slow );
9529 %}
9530
9531 instruct cmpD_ccCF(eFlagsRegUCF cr, regD src1, regD src2) %{
9532 predicate(UseSSE>=2);
9533 match(Set cr (CmpD src1 src2));
9534 ins_cost(100);
9535 format %{ "UCOMISD $src1,$src2" %}
9536 ins_encode %{
9537 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
9538 %}
9539 ins_pipe( pipe_slow );
9540 %}
9541
9542 // float compare and set condition codes in EFLAGS by XMM regs
9543 instruct cmpD_ccmem(eFlagsRegU cr, regD src1, memory src2) %{
9544 predicate(UseSSE>=2);
9545 match(Set cr (CmpD src1 (LoadD src2)));
9546 ins_cost(145);
9547 format %{ "UCOMISD $src1,$src2\n\t"
9548 "JNP,s exit\n\t"
9549 "PUSHF\t# saw NaN, set CF\n\t"
9550 "AND [rsp], #0xffffff2b\n\t"
9551 "POPF\n"
9552 "exit:" %}
9553 ins_encode %{
9554 __ ucomisd($src1$$XMMRegister, $src2$$Address);
9555 emit_cmpfp_fixup(_masm);
9556 %}
9557 ins_pipe( pipe_slow );
9558 %}
9559
9560 instruct cmpD_ccmemCF(eFlagsRegUCF cr, regD src1, memory src2) %{
9561 predicate(UseSSE>=2);
9562 match(Set cr (CmpD src1 (LoadD src2)));
9563 ins_cost(100);
9564 format %{ "UCOMISD $src1,$src2" %}
9565 ins_encode %{
9566 __ ucomisd($src1$$XMMRegister, $src2$$Address);
9567 %}
9568 ins_pipe( pipe_slow );
9569 %}
9570
9571 // Compare into -1,0,1 in XMM
9572 instruct cmpD_reg(xRegI dst, regD src1, regD src2, eFlagsReg cr) %{
9573 predicate(UseSSE>=2);
9574 match(Set dst (CmpD3 src1 src2));
9575 effect(KILL cr);
9576 ins_cost(255);
9577 format %{ "UCOMISD $src1, $src2\n\t"
9578 "MOV $dst, #-1\n\t"
9579 "JP,s done\n\t"
9580 "JB,s done\n\t"
9581 "SETNE $dst\n\t"
9582 "MOVZB $dst, $dst\n"
9583 "done:" %}
9584 ins_encode %{
9585 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
9586 emit_cmpfp3(_masm, $dst$$Register);
9587 %}
9588 ins_pipe( pipe_slow );
9589 %}
9590
9591 // Compare into -1,0,1 in XMM and memory
9592 instruct cmpD_regmem(xRegI dst, regD src1, memory src2, eFlagsReg cr) %{
9593 predicate(UseSSE>=2);
9594 match(Set dst (CmpD3 src1 (LoadD src2)));
9595 effect(KILL cr);
9596 ins_cost(275);
9597 format %{ "UCOMISD $src1, $src2\n\t"
9598 "MOV $dst, #-1\n\t"
9599 "JP,s done\n\t"
9600 "JB,s done\n\t"
9601 "SETNE $dst\n\t"
9602 "MOVZB $dst, $dst\n"
9603 "done:" %}
9604 ins_encode %{
9605 __ ucomisd($src1$$XMMRegister, $src2$$Address);
9606 emit_cmpfp3(_masm, $dst$$Register);
9607 %}
9608 ins_pipe( pipe_slow );
9609 %}
9610
9611
9612 instruct subDPR_reg(regDPR dst, regDPR src) %{
9613 predicate (UseSSE <=1);
9614 match(Set dst (SubD dst src));
9615
9616 format %{ "FLD $src\n\t"
9617 "DSUBp $dst,ST" %}
9618 opcode(0xDE, 0x5); /* DE E8+i or DE /5 */
9619 ins_cost(150);
9620 ins_encode( Push_Reg_DPR(src),
9621 OpcP, RegOpc(dst) );
9622 ins_pipe( fpu_reg_reg );
9623 %}
9624
9625 instruct subDPR_reg_round(stackSlotD dst, regDPR src1, regDPR src2) %{
9626 predicate (UseSSE <=1);
9627 match(Set dst (RoundDouble (SubD src1 src2)));
9628 ins_cost(250);
9629
9630 format %{ "FLD $src2\n\t"
9631 "DSUB ST,$src1\n\t"
9632 "FSTP_D $dst\t# D-round" %}
9633 opcode(0xD8, 0x5);
9634 ins_encode( Push_Reg_DPR(src2),
9635 OpcP, RegOpc(src1), Pop_Mem_DPR(dst) );
9636 ins_pipe( fpu_mem_reg_reg );
9637 %}
9638
9639
9640 instruct subDPR_reg_mem(regDPR dst, memory src) %{
9641 predicate (UseSSE <=1);
9642 match(Set dst (SubD dst (LoadD src)));
9643 ins_cost(150);
9644
9645 format %{ "FLD $src\n\t"
9646 "DSUBp $dst,ST" %}
9647 opcode(0xDE, 0x5, 0xDD); /* DE C0+i */ /* LoadD DD /0 */
9648 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
9649 OpcP, RegOpc(dst) );
9650 ins_pipe( fpu_reg_mem );
9651 %}
9652
9653 instruct absDPR_reg(regDPR1 dst, regDPR1 src) %{
9654 predicate (UseSSE<=1);
9655 match(Set dst (AbsD src));
9656 ins_cost(100);
9657 format %{ "FABS" %}
9658 opcode(0xE1, 0xD9);
9659 ins_encode( OpcS, OpcP );
9660 ins_pipe( fpu_reg_reg );
9661 %}
9662
9663 instruct negDPR_reg(regDPR1 dst, regDPR1 src) %{
9664 predicate(UseSSE<=1);
9665 match(Set dst (NegD src));
9666 ins_cost(100);
9667 format %{ "FCHS" %}
9668 opcode(0xE0, 0xD9);
9669 ins_encode( OpcS, OpcP );
9670 ins_pipe( fpu_reg_reg );
9671 %}
9672
9673 instruct addDPR_reg(regDPR dst, regDPR src) %{
9674 predicate(UseSSE<=1);
9675 match(Set dst (AddD dst src));
9676 format %{ "FLD $src\n\t"
9677 "DADD $dst,ST" %}
9678 size(4);
9679 ins_cost(150);
9680 opcode(0xDE, 0x0); /* DE C0+i or DE /0*/
9681 ins_encode( Push_Reg_DPR(src),
9682 OpcP, RegOpc(dst) );
9683 ins_pipe( fpu_reg_reg );
9684 %}
9685
9686
9687 instruct addDPR_reg_round(stackSlotD dst, regDPR src1, regDPR src2) %{
9688 predicate(UseSSE<=1);
9689 match(Set dst (RoundDouble (AddD src1 src2)));
9690 ins_cost(250);
9691
9692 format %{ "FLD $src2\n\t"
9693 "DADD ST,$src1\n\t"
9694 "FSTP_D $dst\t# D-round" %}
9695 opcode(0xD8, 0x0); /* D8 C0+i or D8 /0*/
9696 ins_encode( Push_Reg_DPR(src2),
9697 OpcP, RegOpc(src1), Pop_Mem_DPR(dst) );
9698 ins_pipe( fpu_mem_reg_reg );
9699 %}
9700
9701
9702 instruct addDPR_reg_mem(regDPR dst, memory src) %{
9703 predicate(UseSSE<=1);
9704 match(Set dst (AddD dst (LoadD src)));
9705 ins_cost(150);
9706
9707 format %{ "FLD $src\n\t"
9708 "DADDp $dst,ST" %}
9709 opcode(0xDE, 0x0, 0xDD); /* DE C0+i */ /* LoadD DD /0 */
9710 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
9711 OpcP, RegOpc(dst) );
9712 ins_pipe( fpu_reg_mem );
9713 %}
9714
9715 // add-to-memory
9716 instruct addDPR_mem_reg(memory dst, regDPR src) %{
9717 predicate(UseSSE<=1);
9718 match(Set dst (StoreD dst (RoundDouble (AddD (LoadD dst) src))));
9719 ins_cost(150);
9720
9721 format %{ "FLD_D $dst\n\t"
9722 "DADD ST,$src\n\t"
9723 "FST_D $dst" %}
9724 opcode(0xDD, 0x0);
9725 ins_encode( Opcode(0xDD), RMopc_Mem(0x00,dst),
9726 Opcode(0xD8), RegOpc(src),
9727 set_instruction_start,
9728 Opcode(0xDD), RMopc_Mem(0x03,dst) );
9729 ins_pipe( fpu_reg_mem );
9730 %}
9731
9732 instruct addDPR_reg_imm1(regDPR dst, immDPR1 con) %{
9733 predicate(UseSSE<=1);
9734 match(Set dst (AddD dst con));
9735 ins_cost(125);
9736 format %{ "FLD1\n\t"
9737 "DADDp $dst,ST" %}
9738 ins_encode %{
9739 __ fld1();
9740 __ faddp($dst$$reg);
9741 %}
9742 ins_pipe(fpu_reg);
9743 %}
9744
9745 instruct addDPR_reg_imm(regDPR dst, immDPR con) %{
9746 predicate(UseSSE<=1 && _kids[1]->_leaf->getd() != 0.0 && _kids[1]->_leaf->getd() != 1.0 );
9747 match(Set dst (AddD dst con));
9748 ins_cost(200);
9749 format %{ "FLD_D [$constantaddress]\t# load from constant table: double=$con\n\t"
9750 "DADDp $dst,ST" %}
9751 ins_encode %{
9752 __ fld_d($constantaddress($con));
9753 __ faddp($dst$$reg);
9754 %}
9755 ins_pipe(fpu_reg_mem);
9756 %}
9757
9758 instruct addDPR_reg_imm_round(stackSlotD dst, regDPR src, immDPR con) %{
9759 predicate(UseSSE<=1 && _kids[0]->_kids[1]->_leaf->getd() != 0.0 && _kids[0]->_kids[1]->_leaf->getd() != 1.0 );
9760 match(Set dst (RoundDouble (AddD src con)));
9761 ins_cost(200);
9762 format %{ "FLD_D [$constantaddress]\t# load from constant table: double=$con\n\t"
9763 "DADD ST,$src\n\t"
9764 "FSTP_D $dst\t# D-round" %}
9765 ins_encode %{
9766 __ fld_d($constantaddress($con));
9767 __ fadd($src$$reg);
9768 __ fstp_d(Address(rsp, $dst$$disp));
9769 %}
9770 ins_pipe(fpu_mem_reg_con);
9771 %}
9772
9773 instruct mulDPR_reg(regDPR dst, regDPR src) %{
9774 predicate(UseSSE<=1);
9775 match(Set dst (MulD dst src));
9776 format %{ "FLD $src\n\t"
9777 "DMULp $dst,ST" %}
9778 opcode(0xDE, 0x1); /* DE C8+i or DE /1*/
9779 ins_cost(150);
9780 ins_encode( Push_Reg_DPR(src),
9781 OpcP, RegOpc(dst) );
9782 ins_pipe( fpu_reg_reg );
9783 %}
9784
9785 // Strict FP instruction biases argument before multiply then
9786 // biases result to avoid double rounding of subnormals.
9787 //
9788 // scale arg1 by multiplying arg1 by 2^(-15360)
9789 // load arg2
9790 // multiply scaled arg1 by arg2
9791 // rescale product by 2^(15360)
9792 //
9793 instruct strictfp_mulDPR_reg(regDPR1 dst, regnotDPR1 src) %{
9794 predicate( UseSSE<=1 && Compile::current()->has_method() && Compile::current()->method()->is_strict() );
9795 match(Set dst (MulD dst src));
9796 ins_cost(1); // Select this instruction for all strict FP double multiplies
9797
9798 format %{ "FLD StubRoutines::_fpu_subnormal_bias1\n\t"
9799 "DMULp $dst,ST\n\t"
9800 "FLD $src\n\t"
9801 "DMULp $dst,ST\n\t"
9802 "FLD StubRoutines::_fpu_subnormal_bias2\n\t"
9803 "DMULp $dst,ST\n\t" %}
9804 opcode(0xDE, 0x1); /* DE C8+i or DE /1*/
9805 ins_encode( strictfp_bias1(dst),
9806 Push_Reg_DPR(src),
9807 OpcP, RegOpc(dst),
9808 strictfp_bias2(dst) );
9809 ins_pipe( fpu_reg_reg );
9810 %}
9811
9812 instruct mulDPR_reg_imm(regDPR dst, immDPR con) %{
9813 predicate( UseSSE<=1 && _kids[1]->_leaf->getd() != 0.0 && _kids[1]->_leaf->getd() != 1.0 );
9814 match(Set dst (MulD dst con));
9815 ins_cost(200);
9816 format %{ "FLD_D [$constantaddress]\t# load from constant table: double=$con\n\t"
9817 "DMULp $dst,ST" %}
9818 ins_encode %{
9819 __ fld_d($constantaddress($con));
9820 __ fmulp($dst$$reg);
9821 %}
9822 ins_pipe(fpu_reg_mem);
9823 %}
9824
9825
9826 instruct mulDPR_reg_mem(regDPR dst, memory src) %{
9827 predicate( UseSSE<=1 );
9828 match(Set dst (MulD dst (LoadD src)));
9829 ins_cost(200);
9830 format %{ "FLD_D $src\n\t"
9831 "DMULp $dst,ST" %}
9832 opcode(0xDE, 0x1, 0xDD); /* DE C8+i or DE /1*/ /* LoadD DD /0 */
9833 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
9834 OpcP, RegOpc(dst) );
9835 ins_pipe( fpu_reg_mem );
9836 %}
9837
9838 //
9839 // Cisc-alternate to reg-reg multiply
9840 instruct mulDPR_reg_mem_cisc(regDPR dst, regDPR src, memory mem) %{
9841 predicate( UseSSE<=1 );
9842 match(Set dst (MulD src (LoadD mem)));
9843 ins_cost(250);
9844 format %{ "FLD_D $mem\n\t"
9845 "DMUL ST,$src\n\t"
9846 "FSTP_D $dst" %}
9847 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i */ /* LoadD D9 /0 */
9848 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,mem),
9849 OpcReg_FPR(src),
9850 Pop_Reg_DPR(dst) );
9851 ins_pipe( fpu_reg_reg_mem );
9852 %}
9853
9854
9855 // MACRO3 -- addDPR a mulDPR
9856 // This instruction is a '2-address' instruction in that the result goes
9857 // back to src2. This eliminates a move from the macro; possibly the
9858 // register allocator will have to add it back (and maybe not).
9859 instruct addDPR_mulDPR_reg(regDPR src2, regDPR src1, regDPR src0) %{
9860 predicate( UseSSE<=1 );
9861 match(Set src2 (AddD (MulD src0 src1) src2));
9862 format %{ "FLD $src0\t# ===MACRO3d===\n\t"
9863 "DMUL ST,$src1\n\t"
9864 "DADDp $src2,ST" %}
9865 ins_cost(250);
9866 opcode(0xDD); /* LoadD DD /0 */
9867 ins_encode( Push_Reg_FPR(src0),
9868 FMul_ST_reg(src1),
9869 FAddP_reg_ST(src2) );
9870 ins_pipe( fpu_reg_reg_reg );
9871 %}
9872
9873
9874 // MACRO3 -- subDPR a mulDPR
9875 instruct subDPR_mulDPR_reg(regDPR src2, regDPR src1, regDPR src0) %{
9876 predicate( UseSSE<=1 );
9877 match(Set src2 (SubD (MulD src0 src1) src2));
9878 format %{ "FLD $src0\t# ===MACRO3d===\n\t"
9879 "DMUL ST,$src1\n\t"
9880 "DSUBRp $src2,ST" %}
9881 ins_cost(250);
9882 ins_encode( Push_Reg_FPR(src0),
9883 FMul_ST_reg(src1),
9884 Opcode(0xDE), Opc_plus(0xE0,src2));
9885 ins_pipe( fpu_reg_reg_reg );
9886 %}
9887
9888
9889 instruct divDPR_reg(regDPR dst, regDPR src) %{
9890 predicate( UseSSE<=1 );
9891 match(Set dst (DivD dst src));
9892
9893 format %{ "FLD $src\n\t"
9894 "FDIVp $dst,ST" %}
9895 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
9896 ins_cost(150);
9897 ins_encode( Push_Reg_DPR(src),
9898 OpcP, RegOpc(dst) );
9899 ins_pipe( fpu_reg_reg );
9900 %}
9901
9902 // Strict FP instruction biases argument before division then
9903 // biases result, to avoid double rounding of subnormals.
9904 //
9905 // scale dividend by multiplying dividend by 2^(-15360)
9906 // load divisor
9907 // divide scaled dividend by divisor
9908 // rescale quotient by 2^(15360)
9909 //
9910 instruct strictfp_divDPR_reg(regDPR1 dst, regnotDPR1 src) %{
9911 predicate (UseSSE<=1);
9912 match(Set dst (DivD dst src));
9913 predicate( UseSSE<=1 && Compile::current()->has_method() && Compile::current()->method()->is_strict() );
9914 ins_cost(01);
9915
9916 format %{ "FLD StubRoutines::_fpu_subnormal_bias1\n\t"
9917 "DMULp $dst,ST\n\t"
9918 "FLD $src\n\t"
9919 "FDIVp $dst,ST\n\t"
9920 "FLD StubRoutines::_fpu_subnormal_bias2\n\t"
9921 "DMULp $dst,ST\n\t" %}
9922 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
9923 ins_encode( strictfp_bias1(dst),
9924 Push_Reg_DPR(src),
9925 OpcP, RegOpc(dst),
9926 strictfp_bias2(dst) );
9927 ins_pipe( fpu_reg_reg );
9928 %}
9929
9930 instruct divDPR_reg_round(stackSlotD dst, regDPR src1, regDPR src2) %{
9931 predicate( UseSSE<=1 && !(Compile::current()->has_method() && Compile::current()->method()->is_strict()) );
9932 match(Set dst (RoundDouble (DivD src1 src2)));
9933
9934 format %{ "FLD $src1\n\t"
9935 "FDIV ST,$src2\n\t"
9936 "FSTP_D $dst\t# D-round" %}
9937 opcode(0xD8, 0x6); /* D8 F0+i or D8 /6 */
9938 ins_encode( Push_Reg_DPR(src1),
9939 OpcP, RegOpc(src2), Pop_Mem_DPR(dst) );
9940 ins_pipe( fpu_mem_reg_reg );
9941 %}
9942
9943
9944 instruct modDPR_reg(regDPR dst, regDPR src, eAXRegI rax, eFlagsReg cr) %{
9945 predicate(UseSSE<=1);
9946 match(Set dst (ModD dst src));
9947 effect(KILL rax, KILL cr); // emitModDPR() uses EAX and EFLAGS
9948
9949 format %{ "DMOD $dst,$src" %}
9950 ins_cost(250);
9951 ins_encode(Push_Reg_Mod_DPR(dst, src),
9952 emitModDPR(),
9953 Push_Result_Mod_DPR(src),
9954 Pop_Reg_DPR(dst));
9955 ins_pipe( pipe_slow );
9956 %}
9957
9958 instruct modD_reg(regD dst, regD src0, regD src1, eAXRegI rax, eFlagsReg cr) %{
9959 predicate(UseSSE>=2);
9960 match(Set dst (ModD src0 src1));
9961 effect(KILL rax, KILL cr);
9962
9963 format %{ "SUB ESP,8\t # DMOD\n"
9964 "\tMOVSD [ESP+0],$src1\n"
9965 "\tFLD_D [ESP+0]\n"
9966 "\tMOVSD [ESP+0],$src0\n"
9967 "\tFLD_D [ESP+0]\n"
9968 "loop:\tFPREM\n"
9969 "\tFWAIT\n"
9970 "\tFNSTSW AX\n"
9971 "\tSAHF\n"
9972 "\tJP loop\n"
9973 "\tFSTP_D [ESP+0]\n"
9974 "\tMOVSD $dst,[ESP+0]\n"
9975 "\tADD ESP,8\n"
9976 "\tFSTP ST0\t # Restore FPU Stack"
9977 %}
9978 ins_cost(250);
9979 ins_encode( Push_ModD_encoding(src0, src1), emitModDPR(), Push_ResultD(dst), PopFPU);
9980 ins_pipe( pipe_slow );
9981 %}
9982
9983 instruct sinDPR_reg(regDPR1 dst, regDPR1 src) %{
9984 predicate (UseSSE<=1);
9985 match(Set dst (SinD src));
9986 ins_cost(1800);
9987 format %{ "DSIN $dst" %}
9988 opcode(0xD9, 0xFE);
9989 ins_encode( OpcP, OpcS );
9990 ins_pipe( pipe_slow );
9991 %}
9992
9993 instruct sinD_reg(regD dst, eFlagsReg cr) %{
9994 predicate (UseSSE>=2);
9995 match(Set dst (SinD dst));
9996 effect(KILL cr); // Push_{Src|Result}D() uses "{SUB|ADD} ESP,8"
9997 ins_cost(1800);
9998 format %{ "DSIN $dst" %}
9999 opcode(0xD9, 0xFE);
10000 ins_encode( Push_SrcD(dst), OpcP, OpcS, Push_ResultD(dst) );
10001 ins_pipe( pipe_slow );
10002 %}
10003
10004 instruct cosDPR_reg(regDPR1 dst, regDPR1 src) %{
10005 predicate (UseSSE<=1);
10006 match(Set dst (CosD src));
10007 ins_cost(1800);
10008 format %{ "DCOS $dst" %}
10009 opcode(0xD9, 0xFF);
10010 ins_encode( OpcP, OpcS );
10011 ins_pipe( pipe_slow );
10012 %}
10013
10014 instruct cosD_reg(regD dst, eFlagsReg cr) %{
10015 predicate (UseSSE>=2);
10016 match(Set dst (CosD dst));
10017 effect(KILL cr); // Push_{Src|Result}D() uses "{SUB|ADD} ESP,8"
10018 ins_cost(1800);
10019 format %{ "DCOS $dst" %}
10020 opcode(0xD9, 0xFF);
10021 ins_encode( Push_SrcD(dst), OpcP, OpcS, Push_ResultD(dst) );
10022 ins_pipe( pipe_slow );
10023 %}
10024
10025 instruct tanDPR_reg(regDPR1 dst, regDPR1 src) %{
10026 predicate (UseSSE<=1);
10027 match(Set dst(TanD src));
10028 format %{ "DTAN $dst" %}
10029 ins_encode( Opcode(0xD9), Opcode(0xF2), // fptan
10030 Opcode(0xDD), Opcode(0xD8)); // fstp st
10031 ins_pipe( pipe_slow );
10032 %}
10033
10034 instruct tanD_reg(regD dst, eFlagsReg cr) %{
10035 predicate (UseSSE>=2);
10036 match(Set dst(TanD dst));
10037 effect(KILL cr); // Push_{Src|Result}D() uses "{SUB|ADD} ESP,8"
10038 format %{ "DTAN $dst" %}
10039 ins_encode( Push_SrcD(dst),
10040 Opcode(0xD9), Opcode(0xF2), // fptan
10041 Opcode(0xDD), Opcode(0xD8), // fstp st
10042 Push_ResultD(dst) );
10043 ins_pipe( pipe_slow );
10044 %}
10045
10046 instruct atanDPR_reg(regDPR dst, regDPR src) %{
10047 predicate (UseSSE<=1);
10048 match(Set dst(AtanD dst src));
10049 format %{ "DATA $dst,$src" %}
10050 opcode(0xD9, 0xF3);
10051 ins_encode( Push_Reg_DPR(src),
10052 OpcP, OpcS, RegOpc(dst) );
10053 ins_pipe( pipe_slow );
10054 %}
10055
10056 instruct atanD_reg(regD dst, regD src, eFlagsReg cr) %{
10057 predicate (UseSSE>=2);
10058 match(Set dst(AtanD dst src));
10059 effect(KILL cr); // Push_{Src|Result}D() uses "{SUB|ADD} ESP,8"
10060 format %{ "DATA $dst,$src" %}
10061 opcode(0xD9, 0xF3);
10062 ins_encode( Push_SrcD(src),
10063 OpcP, OpcS, Push_ResultD(dst) );
10064 ins_pipe( pipe_slow );
10065 %}
10066
10067 instruct sqrtDPR_reg(regDPR dst, regDPR src) %{
10068 predicate (UseSSE<=1);
10069 match(Set dst (SqrtD src));
10070 format %{ "DSQRT $dst,$src" %}
10071 opcode(0xFA, 0xD9);
10072 ins_encode( Push_Reg_DPR(src),
10073 OpcS, OpcP, Pop_Reg_DPR(dst) );
10074 ins_pipe( pipe_slow );
10075 %}
10076
10077 instruct powDPR_reg(regDPR X, regDPR1 Y, eAXRegI rax, eDXRegI rdx, eCXRegI rcx, eFlagsReg cr) %{
10078 predicate (UseSSE<=1);
10079 match(Set Y (PowD X Y)); // Raise X to the Yth power
10080 effect(KILL rax, KILL rdx, KILL rcx, KILL cr);
10081 format %{ "fast_pow $X $Y -> $Y // KILL $rax, $rcx, $rdx" %}
10082 ins_encode %{
10083 __ subptr(rsp, 8);
10084 __ fld_s($X$$reg - 1);
10085 __ fast_pow();
10086 __ addptr(rsp, 8);
10087 %}
10088 ins_pipe( pipe_slow );
10089 %}
10090
10091 instruct powD_reg(regD dst, regD src0, regD src1, eAXRegI rax, eDXRegI rdx, eCXRegI rcx, eFlagsReg cr) %{
10092 predicate (UseSSE>=2);
10093 match(Set dst (PowD src0 src1)); // Raise src0 to the src1'th power
10094 effect(KILL rax, KILL rdx, KILL rcx, KILL cr);
10095 format %{ "fast_pow $src0 $src1 -> $dst // KILL $rax, $rcx, $rdx" %}
10096 ins_encode %{
10097 __ subptr(rsp, 8);
10098 __ movdbl(Address(rsp, 0), $src1$$XMMRegister);
10099 __ fld_d(Address(rsp, 0));
10100 __ movdbl(Address(rsp, 0), $src0$$XMMRegister);
10101 __ fld_d(Address(rsp, 0));
10102 __ fast_pow();
10103 __ fstp_d(Address(rsp, 0));
10104 __ movdbl($dst$$XMMRegister, Address(rsp, 0));
10105 __ addptr(rsp, 8);
10106 %}
10107 ins_pipe( pipe_slow );
10108 %}
10109
10110
10111 instruct expDPR_reg(regDPR1 dpr1, eAXRegI rax, eDXRegI rdx, eCXRegI rcx, eFlagsReg cr) %{
10112 predicate (UseSSE<=1);
10113 match(Set dpr1 (ExpD dpr1));
10114 effect(KILL rax, KILL rcx, KILL rdx, KILL cr);
10115 format %{ "fast_exp $dpr1 -> $dpr1 // KILL $rax, $rcx, $rdx" %}
10116 ins_encode %{
10117 __ fast_exp();
10118 %}
10119 ins_pipe( pipe_slow );
10120 %}
10121
10122 instruct expD_reg(regD dst, regD src, eAXRegI rax, eDXRegI rdx, eCXRegI rcx, eFlagsReg cr) %{
10123 predicate (UseSSE>=2);
10124 match(Set dst (ExpD src));
10125 effect(KILL rax, KILL rcx, KILL rdx, KILL cr);
10126 format %{ "fast_exp $dst -> $src // KILL $rax, $rcx, $rdx" %}
10127 ins_encode %{
10128 __ subptr(rsp, 8);
10129 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
10130 __ fld_d(Address(rsp, 0));
10131 __ fast_exp();
10132 __ fstp_d(Address(rsp, 0));
10133 __ movdbl($dst$$XMMRegister, Address(rsp, 0));
10134 __ addptr(rsp, 8);
10135 %}
10136 ins_pipe( pipe_slow );
10137 %}
10138
10139 instruct log10DPR_reg(regDPR1 dst, regDPR1 src) %{
10140 predicate (UseSSE<=1);
10141 // The source Double operand on FPU stack
10142 match(Set dst (Log10D src));
10143 // fldlg2 ; push log_10(2) on the FPU stack; full 80-bit number
10144 // fxch ; swap ST(0) with ST(1)
10145 // fyl2x ; compute log_10(2) * log_2(x)
10146 format %{ "FLDLG2 \t\t\t#Log10\n\t"
10147 "FXCH \n\t"
10148 "FYL2X \t\t\t# Q=Log10*Log_2(x)"
10149 %}
10150 ins_encode( Opcode(0xD9), Opcode(0xEC), // fldlg2
10151 Opcode(0xD9), Opcode(0xC9), // fxch
10152 Opcode(0xD9), Opcode(0xF1)); // fyl2x
10153
10154 ins_pipe( pipe_slow );
10155 %}
10156
10157 instruct log10D_reg(regD dst, regD src, eFlagsReg cr) %{
10158 predicate (UseSSE>=2);
10159 effect(KILL cr);
10160 match(Set dst (Log10D src));
10161 // fldlg2 ; push log_10(2) on the FPU stack; full 80-bit number
10162 // fyl2x ; compute log_10(2) * log_2(x)
10163 format %{ "FLDLG2 \t\t\t#Log10\n\t"
10164 "FYL2X \t\t\t# Q=Log10*Log_2(x)"
10165 %}
10166 ins_encode( Opcode(0xD9), Opcode(0xEC), // fldlg2
10167 Push_SrcD(src),
10168 Opcode(0xD9), Opcode(0xF1), // fyl2x
10169 Push_ResultD(dst));
10170
10171 ins_pipe( pipe_slow );
10172 %}
10173
10174 instruct logDPR_reg(regDPR1 dst, regDPR1 src) %{
10175 predicate (UseSSE<=1);
10176 // The source Double operand on FPU stack
10177 match(Set dst (LogD src));
10178 // fldln2 ; push log_e(2) on the FPU stack; full 80-bit number
10179 // fxch ; swap ST(0) with ST(1)
10180 // fyl2x ; compute log_e(2) * log_2(x)
10181 format %{ "FLDLN2 \t\t\t#Log_e\n\t"
10182 "FXCH \n\t"
10183 "FYL2X \t\t\t# Q=Log_e*Log_2(x)"
10184 %}
10185 ins_encode( Opcode(0xD9), Opcode(0xED), // fldln2
10186 Opcode(0xD9), Opcode(0xC9), // fxch
10187 Opcode(0xD9), Opcode(0xF1)); // fyl2x
10188
10189 ins_pipe( pipe_slow );
10190 %}
10191
10192 instruct logD_reg(regD dst, regD src, eFlagsReg cr) %{
10193 predicate (UseSSE>=2);
10194 effect(KILL cr);
10195 // The source and result Double operands in XMM registers
10196 match(Set dst (LogD src));
10197 // fldln2 ; push log_e(2) on the FPU stack; full 80-bit number
10198 // fyl2x ; compute log_e(2) * log_2(x)
10199 format %{ "FLDLN2 \t\t\t#Log_e\n\t"
10200 "FYL2X \t\t\t# Q=Log_e*Log_2(x)"
10201 %}
10202 ins_encode( Opcode(0xD9), Opcode(0xED), // fldln2
10203 Push_SrcD(src),
10204 Opcode(0xD9), Opcode(0xF1), // fyl2x
10205 Push_ResultD(dst));
10206 ins_pipe( pipe_slow );
10207 %}
10208
10209 //-------------Float Instructions-------------------------------
10210 // Float Math
10211
10212 // Code for float compare:
10213 // fcompp();
10214 // fwait(); fnstsw_ax();
10215 // sahf();
10216 // movl(dst, unordered_result);
10217 // jcc(Assembler::parity, exit);
10218 // movl(dst, less_result);
10219 // jcc(Assembler::below, exit);
10220 // movl(dst, equal_result);
10221 // jcc(Assembler::equal, exit);
10222 // movl(dst, greater_result);
10223 // exit:
10224
10225 // P6 version of float compare, sets condition codes in EFLAGS
10226 instruct cmpFPR_cc_P6(eFlagsRegU cr, regFPR src1, regFPR src2, eAXRegI rax) %{
10227 predicate(VM_Version::supports_cmov() && UseSSE == 0);
10228 match(Set cr (CmpF src1 src2));
10229 effect(KILL rax);
10230 ins_cost(150);
10231 format %{ "FLD $src1\n\t"
10232 "FUCOMIP ST,$src2 // P6 instruction\n\t"
10233 "JNP exit\n\t"
10234 "MOV ah,1 // saw a NaN, set CF (treat as LT)\n\t"
10235 "SAHF\n"
10236 "exit:\tNOP // avoid branch to branch" %}
10237 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
10238 ins_encode( Push_Reg_DPR(src1),
10239 OpcP, RegOpc(src2),
10240 cmpF_P6_fixup );
10241 ins_pipe( pipe_slow );
10242 %}
10243
10244 instruct cmpFPR_cc_P6CF(eFlagsRegUCF cr, regFPR src1, regFPR src2) %{
10245 predicate(VM_Version::supports_cmov() && UseSSE == 0);
10246 match(Set cr (CmpF src1 src2));
10247 ins_cost(100);
10248 format %{ "FLD $src1\n\t"
10249 "FUCOMIP ST,$src2 // P6 instruction" %}
10250 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */
10251 ins_encode( Push_Reg_DPR(src1),
10252 OpcP, RegOpc(src2));
10253 ins_pipe( pipe_slow );
10254 %}
10255
10256
10257 // Compare & branch
10258 instruct cmpFPR_cc(eFlagsRegU cr, regFPR src1, regFPR src2, eAXRegI rax) %{
10259 predicate(UseSSE == 0);
10260 match(Set cr (CmpF src1 src2));
10261 effect(KILL rax);
10262 ins_cost(200);
10263 format %{ "FLD $src1\n\t"
10264 "FCOMp $src2\n\t"
10265 "FNSTSW AX\n\t"
10266 "TEST AX,0x400\n\t"
10267 "JZ,s flags\n\t"
10268 "MOV AH,1\t# unordered treat as LT\n"
10269 "flags:\tSAHF" %}
10270 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
10271 ins_encode( Push_Reg_DPR(src1),
10272 OpcP, RegOpc(src2),
10273 fpu_flags);
10274 ins_pipe( pipe_slow );
10275 %}
10276
10277 // Compare vs zero into -1,0,1
10278 instruct cmpFPR_0(rRegI dst, regFPR src1, immFPR0 zero, eAXRegI rax, eFlagsReg cr) %{
10279 predicate(UseSSE == 0);
10280 match(Set dst (CmpF3 src1 zero));
10281 effect(KILL cr, KILL rax);
10282 ins_cost(280);
10283 format %{ "FTSTF $dst,$src1" %}
10284 opcode(0xE4, 0xD9);
10285 ins_encode( Push_Reg_DPR(src1),
10286 OpcS, OpcP, PopFPU,
10287 CmpF_Result(dst));
10288 ins_pipe( pipe_slow );
10289 %}
10290
10291 // Compare into -1,0,1
10292 instruct cmpFPR_reg(rRegI dst, regFPR src1, regFPR src2, eAXRegI rax, eFlagsReg cr) %{
10293 predicate(UseSSE == 0);
10294 match(Set dst (CmpF3 src1 src2));
10295 effect(KILL cr, KILL rax);
10296 ins_cost(300);
10297 format %{ "FCMPF $dst,$src1,$src2" %}
10298 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */
10299 ins_encode( Push_Reg_DPR(src1),
10300 OpcP, RegOpc(src2),
10301 CmpF_Result(dst));
10302 ins_pipe( pipe_slow );
10303 %}
10304
10305 // float compare and set condition codes in EFLAGS by XMM regs
10306 instruct cmpF_cc(eFlagsRegU cr, regF src1, regF src2) %{
10307 predicate(UseSSE>=1);
10308 match(Set cr (CmpF src1 src2));
10309 ins_cost(145);
10310 format %{ "UCOMISS $src1,$src2\n\t"
10311 "JNP,s exit\n\t"
10312 "PUSHF\t# saw NaN, set CF\n\t"
10313 "AND [rsp], #0xffffff2b\n\t"
10314 "POPF\n"
10315 "exit:" %}
10316 ins_encode %{
10317 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
10318 emit_cmpfp_fixup(_masm);
10319 %}
10320 ins_pipe( pipe_slow );
10321 %}
10322
10323 instruct cmpF_ccCF(eFlagsRegUCF cr, regF src1, regF src2) %{
10324 predicate(UseSSE>=1);
10325 match(Set cr (CmpF src1 src2));
10326 ins_cost(100);
10327 format %{ "UCOMISS $src1,$src2" %}
10328 ins_encode %{
10329 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
10330 %}
10331 ins_pipe( pipe_slow );
10332 %}
10333
10334 // float compare and set condition codes in EFLAGS by XMM regs
10335 instruct cmpF_ccmem(eFlagsRegU cr, regF src1, memory src2) %{
10336 predicate(UseSSE>=1);
10337 match(Set cr (CmpF src1 (LoadF src2)));
10338 ins_cost(165);
10339 format %{ "UCOMISS $src1,$src2\n\t"
10340 "JNP,s exit\n\t"
10341 "PUSHF\t# saw NaN, set CF\n\t"
10342 "AND [rsp], #0xffffff2b\n\t"
10343 "POPF\n"
10344 "exit:" %}
10345 ins_encode %{
10346 __ ucomiss($src1$$XMMRegister, $src2$$Address);
10347 emit_cmpfp_fixup(_masm);
10348 %}
10349 ins_pipe( pipe_slow );
10350 %}
10351
10352 instruct cmpF_ccmemCF(eFlagsRegUCF cr, regF src1, memory src2) %{
10353 predicate(UseSSE>=1);
10354 match(Set cr (CmpF src1 (LoadF src2)));
10355 ins_cost(100);
10356 format %{ "UCOMISS $src1,$src2" %}
10357 ins_encode %{
10358 __ ucomiss($src1$$XMMRegister, $src2$$Address);
10359 %}
10360 ins_pipe( pipe_slow );
10361 %}
10362
10363 // Compare into -1,0,1 in XMM
10364 instruct cmpF_reg(xRegI dst, regF src1, regF src2, eFlagsReg cr) %{
10365 predicate(UseSSE>=1);
10366 match(Set dst (CmpF3 src1 src2));
10367 effect(KILL cr);
10368 ins_cost(255);
10369 format %{ "UCOMISS $src1, $src2\n\t"
10370 "MOV $dst, #-1\n\t"
10371 "JP,s done\n\t"
10372 "JB,s done\n\t"
10373 "SETNE $dst\n\t"
10374 "MOVZB $dst, $dst\n"
10375 "done:" %}
10376 ins_encode %{
10377 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
10378 emit_cmpfp3(_masm, $dst$$Register);
10379 %}
10380 ins_pipe( pipe_slow );
10381 %}
10382
10383 // Compare into -1,0,1 in XMM and memory
10384 instruct cmpF_regmem(xRegI dst, regF src1, memory src2, eFlagsReg cr) %{
10385 predicate(UseSSE>=1);
10386 match(Set dst (CmpF3 src1 (LoadF src2)));
10387 effect(KILL cr);
10388 ins_cost(275);
10389 format %{ "UCOMISS $src1, $src2\n\t"
10390 "MOV $dst, #-1\n\t"
10391 "JP,s done\n\t"
10392 "JB,s done\n\t"
10393 "SETNE $dst\n\t"
10394 "MOVZB $dst, $dst\n"
10395 "done:" %}
10396 ins_encode %{
10397 __ ucomiss($src1$$XMMRegister, $src2$$Address);
10398 emit_cmpfp3(_masm, $dst$$Register);
10399 %}
10400 ins_pipe( pipe_slow );
10401 %}
10402
10403 // Spill to obtain 24-bit precision
10404 instruct subFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2) %{
10405 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10406 match(Set dst (SubF src1 src2));
10407
10408 format %{ "FSUB $dst,$src1 - $src2" %}
10409 opcode(0xD8, 0x4); /* D8 E0+i or D8 /4 mod==0x3 ;; result in TOS */
10410 ins_encode( Push_Reg_FPR(src1),
10411 OpcReg_FPR(src2),
10412 Pop_Mem_FPR(dst) );
10413 ins_pipe( fpu_mem_reg_reg );
10414 %}
10415 //
10416 // This instruction does not round to 24-bits
10417 instruct subFPR_reg(regFPR dst, regFPR src) %{
10418 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10419 match(Set dst (SubF dst src));
10420
10421 format %{ "FSUB $dst,$src" %}
10422 opcode(0xDE, 0x5); /* DE E8+i or DE /5 */
10423 ins_encode( Push_Reg_FPR(src),
10424 OpcP, RegOpc(dst) );
10425 ins_pipe( fpu_reg_reg );
10426 %}
10427
10428 // Spill to obtain 24-bit precision
10429 instruct addFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2) %{
10430 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10431 match(Set dst (AddF src1 src2));
10432
10433 format %{ "FADD $dst,$src1,$src2" %}
10434 opcode(0xD8, 0x0); /* D8 C0+i */
10435 ins_encode( Push_Reg_FPR(src2),
10436 OpcReg_FPR(src1),
10437 Pop_Mem_FPR(dst) );
10438 ins_pipe( fpu_mem_reg_reg );
10439 %}
10440 //
10441 // This instruction does not round to 24-bits
10442 instruct addFPR_reg(regFPR dst, regFPR src) %{
10443 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10444 match(Set dst (AddF dst src));
10445
10446 format %{ "FLD $src\n\t"
10447 "FADDp $dst,ST" %}
10448 opcode(0xDE, 0x0); /* DE C0+i or DE /0*/
10449 ins_encode( Push_Reg_FPR(src),
10450 OpcP, RegOpc(dst) );
10451 ins_pipe( fpu_reg_reg );
10452 %}
10453
10454 instruct absFPR_reg(regFPR1 dst, regFPR1 src) %{
10455 predicate(UseSSE==0);
10456 match(Set dst (AbsF src));
10457 ins_cost(100);
10458 format %{ "FABS" %}
10459 opcode(0xE1, 0xD9);
10460 ins_encode( OpcS, OpcP );
10461 ins_pipe( fpu_reg_reg );
10462 %}
10463
10464 instruct negFPR_reg(regFPR1 dst, regFPR1 src) %{
10465 predicate(UseSSE==0);
10466 match(Set dst (NegF src));
10467 ins_cost(100);
10468 format %{ "FCHS" %}
10469 opcode(0xE0, 0xD9);
10470 ins_encode( OpcS, OpcP );
10471 ins_pipe( fpu_reg_reg );
10472 %}
10473
10474 // Cisc-alternate to addFPR_reg
10475 // Spill to obtain 24-bit precision
10476 instruct addFPR24_reg_mem(stackSlotF dst, regFPR src1, memory src2) %{
10477 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10478 match(Set dst (AddF src1 (LoadF src2)));
10479
10480 format %{ "FLD $src2\n\t"
10481 "FADD ST,$src1\n\t"
10482 "FSTP_S $dst" %}
10483 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */
10484 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10485 OpcReg_FPR(src1),
10486 Pop_Mem_FPR(dst) );
10487 ins_pipe( fpu_mem_reg_mem );
10488 %}
10489 //
10490 // Cisc-alternate to addFPR_reg
10491 // This instruction does not round to 24-bits
10492 instruct addFPR_reg_mem(regFPR dst, memory src) %{
10493 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10494 match(Set dst (AddF dst (LoadF src)));
10495
10496 format %{ "FADD $dst,$src" %}
10497 opcode(0xDE, 0x0, 0xD9); /* DE C0+i or DE /0*/ /* LoadF D9 /0 */
10498 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src),
10499 OpcP, RegOpc(dst) );
10500 ins_pipe( fpu_reg_mem );
10501 %}
10502
10503 // // Following two instructions for _222_mpegaudio
10504 // Spill to obtain 24-bit precision
10505 instruct addFPR24_mem_reg(stackSlotF dst, regFPR src2, memory src1 ) %{
10506 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10507 match(Set dst (AddF src1 src2));
10508
10509 format %{ "FADD $dst,$src1,$src2" %}
10510 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */
10511 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src1),
10512 OpcReg_FPR(src2),
10513 Pop_Mem_FPR(dst) );
10514 ins_pipe( fpu_mem_reg_mem );
10515 %}
10516
10517 // Cisc-spill variant
10518 // Spill to obtain 24-bit precision
10519 instruct addFPR24_mem_cisc(stackSlotF dst, memory src1, memory src2) %{
10520 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10521 match(Set dst (AddF src1 (LoadF src2)));
10522
10523 format %{ "FADD $dst,$src1,$src2 cisc" %}
10524 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */
10525 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10526 set_instruction_start,
10527 OpcP, RMopc_Mem(secondary,src1),
10528 Pop_Mem_FPR(dst) );
10529 ins_pipe( fpu_mem_mem_mem );
10530 %}
10531
10532 // Spill to obtain 24-bit precision
10533 instruct addFPR24_mem_mem(stackSlotF dst, memory src1, memory src2) %{
10534 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10535 match(Set dst (AddF src1 src2));
10536
10537 format %{ "FADD $dst,$src1,$src2" %}
10538 opcode(0xD8, 0x0, 0xD9); /* D8 /0 */ /* LoadF D9 /0 */
10539 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10540 set_instruction_start,
10541 OpcP, RMopc_Mem(secondary,src1),
10542 Pop_Mem_FPR(dst) );
10543 ins_pipe( fpu_mem_mem_mem );
10544 %}
10545
10546
10547 // Spill to obtain 24-bit precision
10548 instruct addFPR24_reg_imm(stackSlotF dst, regFPR src, immFPR con) %{
10549 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10550 match(Set dst (AddF src con));
10551 format %{ "FLD $src\n\t"
10552 "FADD_S [$constantaddress]\t# load from constant table: float=$con\n\t"
10553 "FSTP_S $dst" %}
10554 ins_encode %{
10555 __ fld_s($src$$reg - 1); // FLD ST(i-1)
10556 __ fadd_s($constantaddress($con));
10557 __ fstp_s(Address(rsp, $dst$$disp));
10558 %}
10559 ins_pipe(fpu_mem_reg_con);
10560 %}
10561 //
10562 // This instruction does not round to 24-bits
10563 instruct addFPR_reg_imm(regFPR dst, regFPR src, immFPR con) %{
10564 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10565 match(Set dst (AddF src con));
10566 format %{ "FLD $src\n\t"
10567 "FADD_S [$constantaddress]\t# load from constant table: float=$con\n\t"
10568 "FSTP $dst" %}
10569 ins_encode %{
10570 __ fld_s($src$$reg - 1); // FLD ST(i-1)
10571 __ fadd_s($constantaddress($con));
10572 __ fstp_d($dst$$reg);
10573 %}
10574 ins_pipe(fpu_reg_reg_con);
10575 %}
10576
10577 // Spill to obtain 24-bit precision
10578 instruct mulFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2) %{
10579 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10580 match(Set dst (MulF src1 src2));
10581
10582 format %{ "FLD $src1\n\t"
10583 "FMUL $src2\n\t"
10584 "FSTP_S $dst" %}
10585 opcode(0xD8, 0x1); /* D8 C8+i or D8 /1 ;; result in TOS */
10586 ins_encode( Push_Reg_FPR(src1),
10587 OpcReg_FPR(src2),
10588 Pop_Mem_FPR(dst) );
10589 ins_pipe( fpu_mem_reg_reg );
10590 %}
10591 //
10592 // This instruction does not round to 24-bits
10593 instruct mulFPR_reg(regFPR dst, regFPR src1, regFPR src2) %{
10594 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10595 match(Set dst (MulF src1 src2));
10596
10597 format %{ "FLD $src1\n\t"
10598 "FMUL $src2\n\t"
10599 "FSTP_S $dst" %}
10600 opcode(0xD8, 0x1); /* D8 C8+i */
10601 ins_encode( Push_Reg_FPR(src2),
10602 OpcReg_FPR(src1),
10603 Pop_Reg_FPR(dst) );
10604 ins_pipe( fpu_reg_reg_reg );
10605 %}
10606
10607
10608 // Spill to obtain 24-bit precision
10609 // Cisc-alternate to reg-reg multiply
10610 instruct mulFPR24_reg_mem(stackSlotF dst, regFPR src1, memory src2) %{
10611 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10612 match(Set dst (MulF src1 (LoadF src2)));
10613
10614 format %{ "FLD_S $src2\n\t"
10615 "FMUL $src1\n\t"
10616 "FSTP_S $dst" %}
10617 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i or DE /1*/ /* LoadF D9 /0 */
10618 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10619 OpcReg_FPR(src1),
10620 Pop_Mem_FPR(dst) );
10621 ins_pipe( fpu_mem_reg_mem );
10622 %}
10623 //
10624 // This instruction does not round to 24-bits
10625 // Cisc-alternate to reg-reg multiply
10626 instruct mulFPR_reg_mem(regFPR dst, regFPR src1, memory src2) %{
10627 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10628 match(Set dst (MulF src1 (LoadF src2)));
10629
10630 format %{ "FMUL $dst,$src1,$src2" %}
10631 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i */ /* LoadF D9 /0 */
10632 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10633 OpcReg_FPR(src1),
10634 Pop_Reg_FPR(dst) );
10635 ins_pipe( fpu_reg_reg_mem );
10636 %}
10637
10638 // Spill to obtain 24-bit precision
10639 instruct mulFPR24_mem_mem(stackSlotF dst, memory src1, memory src2) %{
10640 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10641 match(Set dst (MulF src1 src2));
10642
10643 format %{ "FMUL $dst,$src1,$src2" %}
10644 opcode(0xD8, 0x1, 0xD9); /* D8 /1 */ /* LoadF D9 /0 */
10645 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2),
10646 set_instruction_start,
10647 OpcP, RMopc_Mem(secondary,src1),
10648 Pop_Mem_FPR(dst) );
10649 ins_pipe( fpu_mem_mem_mem );
10650 %}
10651
10652 // Spill to obtain 24-bit precision
10653 instruct mulFPR24_reg_imm(stackSlotF dst, regFPR src, immFPR con) %{
10654 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10655 match(Set dst (MulF src con));
10656
10657 format %{ "FLD $src\n\t"
10658 "FMUL_S [$constantaddress]\t# load from constant table: float=$con\n\t"
10659 "FSTP_S $dst" %}
10660 ins_encode %{
10661 __ fld_s($src$$reg - 1); // FLD ST(i-1)
10662 __ fmul_s($constantaddress($con));
10663 __ fstp_s(Address(rsp, $dst$$disp));
10664 %}
10665 ins_pipe(fpu_mem_reg_con);
10666 %}
10667 //
10668 // This instruction does not round to 24-bits
10669 instruct mulFPR_reg_imm(regFPR dst, regFPR src, immFPR con) %{
10670 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10671 match(Set dst (MulF src con));
10672
10673 format %{ "FLD $src\n\t"
10674 "FMUL_S [$constantaddress]\t# load from constant table: float=$con\n\t"
10675 "FSTP $dst" %}
10676 ins_encode %{
10677 __ fld_s($src$$reg - 1); // FLD ST(i-1)
10678 __ fmul_s($constantaddress($con));
10679 __ fstp_d($dst$$reg);
10680 %}
10681 ins_pipe(fpu_reg_reg_con);
10682 %}
10683
10684
10685 //
10686 // MACRO1 -- subsume unshared load into mulFPR
10687 // This instruction does not round to 24-bits
10688 instruct mulFPR_reg_load1(regFPR dst, regFPR src, memory mem1 ) %{
10689 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10690 match(Set dst (MulF (LoadF mem1) src));
10691
10692 format %{ "FLD $mem1 ===MACRO1===\n\t"
10693 "FMUL ST,$src\n\t"
10694 "FSTP $dst" %}
10695 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i or D8 /1 */ /* LoadF D9 /0 */
10696 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,mem1),
10697 OpcReg_FPR(src),
10698 Pop_Reg_FPR(dst) );
10699 ins_pipe( fpu_reg_reg_mem );
10700 %}
10701 //
10702 // MACRO2 -- addFPR a mulFPR which subsumed an unshared load
10703 // This instruction does not round to 24-bits
10704 instruct addFPR_mulFPR_reg_load1(regFPR dst, memory mem1, regFPR src1, regFPR src2) %{
10705 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10706 match(Set dst (AddF (MulF (LoadF mem1) src1) src2));
10707 ins_cost(95);
10708
10709 format %{ "FLD $mem1 ===MACRO2===\n\t"
10710 "FMUL ST,$src1 subsume mulFPR left load\n\t"
10711 "FADD ST,$src2\n\t"
10712 "FSTP $dst" %}
10713 opcode(0xD9); /* LoadF D9 /0 */
10714 ins_encode( OpcP, RMopc_Mem(0x00,mem1),
10715 FMul_ST_reg(src1),
10716 FAdd_ST_reg(src2),
10717 Pop_Reg_FPR(dst) );
10718 ins_pipe( fpu_reg_mem_reg_reg );
10719 %}
10720
10721 // MACRO3 -- addFPR a mulFPR
10722 // This instruction does not round to 24-bits. It is a '2-address'
10723 // instruction in that the result goes back to src2. This eliminates
10724 // a move from the macro; possibly the register allocator will have
10725 // to add it back (and maybe not).
10726 instruct addFPR_mulFPR_reg(regFPR src2, regFPR src1, regFPR src0) %{
10727 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10728 match(Set src2 (AddF (MulF src0 src1) src2));
10729
10730 format %{ "FLD $src0 ===MACRO3===\n\t"
10731 "FMUL ST,$src1\n\t"
10732 "FADDP $src2,ST" %}
10733 opcode(0xD9); /* LoadF D9 /0 */
10734 ins_encode( Push_Reg_FPR(src0),
10735 FMul_ST_reg(src1),
10736 FAddP_reg_ST(src2) );
10737 ins_pipe( fpu_reg_reg_reg );
10738 %}
10739
10740 // MACRO4 -- divFPR subFPR
10741 // This instruction does not round to 24-bits
10742 instruct subFPR_divFPR_reg(regFPR dst, regFPR src1, regFPR src2, regFPR src3) %{
10743 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10744 match(Set dst (DivF (SubF src2 src1) src3));
10745
10746 format %{ "FLD $src2 ===MACRO4===\n\t"
10747 "FSUB ST,$src1\n\t"
10748 "FDIV ST,$src3\n\t"
10749 "FSTP $dst" %}
10750 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
10751 ins_encode( Push_Reg_FPR(src2),
10752 subFPR_divFPR_encode(src1,src3),
10753 Pop_Reg_FPR(dst) );
10754 ins_pipe( fpu_reg_reg_reg_reg );
10755 %}
10756
10757 // Spill to obtain 24-bit precision
10758 instruct divFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2) %{
10759 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr());
10760 match(Set dst (DivF src1 src2));
10761
10762 format %{ "FDIV $dst,$src1,$src2" %}
10763 opcode(0xD8, 0x6); /* D8 F0+i or DE /6*/
10764 ins_encode( Push_Reg_FPR(src1),
10765 OpcReg_FPR(src2),
10766 Pop_Mem_FPR(dst) );
10767 ins_pipe( fpu_mem_reg_reg );
10768 %}
10769 //
10770 // This instruction does not round to 24-bits
10771 instruct divFPR_reg(regFPR dst, regFPR src) %{
10772 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr());
10773 match(Set dst (DivF dst src));
10774
10775 format %{ "FDIV $dst,$src" %}
10776 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/
10777 ins_encode( Push_Reg_FPR(src),
10778 OpcP, RegOpc(dst) );
10779 ins_pipe( fpu_reg_reg );
10780 %}
10781
10782
10783 // Spill to obtain 24-bit precision
10784 instruct modFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2, eAXRegI rax, eFlagsReg cr) %{
10785 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr());
10786 match(Set dst (ModF src1 src2));
10787 effect(KILL rax, KILL cr); // emitModDPR() uses EAX and EFLAGS
10788
10789 format %{ "FMOD $dst,$src1,$src2" %}
10790 ins_encode( Push_Reg_Mod_DPR(src1, src2),
10791 emitModDPR(),
10792 Push_Result_Mod_DPR(src2),
10793 Pop_Mem_FPR(dst));
10794 ins_pipe( pipe_slow );
10795 %}
10796 //
10797 // This instruction does not round to 24-bits
10798 instruct modFPR_reg(regFPR dst, regFPR src, eAXRegI rax, eFlagsReg cr) %{
10799 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr());
10800 match(Set dst (ModF dst src));
10801 effect(KILL rax, KILL cr); // emitModDPR() uses EAX and EFLAGS
10802
10803 format %{ "FMOD $dst,$src" %}
10804 ins_encode(Push_Reg_Mod_DPR(dst, src),
10805 emitModDPR(),
10806 Push_Result_Mod_DPR(src),
10807 Pop_Reg_FPR(dst));
10808 ins_pipe( pipe_slow );
10809 %}
10810
10811 instruct modF_reg(regF dst, regF src0, regF src1, eAXRegI rax, eFlagsReg cr) %{
10812 predicate(UseSSE>=1);
10813 match(Set dst (ModF src0 src1));
10814 effect(KILL rax, KILL cr);
10815 format %{ "SUB ESP,4\t # FMOD\n"
10816 "\tMOVSS [ESP+0],$src1\n"
10817 "\tFLD_S [ESP+0]\n"
10818 "\tMOVSS [ESP+0],$src0\n"
10819 "\tFLD_S [ESP+0]\n"
10820 "loop:\tFPREM\n"
10821 "\tFWAIT\n"
10822 "\tFNSTSW AX\n"
10823 "\tSAHF\n"
10824 "\tJP loop\n"
10825 "\tFSTP_S [ESP+0]\n"
10826 "\tMOVSS $dst,[ESP+0]\n"
10827 "\tADD ESP,4\n"
10828 "\tFSTP ST0\t # Restore FPU Stack"
10829 %}
10830 ins_cost(250);
10831 ins_encode( Push_ModF_encoding(src0, src1), emitModDPR(), Push_ResultF(dst,0x4), PopFPU);
10832 ins_pipe( pipe_slow );
10833 %}
10834
10835
10836 //----------Arithmetic Conversion Instructions---------------------------------
10837 // The conversions operations are all Alpha sorted. Please keep it that way!
10838
10839 instruct roundFloat_mem_reg(stackSlotF dst, regFPR src) %{
10840 predicate(UseSSE==0);
10841 match(Set dst (RoundFloat src));
10842 ins_cost(125);
10843 format %{ "FST_S $dst,$src\t# F-round" %}
10844 ins_encode( Pop_Mem_Reg_FPR(dst, src) );
10845 ins_pipe( fpu_mem_reg );
10846 %}
10847
10848 instruct roundDouble_mem_reg(stackSlotD dst, regDPR src) %{
10849 predicate(UseSSE<=1);
10850 match(Set dst (RoundDouble src));
10851 ins_cost(125);
10852 format %{ "FST_D $dst,$src\t# D-round" %}
10853 ins_encode( Pop_Mem_Reg_DPR(dst, src) );
10854 ins_pipe( fpu_mem_reg );
10855 %}
10856
10857 // Force rounding to 24-bit precision and 6-bit exponent
10858 instruct convDPR2FPR_reg(stackSlotF dst, regDPR src) %{
10859 predicate(UseSSE==0);
10860 match(Set dst (ConvD2F src));
10861 format %{ "FST_S $dst,$src\t# F-round" %}
10862 expand %{
10863 roundFloat_mem_reg(dst,src);
10864 %}
10865 %}
10866
10867 // Force rounding to 24-bit precision and 6-bit exponent
10868 instruct convDPR2F_reg(regF dst, regDPR src, eFlagsReg cr) %{
10869 predicate(UseSSE==1);
10870 match(Set dst (ConvD2F src));
10871 effect( KILL cr );
10872 format %{ "SUB ESP,4\n\t"
10873 "FST_S [ESP],$src\t# F-round\n\t"
10874 "MOVSS $dst,[ESP]\n\t"
10875 "ADD ESP,4" %}
10876 ins_encode %{
10877 __ subptr(rsp, 4);
10878 if ($src$$reg != FPR1L_enc) {
10879 __ fld_s($src$$reg-1);
10880 __ fstp_s(Address(rsp, 0));
10881 } else {
10882 __ fst_s(Address(rsp, 0));
10883 }
10884 __ movflt($dst$$XMMRegister, Address(rsp, 0));
10885 __ addptr(rsp, 4);
10886 %}
10887 ins_pipe( pipe_slow );
10888 %}
10889
10890 // Force rounding double precision to single precision
10891 instruct convD2F_reg(regF dst, regD src) %{
10892 predicate(UseSSE>=2);
10893 match(Set dst (ConvD2F src));
10894 format %{ "CVTSD2SS $dst,$src\t# F-round" %}
10895 ins_encode %{
10896 __ cvtsd2ss ($dst$$XMMRegister, $src$$XMMRegister);
10897 %}
10898 ins_pipe( pipe_slow );
10899 %}
10900
10901 instruct convFPR2DPR_reg_reg(regDPR dst, regFPR src) %{
10902 predicate(UseSSE==0);
10903 match(Set dst (ConvF2D src));
10904 format %{ "FST_S $dst,$src\t# D-round" %}
10905 ins_encode( Pop_Reg_Reg_DPR(dst, src));
10906 ins_pipe( fpu_reg_reg );
10907 %}
10908
10909 instruct convFPR2D_reg(stackSlotD dst, regFPR src) %{
10910 predicate(UseSSE==1);
10911 match(Set dst (ConvF2D src));
10912 format %{ "FST_D $dst,$src\t# D-round" %}
10913 expand %{
10914 roundDouble_mem_reg(dst,src);
10915 %}
10916 %}
10917
10918 instruct convF2DPR_reg(regDPR dst, regF src, eFlagsReg cr) %{
10919 predicate(UseSSE==1);
10920 match(Set dst (ConvF2D src));
10921 effect( KILL cr );
10922 format %{ "SUB ESP,4\n\t"
10923 "MOVSS [ESP] $src\n\t"
10924 "FLD_S [ESP]\n\t"
10925 "ADD ESP,4\n\t"
10926 "FSTP $dst\t# D-round" %}
10927 ins_encode %{
10928 __ subptr(rsp, 4);
10929 __ movflt(Address(rsp, 0), $src$$XMMRegister);
10930 __ fld_s(Address(rsp, 0));
10931 __ addptr(rsp, 4);
10932 __ fstp_d($dst$$reg);
10933 %}
10934 ins_pipe( pipe_slow );
10935 %}
10936
10937 instruct convF2D_reg(regD dst, regF src) %{
10938 predicate(UseSSE>=2);
10939 match(Set dst (ConvF2D src));
10940 format %{ "CVTSS2SD $dst,$src\t# D-round" %}
10941 ins_encode %{
10942 __ cvtss2sd ($dst$$XMMRegister, $src$$XMMRegister);
10943 %}
10944 ins_pipe( pipe_slow );
10945 %}
10946
10947 // Convert a double to an int. If the double is a NAN, stuff a zero in instead.
10948 instruct convDPR2I_reg_reg( eAXRegI dst, eDXRegI tmp, regDPR src, eFlagsReg cr ) %{
10949 predicate(UseSSE<=1);
10950 match(Set dst (ConvD2I src));
10951 effect( KILL tmp, KILL cr );
10952 format %{ "FLD $src\t# Convert double to int \n\t"
10953 "FLDCW trunc mode\n\t"
10954 "SUB ESP,4\n\t"
10955 "FISTp [ESP + #0]\n\t"
10956 "FLDCW std/24-bit mode\n\t"
10957 "POP EAX\n\t"
10958 "CMP EAX,0x80000000\n\t"
10959 "JNE,s fast\n\t"
10960 "FLD_D $src\n\t"
10961 "CALL d2i_wrapper\n"
10962 "fast:" %}
10963 ins_encode( Push_Reg_DPR(src), DPR2I_encoding(src) );
10964 ins_pipe( pipe_slow );
10965 %}
10966
10967 // Convert a double to an int. If the double is a NAN, stuff a zero in instead.
10968 instruct convD2I_reg_reg( eAXRegI dst, eDXRegI tmp, regD src, eFlagsReg cr ) %{
10969 predicate(UseSSE>=2);
10970 match(Set dst (ConvD2I src));
10971 effect( KILL tmp, KILL cr );
10972 format %{ "CVTTSD2SI $dst, $src\n\t"
10973 "CMP $dst,0x80000000\n\t"
10974 "JNE,s fast\n\t"
10975 "SUB ESP, 8\n\t"
10976 "MOVSD [ESP], $src\n\t"
10977 "FLD_D [ESP]\n\t"
10978 "ADD ESP, 8\n\t"
10979 "CALL d2i_wrapper\n"
10980 "fast:" %}
10981 ins_encode %{
10982 Label fast;
10983 __ cvttsd2sil($dst$$Register, $src$$XMMRegister);
10984 __ cmpl($dst$$Register, 0x80000000);
10985 __ jccb(Assembler::notEqual, fast);
10986 __ subptr(rsp, 8);
10987 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
10988 __ fld_d(Address(rsp, 0));
10989 __ addptr(rsp, 8);
10990 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::d2i_wrapper())));
10991 __ bind(fast);
10992 %}
10993 ins_pipe( pipe_slow );
10994 %}
10995
10996 instruct convDPR2L_reg_reg( eADXRegL dst, regDPR src, eFlagsReg cr ) %{
10997 predicate(UseSSE<=1);
10998 match(Set dst (ConvD2L src));
10999 effect( KILL cr );
11000 format %{ "FLD $src\t# Convert double to long\n\t"
11001 "FLDCW trunc mode\n\t"
11002 "SUB ESP,8\n\t"
11003 "FISTp [ESP + #0]\n\t"
11004 "FLDCW std/24-bit mode\n\t"
11005 "POP EAX\n\t"
11006 "POP EDX\n\t"
11007 "CMP EDX,0x80000000\n\t"
11008 "JNE,s fast\n\t"
11009 "TEST EAX,EAX\n\t"
11010 "JNE,s fast\n\t"
11011 "FLD $src\n\t"
11012 "CALL d2l_wrapper\n"
11013 "fast:" %}
11014 ins_encode( Push_Reg_DPR(src), DPR2L_encoding(src) );
11015 ins_pipe( pipe_slow );
11016 %}
11017
11018 // XMM lacks a float/double->long conversion, so use the old FPU stack.
11019 instruct convD2L_reg_reg( eADXRegL dst, regD src, eFlagsReg cr ) %{
11020 predicate (UseSSE>=2);
11021 match(Set dst (ConvD2L src));
11022 effect( KILL cr );
11023 format %{ "SUB ESP,8\t# Convert double to long\n\t"
11024 "MOVSD [ESP],$src\n\t"
11025 "FLD_D [ESP]\n\t"
11026 "FLDCW trunc mode\n\t"
11027 "FISTp [ESP + #0]\n\t"
11028 "FLDCW std/24-bit mode\n\t"
11029 "POP EAX\n\t"
11030 "POP EDX\n\t"
11031 "CMP EDX,0x80000000\n\t"
11032 "JNE,s fast\n\t"
11033 "TEST EAX,EAX\n\t"
11034 "JNE,s fast\n\t"
11035 "SUB ESP,8\n\t"
11036 "MOVSD [ESP],$src\n\t"
11037 "FLD_D [ESP]\n\t"
11038 "ADD ESP,8\n\t"
11039 "CALL d2l_wrapper\n"
11040 "fast:" %}
11041 ins_encode %{
11042 Label fast;
11043 __ subptr(rsp, 8);
11044 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
11045 __ fld_d(Address(rsp, 0));
11046 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_trunc()));
11047 __ fistp_d(Address(rsp, 0));
11048 // Restore the rounding mode, mask the exception
11049 if (Compile::current()->in_24_bit_fp_mode()) {
11050 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
11051 } else {
11052 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
11053 }
11054 // Load the converted long, adjust CPU stack
11055 __ pop(rax);
11056 __ pop(rdx);
11057 __ cmpl(rdx, 0x80000000);
11058 __ jccb(Assembler::notEqual, fast);
11059 __ testl(rax, rax);
11060 __ jccb(Assembler::notEqual, fast);
11061 __ subptr(rsp, 8);
11062 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
11063 __ fld_d(Address(rsp, 0));
11064 __ addptr(rsp, 8);
11065 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::d2l_wrapper())));
11066 __ bind(fast);
11067 %}
11068 ins_pipe( pipe_slow );
11069 %}
11070
11071 // Convert a double to an int. Java semantics require we do complex
11072 // manglations in the corner cases. So we set the rounding mode to
11073 // 'zero', store the darned double down as an int, and reset the
11074 // rounding mode to 'nearest'. The hardware stores a flag value down
11075 // if we would overflow or converted a NAN; we check for this and
11076 // and go the slow path if needed.
11077 instruct convFPR2I_reg_reg(eAXRegI dst, eDXRegI tmp, regFPR src, eFlagsReg cr ) %{
11078 predicate(UseSSE==0);
11079 match(Set dst (ConvF2I src));
11080 effect( KILL tmp, KILL cr );
11081 format %{ "FLD $src\t# Convert float to int \n\t"
11082 "FLDCW trunc mode\n\t"
11083 "SUB ESP,4\n\t"
11084 "FISTp [ESP + #0]\n\t"
11085 "FLDCW std/24-bit mode\n\t"
11086 "POP EAX\n\t"
11087 "CMP EAX,0x80000000\n\t"
11088 "JNE,s fast\n\t"
11089 "FLD $src\n\t"
11090 "CALL d2i_wrapper\n"
11091 "fast:" %}
11092 // DPR2I_encoding works for FPR2I
11093 ins_encode( Push_Reg_FPR(src), DPR2I_encoding(src) );
11094 ins_pipe( pipe_slow );
11095 %}
11096
11097 // Convert a float in xmm to an int reg.
11098 instruct convF2I_reg(eAXRegI dst, eDXRegI tmp, regF src, eFlagsReg cr ) %{
11099 predicate(UseSSE>=1);
11100 match(Set dst (ConvF2I src));
11101 effect( KILL tmp, KILL cr );
11102 format %{ "CVTTSS2SI $dst, $src\n\t"
11103 "CMP $dst,0x80000000\n\t"
11104 "JNE,s fast\n\t"
11105 "SUB ESP, 4\n\t"
11106 "MOVSS [ESP], $src\n\t"
11107 "FLD [ESP]\n\t"
11108 "ADD ESP, 4\n\t"
11109 "CALL d2i_wrapper\n"
11110 "fast:" %}
11111 ins_encode %{
11112 Label fast;
11113 __ cvttss2sil($dst$$Register, $src$$XMMRegister);
11114 __ cmpl($dst$$Register, 0x80000000);
11115 __ jccb(Assembler::notEqual, fast);
11116 __ subptr(rsp, 4);
11117 __ movflt(Address(rsp, 0), $src$$XMMRegister);
11118 __ fld_s(Address(rsp, 0));
11119 __ addptr(rsp, 4);
11120 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::d2i_wrapper())));
11121 __ bind(fast);
11122 %}
11123 ins_pipe( pipe_slow );
11124 %}
11125
11126 instruct convFPR2L_reg_reg( eADXRegL dst, regFPR src, eFlagsReg cr ) %{
11127 predicate(UseSSE==0);
11128 match(Set dst (ConvF2L src));
11129 effect( KILL cr );
11130 format %{ "FLD $src\t# Convert float to long\n\t"
11131 "FLDCW trunc mode\n\t"
11132 "SUB ESP,8\n\t"
11133 "FISTp [ESP + #0]\n\t"
11134 "FLDCW std/24-bit mode\n\t"
11135 "POP EAX\n\t"
11136 "POP EDX\n\t"
11137 "CMP EDX,0x80000000\n\t"
11138 "JNE,s fast\n\t"
11139 "TEST EAX,EAX\n\t"
11140 "JNE,s fast\n\t"
11141 "FLD $src\n\t"
11142 "CALL d2l_wrapper\n"
11143 "fast:" %}
11144 // DPR2L_encoding works for FPR2L
11145 ins_encode( Push_Reg_FPR(src), DPR2L_encoding(src) );
11146 ins_pipe( pipe_slow );
11147 %}
11148
11149 // XMM lacks a float/double->long conversion, so use the old FPU stack.
11150 instruct convF2L_reg_reg( eADXRegL dst, regF src, eFlagsReg cr ) %{
11151 predicate (UseSSE>=1);
11152 match(Set dst (ConvF2L src));
11153 effect( KILL cr );
11154 format %{ "SUB ESP,8\t# Convert float to long\n\t"
11155 "MOVSS [ESP],$src\n\t"
11156 "FLD_S [ESP]\n\t"
11157 "FLDCW trunc mode\n\t"
11158 "FISTp [ESP + #0]\n\t"
11159 "FLDCW std/24-bit mode\n\t"
11160 "POP EAX\n\t"
11161 "POP EDX\n\t"
11162 "CMP EDX,0x80000000\n\t"
11163 "JNE,s fast\n\t"
11164 "TEST EAX,EAX\n\t"
11165 "JNE,s fast\n\t"
11166 "SUB ESP,4\t# Convert float to long\n\t"
11167 "MOVSS [ESP],$src\n\t"
11168 "FLD_S [ESP]\n\t"
11169 "ADD ESP,4\n\t"
11170 "CALL d2l_wrapper\n"
11171 "fast:" %}
11172 ins_encode %{
11173 Label fast;
11174 __ subptr(rsp, 8);
11175 __ movflt(Address(rsp, 0), $src$$XMMRegister);
11176 __ fld_s(Address(rsp, 0));
11177 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_trunc()));
11178 __ fistp_d(Address(rsp, 0));
11179 // Restore the rounding mode, mask the exception
11180 if (Compile::current()->in_24_bit_fp_mode()) {
11181 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
11182 } else {
11183 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
11184 }
11185 // Load the converted long, adjust CPU stack
11186 __ pop(rax);
11187 __ pop(rdx);
11188 __ cmpl(rdx, 0x80000000);
11189 __ jccb(Assembler::notEqual, fast);
11190 __ testl(rax, rax);
11191 __ jccb(Assembler::notEqual, fast);
11192 __ subptr(rsp, 4);
11193 __ movflt(Address(rsp, 0), $src$$XMMRegister);
11194 __ fld_s(Address(rsp, 0));
11195 __ addptr(rsp, 4);
11196 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::d2l_wrapper())));
11197 __ bind(fast);
11198 %}
11199 ins_pipe( pipe_slow );
11200 %}
11201
11202 instruct convI2DPR_reg(regDPR dst, stackSlotI src) %{
11203 predicate( UseSSE<=1 );
11204 match(Set dst (ConvI2D src));
11205 format %{ "FILD $src\n\t"
11206 "FSTP $dst" %}
11207 opcode(0xDB, 0x0); /* DB /0 */
11208 ins_encode(Push_Mem_I(src), Pop_Reg_DPR(dst));
11209 ins_pipe( fpu_reg_mem );
11210 %}
11211
11212 instruct convI2D_reg(regD dst, rRegI src) %{
11213 predicate( UseSSE>=2 && !UseXmmI2D );
11214 match(Set dst (ConvI2D src));
11215 format %{ "CVTSI2SD $dst,$src" %}
11216 ins_encode %{
11217 __ cvtsi2sdl ($dst$$XMMRegister, $src$$Register);
11218 %}
11219 ins_pipe( pipe_slow );
11220 %}
11221
11222 instruct convI2D_mem(regD dst, memory mem) %{
11223 predicate( UseSSE>=2 );
11224 match(Set dst (ConvI2D (LoadI mem)));
11225 format %{ "CVTSI2SD $dst,$mem" %}
11226 ins_encode %{
11227 __ cvtsi2sdl ($dst$$XMMRegister, $mem$$Address);
11228 %}
11229 ins_pipe( pipe_slow );
11230 %}
11231
11232 instruct convXI2D_reg(regD dst, rRegI src)
11233 %{
11234 predicate( UseSSE>=2 && UseXmmI2D );
11235 match(Set dst (ConvI2D src));
11236
11237 format %{ "MOVD $dst,$src\n\t"
11238 "CVTDQ2PD $dst,$dst\t# i2d" %}
11239 ins_encode %{
11240 __ movdl($dst$$XMMRegister, $src$$Register);
11241 __ cvtdq2pd($dst$$XMMRegister, $dst$$XMMRegister);
11242 %}
11243 ins_pipe(pipe_slow); // XXX
11244 %}
11245
11246 instruct convI2DPR_mem(regDPR dst, memory mem) %{
11247 predicate( UseSSE<=1 && !Compile::current()->select_24_bit_instr());
11248 match(Set dst (ConvI2D (LoadI mem)));
11249 format %{ "FILD $mem\n\t"
11250 "FSTP $dst" %}
11251 opcode(0xDB); /* DB /0 */
11252 ins_encode( OpcP, RMopc_Mem(0x00,mem),
11253 Pop_Reg_DPR(dst));
11254 ins_pipe( fpu_reg_mem );
11255 %}
11256
11257 // Convert a byte to a float; no rounding step needed.
11258 instruct conv24I2FPR_reg(regFPR dst, stackSlotI src) %{
11259 predicate( UseSSE==0 && n->in(1)->Opcode() == Op_AndI && n->in(1)->in(2)->is_Con() && n->in(1)->in(2)->get_int() == 255 );
11260 match(Set dst (ConvI2F src));
11261 format %{ "FILD $src\n\t"
11262 "FSTP $dst" %}
11263
11264 opcode(0xDB, 0x0); /* DB /0 */
11265 ins_encode(Push_Mem_I(src), Pop_Reg_FPR(dst));
11266 ins_pipe( fpu_reg_mem );
11267 %}
11268
11269 // In 24-bit mode, force exponent rounding by storing back out
11270 instruct convI2FPR_SSF(stackSlotF dst, stackSlotI src) %{
11271 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr());
11272 match(Set dst (ConvI2F src));
11273 ins_cost(200);
11274 format %{ "FILD $src\n\t"
11275 "FSTP_S $dst" %}
11276 opcode(0xDB, 0x0); /* DB /0 */
11277 ins_encode( Push_Mem_I(src),
11278 Pop_Mem_FPR(dst));
11279 ins_pipe( fpu_mem_mem );
11280 %}
11281
11282 // In 24-bit mode, force exponent rounding by storing back out
11283 instruct convI2FPR_SSF_mem(stackSlotF dst, memory mem) %{
11284 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr());
11285 match(Set dst (ConvI2F (LoadI mem)));
11286 ins_cost(200);
11287 format %{ "FILD $mem\n\t"
11288 "FSTP_S $dst" %}
11289 opcode(0xDB); /* DB /0 */
11290 ins_encode( OpcP, RMopc_Mem(0x00,mem),
11291 Pop_Mem_FPR(dst));
11292 ins_pipe( fpu_mem_mem );
11293 %}
11294
11295 // This instruction does not round to 24-bits
11296 instruct convI2FPR_reg(regFPR dst, stackSlotI src) %{
11297 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr());
11298 match(Set dst (ConvI2F src));
11299 format %{ "FILD $src\n\t"
11300 "FSTP $dst" %}
11301 opcode(0xDB, 0x0); /* DB /0 */
11302 ins_encode( Push_Mem_I(src),
11303 Pop_Reg_FPR(dst));
11304 ins_pipe( fpu_reg_mem );
11305 %}
11306
11307 // This instruction does not round to 24-bits
11308 instruct convI2FPR_mem(regFPR dst, memory mem) %{
11309 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr());
11310 match(Set dst (ConvI2F (LoadI mem)));
11311 format %{ "FILD $mem\n\t"
11312 "FSTP $dst" %}
11313 opcode(0xDB); /* DB /0 */
11314 ins_encode( OpcP, RMopc_Mem(0x00,mem),
11315 Pop_Reg_FPR(dst));
11316 ins_pipe( fpu_reg_mem );
11317 %}
11318
11319 // Convert an int to a float in xmm; no rounding step needed.
11320 instruct convI2F_reg(regF dst, rRegI src) %{
11321 predicate( UseSSE==1 || UseSSE>=2 && !UseXmmI2F );
11322 match(Set dst (ConvI2F src));
11323 format %{ "CVTSI2SS $dst, $src" %}
11324 ins_encode %{
11325 __ cvtsi2ssl ($dst$$XMMRegister, $src$$Register);
11326 %}
11327 ins_pipe( pipe_slow );
11328 %}
11329
11330 instruct convXI2F_reg(regF dst, rRegI src)
11331 %{
11332 predicate( UseSSE>=2 && UseXmmI2F );
11333 match(Set dst (ConvI2F src));
11334
11335 format %{ "MOVD $dst,$src\n\t"
11336 "CVTDQ2PS $dst,$dst\t# i2f" %}
11337 ins_encode %{
11338 __ movdl($dst$$XMMRegister, $src$$Register);
11339 __ cvtdq2ps($dst$$XMMRegister, $dst$$XMMRegister);
11340 %}
11341 ins_pipe(pipe_slow); // XXX
11342 %}
11343
11344 instruct convI2L_reg( eRegL dst, rRegI src, eFlagsReg cr) %{
11345 match(Set dst (ConvI2L src));
11346 effect(KILL cr);
11347 ins_cost(375);
11348 format %{ "MOV $dst.lo,$src\n\t"
11349 "MOV $dst.hi,$src\n\t"
11350 "SAR $dst.hi,31" %}
11351 ins_encode(convert_int_long(dst,src));
11352 ins_pipe( ialu_reg_reg_long );
11353 %}
11354
11355 // Zero-extend convert int to long
11356 instruct convI2L_reg_zex(eRegL dst, rRegI src, immL_32bits mask, eFlagsReg flags ) %{
11357 match(Set dst (AndL (ConvI2L src) mask) );
11358 effect( KILL flags );
11359 ins_cost(250);
11360 format %{ "MOV $dst.lo,$src\n\t"
11361 "XOR $dst.hi,$dst.hi" %}
11362 opcode(0x33); // XOR
11363 ins_encode(enc_Copy(dst,src), OpcP, RegReg_Hi2(dst,dst) );
11364 ins_pipe( ialu_reg_reg_long );
11365 %}
11366
11367 // Zero-extend long
11368 instruct zerox_long(eRegL dst, eRegL src, immL_32bits mask, eFlagsReg flags ) %{
11369 match(Set dst (AndL src mask) );
11370 effect( KILL flags );
11371 ins_cost(250);
11372 format %{ "MOV $dst.lo,$src.lo\n\t"
11373 "XOR $dst.hi,$dst.hi\n\t" %}
11374 opcode(0x33); // XOR
11375 ins_encode(enc_Copy(dst,src), OpcP, RegReg_Hi2(dst,dst) );
11376 ins_pipe( ialu_reg_reg_long );
11377 %}
11378
11379 instruct convL2DPR_reg( stackSlotD dst, eRegL src, eFlagsReg cr) %{
11380 predicate (UseSSE<=1);
11381 match(Set dst (ConvL2D src));
11382 effect( KILL cr );
11383 format %{ "PUSH $src.hi\t# Convert long to double\n\t"
11384 "PUSH $src.lo\n\t"
11385 "FILD ST,[ESP + #0]\n\t"
11386 "ADD ESP,8\n\t"
11387 "FSTP_D $dst\t# D-round" %}
11388 opcode(0xDF, 0x5); /* DF /5 */
11389 ins_encode(convert_long_double(src), Pop_Mem_DPR(dst));
11390 ins_pipe( pipe_slow );
11391 %}
11392
11393 instruct convL2D_reg( regD dst, eRegL src, eFlagsReg cr) %{
11394 predicate (UseSSE>=2);
11395 match(Set dst (ConvL2D src));
11396 effect( KILL cr );
11397 format %{ "PUSH $src.hi\t# Convert long to double\n\t"
11398 "PUSH $src.lo\n\t"
11399 "FILD_D [ESP]\n\t"
11400 "FSTP_D [ESP]\n\t"
11401 "MOVSD $dst,[ESP]\n\t"
11402 "ADD ESP,8" %}
11403 opcode(0xDF, 0x5); /* DF /5 */
11404 ins_encode(convert_long_double2(src), Push_ResultD(dst));
11405 ins_pipe( pipe_slow );
11406 %}
11407
11408 instruct convL2F_reg( regF dst, eRegL src, eFlagsReg cr) %{
11409 predicate (UseSSE>=1);
11410 match(Set dst (ConvL2F src));
11411 effect( KILL cr );
11412 format %{ "PUSH $src.hi\t# Convert long to single float\n\t"
11413 "PUSH $src.lo\n\t"
11414 "FILD_D [ESP]\n\t"
11415 "FSTP_S [ESP]\n\t"
11416 "MOVSS $dst,[ESP]\n\t"
11417 "ADD ESP,8" %}
11418 opcode(0xDF, 0x5); /* DF /5 */
11419 ins_encode(convert_long_double2(src), Push_ResultF(dst,0x8));
11420 ins_pipe( pipe_slow );
11421 %}
11422
11423 instruct convL2FPR_reg( stackSlotF dst, eRegL src, eFlagsReg cr) %{
11424 match(Set dst (ConvL2F src));
11425 effect( KILL cr );
11426 format %{ "PUSH $src.hi\t# Convert long to single float\n\t"
11427 "PUSH $src.lo\n\t"
11428 "FILD ST,[ESP + #0]\n\t"
11429 "ADD ESP,8\n\t"
11430 "FSTP_S $dst\t# F-round" %}
11431 opcode(0xDF, 0x5); /* DF /5 */
11432 ins_encode(convert_long_double(src), Pop_Mem_FPR(dst));
11433 ins_pipe( pipe_slow );
11434 %}
11435
11436 instruct convL2I_reg( rRegI dst, eRegL src ) %{
11437 match(Set dst (ConvL2I src));
11438 effect( DEF dst, USE src );
11439 format %{ "MOV $dst,$src.lo" %}
11440 ins_encode(enc_CopyL_Lo(dst,src));
11441 ins_pipe( ialu_reg_reg );
11442 %}
11443
11444
11445 instruct MoveF2I_stack_reg(rRegI dst, stackSlotF src) %{
11446 match(Set dst (MoveF2I src));
11447 effect( DEF dst, USE src );
11448 ins_cost(100);
11449 format %{ "MOV $dst,$src\t# MoveF2I_stack_reg" %}
11450 ins_encode %{
11451 __ movl($dst$$Register, Address(rsp, $src$$disp));
11452 %}
11453 ins_pipe( ialu_reg_mem );
11454 %}
11455
11456 instruct MoveFPR2I_reg_stack(stackSlotI dst, regFPR src) %{
11457 predicate(UseSSE==0);
11458 match(Set dst (MoveF2I src));
11459 effect( DEF dst, USE src );
11460
11461 ins_cost(125);
11462 format %{ "FST_S $dst,$src\t# MoveF2I_reg_stack" %}
11463 ins_encode( Pop_Mem_Reg_FPR(dst, src) );
11464 ins_pipe( fpu_mem_reg );
11465 %}
11466
11467 instruct MoveF2I_reg_stack_sse(stackSlotI dst, regF src) %{
11468 predicate(UseSSE>=1);
11469 match(Set dst (MoveF2I src));
11470 effect( DEF dst, USE src );
11471
11472 ins_cost(95);
11473 format %{ "MOVSS $dst,$src\t# MoveF2I_reg_stack_sse" %}
11474 ins_encode %{
11475 __ movflt(Address(rsp, $dst$$disp), $src$$XMMRegister);
11476 %}
11477 ins_pipe( pipe_slow );
11478 %}
11479
11480 instruct MoveF2I_reg_reg_sse(rRegI dst, regF src) %{
11481 predicate(UseSSE>=2);
11482 match(Set dst (MoveF2I src));
11483 effect( DEF dst, USE src );
11484 ins_cost(85);
11485 format %{ "MOVD $dst,$src\t# MoveF2I_reg_reg_sse" %}
11486 ins_encode %{
11487 __ movdl($dst$$Register, $src$$XMMRegister);
11488 %}
11489 ins_pipe( pipe_slow );
11490 %}
11491
11492 instruct MoveI2F_reg_stack(stackSlotF dst, rRegI src) %{
11493 match(Set dst (MoveI2F src));
11494 effect( DEF dst, USE src );
11495
11496 ins_cost(100);
11497 format %{ "MOV $dst,$src\t# MoveI2F_reg_stack" %}
11498 ins_encode %{
11499 __ movl(Address(rsp, $dst$$disp), $src$$Register);
11500 %}
11501 ins_pipe( ialu_mem_reg );
11502 %}
11503
11504
11505 instruct MoveI2FPR_stack_reg(regFPR dst, stackSlotI src) %{
11506 predicate(UseSSE==0);
11507 match(Set dst (MoveI2F src));
11508 effect(DEF dst, USE src);
11509
11510 ins_cost(125);
11511 format %{ "FLD_S $src\n\t"
11512 "FSTP $dst\t# MoveI2F_stack_reg" %}
11513 opcode(0xD9); /* D9 /0, FLD m32real */
11514 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
11515 Pop_Reg_FPR(dst) );
11516 ins_pipe( fpu_reg_mem );
11517 %}
11518
11519 instruct MoveI2F_stack_reg_sse(regF dst, stackSlotI src) %{
11520 predicate(UseSSE>=1);
11521 match(Set dst (MoveI2F src));
11522 effect( DEF dst, USE src );
11523
11524 ins_cost(95);
11525 format %{ "MOVSS $dst,$src\t# MoveI2F_stack_reg_sse" %}
11526 ins_encode %{
11527 __ movflt($dst$$XMMRegister, Address(rsp, $src$$disp));
11528 %}
11529 ins_pipe( pipe_slow );
11530 %}
11531
11532 instruct MoveI2F_reg_reg_sse(regF dst, rRegI src) %{
11533 predicate(UseSSE>=2);
11534 match(Set dst (MoveI2F src));
11535 effect( DEF dst, USE src );
11536
11537 ins_cost(85);
11538 format %{ "MOVD $dst,$src\t# MoveI2F_reg_reg_sse" %}
11539 ins_encode %{
11540 __ movdl($dst$$XMMRegister, $src$$Register);
11541 %}
11542 ins_pipe( pipe_slow );
11543 %}
11544
11545 instruct MoveD2L_stack_reg(eRegL dst, stackSlotD src) %{
11546 match(Set dst (MoveD2L src));
11547 effect(DEF dst, USE src);
11548
11549 ins_cost(250);
11550 format %{ "MOV $dst.lo,$src\n\t"
11551 "MOV $dst.hi,$src+4\t# MoveD2L_stack_reg" %}
11552 opcode(0x8B, 0x8B);
11553 ins_encode( OpcP, RegMem(dst,src), OpcS, RegMem_Hi(dst,src));
11554 ins_pipe( ialu_mem_long_reg );
11555 %}
11556
11557 instruct MoveDPR2L_reg_stack(stackSlotL dst, regDPR src) %{
11558 predicate(UseSSE<=1);
11559 match(Set dst (MoveD2L src));
11560 effect(DEF dst, USE src);
11561
11562 ins_cost(125);
11563 format %{ "FST_D $dst,$src\t# MoveD2L_reg_stack" %}
11564 ins_encode( Pop_Mem_Reg_DPR(dst, src) );
11565 ins_pipe( fpu_mem_reg );
11566 %}
11567
11568 instruct MoveD2L_reg_stack_sse(stackSlotL dst, regD src) %{
11569 predicate(UseSSE>=2);
11570 match(Set dst (MoveD2L src));
11571 effect(DEF dst, USE src);
11572 ins_cost(95);
11573 format %{ "MOVSD $dst,$src\t# MoveD2L_reg_stack_sse" %}
11574 ins_encode %{
11575 __ movdbl(Address(rsp, $dst$$disp), $src$$XMMRegister);
11576 %}
11577 ins_pipe( pipe_slow );
11578 %}
11579
11580 instruct MoveD2L_reg_reg_sse(eRegL dst, regD src, regD tmp) %{
11581 predicate(UseSSE>=2);
11582 match(Set dst (MoveD2L src));
11583 effect(DEF dst, USE src, TEMP tmp);
11584 ins_cost(85);
11585 format %{ "MOVD $dst.lo,$src\n\t"
11586 "PSHUFLW $tmp,$src,0x4E\n\t"
11587 "MOVD $dst.hi,$tmp\t# MoveD2L_reg_reg_sse" %}
11588 ins_encode %{
11589 __ movdl($dst$$Register, $src$$XMMRegister);
11590 __ pshuflw($tmp$$XMMRegister, $src$$XMMRegister, 0x4e);
11591 __ movdl(HIGH_FROM_LOW($dst$$Register), $tmp$$XMMRegister);
11592 %}
11593 ins_pipe( pipe_slow );
11594 %}
11595
11596 instruct MoveL2D_reg_stack(stackSlotD dst, eRegL src) %{
11597 match(Set dst (MoveL2D src));
11598 effect(DEF dst, USE src);
11599
11600 ins_cost(200);
11601 format %{ "MOV $dst,$src.lo\n\t"
11602 "MOV $dst+4,$src.hi\t# MoveL2D_reg_stack" %}
11603 opcode(0x89, 0x89);
11604 ins_encode( OpcP, RegMem( src, dst ), OpcS, RegMem_Hi( src, dst ) );
11605 ins_pipe( ialu_mem_long_reg );
11606 %}
11607
11608
11609 instruct MoveL2DPR_stack_reg(regDPR dst, stackSlotL src) %{
11610 predicate(UseSSE<=1);
11611 match(Set dst (MoveL2D src));
11612 effect(DEF dst, USE src);
11613 ins_cost(125);
11614
11615 format %{ "FLD_D $src\n\t"
11616 "FSTP $dst\t# MoveL2D_stack_reg" %}
11617 opcode(0xDD); /* DD /0, FLD m64real */
11618 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src),
11619 Pop_Reg_DPR(dst) );
11620 ins_pipe( fpu_reg_mem );
11621 %}
11622
11623
11624 instruct MoveL2D_stack_reg_sse(regD dst, stackSlotL src) %{
11625 predicate(UseSSE>=2 && UseXmmLoadAndClearUpper);
11626 match(Set dst (MoveL2D src));
11627 effect(DEF dst, USE src);
11628
11629 ins_cost(95);
11630 format %{ "MOVSD $dst,$src\t# MoveL2D_stack_reg_sse" %}
11631 ins_encode %{
11632 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
11633 %}
11634 ins_pipe( pipe_slow );
11635 %}
11636
11637 instruct MoveL2D_stack_reg_sse_partial(regD dst, stackSlotL src) %{
11638 predicate(UseSSE>=2 && !UseXmmLoadAndClearUpper);
11639 match(Set dst (MoveL2D src));
11640 effect(DEF dst, USE src);
11641
11642 ins_cost(95);
11643 format %{ "MOVLPD $dst,$src\t# MoveL2D_stack_reg_sse" %}
11644 ins_encode %{
11645 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
11646 %}
11647 ins_pipe( pipe_slow );
11648 %}
11649
11650 instruct MoveL2D_reg_reg_sse(regD dst, eRegL src, regD tmp) %{
11651 predicate(UseSSE>=2);
11652 match(Set dst (MoveL2D src));
11653 effect(TEMP dst, USE src, TEMP tmp);
11654 ins_cost(85);
11655 format %{ "MOVD $dst,$src.lo\n\t"
11656 "MOVD $tmp,$src.hi\n\t"
11657 "PUNPCKLDQ $dst,$tmp\t# MoveL2D_reg_reg_sse" %}
11658 ins_encode %{
11659 __ movdl($dst$$XMMRegister, $src$$Register);
11660 __ movdl($tmp$$XMMRegister, HIGH_FROM_LOW($src$$Register));
11661 __ punpckldq($dst$$XMMRegister, $tmp$$XMMRegister);
11662 %}
11663 ins_pipe( pipe_slow );
11664 %}
11665
11666
11667 // =======================================================================
11668 // fast clearing of an array
11669 instruct rep_stos(eCXRegI cnt, eDIRegP base, eAXRegI zero, Universe dummy, eFlagsReg cr) %{
11670 predicate(!UseFastStosb);
11671 match(Set dummy (ClearArray cnt base));
11672 effect(USE_KILL cnt, USE_KILL base, KILL zero, KILL cr);
11673 format %{ "XOR EAX,EAX\t# ClearArray:\n\t"
11674 "SHL ECX,1\t# Convert doublewords to words\n\t"
11675 "REP STOS\t# store EAX into [EDI++] while ECX--" %}
11676 ins_encode %{
11677 __ clear_mem($base$$Register, $cnt$$Register, $zero$$Register);
11678 %}
11679 ins_pipe( pipe_slow );
11680 %}
11681
11682 instruct rep_fast_stosb(eCXRegI cnt, eDIRegP base, eAXRegI zero, Universe dummy, eFlagsReg cr) %{
11683 predicate(UseFastStosb);
11684 match(Set dummy (ClearArray cnt base));
11685 effect(USE_KILL cnt, USE_KILL base, KILL zero, KILL cr);
11686 format %{ "XOR EAX,EAX\t# ClearArray:\n\t"
11687 "SHL ECX,3\t# Convert doublewords to bytes\n\t"
11688 "REP STOSB\t# store EAX into [EDI++] while ECX--" %}
11689 ins_encode %{
11690 __ clear_mem($base$$Register, $cnt$$Register, $zero$$Register);
11691 %}
11692 ins_pipe( pipe_slow );
11693 %}
11694
11695 instruct string_compare(eDIRegP str1, eCXRegI cnt1, eSIRegP str2, eDXRegI cnt2,
11696 eAXRegI result, regD tmp1, eFlagsReg cr) %{
11697 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
11698 effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
11699
11700 format %{ "String Compare $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %}
11701 ins_encode %{
11702 __ string_compare($str1$$Register, $str2$$Register,
11703 $cnt1$$Register, $cnt2$$Register, $result$$Register,
11704 $tmp1$$XMMRegister);
11705 %}
11706 ins_pipe( pipe_slow );
11707 %}
11708
11709 // fast string equals
11710 instruct string_equals(eDIRegP str1, eSIRegP str2, eCXRegI cnt, eAXRegI result,
11711 regD tmp1, regD tmp2, eBXRegI tmp3, eFlagsReg cr) %{
11712 match(Set result (StrEquals (Binary str1 str2) cnt));
11713 effect(TEMP tmp1, TEMP tmp2, USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp3, KILL cr);
11714
11715 format %{ "String Equals $str1,$str2,$cnt -> $result // KILL $tmp1, $tmp2, $tmp3" %}
11716 ins_encode %{
11717 __ char_arrays_equals(false, $str1$$Register, $str2$$Register,
11718 $cnt$$Register, $result$$Register, $tmp3$$Register,
11719 $tmp1$$XMMRegister, $tmp2$$XMMRegister);
11720 %}
11721 ins_pipe( pipe_slow );
11722 %}
11723
11724 // fast search of substring with known size.
11725 instruct string_indexof_con(eDIRegP str1, eDXRegI cnt1, eSIRegP str2, immI int_cnt2,
11726 eBXRegI result, regD vec, eAXRegI cnt2, eCXRegI tmp, eFlagsReg cr) %{
11727 predicate(UseSSE42Intrinsics);
11728 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
11729 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, KILL cnt2, KILL tmp, KILL cr);
11730
11731 format %{ "String IndexOf $str1,$cnt1,$str2,$int_cnt2 -> $result // KILL $vec, $cnt1, $cnt2, $tmp" %}
11732 ins_encode %{
11733 int icnt2 = (int)$int_cnt2$$constant;
11734 if (icnt2 >= 8) {
11735 // IndexOf for constant substrings with size >= 8 elements
11736 // which don't need to be loaded through stack.
11737 __ string_indexofC8($str1$$Register, $str2$$Register,
11738 $cnt1$$Register, $cnt2$$Register,
11739 icnt2, $result$$Register,
11740 $vec$$XMMRegister, $tmp$$Register);
11741 } else {
11742 // Small strings are loaded through stack if they cross page boundary.
11743 __ string_indexof($str1$$Register, $str2$$Register,
11744 $cnt1$$Register, $cnt2$$Register,
11745 icnt2, $result$$Register,
11746 $vec$$XMMRegister, $tmp$$Register);
11747 }
11748 %}
11749 ins_pipe( pipe_slow );
11750 %}
11751
11752 instruct string_indexof(eDIRegP str1, eDXRegI cnt1, eSIRegP str2, eAXRegI cnt2,
11753 eBXRegI result, regD vec, eCXRegI tmp, eFlagsReg cr) %{
11754 predicate(UseSSE42Intrinsics);
11755 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
11756 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL tmp, KILL cr);
11757
11758 format %{ "String IndexOf $str1,$cnt1,$str2,$cnt2 -> $result // KILL all" %}
11759 ins_encode %{
11760 __ string_indexof($str1$$Register, $str2$$Register,
11761 $cnt1$$Register, $cnt2$$Register,
11762 (-1), $result$$Register,
11763 $vec$$XMMRegister, $tmp$$Register);
11764 %}
11765 ins_pipe( pipe_slow );
11766 %}
11767
11768 // fast array equals
11769 instruct array_equals(eDIRegP ary1, eSIRegP ary2, eAXRegI result,
11770 regD tmp1, regD tmp2, eCXRegI tmp3, eBXRegI tmp4, eFlagsReg cr)
11771 %{
11772 match(Set result (AryEq ary1 ary2));
11773 effect(TEMP tmp1, TEMP tmp2, USE_KILL ary1, USE_KILL ary2, KILL tmp3, KILL tmp4, KILL cr);
11774 //ins_cost(300);
11775
11776 format %{ "Array Equals $ary1,$ary2 -> $result // KILL $tmp1, $tmp2, $tmp3, $tmp4" %}
11777 ins_encode %{
11778 __ char_arrays_equals(true, $ary1$$Register, $ary2$$Register,
11779 $tmp3$$Register, $result$$Register, $tmp4$$Register,
11780 $tmp1$$XMMRegister, $tmp2$$XMMRegister);
11781 %}
11782 ins_pipe( pipe_slow );
11783 %}
11784
11785 //----------Control Flow Instructions------------------------------------------
11786 // Signed compare Instructions
11787 instruct compI_eReg(eFlagsReg cr, rRegI op1, rRegI op2) %{
11788 match(Set cr (CmpI op1 op2));
11789 effect( DEF cr, USE op1, USE op2 );
11790 format %{ "CMP $op1,$op2" %}
11791 opcode(0x3B); /* Opcode 3B /r */
11792 ins_encode( OpcP, RegReg( op1, op2) );
11793 ins_pipe( ialu_cr_reg_reg );
11794 %}
11795
11796 instruct compI_eReg_imm(eFlagsReg cr, rRegI op1, immI op2) %{
11797 match(Set cr (CmpI op1 op2));
11798 effect( DEF cr, USE op1 );
11799 format %{ "CMP $op1,$op2" %}
11800 opcode(0x81,0x07); /* Opcode 81 /7 */
11801 // ins_encode( RegImm( op1, op2) ); /* Was CmpImm */
11802 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) );
11803 ins_pipe( ialu_cr_reg_imm );
11804 %}
11805
11806 // Cisc-spilled version of cmpI_eReg
11807 instruct compI_eReg_mem(eFlagsReg cr, rRegI op1, memory op2) %{
11808 match(Set cr (CmpI op1 (LoadI op2)));
11809
11810 format %{ "CMP $op1,$op2" %}
11811 ins_cost(500);
11812 opcode(0x3B); /* Opcode 3B /r */
11813 ins_encode( OpcP, RegMem( op1, op2) );
11814 ins_pipe( ialu_cr_reg_mem );
11815 %}
11816
11817 instruct testI_reg( eFlagsReg cr, rRegI src, immI0 zero ) %{
11818 match(Set cr (CmpI src zero));
11819 effect( DEF cr, USE src );
11820
11821 format %{ "TEST $src,$src" %}
11822 opcode(0x85);
11823 ins_encode( OpcP, RegReg( src, src ) );
11824 ins_pipe( ialu_cr_reg_imm );
11825 %}
11826
11827 instruct testI_reg_imm( eFlagsReg cr, rRegI src, immI con, immI0 zero ) %{
11828 match(Set cr (CmpI (AndI src con) zero));
11829
11830 format %{ "TEST $src,$con" %}
11831 opcode(0xF7,0x00);
11832 ins_encode( OpcP, RegOpc(src), Con32(con) );
11833 ins_pipe( ialu_cr_reg_imm );
11834 %}
11835
11836 instruct testI_reg_mem( eFlagsReg cr, rRegI src, memory mem, immI0 zero ) %{
11837 match(Set cr (CmpI (AndI src mem) zero));
11838
11839 format %{ "TEST $src,$mem" %}
11840 opcode(0x85);
11841 ins_encode( OpcP, RegMem( src, mem ) );
11842 ins_pipe( ialu_cr_reg_mem );
11843 %}
11844
11845 // Unsigned compare Instructions; really, same as signed except they
11846 // produce an eFlagsRegU instead of eFlagsReg.
11847 instruct compU_eReg(eFlagsRegU cr, rRegI op1, rRegI op2) %{
11848 match(Set cr (CmpU op1 op2));
11849
11850 format %{ "CMPu $op1,$op2" %}
11851 opcode(0x3B); /* Opcode 3B /r */
11852 ins_encode( OpcP, RegReg( op1, op2) );
11853 ins_pipe( ialu_cr_reg_reg );
11854 %}
11855
11856 instruct compU_eReg_imm(eFlagsRegU cr, rRegI op1, immI op2) %{
11857 match(Set cr (CmpU op1 op2));
11858
11859 format %{ "CMPu $op1,$op2" %}
11860 opcode(0x81,0x07); /* Opcode 81 /7 */
11861 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) );
11862 ins_pipe( ialu_cr_reg_imm );
11863 %}
11864
11865 // // Cisc-spilled version of cmpU_eReg
11866 instruct compU_eReg_mem(eFlagsRegU cr, rRegI op1, memory op2) %{
11867 match(Set cr (CmpU op1 (LoadI op2)));
11868
11869 format %{ "CMPu $op1,$op2" %}
11870 ins_cost(500);
11871 opcode(0x3B); /* Opcode 3B /r */
11872 ins_encode( OpcP, RegMem( op1, op2) );
11873 ins_pipe( ialu_cr_reg_mem );
11874 %}
11875
11876 // // Cisc-spilled version of cmpU_eReg
11877 //instruct compU_mem_eReg(eFlagsRegU cr, memory op1, rRegI op2) %{
11878 // match(Set cr (CmpU (LoadI op1) op2));
11879 //
11880 // format %{ "CMPu $op1,$op2" %}
11881 // ins_cost(500);
11882 // opcode(0x39); /* Opcode 39 /r */
11883 // ins_encode( OpcP, RegMem( op1, op2) );
11884 //%}
11885
11886 instruct testU_reg( eFlagsRegU cr, rRegI src, immI0 zero ) %{
11887 match(Set cr (CmpU src zero));
11888
11889 format %{ "TESTu $src,$src" %}
11890 opcode(0x85);
11891 ins_encode( OpcP, RegReg( src, src ) );
11892 ins_pipe( ialu_cr_reg_imm );
11893 %}
11894
11895 // Unsigned pointer compare Instructions
11896 instruct compP_eReg(eFlagsRegU cr, eRegP op1, eRegP op2) %{
11897 match(Set cr (CmpP op1 op2));
11898
11899 format %{ "CMPu $op1,$op2" %}
11900 opcode(0x3B); /* Opcode 3B /r */
11901 ins_encode( OpcP, RegReg( op1, op2) );
11902 ins_pipe( ialu_cr_reg_reg );
11903 %}
11904
11905 instruct compP_eReg_imm(eFlagsRegU cr, eRegP op1, immP op2) %{
11906 match(Set cr (CmpP op1 op2));
11907
11908 format %{ "CMPu $op1,$op2" %}
11909 opcode(0x81,0x07); /* Opcode 81 /7 */
11910 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) );
11911 ins_pipe( ialu_cr_reg_imm );
11912 %}
11913
11914 // // Cisc-spilled version of cmpP_eReg
11915 instruct compP_eReg_mem(eFlagsRegU cr, eRegP op1, memory op2) %{
11916 match(Set cr (CmpP op1 (LoadP op2)));
11917
11918 format %{ "CMPu $op1,$op2" %}
11919 ins_cost(500);
11920 opcode(0x3B); /* Opcode 3B /r */
11921 ins_encode( OpcP, RegMem( op1, op2) );
11922 ins_pipe( ialu_cr_reg_mem );
11923 %}
11924
11925 // // Cisc-spilled version of cmpP_eReg
11926 //instruct compP_mem_eReg(eFlagsRegU cr, memory op1, eRegP op2) %{
11927 // match(Set cr (CmpP (LoadP op1) op2));
11928 //
11929 // format %{ "CMPu $op1,$op2" %}
11930 // ins_cost(500);
11931 // opcode(0x39); /* Opcode 39 /r */
11932 // ins_encode( OpcP, RegMem( op1, op2) );
11933 //%}
11934
11935 // Compare raw pointer (used in out-of-heap check).
11936 // Only works because non-oop pointers must be raw pointers
11937 // and raw pointers have no anti-dependencies.
11938 instruct compP_mem_eReg( eFlagsRegU cr, eRegP op1, memory op2 ) %{
11939 predicate( !n->in(2)->in(2)->bottom_type()->isa_oop_ptr() );
11940 match(Set cr (CmpP op1 (LoadP op2)));
11941
11942 format %{ "CMPu $op1,$op2" %}
11943 opcode(0x3B); /* Opcode 3B /r */
11944 ins_encode( OpcP, RegMem( op1, op2) );
11945 ins_pipe( ialu_cr_reg_mem );
11946 %}
11947
11948 //
11949 // This will generate a signed flags result. This should be ok
11950 // since any compare to a zero should be eq/neq.
11951 instruct testP_reg( eFlagsReg cr, eRegP src, immP0 zero ) %{
11952 match(Set cr (CmpP src zero));
11953
11954 format %{ "TEST $src,$src" %}
11955 opcode(0x85);
11956 ins_encode( OpcP, RegReg( src, src ) );
11957 ins_pipe( ialu_cr_reg_imm );
11958 %}
11959
11960 // Cisc-spilled version of testP_reg
11961 // This will generate a signed flags result. This should be ok
11962 // since any compare to a zero should be eq/neq.
11963 instruct testP_Reg_mem( eFlagsReg cr, memory op, immI0 zero ) %{
11964 match(Set cr (CmpP (LoadP op) zero));
11965
11966 format %{ "TEST $op,0xFFFFFFFF" %}
11967 ins_cost(500);
11968 opcode(0xF7); /* Opcode F7 /0 */
11969 ins_encode( OpcP, RMopc_Mem(0x00,op), Con_d32(0xFFFFFFFF) );
11970 ins_pipe( ialu_cr_reg_imm );
11971 %}
11972
11973 // Yanked all unsigned pointer compare operations.
11974 // Pointer compares are done with CmpP which is already unsigned.
11975
11976 //----------Max and Min--------------------------------------------------------
11977 // Min Instructions
11978 ////
11979 // *** Min and Max using the conditional move are slower than the
11980 // *** branch version on a Pentium III.
11981 // // Conditional move for min
11982 //instruct cmovI_reg_lt( rRegI op2, rRegI op1, eFlagsReg cr ) %{
11983 // effect( USE_DEF op2, USE op1, USE cr );
11984 // format %{ "CMOVlt $op2,$op1\t! min" %}
11985 // opcode(0x4C,0x0F);
11986 // ins_encode( OpcS, OpcP, RegReg( op2, op1 ) );
11987 // ins_pipe( pipe_cmov_reg );
11988 //%}
11989 //
11990 //// Min Register with Register (P6 version)
11991 //instruct minI_eReg_p6( rRegI op1, rRegI op2 ) %{
11992 // predicate(VM_Version::supports_cmov() );
11993 // match(Set op2 (MinI op1 op2));
11994 // ins_cost(200);
11995 // expand %{
11996 // eFlagsReg cr;
11997 // compI_eReg(cr,op1,op2);
11998 // cmovI_reg_lt(op2,op1,cr);
11999 // %}
12000 //%}
12001
12002 // Min Register with Register (generic version)
12003 instruct minI_eReg(rRegI dst, rRegI src, eFlagsReg flags) %{
12004 match(Set dst (MinI dst src));
12005 effect(KILL flags);
12006 ins_cost(300);
12007
12008 format %{ "MIN $dst,$src" %}
12009 opcode(0xCC);
12010 ins_encode( min_enc(dst,src) );
12011 ins_pipe( pipe_slow );
12012 %}
12013
12014 // Max Register with Register
12015 // *** Min and Max using the conditional move are slower than the
12016 // *** branch version on a Pentium III.
12017 // // Conditional move for max
12018 //instruct cmovI_reg_gt( rRegI op2, rRegI op1, eFlagsReg cr ) %{
12019 // effect( USE_DEF op2, USE op1, USE cr );
12020 // format %{ "CMOVgt $op2,$op1\t! max" %}
12021 // opcode(0x4F,0x0F);
12022 // ins_encode( OpcS, OpcP, RegReg( op2, op1 ) );
12023 // ins_pipe( pipe_cmov_reg );
12024 //%}
12025 //
12026 // // Max Register with Register (P6 version)
12027 //instruct maxI_eReg_p6( rRegI op1, rRegI op2 ) %{
12028 // predicate(VM_Version::supports_cmov() );
12029 // match(Set op2 (MaxI op1 op2));
12030 // ins_cost(200);
12031 // expand %{
12032 // eFlagsReg cr;
12033 // compI_eReg(cr,op1,op2);
12034 // cmovI_reg_gt(op2,op1,cr);
12035 // %}
12036 //%}
12037
12038 // Max Register with Register (generic version)
12039 instruct maxI_eReg(rRegI dst, rRegI src, eFlagsReg flags) %{
12040 match(Set dst (MaxI dst src));
12041 effect(KILL flags);
12042 ins_cost(300);
12043
12044 format %{ "MAX $dst,$src" %}
12045 opcode(0xCC);
12046 ins_encode( max_enc(dst,src) );
12047 ins_pipe( pipe_slow );
12048 %}
12049
12050 // ============================================================================
12051 // Counted Loop limit node which represents exact final iterator value.
12052 // Note: the resulting value should fit into integer range since
12053 // counted loops have limit check on overflow.
12054 instruct loopLimit_eReg(eAXRegI limit, nadxRegI init, immI stride, eDXRegI limit_hi, nadxRegI tmp, eFlagsReg flags) %{
12055 match(Set limit (LoopLimit (Binary init limit) stride));
12056 effect(TEMP limit_hi, TEMP tmp, KILL flags);
12057 ins_cost(300);
12058
12059 format %{ "loopLimit $init,$limit,$stride # $limit = $init + $stride *( $limit - $init + $stride -1)/ $stride, kills $limit_hi" %}
12060 ins_encode %{
12061 int strd = (int)$stride$$constant;
12062 assert(strd != 1 && strd != -1, "sanity");
12063 int m1 = (strd > 0) ? 1 : -1;
12064 // Convert limit to long (EAX:EDX)
12065 __ cdql();
12066 // Convert init to long (init:tmp)
12067 __ movl($tmp$$Register, $init$$Register);
12068 __ sarl($tmp$$Register, 31);
12069 // $limit - $init
12070 __ subl($limit$$Register, $init$$Register);
12071 __ sbbl($limit_hi$$Register, $tmp$$Register);
12072 // + ($stride - 1)
12073 if (strd > 0) {
12074 __ addl($limit$$Register, (strd - 1));
12075 __ adcl($limit_hi$$Register, 0);
12076 __ movl($tmp$$Register, strd);
12077 } else {
12078 __ addl($limit$$Register, (strd + 1));
12079 __ adcl($limit_hi$$Register, -1);
12080 __ lneg($limit_hi$$Register, $limit$$Register);
12081 __ movl($tmp$$Register, -strd);
12082 }
12083 // signed devision: (EAX:EDX) / pos_stride
12084 __ idivl($tmp$$Register);
12085 if (strd < 0) {
12086 // restore sign
12087 __ negl($tmp$$Register);
12088 }
12089 // (EAX) * stride
12090 __ mull($tmp$$Register);
12091 // + init (ignore upper bits)
12092 __ addl($limit$$Register, $init$$Register);
12093 %}
12094 ins_pipe( pipe_slow );
12095 %}
12096
12097 // ============================================================================
12098 // Branch Instructions
12099 // Jump Table
12100 instruct jumpXtnd(rRegI switch_val) %{
12101 match(Jump switch_val);
12102 ins_cost(350);
12103 format %{ "JMP [$constantaddress](,$switch_val,1)\n\t" %}
12104 ins_encode %{
12105 // Jump to Address(table_base + switch_reg)
12106 Address index(noreg, $switch_val$$Register, Address::times_1);
12107 __ jump(ArrayAddress($constantaddress, index));
12108 %}
12109 ins_pipe(pipe_jmp);
12110 %}
12111
12112 // Jump Direct - Label defines a relative address from JMP+1
12113 instruct jmpDir(label labl) %{
12114 match(Goto);
12115 effect(USE labl);
12116
12117 ins_cost(300);
12118 format %{ "JMP $labl" %}
12119 size(5);
12120 ins_encode %{
12121 Label* L = $labl$$label;
12122 __ jmp(*L, false); // Always long jump
12123 %}
12124 ins_pipe( pipe_jmp );
12125 %}
12126
12127 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12128 instruct jmpCon(cmpOp cop, eFlagsReg cr, label labl) %{
12129 match(If cop cr);
12130 effect(USE labl);
12131
12132 ins_cost(300);
12133 format %{ "J$cop $labl" %}
12134 size(6);
12135 ins_encode %{
12136 Label* L = $labl$$label;
12137 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12138 %}
12139 ins_pipe( pipe_jcc );
12140 %}
12141
12142 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12143 instruct jmpLoopEnd(cmpOp cop, eFlagsReg cr, label labl) %{
12144 match(CountedLoopEnd cop cr);
12145 effect(USE labl);
12146
12147 ins_cost(300);
12148 format %{ "J$cop $labl\t# Loop end" %}
12149 size(6);
12150 ins_encode %{
12151 Label* L = $labl$$label;
12152 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12153 %}
12154 ins_pipe( pipe_jcc );
12155 %}
12156
12157 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12158 instruct jmpLoopEndU(cmpOpU cop, eFlagsRegU cmp, label labl) %{
12159 match(CountedLoopEnd cop cmp);
12160 effect(USE labl);
12161
12162 ins_cost(300);
12163 format %{ "J$cop,u $labl\t# Loop end" %}
12164 size(6);
12165 ins_encode %{
12166 Label* L = $labl$$label;
12167 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12168 %}
12169 ins_pipe( pipe_jcc );
12170 %}
12171
12172 instruct jmpLoopEndUCF(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
12173 match(CountedLoopEnd cop cmp);
12174 effect(USE labl);
12175
12176 ins_cost(200);
12177 format %{ "J$cop,u $labl\t# Loop end" %}
12178 size(6);
12179 ins_encode %{
12180 Label* L = $labl$$label;
12181 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12182 %}
12183 ins_pipe( pipe_jcc );
12184 %}
12185
12186 // Jump Direct Conditional - using unsigned comparison
12187 instruct jmpConU(cmpOpU cop, eFlagsRegU cmp, label labl) %{
12188 match(If cop cmp);
12189 effect(USE labl);
12190
12191 ins_cost(300);
12192 format %{ "J$cop,u $labl" %}
12193 size(6);
12194 ins_encode %{
12195 Label* L = $labl$$label;
12196 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12197 %}
12198 ins_pipe(pipe_jcc);
12199 %}
12200
12201 instruct jmpConUCF(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
12202 match(If cop cmp);
12203 effect(USE labl);
12204
12205 ins_cost(200);
12206 format %{ "J$cop,u $labl" %}
12207 size(6);
12208 ins_encode %{
12209 Label* L = $labl$$label;
12210 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12211 %}
12212 ins_pipe(pipe_jcc);
12213 %}
12214
12215 instruct jmpConUCF2(cmpOpUCF2 cop, eFlagsRegUCF cmp, label labl) %{
12216 match(If cop cmp);
12217 effect(USE labl);
12218
12219 ins_cost(200);
12220 format %{ $$template
12221 if ($cop$$cmpcode == Assembler::notEqual) {
12222 $$emit$$"JP,u $labl\n\t"
12223 $$emit$$"J$cop,u $labl"
12224 } else {
12225 $$emit$$"JP,u done\n\t"
12226 $$emit$$"J$cop,u $labl\n\t"
12227 $$emit$$"done:"
12228 }
12229 %}
12230 ins_encode %{
12231 Label* l = $labl$$label;
12232 if ($cop$$cmpcode == Assembler::notEqual) {
12233 __ jcc(Assembler::parity, *l, false);
12234 __ jcc(Assembler::notEqual, *l, false);
12235 } else if ($cop$$cmpcode == Assembler::equal) {
12236 Label done;
12237 __ jccb(Assembler::parity, done);
12238 __ jcc(Assembler::equal, *l, false);
12239 __ bind(done);
12240 } else {
12241 ShouldNotReachHere();
12242 }
12243 %}
12244 ins_pipe(pipe_jcc);
12245 %}
12246
12247 // ============================================================================
12248 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass
12249 // array for an instance of the superklass. Set a hidden internal cache on a
12250 // hit (cache is checked with exposed code in gen_subtype_check()). Return
12251 // NZ for a miss or zero for a hit. The encoding ALSO sets flags.
12252 instruct partialSubtypeCheck( eDIRegP result, eSIRegP sub, eAXRegP super, eCXRegI rcx, eFlagsReg cr ) %{
12253 match(Set result (PartialSubtypeCheck sub super));
12254 effect( KILL rcx, KILL cr );
12255
12256 ins_cost(1100); // slightly larger than the next version
12257 format %{ "MOV EDI,[$sub+Klass::secondary_supers]\n\t"
12258 "MOV ECX,[EDI+arrayKlass::length]\t# length to scan\n\t"
12259 "ADD EDI,arrayKlass::base_offset\t# Skip to start of data; set NZ in case count is zero\n\t"
12260 "REPNE SCASD\t# Scan *EDI++ for a match with EAX while CX-- != 0\n\t"
12261 "JNE,s miss\t\t# Missed: EDI not-zero\n\t"
12262 "MOV [$sub+Klass::secondary_super_cache],$super\t# Hit: update cache\n\t"
12263 "XOR $result,$result\t\t Hit: EDI zero\n\t"
12264 "miss:\t" %}
12265
12266 opcode(0x1); // Force a XOR of EDI
12267 ins_encode( enc_PartialSubtypeCheck() );
12268 ins_pipe( pipe_slow );
12269 %}
12270
12271 instruct partialSubtypeCheck_vs_Zero( eFlagsReg cr, eSIRegP sub, eAXRegP super, eCXRegI rcx, eDIRegP result, immP0 zero ) %{
12272 match(Set cr (CmpP (PartialSubtypeCheck sub super) zero));
12273 effect( KILL rcx, KILL result );
12274
12275 ins_cost(1000);
12276 format %{ "MOV EDI,[$sub+Klass::secondary_supers]\n\t"
12277 "MOV ECX,[EDI+arrayKlass::length]\t# length to scan\n\t"
12278 "ADD EDI,arrayKlass::base_offset\t# Skip to start of data; set NZ in case count is zero\n\t"
12279 "REPNE SCASD\t# Scan *EDI++ for a match with EAX while CX-- != 0\n\t"
12280 "JNE,s miss\t\t# Missed: flags NZ\n\t"
12281 "MOV [$sub+Klass::secondary_super_cache],$super\t# Hit: update cache, flags Z\n\t"
12282 "miss:\t" %}
12283
12284 opcode(0x0); // No need to XOR EDI
12285 ins_encode( enc_PartialSubtypeCheck() );
12286 ins_pipe( pipe_slow );
12287 %}
12288
12289 // ============================================================================
12290 // Branch Instructions -- short offset versions
12291 //
12292 // These instructions are used to replace jumps of a long offset (the default
12293 // match) with jumps of a shorter offset. These instructions are all tagged
12294 // with the ins_short_branch attribute, which causes the ADLC to suppress the
12295 // match rules in general matching. Instead, the ADLC generates a conversion
12296 // method in the MachNode which can be used to do in-place replacement of the
12297 // long variant with the shorter variant. The compiler will determine if a
12298 // branch can be taken by the is_short_branch_offset() predicate in the machine
12299 // specific code section of the file.
12300
12301 // Jump Direct - Label defines a relative address from JMP+1
12302 instruct jmpDir_short(label labl) %{
12303 match(Goto);
12304 effect(USE labl);
12305
12306 ins_cost(300);
12307 format %{ "JMP,s $labl" %}
12308 size(2);
12309 ins_encode %{
12310 Label* L = $labl$$label;
12311 __ jmpb(*L);
12312 %}
12313 ins_pipe( pipe_jmp );
12314 ins_short_branch(1);
12315 %}
12316
12317 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12318 instruct jmpCon_short(cmpOp cop, eFlagsReg cr, label labl) %{
12319 match(If cop cr);
12320 effect(USE labl);
12321
12322 ins_cost(300);
12323 format %{ "J$cop,s $labl" %}
12324 size(2);
12325 ins_encode %{
12326 Label* L = $labl$$label;
12327 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12328 %}
12329 ins_pipe( pipe_jcc );
12330 ins_short_branch(1);
12331 %}
12332
12333 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12334 instruct jmpLoopEnd_short(cmpOp cop, eFlagsReg cr, label labl) %{
12335 match(CountedLoopEnd cop cr);
12336 effect(USE labl);
12337
12338 ins_cost(300);
12339 format %{ "J$cop,s $labl\t# Loop end" %}
12340 size(2);
12341 ins_encode %{
12342 Label* L = $labl$$label;
12343 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12344 %}
12345 ins_pipe( pipe_jcc );
12346 ins_short_branch(1);
12347 %}
12348
12349 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12350 instruct jmpLoopEndU_short(cmpOpU cop, eFlagsRegU cmp, label labl) %{
12351 match(CountedLoopEnd cop cmp);
12352 effect(USE labl);
12353
12354 ins_cost(300);
12355 format %{ "J$cop,us $labl\t# Loop end" %}
12356 size(2);
12357 ins_encode %{
12358 Label* L = $labl$$label;
12359 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12360 %}
12361 ins_pipe( pipe_jcc );
12362 ins_short_branch(1);
12363 %}
12364
12365 instruct jmpLoopEndUCF_short(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
12366 match(CountedLoopEnd cop cmp);
12367 effect(USE labl);
12368
12369 ins_cost(300);
12370 format %{ "J$cop,us $labl\t# Loop end" %}
12371 size(2);
12372 ins_encode %{
12373 Label* L = $labl$$label;
12374 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12375 %}
12376 ins_pipe( pipe_jcc );
12377 ins_short_branch(1);
12378 %}
12379
12380 // Jump Direct Conditional - using unsigned comparison
12381 instruct jmpConU_short(cmpOpU cop, eFlagsRegU cmp, label labl) %{
12382 match(If cop cmp);
12383 effect(USE labl);
12384
12385 ins_cost(300);
12386 format %{ "J$cop,us $labl" %}
12387 size(2);
12388 ins_encode %{
12389 Label* L = $labl$$label;
12390 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12391 %}
12392 ins_pipe( pipe_jcc );
12393 ins_short_branch(1);
12394 %}
12395
12396 instruct jmpConUCF_short(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{
12397 match(If cop cmp);
12398 effect(USE labl);
12399
12400 ins_cost(300);
12401 format %{ "J$cop,us $labl" %}
12402 size(2);
12403 ins_encode %{
12404 Label* L = $labl$$label;
12405 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12406 %}
12407 ins_pipe( pipe_jcc );
12408 ins_short_branch(1);
12409 %}
12410
12411 instruct jmpConUCF2_short(cmpOpUCF2 cop, eFlagsRegUCF cmp, label labl) %{
12412 match(If cop cmp);
12413 effect(USE labl);
12414
12415 ins_cost(300);
12416 format %{ $$template
12417 if ($cop$$cmpcode == Assembler::notEqual) {
12418 $$emit$$"JP,u,s $labl\n\t"
12419 $$emit$$"J$cop,u,s $labl"
12420 } else {
12421 $$emit$$"JP,u,s done\n\t"
12422 $$emit$$"J$cop,u,s $labl\n\t"
12423 $$emit$$"done:"
12424 }
12425 %}
12426 size(4);
12427 ins_encode %{
12428 Label* l = $labl$$label;
12429 if ($cop$$cmpcode == Assembler::notEqual) {
12430 __ jccb(Assembler::parity, *l);
12431 __ jccb(Assembler::notEqual, *l);
12432 } else if ($cop$$cmpcode == Assembler::equal) {
12433 Label done;
12434 __ jccb(Assembler::parity, done);
12435 __ jccb(Assembler::equal, *l);
12436 __ bind(done);
12437 } else {
12438 ShouldNotReachHere();
12439 }
12440 %}
12441 ins_pipe(pipe_jcc);
12442 ins_short_branch(1);
12443 %}
12444
12445 // ============================================================================
12446 // Long Compare
12447 //
12448 // Currently we hold longs in 2 registers. Comparing such values efficiently
12449 // is tricky. The flavor of compare used depends on whether we are testing
12450 // for LT, LE, or EQ. For a simple LT test we can check just the sign bit.
12451 // The GE test is the negated LT test. The LE test can be had by commuting
12452 // the operands (yielding a GE test) and then negating; negate again for the
12453 // GT test. The EQ test is done by ORcc'ing the high and low halves, and the
12454 // NE test is negated from that.
12455
12456 // Due to a shortcoming in the ADLC, it mixes up expressions like:
12457 // (foo (CmpI (CmpL X Y) 0)) and (bar (CmpI (CmpL X 0L) 0)). Note the
12458 // difference between 'Y' and '0L'. The tree-matches for the CmpI sections
12459 // are collapsed internally in the ADLC's dfa-gen code. The match for
12460 // (CmpI (CmpL X Y) 0) is silently replaced with (CmpI (CmpL X 0L) 0) and the
12461 // foo match ends up with the wrong leaf. One fix is to not match both
12462 // reg-reg and reg-zero forms of long-compare. This is unfortunate because
12463 // both forms beat the trinary form of long-compare and both are very useful
12464 // on Intel which has so few registers.
12465
12466 // Manifest a CmpL result in an integer register. Very painful.
12467 // This is the test to avoid.
12468 instruct cmpL3_reg_reg(eSIRegI dst, eRegL src1, eRegL src2, eFlagsReg flags ) %{
12469 match(Set dst (CmpL3 src1 src2));
12470 effect( KILL flags );
12471 ins_cost(1000);
12472 format %{ "XOR $dst,$dst\n\t"
12473 "CMP $src1.hi,$src2.hi\n\t"
12474 "JLT,s m_one\n\t"
12475 "JGT,s p_one\n\t"
12476 "CMP $src1.lo,$src2.lo\n\t"
12477 "JB,s m_one\n\t"
12478 "JEQ,s done\n"
12479 "p_one:\tINC $dst\n\t"
12480 "JMP,s done\n"
12481 "m_one:\tDEC $dst\n"
12482 "done:" %}
12483 ins_encode %{
12484 Label p_one, m_one, done;
12485 __ xorptr($dst$$Register, $dst$$Register);
12486 __ cmpl(HIGH_FROM_LOW($src1$$Register), HIGH_FROM_LOW($src2$$Register));
12487 __ jccb(Assembler::less, m_one);
12488 __ jccb(Assembler::greater, p_one);
12489 __ cmpl($src1$$Register, $src2$$Register);
12490 __ jccb(Assembler::below, m_one);
12491 __ jccb(Assembler::equal, done);
12492 __ bind(p_one);
12493 __ incrementl($dst$$Register);
12494 __ jmpb(done);
12495 __ bind(m_one);
12496 __ decrementl($dst$$Register);
12497 __ bind(done);
12498 %}
12499 ins_pipe( pipe_slow );
12500 %}
12501
12502 //======
12503 // Manifest a CmpL result in the normal flags. Only good for LT or GE
12504 // compares. Can be used for LE or GT compares by reversing arguments.
12505 // NOT GOOD FOR EQ/NE tests.
12506 instruct cmpL_zero_flags_LTGE( flagsReg_long_LTGE flags, eRegL src, immL0 zero ) %{
12507 match( Set flags (CmpL src zero ));
12508 ins_cost(100);
12509 format %{ "TEST $src.hi,$src.hi" %}
12510 opcode(0x85);
12511 ins_encode( OpcP, RegReg_Hi2( src, src ) );
12512 ins_pipe( ialu_cr_reg_reg );
12513 %}
12514
12515 // Manifest a CmpL result in the normal flags. Only good for LT or GE
12516 // compares. Can be used for LE or GT compares by reversing arguments.
12517 // NOT GOOD FOR EQ/NE tests.
12518 instruct cmpL_reg_flags_LTGE( flagsReg_long_LTGE flags, eRegL src1, eRegL src2, rRegI tmp ) %{
12519 match( Set flags (CmpL src1 src2 ));
12520 effect( TEMP tmp );
12521 ins_cost(300);
12522 format %{ "CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits\n\t"
12523 "MOV $tmp,$src1.hi\n\t"
12524 "SBB $tmp,$src2.hi\t! Compute flags for long compare" %}
12525 ins_encode( long_cmp_flags2( src1, src2, tmp ) );
12526 ins_pipe( ialu_cr_reg_reg );
12527 %}
12528
12529 // Long compares reg < zero/req OR reg >= zero/req.
12530 // Just a wrapper for a normal branch, plus the predicate test.
12531 instruct cmpL_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, label labl) %{
12532 match(If cmp flags);
12533 effect(USE labl);
12534 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
12535 expand %{
12536 jmpCon(cmp,flags,labl); // JLT or JGE...
12537 %}
12538 %}
12539
12540 //======
12541 // Manifest a CmpUL result in the normal flags. Only good for LT or GE
12542 // compares. Can be used for LE or GT compares by reversing arguments.
12543 // NOT GOOD FOR EQ/NE tests.
12544 instruct cmpUL_zero_flags_LTGE(flagsReg_ulong_LTGE flags, eRegL src, immL0 zero) %{
12545 match(Set flags (CmpUL src zero));
12546 ins_cost(100);
12547 format %{ "TEST $src.hi,$src.hi" %}
12548 opcode(0x85);
12549 ins_encode(OpcP, RegReg_Hi2(src, src));
12550 ins_pipe(ialu_cr_reg_reg);
12551 %}
12552
12553 // Manifest a CmpUL result in the normal flags. Only good for LT or GE
12554 // compares. Can be used for LE or GT compares by reversing arguments.
12555 // NOT GOOD FOR EQ/NE tests.
12556 instruct cmpUL_reg_flags_LTGE(flagsReg_ulong_LTGE flags, eRegL src1, eRegL src2, rRegI tmp) %{
12557 match(Set flags (CmpUL src1 src2));
12558 effect(TEMP tmp);
12559 ins_cost(300);
12560 format %{ "CMP $src1.lo,$src2.lo\t! Unsigned long compare; set flags for low bits\n\t"
12561 "MOV $tmp,$src1.hi\n\t"
12562 "SBB $tmp,$src2.hi\t! Compute flags for unsigned long compare" %}
12563 ins_encode(long_cmp_flags2(src1, src2, tmp));
12564 ins_pipe(ialu_cr_reg_reg);
12565 %}
12566
12567 // Unsigned long compares reg < zero/req OR reg >= zero/req.
12568 // Just a wrapper for a normal branch, plus the predicate test.
12569 instruct cmpUL_LTGE(cmpOpU cmp, flagsReg_ulong_LTGE flags, label labl) %{
12570 match(If cmp flags);
12571 effect(USE labl);
12572 predicate(_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge);
12573 expand %{
12574 jmpCon(cmp, flags, labl); // JLT or JGE...
12575 %}
12576 %}
12577
12578 // Compare 2 longs and CMOVE longs.
12579 instruct cmovLL_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegL dst, eRegL src) %{
12580 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src)));
12581 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
12582 ins_cost(400);
12583 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12584 "CMOV$cmp $dst.hi,$src.hi" %}
12585 opcode(0x0F,0x40);
12586 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) );
12587 ins_pipe( pipe_cmov_reg_long );
12588 %}
12589
12590 instruct cmovLL_mem_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegL dst, load_long_memory src) %{
12591 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src))));
12592 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
12593 ins_cost(500);
12594 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12595 "CMOV$cmp $dst.hi,$src.hi" %}
12596 opcode(0x0F,0x40);
12597 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) );
12598 ins_pipe( pipe_cmov_reg_long );
12599 %}
12600
12601 // Compare 2 longs and CMOVE ints.
12602 instruct cmovII_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, rRegI dst, rRegI src) %{
12603 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
12604 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src)));
12605 ins_cost(200);
12606 format %{ "CMOV$cmp $dst,$src" %}
12607 opcode(0x0F,0x40);
12608 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12609 ins_pipe( pipe_cmov_reg );
12610 %}
12611
12612 instruct cmovII_mem_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, rRegI dst, memory src) %{
12613 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
12614 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src))));
12615 ins_cost(250);
12616 format %{ "CMOV$cmp $dst,$src" %}
12617 opcode(0x0F,0x40);
12618 ins_encode( enc_cmov(cmp), RegMem( dst, src ) );
12619 ins_pipe( pipe_cmov_mem );
12620 %}
12621
12622 // Compare 2 longs and CMOVE ints.
12623 instruct cmovPP_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegP dst, eRegP src) %{
12624 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ));
12625 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src)));
12626 ins_cost(200);
12627 format %{ "CMOV$cmp $dst,$src" %}
12628 opcode(0x0F,0x40);
12629 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12630 ins_pipe( pipe_cmov_reg );
12631 %}
12632
12633 // Compare 2 longs and CMOVE doubles
12634 instruct cmovDDPR_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regDPR dst, regDPR src) %{
12635 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
12636 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12637 ins_cost(200);
12638 expand %{
12639 fcmovDPR_regS(cmp,flags,dst,src);
12640 %}
12641 %}
12642
12643 // Compare 2 longs and CMOVE doubles
12644 instruct cmovDD_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regD dst, regD src) %{
12645 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
12646 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12647 ins_cost(200);
12648 expand %{
12649 fcmovD_regS(cmp,flags,dst,src);
12650 %}
12651 %}
12652
12653 instruct cmovFFPR_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regFPR dst, regFPR src) %{
12654 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
12655 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12656 ins_cost(200);
12657 expand %{
12658 fcmovFPR_regS(cmp,flags,dst,src);
12659 %}
12660 %}
12661
12662 instruct cmovFF_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regF dst, regF src) %{
12663 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge );
12664 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12665 ins_cost(200);
12666 expand %{
12667 fcmovF_regS(cmp,flags,dst,src);
12668 %}
12669 %}
12670
12671 //======
12672 // Manifest a CmpL result in the normal flags. Only good for EQ/NE compares.
12673 instruct cmpL_zero_flags_EQNE( flagsReg_long_EQNE flags, eRegL src, immL0 zero, rRegI tmp ) %{
12674 match( Set flags (CmpL src zero ));
12675 effect(TEMP tmp);
12676 ins_cost(200);
12677 format %{ "MOV $tmp,$src.lo\n\t"
12678 "OR $tmp,$src.hi\t! Long is EQ/NE 0?" %}
12679 ins_encode( long_cmp_flags0( src, tmp ) );
12680 ins_pipe( ialu_reg_reg_long );
12681 %}
12682
12683 // Manifest a CmpL result in the normal flags. Only good for EQ/NE compares.
12684 instruct cmpL_reg_flags_EQNE( flagsReg_long_EQNE flags, eRegL src1, eRegL src2 ) %{
12685 match( Set flags (CmpL src1 src2 ));
12686 ins_cost(200+300);
12687 format %{ "CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits\n\t"
12688 "JNE,s skip\n\t"
12689 "CMP $src1.hi,$src2.hi\n\t"
12690 "skip:\t" %}
12691 ins_encode( long_cmp_flags1( src1, src2 ) );
12692 ins_pipe( ialu_cr_reg_reg );
12693 %}
12694
12695 // Long compare reg == zero/reg OR reg != zero/reg
12696 // Just a wrapper for a normal branch, plus the predicate test.
12697 instruct cmpL_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, label labl) %{
12698 match(If cmp flags);
12699 effect(USE labl);
12700 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
12701 expand %{
12702 jmpCon(cmp,flags,labl); // JEQ or JNE...
12703 %}
12704 %}
12705
12706 //======
12707 // Manifest a CmpUL result in the normal flags. Only good for EQ/NE compares.
12708 instruct cmpUL_zero_flags_EQNE(flagsReg_ulong_EQNE flags, eRegL src, immL0 zero, rRegI tmp) %{
12709 match(Set flags (CmpUL src zero));
12710 effect(TEMP tmp);
12711 ins_cost(200);
12712 format %{ "MOV $tmp,$src.lo\n\t"
12713 "OR $tmp,$src.hi\t! Unsigned long is EQ/NE 0?" %}
12714 ins_encode(long_cmp_flags0(src, tmp));
12715 ins_pipe(ialu_reg_reg_long);
12716 %}
12717
12718 // Manifest a CmpUL result in the normal flags. Only good for EQ/NE compares.
12719 instruct cmpUL_reg_flags_EQNE(flagsReg_ulong_EQNE flags, eRegL src1, eRegL src2) %{
12720 match(Set flags (CmpUL src1 src2));
12721 ins_cost(200+300);
12722 format %{ "CMP $src1.lo,$src2.lo\t! Unsigned long compare; set flags for low bits\n\t"
12723 "JNE,s skip\n\t"
12724 "CMP $src1.hi,$src2.hi\n\t"
12725 "skip:\t" %}
12726 ins_encode(long_cmp_flags1(src1, src2));
12727 ins_pipe(ialu_cr_reg_reg);
12728 %}
12729
12730 // Unsigned long compare reg == zero/reg OR reg != zero/reg
12731 // Just a wrapper for a normal branch, plus the predicate test.
12732 instruct cmpUL_EQNE(cmpOpU cmp, flagsReg_ulong_EQNE flags, label labl) %{
12733 match(If cmp flags);
12734 effect(USE labl);
12735 predicate(_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne);
12736 expand %{
12737 jmpCon(cmp, flags, labl); // JEQ or JNE...
12738 %}
12739 %}
12740
12741 // Compare 2 longs and CMOVE longs.
12742 instruct cmovLL_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegL dst, eRegL src) %{
12743 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src)));
12744 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
12745 ins_cost(400);
12746 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12747 "CMOV$cmp $dst.hi,$src.hi" %}
12748 opcode(0x0F,0x40);
12749 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) );
12750 ins_pipe( pipe_cmov_reg_long );
12751 %}
12752
12753 instruct cmovLL_mem_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegL dst, load_long_memory src) %{
12754 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src))));
12755 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
12756 ins_cost(500);
12757 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12758 "CMOV$cmp $dst.hi,$src.hi" %}
12759 opcode(0x0F,0x40);
12760 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) );
12761 ins_pipe( pipe_cmov_reg_long );
12762 %}
12763
12764 // Compare 2 longs and CMOVE ints.
12765 instruct cmovII_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, rRegI dst, rRegI src) %{
12766 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
12767 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src)));
12768 ins_cost(200);
12769 format %{ "CMOV$cmp $dst,$src" %}
12770 opcode(0x0F,0x40);
12771 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12772 ins_pipe( pipe_cmov_reg );
12773 %}
12774
12775 instruct cmovII_mem_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, rRegI dst, memory src) %{
12776 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
12777 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src))));
12778 ins_cost(250);
12779 format %{ "CMOV$cmp $dst,$src" %}
12780 opcode(0x0F,0x40);
12781 ins_encode( enc_cmov(cmp), RegMem( dst, src ) );
12782 ins_pipe( pipe_cmov_mem );
12783 %}
12784
12785 // Compare 2 longs and CMOVE ints.
12786 instruct cmovPP_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegP dst, eRegP src) %{
12787 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ));
12788 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src)));
12789 ins_cost(200);
12790 format %{ "CMOV$cmp $dst,$src" %}
12791 opcode(0x0F,0x40);
12792 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12793 ins_pipe( pipe_cmov_reg );
12794 %}
12795
12796 // Compare 2 longs and CMOVE doubles
12797 instruct cmovDDPR_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regDPR dst, regDPR src) %{
12798 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
12799 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12800 ins_cost(200);
12801 expand %{
12802 fcmovDPR_regS(cmp,flags,dst,src);
12803 %}
12804 %}
12805
12806 // Compare 2 longs and CMOVE doubles
12807 instruct cmovDD_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regD dst, regD src) %{
12808 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
12809 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12810 ins_cost(200);
12811 expand %{
12812 fcmovD_regS(cmp,flags,dst,src);
12813 %}
12814 %}
12815
12816 instruct cmovFFPR_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regFPR dst, regFPR src) %{
12817 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
12818 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12819 ins_cost(200);
12820 expand %{
12821 fcmovFPR_regS(cmp,flags,dst,src);
12822 %}
12823 %}
12824
12825 instruct cmovFF_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regF dst, regF src) %{
12826 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne );
12827 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12828 ins_cost(200);
12829 expand %{
12830 fcmovF_regS(cmp,flags,dst,src);
12831 %}
12832 %}
12833
12834 //======
12835 // Manifest a CmpL result in the normal flags. Only good for LE or GT compares.
12836 // Same as cmpL_reg_flags_LEGT except must negate src
12837 instruct cmpL_zero_flags_LEGT( flagsReg_long_LEGT flags, eRegL src, immL0 zero, rRegI tmp ) %{
12838 match( Set flags (CmpL src zero ));
12839 effect( TEMP tmp );
12840 ins_cost(300);
12841 format %{ "XOR $tmp,$tmp\t# Long compare for -$src < 0, use commuted test\n\t"
12842 "CMP $tmp,$src.lo\n\t"
12843 "SBB $tmp,$src.hi\n\t" %}
12844 ins_encode( long_cmp_flags3(src, tmp) );
12845 ins_pipe( ialu_reg_reg_long );
12846 %}
12847
12848 // Manifest a CmpL result in the normal flags. Only good for LE or GT compares.
12849 // Same as cmpL_reg_flags_LTGE except operands swapped. Swapping operands
12850 // requires a commuted test to get the same result.
12851 instruct cmpL_reg_flags_LEGT( flagsReg_long_LEGT flags, eRegL src1, eRegL src2, rRegI tmp ) %{
12852 match( Set flags (CmpL src1 src2 ));
12853 effect( TEMP tmp );
12854 ins_cost(300);
12855 format %{ "CMP $src2.lo,$src1.lo\t! Long compare, swapped operands, use with commuted test\n\t"
12856 "MOV $tmp,$src2.hi\n\t"
12857 "SBB $tmp,$src1.hi\t! Compute flags for long compare" %}
12858 ins_encode( long_cmp_flags2( src2, src1, tmp ) );
12859 ins_pipe( ialu_cr_reg_reg );
12860 %}
12861
12862 // Long compares reg < zero/req OR reg >= zero/req.
12863 // Just a wrapper for a normal branch, plus the predicate test
12864 instruct cmpL_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, label labl) %{
12865 match(If cmp flags);
12866 effect(USE labl);
12867 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le );
12868 ins_cost(300);
12869 expand %{
12870 jmpCon(cmp,flags,labl); // JGT or JLE...
12871 %}
12872 %}
12873
12874 //======
12875 // Manifest a CmpUL result in the normal flags. Only good for LE or GT compares.
12876 // Same as cmpUL_reg_flags_LEGT except must negate src
12877 instruct cmpUL_zero_flags_LEGT(flagsReg_ulong_LEGT flags, eRegL src, immL0 zero, rRegI tmp) %{
12878 match(Set flags (CmpUL src zero));
12879 effect(TEMP tmp);
12880 ins_cost(300);
12881 format %{ "XOR $tmp,$tmp\t# Unsigned long compare for -$src < 0, use commuted test\n\t"
12882 "CMP $tmp,$src.lo\n\t"
12883 "SBB $tmp,$src.hi\n\t" %}
12884 ins_encode(long_cmp_flags3(src, tmp));
12885 ins_pipe(ialu_reg_reg_long);
12886 %}
12887
12888 // Manifest a CmpUL result in the normal flags. Only good for LE or GT compares.
12889 // Same as cmpUL_reg_flags_LTGE except operands swapped. Swapping operands
12890 // requires a commuted test to get the same result.
12891 instruct cmpUL_reg_flags_LEGT(flagsReg_ulong_LEGT flags, eRegL src1, eRegL src2, rRegI tmp) %{
12892 match(Set flags (CmpUL src1 src2));
12893 effect(TEMP tmp);
12894 ins_cost(300);
12895 format %{ "CMP $src2.lo,$src1.lo\t! Unsigned long compare, swapped operands, use with commuted test\n\t"
12896 "MOV $tmp,$src2.hi\n\t"
12897 "SBB $tmp,$src1.hi\t! Compute flags for unsigned long compare" %}
12898 ins_encode(long_cmp_flags2( src2, src1, tmp));
12899 ins_pipe(ialu_cr_reg_reg);
12900 %}
12901
12902 // Unsigned long compares reg < zero/req OR reg >= zero/req.
12903 // Just a wrapper for a normal branch, plus the predicate test
12904 instruct cmpUL_LEGT(cmpOpU_commute cmp, flagsReg_ulong_LEGT flags, label labl) %{
12905 match(If cmp flags);
12906 effect(USE labl);
12907 predicate(_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le);
12908 ins_cost(300);
12909 expand %{
12910 jmpCon(cmp, flags, labl); // JGT or JLE...
12911 %}
12912 %}
12913
12914 // Compare 2 longs and CMOVE longs.
12915 instruct cmovLL_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegL dst, eRegL src) %{
12916 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src)));
12917 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
12918 ins_cost(400);
12919 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12920 "CMOV$cmp $dst.hi,$src.hi" %}
12921 opcode(0x0F,0x40);
12922 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) );
12923 ins_pipe( pipe_cmov_reg_long );
12924 %}
12925
12926 instruct cmovLL_mem_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegL dst, load_long_memory src) %{
12927 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src))));
12928 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
12929 ins_cost(500);
12930 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t"
12931 "CMOV$cmp $dst.hi,$src.hi+4" %}
12932 opcode(0x0F,0x40);
12933 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) );
12934 ins_pipe( pipe_cmov_reg_long );
12935 %}
12936
12937 // Compare 2 longs and CMOVE ints.
12938 instruct cmovII_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, rRegI dst, rRegI src) %{
12939 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
12940 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src)));
12941 ins_cost(200);
12942 format %{ "CMOV$cmp $dst,$src" %}
12943 opcode(0x0F,0x40);
12944 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12945 ins_pipe( pipe_cmov_reg );
12946 %}
12947
12948 instruct cmovII_mem_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, rRegI dst, memory src) %{
12949 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
12950 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src))));
12951 ins_cost(250);
12952 format %{ "CMOV$cmp $dst,$src" %}
12953 opcode(0x0F,0x40);
12954 ins_encode( enc_cmov(cmp), RegMem( dst, src ) );
12955 ins_pipe( pipe_cmov_mem );
12956 %}
12957
12958 // Compare 2 longs and CMOVE ptrs.
12959 instruct cmovPP_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegP dst, eRegP src) %{
12960 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ));
12961 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src)));
12962 ins_cost(200);
12963 format %{ "CMOV$cmp $dst,$src" %}
12964 opcode(0x0F,0x40);
12965 ins_encode( enc_cmov(cmp), RegReg( dst, src ) );
12966 ins_pipe( pipe_cmov_reg );
12967 %}
12968
12969 // Compare 2 longs and CMOVE doubles
12970 instruct cmovDDPR_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regDPR dst, regDPR src) %{
12971 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
12972 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12973 ins_cost(200);
12974 expand %{
12975 fcmovDPR_regS(cmp,flags,dst,src);
12976 %}
12977 %}
12978
12979 // Compare 2 longs and CMOVE doubles
12980 instruct cmovDD_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regD dst, regD src) %{
12981 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
12982 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src)));
12983 ins_cost(200);
12984 expand %{
12985 fcmovD_regS(cmp,flags,dst,src);
12986 %}
12987 %}
12988
12989 instruct cmovFFPR_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regFPR dst, regFPR src) %{
12990 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
12991 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
12992 ins_cost(200);
12993 expand %{
12994 fcmovFPR_regS(cmp,flags,dst,src);
12995 %}
12996 %}
12997
12998
12999 instruct cmovFF_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regF dst, regF src) %{
13000 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt );
13001 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src)));
13002 ins_cost(200);
13003 expand %{
13004 fcmovF_regS(cmp,flags,dst,src);
13005 %}
13006 %}
13007
13008
13009 // ============================================================================
13010 // Procedure Call/Return Instructions
13011 // Call Java Static Instruction
13012 // Note: If this code changes, the corresponding ret_addr_offset() and
13013 // compute_padding() functions will have to be adjusted.
13014 instruct CallStaticJavaDirect(method meth) %{
13015 match(CallStaticJava);
13016 predicate(! ((CallStaticJavaNode*)n)->is_method_handle_invoke());
13017 effect(USE meth);
13018
13019 ins_cost(300);
13020 format %{ "CALL,static " %}
13021 opcode(0xE8); /* E8 cd */
13022 ins_encode( pre_call_resets,
13023 Java_Static_Call( meth ),
13024 call_epilog,
13025 post_call_FPU );
13026 ins_pipe( pipe_slow );
13027 ins_alignment(4);
13028 %}
13029
13030 // Call Java Static Instruction (method handle version)
13031 // Note: If this code changes, the corresponding ret_addr_offset() and
13032 // compute_padding() functions will have to be adjusted.
13033 instruct CallStaticJavaHandle(method meth, eBPRegP ebp_mh_SP_save) %{
13034 match(CallStaticJava);
13035 predicate(((CallStaticJavaNode*)n)->is_method_handle_invoke());
13036 effect(USE meth);
13037 // EBP is saved by all callees (for interpreter stack correction).
13038 // We use it here for a similar purpose, in {preserve,restore}_SP.
13039
13040 ins_cost(300);
13041 format %{ "CALL,static/MethodHandle " %}
13042 opcode(0xE8); /* E8 cd */
13043 ins_encode( pre_call_resets,
13044 preserve_SP,
13045 Java_Static_Call( meth ),
13046 restore_SP,
13047 call_epilog,
13048 post_call_FPU );
13049 ins_pipe( pipe_slow );
13050 ins_alignment(4);
13051 %}
13052
13053 // Call Java Dynamic Instruction
13054 // Note: If this code changes, the corresponding ret_addr_offset() and
13055 // compute_padding() functions will have to be adjusted.
13056 instruct CallDynamicJavaDirect(method meth) %{
13057 match(CallDynamicJava);
13058 effect(USE meth);
13059
13060 ins_cost(300);
13061 format %{ "MOV EAX,(oop)-1\n\t"
13062 "CALL,dynamic" %}
13063 opcode(0xE8); /* E8 cd */
13064 ins_encode( pre_call_resets,
13065 Java_Dynamic_Call( meth ),
13066 call_epilog,
13067 post_call_FPU );
13068 ins_pipe( pipe_slow );
13069 ins_alignment(4);
13070 %}
13071
13072 // Call Runtime Instruction
13073 instruct CallRuntimeDirect(method meth) %{
13074 match(CallRuntime );
13075 effect(USE meth);
13076
13077 ins_cost(300);
13078 format %{ "CALL,runtime " %}
13079 opcode(0xE8); /* E8 cd */
13080 // Use FFREEs to clear entries in float stack
13081 ins_encode( pre_call_resets,
13082 FFree_Float_Stack_All,
13083 Java_To_Runtime( meth ),
13084 post_call_FPU );
13085 ins_pipe( pipe_slow );
13086 %}
13087
13088 // Call runtime without safepoint
13089 instruct CallLeafDirect(method meth) %{
13090 match(CallLeaf);
13091 effect(USE meth);
13092
13093 ins_cost(300);
13094 format %{ "CALL_LEAF,runtime " %}
13095 opcode(0xE8); /* E8 cd */
13096 ins_encode( pre_call_resets,
13097 FFree_Float_Stack_All,
13098 Java_To_Runtime( meth ),
13099 Verify_FPU_For_Leaf, post_call_FPU );
13100 ins_pipe( pipe_slow );
13101 %}
13102
13103 instruct CallLeafNoFPDirect(method meth) %{
13104 match(CallLeafNoFP);
13105 effect(USE meth);
13106
13107 ins_cost(300);
13108 format %{ "CALL_LEAF_NOFP,runtime " %}
13109 opcode(0xE8); /* E8 cd */
13110 ins_encode(Java_To_Runtime(meth));
13111 ins_pipe( pipe_slow );
13112 %}
13113
13114
13115 // Return Instruction
13116 // Remove the return address & jump to it.
13117 instruct Ret() %{
13118 match(Return);
13119 format %{ "RET" %}
13120 opcode(0xC3);
13121 ins_encode(OpcP);
13122 ins_pipe( pipe_jmp );
13123 %}
13124
13125 // Tail Call; Jump from runtime stub to Java code.
13126 // Also known as an 'interprocedural jump'.
13127 // Target of jump will eventually return to caller.
13128 // TailJump below removes the return address.
13129 instruct TailCalljmpInd(eRegP_no_EBP jump_target, eBXRegP method_oop) %{
13130 match(TailCall jump_target method_oop );
13131 ins_cost(300);
13132 format %{ "JMP $jump_target \t# EBX holds method oop" %}
13133 opcode(0xFF, 0x4); /* Opcode FF /4 */
13134 ins_encode( OpcP, RegOpc(jump_target) );
13135 ins_pipe( pipe_jmp );
13136 %}
13137
13138
13139 // Tail Jump; remove the return address; jump to target.
13140 // TailCall above leaves the return address around.
13141 instruct tailjmpInd(eRegP_no_EBP jump_target, eAXRegP ex_oop) %{
13142 match( TailJump jump_target ex_oop );
13143 ins_cost(300);
13144 format %{ "POP EDX\t# pop return address into dummy\n\t"
13145 "JMP $jump_target " %}
13146 opcode(0xFF, 0x4); /* Opcode FF /4 */
13147 ins_encode( enc_pop_rdx,
13148 OpcP, RegOpc(jump_target) );
13149 ins_pipe( pipe_jmp );
13150 %}
13151
13152 // Create exception oop: created by stack-crawling runtime code.
13153 // Created exception is now available to this handler, and is setup
13154 // just prior to jumping to this handler. No code emitted.
13155 instruct CreateException( eAXRegP ex_oop )
13156 %{
13157 match(Set ex_oop (CreateEx));
13158
13159 size(0);
13160 // use the following format syntax
13161 format %{ "# exception oop is in EAX; no code emitted" %}
13162 ins_encode();
13163 ins_pipe( empty );
13164 %}
13165
13166
13167 // Rethrow exception:
13168 // The exception oop will come in the first argument position.
13169 // Then JUMP (not call) to the rethrow stub code.
13170 instruct RethrowException()
13171 %{
13172 match(Rethrow);
13173
13174 // use the following format syntax
13175 format %{ "JMP rethrow_stub" %}
13176 ins_encode(enc_rethrow);
13177 ins_pipe( pipe_jmp );
13178 %}
13179
13180 // inlined locking and unlocking
13181
13182
13183 instruct cmpFastLock( eFlagsReg cr, eRegP object, eBXRegP box, eAXRegI tmp, eRegP scr) %{
13184 match( Set cr (FastLock object box) );
13185 effect( TEMP tmp, TEMP scr, USE_KILL box );
13186 ins_cost(300);
13187 format %{ "FASTLOCK $object,$box\t! kills $box,$tmp,$scr" %}
13188 ins_encode( Fast_Lock(object,box,tmp,scr) );
13189 ins_pipe( pipe_slow );
13190 %}
13191
13192 instruct cmpFastUnlock( eFlagsReg cr, eRegP object, eAXRegP box, eRegP tmp ) %{
13193 match( Set cr (FastUnlock object box) );
13194 effect( TEMP tmp, USE_KILL box );
13195 ins_cost(300);
13196 format %{ "FASTUNLOCK $object,$box\t! kills $box,$tmp" %}
13197 ins_encode( Fast_Unlock(object,box,tmp) );
13198 ins_pipe( pipe_slow );
13199 %}
13200
13201
13202
13203 // ============================================================================
13204 // Safepoint Instruction
13205 instruct safePoint_poll(eFlagsReg cr) %{
13206 match(SafePoint);
13207 effect(KILL cr);
13208
13209 // TODO-FIXME: we currently poll at offset 0 of the safepoint polling page.
13210 // On SPARC that might be acceptable as we can generate the address with
13211 // just a sethi, saving an or. By polling at offset 0 we can end up
13212 // putting additional pressure on the index-0 in the D$. Because of
13213 // alignment (just like the situation at hand) the lower indices tend
13214 // to see more traffic. It'd be better to change the polling address
13215 // to offset 0 of the last $line in the polling page.
13216
13217 format %{ "TSTL #polladdr,EAX\t! Safepoint: poll for GC" %}
13218 ins_cost(125);
13219 size(6) ;
13220 ins_encode( Safepoint_Poll() );
13221 ins_pipe( ialu_reg_mem );
13222 %}
13223
13224
13225 // ============================================================================
13226 // This name is KNOWN by the ADLC and cannot be changed.
13227 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type
13228 // for this guy.
13229 instruct tlsLoadP(eRegP dst, eFlagsReg cr) %{
13230 match(Set dst (ThreadLocal));
13231 effect(DEF dst, KILL cr);
13232
13233 format %{ "MOV $dst, Thread::current()" %}
13234 ins_encode %{
13235 Register dstReg = as_Register($dst$$reg);
13236 __ get_thread(dstReg);
13237 %}
13238 ins_pipe( ialu_reg_fat );
13239 %}
13240
13241
13242
13243 //----------PEEPHOLE RULES-----------------------------------------------------
13244 // These must follow all instruction definitions as they use the names
13245 // defined in the instructions definitions.
13246 //
13247 // peepmatch ( root_instr_name [preceding_instruction]* );
13248 //
13249 // peepconstraint %{
13250 // (instruction_number.operand_name relational_op instruction_number.operand_name
13251 // [, ...] );
13252 // // instruction numbers are zero-based using left to right order in peepmatch
13253 //
13254 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
13255 // // provide an instruction_number.operand_name for each operand that appears
13256 // // in the replacement instruction's match rule
13257 //
13258 // ---------VM FLAGS---------------------------------------------------------
13259 //
13260 // All peephole optimizations can be turned off using -XX:-OptoPeephole
13261 //
13262 // Each peephole rule is given an identifying number starting with zero and
13263 // increasing by one in the order seen by the parser. An individual peephole
13264 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
13265 // on the command-line.
13266 //
13267 // ---------CURRENT LIMITATIONS----------------------------------------------
13268 //
13269 // Only match adjacent instructions in same basic block
13270 // Only equality constraints
13271 // Only constraints between operands, not (0.dest_reg == EAX_enc)
13272 // Only one replacement instruction
13273 //
13274 // ---------EXAMPLE----------------------------------------------------------
13275 //
13276 // // pertinent parts of existing instructions in architecture description
13277 // instruct movI(rRegI dst, rRegI src) %{
13278 // match(Set dst (CopyI src));
13279 // %}
13280 //
13281 // instruct incI_eReg(rRegI dst, immI1 src, eFlagsReg cr) %{
13282 // match(Set dst (AddI dst src));
13283 // effect(KILL cr);
13284 // %}
13285 //
13286 // // Change (inc mov) to lea
13287 // peephole %{
13288 // // increment preceeded by register-register move
13289 // peepmatch ( incI_eReg movI );
13290 // // require that the destination register of the increment
13291 // // match the destination register of the move
13292 // peepconstraint ( 0.dst == 1.dst );
13293 // // construct a replacement instruction that sets
13294 // // the destination to ( move's source register + one )
13295 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13296 // %}
13297 //
13298 // Implementation no longer uses movX instructions since
13299 // machine-independent system no longer uses CopyX nodes.
13300 //
13301 // peephole %{
13302 // peepmatch ( incI_eReg movI );
13303 // peepconstraint ( 0.dst == 1.dst );
13304 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13305 // %}
13306 //
13307 // peephole %{
13308 // peepmatch ( decI_eReg movI );
13309 // peepconstraint ( 0.dst == 1.dst );
13310 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13311 // %}
13312 //
13313 // peephole %{
13314 // peepmatch ( addI_eReg_imm movI );
13315 // peepconstraint ( 0.dst == 1.dst );
13316 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13317 // %}
13318 //
13319 // peephole %{
13320 // peepmatch ( addP_eReg_imm movP );
13321 // peepconstraint ( 0.dst == 1.dst );
13322 // peepreplace ( leaP_eReg_immI( 0.dst 1.src 0.src ) );
13323 // %}
13324
13325 // // Change load of spilled value to only a spill
13326 // instruct storeI(memory mem, rRegI src) %{
13327 // match(Set mem (StoreI mem src));
13328 // %}
13329 //
13330 // instruct loadI(rRegI dst, memory mem) %{
13331 // match(Set dst (LoadI mem));
13332 // %}
13333 //
13334 peephole %{
13335 peepmatch ( loadI storeI );
13336 peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem );
13337 peepreplace ( storeI( 1.mem 1.mem 1.src ) );
13338 %}
13339
13340 //----------SMARTSPILL RULES---------------------------------------------------
13341 // These must follow all instruction definitions as they use the names
13342 // defined in the instructions definitions.