10721 %}
10722
10723 // Manifest a CmpL result in an integer register. Very painful.
10724 // This is the test to avoid.
10725 instruct cmpL3_reg_reg(rRegI dst, rRegL src1, rRegL src2, rFlagsReg flags)
10726 %{
10727 match(Set dst (CmpL3 src1 src2));
10728 effect(KILL flags);
10729
10730 ins_cost(275); // XXX
10731 format %{ "cmpq $src1, $src2\t# CmpL3\n\t"
10732 "movl $dst, -1\n\t"
10733 "jl,s done\n\t"
10734 "setne $dst\n\t"
10735 "movzbl $dst, $dst\n\t"
10736 "done:" %}
10737 ins_encode(cmpl3_flag(src1, src2, dst));
10738 ins_pipe(pipe_slow);
10739 %}
10740
10741 //----------Max and Min--------------------------------------------------------
10742 // Min Instructions
10743
10744 instruct cmovI_reg_g(rRegI dst, rRegI src, rFlagsReg cr)
10745 %{
10746 effect(USE_DEF dst, USE src, USE cr);
10747
10748 format %{ "cmovlgt $dst, $src\t# min" %}
10749 opcode(0x0F, 0x4F);
10750 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
10751 ins_pipe(pipe_cmov_reg);
10752 %}
10753
10754
10755 instruct minI_rReg(rRegI dst, rRegI src)
10756 %{
10757 match(Set dst (MinI dst src));
10758
10759 ins_cost(200);
10760 expand %{
|
10721 %}
10722
10723 // Manifest a CmpL result in an integer register. Very painful.
10724 // This is the test to avoid.
10725 instruct cmpL3_reg_reg(rRegI dst, rRegL src1, rRegL src2, rFlagsReg flags)
10726 %{
10727 match(Set dst (CmpL3 src1 src2));
10728 effect(KILL flags);
10729
10730 ins_cost(275); // XXX
10731 format %{ "cmpq $src1, $src2\t# CmpL3\n\t"
10732 "movl $dst, -1\n\t"
10733 "jl,s done\n\t"
10734 "setne $dst\n\t"
10735 "movzbl $dst, $dst\n\t"
10736 "done:" %}
10737 ins_encode(cmpl3_flag(src1, src2, dst));
10738 ins_pipe(pipe_slow);
10739 %}
10740
10741 // Unsigned long compare Instructions; really, same as signed long except they
10742 // produce an rFlagsRegU instead of rFlagsReg.
10743 instruct compUL_rReg(rFlagsRegU cr, rRegL op1, rRegL op2)
10744 %{
10745 match(Set cr (CmpUL op1 op2));
10746
10747 format %{ "cmpq $op1, $op2\t# unsigned" %}
10748 opcode(0x3B); /* Opcode 3B /r */
10749 ins_encode(REX_reg_reg_wide(op1, op2), OpcP, reg_reg(op1, op2));
10750 ins_pipe(ialu_cr_reg_reg);
10751 %}
10752
10753 instruct compUL_rReg_imm(rFlagsRegU cr, rRegL op1, immL32 op2)
10754 %{
10755 match(Set cr (CmpUL op1 op2));
10756
10757 format %{ "cmpq $op1, $op2\t# unsigned" %}
10758 opcode(0x81, 0x07); /* Opcode 81 /7 */
10759 ins_encode(OpcSErm_wide(op1, op2), Con8or32(op2));
10760 ins_pipe(ialu_cr_reg_imm);
10761 %}
10762
10763 instruct compUL_rReg_mem(rFlagsRegU cr, rRegL op1, memory op2)
10764 %{
10765 match(Set cr (CmpUL op1 (LoadL op2)));
10766
10767 format %{ "cmpq $op1, $op2\t# unsigned" %}
10768 opcode(0x3B); /* Opcode 3B /r */
10769 ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2));
10770 ins_pipe(ialu_cr_reg_mem);
10771 %}
10772
10773 instruct testUL_reg(rFlagsRegU cr, rRegL src, immL0 zero)
10774 %{
10775 match(Set cr (CmpUL src zero));
10776
10777 format %{ "testq $src, $src\t# unsigned" %}
10778 opcode(0x85);
10779 ins_encode(REX_reg_reg_wide(src, src), OpcP, reg_reg(src, src));
10780 ins_pipe(ialu_cr_reg_imm);
10781 %}
10782
10783 //----------Max and Min--------------------------------------------------------
10784 // Min Instructions
10785
10786 instruct cmovI_reg_g(rRegI dst, rRegI src, rFlagsReg cr)
10787 %{
10788 effect(USE_DEF dst, USE src, USE cr);
10789
10790 format %{ "cmovlgt $dst, $src\t# min" %}
10791 opcode(0x0F, 0x4F);
10792 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
10793 ins_pipe(pipe_cmov_reg);
10794 %}
10795
10796
10797 instruct minI_rReg(rRegI dst, rRegI src)
10798 %{
10799 match(Set dst (MinI dst src));
10800
10801 ins_cost(200);
10802 expand %{
|