1 // 2 // Copyright (c) 2011, 2014, Oracle and/or its affiliates. All rights reserved. 3 // Copyright 2012, 2014 SAP AG. All rights reserved. 4 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 5 // 6 // This code is free software; you can redistribute it and/or modify it 7 // under the terms of the GNU General Public License version 2 only, as 8 // published by the Free Software Foundation. 9 // 10 // This code is distributed in the hope that it will be useful, but WITHOUT 11 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 13 // version 2 for more details (a copy is included in the LICENSE file that 14 // accompanied this code). 15 // 16 // You should have received a copy of the GNU General Public License version 17 // 2 along with this work; if not, write to the Free Software Foundation, 18 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 19 // 20 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 21 // or visit www.oracle.com if you need additional information or have any 22 // questions. 23 // 24 // 25 26 // 27 // PPC64 Architecture Description File 28 // 29 30 //----------REGISTER DEFINITION BLOCK------------------------------------------ 31 // This information is used by the matcher and the register allocator to 32 // describe individual registers and classes of registers within the target 33 // architecture. 34 register %{ 35 //----------Architecture Description Register Definitions---------------------- 36 // General Registers 37 // "reg_def" name (register save type, C convention save type, 38 // ideal register type, encoding); 39 // 40 // Register Save Types: 41 // 42 // NS = No-Save: The register allocator assumes that these registers 43 // can be used without saving upon entry to the method, & 44 // that they do not need to be saved at call sites. 45 // 46 // SOC = Save-On-Call: The register allocator assumes that these registers 47 // can be used without saving upon entry to the method, 48 // but that they must be saved at call sites. 49 // These are called "volatiles" on ppc. 50 // 51 // SOE = Save-On-Entry: The register allocator assumes that these registers 52 // must be saved before using them upon entry to the 53 // method, but they do not need to be saved at call 54 // sites. 55 // These are called "nonvolatiles" on ppc. 56 // 57 // AS = Always-Save: The register allocator assumes that these registers 58 // must be saved before using them upon entry to the 59 // method, & that they must be saved at call sites. 60 // 61 // Ideal Register Type is used to determine how to save & restore a 62 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get 63 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI. 64 // 65 // The encoding number is the actual bit-pattern placed into the opcodes. 66 // 67 // PPC64 register definitions, based on the 64-bit PowerPC ELF ABI 68 // Supplement Version 1.7 as of 2003-10-29. 69 // 70 // For each 64-bit register we must define two registers: the register 71 // itself, e.g. R3, and a corresponding virtual other (32-bit-)'half', 72 // e.g. R3_H, which is needed by the allocator, but is not used 73 // for stores, loads, etc. 74 75 // ---------------------------- 76 // Integer/Long Registers 77 // ---------------------------- 78 79 // PPC64 has 32 64-bit integer registers. 80 81 // types: v = volatile, nv = non-volatile, s = system 82 reg_def R0 ( SOC, SOC, Op_RegI, 0, R0->as_VMReg() ); // v used in prologs 83 reg_def R0_H ( SOC, SOC, Op_RegI, 99, R0->as_VMReg()->next() ); 84 reg_def R1 ( NS, NS, Op_RegI, 1, R1->as_VMReg() ); // s SP 85 reg_def R1_H ( NS, NS, Op_RegI, 99, R1->as_VMReg()->next() ); 86 reg_def R2 ( SOC, SOC, Op_RegI, 2, R2->as_VMReg() ); // v TOC 87 reg_def R2_H ( SOC, SOC, Op_RegI, 99, R2->as_VMReg()->next() ); 88 reg_def R3 ( SOC, SOC, Op_RegI, 3, R3->as_VMReg() ); // v iarg1 & iret 89 reg_def R3_H ( SOC, SOC, Op_RegI, 99, R3->as_VMReg()->next() ); 90 reg_def R4 ( SOC, SOC, Op_RegI, 4, R4->as_VMReg() ); // iarg2 91 reg_def R4_H ( SOC, SOC, Op_RegI, 99, R4->as_VMReg()->next() ); 92 reg_def R5 ( SOC, SOC, Op_RegI, 5, R5->as_VMReg() ); // v iarg3 93 reg_def R5_H ( SOC, SOC, Op_RegI, 99, R5->as_VMReg()->next() ); 94 reg_def R6 ( SOC, SOC, Op_RegI, 6, R6->as_VMReg() ); // v iarg4 95 reg_def R6_H ( SOC, SOC, Op_RegI, 99, R6->as_VMReg()->next() ); 96 reg_def R7 ( SOC, SOC, Op_RegI, 7, R7->as_VMReg() ); // v iarg5 97 reg_def R7_H ( SOC, SOC, Op_RegI, 99, R7->as_VMReg()->next() ); 98 reg_def R8 ( SOC, SOC, Op_RegI, 8, R8->as_VMReg() ); // v iarg6 99 reg_def R8_H ( SOC, SOC, Op_RegI, 99, R8->as_VMReg()->next() ); 100 reg_def R9 ( SOC, SOC, Op_RegI, 9, R9->as_VMReg() ); // v iarg7 101 reg_def R9_H ( SOC, SOC, Op_RegI, 99, R9->as_VMReg()->next() ); 102 reg_def R10 ( SOC, SOC, Op_RegI, 10, R10->as_VMReg() ); // v iarg8 103 reg_def R10_H( SOC, SOC, Op_RegI, 99, R10->as_VMReg()->next()); 104 reg_def R11 ( SOC, SOC, Op_RegI, 11, R11->as_VMReg() ); // v ENV / scratch 105 reg_def R11_H( SOC, SOC, Op_RegI, 99, R11->as_VMReg()->next()); 106 reg_def R12 ( SOC, SOC, Op_RegI, 12, R12->as_VMReg() ); // v scratch 107 reg_def R12_H( SOC, SOC, Op_RegI, 99, R12->as_VMReg()->next()); 108 reg_def R13 ( NS, NS, Op_RegI, 13, R13->as_VMReg() ); // s system thread id 109 reg_def R13_H( NS, NS, Op_RegI, 99, R13->as_VMReg()->next()); 110 reg_def R14 ( SOC, SOE, Op_RegI, 14, R14->as_VMReg() ); // nv 111 reg_def R14_H( SOC, SOE, Op_RegI, 99, R14->as_VMReg()->next()); 112 reg_def R15 ( SOC, SOE, Op_RegI, 15, R15->as_VMReg() ); // nv 113 reg_def R15_H( SOC, SOE, Op_RegI, 99, R15->as_VMReg()->next()); 114 reg_def R16 ( SOC, SOE, Op_RegI, 16, R16->as_VMReg() ); // nv 115 reg_def R16_H( SOC, SOE, Op_RegI, 99, R16->as_VMReg()->next()); 116 reg_def R17 ( SOC, SOE, Op_RegI, 17, R17->as_VMReg() ); // nv 117 reg_def R17_H( SOC, SOE, Op_RegI, 99, R17->as_VMReg()->next()); 118 reg_def R18 ( SOC, SOE, Op_RegI, 18, R18->as_VMReg() ); // nv 119 reg_def R18_H( SOC, SOE, Op_RegI, 99, R18->as_VMReg()->next()); 120 reg_def R19 ( SOC, SOE, Op_RegI, 19, R19->as_VMReg() ); // nv 121 reg_def R19_H( SOC, SOE, Op_RegI, 99, R19->as_VMReg()->next()); 122 reg_def R20 ( SOC, SOE, Op_RegI, 20, R20->as_VMReg() ); // nv 123 reg_def R20_H( SOC, SOE, Op_RegI, 99, R20->as_VMReg()->next()); 124 reg_def R21 ( SOC, SOE, Op_RegI, 21, R21->as_VMReg() ); // nv 125 reg_def R21_H( SOC, SOE, Op_RegI, 99, R21->as_VMReg()->next()); 126 reg_def R22 ( SOC, SOE, Op_RegI, 22, R22->as_VMReg() ); // nv 127 reg_def R22_H( SOC, SOE, Op_RegI, 99, R22->as_VMReg()->next()); 128 reg_def R23 ( SOC, SOE, Op_RegI, 23, R23->as_VMReg() ); // nv 129 reg_def R23_H( SOC, SOE, Op_RegI, 99, R23->as_VMReg()->next()); 130 reg_def R24 ( SOC, SOE, Op_RegI, 24, R24->as_VMReg() ); // nv 131 reg_def R24_H( SOC, SOE, Op_RegI, 99, R24->as_VMReg()->next()); 132 reg_def R25 ( SOC, SOE, Op_RegI, 25, R25->as_VMReg() ); // nv 133 reg_def R25_H( SOC, SOE, Op_RegI, 99, R25->as_VMReg()->next()); 134 reg_def R26 ( SOC, SOE, Op_RegI, 26, R26->as_VMReg() ); // nv 135 reg_def R26_H( SOC, SOE, Op_RegI, 99, R26->as_VMReg()->next()); 136 reg_def R27 ( SOC, SOE, Op_RegI, 27, R27->as_VMReg() ); // nv 137 reg_def R27_H( SOC, SOE, Op_RegI, 99, R27->as_VMReg()->next()); 138 reg_def R28 ( SOC, SOE, Op_RegI, 28, R28->as_VMReg() ); // nv 139 reg_def R28_H( SOC, SOE, Op_RegI, 99, R28->as_VMReg()->next()); 140 reg_def R29 ( SOC, SOE, Op_RegI, 29, R29->as_VMReg() ); // nv 141 reg_def R29_H( SOC, SOE, Op_RegI, 99, R29->as_VMReg()->next()); 142 reg_def R30 ( SOC, SOE, Op_RegI, 30, R30->as_VMReg() ); // nv 143 reg_def R30_H( SOC, SOE, Op_RegI, 99, R30->as_VMReg()->next()); 144 reg_def R31 ( SOC, SOE, Op_RegI, 31, R31->as_VMReg() ); // nv 145 reg_def R31_H( SOC, SOE, Op_RegI, 99, R31->as_VMReg()->next()); 146 147 148 // ---------------------------- 149 // Float/Double Registers 150 // ---------------------------- 151 152 // Double Registers 153 // The rules of ADL require that double registers be defined in pairs. 154 // Each pair must be two 32-bit values, but not necessarily a pair of 155 // single float registers. In each pair, ADLC-assigned register numbers 156 // must be adjacent, with the lower number even. Finally, when the 157 // CPU stores such a register pair to memory, the word associated with 158 // the lower ADLC-assigned number must be stored to the lower address. 159 160 // PPC64 has 32 64-bit floating-point registers. Each can store a single 161 // or double precision floating-point value. 162 163 // types: v = volatile, nv = non-volatile, s = system 164 reg_def F0 ( SOC, SOC, Op_RegF, 0, F0->as_VMReg() ); // v scratch 165 reg_def F0_H ( SOC, SOC, Op_RegF, 99, F0->as_VMReg()->next() ); 166 reg_def F1 ( SOC, SOC, Op_RegF, 1, F1->as_VMReg() ); // v farg1 & fret 167 reg_def F1_H ( SOC, SOC, Op_RegF, 99, F1->as_VMReg()->next() ); 168 reg_def F2 ( SOC, SOC, Op_RegF, 2, F2->as_VMReg() ); // v farg2 169 reg_def F2_H ( SOC, SOC, Op_RegF, 99, F2->as_VMReg()->next() ); 170 reg_def F3 ( SOC, SOC, Op_RegF, 3, F3->as_VMReg() ); // v farg3 171 reg_def F3_H ( SOC, SOC, Op_RegF, 99, F3->as_VMReg()->next() ); 172 reg_def F4 ( SOC, SOC, Op_RegF, 4, F4->as_VMReg() ); // v farg4 173 reg_def F4_H ( SOC, SOC, Op_RegF, 99, F4->as_VMReg()->next() ); 174 reg_def F5 ( SOC, SOC, Op_RegF, 5, F5->as_VMReg() ); // v farg5 175 reg_def F5_H ( SOC, SOC, Op_RegF, 99, F5->as_VMReg()->next() ); 176 reg_def F6 ( SOC, SOC, Op_RegF, 6, F6->as_VMReg() ); // v farg6 177 reg_def F6_H ( SOC, SOC, Op_RegF, 99, F6->as_VMReg()->next() ); 178 reg_def F7 ( SOC, SOC, Op_RegF, 7, F7->as_VMReg() ); // v farg7 179 reg_def F7_H ( SOC, SOC, Op_RegF, 99, F7->as_VMReg()->next() ); 180 reg_def F8 ( SOC, SOC, Op_RegF, 8, F8->as_VMReg() ); // v farg8 181 reg_def F8_H ( SOC, SOC, Op_RegF, 99, F8->as_VMReg()->next() ); 182 reg_def F9 ( SOC, SOC, Op_RegF, 9, F9->as_VMReg() ); // v farg9 183 reg_def F9_H ( SOC, SOC, Op_RegF, 99, F9->as_VMReg()->next() ); 184 reg_def F10 ( SOC, SOC, Op_RegF, 10, F10->as_VMReg() ); // v farg10 185 reg_def F10_H( SOC, SOC, Op_RegF, 99, F10->as_VMReg()->next()); 186 reg_def F11 ( SOC, SOC, Op_RegF, 11, F11->as_VMReg() ); // v farg11 187 reg_def F11_H( SOC, SOC, Op_RegF, 99, F11->as_VMReg()->next()); 188 reg_def F12 ( SOC, SOC, Op_RegF, 12, F12->as_VMReg() ); // v farg12 189 reg_def F12_H( SOC, SOC, Op_RegF, 99, F12->as_VMReg()->next()); 190 reg_def F13 ( SOC, SOC, Op_RegF, 13, F13->as_VMReg() ); // v farg13 191 reg_def F13_H( SOC, SOC, Op_RegF, 99, F13->as_VMReg()->next()); 192 reg_def F14 ( SOC, SOE, Op_RegF, 14, F14->as_VMReg() ); // nv 193 reg_def F14_H( SOC, SOE, Op_RegF, 99, F14->as_VMReg()->next()); 194 reg_def F15 ( SOC, SOE, Op_RegF, 15, F15->as_VMReg() ); // nv 195 reg_def F15_H( SOC, SOE, Op_RegF, 99, F15->as_VMReg()->next()); 196 reg_def F16 ( SOC, SOE, Op_RegF, 16, F16->as_VMReg() ); // nv 197 reg_def F16_H( SOC, SOE, Op_RegF, 99, F16->as_VMReg()->next()); 198 reg_def F17 ( SOC, SOE, Op_RegF, 17, F17->as_VMReg() ); // nv 199 reg_def F17_H( SOC, SOE, Op_RegF, 99, F17->as_VMReg()->next()); 200 reg_def F18 ( SOC, SOE, Op_RegF, 18, F18->as_VMReg() ); // nv 201 reg_def F18_H( SOC, SOE, Op_RegF, 99, F18->as_VMReg()->next()); 202 reg_def F19 ( SOC, SOE, Op_RegF, 19, F19->as_VMReg() ); // nv 203 reg_def F19_H( SOC, SOE, Op_RegF, 99, F19->as_VMReg()->next()); 204 reg_def F20 ( SOC, SOE, Op_RegF, 20, F20->as_VMReg() ); // nv 205 reg_def F20_H( SOC, SOE, Op_RegF, 99, F20->as_VMReg()->next()); 206 reg_def F21 ( SOC, SOE, Op_RegF, 21, F21->as_VMReg() ); // nv 207 reg_def F21_H( SOC, SOE, Op_RegF, 99, F21->as_VMReg()->next()); 208 reg_def F22 ( SOC, SOE, Op_RegF, 22, F22->as_VMReg() ); // nv 209 reg_def F22_H( SOC, SOE, Op_RegF, 99, F22->as_VMReg()->next()); 210 reg_def F23 ( SOC, SOE, Op_RegF, 23, F23->as_VMReg() ); // nv 211 reg_def F23_H( SOC, SOE, Op_RegF, 99, F23->as_VMReg()->next()); 212 reg_def F24 ( SOC, SOE, Op_RegF, 24, F24->as_VMReg() ); // nv 213 reg_def F24_H( SOC, SOE, Op_RegF, 99, F24->as_VMReg()->next()); 214 reg_def F25 ( SOC, SOE, Op_RegF, 25, F25->as_VMReg() ); // nv 215 reg_def F25_H( SOC, SOE, Op_RegF, 99, F25->as_VMReg()->next()); 216 reg_def F26 ( SOC, SOE, Op_RegF, 26, F26->as_VMReg() ); // nv 217 reg_def F26_H( SOC, SOE, Op_RegF, 99, F26->as_VMReg()->next()); 218 reg_def F27 ( SOC, SOE, Op_RegF, 27, F27->as_VMReg() ); // nv 219 reg_def F27_H( SOC, SOE, Op_RegF, 99, F27->as_VMReg()->next()); 220 reg_def F28 ( SOC, SOE, Op_RegF, 28, F28->as_VMReg() ); // nv 221 reg_def F28_H( SOC, SOE, Op_RegF, 99, F28->as_VMReg()->next()); 222 reg_def F29 ( SOC, SOE, Op_RegF, 29, F29->as_VMReg() ); // nv 223 reg_def F29_H( SOC, SOE, Op_RegF, 99, F29->as_VMReg()->next()); 224 reg_def F30 ( SOC, SOE, Op_RegF, 30, F30->as_VMReg() ); // nv 225 reg_def F30_H( SOC, SOE, Op_RegF, 99, F30->as_VMReg()->next()); 226 reg_def F31 ( SOC, SOE, Op_RegF, 31, F31->as_VMReg() ); // nv 227 reg_def F31_H( SOC, SOE, Op_RegF, 99, F31->as_VMReg()->next()); 228 229 // ---------------------------- 230 // Special Registers 231 // ---------------------------- 232 233 // Condition Codes Flag Registers 234 235 // PPC64 has 8 condition code "registers" which are all contained 236 // in the CR register. 237 238 // types: v = volatile, nv = non-volatile, s = system 239 reg_def CCR0(SOC, SOC, Op_RegFlags, 0, CCR0->as_VMReg()); // v 240 reg_def CCR1(SOC, SOC, Op_RegFlags, 1, CCR1->as_VMReg()); // v 241 reg_def CCR2(SOC, SOC, Op_RegFlags, 2, CCR2->as_VMReg()); // nv 242 reg_def CCR3(SOC, SOC, Op_RegFlags, 3, CCR3->as_VMReg()); // nv 243 reg_def CCR4(SOC, SOC, Op_RegFlags, 4, CCR4->as_VMReg()); // nv 244 reg_def CCR5(SOC, SOC, Op_RegFlags, 5, CCR5->as_VMReg()); // v 245 reg_def CCR6(SOC, SOC, Op_RegFlags, 6, CCR6->as_VMReg()); // v 246 reg_def CCR7(SOC, SOC, Op_RegFlags, 7, CCR7->as_VMReg()); // v 247 248 // Special registers of PPC64 249 250 reg_def SR_XER( SOC, SOC, Op_RegP, 0, SR_XER->as_VMReg()); // v 251 reg_def SR_LR( SOC, SOC, Op_RegP, 1, SR_LR->as_VMReg()); // v 252 reg_def SR_CTR( SOC, SOC, Op_RegP, 2, SR_CTR->as_VMReg()); // v 253 reg_def SR_VRSAVE( SOC, SOC, Op_RegP, 3, SR_VRSAVE->as_VMReg()); // v 254 reg_def SR_SPEFSCR(SOC, SOC, Op_RegP, 4, SR_SPEFSCR->as_VMReg()); // v 255 reg_def SR_PPR( SOC, SOC, Op_RegP, 5, SR_PPR->as_VMReg()); // v 256 257 258 // ---------------------------- 259 // Specify priority of register selection within phases of register 260 // allocation. Highest priority is first. A useful heuristic is to 261 // give registers a low priority when they are required by machine 262 // instructions, like EAX and EDX on I486, and choose no-save registers 263 // before save-on-call, & save-on-call before save-on-entry. Registers 264 // which participate in fixed calling sequences should come last. 265 // Registers which are used as pairs must fall on an even boundary. 266 267 // It's worth about 1% on SPEC geomean to get this right. 268 269 // Chunk0, chunk1, and chunk2 form the MachRegisterNumbers enumeration 270 // in adGlobals_ppc64.hpp which defines the <register>_num values, e.g. 271 // R3_num. Therefore, R3_num may not be (and in reality is not) 272 // the same as R3->encoding()! Furthermore, we cannot make any 273 // assumptions on ordering, e.g. R3_num may be less than R2_num. 274 // Additionally, the function 275 // static enum RC rc_class(OptoReg::Name reg ) 276 // maps a given <register>_num value to its chunk type (except for flags) 277 // and its current implementation relies on chunk0 and chunk1 having a 278 // size of 64 each. 279 280 // If you change this allocation class, please have a look at the 281 // default values for the parameters RoundRobinIntegerRegIntervalStart 282 // and RoundRobinFloatRegIntervalStart 283 284 alloc_class chunk0 ( 285 // Chunk0 contains *all* 64 integer registers halves. 286 287 // "non-volatile" registers 288 R14, R14_H, 289 R15, R15_H, 290 R17, R17_H, 291 R18, R18_H, 292 R19, R19_H, 293 R20, R20_H, 294 R21, R21_H, 295 R22, R22_H, 296 R23, R23_H, 297 R24, R24_H, 298 R25, R25_H, 299 R26, R26_H, 300 R27, R27_H, 301 R28, R28_H, 302 R29, R29_H, 303 R30, R30_H, 304 R31, R31_H, 305 306 // scratch/special registers 307 R11, R11_H, 308 R12, R12_H, 309 310 // argument registers 311 R10, R10_H, 312 R9, R9_H, 313 R8, R8_H, 314 R7, R7_H, 315 R6, R6_H, 316 R5, R5_H, 317 R4, R4_H, 318 R3, R3_H, 319 320 // special registers, not available for allocation 321 R16, R16_H, // R16_thread 322 R13, R13_H, // system thread id 323 R2, R2_H, // may be used for TOC 324 R1, R1_H, // SP 325 R0, R0_H // R0 (scratch) 326 ); 327 328 // If you change this allocation class, please have a look at the 329 // default values for the parameters RoundRobinIntegerRegIntervalStart 330 // and RoundRobinFloatRegIntervalStart 331 332 alloc_class chunk1 ( 333 // Chunk1 contains *all* 64 floating-point registers halves. 334 335 // scratch register 336 F0, F0_H, 337 338 // argument registers 339 F13, F13_H, 340 F12, F12_H, 341 F11, F11_H, 342 F10, F10_H, 343 F9, F9_H, 344 F8, F8_H, 345 F7, F7_H, 346 F6, F6_H, 347 F5, F5_H, 348 F4, F4_H, 349 F3, F3_H, 350 F2, F2_H, 351 F1, F1_H, 352 353 // non-volatile registers 354 F14, F14_H, 355 F15, F15_H, 356 F16, F16_H, 357 F17, F17_H, 358 F18, F18_H, 359 F19, F19_H, 360 F20, F20_H, 361 F21, F21_H, 362 F22, F22_H, 363 F23, F23_H, 364 F24, F24_H, 365 F25, F25_H, 366 F26, F26_H, 367 F27, F27_H, 368 F28, F28_H, 369 F29, F29_H, 370 F30, F30_H, 371 F31, F31_H 372 ); 373 374 alloc_class chunk2 ( 375 // Chunk2 contains *all* 8 condition code registers. 376 377 CCR0, 378 CCR1, 379 CCR2, 380 CCR3, 381 CCR4, 382 CCR5, 383 CCR6, 384 CCR7 385 ); 386 387 alloc_class chunk3 ( 388 // special registers 389 // These registers are not allocated, but used for nodes generated by postalloc expand. 390 SR_XER, 391 SR_LR, 392 SR_CTR, 393 SR_VRSAVE, 394 SR_SPEFSCR, 395 SR_PPR 396 ); 397 398 //-------Architecture Description Register Classes----------------------- 399 400 // Several register classes are automatically defined based upon 401 // information in this architecture description. 402 403 // 1) reg_class inline_cache_reg ( as defined in frame section ) 404 // 2) reg_class compiler_method_oop_reg ( as defined in frame section ) 405 // 2) reg_class interpreter_method_oop_reg ( as defined in frame section ) 406 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ ) 407 // 408 409 // ---------------------------- 410 // 32 Bit Register Classes 411 // ---------------------------- 412 413 // We specify registers twice, once as read/write, and once read-only. 414 // We use the read-only registers for source operands. With this, we 415 // can include preset read only registers in this class, as a hard-coded 416 // '0'-register. (We used to simulate this on ppc.) 417 418 // 32 bit registers that can be read and written i.e. these registers 419 // can be dest (or src) of normal instructions. 420 reg_class bits32_reg_rw( 421 /*R0*/ // R0 422 /*R1*/ // SP 423 R2, // TOC 424 R3, 425 R4, 426 R5, 427 R6, 428 R7, 429 R8, 430 R9, 431 R10, 432 R11, 433 R12, 434 /*R13*/ // system thread id 435 R14, 436 R15, 437 /*R16*/ // R16_thread 438 R17, 439 R18, 440 R19, 441 R20, 442 R21, 443 R22, 444 R23, 445 R24, 446 R25, 447 R26, 448 R27, 449 R28, 450 /*R29*/ // global TOC 451 /*R30*/ // Narrow Oop Base 452 R31 453 ); 454 455 // 32 bit registers that can only be read i.e. these registers can 456 // only be src of all instructions. 457 reg_class bits32_reg_ro( 458 /*R0*/ // R0 459 /*R1*/ // SP 460 R2 // TOC 461 R3, 462 R4, 463 R5, 464 R6, 465 R7, 466 R8, 467 R9, 468 R10, 469 R11, 470 R12, 471 /*R13*/ // system thread id 472 R14, 473 R15, 474 /*R16*/ // R16_thread 475 R17, 476 R18, 477 R19, 478 R20, 479 R21, 480 R22, 481 R23, 482 R24, 483 R25, 484 R26, 485 R27, 486 R28, 487 /*R29*/ 488 /*R30*/ // Narrow Oop Base 489 R31 490 ); 491 492 // Complement-required-in-pipeline operands for narrow oops. 493 reg_class bits32_reg_ro_not_complement ( 494 /*R0*/ // R0 495 R1, // SP 496 R2, // TOC 497 R3, 498 R4, 499 R5, 500 R6, 501 R7, 502 R8, 503 R9, 504 R10, 505 R11, 506 R12, 507 /*R13,*/ // system thread id 508 R14, 509 R15, 510 R16, // R16_thread 511 R17, 512 R18, 513 R19, 514 R20, 515 R21, 516 R22, 517 /*R23, 518 R24, 519 R25, 520 R26, 521 R27, 522 R28,*/ 523 /*R29,*/ // TODO: let allocator handle TOC!! 524 /*R30,*/ 525 R31 526 ); 527 528 // Complement-required-in-pipeline operands for narrow oops. 529 // See 64-bit declaration. 530 reg_class bits32_reg_ro_complement ( 531 R23, 532 R24, 533 R25, 534 R26, 535 R27, 536 R28 537 ); 538 539 reg_class rscratch1_bits32_reg(R11); 540 reg_class rscratch2_bits32_reg(R12); 541 reg_class rarg1_bits32_reg(R3); 542 reg_class rarg2_bits32_reg(R4); 543 reg_class rarg3_bits32_reg(R5); 544 reg_class rarg4_bits32_reg(R6); 545 546 // ---------------------------- 547 // 64 Bit Register Classes 548 // ---------------------------- 549 // 64-bit build means 64-bit pointers means hi/lo pairs 550 551 reg_class rscratch1_bits64_reg(R11_H, R11); 552 reg_class rscratch2_bits64_reg(R12_H, R12); 553 reg_class rarg1_bits64_reg(R3_H, R3); 554 reg_class rarg2_bits64_reg(R4_H, R4); 555 reg_class rarg3_bits64_reg(R5_H, R5); 556 reg_class rarg4_bits64_reg(R6_H, R6); 557 // Thread register, 'written' by tlsLoadP, see there. 558 reg_class thread_bits64_reg(R16_H, R16); 559 560 reg_class r19_bits64_reg(R19_H, R19); 561 562 // 64 bit registers that can be read and written i.e. these registers 563 // can be dest (or src) of normal instructions. 564 reg_class bits64_reg_rw( 565 /*R0_H, R0*/ // R0 566 /*R1_H, R1*/ // SP 567 R2_H, R2, // TOC 568 R3_H, R3, 569 R4_H, R4, 570 R5_H, R5, 571 R6_H, R6, 572 R7_H, R7, 573 R8_H, R8, 574 R9_H, R9, 575 R10_H, R10, 576 R11_H, R11, 577 R12_H, R12, 578 /*R13_H, R13*/ // system thread id 579 R14_H, R14, 580 R15_H, R15, 581 /*R16_H, R16*/ // R16_thread 582 R17_H, R17, 583 R18_H, R18, 584 R19_H, R19, 585 R20_H, R20, 586 R21_H, R21, 587 R22_H, R22, 588 R23_H, R23, 589 R24_H, R24, 590 R25_H, R25, 591 R26_H, R26, 592 R27_H, R27, 593 R28_H, R28, 594 /*R29_H, R29*/ 595 /*R30_H, R30*/ 596 R31_H, R31 597 ); 598 599 // 64 bit registers used excluding r2, r11 and r12 600 // Used to hold the TOC to avoid collisions with expanded LeafCall which uses 601 // r2, r11 and r12 internally. 602 reg_class bits64_reg_leaf_call( 603 /*R0_H, R0*/ // R0 604 /*R1_H, R1*/ // SP 605 /*R2_H, R2*/ // TOC 606 R3_H, R3, 607 R4_H, R4, 608 R5_H, R5, 609 R6_H, R6, 610 R7_H, R7, 611 R8_H, R8, 612 R9_H, R9, 613 R10_H, R10, 614 /*R11_H, R11*/ 615 /*R12_H, R12*/ 616 /*R13_H, R13*/ // system thread id 617 R14_H, R14, 618 R15_H, R15, 619 /*R16_H, R16*/ // R16_thread 620 R17_H, R17, 621 R18_H, R18, 622 R19_H, R19, 623 R20_H, R20, 624 R21_H, R21, 625 R22_H, R22, 626 R23_H, R23, 627 R24_H, R24, 628 R25_H, R25, 629 R26_H, R26, 630 R27_H, R27, 631 R28_H, R28, 632 /*R29_H, R29*/ 633 /*R30_H, R30*/ 634 R31_H, R31 635 ); 636 637 // Used to hold the TOC to avoid collisions with expanded DynamicCall 638 // which uses r19 as inline cache internally and expanded LeafCall which uses 639 // r2, r11 and r12 internally. 640 reg_class bits64_constant_table_base( 641 /*R0_H, R0*/ // R0 642 /*R1_H, R1*/ // SP 643 /*R2_H, R2*/ // TOC 644 R3_H, R3, 645 R4_H, R4, 646 R5_H, R5, 647 R6_H, R6, 648 R7_H, R7, 649 R8_H, R8, 650 R9_H, R9, 651 R10_H, R10, 652 /*R11_H, R11*/ 653 /*R12_H, R12*/ 654 /*R13_H, R13*/ // system thread id 655 R14_H, R14, 656 R15_H, R15, 657 /*R16_H, R16*/ // R16_thread 658 R17_H, R17, 659 R18_H, R18, 660 /*R19_H, R19*/ 661 R20_H, R20, 662 R21_H, R21, 663 R22_H, R22, 664 R23_H, R23, 665 R24_H, R24, 666 R25_H, R25, 667 R26_H, R26, 668 R27_H, R27, 669 R28_H, R28, 670 /*R29_H, R29*/ 671 /*R30_H, R30*/ 672 R31_H, R31 673 ); 674 675 // 64 bit registers that can only be read i.e. these registers can 676 // only be src of all instructions. 677 reg_class bits64_reg_ro( 678 /*R0_H, R0*/ // R0 679 R1_H, R1, 680 R2_H, R2, // TOC 681 R3_H, R3, 682 R4_H, R4, 683 R5_H, R5, 684 R6_H, R6, 685 R7_H, R7, 686 R8_H, R8, 687 R9_H, R9, 688 R10_H, R10, 689 R11_H, R11, 690 R12_H, R12, 691 /*R13_H, R13*/ // system thread id 692 R14_H, R14, 693 R15_H, R15, 694 R16_H, R16, // R16_thread 695 R17_H, R17, 696 R18_H, R18, 697 R19_H, R19, 698 R20_H, R20, 699 R21_H, R21, 700 R22_H, R22, 701 R23_H, R23, 702 R24_H, R24, 703 R25_H, R25, 704 R26_H, R26, 705 R27_H, R27, 706 R28_H, R28, 707 /*R29_H, R29*/ // TODO: let allocator handle TOC!! 708 /*R30_H, R30,*/ 709 R31_H, R31 710 ); 711 712 // Complement-required-in-pipeline operands. 713 reg_class bits64_reg_ro_not_complement ( 714 /*R0_H, R0*/ // R0 715 R1_H, R1, // SP 716 R2_H, R2, // TOC 717 R3_H, R3, 718 R4_H, R4, 719 R5_H, R5, 720 R6_H, R6, 721 R7_H, R7, 722 R8_H, R8, 723 R9_H, R9, 724 R10_H, R10, 725 R11_H, R11, 726 R12_H, R12, 727 /*R13_H, R13*/ // system thread id 728 R14_H, R14, 729 R15_H, R15, 730 R16_H, R16, // R16_thread 731 R17_H, R17, 732 R18_H, R18, 733 R19_H, R19, 734 R20_H, R20, 735 R21_H, R21, 736 R22_H, R22, 737 /*R23_H, R23, 738 R24_H, R24, 739 R25_H, R25, 740 R26_H, R26, 741 R27_H, R27, 742 R28_H, R28,*/ 743 /*R29_H, R29*/ // TODO: let allocator handle TOC!! 744 /*R30_H, R30,*/ 745 R31_H, R31 746 ); 747 748 // Complement-required-in-pipeline operands. 749 // This register mask is used for the trap instructions that implement 750 // the null checks on AIX. The trap instruction first computes the 751 // complement of the value it shall trap on. Because of this, the 752 // instruction can not be scheduled in the same cycle as an other 753 // instruction reading the normal value of the same register. So we 754 // force the value to check into 'bits64_reg_ro_not_complement' 755 // and then copy it to 'bits64_reg_ro_complement' for the trap. 756 reg_class bits64_reg_ro_complement ( 757 R23_H, R23, 758 R24_H, R24, 759 R25_H, R25, 760 R26_H, R26, 761 R27_H, R27, 762 R28_H, R28 763 ); 764 765 766 // ---------------------------- 767 // Special Class for Condition Code Flags Register 768 769 reg_class int_flags( 770 /*CCR0*/ // scratch 771 /*CCR1*/ // scratch 772 /*CCR2*/ // nv! 773 /*CCR3*/ // nv! 774 /*CCR4*/ // nv! 775 CCR5, 776 CCR6, 777 CCR7 778 ); 779 780 reg_class int_flags_CR0(CCR0); 781 reg_class int_flags_CR1(CCR1); 782 reg_class int_flags_CR6(CCR6); 783 reg_class ctr_reg(SR_CTR); 784 785 // ---------------------------- 786 // Float Register Classes 787 // ---------------------------- 788 789 reg_class flt_reg( 790 /*F0*/ // scratch 791 F1, 792 F2, 793 F3, 794 F4, 795 F5, 796 F6, 797 F7, 798 F8, 799 F9, 800 F10, 801 F11, 802 F12, 803 F13, 804 F14, // nv! 805 F15, // nv! 806 F16, // nv! 807 F17, // nv! 808 F18, // nv! 809 F19, // nv! 810 F20, // nv! 811 F21, // nv! 812 F22, // nv! 813 F23, // nv! 814 F24, // nv! 815 F25, // nv! 816 F26, // nv! 817 F27, // nv! 818 F28, // nv! 819 F29, // nv! 820 F30, // nv! 821 F31 // nv! 822 ); 823 824 // Double precision float registers have virtual `high halves' that 825 // are needed by the allocator. 826 reg_class dbl_reg( 827 /*F0, F0_H*/ // scratch 828 F1, F1_H, 829 F2, F2_H, 830 F3, F3_H, 831 F4, F4_H, 832 F5, F5_H, 833 F6, F6_H, 834 F7, F7_H, 835 F8, F8_H, 836 F9, F9_H, 837 F10, F10_H, 838 F11, F11_H, 839 F12, F12_H, 840 F13, F13_H, 841 F14, F14_H, // nv! 842 F15, F15_H, // nv! 843 F16, F16_H, // nv! 844 F17, F17_H, // nv! 845 F18, F18_H, // nv! 846 F19, F19_H, // nv! 847 F20, F20_H, // nv! 848 F21, F21_H, // nv! 849 F22, F22_H, // nv! 850 F23, F23_H, // nv! 851 F24, F24_H, // nv! 852 F25, F25_H, // nv! 853 F26, F26_H, // nv! 854 F27, F27_H, // nv! 855 F28, F28_H, // nv! 856 F29, F29_H, // nv! 857 F30, F30_H, // nv! 858 F31, F31_H // nv! 859 ); 860 861 %} 862 863 //----------DEFINITION BLOCK--------------------------------------------------- 864 // Define name --> value mappings to inform the ADLC of an integer valued name 865 // Current support includes integer values in the range [0, 0x7FFFFFFF] 866 // Format: 867 // int_def <name> ( <int_value>, <expression>); 868 // Generated Code in ad_<arch>.hpp 869 // #define <name> (<expression>) 870 // // value == <int_value> 871 // Generated code in ad_<arch>.cpp adlc_verification() 872 // assert( <name> == <int_value>, "Expect (<expression>) to equal <int_value>"); 873 // 874 definitions %{ 875 // The default cost (of an ALU instruction). 876 int_def DEFAULT_COST_LOW ( 30, 30); 877 int_def DEFAULT_COST ( 100, 100); 878 int_def HUGE_COST (1000000, 1000000); 879 880 // Memory refs 881 int_def MEMORY_REF_COST_LOW ( 200, DEFAULT_COST * 2); 882 int_def MEMORY_REF_COST ( 300, DEFAULT_COST * 3); 883 884 // Branches are even more expensive. 885 int_def BRANCH_COST ( 900, DEFAULT_COST * 9); 886 int_def CALL_COST ( 1300, DEFAULT_COST * 13); 887 %} 888 889 890 //----------SOURCE BLOCK------------------------------------------------------- 891 // This is a block of C++ code which provides values, functions, and 892 // definitions necessary in the rest of the architecture description. 893 source_hpp %{ 894 // Header information of the source block. 895 // Method declarations/definitions which are used outside 896 // the ad-scope can conveniently be defined here. 897 // 898 // To keep related declarations/definitions/uses close together, 899 // we switch between source %{ }% and source_hpp %{ }% freely as needed. 900 901 // Returns true if Node n is followed by a MemBar node that 902 // will do an acquire. If so, this node must not do the acquire 903 // operation. 904 bool followed_by_acquire(const Node *n); 905 %} 906 907 source %{ 908 909 // Optimize load-acquire. 910 // 911 // Check if acquire is unnecessary due to following operation that does 912 // acquire anyways. 913 // Walk the pattern: 914 // 915 // n: Load.acq 916 // | 917 // MemBarAcquire 918 // | | 919 // Proj(ctrl) Proj(mem) 920 // | | 921 // MemBarRelease/Volatile 922 // 923 bool followed_by_acquire(const Node *load) { 924 assert(load->is_Load(), "So far implemented only for loads."); 925 926 // Find MemBarAcquire. 927 const Node *mba = NULL; 928 for (DUIterator_Fast imax, i = load->fast_outs(imax); i < imax; i++) { 929 const Node *out = load->fast_out(i); 930 if (out->Opcode() == Op_MemBarAcquire) { 931 if (out->in(0) == load) continue; // Skip control edge, membar should be found via precedence edge. 932 mba = out; 933 break; 934 } 935 } 936 if (!mba) return false; 937 938 // Find following MemBar node. 939 // 940 // The following node must be reachable by control AND memory 941 // edge to assure no other operations are in between the two nodes. 942 // 943 // So first get the Proj node, mem_proj, to use it to iterate forward. 944 Node *mem_proj = NULL; 945 for (DUIterator_Fast imax, i = mba->fast_outs(imax); i < imax; i++) { 946 mem_proj = mba->fast_out(i); // Throw out-of-bounds if proj not found 947 assert(mem_proj->is_Proj(), "only projections here"); 948 ProjNode *proj = mem_proj->as_Proj(); 949 if (proj->_con == TypeFunc::Memory && 950 !Compile::current()->node_arena()->contains(mem_proj)) // Unmatched old-space only 951 break; 952 } 953 assert(mem_proj->as_Proj()->_con == TypeFunc::Memory, "Graph broken"); 954 955 // Search MemBar behind Proj. If there are other memory operations 956 // behind the Proj we lost. 957 for (DUIterator_Fast jmax, j = mem_proj->fast_outs(jmax); j < jmax; j++) { 958 Node *x = mem_proj->fast_out(j); 959 // Proj might have an edge to a store or load node which precedes the membar. 960 if (x->is_Mem()) return false; 961 962 // On PPC64 release and volatile are implemented by an instruction 963 // that also has acquire semantics. I.e. there is no need for an 964 // acquire before these. 965 int xop = x->Opcode(); 966 if (xop == Op_MemBarRelease || xop == Op_MemBarVolatile) { 967 // Make sure we're not missing Call/Phi/MergeMem by checking 968 // control edges. The control edge must directly lead back 969 // to the MemBarAcquire 970 Node *ctrl_proj = x->in(0); 971 if (ctrl_proj->is_Proj() && ctrl_proj->in(0) == mba) { 972 return true; 973 } 974 } 975 } 976 977 return false; 978 } 979 980 #define __ _masm. 981 982 // Tertiary op of a LoadP or StoreP encoding. 983 #define REGP_OP true 984 985 // **************************************************************************** 986 987 // REQUIRED FUNCTIONALITY 988 989 // !!!!! Special hack to get all type of calls to specify the byte offset 990 // from the start of the call to the point where the return address 991 // will point. 992 993 // PPC port: Removed use of lazy constant construct. 994 995 int MachCallStaticJavaNode::ret_addr_offset() { 996 // It's only a single branch-and-link instruction. 997 return 4; 998 } 999 1000 int MachCallDynamicJavaNode::ret_addr_offset() { 1001 // Offset is 4 with postalloc expanded calls (bl is one instruction). We use 1002 // postalloc expanded calls if we use inline caches and do not update method data. 1003 if (UseInlineCaches) 1004 return 4; 1005 1006 int vtable_index = this->_vtable_index; 1007 if (vtable_index < 0) { 1008 // Must be invalid_vtable_index, not nonvirtual_vtable_index. 1009 assert(vtable_index == Method::invalid_vtable_index, "correct sentinel value"); 1010 return 12; 1011 } else { 1012 assert(!UseInlineCaches, "expect vtable calls only if not using ICs"); 1013 return 24; 1014 } 1015 } 1016 1017 int MachCallRuntimeNode::ret_addr_offset() { 1018 #if defined(ABI_ELFv2) 1019 return 28; 1020 #else 1021 return 40; 1022 #endif 1023 } 1024 1025 //============================================================================= 1026 1027 // condition code conversions 1028 1029 static int cc_to_boint(int cc) { 1030 return Assembler::bcondCRbiIs0 | (cc & 8); 1031 } 1032 1033 static int cc_to_inverse_boint(int cc) { 1034 return Assembler::bcondCRbiIs0 | (8-(cc & 8)); 1035 } 1036 1037 static int cc_to_biint(int cc, int flags_reg) { 1038 return (flags_reg << 2) | (cc & 3); 1039 } 1040 1041 //============================================================================= 1042 1043 // Compute padding required for nodes which need alignment. The padding 1044 // is the number of bytes (not instructions) which will be inserted before 1045 // the instruction. The padding must match the size of a NOP instruction. 1046 1047 int string_indexOf_imm1_charNode::compute_padding(int current_offset) const { 1048 return (3*4-current_offset)&31; 1049 } 1050 1051 int string_indexOf_imm1Node::compute_padding(int current_offset) const { 1052 return (2*4-current_offset)&31; 1053 } 1054 1055 int string_indexOf_immNode::compute_padding(int current_offset) const { 1056 return (3*4-current_offset)&31; 1057 } 1058 1059 int string_indexOfNode::compute_padding(int current_offset) const { 1060 return (1*4-current_offset)&31; 1061 } 1062 1063 int string_compareNode::compute_padding(int current_offset) const { 1064 return (4*4-current_offset)&31; 1065 } 1066 1067 int string_equals_immNode::compute_padding(int current_offset) const { 1068 if (opnd_array(3)->constant() < 16) return 0; // Don't insert nops for short version (loop completely unrolled). 1069 return (2*4-current_offset)&31; 1070 } 1071 1072 int string_equalsNode::compute_padding(int current_offset) const { 1073 return (7*4-current_offset)&31; 1074 } 1075 1076 int inlineCallClearArrayNode::compute_padding(int current_offset) const { 1077 return (2*4-current_offset)&31; 1078 } 1079 1080 //============================================================================= 1081 1082 // Indicate if the safepoint node needs the polling page as an input. 1083 bool SafePointNode::needs_polling_address_input() { 1084 // The address is loaded from thread by a seperate node. 1085 return true; 1086 } 1087 1088 //============================================================================= 1089 1090 // Emit an interrupt that is caught by the debugger (for debugging compiler). 1091 void emit_break(CodeBuffer &cbuf) { 1092 MacroAssembler _masm(&cbuf); 1093 __ illtrap(); 1094 } 1095 1096 #ifndef PRODUCT 1097 void MachBreakpointNode::format(PhaseRegAlloc *ra_, outputStream *st) const { 1098 st->print("BREAKPOINT"); 1099 } 1100 #endif 1101 1102 void MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 1103 emit_break(cbuf); 1104 } 1105 1106 uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const { 1107 return MachNode::size(ra_); 1108 } 1109 1110 //============================================================================= 1111 1112 void emit_nop(CodeBuffer &cbuf) { 1113 MacroAssembler _masm(&cbuf); 1114 __ nop(); 1115 } 1116 1117 static inline void emit_long(CodeBuffer &cbuf, int value) { 1118 *((int*)(cbuf.insts_end())) = value; 1119 cbuf.set_insts_end(cbuf.insts_end() + BytesPerInstWord); 1120 } 1121 1122 //============================================================================= 1123 1124 %} // interrupt source 1125 1126 source_hpp %{ // Header information of the source block. 1127 1128 //-------------------------------------------------------------- 1129 //---< Used for optimization in Compile::Shorten_branches >--- 1130 //-------------------------------------------------------------- 1131 1132 const uint trampoline_stub_size = 6 * BytesPerInstWord; 1133 1134 class CallStubImpl { 1135 1136 public: 1137 1138 // Emit call stub, compiled java to interpreter. 1139 static void emit_trampoline_stub(MacroAssembler &_masm, int destination_toc_offset, int insts_call_instruction_offset); 1140 1141 // Size of call trampoline stub. 1142 // This doesn't need to be accurate to the byte, but it 1143 // must be larger than or equal to the real size of the stub. 1144 static uint size_call_trampoline() { 1145 return trampoline_stub_size; 1146 } 1147 1148 // number of relocations needed by a call trampoline stub 1149 static uint reloc_call_trampoline() { 1150 return 5; 1151 } 1152 1153 }; 1154 1155 %} // end source_hpp 1156 1157 source %{ 1158 1159 // Emit a trampoline stub for a call to a target which is too far away. 1160 // 1161 // code sequences: 1162 // 1163 // call-site: 1164 // branch-and-link to <destination> or <trampoline stub> 1165 // 1166 // Related trampoline stub for this call-site in the stub section: 1167 // load the call target from the constant pool 1168 // branch via CTR (LR/link still points to the call-site above) 1169 1170 void CallStubImpl::emit_trampoline_stub(MacroAssembler &_masm, int destination_toc_offset, int insts_call_instruction_offset) { 1171 // Start the stub. 1172 address stub = __ start_a_stub(Compile::MAX_stubs_size/2); 1173 if (stub == NULL) { 1174 Compile::current()->env()->record_out_of_memory_failure(); 1175 return; 1176 } 1177 1178 // For java_to_interp stubs we use R11_scratch1 as scratch register 1179 // and in call trampoline stubs we use R12_scratch2. This way we 1180 // can distinguish them (see is_NativeCallTrampolineStub_at()). 1181 Register reg_scratch = R12_scratch2; 1182 1183 // Create a trampoline stub relocation which relates this trampoline stub 1184 // with the call instruction at insts_call_instruction_offset in the 1185 // instructions code-section. 1186 __ relocate(trampoline_stub_Relocation::spec(__ code()->insts()->start() + insts_call_instruction_offset)); 1187 const int stub_start_offset = __ offset(); 1188 1189 // Now, create the trampoline stub's code: 1190 // - load the TOC 1191 // - load the call target from the constant pool 1192 // - call 1193 __ calculate_address_from_global_toc(reg_scratch, __ method_toc()); 1194 __ ld_largeoffset_unchecked(reg_scratch, destination_toc_offset, reg_scratch, false); 1195 __ mtctr(reg_scratch); 1196 __ bctr(); 1197 1198 const address stub_start_addr = __ addr_at(stub_start_offset); 1199 1200 // FIXME: Assert that the trampoline stub can be identified and patched. 1201 1202 // Assert that the encoded destination_toc_offset can be identified and that it is correct. 1203 assert(destination_toc_offset == NativeCallTrampolineStub_at(stub_start_addr)->destination_toc_offset(), 1204 "encoded offset into the constant pool must match"); 1205 // Trampoline_stub_size should be good. 1206 assert((uint)(__ offset() - stub_start_offset) <= trampoline_stub_size, "should be good size"); 1207 assert(is_NativeCallTrampolineStub_at(stub_start_addr), "doesn't look like a trampoline"); 1208 1209 // End the stub. 1210 __ end_a_stub(); 1211 } 1212 1213 //============================================================================= 1214 1215 // Emit an inline branch-and-link call and a related trampoline stub. 1216 // 1217 // code sequences: 1218 // 1219 // call-site: 1220 // branch-and-link to <destination> or <trampoline stub> 1221 // 1222 // Related trampoline stub for this call-site in the stub section: 1223 // load the call target from the constant pool 1224 // branch via CTR (LR/link still points to the call-site above) 1225 // 1226 1227 typedef struct { 1228 int insts_call_instruction_offset; 1229 int ret_addr_offset; 1230 } EmitCallOffsets; 1231 1232 // Emit a branch-and-link instruction that branches to a trampoline. 1233 // - Remember the offset of the branch-and-link instruction. 1234 // - Add a relocation at the branch-and-link instruction. 1235 // - Emit a branch-and-link. 1236 // - Remember the return pc offset. 1237 EmitCallOffsets emit_call_with_trampoline_stub(MacroAssembler &_masm, address entry_point, relocInfo::relocType rtype) { 1238 EmitCallOffsets offsets = { -1, -1 }; 1239 const int start_offset = __ offset(); 1240 offsets.insts_call_instruction_offset = __ offset(); 1241 1242 // No entry point given, use the current pc. 1243 if (entry_point == NULL) entry_point = __ pc(); 1244 1245 if (!Compile::current()->in_scratch_emit_size()) { 1246 // Put the entry point as a constant into the constant pool. 1247 const address entry_point_toc_addr = __ address_constant(entry_point, RelocationHolder::none); 1248 const int entry_point_toc_offset = __ offset_to_method_toc(entry_point_toc_addr); 1249 1250 // Emit the trampoline stub which will be related to the branch-and-link below. 1251 CallStubImpl::emit_trampoline_stub(_masm, entry_point_toc_offset, offsets.insts_call_instruction_offset); 1252 __ relocate(rtype); 1253 } 1254 1255 // Note: At this point we do not have the address of the trampoline 1256 // stub, and the entry point might be too far away for bl, so __ pc() 1257 // serves as dummy and the bl will be patched later. 1258 __ bl((address) __ pc()); 1259 1260 offsets.ret_addr_offset = __ offset() - start_offset; 1261 1262 return offsets; 1263 } 1264 1265 //============================================================================= 1266 1267 // Factory for creating loadConL* nodes for large/small constant pool. 1268 1269 static inline jlong replicate_immF(float con) { 1270 // Replicate float con 2 times and pack into vector. 1271 int val = *((int*)&con); 1272 jlong lval = val; 1273 lval = (lval << 32) | (lval & 0xFFFFFFFFl); 1274 return lval; 1275 } 1276 1277 //============================================================================= 1278 1279 const RegMask& MachConstantBaseNode::_out_RegMask = BITS64_CONSTANT_TABLE_BASE_mask(); 1280 int Compile::ConstantTable::calculate_table_base_offset() const { 1281 return 0; // absolute addressing, no offset 1282 } 1283 1284 bool MachConstantBaseNode::requires_postalloc_expand() const { return true; } 1285 void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) { 1286 Compile *C = ra_->C; 1287 1288 iRegPdstOper *op_dst = iRegPdstOper(); 1289 MachNode *m1 = loadToc_hiNode(); 1290 MachNode *m2 = loadToc_loNode(); 1291 1292 m1->add_req(NULL); 1293 m2->add_req(NULL, m1); 1294 m1->_opnds[0] = op_dst; 1295 m2->_opnds[0] = op_dst; 1296 m2->_opnds[1] = op_dst; 1297 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 1298 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 1299 nodes->push(m1); 1300 nodes->push(m2); 1301 } 1302 1303 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const { 1304 // Is postalloc expanded. 1305 ShouldNotReachHere(); 1306 } 1307 1308 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const { 1309 return 0; 1310 } 1311 1312 #ifndef PRODUCT 1313 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const { 1314 st->print("-- \t// MachConstantBaseNode (empty encoding)"); 1315 } 1316 #endif 1317 1318 //============================================================================= 1319 1320 #ifndef PRODUCT 1321 void MachPrologNode::format(PhaseRegAlloc *ra_, outputStream *st) const { 1322 Compile* C = ra_->C; 1323 const long framesize = C->frame_slots() << LogBytesPerInt; 1324 1325 st->print("PROLOG\n\t"); 1326 if (C->need_stack_bang(framesize)) { 1327 st->print("stack_overflow_check\n\t"); 1328 } 1329 1330 if (!false /* TODO: PPC port C->is_frameless_method()*/) { 1331 st->print("save return pc\n\t"); 1332 st->print("push frame %d\n\t", -framesize); 1333 } 1334 } 1335 #endif 1336 1337 // Macro used instead of the common __ to emulate the pipes of PPC. 1338 // Instead of e.g. __ ld(...) one hase to write ___(ld) ld(...) This enables the 1339 // micro scheduler to cope with "hand written" assembler like in the prolog. Though 1340 // still no scheduling of this code is possible, the micro scheduler is aware of the 1341 // code and can update its internal data. The following mechanism is used to achieve this: 1342 // The micro scheduler calls size() of each compound node during scheduling. size() does a 1343 // dummy emit and only during this dummy emit C->hb_scheduling() is not NULL. 1344 #if 0 // TODO: PPC port 1345 #define ___(op) if (UsePower6SchedulerPPC64 && C->hb_scheduling()) \ 1346 C->hb_scheduling()->_pdScheduling->PdEmulatePipe(ppc64Opcode_##op); \ 1347 _masm. 1348 #define ___stop if (UsePower6SchedulerPPC64 && C->hb_scheduling()) \ 1349 C->hb_scheduling()->_pdScheduling->PdEmulatePipe(archOpcode_none) 1350 #define ___advance if (UsePower6SchedulerPPC64 && C->hb_scheduling()) \ 1351 C->hb_scheduling()->_pdScheduling->advance_offset 1352 #else 1353 #define ___(op) if (UsePower6SchedulerPPC64) \ 1354 Unimplemented(); \ 1355 _masm. 1356 #define ___stop if (UsePower6SchedulerPPC64) \ 1357 Unimplemented() 1358 #define ___advance if (UsePower6SchedulerPPC64) \ 1359 Unimplemented() 1360 #endif 1361 1362 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 1363 Compile* C = ra_->C; 1364 MacroAssembler _masm(&cbuf); 1365 1366 const long framesize = C->frame_size_in_bytes(); 1367 assert(framesize % (2 * wordSize) == 0, "must preserve 2*wordSize alignment"); 1368 1369 const bool method_is_frameless = false /* TODO: PPC port C->is_frameless_method()*/; 1370 1371 const Register return_pc = R20; // Must match return_addr() in frame section. 1372 const Register callers_sp = R21; 1373 const Register push_frame_temp = R22; 1374 const Register toc_temp = R23; 1375 assert_different_registers(R11, return_pc, callers_sp, push_frame_temp, toc_temp); 1376 1377 if (method_is_frameless) { 1378 // Add nop at beginning of all frameless methods to prevent any 1379 // oop instructions from getting overwritten by make_not_entrant 1380 // (patching attempt would fail). 1381 ___(nop) nop(); 1382 } else { 1383 // Get return pc. 1384 ___(mflr) mflr(return_pc); 1385 } 1386 1387 // Calls to C2R adapters often do not accept exceptional returns. 1388 // We require that their callers must bang for them. But be 1389 // careful, because some VM calls (such as call site linkage) can 1390 // use several kilobytes of stack. But the stack safety zone should 1391 // account for that. See bugs 4446381, 4468289, 4497237. 1392 1393 int bangsize = C->bang_size_in_bytes(); 1394 assert(bangsize >= framesize || bangsize <= 0, "stack bang size incorrect"); 1395 if (C->need_stack_bang(bangsize) && UseStackBanging) { 1396 // Unfortunately we cannot use the function provided in 1397 // assembler.cpp as we have to emulate the pipes. So I had to 1398 // insert the code of generate_stack_overflow_check(), see 1399 // assembler.cpp for some illuminative comments. 1400 const int page_size = os::vm_page_size(); 1401 int bang_end = StackShadowPages * page_size; 1402 1403 // This is how far the previous frame's stack banging extended. 1404 const int bang_end_safe = bang_end; 1405 1406 if (bangsize > page_size) { 1407 bang_end += bangsize; 1408 } 1409 1410 int bang_offset = bang_end_safe; 1411 1412 while (bang_offset <= bang_end) { 1413 // Need at least one stack bang at end of shadow zone. 1414 1415 // Again I had to copy code, this time from assembler_ppc64.cpp, 1416 // bang_stack_with_offset - see there for comments. 1417 1418 // Stack grows down, caller passes positive offset. 1419 assert(bang_offset > 0, "must bang with positive offset"); 1420 1421 long stdoffset = -bang_offset; 1422 1423 if (Assembler::is_simm(stdoffset, 16)) { 1424 // Signed 16 bit offset, a simple std is ok. 1425 if (UseLoadInstructionsForStackBangingPPC64) { 1426 ___(ld) ld(R0, (int)(signed short)stdoffset, R1_SP); 1427 } else { 1428 ___(std) std(R0, (int)(signed short)stdoffset, R1_SP); 1429 } 1430 } else if (Assembler::is_simm(stdoffset, 31)) { 1431 // Use largeoffset calculations for addis & ld/std. 1432 const int hi = MacroAssembler::largeoffset_si16_si16_hi(stdoffset); 1433 const int lo = MacroAssembler::largeoffset_si16_si16_lo(stdoffset); 1434 1435 Register tmp = R11; 1436 ___(addis) addis(tmp, R1_SP, hi); 1437 if (UseLoadInstructionsForStackBangingPPC64) { 1438 ___(ld) ld(R0, lo, tmp); 1439 } else { 1440 ___(std) std(R0, lo, tmp); 1441 } 1442 } else { 1443 ShouldNotReachHere(); 1444 } 1445 1446 bang_offset += page_size; 1447 } 1448 // R11 trashed 1449 } // C->need_stack_bang(framesize) && UseStackBanging 1450 1451 unsigned int bytes = (unsigned int)framesize; 1452 long offset = Assembler::align_addr(bytes, frame::alignment_in_bytes); 1453 ciMethod *currMethod = C->method(); 1454 1455 // Optimized version for most common case. 1456 if (UsePower6SchedulerPPC64 && 1457 !method_is_frameless && Assembler::is_simm((int)(-offset), 16) && 1458 !(false /* ConstantsALot TODO: PPC port*/)) { 1459 ___(or) mr(callers_sp, R1_SP); 1460 ___(std) std(return_pc, _abi(lr), R1_SP); 1461 ___(stdu) stdu(R1_SP, -offset, R1_SP); 1462 return; 1463 } 1464 1465 if (!method_is_frameless) { 1466 // Get callers sp. 1467 ___(or) mr(callers_sp, R1_SP); 1468 1469 // Push method's frame, modifies SP. 1470 assert(Assembler::is_uimm(framesize, 32U), "wrong type"); 1471 // The ABI is already accounted for in 'framesize' via the 1472 // 'out_preserve' area. 1473 Register tmp = push_frame_temp; 1474 // Had to insert code of push_frame((unsigned int)framesize, push_frame_temp). 1475 if (Assembler::is_simm(-offset, 16)) { 1476 ___(stdu) stdu(R1_SP, -offset, R1_SP); 1477 } else { 1478 long x = -offset; 1479 // Had to insert load_const(tmp, -offset). 1480 ___(addis) lis( tmp, (int)((signed short)(((x >> 32) & 0xffff0000) >> 16))); 1481 ___(ori) ori( tmp, tmp, ((x >> 32) & 0x0000ffff)); 1482 ___(rldicr) sldi(tmp, tmp, 32); 1483 ___(oris) oris(tmp, tmp, (x & 0xffff0000) >> 16); 1484 ___(ori) ori( tmp, tmp, (x & 0x0000ffff)); 1485 1486 ___(stdux) stdux(R1_SP, R1_SP, tmp); 1487 } 1488 } 1489 #if 0 // TODO: PPC port 1490 // For testing large constant pools, emit a lot of constants to constant pool. 1491 // "Randomize" const_size. 1492 if (ConstantsALot) { 1493 const int num_consts = const_size(); 1494 for (int i = 0; i < num_consts; i++) { 1495 __ long_constant(0xB0B5B00BBABE); 1496 } 1497 } 1498 #endif 1499 if (!method_is_frameless) { 1500 // Save return pc. 1501 ___(std) std(return_pc, _abi(lr), callers_sp); 1502 } 1503 } 1504 #undef ___ 1505 #undef ___stop 1506 #undef ___advance 1507 1508 uint MachPrologNode::size(PhaseRegAlloc *ra_) const { 1509 // Variable size. determine dynamically. 1510 return MachNode::size(ra_); 1511 } 1512 1513 int MachPrologNode::reloc() const { 1514 // Return number of relocatable values contained in this instruction. 1515 return 1; // 1 reloc entry for load_const(toc). 1516 } 1517 1518 //============================================================================= 1519 1520 #ifndef PRODUCT 1521 void MachEpilogNode::format(PhaseRegAlloc *ra_, outputStream *st) const { 1522 Compile* C = ra_->C; 1523 1524 st->print("EPILOG\n\t"); 1525 st->print("restore return pc\n\t"); 1526 st->print("pop frame\n\t"); 1527 1528 if (do_polling() && C->is_method_compilation()) { 1529 st->print("touch polling page\n\t"); 1530 } 1531 } 1532 #endif 1533 1534 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 1535 Compile* C = ra_->C; 1536 MacroAssembler _masm(&cbuf); 1537 1538 const long framesize = ((long)C->frame_slots()) << LogBytesPerInt; 1539 assert(framesize >= 0, "negative frame-size?"); 1540 1541 const bool method_needs_polling = do_polling() && C->is_method_compilation(); 1542 const bool method_is_frameless = false /* TODO: PPC port C->is_frameless_method()*/; 1543 const Register return_pc = R11; 1544 const Register polling_page = R12; 1545 1546 if (!method_is_frameless) { 1547 // Restore return pc relative to callers' sp. 1548 __ ld(return_pc, ((int)framesize) + _abi(lr), R1_SP); 1549 } 1550 1551 if (method_needs_polling) { 1552 if (LoadPollAddressFromThread) { 1553 // TODO: PPC port __ ld(polling_page, in_bytes(JavaThread::poll_address_offset()), R16_thread); 1554 Unimplemented(); 1555 } else { 1556 __ load_const_optimized(polling_page, (long)(address) os::get_polling_page()); // TODO: PPC port: get_standard_polling_page() 1557 } 1558 } 1559 1560 if (!method_is_frameless) { 1561 // Move return pc to LR. 1562 __ mtlr(return_pc); 1563 // Pop frame (fixed frame-size). 1564 __ addi(R1_SP, R1_SP, (int)framesize); 1565 } 1566 1567 if (method_needs_polling) { 1568 // We need to mark the code position where the load from the safepoint 1569 // polling page was emitted as relocInfo::poll_return_type here. 1570 __ relocate(relocInfo::poll_return_type); 1571 __ load_from_polling_page(polling_page); 1572 } 1573 } 1574 1575 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const { 1576 // Variable size. Determine dynamically. 1577 return MachNode::size(ra_); 1578 } 1579 1580 int MachEpilogNode::reloc() const { 1581 // Return number of relocatable values contained in this instruction. 1582 return 1; // 1 for load_from_polling_page. 1583 } 1584 1585 const Pipeline * MachEpilogNode::pipeline() const { 1586 return MachNode::pipeline_class(); 1587 } 1588 1589 // This method seems to be obsolete. It is declared in machnode.hpp 1590 // and defined in all *.ad files, but it is never called. Should we 1591 // get rid of it? 1592 int MachEpilogNode::safepoint_offset() const { 1593 assert(do_polling(), "no return for this epilog node"); 1594 return 0; 1595 } 1596 1597 #if 0 // TODO: PPC port 1598 void MachLoadPollAddrLateNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const { 1599 MacroAssembler _masm(&cbuf); 1600 if (LoadPollAddressFromThread) { 1601 _masm.ld(R11, in_bytes(JavaThread::poll_address_offset()), R16_thread); 1602 } else { 1603 _masm.nop(); 1604 } 1605 } 1606 1607 uint MachLoadPollAddrLateNode::size(PhaseRegAlloc* ra_) const { 1608 if (LoadPollAddressFromThread) { 1609 return 4; 1610 } else { 1611 return 4; 1612 } 1613 } 1614 1615 #ifndef PRODUCT 1616 void MachLoadPollAddrLateNode::format(PhaseRegAlloc* ra_, outputStream* st) const { 1617 st->print_cr(" LD R11, PollAddressOffset, R16_thread \t// LoadPollAddressFromThread"); 1618 } 1619 #endif 1620 1621 const RegMask &MachLoadPollAddrLateNode::out_RegMask() const { 1622 return RSCRATCH1_BITS64_REG_mask(); 1623 } 1624 #endif // PPC port 1625 1626 // ============================================================================= 1627 1628 // Figure out which register class each belongs in: rc_int, rc_float or 1629 // rc_stack. 1630 enum RC { rc_bad, rc_int, rc_float, rc_stack }; 1631 1632 static enum RC rc_class(OptoReg::Name reg) { 1633 // Return the register class for the given register. The given register 1634 // reg is a <register>_num value, which is an index into the MachRegisterNumbers 1635 // enumeration in adGlobals_ppc64.hpp. 1636 1637 if (reg == OptoReg::Bad) return rc_bad; 1638 1639 // We have 64 integer register halves, starting at index 0. 1640 if (reg < 64) return rc_int; 1641 1642 // We have 64 floating-point register halves, starting at index 64. 1643 if (reg < 64+64) return rc_float; 1644 1645 // Between float regs & stack are the flags regs. 1646 assert(OptoReg::is_stack(reg), "blow up if spilling flags"); 1647 1648 return rc_stack; 1649 } 1650 1651 static int ld_st_helper(CodeBuffer *cbuf, const char *op_str, uint opcode, int reg, int offset, 1652 bool do_print, Compile* C, outputStream *st) { 1653 1654 assert(opcode == Assembler::LD_OPCODE || 1655 opcode == Assembler::STD_OPCODE || 1656 opcode == Assembler::LWZ_OPCODE || 1657 opcode == Assembler::STW_OPCODE || 1658 opcode == Assembler::LFD_OPCODE || 1659 opcode == Assembler::STFD_OPCODE || 1660 opcode == Assembler::LFS_OPCODE || 1661 opcode == Assembler::STFS_OPCODE, 1662 "opcode not supported"); 1663 1664 if (cbuf) { 1665 int d = 1666 (Assembler::LD_OPCODE == opcode || Assembler::STD_OPCODE == opcode) ? 1667 Assembler::ds(offset+0 /* TODO: PPC port C->frame_slots_sp_bias_in_bytes()*/) 1668 : Assembler::d1(offset+0 /* TODO: PPC port C->frame_slots_sp_bias_in_bytes()*/); // Makes no difference in opt build. 1669 emit_long(*cbuf, opcode | Assembler::rt(Matcher::_regEncode[reg]) | d | Assembler::ra(R1_SP)); 1670 } 1671 #ifndef PRODUCT 1672 else if (do_print) { 1673 st->print("%-7s %s, [R1_SP + #%d+%d] \t// spill copy", 1674 op_str, 1675 Matcher::regName[reg], 1676 offset, 0 /* TODO: PPC port C->frame_slots_sp_bias_in_bytes()*/); 1677 } 1678 #endif 1679 return 4; // size 1680 } 1681 1682 uint MachSpillCopyNode::implementation(CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, outputStream *st) const { 1683 Compile* C = ra_->C; 1684 1685 // Get registers to move. 1686 OptoReg::Name src_hi = ra_->get_reg_second(in(1)); 1687 OptoReg::Name src_lo = ra_->get_reg_first(in(1)); 1688 OptoReg::Name dst_hi = ra_->get_reg_second(this); 1689 OptoReg::Name dst_lo = ra_->get_reg_first(this); 1690 1691 enum RC src_hi_rc = rc_class(src_hi); 1692 enum RC src_lo_rc = rc_class(src_lo); 1693 enum RC dst_hi_rc = rc_class(dst_hi); 1694 enum RC dst_lo_rc = rc_class(dst_lo); 1695 1696 assert(src_lo != OptoReg::Bad && dst_lo != OptoReg::Bad, "must move at least 1 register"); 1697 if (src_hi != OptoReg::Bad) 1698 assert((src_lo&1)==0 && src_lo+1==src_hi && 1699 (dst_lo&1)==0 && dst_lo+1==dst_hi, 1700 "expected aligned-adjacent pairs"); 1701 // Generate spill code! 1702 int size = 0; 1703 1704 if (src_lo == dst_lo && src_hi == dst_hi) 1705 return size; // Self copy, no move. 1706 1707 // -------------------------------------- 1708 // Memory->Memory Spill. Use R0 to hold the value. 1709 if (src_lo_rc == rc_stack && dst_lo_rc == rc_stack) { 1710 int src_offset = ra_->reg2offset(src_lo); 1711 int dst_offset = ra_->reg2offset(dst_lo); 1712 if (src_hi != OptoReg::Bad) { 1713 assert(src_hi_rc==rc_stack && dst_hi_rc==rc_stack, 1714 "expected same type of move for high parts"); 1715 size += ld_st_helper(cbuf, "LD ", Assembler::LD_OPCODE, R0_num, src_offset, !do_size, C, st); 1716 if (!cbuf && !do_size) st->print("\n\t"); 1717 size += ld_st_helper(cbuf, "STD ", Assembler::STD_OPCODE, R0_num, dst_offset, !do_size, C, st); 1718 } else { 1719 size += ld_st_helper(cbuf, "LWZ ", Assembler::LWZ_OPCODE, R0_num, src_offset, !do_size, C, st); 1720 if (!cbuf && !do_size) st->print("\n\t"); 1721 size += ld_st_helper(cbuf, "STW ", Assembler::STW_OPCODE, R0_num, dst_offset, !do_size, C, st); 1722 } 1723 return size; 1724 } 1725 1726 // -------------------------------------- 1727 // Check for float->int copy; requires a trip through memory. 1728 if (src_lo_rc == rc_float && dst_lo_rc == rc_int) { 1729 Unimplemented(); 1730 } 1731 1732 // -------------------------------------- 1733 // Check for integer reg-reg copy. 1734 if (src_lo_rc == rc_int && dst_lo_rc == rc_int) { 1735 Register Rsrc = as_Register(Matcher::_regEncode[src_lo]); 1736 Register Rdst = as_Register(Matcher::_regEncode[dst_lo]); 1737 size = (Rsrc != Rdst) ? 4 : 0; 1738 1739 if (cbuf) { 1740 MacroAssembler _masm(cbuf); 1741 if (size) { 1742 __ mr(Rdst, Rsrc); 1743 } 1744 } 1745 #ifndef PRODUCT 1746 else if (!do_size) { 1747 if (size) { 1748 st->print("%-7s %s, %s \t// spill copy", "MR", Matcher::regName[dst_lo], Matcher::regName[src_lo]); 1749 } else { 1750 st->print("%-7s %s, %s \t// spill copy", "MR-NOP", Matcher::regName[dst_lo], Matcher::regName[src_lo]); 1751 } 1752 } 1753 #endif 1754 return size; 1755 } 1756 1757 // Check for integer store. 1758 if (src_lo_rc == rc_int && dst_lo_rc == rc_stack) { 1759 int dst_offset = ra_->reg2offset(dst_lo); 1760 if (src_hi != OptoReg::Bad) { 1761 assert(src_hi_rc==rc_int && dst_hi_rc==rc_stack, 1762 "expected same type of move for high parts"); 1763 size += ld_st_helper(cbuf, "STD ", Assembler::STD_OPCODE, src_lo, dst_offset, !do_size, C, st); 1764 } else { 1765 size += ld_st_helper(cbuf, "STW ", Assembler::STW_OPCODE, src_lo, dst_offset, !do_size, C, st); 1766 } 1767 return size; 1768 } 1769 1770 // Check for integer load. 1771 if (dst_lo_rc == rc_int && src_lo_rc == rc_stack) { 1772 int src_offset = ra_->reg2offset(src_lo); 1773 if (src_hi != OptoReg::Bad) { 1774 assert(dst_hi_rc==rc_int && src_hi_rc==rc_stack, 1775 "expected same type of move for high parts"); 1776 size += ld_st_helper(cbuf, "LD ", Assembler::LD_OPCODE, dst_lo, src_offset, !do_size, C, st); 1777 } else { 1778 size += ld_st_helper(cbuf, "LWZ ", Assembler::LWZ_OPCODE, dst_lo, src_offset, !do_size, C, st); 1779 } 1780 return size; 1781 } 1782 1783 // Check for float reg-reg copy. 1784 if (src_lo_rc == rc_float && dst_lo_rc == rc_float) { 1785 if (cbuf) { 1786 MacroAssembler _masm(cbuf); 1787 FloatRegister Rsrc = as_FloatRegister(Matcher::_regEncode[src_lo]); 1788 FloatRegister Rdst = as_FloatRegister(Matcher::_regEncode[dst_lo]); 1789 __ fmr(Rdst, Rsrc); 1790 } 1791 #ifndef PRODUCT 1792 else if (!do_size) { 1793 st->print("%-7s %s, %s \t// spill copy", "FMR", Matcher::regName[dst_lo], Matcher::regName[src_lo]); 1794 } 1795 #endif 1796 return 4; 1797 } 1798 1799 // Check for float store. 1800 if (src_lo_rc == rc_float && dst_lo_rc == rc_stack) { 1801 int dst_offset = ra_->reg2offset(dst_lo); 1802 if (src_hi != OptoReg::Bad) { 1803 assert(src_hi_rc==rc_float && dst_hi_rc==rc_stack, 1804 "expected same type of move for high parts"); 1805 size += ld_st_helper(cbuf, "STFD", Assembler::STFD_OPCODE, src_lo, dst_offset, !do_size, C, st); 1806 } else { 1807 size += ld_st_helper(cbuf, "STFS", Assembler::STFS_OPCODE, src_lo, dst_offset, !do_size, C, st); 1808 } 1809 return size; 1810 } 1811 1812 // Check for float load. 1813 if (dst_lo_rc == rc_float && src_lo_rc == rc_stack) { 1814 int src_offset = ra_->reg2offset(src_lo); 1815 if (src_hi != OptoReg::Bad) { 1816 assert(dst_hi_rc==rc_float && src_hi_rc==rc_stack, 1817 "expected same type of move for high parts"); 1818 size += ld_st_helper(cbuf, "LFD ", Assembler::LFD_OPCODE, dst_lo, src_offset, !do_size, C, st); 1819 } else { 1820 size += ld_st_helper(cbuf, "LFS ", Assembler::LFS_OPCODE, dst_lo, src_offset, !do_size, C, st); 1821 } 1822 return size; 1823 } 1824 1825 // -------------------------------------------------------------------- 1826 // Check for hi bits still needing moving. Only happens for misaligned 1827 // arguments to native calls. 1828 if (src_hi == dst_hi) 1829 return size; // Self copy; no move. 1830 1831 assert(src_hi_rc != rc_bad && dst_hi_rc != rc_bad, "src_hi & dst_hi cannot be Bad"); 1832 ShouldNotReachHere(); // Unimplemented 1833 return 0; 1834 } 1835 1836 #ifndef PRODUCT 1837 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream *st) const { 1838 if (!ra_) 1839 st->print("N%d = SpillCopy(N%d)", _idx, in(1)->_idx); 1840 else 1841 implementation(NULL, ra_, false, st); 1842 } 1843 #endif 1844 1845 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 1846 implementation(&cbuf, ra_, false, NULL); 1847 } 1848 1849 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const { 1850 return implementation(NULL, ra_, true, NULL); 1851 } 1852 1853 #if 0 // TODO: PPC port 1854 ArchOpcode MachSpillCopyNode_archOpcode(MachSpillCopyNode *n, PhaseRegAlloc *ra_) { 1855 #ifndef PRODUCT 1856 if (ra_->node_regs_max_index() == 0) return archOpcode_undefined; 1857 #endif 1858 assert(ra_->node_regs_max_index() != 0, ""); 1859 1860 // Get registers to move. 1861 OptoReg::Name src_hi = ra_->get_reg_second(n->in(1)); 1862 OptoReg::Name src_lo = ra_->get_reg_first(n->in(1)); 1863 OptoReg::Name dst_hi = ra_->get_reg_second(n); 1864 OptoReg::Name dst_lo = ra_->get_reg_first(n); 1865 1866 enum RC src_lo_rc = rc_class(src_lo); 1867 enum RC dst_lo_rc = rc_class(dst_lo); 1868 1869 if (src_lo == dst_lo && src_hi == dst_hi) 1870 return ppc64Opcode_none; // Self copy, no move. 1871 1872 // -------------------------------------- 1873 // Memory->Memory Spill. Use R0 to hold the value. 1874 if (src_lo_rc == rc_stack && dst_lo_rc == rc_stack) { 1875 return ppc64Opcode_compound; 1876 } 1877 1878 // -------------------------------------- 1879 // Check for float->int copy; requires a trip through memory. 1880 if (src_lo_rc == rc_float && dst_lo_rc == rc_int) { 1881 Unimplemented(); 1882 } 1883 1884 // -------------------------------------- 1885 // Check for integer reg-reg copy. 1886 if (src_lo_rc == rc_int && dst_lo_rc == rc_int) { 1887 Register Rsrc = as_Register(Matcher::_regEncode[src_lo]); 1888 Register Rdst = as_Register(Matcher::_regEncode[dst_lo]); 1889 if (Rsrc == Rdst) { 1890 return ppc64Opcode_none; 1891 } else { 1892 return ppc64Opcode_or; 1893 } 1894 } 1895 1896 // Check for integer store. 1897 if (src_lo_rc == rc_int && dst_lo_rc == rc_stack) { 1898 if (src_hi != OptoReg::Bad) { 1899 return ppc64Opcode_std; 1900 } else { 1901 return ppc64Opcode_stw; 1902 } 1903 } 1904 1905 // Check for integer load. 1906 if (dst_lo_rc == rc_int && src_lo_rc == rc_stack) { 1907 if (src_hi != OptoReg::Bad) { 1908 return ppc64Opcode_ld; 1909 } else { 1910 return ppc64Opcode_lwz; 1911 } 1912 } 1913 1914 // Check for float reg-reg copy. 1915 if (src_lo_rc == rc_float && dst_lo_rc == rc_float) { 1916 return ppc64Opcode_fmr; 1917 } 1918 1919 // Check for float store. 1920 if (src_lo_rc == rc_float && dst_lo_rc == rc_stack) { 1921 if (src_hi != OptoReg::Bad) { 1922 return ppc64Opcode_stfd; 1923 } else { 1924 return ppc64Opcode_stfs; 1925 } 1926 } 1927 1928 // Check for float load. 1929 if (dst_lo_rc == rc_float && src_lo_rc == rc_stack) { 1930 if (src_hi != OptoReg::Bad) { 1931 return ppc64Opcode_lfd; 1932 } else { 1933 return ppc64Opcode_lfs; 1934 } 1935 } 1936 1937 // -------------------------------------------------------------------- 1938 // Check for hi bits still needing moving. Only happens for misaligned 1939 // arguments to native calls. 1940 if (src_hi == dst_hi) 1941 return ppc64Opcode_none; // Self copy; no move. 1942 1943 ShouldNotReachHere(); 1944 return ppc64Opcode_undefined; 1945 } 1946 #endif // PPC port 1947 1948 #ifndef PRODUCT 1949 void MachNopNode::format(PhaseRegAlloc *ra_, outputStream *st) const { 1950 st->print("NOP \t// %d nops to pad for loops.", _count); 1951 } 1952 #endif 1953 1954 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *) const { 1955 MacroAssembler _masm(&cbuf); 1956 // _count contains the number of nops needed for padding. 1957 for (int i = 0; i < _count; i++) { 1958 __ nop(); 1959 } 1960 } 1961 1962 uint MachNopNode::size(PhaseRegAlloc *ra_) const { 1963 return _count * 4; 1964 } 1965 1966 #ifndef PRODUCT 1967 void BoxLockNode::format(PhaseRegAlloc *ra_, outputStream *st) const { 1968 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()); 1969 int reg = ra_->get_reg_first(this); 1970 st->print("ADDI %s, SP, %d \t// box node", Matcher::regName[reg], offset); 1971 } 1972 #endif 1973 1974 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 1975 MacroAssembler _masm(&cbuf); 1976 1977 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()); 1978 int reg = ra_->get_encode(this); 1979 1980 if (Assembler::is_simm(offset, 16)) { 1981 __ addi(as_Register(reg), R1, offset); 1982 } else { 1983 ShouldNotReachHere(); 1984 } 1985 } 1986 1987 uint BoxLockNode::size(PhaseRegAlloc *ra_) const { 1988 // BoxLockNode is not a MachNode, so we can't just call MachNode::size(ra_). 1989 return 4; 1990 } 1991 1992 #ifndef PRODUCT 1993 void MachUEPNode::format(PhaseRegAlloc *ra_, outputStream *st) const { 1994 st->print_cr("---- MachUEPNode ----"); 1995 st->print_cr("..."); 1996 } 1997 #endif 1998 1999 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 2000 // This is the unverified entry point. 2001 MacroAssembler _masm(&cbuf); 2002 2003 // Inline_cache contains a klass. 2004 Register ic_klass = as_Register(Matcher::inline_cache_reg_encode()); 2005 Register receiver_klass = R0; // tmp 2006 2007 assert_different_registers(ic_klass, receiver_klass, R11_scratch1, R3_ARG1); 2008 assert(R11_scratch1 == R11, "need prologue scratch register"); 2009 2010 // Check for NULL argument if we don't have implicit null checks. 2011 if (!ImplicitNullChecks || !os::zero_page_read_protected()) { 2012 if (TrapBasedNullChecks) { 2013 __ trap_null_check(R3_ARG1); 2014 } else { 2015 Label valid; 2016 __ cmpdi(CCR0, R3_ARG1, 0); 2017 __ bne_predict_taken(CCR0, valid); 2018 // We have a null argument, branch to ic_miss_stub. 2019 __ b64_patchable((address)SharedRuntime::get_ic_miss_stub(), 2020 relocInfo::runtime_call_type); 2021 __ bind(valid); 2022 } 2023 } 2024 // Assume argument is not NULL, load klass from receiver. 2025 __ load_klass(receiver_klass, R3_ARG1); 2026 2027 if (TrapBasedICMissChecks) { 2028 __ trap_ic_miss_check(receiver_klass, ic_klass); 2029 } else { 2030 Label valid; 2031 __ cmpd(CCR0, receiver_klass, ic_klass); 2032 __ beq_predict_taken(CCR0, valid); 2033 // We have an unexpected klass, branch to ic_miss_stub. 2034 __ b64_patchable((address)SharedRuntime::get_ic_miss_stub(), 2035 relocInfo::runtime_call_type); 2036 __ bind(valid); 2037 } 2038 2039 // Argument is valid and klass is as expected, continue. 2040 } 2041 2042 #if 0 // TODO: PPC port 2043 // Optimize UEP code on z (save a load_const() call in main path). 2044 int MachUEPNode::ep_offset() { 2045 return 0; 2046 } 2047 #endif 2048 2049 uint MachUEPNode::size(PhaseRegAlloc *ra_) const { 2050 // Variable size. Determine dynamically. 2051 return MachNode::size(ra_); 2052 } 2053 2054 //============================================================================= 2055 2056 %} // interrupt source 2057 2058 source_hpp %{ // Header information of the source block. 2059 2060 class HandlerImpl { 2061 2062 public: 2063 2064 static int emit_exception_handler(CodeBuffer &cbuf); 2065 static int emit_deopt_handler(CodeBuffer& cbuf); 2066 2067 static uint size_exception_handler() { 2068 // The exception_handler is a b64_patchable. 2069 return MacroAssembler::b64_patchable_size; 2070 } 2071 2072 static uint size_deopt_handler() { 2073 // The deopt_handler is a bl64_patchable. 2074 return MacroAssembler::bl64_patchable_size; 2075 } 2076 2077 }; 2078 2079 %} // end source_hpp 2080 2081 source %{ 2082 2083 int HandlerImpl::emit_exception_handler(CodeBuffer &cbuf) { 2084 MacroAssembler _masm(&cbuf); 2085 2086 address base = __ start_a_stub(size_exception_handler()); 2087 if (base == NULL) return 0; // CodeBuffer::expand failed 2088 2089 int offset = __ offset(); 2090 __ b64_patchable((address)OptoRuntime::exception_blob()->content_begin(), 2091 relocInfo::runtime_call_type); 2092 assert(__ offset() - offset == (int)size_exception_handler(), "must be fixed size"); 2093 __ end_a_stub(); 2094 2095 return offset; 2096 } 2097 2098 // The deopt_handler is like the exception handler, but it calls to 2099 // the deoptimization blob instead of jumping to the exception blob. 2100 int HandlerImpl::emit_deopt_handler(CodeBuffer& cbuf) { 2101 MacroAssembler _masm(&cbuf); 2102 2103 address base = __ start_a_stub(size_deopt_handler()); 2104 if (base == NULL) return 0; // CodeBuffer::expand failed 2105 2106 int offset = __ offset(); 2107 __ bl64_patchable((address)SharedRuntime::deopt_blob()->unpack(), 2108 relocInfo::runtime_call_type); 2109 assert(__ offset() - offset == (int) size_deopt_handler(), "must be fixed size"); 2110 __ end_a_stub(); 2111 2112 return offset; 2113 } 2114 2115 //============================================================================= 2116 2117 // Use a frame slots bias for frameless methods if accessing the stack. 2118 static int frame_slots_bias(int reg_enc, PhaseRegAlloc* ra_) { 2119 if (as_Register(reg_enc) == R1_SP) { 2120 return 0; // TODO: PPC port ra_->C->frame_slots_sp_bias_in_bytes(); 2121 } 2122 return 0; 2123 } 2124 2125 const bool Matcher::match_rule_supported(int opcode) { 2126 if (!has_match_rule(opcode)) 2127 return false; 2128 2129 switch (opcode) { 2130 case Op_SqrtD: 2131 return VM_Version::has_fsqrt(); 2132 case Op_CountLeadingZerosI: 2133 case Op_CountLeadingZerosL: 2134 case Op_CountTrailingZerosI: 2135 case Op_CountTrailingZerosL: 2136 if (!UseCountLeadingZerosInstructionsPPC64) 2137 return false; 2138 break; 2139 2140 case Op_PopCountI: 2141 case Op_PopCountL: 2142 return (UsePopCountInstruction && VM_Version::has_popcntw()); 2143 2144 case Op_StrComp: 2145 return SpecialStringCompareTo; 2146 case Op_StrEquals: 2147 return SpecialStringEquals; 2148 case Op_StrIndexOf: 2149 return SpecialStringIndexOf; 2150 } 2151 2152 return true; // Per default match rules are supported. 2153 } 2154 2155 int Matcher::regnum_to_fpu_offset(int regnum) { 2156 // No user for this method? 2157 Unimplemented(); 2158 return 999; 2159 } 2160 2161 const bool Matcher::convL2FSupported(void) { 2162 // fcfids can do the conversion (>= Power7). 2163 // fcfid + frsp showed rounding problem when result should be 0x3f800001. 2164 return VM_Version::has_fcfids(); // False means that conversion is done by runtime call. 2165 } 2166 2167 // Vector width in bytes. 2168 const int Matcher::vector_width_in_bytes(BasicType bt) { 2169 assert(MaxVectorSize == 8, ""); 2170 return 8; 2171 } 2172 2173 // Vector ideal reg. 2174 const int Matcher::vector_ideal_reg(int size) { 2175 assert(MaxVectorSize == 8 && size == 8, ""); 2176 return Op_RegL; 2177 } 2178 2179 const int Matcher::vector_shift_count_ideal_reg(int size) { 2180 fatal("vector shift is not supported"); 2181 return Node::NotAMachineReg; 2182 } 2183 2184 // Limits on vector size (number of elements) loaded into vector. 2185 const int Matcher::max_vector_size(const BasicType bt) { 2186 assert(is_java_primitive(bt), "only primitive type vectors"); 2187 return vector_width_in_bytes(bt)/type2aelembytes(bt); 2188 } 2189 2190 const int Matcher::min_vector_size(const BasicType bt) { 2191 return max_vector_size(bt); // Same as max. 2192 } 2193 2194 // PPC doesn't support misaligned vectors store/load. 2195 const bool Matcher::misaligned_vectors_ok() { 2196 return false; 2197 } 2198 2199 // PPC AES support not yet implemented 2200 const bool Matcher::pass_original_key_for_aes() { 2201 return false; 2202 } 2203 2204 // RETURNS: whether this branch offset is short enough that a short 2205 // branch can be used. 2206 // 2207 // If the platform does not provide any short branch variants, then 2208 // this method should return `false' for offset 0. 2209 // 2210 // `Compile::Fill_buffer' will decide on basis of this information 2211 // whether to do the pass `Compile::Shorten_branches' at all. 2212 // 2213 // And `Compile::Shorten_branches' will decide on basis of this 2214 // information whether to replace particular branch sites by short 2215 // ones. 2216 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) { 2217 // Is the offset within the range of a ppc64 pc relative branch? 2218 bool b; 2219 2220 const int safety_zone = 3 * BytesPerInstWord; 2221 b = Assembler::is_simm((offset<0 ? offset-safety_zone : offset+safety_zone), 2222 29 - 16 + 1 + 2); 2223 return b; 2224 } 2225 2226 const bool Matcher::isSimpleConstant64(jlong value) { 2227 // Probably always true, even if a temp register is required. 2228 return true; 2229 } 2230 /* TODO: PPC port 2231 // Make a new machine dependent decode node (with its operands). 2232 MachTypeNode *Matcher::make_decode_node(Compile *C) { 2233 assert(Universe::narrow_oop_base() == NULL && Universe::narrow_oop_shift() == 0, 2234 "This method is only implemented for unscaled cOops mode so far"); 2235 MachTypeNode *decode = decodeN_unscaledNode(); 2236 decode->set_opnd_array(0, iRegPdstOper()); 2237 decode->set_opnd_array(1, iRegNsrcOper()); 2238 return decode; 2239 } 2240 */ 2241 // Threshold size for cleararray. 2242 const int Matcher::init_array_short_size = 8 * BytesPerLong; 2243 2244 // false => size gets scaled to BytesPerLong, ok. 2245 const bool Matcher::init_array_count_is_in_bytes = false; 2246 2247 // Use conditional move (CMOVL) on Power7. 2248 const int Matcher::long_cmove_cost() { return 0; } // this only makes long cmoves more expensive than int cmoves 2249 2250 // Suppress CMOVF. Conditional move available (sort of) on PPC64 only from P7 onwards. Not exploited yet. 2251 // fsel doesn't accept a condition register as input, so this would be slightly different. 2252 const int Matcher::float_cmove_cost() { return ConditionalMoveLimit; } 2253 2254 // Power6 requires postalloc expand (see block.cpp for description of postalloc expand). 2255 const bool Matcher::require_postalloc_expand = true; 2256 2257 // Should the Matcher clone shifts on addressing modes, expecting them to 2258 // be subsumed into complex addressing expressions or compute them into 2259 // registers? True for Intel but false for most RISCs. 2260 const bool Matcher::clone_shift_expressions = false; 2261 2262 // Do we need to mask the count passed to shift instructions or does 2263 // the cpu only look at the lower 5/6 bits anyway? 2264 // Off, as masks are generated in expand rules where required. 2265 // Constant shift counts are handled in Ideal phase. 2266 const bool Matcher::need_masked_shift_count = false; 2267 2268 // This affects two different things: 2269 // - how Decode nodes are matched 2270 // - how ImplicitNullCheck opportunities are recognized 2271 // If true, the matcher will try to remove all Decodes and match them 2272 // (as operands) into nodes. NullChecks are not prepared to deal with 2273 // Decodes by final_graph_reshaping(). 2274 // If false, final_graph_reshaping() forces the decode behind the Cmp 2275 // for a NullCheck. The matcher matches the Decode node into a register. 2276 // Implicit_null_check optimization moves the Decode along with the 2277 // memory operation back up before the NullCheck. 2278 bool Matcher::narrow_oop_use_complex_address() { 2279 // TODO: PPC port if (MatchDecodeNodes) return true; 2280 return false; 2281 } 2282 2283 bool Matcher::narrow_klass_use_complex_address() { 2284 NOT_LP64(ShouldNotCallThis()); 2285 assert(UseCompressedClassPointers, "only for compressed klass code"); 2286 // TODO: PPC port if (MatchDecodeNodes) return true; 2287 return false; 2288 } 2289 2290 // Is it better to copy float constants, or load them directly from memory? 2291 // Intel can load a float constant from a direct address, requiring no 2292 // extra registers. Most RISCs will have to materialize an address into a 2293 // register first, so they would do better to copy the constant from stack. 2294 const bool Matcher::rematerialize_float_constants = false; 2295 2296 // If CPU can load and store mis-aligned doubles directly then no fixup is 2297 // needed. Else we split the double into 2 integer pieces and move it 2298 // piece-by-piece. Only happens when passing doubles into C code as the 2299 // Java calling convention forces doubles to be aligned. 2300 const bool Matcher::misaligned_doubles_ok = true; 2301 2302 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) { 2303 Unimplemented(); 2304 } 2305 2306 // Advertise here if the CPU requires explicit rounding operations 2307 // to implement the UseStrictFP mode. 2308 const bool Matcher::strict_fp_requires_explicit_rounding = false; 2309 2310 // Do floats take an entire double register or just half? 2311 // 2312 // A float occupies a ppc64 double register. For the allocator, a 2313 // ppc64 double register appears as a pair of float registers. 2314 bool Matcher::float_in_double() { return true; } 2315 2316 // Do ints take an entire long register or just half? 2317 // The relevant question is how the int is callee-saved: 2318 // the whole long is written but de-opt'ing will have to extract 2319 // the relevant 32 bits. 2320 const bool Matcher::int_in_long = true; 2321 2322 // Constants for c2c and c calling conventions. 2323 2324 const MachRegisterNumbers iarg_reg[8] = { 2325 R3_num, R4_num, R5_num, R6_num, 2326 R7_num, R8_num, R9_num, R10_num 2327 }; 2328 2329 const MachRegisterNumbers farg_reg[13] = { 2330 F1_num, F2_num, F3_num, F4_num, 2331 F5_num, F6_num, F7_num, F8_num, 2332 F9_num, F10_num, F11_num, F12_num, 2333 F13_num 2334 }; 2335 2336 const int num_iarg_registers = sizeof(iarg_reg) / sizeof(iarg_reg[0]); 2337 2338 const int num_farg_registers = sizeof(farg_reg) / sizeof(farg_reg[0]); 2339 2340 // Return whether or not this register is ever used as an argument. This 2341 // function is used on startup to build the trampoline stubs in generateOptoStub. 2342 // Registers not mentioned will be killed by the VM call in the trampoline, and 2343 // arguments in those registers not be available to the callee. 2344 bool Matcher::can_be_java_arg(int reg) { 2345 // We return true for all registers contained in iarg_reg[] and 2346 // farg_reg[] and their virtual halves. 2347 // We must include the virtual halves in order to get STDs and LDs 2348 // instead of STWs and LWs in the trampoline stubs. 2349 2350 if ( reg == R3_num || reg == R3_H_num 2351 || reg == R4_num || reg == R4_H_num 2352 || reg == R5_num || reg == R5_H_num 2353 || reg == R6_num || reg == R6_H_num 2354 || reg == R7_num || reg == R7_H_num 2355 || reg == R8_num || reg == R8_H_num 2356 || reg == R9_num || reg == R9_H_num 2357 || reg == R10_num || reg == R10_H_num) 2358 return true; 2359 2360 if ( reg == F1_num || reg == F1_H_num 2361 || reg == F2_num || reg == F2_H_num 2362 || reg == F3_num || reg == F3_H_num 2363 || reg == F4_num || reg == F4_H_num 2364 || reg == F5_num || reg == F5_H_num 2365 || reg == F6_num || reg == F6_H_num 2366 || reg == F7_num || reg == F7_H_num 2367 || reg == F8_num || reg == F8_H_num 2368 || reg == F9_num || reg == F9_H_num 2369 || reg == F10_num || reg == F10_H_num 2370 || reg == F11_num || reg == F11_H_num 2371 || reg == F12_num || reg == F12_H_num 2372 || reg == F13_num || reg == F13_H_num) 2373 return true; 2374 2375 return false; 2376 } 2377 2378 bool Matcher::is_spillable_arg(int reg) { 2379 return can_be_java_arg(reg); 2380 } 2381 2382 bool Matcher::use_asm_for_ldiv_by_con(jlong divisor) { 2383 return false; 2384 } 2385 2386 // Register for DIVI projection of divmodI. 2387 RegMask Matcher::divI_proj_mask() { 2388 ShouldNotReachHere(); 2389 return RegMask(); 2390 } 2391 2392 // Register for MODI projection of divmodI. 2393 RegMask Matcher::modI_proj_mask() { 2394 ShouldNotReachHere(); 2395 return RegMask(); 2396 } 2397 2398 // Register for DIVL projection of divmodL. 2399 RegMask Matcher::divL_proj_mask() { 2400 ShouldNotReachHere(); 2401 return RegMask(); 2402 } 2403 2404 // Register for MODL projection of divmodL. 2405 RegMask Matcher::modL_proj_mask() { 2406 ShouldNotReachHere(); 2407 return RegMask(); 2408 } 2409 2410 const RegMask Matcher::method_handle_invoke_SP_save_mask() { 2411 return RegMask(); 2412 } 2413 2414 %} 2415 2416 //----------ENCODING BLOCK----------------------------------------------------- 2417 // This block specifies the encoding classes used by the compiler to output 2418 // byte streams. Encoding classes are parameterized macros used by 2419 // Machine Instruction Nodes in order to generate the bit encoding of the 2420 // instruction. Operands specify their base encoding interface with the 2421 // interface keyword. There are currently supported four interfaces, 2422 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an 2423 // operand to generate a function which returns its register number when 2424 // queried. CONST_INTER causes an operand to generate a function which 2425 // returns the value of the constant when queried. MEMORY_INTER causes an 2426 // operand to generate four functions which return the Base Register, the 2427 // Index Register, the Scale Value, and the Offset Value of the operand when 2428 // queried. COND_INTER causes an operand to generate six functions which 2429 // return the encoding code (ie - encoding bits for the instruction) 2430 // associated with each basic boolean condition for a conditional instruction. 2431 // 2432 // Instructions specify two basic values for encoding. Again, a function 2433 // is available to check if the constant displacement is an oop. They use the 2434 // ins_encode keyword to specify their encoding classes (which must be 2435 // a sequence of enc_class names, and their parameters, specified in 2436 // the encoding block), and they use the 2437 // opcode keyword to specify, in order, their primary, secondary, and 2438 // tertiary opcode. Only the opcode sections which a particular instruction 2439 // needs for encoding need to be specified. 2440 encode %{ 2441 enc_class enc_unimplemented %{ 2442 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 2443 MacroAssembler _masm(&cbuf); 2444 __ unimplemented("Unimplemented mach node encoding in AD file.", 13); 2445 %} 2446 2447 enc_class enc_untested %{ 2448 #ifdef ASSERT 2449 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 2450 MacroAssembler _masm(&cbuf); 2451 __ untested("Untested mach node encoding in AD file."); 2452 #else 2453 // TODO: PPC port $archOpcode(ppc64Opcode_none); 2454 #endif 2455 %} 2456 2457 enc_class enc_lbz(iRegIdst dst, memory mem) %{ 2458 // TODO: PPC port $archOpcode(ppc64Opcode_lbz); 2459 MacroAssembler _masm(&cbuf); 2460 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); 2461 __ lbz($dst$$Register, Idisp, $mem$$base$$Register); 2462 %} 2463 2464 // Load acquire. 2465 enc_class enc_lbz_ac(iRegIdst dst, memory mem) %{ 2466 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 2467 MacroAssembler _masm(&cbuf); 2468 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); 2469 __ lbz($dst$$Register, Idisp, $mem$$base$$Register); 2470 __ twi_0($dst$$Register); 2471 __ isync(); 2472 %} 2473 2474 enc_class enc_lhz(iRegIdst dst, memory mem) %{ 2475 // TODO: PPC port $archOpcode(ppc64Opcode_lhz); 2476 2477 MacroAssembler _masm(&cbuf); 2478 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); 2479 __ lhz($dst$$Register, Idisp, $mem$$base$$Register); 2480 %} 2481 2482 // Load acquire. 2483 enc_class enc_lhz_ac(iRegIdst dst, memory mem) %{ 2484 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 2485 2486 MacroAssembler _masm(&cbuf); 2487 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); 2488 __ lhz($dst$$Register, Idisp, $mem$$base$$Register); 2489 __ twi_0($dst$$Register); 2490 __ isync(); 2491 %} 2492 2493 enc_class enc_lwz(iRegIdst dst, memory mem) %{ 2494 // TODO: PPC port $archOpcode(ppc64Opcode_lwz); 2495 2496 MacroAssembler _masm(&cbuf); 2497 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); 2498 __ lwz($dst$$Register, Idisp, $mem$$base$$Register); 2499 %} 2500 2501 // Load acquire. 2502 enc_class enc_lwz_ac(iRegIdst dst, memory mem) %{ 2503 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 2504 2505 MacroAssembler _masm(&cbuf); 2506 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); 2507 __ lwz($dst$$Register, Idisp, $mem$$base$$Register); 2508 __ twi_0($dst$$Register); 2509 __ isync(); 2510 %} 2511 2512 enc_class enc_ld(iRegLdst dst, memoryAlg4 mem) %{ 2513 // TODO: PPC port $archOpcode(ppc64Opcode_ld); 2514 MacroAssembler _masm(&cbuf); 2515 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); 2516 // Operand 'ds' requires 4-alignment. 2517 assert((Idisp & 0x3) == 0, "unaligned offset"); 2518 __ ld($dst$$Register, Idisp, $mem$$base$$Register); 2519 %} 2520 2521 // Load acquire. 2522 enc_class enc_ld_ac(iRegLdst dst, memoryAlg4 mem) %{ 2523 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 2524 MacroAssembler _masm(&cbuf); 2525 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); 2526 // Operand 'ds' requires 4-alignment. 2527 assert((Idisp & 0x3) == 0, "unaligned offset"); 2528 __ ld($dst$$Register, Idisp, $mem$$base$$Register); 2529 __ twi_0($dst$$Register); 2530 __ isync(); 2531 %} 2532 2533 enc_class enc_lfd(RegF dst, memory mem) %{ 2534 // TODO: PPC port $archOpcode(ppc64Opcode_lfd); 2535 MacroAssembler _masm(&cbuf); 2536 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); 2537 __ lfd($dst$$FloatRegister, Idisp, $mem$$base$$Register); 2538 %} 2539 2540 enc_class enc_load_long_constL(iRegLdst dst, immL src, iRegLdst toc) %{ 2541 // TODO: PPC port $archOpcode(ppc64Opcode_ld); 2542 2543 MacroAssembler _masm(&cbuf); 2544 int toc_offset = 0; 2545 2546 if (!ra_->C->in_scratch_emit_size()) { 2547 address const_toc_addr; 2548 // Create a non-oop constant, no relocation needed. 2549 // If it is an IC, it has a virtual_call_Relocation. 2550 const_toc_addr = __ long_constant((jlong)$src$$constant); 2551 2552 // Get the constant's TOC offset. 2553 toc_offset = __ offset_to_method_toc(const_toc_addr); 2554 2555 // Keep the current instruction offset in mind. 2556 ((loadConLNode*)this)->_cbuf_insts_offset = __ offset(); 2557 } 2558 2559 __ ld($dst$$Register, toc_offset, $toc$$Register); 2560 %} 2561 2562 enc_class enc_load_long_constL_hi(iRegLdst dst, iRegLdst toc, immL src) %{ 2563 // TODO: PPC port $archOpcode(ppc64Opcode_addis); 2564 2565 MacroAssembler _masm(&cbuf); 2566 2567 if (!ra_->C->in_scratch_emit_size()) { 2568 address const_toc_addr; 2569 // Create a non-oop constant, no relocation needed. 2570 // If it is an IC, it has a virtual_call_Relocation. 2571 const_toc_addr = __ long_constant((jlong)$src$$constant); 2572 2573 // Get the constant's TOC offset. 2574 const int toc_offset = __ offset_to_method_toc(const_toc_addr); 2575 // Store the toc offset of the constant. 2576 ((loadConL_hiNode*)this)->_const_toc_offset = toc_offset; 2577 2578 // Also keep the current instruction offset in mind. 2579 ((loadConL_hiNode*)this)->_cbuf_insts_offset = __ offset(); 2580 } 2581 2582 __ addis($dst$$Register, $toc$$Register, MacroAssembler::largeoffset_si16_si16_hi(_const_toc_offset)); 2583 %} 2584 2585 %} // encode 2586 2587 source %{ 2588 2589 typedef struct { 2590 loadConL_hiNode *_large_hi; 2591 loadConL_loNode *_large_lo; 2592 loadConLNode *_small; 2593 MachNode *_last; 2594 } loadConLNodesTuple; 2595 2596 loadConLNodesTuple loadConLNodesTuple_create(Compile *C, PhaseRegAlloc *ra_, Node *toc, immLOper *immSrc, 2597 OptoReg::Name reg_second, OptoReg::Name reg_first) { 2598 loadConLNodesTuple nodes; 2599 2600 const bool large_constant_pool = true; // TODO: PPC port C->cfg()->_consts_size > 4000; 2601 if (large_constant_pool) { 2602 // Create new nodes. 2603 loadConL_hiNode *m1 = loadConL_hiNode(); 2604 loadConL_loNode *m2 = loadConL_loNode(); 2605 2606 // inputs for new nodes 2607 m1->add_req(NULL, toc); 2608 m2->add_req(NULL, m1); 2609 2610 // operands for new nodes 2611 m1->_opnds[0] = iRegLdstOper(); // dst 2612 m1->_opnds[1] = immSrc; // src 2613 m1->_opnds[2] = iRegPdstOper(); // toc 2614 m2->_opnds[0] = iRegLdstOper(); // dst 2615 m2->_opnds[1] = immSrc; // src 2616 m2->_opnds[2] = iRegLdstOper(); // base 2617 2618 // Initialize ins_attrib TOC fields. 2619 m1->_const_toc_offset = -1; 2620 m2->_const_toc_offset_hi_node = m1; 2621 2622 // Initialize ins_attrib instruction offset. 2623 m1->_cbuf_insts_offset = -1; 2624 2625 // register allocation for new nodes 2626 ra_->set_pair(m1->_idx, reg_second, reg_first); 2627 ra_->set_pair(m2->_idx, reg_second, reg_first); 2628 2629 // Create result. 2630 nodes._large_hi = m1; 2631 nodes._large_lo = m2; 2632 nodes._small = NULL; 2633 nodes._last = nodes._large_lo; 2634 assert(m2->bottom_type()->isa_long(), "must be long"); 2635 } else { 2636 loadConLNode *m2 = loadConLNode(); 2637 2638 // inputs for new nodes 2639 m2->add_req(NULL, toc); 2640 2641 // operands for new nodes 2642 m2->_opnds[0] = iRegLdstOper(); // dst 2643 m2->_opnds[1] = immSrc; // src 2644 m2->_opnds[2] = iRegPdstOper(); // toc 2645 2646 // Initialize ins_attrib instruction offset. 2647 m2->_cbuf_insts_offset = -1; 2648 2649 // register allocation for new nodes 2650 ra_->set_pair(m2->_idx, reg_second, reg_first); 2651 2652 // Create result. 2653 nodes._large_hi = NULL; 2654 nodes._large_lo = NULL; 2655 nodes._small = m2; 2656 nodes._last = nodes._small; 2657 assert(m2->bottom_type()->isa_long(), "must be long"); 2658 } 2659 2660 return nodes; 2661 } 2662 2663 %} // source 2664 2665 encode %{ 2666 // Postalloc expand emitter for loading a long constant from the method's TOC. 2667 // Enc_class needed as consttanttablebase is not supported by postalloc 2668 // expand. 2669 enc_class postalloc_expand_load_long_constant(iRegLdst dst, immL src, iRegLdst toc) %{ 2670 // Create new nodes. 2671 loadConLNodesTuple loadConLNodes = 2672 loadConLNodesTuple_create(C, ra_, n_toc, op_src, 2673 ra_->get_reg_second(this), ra_->get_reg_first(this)); 2674 2675 // Push new nodes. 2676 if (loadConLNodes._large_hi) nodes->push(loadConLNodes._large_hi); 2677 if (loadConLNodes._last) nodes->push(loadConLNodes._last); 2678 2679 // some asserts 2680 assert(nodes->length() >= 1, "must have created at least 1 node"); 2681 assert(loadConLNodes._last->bottom_type()->isa_long(), "must be long"); 2682 %} 2683 2684 enc_class enc_load_long_constP(iRegLdst dst, immP src, iRegLdst toc) %{ 2685 // TODO: PPC port $archOpcode(ppc64Opcode_ld); 2686 2687 MacroAssembler _masm(&cbuf); 2688 int toc_offset = 0; 2689 2690 if (!ra_->C->in_scratch_emit_size()) { 2691 intptr_t val = $src$$constant; 2692 relocInfo::relocType constant_reloc = $src->constant_reloc(); // src 2693 address const_toc_addr; 2694 if (constant_reloc == relocInfo::oop_type) { 2695 // Create an oop constant and a corresponding relocation. 2696 AddressLiteral a = __ allocate_oop_address((jobject)val); 2697 const_toc_addr = __ address_constant((address)a.value(), RelocationHolder::none); 2698 __ relocate(a.rspec()); 2699 } else if (constant_reloc == relocInfo::metadata_type) { 2700 AddressLiteral a = __ allocate_metadata_address((Metadata *)val); 2701 const_toc_addr = __ address_constant((address)a.value(), RelocationHolder::none); 2702 __ relocate(a.rspec()); 2703 } else { 2704 // Create a non-oop constant, no relocation needed. 2705 const_toc_addr = __ long_constant((jlong)$src$$constant); 2706 } 2707 2708 // Get the constant's TOC offset. 2709 toc_offset = __ offset_to_method_toc(const_toc_addr); 2710 } 2711 2712 __ ld($dst$$Register, toc_offset, $toc$$Register); 2713 %} 2714 2715 enc_class enc_load_long_constP_hi(iRegLdst dst, immP src, iRegLdst toc) %{ 2716 // TODO: PPC port $archOpcode(ppc64Opcode_addis); 2717 2718 MacroAssembler _masm(&cbuf); 2719 if (!ra_->C->in_scratch_emit_size()) { 2720 intptr_t val = $src$$constant; 2721 relocInfo::relocType constant_reloc = $src->constant_reloc(); // src 2722 address const_toc_addr; 2723 if (constant_reloc == relocInfo::oop_type) { 2724 // Create an oop constant and a corresponding relocation. 2725 AddressLiteral a = __ allocate_oop_address((jobject)val); 2726 const_toc_addr = __ address_constant((address)a.value(), RelocationHolder::none); 2727 __ relocate(a.rspec()); 2728 } else if (constant_reloc == relocInfo::metadata_type) { 2729 AddressLiteral a = __ allocate_metadata_address((Metadata *)val); 2730 const_toc_addr = __ address_constant((address)a.value(), RelocationHolder::none); 2731 __ relocate(a.rspec()); 2732 } else { // non-oop pointers, e.g. card mark base, heap top 2733 // Create a non-oop constant, no relocation needed. 2734 const_toc_addr = __ long_constant((jlong)$src$$constant); 2735 } 2736 2737 // Get the constant's TOC offset. 2738 const int toc_offset = __ offset_to_method_toc(const_toc_addr); 2739 // Store the toc offset of the constant. 2740 ((loadConP_hiNode*)this)->_const_toc_offset = toc_offset; 2741 } 2742 2743 __ addis($dst$$Register, $toc$$Register, MacroAssembler::largeoffset_si16_si16_hi(_const_toc_offset)); 2744 %} 2745 2746 // Postalloc expand emitter for loading a ptr constant from the method's TOC. 2747 // Enc_class needed as consttanttablebase is not supported by postalloc 2748 // expand. 2749 enc_class postalloc_expand_load_ptr_constant(iRegPdst dst, immP src, iRegLdst toc) %{ 2750 const bool large_constant_pool = true; // TODO: PPC port C->cfg()->_consts_size > 4000; 2751 if (large_constant_pool) { 2752 // Create new nodes. 2753 loadConP_hiNode *m1 = loadConP_hiNode(); 2754 loadConP_loNode *m2 = loadConP_loNode(); 2755 2756 // inputs for new nodes 2757 m1->add_req(NULL, n_toc); 2758 m2->add_req(NULL, m1); 2759 2760 // operands for new nodes 2761 m1->_opnds[0] = iRegPdstOper(); // dst 2762 m1->_opnds[1] = op_src; // src 2763 m1->_opnds[2] = iRegPdstOper(); // toc 2764 m2->_opnds[0] = iRegPdstOper(); // dst 2765 m2->_opnds[1] = op_src; // src 2766 m2->_opnds[2] = iRegLdstOper(); // base 2767 2768 // Initialize ins_attrib TOC fields. 2769 m1->_const_toc_offset = -1; 2770 m2->_const_toc_offset_hi_node = m1; 2771 2772 // Register allocation for new nodes. 2773 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 2774 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 2775 2776 nodes->push(m1); 2777 nodes->push(m2); 2778 assert(m2->bottom_type()->isa_ptr(), "must be ptr"); 2779 } else { 2780 loadConPNode *m2 = loadConPNode(); 2781 2782 // inputs for new nodes 2783 m2->add_req(NULL, n_toc); 2784 2785 // operands for new nodes 2786 m2->_opnds[0] = iRegPdstOper(); // dst 2787 m2->_opnds[1] = op_src; // src 2788 m2->_opnds[2] = iRegPdstOper(); // toc 2789 2790 // Register allocation for new nodes. 2791 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 2792 2793 nodes->push(m2); 2794 assert(m2->bottom_type()->isa_ptr(), "must be ptr"); 2795 } 2796 %} 2797 2798 // Enc_class needed as consttanttablebase is not supported by postalloc 2799 // expand. 2800 enc_class postalloc_expand_load_float_constant(regF dst, immF src, iRegLdst toc) %{ 2801 bool large_constant_pool = true; // TODO: PPC port C->cfg()->_consts_size > 4000; 2802 2803 MachNode *m2; 2804 if (large_constant_pool) { 2805 m2 = loadConFCompNode(); 2806 } else { 2807 m2 = loadConFNode(); 2808 } 2809 // inputs for new nodes 2810 m2->add_req(NULL, n_toc); 2811 2812 // operands for new nodes 2813 m2->_opnds[0] = op_dst; 2814 m2->_opnds[1] = op_src; 2815 m2->_opnds[2] = iRegPdstOper(); // constanttablebase 2816 2817 // register allocation for new nodes 2818 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 2819 nodes->push(m2); 2820 %} 2821 2822 // Enc_class needed as consttanttablebase is not supported by postalloc 2823 // expand. 2824 enc_class postalloc_expand_load_double_constant(regD dst, immD src, iRegLdst toc) %{ 2825 bool large_constant_pool = true; // TODO: PPC port C->cfg()->_consts_size > 4000; 2826 2827 MachNode *m2; 2828 if (large_constant_pool) { 2829 m2 = loadConDCompNode(); 2830 } else { 2831 m2 = loadConDNode(); 2832 } 2833 // inputs for new nodes 2834 m2->add_req(NULL, n_toc); 2835 2836 // operands for new nodes 2837 m2->_opnds[0] = op_dst; 2838 m2->_opnds[1] = op_src; 2839 m2->_opnds[2] = iRegPdstOper(); // constanttablebase 2840 2841 // register allocation for new nodes 2842 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 2843 nodes->push(m2); 2844 %} 2845 2846 enc_class enc_stw(iRegIsrc src, memory mem) %{ 2847 // TODO: PPC port $archOpcode(ppc64Opcode_stw); 2848 MacroAssembler _masm(&cbuf); 2849 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); 2850 __ stw($src$$Register, Idisp, $mem$$base$$Register); 2851 %} 2852 2853 enc_class enc_std(iRegIsrc src, memoryAlg4 mem) %{ 2854 // TODO: PPC port $archOpcode(ppc64Opcode_std); 2855 MacroAssembler _masm(&cbuf); 2856 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); 2857 // Operand 'ds' requires 4-alignment. 2858 assert((Idisp & 0x3) == 0, "unaligned offset"); 2859 __ std($src$$Register, Idisp, $mem$$base$$Register); 2860 %} 2861 2862 enc_class enc_stfs(RegF src, memory mem) %{ 2863 // TODO: PPC port $archOpcode(ppc64Opcode_stfs); 2864 MacroAssembler _masm(&cbuf); 2865 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); 2866 __ stfs($src$$FloatRegister, Idisp, $mem$$base$$Register); 2867 %} 2868 2869 enc_class enc_stfd(RegF src, memory mem) %{ 2870 // TODO: PPC port $archOpcode(ppc64Opcode_stfd); 2871 MacroAssembler _masm(&cbuf); 2872 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); 2873 __ stfd($src$$FloatRegister, Idisp, $mem$$base$$Register); 2874 %} 2875 2876 // Use release_store for card-marking to ensure that previous 2877 // oop-stores are visible before the card-mark change. 2878 enc_class enc_cms_card_mark(memory mem, iRegLdst releaseFieldAddr) %{ 2879 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 2880 // FIXME: Implement this as a cmove and use a fixed condition code 2881 // register which is written on every transition to compiled code, 2882 // e.g. in call-stub and when returning from runtime stubs. 2883 // 2884 // Proposed code sequence for the cmove implementation: 2885 // 2886 // Label skip_release; 2887 // __ beq(CCRfixed, skip_release); 2888 // __ release(); 2889 // __ bind(skip_release); 2890 // __ stb(card mark); 2891 2892 MacroAssembler _masm(&cbuf); 2893 Label skip_storestore; 2894 2895 #if 0 // TODO: PPC port 2896 // Check CMSCollectorCardTableModRefBSExt::_requires_release and do the 2897 // StoreStore barrier conditionally. 2898 __ lwz(R0, 0, $releaseFieldAddr$$Register); 2899 __ cmpwi(CCR0, R0, 0); 2900 __ beq_predict_taken(CCR0, skip_storestore); 2901 #endif 2902 __ li(R0, 0); 2903 __ membar(Assembler::StoreStore); 2904 #if 0 // TODO: PPC port 2905 __ bind(skip_storestore); 2906 #endif 2907 2908 // Do the store. 2909 if ($mem$$index == 0) { 2910 __ stb(R0, $mem$$disp, $mem$$base$$Register); 2911 } else { 2912 assert(0 == $mem$$disp, "no displacement possible with indexed load/stores on ppc"); 2913 __ stbx(R0, $mem$$base$$Register, $mem$$index$$Register); 2914 } 2915 %} 2916 2917 enc_class postalloc_expand_encode_oop(iRegNdst dst, iRegPdst src, flagsReg crx) %{ 2918 2919 if (VM_Version::has_isel()) { 2920 // use isel instruction with Power 7 2921 cmpP_reg_imm16Node *n_compare = cmpP_reg_imm16Node(); 2922 encodeP_subNode *n_sub_base = encodeP_subNode(); 2923 encodeP_shiftNode *n_shift = encodeP_shiftNode(); 2924 cond_set_0_oopNode *n_cond_set = cond_set_0_oopNode(); 2925 2926 n_compare->add_req(n_region, n_src); 2927 n_compare->_opnds[0] = op_crx; 2928 n_compare->_opnds[1] = op_src; 2929 n_compare->_opnds[2] = immL16Oper(0); 2930 2931 n_sub_base->add_req(n_region, n_src); 2932 n_sub_base->_opnds[0] = op_dst; 2933 n_sub_base->_opnds[1] = op_src; 2934 n_sub_base->_bottom_type = _bottom_type; 2935 2936 n_shift->add_req(n_region, n_sub_base); 2937 n_shift->_opnds[0] = op_dst; 2938 n_shift->_opnds[1] = op_dst; 2939 n_shift->_bottom_type = _bottom_type; 2940 2941 n_cond_set->add_req(n_region, n_compare, n_shift); 2942 n_cond_set->_opnds[0] = op_dst; 2943 n_cond_set->_opnds[1] = op_crx; 2944 n_cond_set->_opnds[2] = op_dst; 2945 n_cond_set->_bottom_type = _bottom_type; 2946 2947 ra_->set_pair(n_compare->_idx, ra_->get_reg_second(n_crx), ra_->get_reg_first(n_crx)); 2948 ra_->set_pair(n_sub_base->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 2949 ra_->set_pair(n_shift->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 2950 ra_->set_pair(n_cond_set->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 2951 2952 nodes->push(n_compare); 2953 nodes->push(n_sub_base); 2954 nodes->push(n_shift); 2955 nodes->push(n_cond_set); 2956 2957 } else { 2958 // before Power 7 2959 moveRegNode *n_move = moveRegNode(); 2960 cmpP_reg_imm16Node *n_compare = cmpP_reg_imm16Node(); 2961 encodeP_shiftNode *n_shift = encodeP_shiftNode(); 2962 cond_sub_baseNode *n_sub_base = cond_sub_baseNode(); 2963 2964 n_move->add_req(n_region, n_src); 2965 n_move->_opnds[0] = op_dst; 2966 n_move->_opnds[1] = op_src; 2967 ra_->set_oop(n_move, true); // Until here, 'n_move' still produces an oop. 2968 2969 n_compare->add_req(n_region, n_src); 2970 n_compare->add_prec(n_move); 2971 2972 n_compare->_opnds[0] = op_crx; 2973 n_compare->_opnds[1] = op_src; 2974 n_compare->_opnds[2] = immL16Oper(0); 2975 2976 n_sub_base->add_req(n_region, n_compare, n_src); 2977 n_sub_base->_opnds[0] = op_dst; 2978 n_sub_base->_opnds[1] = op_crx; 2979 n_sub_base->_opnds[2] = op_src; 2980 n_sub_base->_bottom_type = _bottom_type; 2981 2982 n_shift->add_req(n_region, n_sub_base); 2983 n_shift->_opnds[0] = op_dst; 2984 n_shift->_opnds[1] = op_dst; 2985 n_shift->_bottom_type = _bottom_type; 2986 2987 ra_->set_pair(n_shift->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 2988 ra_->set_pair(n_compare->_idx, ra_->get_reg_second(n_crx), ra_->get_reg_first(n_crx)); 2989 ra_->set_pair(n_sub_base->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 2990 ra_->set_pair(n_move->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 2991 2992 nodes->push(n_move); 2993 nodes->push(n_compare); 2994 nodes->push(n_sub_base); 2995 nodes->push(n_shift); 2996 } 2997 2998 assert(!(ra_->is_oop(this)), "sanity"); // This is not supposed to be GC'ed. 2999 %} 3000 3001 enc_class postalloc_expand_encode_oop_not_null(iRegNdst dst, iRegPdst src) %{ 3002 3003 encodeP_subNode *n1 = encodeP_subNode(); 3004 n1->add_req(n_region, n_src); 3005 n1->_opnds[0] = op_dst; 3006 n1->_opnds[1] = op_src; 3007 n1->_bottom_type = _bottom_type; 3008 3009 encodeP_shiftNode *n2 = encodeP_shiftNode(); 3010 n2->add_req(n_region, n1); 3011 n2->_opnds[0] = op_dst; 3012 n2->_opnds[1] = op_dst; 3013 n2->_bottom_type = _bottom_type; 3014 ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 3015 ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 3016 3017 nodes->push(n1); 3018 nodes->push(n2); 3019 assert(!(ra_->is_oop(this)), "sanity"); // This is not supposed to be GC'ed. 3020 %} 3021 3022 enc_class postalloc_expand_decode_oop(iRegPdst dst, iRegNsrc src, flagsReg crx) %{ 3023 decodeN_shiftNode *n_shift = decodeN_shiftNode(); 3024 cmpN_reg_imm0Node *n_compare = cmpN_reg_imm0Node(); 3025 3026 n_compare->add_req(n_region, n_src); 3027 n_compare->_opnds[0] = op_crx; 3028 n_compare->_opnds[1] = op_src; 3029 n_compare->_opnds[2] = immN_0Oper(TypeNarrowOop::NULL_PTR); 3030 3031 n_shift->add_req(n_region, n_src); 3032 n_shift->_opnds[0] = op_dst; 3033 n_shift->_opnds[1] = op_src; 3034 n_shift->_bottom_type = _bottom_type; 3035 3036 if (VM_Version::has_isel()) { 3037 // use isel instruction with Power 7 3038 3039 decodeN_addNode *n_add_base = decodeN_addNode(); 3040 n_add_base->add_req(n_region, n_shift); 3041 n_add_base->_opnds[0] = op_dst; 3042 n_add_base->_opnds[1] = op_dst; 3043 n_add_base->_bottom_type = _bottom_type; 3044 3045 cond_set_0_ptrNode *n_cond_set = cond_set_0_ptrNode(); 3046 n_cond_set->add_req(n_region, n_compare, n_add_base); 3047 n_cond_set->_opnds[0] = op_dst; 3048 n_cond_set->_opnds[1] = op_crx; 3049 n_cond_set->_opnds[2] = op_dst; 3050 n_cond_set->_bottom_type = _bottom_type; 3051 3052 assert(ra_->is_oop(this) == true, "A decodeN node must produce an oop!"); 3053 ra_->set_oop(n_cond_set, true); 3054 3055 ra_->set_pair(n_shift->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 3056 ra_->set_pair(n_compare->_idx, ra_->get_reg_second(n_crx), ra_->get_reg_first(n_crx)); 3057 ra_->set_pair(n_add_base->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 3058 ra_->set_pair(n_cond_set->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 3059 3060 nodes->push(n_compare); 3061 nodes->push(n_shift); 3062 nodes->push(n_add_base); 3063 nodes->push(n_cond_set); 3064 3065 } else { 3066 // before Power 7 3067 cond_add_baseNode *n_add_base = cond_add_baseNode(); 3068 3069 n_add_base->add_req(n_region, n_compare, n_shift); 3070 n_add_base->_opnds[0] = op_dst; 3071 n_add_base->_opnds[1] = op_crx; 3072 n_add_base->_opnds[2] = op_dst; 3073 n_add_base->_bottom_type = _bottom_type; 3074 3075 assert(ra_->is_oop(this) == true, "A decodeN node must produce an oop!"); 3076 ra_->set_oop(n_add_base, true); 3077 3078 ra_->set_pair(n_shift->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 3079 ra_->set_pair(n_compare->_idx, ra_->get_reg_second(n_crx), ra_->get_reg_first(n_crx)); 3080 ra_->set_pair(n_add_base->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 3081 3082 nodes->push(n_compare); 3083 nodes->push(n_shift); 3084 nodes->push(n_add_base); 3085 } 3086 %} 3087 3088 enc_class postalloc_expand_decode_oop_not_null(iRegPdst dst, iRegNsrc src) %{ 3089 decodeN_shiftNode *n1 = decodeN_shiftNode(); 3090 n1->add_req(n_region, n_src); 3091 n1->_opnds[0] = op_dst; 3092 n1->_opnds[1] = op_src; 3093 n1->_bottom_type = _bottom_type; 3094 3095 decodeN_addNode *n2 = decodeN_addNode(); 3096 n2->add_req(n_region, n1); 3097 n2->_opnds[0] = op_dst; 3098 n2->_opnds[1] = op_dst; 3099 n2->_bottom_type = _bottom_type; 3100 ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 3101 ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 3102 3103 assert(ra_->is_oop(this) == true, "A decodeN node must produce an oop!"); 3104 ra_->set_oop(n2, true); 3105 3106 nodes->push(n1); 3107 nodes->push(n2); 3108 %} 3109 3110 enc_class enc_cmove_reg(iRegIdst dst, flagsReg crx, iRegIsrc src, cmpOp cmp) %{ 3111 // TODO: PPC port $archOpcode(ppc64Opcode_cmove); 3112 3113 MacroAssembler _masm(&cbuf); 3114 int cc = $cmp$$cmpcode; 3115 int flags_reg = $crx$$reg; 3116 Label done; 3117 assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding"); 3118 // Branch if not (cmp crx). 3119 __ bc(cc_to_inverse_boint(cc), cc_to_biint(cc, flags_reg), done); 3120 __ mr($dst$$Register, $src$$Register); 3121 // TODO PPC port __ endgroup_if_needed(_size == 12); 3122 __ bind(done); 3123 %} 3124 3125 enc_class enc_cmove_imm(iRegIdst dst, flagsReg crx, immI16 src, cmpOp cmp) %{ 3126 // TODO: PPC port $archOpcode(ppc64Opcode_cmove); 3127 3128 MacroAssembler _masm(&cbuf); 3129 Label done; 3130 assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding"); 3131 // Branch if not (cmp crx). 3132 __ bc(cc_to_inverse_boint($cmp$$cmpcode), cc_to_biint($cmp$$cmpcode, $crx$$reg), done); 3133 __ li($dst$$Register, $src$$constant); 3134 // TODO PPC port __ endgroup_if_needed(_size == 12); 3135 __ bind(done); 3136 %} 3137 3138 // New atomics. 3139 enc_class enc_GetAndAddI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src) %{ 3140 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 3141 3142 MacroAssembler _masm(&cbuf); 3143 Register Rtmp = R0; 3144 Register Rres = $res$$Register; 3145 Register Rsrc = $src$$Register; 3146 Register Rptr = $mem_ptr$$Register; 3147 bool RegCollision = (Rres == Rsrc) || (Rres == Rptr); 3148 Register Rold = RegCollision ? Rtmp : Rres; 3149 3150 Label Lretry; 3151 __ bind(Lretry); 3152 __ lwarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update()); 3153 __ add(Rtmp, Rsrc, Rold); 3154 __ stwcx_(Rtmp, Rptr); 3155 if (UseStaticBranchPredictionInCompareAndSwapPPC64) { 3156 __ bne_predict_not_taken(CCR0, Lretry); 3157 } else { 3158 __ bne( CCR0, Lretry); 3159 } 3160 if (RegCollision) __ subf(Rres, Rsrc, Rtmp); 3161 __ fence(); 3162 %} 3163 3164 enc_class enc_GetAndAddL(iRegLdst res, iRegPdst mem_ptr, iRegLsrc src) %{ 3165 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 3166 3167 MacroAssembler _masm(&cbuf); 3168 Register Rtmp = R0; 3169 Register Rres = $res$$Register; 3170 Register Rsrc = $src$$Register; 3171 Register Rptr = $mem_ptr$$Register; 3172 bool RegCollision = (Rres == Rsrc) || (Rres == Rptr); 3173 Register Rold = RegCollision ? Rtmp : Rres; 3174 3175 Label Lretry; 3176 __ bind(Lretry); 3177 __ ldarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update()); 3178 __ add(Rtmp, Rsrc, Rold); 3179 __ stdcx_(Rtmp, Rptr); 3180 if (UseStaticBranchPredictionInCompareAndSwapPPC64) { 3181 __ bne_predict_not_taken(CCR0, Lretry); 3182 } else { 3183 __ bne( CCR0, Lretry); 3184 } 3185 if (RegCollision) __ subf(Rres, Rsrc, Rtmp); 3186 __ fence(); 3187 %} 3188 3189 enc_class enc_GetAndSetI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src) %{ 3190 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 3191 3192 MacroAssembler _masm(&cbuf); 3193 Register Rtmp = R0; 3194 Register Rres = $res$$Register; 3195 Register Rsrc = $src$$Register; 3196 Register Rptr = $mem_ptr$$Register; 3197 bool RegCollision = (Rres == Rsrc) || (Rres == Rptr); 3198 Register Rold = RegCollision ? Rtmp : Rres; 3199 3200 Label Lretry; 3201 __ bind(Lretry); 3202 __ lwarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update()); 3203 __ stwcx_(Rsrc, Rptr); 3204 if (UseStaticBranchPredictionInCompareAndSwapPPC64) { 3205 __ bne_predict_not_taken(CCR0, Lretry); 3206 } else { 3207 __ bne( CCR0, Lretry); 3208 } 3209 if (RegCollision) __ mr(Rres, Rtmp); 3210 __ fence(); 3211 %} 3212 3213 enc_class enc_GetAndSetL(iRegLdst res, iRegPdst mem_ptr, iRegLsrc src) %{ 3214 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 3215 3216 MacroAssembler _masm(&cbuf); 3217 Register Rtmp = R0; 3218 Register Rres = $res$$Register; 3219 Register Rsrc = $src$$Register; 3220 Register Rptr = $mem_ptr$$Register; 3221 bool RegCollision = (Rres == Rsrc) || (Rres == Rptr); 3222 Register Rold = RegCollision ? Rtmp : Rres; 3223 3224 Label Lretry; 3225 __ bind(Lretry); 3226 __ ldarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update()); 3227 __ stdcx_(Rsrc, Rptr); 3228 if (UseStaticBranchPredictionInCompareAndSwapPPC64) { 3229 __ bne_predict_not_taken(CCR0, Lretry); 3230 } else { 3231 __ bne( CCR0, Lretry); 3232 } 3233 if (RegCollision) __ mr(Rres, Rtmp); 3234 __ fence(); 3235 %} 3236 3237 // This enc_class is needed so that scheduler gets proper 3238 // input mapping for latency computation. 3239 enc_class enc_andc(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ 3240 // TODO: PPC port $archOpcode(ppc64Opcode_andc); 3241 MacroAssembler _masm(&cbuf); 3242 __ andc($dst$$Register, $src1$$Register, $src2$$Register); 3243 %} 3244 3245 enc_class enc_convI2B_regI__cmove(iRegIdst dst, iRegIsrc src, flagsReg crx, immI16 zero, immI16 notzero) %{ 3246 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 3247 3248 MacroAssembler _masm(&cbuf); 3249 3250 Label done; 3251 __ cmpwi($crx$$CondRegister, $src$$Register, 0); 3252 __ li($dst$$Register, $zero$$constant); 3253 __ beq($crx$$CondRegister, done); 3254 __ li($dst$$Register, $notzero$$constant); 3255 __ bind(done); 3256 %} 3257 3258 enc_class enc_convP2B_regP__cmove(iRegIdst dst, iRegPsrc src, flagsReg crx, immI16 zero, immI16 notzero) %{ 3259 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 3260 3261 MacroAssembler _masm(&cbuf); 3262 3263 Label done; 3264 __ cmpdi($crx$$CondRegister, $src$$Register, 0); 3265 __ li($dst$$Register, $zero$$constant); 3266 __ beq($crx$$CondRegister, done); 3267 __ li($dst$$Register, $notzero$$constant); 3268 __ bind(done); 3269 %} 3270 3271 enc_class enc_cmove_bso_stackSlotL(iRegLdst dst, flagsReg crx, stackSlotL mem ) %{ 3272 // TODO: PPC port $archOpcode(ppc64Opcode_cmove); 3273 3274 MacroAssembler _masm(&cbuf); 3275 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); 3276 Label done; 3277 __ bso($crx$$CondRegister, done); 3278 __ ld($dst$$Register, Idisp, $mem$$base$$Register); 3279 // TODO PPC port __ endgroup_if_needed(_size == 12); 3280 __ bind(done); 3281 %} 3282 3283 enc_class enc_bc(flagsReg crx, cmpOp cmp, Label lbl) %{ 3284 // TODO: PPC port $archOpcode(ppc64Opcode_bc); 3285 3286 MacroAssembler _masm(&cbuf); 3287 Label d; // dummy 3288 __ bind(d); 3289 Label* p = ($lbl$$label); 3290 // `p' is `NULL' when this encoding class is used only to 3291 // determine the size of the encoded instruction. 3292 Label& l = (NULL == p)? d : *(p); 3293 int cc = $cmp$$cmpcode; 3294 int flags_reg = $crx$$reg; 3295 assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding"); 3296 int bhint = Assembler::bhintNoHint; 3297 3298 if (UseStaticBranchPredictionForUncommonPathsPPC64) { 3299 if (_prob <= PROB_NEVER) { 3300 bhint = Assembler::bhintIsNotTaken; 3301 } else if (_prob >= PROB_ALWAYS) { 3302 bhint = Assembler::bhintIsTaken; 3303 } 3304 } 3305 3306 __ bc(Assembler::add_bhint_to_boint(bhint, cc_to_boint(cc)), 3307 cc_to_biint(cc, flags_reg), 3308 l); 3309 %} 3310 3311 enc_class enc_bc_far(flagsReg crx, cmpOp cmp, Label lbl) %{ 3312 // The scheduler doesn't know about branch shortening, so we set the opcode 3313 // to ppc64Opcode_bc in order to hide this detail from the scheduler. 3314 // TODO: PPC port $archOpcode(ppc64Opcode_bc); 3315 3316 MacroAssembler _masm(&cbuf); 3317 Label d; // dummy 3318 __ bind(d); 3319 Label* p = ($lbl$$label); 3320 // `p' is `NULL' when this encoding class is used only to 3321 // determine the size of the encoded instruction. 3322 Label& l = (NULL == p)? d : *(p); 3323 int cc = $cmp$$cmpcode; 3324 int flags_reg = $crx$$reg; 3325 int bhint = Assembler::bhintNoHint; 3326 3327 if (UseStaticBranchPredictionForUncommonPathsPPC64) { 3328 if (_prob <= PROB_NEVER) { 3329 bhint = Assembler::bhintIsNotTaken; 3330 } else if (_prob >= PROB_ALWAYS) { 3331 bhint = Assembler::bhintIsTaken; 3332 } 3333 } 3334 3335 // Tell the conditional far branch to optimize itself when being relocated. 3336 __ bc_far(Assembler::add_bhint_to_boint(bhint, cc_to_boint(cc)), 3337 cc_to_biint(cc, flags_reg), 3338 l, 3339 MacroAssembler::bc_far_optimize_on_relocate); 3340 %} 3341 3342 // Branch used with Power6 scheduling (can be shortened without changing the node). 3343 enc_class enc_bc_short_far(flagsReg crx, cmpOp cmp, Label lbl) %{ 3344 // The scheduler doesn't know about branch shortening, so we set the opcode 3345 // to ppc64Opcode_bc in order to hide this detail from the scheduler. 3346 // TODO: PPC port $archOpcode(ppc64Opcode_bc); 3347 3348 MacroAssembler _masm(&cbuf); 3349 Label d; // dummy 3350 __ bind(d); 3351 Label* p = ($lbl$$label); 3352 // `p' is `NULL' when this encoding class is used only to 3353 // determine the size of the encoded instruction. 3354 Label& l = (NULL == p)? d : *(p); 3355 int cc = $cmp$$cmpcode; 3356 int flags_reg = $crx$$reg; 3357 int bhint = Assembler::bhintNoHint; 3358 3359 if (UseStaticBranchPredictionForUncommonPathsPPC64) { 3360 if (_prob <= PROB_NEVER) { 3361 bhint = Assembler::bhintIsNotTaken; 3362 } else if (_prob >= PROB_ALWAYS) { 3363 bhint = Assembler::bhintIsTaken; 3364 } 3365 } 3366 3367 #if 0 // TODO: PPC port 3368 if (_size == 8) { 3369 // Tell the conditional far branch to optimize itself when being relocated. 3370 __ bc_far(Assembler::add_bhint_to_boint(bhint, cc_to_boint(cc)), 3371 cc_to_biint(cc, flags_reg), 3372 l, 3373 MacroAssembler::bc_far_optimize_on_relocate); 3374 } else { 3375 __ bc (Assembler::add_bhint_to_boint(bhint, cc_to_boint(cc)), 3376 cc_to_biint(cc, flags_reg), 3377 l); 3378 } 3379 #endif 3380 Unimplemented(); 3381 %} 3382 3383 // Postalloc expand emitter for loading a replicatef float constant from 3384 // the method's TOC. 3385 // Enc_class needed as consttanttablebase is not supported by postalloc 3386 // expand. 3387 enc_class postalloc_expand_load_replF_constant(iRegLdst dst, immF src, iRegLdst toc) %{ 3388 // Create new nodes. 3389 3390 // Make an operand with the bit pattern to load as float. 3391 immLOper *op_repl = immLOper((jlong)replicate_immF(op_src->constantF())); 3392 3393 loadConLNodesTuple loadConLNodes = 3394 loadConLNodesTuple_create(C, ra_, n_toc, op_repl, 3395 ra_->get_reg_second(this), ra_->get_reg_first(this)); 3396 3397 // Push new nodes. 3398 if (loadConLNodes._large_hi) nodes->push(loadConLNodes._large_hi); 3399 if (loadConLNodes._last) nodes->push(loadConLNodes._last); 3400 3401 assert(nodes->length() >= 1, "must have created at least 1 node"); 3402 assert(loadConLNodes._last->bottom_type()->isa_long(), "must be long"); 3403 %} 3404 3405 // This enc_class is needed so that scheduler gets proper 3406 // input mapping for latency computation. 3407 enc_class enc_poll(immI dst, iRegLdst poll) %{ 3408 // TODO: PPC port $archOpcode(ppc64Opcode_ld); 3409 // Fake operand dst needed for PPC scheduler. 3410 assert($dst$$constant == 0x0, "dst must be 0x0"); 3411 3412 MacroAssembler _masm(&cbuf); 3413 // Mark the code position where the load from the safepoint 3414 // polling page was emitted as relocInfo::poll_type. 3415 __ relocate(relocInfo::poll_type); 3416 __ load_from_polling_page($poll$$Register); 3417 %} 3418 3419 // A Java static call or a runtime call. 3420 // 3421 // Branch-and-link relative to a trampoline. 3422 // The trampoline loads the target address and does a long branch to there. 3423 // In case we call java, the trampoline branches to a interpreter_stub 3424 // which loads the inline cache and the real call target from the constant pool. 3425 // 3426 // This basically looks like this: 3427 // 3428 // >>>> consts -+ -+ 3429 // | |- offset1 3430 // [call target1] | <-+ 3431 // [IC cache] |- offset2 3432 // [call target2] <--+ 3433 // 3434 // <<<< consts 3435 // >>>> insts 3436 // 3437 // bl offset16 -+ -+ ??? // How many bits available? 3438 // | | 3439 // <<<< insts | | 3440 // >>>> stubs | | 3441 // | |- trampoline_stub_Reloc 3442 // trampoline stub: | <-+ 3443 // r2 = toc | 3444 // r2 = [r2 + offset1] | // Load call target1 from const section 3445 // mtctr r2 | 3446 // bctr |- static_stub_Reloc 3447 // comp_to_interp_stub: <---+ 3448 // r1 = toc 3449 // ICreg = [r1 + IC_offset] // Load IC from const section 3450 // r1 = [r1 + offset2] // Load call target2 from const section 3451 // mtctr r1 3452 // bctr 3453 // 3454 // <<<< stubs 3455 // 3456 // The call instruction in the code either 3457 // - Branches directly to a compiled method if the offset is encodable in instruction. 3458 // - Branches to the trampoline stub if the offset to the compiled method is not encodable. 3459 // - Branches to the compiled_to_interp stub if the target is interpreted. 3460 // 3461 // Further there are three relocations from the loads to the constants in 3462 // the constant section. 3463 // 3464 // Usage of r1 and r2 in the stubs allows to distinguish them. 3465 enc_class enc_java_static_call(method meth) %{ 3466 // TODO: PPC port $archOpcode(ppc64Opcode_bl); 3467 3468 MacroAssembler _masm(&cbuf); 3469 address entry_point = (address)$meth$$method; 3470 3471 if (!_method) { 3472 // A call to a runtime wrapper, e.g. new, new_typeArray_Java, uncommon_trap. 3473 emit_call_with_trampoline_stub(_masm, entry_point, relocInfo::runtime_call_type); 3474 } else { 3475 // Remember the offset not the address. 3476 const int start_offset = __ offset(); 3477 // The trampoline stub. 3478 if (!Compile::current()->in_scratch_emit_size()) { 3479 // No entry point given, use the current pc. 3480 // Make sure branch fits into 3481 if (entry_point == 0) entry_point = __ pc(); 3482 3483 // Put the entry point as a constant into the constant pool. 3484 const address entry_point_toc_addr = __ address_constant(entry_point, RelocationHolder::none); 3485 const int entry_point_toc_offset = __ offset_to_method_toc(entry_point_toc_addr); 3486 3487 // Emit the trampoline stub which will be related to the branch-and-link below. 3488 CallStubImpl::emit_trampoline_stub(_masm, entry_point_toc_offset, start_offset); 3489 __ relocate(_optimized_virtual ? 3490 relocInfo::opt_virtual_call_type : relocInfo::static_call_type); 3491 } 3492 3493 // The real call. 3494 // Note: At this point we do not have the address of the trampoline 3495 // stub, and the entry point might be too far away for bl, so __ pc() 3496 // serves as dummy and the bl will be patched later. 3497 cbuf.set_insts_mark(); 3498 __ bl(__ pc()); // Emits a relocation. 3499 3500 // The stub for call to interpreter. 3501 CompiledStaticCall::emit_to_interp_stub(cbuf); 3502 } 3503 %} 3504 3505 // Emit a method handle call. 3506 // 3507 // Method handle calls from compiled to compiled are going thru a 3508 // c2i -> i2c adapter, extending the frame for their arguments. The 3509 // caller however, returns directly to the compiled callee, that has 3510 // to cope with the extended frame. We restore the original frame by 3511 // loading the callers sp and adding the calculated framesize. 3512 enc_class enc_java_handle_call(method meth) %{ 3513 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 3514 3515 MacroAssembler _masm(&cbuf); 3516 address entry_point = (address)$meth$$method; 3517 3518 // Remember the offset not the address. 3519 const int start_offset = __ offset(); 3520 // The trampoline stub. 3521 if (!ra_->C->in_scratch_emit_size()) { 3522 // No entry point given, use the current pc. 3523 // Make sure branch fits into 3524 if (entry_point == 0) entry_point = __ pc(); 3525 3526 // Put the entry point as a constant into the constant pool. 3527 const address entry_point_toc_addr = __ address_constant(entry_point, RelocationHolder::none); 3528 const int entry_point_toc_offset = __ offset_to_method_toc(entry_point_toc_addr); 3529 3530 // Emit the trampoline stub which will be related to the branch-and-link below. 3531 CallStubImpl::emit_trampoline_stub(_masm, entry_point_toc_offset, start_offset); 3532 assert(_optimized_virtual, "methodHandle call should be a virtual call"); 3533 __ relocate(relocInfo::opt_virtual_call_type); 3534 } 3535 3536 // The real call. 3537 // Note: At this point we do not have the address of the trampoline 3538 // stub, and the entry point might be too far away for bl, so __ pc() 3539 // serves as dummy and the bl will be patched later. 3540 cbuf.set_insts_mark(); 3541 __ bl(__ pc()); // Emits a relocation. 3542 3543 assert(_method, "execute next statement conditionally"); 3544 // The stub for call to interpreter. 3545 CompiledStaticCall::emit_to_interp_stub(cbuf); 3546 3547 // Restore original sp. 3548 __ ld(R11_scratch1, 0, R1_SP); // Load caller sp. 3549 const long framesize = ra_->C->frame_slots() << LogBytesPerInt; 3550 unsigned int bytes = (unsigned int)framesize; 3551 long offset = Assembler::align_addr(bytes, frame::alignment_in_bytes); 3552 if (Assembler::is_simm(-offset, 16)) { 3553 __ addi(R1_SP, R11_scratch1, -offset); 3554 } else { 3555 __ load_const_optimized(R12_scratch2, -offset); 3556 __ add(R1_SP, R11_scratch1, R12_scratch2); 3557 } 3558 #ifdef ASSERT 3559 __ ld(R12_scratch2, 0, R1_SP); // Load from unextended_sp. 3560 __ cmpd(CCR0, R11_scratch1, R12_scratch2); 3561 __ asm_assert_eq("backlink changed", 0x8000); 3562 #endif 3563 // If fails should store backlink before unextending. 3564 3565 if (ra_->C->env()->failing()) { 3566 return; 3567 } 3568 %} 3569 3570 // Second node of expanded dynamic call - the call. 3571 enc_class enc_java_dynamic_call_sched(method meth) %{ 3572 // TODO: PPC port $archOpcode(ppc64Opcode_bl); 3573 3574 MacroAssembler _masm(&cbuf); 3575 3576 if (!ra_->C->in_scratch_emit_size()) { 3577 // Create a call trampoline stub for the given method. 3578 const address entry_point = !($meth$$method) ? 0 : (address)$meth$$method; 3579 const address entry_point_const = __ address_constant(entry_point, RelocationHolder::none); 3580 const int entry_point_const_toc_offset = __ offset_to_method_toc(entry_point_const); 3581 CallStubImpl::emit_trampoline_stub(_masm, entry_point_const_toc_offset, __ offset()); 3582 3583 if (ra_->C->env()->failing()) 3584 return; 3585 3586 // Build relocation at call site with ic position as data. 3587 assert((_load_ic_hi_node != NULL && _load_ic_node == NULL) || 3588 (_load_ic_hi_node == NULL && _load_ic_node != NULL), 3589 "must have one, but can't have both"); 3590 assert((_load_ic_hi_node != NULL && _load_ic_hi_node->_cbuf_insts_offset != -1) || 3591 (_load_ic_node != NULL && _load_ic_node->_cbuf_insts_offset != -1), 3592 "must contain instruction offset"); 3593 const int virtual_call_oop_addr_offset = _load_ic_hi_node != NULL 3594 ? _load_ic_hi_node->_cbuf_insts_offset 3595 : _load_ic_node->_cbuf_insts_offset; 3596 const address virtual_call_oop_addr = __ addr_at(virtual_call_oop_addr_offset); 3597 assert(MacroAssembler::is_load_const_from_method_toc_at(virtual_call_oop_addr), 3598 "should be load from TOC"); 3599 3600 __ relocate(virtual_call_Relocation::spec(virtual_call_oop_addr)); 3601 } 3602 3603 // At this point I do not have the address of the trampoline stub, 3604 // and the entry point might be too far away for bl. Pc() serves 3605 // as dummy and bl will be patched later. 3606 __ bl((address) __ pc()); 3607 %} 3608 3609 // postalloc expand emitter for virtual calls. 3610 enc_class postalloc_expand_java_dynamic_call_sched(method meth, iRegLdst toc) %{ 3611 3612 // Create the nodes for loading the IC from the TOC. 3613 loadConLNodesTuple loadConLNodes_IC = 3614 loadConLNodesTuple_create(C, ra_, n_toc, immLOper((jlong)Universe::non_oop_word()), 3615 OptoReg::Name(R19_H_num), OptoReg::Name(R19_num)); 3616 3617 // Create the call node. 3618 CallDynamicJavaDirectSchedNode *call = CallDynamicJavaDirectSchedNode(); 3619 call->_method_handle_invoke = _method_handle_invoke; 3620 call->_vtable_index = _vtable_index; 3621 call->_method = _method; 3622 call->_bci = _bci; 3623 call->_optimized_virtual = _optimized_virtual; 3624 call->_tf = _tf; 3625 call->_entry_point = _entry_point; 3626 call->_cnt = _cnt; 3627 call->_argsize = _argsize; 3628 call->_oop_map = _oop_map; 3629 call->_jvms = _jvms; 3630 call->_jvmadj = _jvmadj; 3631 call->_in_rms = _in_rms; 3632 call->_nesting = _nesting; 3633 3634 // New call needs all inputs of old call. 3635 // Req... 3636 for (uint i = 0; i < req(); ++i) { 3637 // The expanded node does not need toc any more. 3638 // Add the inline cache constant here instead. This expresses the 3639 // register of the inline cache must be live at the call. 3640 // Else we would have to adapt JVMState by -1. 3641 if (i == mach_constant_base_node_input()) { 3642 call->add_req(loadConLNodes_IC._last); 3643 } else { 3644 call->add_req(in(i)); 3645 } 3646 } 3647 // ...as well as prec 3648 for (uint i = req(); i < len(); ++i) { 3649 call->add_prec(in(i)); 3650 } 3651 3652 // Remember nodes loading the inline cache into r19. 3653 call->_load_ic_hi_node = loadConLNodes_IC._large_hi; 3654 call->_load_ic_node = loadConLNodes_IC._small; 3655 3656 // Operands for new nodes. 3657 call->_opnds[0] = _opnds[0]; 3658 call->_opnds[1] = _opnds[1]; 3659 3660 // Only the inline cache is associated with a register. 3661 assert(Matcher::inline_cache_reg() == OptoReg::Name(R19_num), "ic reg should be R19"); 3662 3663 // Push new nodes. 3664 if (loadConLNodes_IC._large_hi) nodes->push(loadConLNodes_IC._large_hi); 3665 if (loadConLNodes_IC._last) nodes->push(loadConLNodes_IC._last); 3666 nodes->push(call); 3667 %} 3668 3669 // Compound version of call dynamic 3670 // Toc is only passed so that it can be used in ins_encode statement. 3671 // In the code we have to use $constanttablebase. 3672 enc_class enc_java_dynamic_call(method meth, iRegLdst toc) %{ 3673 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 3674 MacroAssembler _masm(&cbuf); 3675 int start_offset = __ offset(); 3676 3677 Register Rtoc = (ra_) ? $constanttablebase : R2_TOC; 3678 #if 0 3679 int vtable_index = this->_vtable_index; 3680 if (_vtable_index < 0) { 3681 // Must be invalid_vtable_index, not nonvirtual_vtable_index. 3682 assert(_vtable_index == Method::invalid_vtable_index, "correct sentinel value"); 3683 Register ic_reg = as_Register(Matcher::inline_cache_reg_encode()); 3684 3685 // Virtual call relocation will point to ic load. 3686 address virtual_call_meta_addr = __ pc(); 3687 // Load a clear inline cache. 3688 AddressLiteral empty_ic((address) Universe::non_oop_word()); 3689 __ load_const_from_method_toc(ic_reg, empty_ic, Rtoc); 3690 // CALL to fixup routine. Fixup routine uses ScopeDesc info 3691 // to determine who we intended to call. 3692 __ relocate(virtual_call_Relocation::spec(virtual_call_meta_addr)); 3693 emit_call_with_trampoline_stub(_masm, (address)$meth$$method, relocInfo::none); 3694 assert(((MachCallDynamicJavaNode*)this)->ret_addr_offset() == __ offset() - start_offset, 3695 "Fix constant in ret_addr_offset()"); 3696 } else { 3697 assert(!UseInlineCaches, "expect vtable calls only if not using ICs"); 3698 // Go thru the vtable. Get receiver klass. Receiver already 3699 // checked for non-null. If we'll go thru a C2I adapter, the 3700 // interpreter expects method in R19_method. 3701 3702 __ load_klass(R11_scratch1, R3); 3703 3704 int entry_offset = InstanceKlass::vtable_start_offset() + _vtable_index * vtableEntry::size(); 3705 int v_off = entry_offset * wordSize + vtableEntry::method_offset_in_bytes(); 3706 __ li(R19_method, v_off); 3707 __ ldx(R19_method/*method oop*/, R19_method/*method offset*/, R11_scratch1/*class*/); 3708 // NOTE: for vtable dispatches, the vtable entry will never be 3709 // null. However it may very well end up in handle_wrong_method 3710 // if the method is abstract for the particular class. 3711 __ ld(R11_scratch1, in_bytes(Method::from_compiled_offset()), R19_method); 3712 // Call target. Either compiled code or C2I adapter. 3713 __ mtctr(R11_scratch1); 3714 __ bctrl(); 3715 if (((MachCallDynamicJavaNode*)this)->ret_addr_offset() != __ offset() - start_offset) { 3716 tty->print(" %d, %d\n", ((MachCallDynamicJavaNode*)this)->ret_addr_offset(),__ offset() - start_offset); 3717 } 3718 assert(((MachCallDynamicJavaNode*)this)->ret_addr_offset() == __ offset() - start_offset, 3719 "Fix constant in ret_addr_offset()"); 3720 } 3721 #endif 3722 Unimplemented(); // ret_addr_offset not yet fixed. Depends on compressed oops (load klass!). 3723 %} 3724 3725 // a runtime call 3726 enc_class enc_java_to_runtime_call (method meth) %{ 3727 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 3728 3729 MacroAssembler _masm(&cbuf); 3730 const address start_pc = __ pc(); 3731 3732 #if defined(ABI_ELFv2) 3733 address entry= !($meth$$method) ? NULL : (address)$meth$$method; 3734 __ call_c(entry, relocInfo::runtime_call_type); 3735 #else 3736 // The function we're going to call. 3737 FunctionDescriptor fdtemp; 3738 const FunctionDescriptor* fd = !($meth$$method) ? &fdtemp : (FunctionDescriptor*)$meth$$method; 3739 3740 Register Rtoc = R12_scratch2; 3741 // Calculate the method's TOC. 3742 __ calculate_address_from_global_toc(Rtoc, __ method_toc()); 3743 // Put entry, env, toc into the constant pool, this needs up to 3 constant 3744 // pool entries; call_c_using_toc will optimize the call. 3745 __ call_c_using_toc(fd, relocInfo::runtime_call_type, Rtoc); 3746 #endif 3747 3748 // Check the ret_addr_offset. 3749 assert(((MachCallRuntimeNode*)this)->ret_addr_offset() == __ last_calls_return_pc() - start_pc, 3750 "Fix constant in ret_addr_offset()"); 3751 %} 3752 3753 // Move to ctr for leaf call. 3754 // This enc_class is needed so that scheduler gets proper 3755 // input mapping for latency computation. 3756 enc_class enc_leaf_call_mtctr(iRegLsrc src) %{ 3757 // TODO: PPC port $archOpcode(ppc64Opcode_mtctr); 3758 MacroAssembler _masm(&cbuf); 3759 __ mtctr($src$$Register); 3760 %} 3761 3762 // Postalloc expand emitter for runtime leaf calls. 3763 enc_class postalloc_expand_java_to_runtime_call(method meth, iRegLdst toc) %{ 3764 loadConLNodesTuple loadConLNodes_Entry; 3765 #if defined(ABI_ELFv2) 3766 jlong entry_address = (jlong) this->entry_point(); 3767 assert(entry_address, "need address here"); 3768 loadConLNodes_Entry = loadConLNodesTuple_create(C, ra_, n_toc, immLOper(entry_address), 3769 OptoReg::Name(R12_H_num), OptoReg::Name(R12_num)); 3770 #else 3771 // Get the struct that describes the function we are about to call. 3772 FunctionDescriptor* fd = (FunctionDescriptor*) this->entry_point(); 3773 assert(fd, "need fd here"); 3774 jlong entry_address = (jlong) fd->entry(); 3775 // new nodes 3776 loadConLNodesTuple loadConLNodes_Env; 3777 loadConLNodesTuple loadConLNodes_Toc; 3778 3779 // Create nodes and operands for loading the entry point. 3780 loadConLNodes_Entry = loadConLNodesTuple_create(C, ra_, n_toc, immLOper(entry_address), 3781 OptoReg::Name(R12_H_num), OptoReg::Name(R12_num)); 3782 3783 3784 // Create nodes and operands for loading the env pointer. 3785 if (fd->env() != NULL) { 3786 loadConLNodes_Env = loadConLNodesTuple_create(C, ra_, n_toc, immLOper((jlong) fd->env()), 3787 OptoReg::Name(R11_H_num), OptoReg::Name(R11_num)); 3788 } else { 3789 loadConLNodes_Env._large_hi = NULL; 3790 loadConLNodes_Env._large_lo = NULL; 3791 loadConLNodes_Env._small = NULL; 3792 loadConLNodes_Env._last = loadConL16Node(); 3793 loadConLNodes_Env._last->_opnds[0] = iRegLdstOper(); 3794 loadConLNodes_Env._last->_opnds[1] = immL16Oper(0); 3795 ra_->set_pair(loadConLNodes_Env._last->_idx, OptoReg::Name(R11_H_num), OptoReg::Name(R11_num)); 3796 } 3797 3798 // Create nodes and operands for loading the Toc point. 3799 loadConLNodes_Toc = loadConLNodesTuple_create(C, ra_, n_toc, immLOper((jlong) fd->toc()), 3800 OptoReg::Name(R2_H_num), OptoReg::Name(R2_num)); 3801 #endif // ABI_ELFv2 3802 // mtctr node 3803 MachNode *mtctr = CallLeafDirect_mtctrNode(); 3804 3805 assert(loadConLNodes_Entry._last != NULL, "entry must exist"); 3806 mtctr->add_req(0, loadConLNodes_Entry._last); 3807 3808 mtctr->_opnds[0] = iRegLdstOper(); 3809 mtctr->_opnds[1] = iRegLdstOper(); 3810 3811 // call node 3812 MachCallLeafNode *call = CallLeafDirectNode(); 3813 3814 call->_opnds[0] = _opnds[0]; 3815 call->_opnds[1] = methodOper((intptr_t) entry_address); // May get set later. 3816 3817 // Make the new call node look like the old one. 3818 call->_name = _name; 3819 call->_tf = _tf; 3820 call->_entry_point = _entry_point; 3821 call->_cnt = _cnt; 3822 call->_argsize = _argsize; 3823 call->_oop_map = _oop_map; 3824 guarantee(!_jvms, "You must clone the jvms and adapt the offsets by fix_jvms()."); 3825 call->_jvms = NULL; 3826 call->_jvmadj = _jvmadj; 3827 call->_in_rms = _in_rms; 3828 call->_nesting = _nesting; 3829 3830 3831 // New call needs all inputs of old call. 3832 // Req... 3833 for (uint i = 0; i < req(); ++i) { 3834 if (i != mach_constant_base_node_input()) { 3835 call->add_req(in(i)); 3836 } 3837 } 3838 3839 // These must be reqired edges, as the registers are live up to 3840 // the call. Else the constants are handled as kills. 3841 call->add_req(mtctr); 3842 #if !defined(ABI_ELFv2) 3843 call->add_req(loadConLNodes_Env._last); 3844 call->add_req(loadConLNodes_Toc._last); 3845 #endif 3846 3847 // ...as well as prec 3848 for (uint i = req(); i < len(); ++i) { 3849 call->add_prec(in(i)); 3850 } 3851 3852 // registers 3853 ra_->set1(mtctr->_idx, OptoReg::Name(SR_CTR_num)); 3854 3855 // Insert the new nodes. 3856 if (loadConLNodes_Entry._large_hi) nodes->push(loadConLNodes_Entry._large_hi); 3857 if (loadConLNodes_Entry._last) nodes->push(loadConLNodes_Entry._last); 3858 #if !defined(ABI_ELFv2) 3859 if (loadConLNodes_Env._large_hi) nodes->push(loadConLNodes_Env._large_hi); 3860 if (loadConLNodes_Env._last) nodes->push(loadConLNodes_Env._last); 3861 if (loadConLNodes_Toc._large_hi) nodes->push(loadConLNodes_Toc._large_hi); 3862 if (loadConLNodes_Toc._last) nodes->push(loadConLNodes_Toc._last); 3863 #endif 3864 nodes->push(mtctr); 3865 nodes->push(call); 3866 %} 3867 %} 3868 3869 //----------FRAME-------------------------------------------------------------- 3870 // Definition of frame structure and management information. 3871 3872 frame %{ 3873 // What direction does stack grow in (assumed to be same for native & Java). 3874 stack_direction(TOWARDS_LOW); 3875 3876 // These two registers define part of the calling convention between 3877 // compiled code and the interpreter. 3878 3879 // Inline Cache Register or method for I2C. 3880 inline_cache_reg(R19); // R19_method 3881 3882 // Method Oop Register when calling interpreter. 3883 interpreter_method_oop_reg(R19); // R19_method 3884 3885 // Optional: name the operand used by cisc-spilling to access 3886 // [stack_pointer + offset]. 3887 cisc_spilling_operand_name(indOffset); 3888 3889 // Number of stack slots consumed by a Monitor enter. 3890 sync_stack_slots((frame::jit_monitor_size / VMRegImpl::stack_slot_size)); 3891 3892 // Compiled code's Frame Pointer. 3893 frame_pointer(R1); // R1_SP 3894 3895 // Interpreter stores its frame pointer in a register which is 3896 // stored to the stack by I2CAdaptors. I2CAdaptors convert from 3897 // interpreted java to compiled java. 3898 // 3899 // R14_state holds pointer to caller's cInterpreter. 3900 interpreter_frame_pointer(R14); // R14_state 3901 3902 stack_alignment(frame::alignment_in_bytes); 3903 3904 in_preserve_stack_slots((frame::jit_in_preserve_size / VMRegImpl::stack_slot_size)); 3905 3906 // Number of outgoing stack slots killed above the 3907 // out_preserve_stack_slots for calls to C. Supports the var-args 3908 // backing area for register parms. 3909 // 3910 varargs_C_out_slots_killed(((frame::abi_reg_args_size - frame::jit_out_preserve_size) / VMRegImpl::stack_slot_size)); 3911 3912 // The after-PROLOG location of the return address. Location of 3913 // return address specifies a type (REG or STACK) and a number 3914 // representing the register number (i.e. - use a register name) or 3915 // stack slot. 3916 // 3917 // A: Link register is stored in stack slot ... 3918 // M: ... but it's in the caller's frame according to PPC-64 ABI. 3919 // J: Therefore, we make sure that the link register is also in R11_scratch1 3920 // at the end of the prolog. 3921 // B: We use R20, now. 3922 //return_addr(REG R20); 3923 3924 // G: After reading the comments made by all the luminaries on their 3925 // failure to tell the compiler where the return address really is, 3926 // I hardly dare to try myself. However, I'm convinced it's in slot 3927 // 4 what apparently works and saves us some spills. 3928 return_addr(STACK 4); 3929 3930 // This is the body of the function 3931 // 3932 // void Matcher::calling_convention(OptoRegPair* sig, // array of ideal regs 3933 // uint length, // length of array 3934 // bool is_outgoing) 3935 // 3936 // The `sig' array is to be updated. sig[j] represents the location 3937 // of the j-th argument, either a register or a stack slot. 3938 3939 // Comment taken from i486.ad: 3940 // Body of function which returns an integer array locating 3941 // arguments either in registers or in stack slots. Passed an array 3942 // of ideal registers called "sig" and a "length" count. Stack-slot 3943 // offsets are based on outgoing arguments, i.e. a CALLER setting up 3944 // arguments for a CALLEE. Incoming stack arguments are 3945 // automatically biased by the preserve_stack_slots field above. 3946 calling_convention %{ 3947 // No difference between ingoing/outgoing. Just pass false. 3948 SharedRuntime::java_calling_convention(sig_bt, regs, length, false); 3949 %} 3950 3951 // Comment taken from i486.ad: 3952 // Body of function which returns an integer array locating 3953 // arguments either in registers or in stack slots. Passed an array 3954 // of ideal registers called "sig" and a "length" count. Stack-slot 3955 // offsets are based on outgoing arguments, i.e. a CALLER setting up 3956 // arguments for a CALLEE. Incoming stack arguments are 3957 // automatically biased by the preserve_stack_slots field above. 3958 c_calling_convention %{ 3959 // This is obviously always outgoing. 3960 // C argument in register AND stack slot. 3961 (void) SharedRuntime::c_calling_convention(sig_bt, regs, /*regs2=*/NULL, length); 3962 %} 3963 3964 // Location of native (C/C++) and interpreter return values. This 3965 // is specified to be the same as Java. In the 32-bit VM, long 3966 // values are actually returned from native calls in O0:O1 and 3967 // returned to the interpreter in I0:I1. The copying to and from 3968 // the register pairs is done by the appropriate call and epilog 3969 // opcodes. This simplifies the register allocator. 3970 c_return_value %{ 3971 assert((ideal_reg >= Op_RegI && ideal_reg <= Op_RegL) || 3972 (ideal_reg == Op_RegN && Universe::narrow_oop_base() == NULL && Universe::narrow_oop_shift() == 0), 3973 "only return normal values"); 3974 // enum names from opcodes.hpp: Op_Node Op_Set Op_RegN Op_RegI Op_RegP Op_RegF Op_RegD Op_RegL 3975 static int typeToRegLo[Op_RegL+1] = { 0, 0, R3_num, R3_num, R3_num, F1_num, F1_num, R3_num }; 3976 static int typeToRegHi[Op_RegL+1] = { 0, 0, OptoReg::Bad, R3_H_num, R3_H_num, OptoReg::Bad, F1_H_num, R3_H_num }; 3977 return OptoRegPair(typeToRegHi[ideal_reg], typeToRegLo[ideal_reg]); 3978 %} 3979 3980 // Location of compiled Java return values. Same as C 3981 return_value %{ 3982 assert((ideal_reg >= Op_RegI && ideal_reg <= Op_RegL) || 3983 (ideal_reg == Op_RegN && Universe::narrow_oop_base() == NULL && Universe::narrow_oop_shift() == 0), 3984 "only return normal values"); 3985 // enum names from opcodes.hpp: Op_Node Op_Set Op_RegN Op_RegI Op_RegP Op_RegF Op_RegD Op_RegL 3986 static int typeToRegLo[Op_RegL+1] = { 0, 0, R3_num, R3_num, R3_num, F1_num, F1_num, R3_num }; 3987 static int typeToRegHi[Op_RegL+1] = { 0, 0, OptoReg::Bad, R3_H_num, R3_H_num, OptoReg::Bad, F1_H_num, R3_H_num }; 3988 return OptoRegPair(typeToRegHi[ideal_reg], typeToRegLo[ideal_reg]); 3989 %} 3990 %} 3991 3992 3993 //----------ATTRIBUTES--------------------------------------------------------- 3994 3995 //----------Operand Attributes------------------------------------------------- 3996 op_attrib op_cost(1); // Required cost attribute. 3997 3998 //----------Instruction Attributes--------------------------------------------- 3999 4000 // Cost attribute. required. 4001 ins_attrib ins_cost(DEFAULT_COST); 4002 4003 // Is this instruction a non-matching short branch variant of some 4004 // long branch? Not required. 4005 ins_attrib ins_short_branch(0); 4006 4007 ins_attrib ins_is_TrapBasedCheckNode(true); 4008 4009 // Number of constants. 4010 // This instruction uses the given number of constants 4011 // (optional attribute). 4012 // This is needed to determine in time whether the constant pool will 4013 // exceed 4000 entries. Before postalloc_expand the overall number of constants 4014 // is determined. It's also used to compute the constant pool size 4015 // in Output(). 4016 ins_attrib ins_num_consts(0); 4017 4018 // Required alignment attribute (must be a power of 2) specifies the 4019 // alignment that some part of the instruction (not necessarily the 4020 // start) requires. If > 1, a compute_padding() function must be 4021 // provided for the instruction. 4022 ins_attrib ins_alignment(1); 4023 4024 // Enforce/prohibit rematerializations. 4025 // - If an instruction is attributed with 'ins_cannot_rematerialize(true)' 4026 // then rematerialization of that instruction is prohibited and the 4027 // instruction's value will be spilled if necessary. 4028 // Causes that MachNode::rematerialize() returns false. 4029 // - If an instruction is attributed with 'ins_should_rematerialize(true)' 4030 // then rematerialization should be enforced and a copy of the instruction 4031 // should be inserted if possible; rematerialization is not guaranteed. 4032 // Note: this may result in rematerializations in front of every use. 4033 // Causes that MachNode::rematerialize() can return true. 4034 // (optional attribute) 4035 ins_attrib ins_cannot_rematerialize(false); 4036 ins_attrib ins_should_rematerialize(false); 4037 4038 // Instruction has variable size depending on alignment. 4039 ins_attrib ins_variable_size_depending_on_alignment(false); 4040 4041 // Instruction is a nop. 4042 ins_attrib ins_is_nop(false); 4043 4044 // Instruction is mapped to a MachIfFastLock node (instead of MachFastLock). 4045 ins_attrib ins_use_mach_if_fast_lock_node(false); 4046 4047 // Field for the toc offset of a constant. 4048 // 4049 // This is needed if the toc offset is not encodable as an immediate in 4050 // the PPC load instruction. If so, the upper (hi) bits of the offset are 4051 // added to the toc, and from this a load with immediate is performed. 4052 // With postalloc expand, we get two nodes that require the same offset 4053 // but which don't know about each other. The offset is only known 4054 // when the constant is added to the constant pool during emitting. 4055 // It is generated in the 'hi'-node adding the upper bits, and saved 4056 // in this node. The 'lo'-node has a link to the 'hi'-node and reads 4057 // the offset from there when it gets encoded. 4058 ins_attrib ins_field_const_toc_offset(0); 4059 ins_attrib ins_field_const_toc_offset_hi_node(0); 4060 4061 // A field that can hold the instructions offset in the code buffer. 4062 // Set in the nodes emitter. 4063 ins_attrib ins_field_cbuf_insts_offset(-1); 4064 4065 // Fields for referencing a call's load-IC-node. 4066 // If the toc offset can not be encoded as an immediate in a load, we 4067 // use two nodes. 4068 ins_attrib ins_field_load_ic_hi_node(0); 4069 ins_attrib ins_field_load_ic_node(0); 4070 4071 //----------OPERANDS----------------------------------------------------------- 4072 // Operand definitions must precede instruction definitions for correct 4073 // parsing in the ADLC because operands constitute user defined types 4074 // which are used in instruction definitions. 4075 // 4076 // Formats are generated automatically for constants and base registers. 4077 4078 //----------Simple Operands---------------------------------------------------- 4079 // Immediate Operands 4080 4081 // Integer Immediate: 32-bit 4082 operand immI() %{ 4083 match(ConI); 4084 op_cost(40); 4085 format %{ %} 4086 interface(CONST_INTER); 4087 %} 4088 4089 operand immI8() %{ 4090 predicate(Assembler::is_simm(n->get_int(), 8)); 4091 op_cost(0); 4092 match(ConI); 4093 format %{ %} 4094 interface(CONST_INTER); 4095 %} 4096 4097 // Integer Immediate: 16-bit 4098 operand immI16() %{ 4099 predicate(Assembler::is_simm(n->get_int(), 16)); 4100 op_cost(0); 4101 match(ConI); 4102 format %{ %} 4103 interface(CONST_INTER); 4104 %} 4105 4106 // Integer Immediate: 32-bit, where lowest 16 bits are 0x0000. 4107 operand immIhi16() %{ 4108 predicate(((n->get_int() & 0xffff0000) != 0) && ((n->get_int() & 0xffff) == 0)); 4109 match(ConI); 4110 op_cost(0); 4111 format %{ %} 4112 interface(CONST_INTER); 4113 %} 4114 4115 operand immInegpow2() %{ 4116 predicate(is_power_of_2_long((jlong) (julong) (juint) (-(n->get_int())))); 4117 match(ConI); 4118 op_cost(0); 4119 format %{ %} 4120 interface(CONST_INTER); 4121 %} 4122 4123 operand immIpow2minus1() %{ 4124 predicate(is_power_of_2_long((((jlong) (n->get_int()))+1))); 4125 match(ConI); 4126 op_cost(0); 4127 format %{ %} 4128 interface(CONST_INTER); 4129 %} 4130 4131 operand immIpowerOf2() %{ 4132 predicate(is_power_of_2_long((((jlong) (julong) (juint) (n->get_int()))))); 4133 match(ConI); 4134 op_cost(0); 4135 format %{ %} 4136 interface(CONST_INTER); 4137 %} 4138 4139 // Unsigned Integer Immediate: the values 0-31 4140 operand uimmI5() %{ 4141 predicate(Assembler::is_uimm(n->get_int(), 5)); 4142 match(ConI); 4143 op_cost(0); 4144 format %{ %} 4145 interface(CONST_INTER); 4146 %} 4147 4148 // Unsigned Integer Immediate: 6-bit 4149 operand uimmI6() %{ 4150 predicate(Assembler::is_uimm(n->get_int(), 6)); 4151 match(ConI); 4152 op_cost(0); 4153 format %{ %} 4154 interface(CONST_INTER); 4155 %} 4156 4157 // Unsigned Integer Immediate: 6-bit int, greater than 32 4158 operand uimmI6_ge32() %{ 4159 predicate(Assembler::is_uimm(n->get_int(), 6) && n->get_int() >= 32); 4160 match(ConI); 4161 op_cost(0); 4162 format %{ %} 4163 interface(CONST_INTER); 4164 %} 4165 4166 // Unsigned Integer Immediate: 15-bit 4167 operand uimmI15() %{ 4168 predicate(Assembler::is_uimm(n->get_int(), 15)); 4169 match(ConI); 4170 op_cost(0); 4171 format %{ %} 4172 interface(CONST_INTER); 4173 %} 4174 4175 // Unsigned Integer Immediate: 16-bit 4176 operand uimmI16() %{ 4177 predicate(Assembler::is_uimm(n->get_int(), 16)); 4178 match(ConI); 4179 op_cost(0); 4180 format %{ %} 4181 interface(CONST_INTER); 4182 %} 4183 4184 // constant 'int 0'. 4185 operand immI_0() %{ 4186 predicate(n->get_int() == 0); 4187 match(ConI); 4188 op_cost(0); 4189 format %{ %} 4190 interface(CONST_INTER); 4191 %} 4192 4193 // constant 'int 1'. 4194 operand immI_1() %{ 4195 predicate(n->get_int() == 1); 4196 match(ConI); 4197 op_cost(0); 4198 format %{ %} 4199 interface(CONST_INTER); 4200 %} 4201 4202 // constant 'int -1'. 4203 operand immI_minus1() %{ 4204 predicate(n->get_int() == -1); 4205 match(ConI); 4206 op_cost(0); 4207 format %{ %} 4208 interface(CONST_INTER); 4209 %} 4210 4211 // int value 16. 4212 operand immI_16() %{ 4213 predicate(n->get_int() == 16); 4214 match(ConI); 4215 op_cost(0); 4216 format %{ %} 4217 interface(CONST_INTER); 4218 %} 4219 4220 // int value 24. 4221 operand immI_24() %{ 4222 predicate(n->get_int() == 24); 4223 match(ConI); 4224 op_cost(0); 4225 format %{ %} 4226 interface(CONST_INTER); 4227 %} 4228 4229 // Compressed oops constants 4230 // Pointer Immediate 4231 operand immN() %{ 4232 match(ConN); 4233 4234 op_cost(10); 4235 format %{ %} 4236 interface(CONST_INTER); 4237 %} 4238 4239 // NULL Pointer Immediate 4240 operand immN_0() %{ 4241 predicate(n->get_narrowcon() == 0); 4242 match(ConN); 4243 4244 op_cost(0); 4245 format %{ %} 4246 interface(CONST_INTER); 4247 %} 4248 4249 // Compressed klass constants 4250 operand immNKlass() %{ 4251 match(ConNKlass); 4252 4253 op_cost(0); 4254 format %{ %} 4255 interface(CONST_INTER); 4256 %} 4257 4258 // This operand can be used to avoid matching of an instruct 4259 // with chain rule. 4260 operand immNKlass_NM() %{ 4261 match(ConNKlass); 4262 predicate(false); 4263 op_cost(0); 4264 format %{ %} 4265 interface(CONST_INTER); 4266 %} 4267 4268 // Pointer Immediate: 64-bit 4269 operand immP() %{ 4270 match(ConP); 4271 op_cost(0); 4272 format %{ %} 4273 interface(CONST_INTER); 4274 %} 4275 4276 // Operand to avoid match of loadConP. 4277 // This operand can be used to avoid matching of an instruct 4278 // with chain rule. 4279 operand immP_NM() %{ 4280 match(ConP); 4281 predicate(false); 4282 op_cost(0); 4283 format %{ %} 4284 interface(CONST_INTER); 4285 %} 4286 4287 // costant 'pointer 0'. 4288 operand immP_0() %{ 4289 predicate(n->get_ptr() == 0); 4290 match(ConP); 4291 op_cost(0); 4292 format %{ %} 4293 interface(CONST_INTER); 4294 %} 4295 4296 // pointer 0x0 or 0x1 4297 operand immP_0or1() %{ 4298 predicate((n->get_ptr() == 0) || (n->get_ptr() == 1)); 4299 match(ConP); 4300 op_cost(0); 4301 format %{ %} 4302 interface(CONST_INTER); 4303 %} 4304 4305 operand immL() %{ 4306 match(ConL); 4307 op_cost(40); 4308 format %{ %} 4309 interface(CONST_INTER); 4310 %} 4311 4312 // Long Immediate: 16-bit 4313 operand immL16() %{ 4314 predicate(Assembler::is_simm(n->get_long(), 16)); 4315 match(ConL); 4316 op_cost(0); 4317 format %{ %} 4318 interface(CONST_INTER); 4319 %} 4320 4321 // Long Immediate: 16-bit, 4-aligned 4322 operand immL16Alg4() %{ 4323 predicate(Assembler::is_simm(n->get_long(), 16) && ((n->get_long() & 0x3) == 0)); 4324 match(ConL); 4325 op_cost(0); 4326 format %{ %} 4327 interface(CONST_INTER); 4328 %} 4329 4330 // Long Immediate: 32-bit, where lowest 16 bits are 0x0000. 4331 operand immL32hi16() %{ 4332 predicate(Assembler::is_simm(n->get_long(), 32) && ((n->get_long() & 0xffffL) == 0L)); 4333 match(ConL); 4334 op_cost(0); 4335 format %{ %} 4336 interface(CONST_INTER); 4337 %} 4338 4339 // Long Immediate: 32-bit 4340 operand immL32() %{ 4341 predicate(Assembler::is_simm(n->get_long(), 32)); 4342 match(ConL); 4343 op_cost(0); 4344 format %{ %} 4345 interface(CONST_INTER); 4346 %} 4347 4348 // Long Immediate: 64-bit, where highest 16 bits are not 0x0000. 4349 operand immLhighest16() %{ 4350 predicate((n->get_long() & 0xffff000000000000L) != 0L && (n->get_long() & 0x0000ffffffffffffL) == 0L); 4351 match(ConL); 4352 op_cost(0); 4353 format %{ %} 4354 interface(CONST_INTER); 4355 %} 4356 4357 operand immLnegpow2() %{ 4358 predicate(is_power_of_2_long((jlong)-(n->get_long()))); 4359 match(ConL); 4360 op_cost(0); 4361 format %{ %} 4362 interface(CONST_INTER); 4363 %} 4364 4365 operand immLpow2minus1() %{ 4366 predicate(is_power_of_2_long((((jlong) (n->get_long()))+1)) && 4367 (n->get_long() != (jlong)0xffffffffffffffffL)); 4368 match(ConL); 4369 op_cost(0); 4370 format %{ %} 4371 interface(CONST_INTER); 4372 %} 4373 4374 // constant 'long 0'. 4375 operand immL_0() %{ 4376 predicate(n->get_long() == 0L); 4377 match(ConL); 4378 op_cost(0); 4379 format %{ %} 4380 interface(CONST_INTER); 4381 %} 4382 4383 // constat ' long -1'. 4384 operand immL_minus1() %{ 4385 predicate(n->get_long() == -1L); 4386 match(ConL); 4387 op_cost(0); 4388 format %{ %} 4389 interface(CONST_INTER); 4390 %} 4391 4392 // Long Immediate: low 32-bit mask 4393 operand immL_32bits() %{ 4394 predicate(n->get_long() == 0xFFFFFFFFL); 4395 match(ConL); 4396 op_cost(0); 4397 format %{ %} 4398 interface(CONST_INTER); 4399 %} 4400 4401 // Unsigned Long Immediate: 16-bit 4402 operand uimmL16() %{ 4403 predicate(Assembler::is_uimm(n->get_long(), 16)); 4404 match(ConL); 4405 op_cost(0); 4406 format %{ %} 4407 interface(CONST_INTER); 4408 %} 4409 4410 // Float Immediate 4411 operand immF() %{ 4412 match(ConF); 4413 op_cost(40); 4414 format %{ %} 4415 interface(CONST_INTER); 4416 %} 4417 4418 // constant 'float +0.0'. 4419 operand immF_0() %{ 4420 predicate((n->getf() == 0) && 4421 (fpclassify(n->getf()) == FP_ZERO) && (signbit(n->getf()) == 0)); 4422 match(ConF); 4423 op_cost(0); 4424 format %{ %} 4425 interface(CONST_INTER); 4426 %} 4427 4428 // Double Immediate 4429 operand immD() %{ 4430 match(ConD); 4431 op_cost(40); 4432 format %{ %} 4433 interface(CONST_INTER); 4434 %} 4435 4436 // Integer Register Operands 4437 // Integer Destination Register 4438 // See definition of reg_class bits32_reg_rw. 4439 operand iRegIdst() %{ 4440 constraint(ALLOC_IN_RC(bits32_reg_rw)); 4441 match(RegI); 4442 match(rscratch1RegI); 4443 match(rscratch2RegI); 4444 match(rarg1RegI); 4445 match(rarg2RegI); 4446 match(rarg3RegI); 4447 match(rarg4RegI); 4448 format %{ %} 4449 interface(REG_INTER); 4450 %} 4451 4452 // Integer Source Register 4453 // See definition of reg_class bits32_reg_ro. 4454 operand iRegIsrc() %{ 4455 constraint(ALLOC_IN_RC(bits32_reg_ro)); 4456 match(RegI); 4457 match(rscratch1RegI); 4458 match(rscratch2RegI); 4459 match(rarg1RegI); 4460 match(rarg2RegI); 4461 match(rarg3RegI); 4462 match(rarg4RegI); 4463 format %{ %} 4464 interface(REG_INTER); 4465 %} 4466 4467 operand rscratch1RegI() %{ 4468 constraint(ALLOC_IN_RC(rscratch1_bits32_reg)); 4469 match(iRegIdst); 4470 format %{ %} 4471 interface(REG_INTER); 4472 %} 4473 4474 operand rscratch2RegI() %{ 4475 constraint(ALLOC_IN_RC(rscratch2_bits32_reg)); 4476 match(iRegIdst); 4477 format %{ %} 4478 interface(REG_INTER); 4479 %} 4480 4481 operand rarg1RegI() %{ 4482 constraint(ALLOC_IN_RC(rarg1_bits32_reg)); 4483 match(iRegIdst); 4484 format %{ %} 4485 interface(REG_INTER); 4486 %} 4487 4488 operand rarg2RegI() %{ 4489 constraint(ALLOC_IN_RC(rarg2_bits32_reg)); 4490 match(iRegIdst); 4491 format %{ %} 4492 interface(REG_INTER); 4493 %} 4494 4495 operand rarg3RegI() %{ 4496 constraint(ALLOC_IN_RC(rarg3_bits32_reg)); 4497 match(iRegIdst); 4498 format %{ %} 4499 interface(REG_INTER); 4500 %} 4501 4502 operand rarg4RegI() %{ 4503 constraint(ALLOC_IN_RC(rarg4_bits32_reg)); 4504 match(iRegIdst); 4505 format %{ %} 4506 interface(REG_INTER); 4507 %} 4508 4509 operand rarg1RegL() %{ 4510 constraint(ALLOC_IN_RC(rarg1_bits64_reg)); 4511 match(iRegLdst); 4512 format %{ %} 4513 interface(REG_INTER); 4514 %} 4515 4516 operand rarg2RegL() %{ 4517 constraint(ALLOC_IN_RC(rarg2_bits64_reg)); 4518 match(iRegLdst); 4519 format %{ %} 4520 interface(REG_INTER); 4521 %} 4522 4523 operand rarg3RegL() %{ 4524 constraint(ALLOC_IN_RC(rarg3_bits64_reg)); 4525 match(iRegLdst); 4526 format %{ %} 4527 interface(REG_INTER); 4528 %} 4529 4530 operand rarg4RegL() %{ 4531 constraint(ALLOC_IN_RC(rarg4_bits64_reg)); 4532 match(iRegLdst); 4533 format %{ %} 4534 interface(REG_INTER); 4535 %} 4536 4537 // Pointer Destination Register 4538 // See definition of reg_class bits64_reg_rw. 4539 operand iRegPdst() %{ 4540 constraint(ALLOC_IN_RC(bits64_reg_rw)); 4541 match(RegP); 4542 match(rscratch1RegP); 4543 match(rscratch2RegP); 4544 match(rarg1RegP); 4545 match(rarg2RegP); 4546 match(rarg3RegP); 4547 match(rarg4RegP); 4548 format %{ %} 4549 interface(REG_INTER); 4550 %} 4551 4552 // Pointer Destination Register 4553 // Operand not using r11 and r12 (killed in epilog). 4554 operand iRegPdstNoScratch() %{ 4555 constraint(ALLOC_IN_RC(bits64_reg_leaf_call)); 4556 match(RegP); 4557 match(rarg1RegP); 4558 match(rarg2RegP); 4559 match(rarg3RegP); 4560 match(rarg4RegP); 4561 format %{ %} 4562 interface(REG_INTER); 4563 %} 4564 4565 // Pointer Source Register 4566 // See definition of reg_class bits64_reg_ro. 4567 operand iRegPsrc() %{ 4568 constraint(ALLOC_IN_RC(bits64_reg_ro)); 4569 match(RegP); 4570 match(iRegPdst); 4571 match(rscratch1RegP); 4572 match(rscratch2RegP); 4573 match(rarg1RegP); 4574 match(rarg2RegP); 4575 match(rarg3RegP); 4576 match(rarg4RegP); 4577 match(threadRegP); 4578 format %{ %} 4579 interface(REG_INTER); 4580 %} 4581 4582 // Thread operand. 4583 operand threadRegP() %{ 4584 constraint(ALLOC_IN_RC(thread_bits64_reg)); 4585 match(iRegPdst); 4586 format %{ "R16" %} 4587 interface(REG_INTER); 4588 %} 4589 4590 operand rscratch1RegP() %{ 4591 constraint(ALLOC_IN_RC(rscratch1_bits64_reg)); 4592 match(iRegPdst); 4593 format %{ "R11" %} 4594 interface(REG_INTER); 4595 %} 4596 4597 operand rscratch2RegP() %{ 4598 constraint(ALLOC_IN_RC(rscratch2_bits64_reg)); 4599 match(iRegPdst); 4600 format %{ %} 4601 interface(REG_INTER); 4602 %} 4603 4604 operand rarg1RegP() %{ 4605 constraint(ALLOC_IN_RC(rarg1_bits64_reg)); 4606 match(iRegPdst); 4607 format %{ %} 4608 interface(REG_INTER); 4609 %} 4610 4611 operand rarg2RegP() %{ 4612 constraint(ALLOC_IN_RC(rarg2_bits64_reg)); 4613 match(iRegPdst); 4614 format %{ %} 4615 interface(REG_INTER); 4616 %} 4617 4618 operand rarg3RegP() %{ 4619 constraint(ALLOC_IN_RC(rarg3_bits64_reg)); 4620 match(iRegPdst); 4621 format %{ %} 4622 interface(REG_INTER); 4623 %} 4624 4625 operand rarg4RegP() %{ 4626 constraint(ALLOC_IN_RC(rarg4_bits64_reg)); 4627 match(iRegPdst); 4628 format %{ %} 4629 interface(REG_INTER); 4630 %} 4631 4632 operand iRegNsrc() %{ 4633 constraint(ALLOC_IN_RC(bits32_reg_ro)); 4634 match(RegN); 4635 match(iRegNdst); 4636 4637 format %{ %} 4638 interface(REG_INTER); 4639 %} 4640 4641 operand iRegNdst() %{ 4642 constraint(ALLOC_IN_RC(bits32_reg_rw)); 4643 match(RegN); 4644 4645 format %{ %} 4646 interface(REG_INTER); 4647 %} 4648 4649 // Long Destination Register 4650 // See definition of reg_class bits64_reg_rw. 4651 operand iRegLdst() %{ 4652 constraint(ALLOC_IN_RC(bits64_reg_rw)); 4653 match(RegL); 4654 match(rscratch1RegL); 4655 match(rscratch2RegL); 4656 format %{ %} 4657 interface(REG_INTER); 4658 %} 4659 4660 // Long Source Register 4661 // See definition of reg_class bits64_reg_ro. 4662 operand iRegLsrc() %{ 4663 constraint(ALLOC_IN_RC(bits64_reg_ro)); 4664 match(RegL); 4665 match(iRegLdst); 4666 match(rscratch1RegL); 4667 match(rscratch2RegL); 4668 format %{ %} 4669 interface(REG_INTER); 4670 %} 4671 4672 // Special operand for ConvL2I. 4673 operand iRegL2Isrc(iRegLsrc reg) %{ 4674 constraint(ALLOC_IN_RC(bits64_reg_ro)); 4675 match(ConvL2I reg); 4676 format %{ "ConvL2I($reg)" %} 4677 interface(REG_INTER) 4678 %} 4679 4680 operand rscratch1RegL() %{ 4681 constraint(ALLOC_IN_RC(rscratch1_bits64_reg)); 4682 match(RegL); 4683 format %{ %} 4684 interface(REG_INTER); 4685 %} 4686 4687 operand rscratch2RegL() %{ 4688 constraint(ALLOC_IN_RC(rscratch2_bits64_reg)); 4689 match(RegL); 4690 format %{ %} 4691 interface(REG_INTER); 4692 %} 4693 4694 // Condition Code Flag Registers 4695 operand flagsReg() %{ 4696 constraint(ALLOC_IN_RC(int_flags)); 4697 match(RegFlags); 4698 format %{ %} 4699 interface(REG_INTER); 4700 %} 4701 4702 // Condition Code Flag Register CR0 4703 operand flagsRegCR0() %{ 4704 constraint(ALLOC_IN_RC(int_flags_CR0)); 4705 match(RegFlags); 4706 format %{ "CR0" %} 4707 interface(REG_INTER); 4708 %} 4709 4710 operand flagsRegCR1() %{ 4711 constraint(ALLOC_IN_RC(int_flags_CR1)); 4712 match(RegFlags); 4713 format %{ "CR1" %} 4714 interface(REG_INTER); 4715 %} 4716 4717 operand flagsRegCR6() %{ 4718 constraint(ALLOC_IN_RC(int_flags_CR6)); 4719 match(RegFlags); 4720 format %{ "CR6" %} 4721 interface(REG_INTER); 4722 %} 4723 4724 operand regCTR() %{ 4725 constraint(ALLOC_IN_RC(ctr_reg)); 4726 // RegFlags should work. Introducing a RegSpecial type would cause a 4727 // lot of changes. 4728 match(RegFlags); 4729 format %{"SR_CTR" %} 4730 interface(REG_INTER); 4731 %} 4732 4733 operand regD() %{ 4734 constraint(ALLOC_IN_RC(dbl_reg)); 4735 match(RegD); 4736 format %{ %} 4737 interface(REG_INTER); 4738 %} 4739 4740 operand regF() %{ 4741 constraint(ALLOC_IN_RC(flt_reg)); 4742 match(RegF); 4743 format %{ %} 4744 interface(REG_INTER); 4745 %} 4746 4747 // Special Registers 4748 4749 // Method Register 4750 operand inline_cache_regP(iRegPdst reg) %{ 4751 constraint(ALLOC_IN_RC(r19_bits64_reg)); // inline_cache_reg 4752 match(reg); 4753 format %{ %} 4754 interface(REG_INTER); 4755 %} 4756 4757 operand compiler_method_oop_regP(iRegPdst reg) %{ 4758 constraint(ALLOC_IN_RC(rscratch1_bits64_reg)); // compiler_method_oop_reg 4759 match(reg); 4760 format %{ %} 4761 interface(REG_INTER); 4762 %} 4763 4764 operand interpreter_method_oop_regP(iRegPdst reg) %{ 4765 constraint(ALLOC_IN_RC(r19_bits64_reg)); // interpreter_method_oop_reg 4766 match(reg); 4767 format %{ %} 4768 interface(REG_INTER); 4769 %} 4770 4771 // Operands to remove register moves in unscaled mode. 4772 // Match read/write registers with an EncodeP node if neither shift nor add are required. 4773 operand iRegP2N(iRegPsrc reg) %{ 4774 predicate(false /* TODO: PPC port MatchDecodeNodes*/&& Universe::narrow_oop_shift() == 0); 4775 constraint(ALLOC_IN_RC(bits64_reg_ro)); 4776 match(EncodeP reg); 4777 format %{ "$reg" %} 4778 interface(REG_INTER) 4779 %} 4780 4781 operand iRegN2P(iRegNsrc reg) %{ 4782 predicate(false /* TODO: PPC port MatchDecodeNodes*/); 4783 constraint(ALLOC_IN_RC(bits32_reg_ro)); 4784 match(DecodeN reg); 4785 match(DecodeNKlass reg); 4786 format %{ "$reg" %} 4787 interface(REG_INTER) 4788 %} 4789 4790 //----------Complex Operands--------------------------------------------------- 4791 // Indirect Memory Reference 4792 operand indirect(iRegPsrc reg) %{ 4793 constraint(ALLOC_IN_RC(bits64_reg_ro)); 4794 match(reg); 4795 op_cost(100); 4796 format %{ "[$reg]" %} 4797 interface(MEMORY_INTER) %{ 4798 base($reg); 4799 index(0x0); 4800 scale(0x0); 4801 disp(0x0); 4802 %} 4803 %} 4804 4805 // Indirect with Offset 4806 operand indOffset16(iRegPsrc reg, immL16 offset) %{ 4807 constraint(ALLOC_IN_RC(bits64_reg_ro)); 4808 match(AddP reg offset); 4809 op_cost(100); 4810 format %{ "[$reg + $offset]" %} 4811 interface(MEMORY_INTER) %{ 4812 base($reg); 4813 index(0x0); 4814 scale(0x0); 4815 disp($offset); 4816 %} 4817 %} 4818 4819 // Indirect with 4-aligned Offset 4820 operand indOffset16Alg4(iRegPsrc reg, immL16Alg4 offset) %{ 4821 constraint(ALLOC_IN_RC(bits64_reg_ro)); 4822 match(AddP reg offset); 4823 op_cost(100); 4824 format %{ "[$reg + $offset]" %} 4825 interface(MEMORY_INTER) %{ 4826 base($reg); 4827 index(0x0); 4828 scale(0x0); 4829 disp($offset); 4830 %} 4831 %} 4832 4833 //----------Complex Operands for Compressed OOPs------------------------------- 4834 // Compressed OOPs with narrow_oop_shift == 0. 4835 4836 // Indirect Memory Reference, compressed OOP 4837 operand indirectNarrow(iRegNsrc reg) %{ 4838 predicate(false /* TODO: PPC port MatchDecodeNodes*/); 4839 constraint(ALLOC_IN_RC(bits64_reg_ro)); 4840 match(DecodeN reg); 4841 match(DecodeNKlass reg); 4842 op_cost(100); 4843 format %{ "[$reg]" %} 4844 interface(MEMORY_INTER) %{ 4845 base($reg); 4846 index(0x0); 4847 scale(0x0); 4848 disp(0x0); 4849 %} 4850 %} 4851 4852 // Indirect with Offset, compressed OOP 4853 operand indOffset16Narrow(iRegNsrc reg, immL16 offset) %{ 4854 predicate(false /* TODO: PPC port MatchDecodeNodes*/); 4855 constraint(ALLOC_IN_RC(bits64_reg_ro)); 4856 match(AddP (DecodeN reg) offset); 4857 match(AddP (DecodeNKlass reg) offset); 4858 op_cost(100); 4859 format %{ "[$reg + $offset]" %} 4860 interface(MEMORY_INTER) %{ 4861 base($reg); 4862 index(0x0); 4863 scale(0x0); 4864 disp($offset); 4865 %} 4866 %} 4867 4868 // Indirect with 4-aligned Offset, compressed OOP 4869 operand indOffset16NarrowAlg4(iRegNsrc reg, immL16Alg4 offset) %{ 4870 predicate(false /* TODO: PPC port MatchDecodeNodes*/); 4871 constraint(ALLOC_IN_RC(bits64_reg_ro)); 4872 match(AddP (DecodeN reg) offset); 4873 match(AddP (DecodeNKlass reg) offset); 4874 op_cost(100); 4875 format %{ "[$reg + $offset]" %} 4876 interface(MEMORY_INTER) %{ 4877 base($reg); 4878 index(0x0); 4879 scale(0x0); 4880 disp($offset); 4881 %} 4882 %} 4883 4884 //----------Special Memory Operands-------------------------------------------- 4885 // Stack Slot Operand 4886 // 4887 // This operand is used for loading and storing temporary values on 4888 // the stack where a match requires a value to flow through memory. 4889 operand stackSlotI(sRegI reg) %{ 4890 constraint(ALLOC_IN_RC(stack_slots)); 4891 op_cost(100); 4892 //match(RegI); 4893 format %{ "[sp+$reg]" %} 4894 interface(MEMORY_INTER) %{ 4895 base(0x1); // R1_SP 4896 index(0x0); 4897 scale(0x0); 4898 disp($reg); // Stack Offset 4899 %} 4900 %} 4901 4902 operand stackSlotL(sRegL reg) %{ 4903 constraint(ALLOC_IN_RC(stack_slots)); 4904 op_cost(100); 4905 //match(RegL); 4906 format %{ "[sp+$reg]" %} 4907 interface(MEMORY_INTER) %{ 4908 base(0x1); // R1_SP 4909 index(0x0); 4910 scale(0x0); 4911 disp($reg); // Stack Offset 4912 %} 4913 %} 4914 4915 operand stackSlotP(sRegP reg) %{ 4916 constraint(ALLOC_IN_RC(stack_slots)); 4917 op_cost(100); 4918 //match(RegP); 4919 format %{ "[sp+$reg]" %} 4920 interface(MEMORY_INTER) %{ 4921 base(0x1); // R1_SP 4922 index(0x0); 4923 scale(0x0); 4924 disp($reg); // Stack Offset 4925 %} 4926 %} 4927 4928 operand stackSlotF(sRegF reg) %{ 4929 constraint(ALLOC_IN_RC(stack_slots)); 4930 op_cost(100); 4931 //match(RegF); 4932 format %{ "[sp+$reg]" %} 4933 interface(MEMORY_INTER) %{ 4934 base(0x1); // R1_SP 4935 index(0x0); 4936 scale(0x0); 4937 disp($reg); // Stack Offset 4938 %} 4939 %} 4940 4941 operand stackSlotD(sRegD reg) %{ 4942 constraint(ALLOC_IN_RC(stack_slots)); 4943 op_cost(100); 4944 //match(RegD); 4945 format %{ "[sp+$reg]" %} 4946 interface(MEMORY_INTER) %{ 4947 base(0x1); // R1_SP 4948 index(0x0); 4949 scale(0x0); 4950 disp($reg); // Stack Offset 4951 %} 4952 %} 4953 4954 // Operands for expressing Control Flow 4955 // NOTE: Label is a predefined operand which should not be redefined in 4956 // the AD file. It is generically handled within the ADLC. 4957 4958 //----------Conditional Branch Operands---------------------------------------- 4959 // Comparison Op 4960 // 4961 // This is the operation of the comparison, and is limited to the 4962 // following set of codes: L (<), LE (<=), G (>), GE (>=), E (==), NE 4963 // (!=). 4964 // 4965 // Other attributes of the comparison, such as unsignedness, are specified 4966 // by the comparison instruction that sets a condition code flags register. 4967 // That result is represented by a flags operand whose subtype is appropriate 4968 // to the unsignedness (etc.) of the comparison. 4969 // 4970 // Later, the instruction which matches both the Comparison Op (a Bool) and 4971 // the flags (produced by the Cmp) specifies the coding of the comparison op 4972 // by matching a specific subtype of Bool operand below. 4973 4974 // When used for floating point comparisons: unordered same as less. 4975 operand cmpOp() %{ 4976 match(Bool); 4977 format %{ "" %} 4978 interface(COND_INTER) %{ 4979 // BO only encodes bit 4 of bcondCRbiIsX, as bits 1-3 are always '100'. 4980 // BO & BI 4981 equal(0xA); // 10 10: bcondCRbiIs1 & Condition::equal 4982 not_equal(0x2); // 00 10: bcondCRbiIs0 & Condition::equal 4983 less(0x8); // 10 00: bcondCRbiIs1 & Condition::less 4984 greater_equal(0x0); // 00 00: bcondCRbiIs0 & Condition::less 4985 less_equal(0x1); // 00 01: bcondCRbiIs0 & Condition::greater 4986 greater(0x9); // 10 01: bcondCRbiIs1 & Condition::greater 4987 overflow(0xB); // 10 11: bcondCRbiIs1 & Condition::summary_overflow 4988 no_overflow(0x3); // 00 11: bcondCRbiIs0 & Condition::summary_overflow 4989 %} 4990 %} 4991 4992 //----------OPERAND CLASSES---------------------------------------------------- 4993 // Operand Classes are groups of operands that are used to simplify 4994 // instruction definitions by not requiring the AD writer to specify 4995 // seperate instructions for every form of operand when the 4996 // instruction accepts multiple operand types with the same basic 4997 // encoding and format. The classic case of this is memory operands. 4998 // Indirect is not included since its use is limited to Compare & Swap. 4999 5000 opclass memory(indirect, indOffset16 /*, indIndex, tlsReference*/, indirectNarrow, indOffset16Narrow); 5001 // Memory operand where offsets are 4-aligned. Required for ld, std. 5002 opclass memoryAlg4(indirect, indOffset16Alg4, indirectNarrow, indOffset16NarrowAlg4); 5003 opclass indirectMemory(indirect, indirectNarrow); 5004 5005 // Special opclass for I and ConvL2I. 5006 opclass iRegIsrc_iRegL2Isrc(iRegIsrc, iRegL2Isrc); 5007 5008 // Operand classes to match encode and decode. iRegN_P2N is only used 5009 // for storeN. I have never seen an encode node elsewhere. 5010 opclass iRegN_P2N(iRegNsrc, iRegP2N); 5011 opclass iRegP_N2P(iRegPsrc, iRegN2P); 5012 5013 //----------PIPELINE----------------------------------------------------------- 5014 5015 pipeline %{ 5016 5017 // See J.M.Tendler et al. "Power4 system microarchitecture", IBM 5018 // J. Res. & Dev., No. 1, Jan. 2002. 5019 5020 //----------ATTRIBUTES--------------------------------------------------------- 5021 attributes %{ 5022 5023 // Power4 instructions are of fixed length. 5024 fixed_size_instructions; 5025 5026 // TODO: if `bundle' means number of instructions fetched 5027 // per cycle, this is 8. If `bundle' means Power4 `group', that is 5028 // max instructions issued per cycle, this is 5. 5029 max_instructions_per_bundle = 8; 5030 5031 // A Power4 instruction is 4 bytes long. 5032 instruction_unit_size = 4; 5033 5034 // The Power4 processor fetches 64 bytes... 5035 instruction_fetch_unit_size = 64; 5036 5037 // ...in one line 5038 instruction_fetch_units = 1 5039 5040 // Unused, list one so that array generated by adlc is not empty. 5041 // Aix compiler chokes if _nop_count = 0. 5042 nops(fxNop); 5043 %} 5044 5045 //----------RESOURCES---------------------------------------------------------- 5046 // Resources are the functional units available to the machine 5047 resources( 5048 PPC_BR, // branch unit 5049 PPC_CR, // condition unit 5050 PPC_FX1, // integer arithmetic unit 1 5051 PPC_FX2, // integer arithmetic unit 2 5052 PPC_LDST1, // load/store unit 1 5053 PPC_LDST2, // load/store unit 2 5054 PPC_FP1, // float arithmetic unit 1 5055 PPC_FP2, // float arithmetic unit 2 5056 PPC_LDST = PPC_LDST1 | PPC_LDST2, 5057 PPC_FX = PPC_FX1 | PPC_FX2, 5058 PPC_FP = PPC_FP1 | PPC_FP2 5059 ); 5060 5061 //----------PIPELINE DESCRIPTION----------------------------------------------- 5062 // Pipeline Description specifies the stages in the machine's pipeline 5063 pipe_desc( 5064 // Power4 longest pipeline path 5065 PPC_IF, // instruction fetch 5066 PPC_IC, 5067 //PPC_BP, // branch prediction 5068 PPC_D0, // decode 5069 PPC_D1, // decode 5070 PPC_D2, // decode 5071 PPC_D3, // decode 5072 PPC_Xfer1, 5073 PPC_GD, // group definition 5074 PPC_MP, // map 5075 PPC_ISS, // issue 5076 PPC_RF, // resource fetch 5077 PPC_EX1, // execute (all units) 5078 PPC_EX2, // execute (FP, LDST) 5079 PPC_EX3, // execute (FP, LDST) 5080 PPC_EX4, // execute (FP) 5081 PPC_EX5, // execute (FP) 5082 PPC_EX6, // execute (FP) 5083 PPC_WB, // write back 5084 PPC_Xfer2, 5085 PPC_CP 5086 ); 5087 5088 //----------PIPELINE CLASSES--------------------------------------------------- 5089 // Pipeline Classes describe the stages in which input and output are 5090 // referenced by the hardware pipeline. 5091 5092 // Simple pipeline classes. 5093 5094 // Default pipeline class. 5095 pipe_class pipe_class_default() %{ 5096 single_instruction; 5097 fixed_latency(2); 5098 %} 5099 5100 // Pipeline class for empty instructions. 5101 pipe_class pipe_class_empty() %{ 5102 single_instruction; 5103 fixed_latency(0); 5104 %} 5105 5106 // Pipeline class for compares. 5107 pipe_class pipe_class_compare() %{ 5108 single_instruction; 5109 fixed_latency(16); 5110 %} 5111 5112 // Pipeline class for traps. 5113 pipe_class pipe_class_trap() %{ 5114 single_instruction; 5115 fixed_latency(100); 5116 %} 5117 5118 // Pipeline class for memory operations. 5119 pipe_class pipe_class_memory() %{ 5120 single_instruction; 5121 fixed_latency(16); 5122 %} 5123 5124 // Pipeline class for call. 5125 pipe_class pipe_class_call() %{ 5126 single_instruction; 5127 fixed_latency(100); 5128 %} 5129 5130 // Define the class for the Nop node. 5131 define %{ 5132 MachNop = pipe_class_default; 5133 %} 5134 5135 %} 5136 5137 //----------INSTRUCTIONS------------------------------------------------------- 5138 5139 // Naming of instructions: 5140 // opA_operB / opA_operB_operC: 5141 // Operation 'op' with one or two source operands 'oper'. Result 5142 // type is A, source operand types are B and C. 5143 // Iff A == B == C, B and C are left out. 5144 // 5145 // The instructions are ordered according to the following scheme: 5146 // - loads 5147 // - load constants 5148 // - prefetch 5149 // - store 5150 // - encode/decode 5151 // - membar 5152 // - conditional moves 5153 // - compare & swap 5154 // - arithmetic and logic operations 5155 // * int: Add, Sub, Mul, Div, Mod 5156 // * int: lShift, arShift, urShift, rot 5157 // * float: Add, Sub, Mul, Div 5158 // * and, or, xor ... 5159 // - register moves: float <-> int, reg <-> stack, repl 5160 // - cast (high level type cast, XtoP, castPP, castII, not_null etc. 5161 // - conv (low level type cast requiring bit changes (sign extend etc) 5162 // - compares, range & zero checks. 5163 // - branches 5164 // - complex operations, intrinsics, min, max, replicate 5165 // - lock 5166 // - Calls 5167 // 5168 // If there are similar instructions with different types they are sorted: 5169 // int before float 5170 // small before big 5171 // signed before unsigned 5172 // e.g., loadS before loadUS before loadI before loadF. 5173 5174 5175 //----------Load/Store Instructions-------------------------------------------- 5176 5177 //----------Load Instructions-------------------------------------------------- 5178 5179 // Converts byte to int. 5180 // As convB2I_reg, but without match rule. The match rule of convB2I_reg 5181 // reuses the 'amount' operand, but adlc expects that operand specification 5182 // and operands in match rule are equivalent. 5183 instruct convB2I_reg_2(iRegIdst dst, iRegIsrc src) %{ 5184 effect(DEF dst, USE src); 5185 format %{ "EXTSB $dst, $src \t// byte->int" %} 5186 size(4); 5187 ins_encode %{ 5188 // TODO: PPC port $archOpcode(ppc64Opcode_extsb); 5189 __ extsb($dst$$Register, $src$$Register); 5190 %} 5191 ins_pipe(pipe_class_default); 5192 %} 5193 5194 instruct loadUB_indirect(iRegIdst dst, indirectMemory mem) %{ 5195 // match-rule, false predicate 5196 match(Set dst (LoadB mem)); 5197 predicate(false); 5198 5199 format %{ "LBZ $dst, $mem" %} 5200 size(4); 5201 ins_encode( enc_lbz(dst, mem) ); 5202 ins_pipe(pipe_class_memory); 5203 %} 5204 5205 instruct loadUB_indirect_ac(iRegIdst dst, indirectMemory mem) %{ 5206 // match-rule, false predicate 5207 match(Set dst (LoadB mem)); 5208 predicate(false); 5209 5210 format %{ "LBZ $dst, $mem\n\t" 5211 "TWI $dst\n\t" 5212 "ISYNC" %} 5213 size(12); 5214 ins_encode( enc_lbz_ac(dst, mem) ); 5215 ins_pipe(pipe_class_memory); 5216 %} 5217 5218 // Load Byte (8bit signed). LoadB = LoadUB + ConvUB2B. 5219 instruct loadB_indirect_Ex(iRegIdst dst, indirectMemory mem) %{ 5220 match(Set dst (LoadB mem)); 5221 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n)); 5222 ins_cost(MEMORY_REF_COST + DEFAULT_COST); 5223 expand %{ 5224 iRegIdst tmp; 5225 loadUB_indirect(tmp, mem); 5226 convB2I_reg_2(dst, tmp); 5227 %} 5228 %} 5229 5230 instruct loadB_indirect_ac_Ex(iRegIdst dst, indirectMemory mem) %{ 5231 match(Set dst (LoadB mem)); 5232 ins_cost(3*MEMORY_REF_COST + DEFAULT_COST); 5233 expand %{ 5234 iRegIdst tmp; 5235 loadUB_indirect_ac(tmp, mem); 5236 convB2I_reg_2(dst, tmp); 5237 %} 5238 %} 5239 5240 instruct loadUB_indOffset16(iRegIdst dst, indOffset16 mem) %{ 5241 // match-rule, false predicate 5242 match(Set dst (LoadB mem)); 5243 predicate(false); 5244 5245 format %{ "LBZ $dst, $mem" %} 5246 size(4); 5247 ins_encode( enc_lbz(dst, mem) ); 5248 ins_pipe(pipe_class_memory); 5249 %} 5250 5251 instruct loadUB_indOffset16_ac(iRegIdst dst, indOffset16 mem) %{ 5252 // match-rule, false predicate 5253 match(Set dst (LoadB mem)); 5254 predicate(false); 5255 5256 format %{ "LBZ $dst, $mem\n\t" 5257 "TWI $dst\n\t" 5258 "ISYNC" %} 5259 size(12); 5260 ins_encode( enc_lbz_ac(dst, mem) ); 5261 ins_pipe(pipe_class_memory); 5262 %} 5263 5264 // Load Byte (8bit signed). LoadB = LoadUB + ConvUB2B. 5265 instruct loadB_indOffset16_Ex(iRegIdst dst, indOffset16 mem) %{ 5266 match(Set dst (LoadB mem)); 5267 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n)); 5268 ins_cost(MEMORY_REF_COST + DEFAULT_COST); 5269 5270 expand %{ 5271 iRegIdst tmp; 5272 loadUB_indOffset16(tmp, mem); 5273 convB2I_reg_2(dst, tmp); 5274 %} 5275 %} 5276 5277 instruct loadB_indOffset16_ac_Ex(iRegIdst dst, indOffset16 mem) %{ 5278 match(Set dst (LoadB mem)); 5279 ins_cost(3*MEMORY_REF_COST + DEFAULT_COST); 5280 5281 expand %{ 5282 iRegIdst tmp; 5283 loadUB_indOffset16_ac(tmp, mem); 5284 convB2I_reg_2(dst, tmp); 5285 %} 5286 %} 5287 5288 // Load Unsigned Byte (8bit UNsigned) into an int reg. 5289 instruct loadUB(iRegIdst dst, memory mem) %{ 5290 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n)); 5291 match(Set dst (LoadUB mem)); 5292 ins_cost(MEMORY_REF_COST); 5293 5294 format %{ "LBZ $dst, $mem \t// byte, zero-extend to int" %} 5295 size(4); 5296 ins_encode( enc_lbz(dst, mem) ); 5297 ins_pipe(pipe_class_memory); 5298 %} 5299 5300 // Load Unsigned Byte (8bit UNsigned) acquire. 5301 instruct loadUB_ac(iRegIdst dst, memory mem) %{ 5302 match(Set dst (LoadUB mem)); 5303 ins_cost(3*MEMORY_REF_COST); 5304 5305 format %{ "LBZ $dst, $mem \t// byte, zero-extend to int, acquire\n\t" 5306 "TWI $dst\n\t" 5307 "ISYNC" %} 5308 size(12); 5309 ins_encode( enc_lbz_ac(dst, mem) ); 5310 ins_pipe(pipe_class_memory); 5311 %} 5312 5313 // Load Unsigned Byte (8bit UNsigned) into a Long Register. 5314 instruct loadUB2L(iRegLdst dst, memory mem) %{ 5315 match(Set dst (ConvI2L (LoadUB mem))); 5316 predicate(_kids[0]->_leaf->as_Load()->is_unordered() || followed_by_acquire(_kids[0]->_leaf)); 5317 ins_cost(MEMORY_REF_COST); 5318 5319 format %{ "LBZ $dst, $mem \t// byte, zero-extend to long" %} 5320 size(4); 5321 ins_encode( enc_lbz(dst, mem) ); 5322 ins_pipe(pipe_class_memory); 5323 %} 5324 5325 instruct loadUB2L_ac(iRegLdst dst, memory mem) %{ 5326 match(Set dst (ConvI2L (LoadUB mem))); 5327 ins_cost(3*MEMORY_REF_COST); 5328 5329 format %{ "LBZ $dst, $mem \t// byte, zero-extend to long, acquire\n\t" 5330 "TWI $dst\n\t" 5331 "ISYNC" %} 5332 size(12); 5333 ins_encode( enc_lbz_ac(dst, mem) ); 5334 ins_pipe(pipe_class_memory); 5335 %} 5336 5337 // Load Short (16bit signed) 5338 instruct loadS(iRegIdst dst, memory mem) %{ 5339 match(Set dst (LoadS mem)); 5340 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n)); 5341 ins_cost(MEMORY_REF_COST); 5342 5343 format %{ "LHA $dst, $mem" %} 5344 size(4); 5345 ins_encode %{ 5346 // TODO: PPC port $archOpcode(ppc64Opcode_lha); 5347 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); 5348 __ lha($dst$$Register, Idisp, $mem$$base$$Register); 5349 %} 5350 ins_pipe(pipe_class_memory); 5351 %} 5352 5353 // Load Short (16bit signed) acquire. 5354 instruct loadS_ac(iRegIdst dst, memory mem) %{ 5355 match(Set dst (LoadS mem)); 5356 ins_cost(3*MEMORY_REF_COST); 5357 5358 format %{ "LHA $dst, $mem\t acquire\n\t" 5359 "TWI $dst\n\t" 5360 "ISYNC" %} 5361 size(12); 5362 ins_encode %{ 5363 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 5364 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); 5365 __ lha($dst$$Register, Idisp, $mem$$base$$Register); 5366 __ twi_0($dst$$Register); 5367 __ isync(); 5368 %} 5369 ins_pipe(pipe_class_memory); 5370 %} 5371 5372 // Load Char (16bit unsigned) 5373 instruct loadUS(iRegIdst dst, memory mem) %{ 5374 match(Set dst (LoadUS mem)); 5375 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n)); 5376 ins_cost(MEMORY_REF_COST); 5377 5378 format %{ "LHZ $dst, $mem" %} 5379 size(4); 5380 ins_encode( enc_lhz(dst, mem) ); 5381 ins_pipe(pipe_class_memory); 5382 %} 5383 5384 // Load Char (16bit unsigned) acquire. 5385 instruct loadUS_ac(iRegIdst dst, memory mem) %{ 5386 match(Set dst (LoadUS mem)); 5387 ins_cost(3*MEMORY_REF_COST); 5388 5389 format %{ "LHZ $dst, $mem \t// acquire\n\t" 5390 "TWI $dst\n\t" 5391 "ISYNC" %} 5392 size(12); 5393 ins_encode( enc_lhz_ac(dst, mem) ); 5394 ins_pipe(pipe_class_memory); 5395 %} 5396 5397 // Load Unsigned Short/Char (16bit UNsigned) into a Long Register. 5398 instruct loadUS2L(iRegLdst dst, memory mem) %{ 5399 match(Set dst (ConvI2L (LoadUS mem))); 5400 predicate(_kids[0]->_leaf->as_Load()->is_unordered() || followed_by_acquire(_kids[0]->_leaf)); 5401 ins_cost(MEMORY_REF_COST); 5402 5403 format %{ "LHZ $dst, $mem \t// short, zero-extend to long" %} 5404 size(4); 5405 ins_encode( enc_lhz(dst, mem) ); 5406 ins_pipe(pipe_class_memory); 5407 %} 5408 5409 // Load Unsigned Short/Char (16bit UNsigned) into a Long Register acquire. 5410 instruct loadUS2L_ac(iRegLdst dst, memory mem) %{ 5411 match(Set dst (ConvI2L (LoadUS mem))); 5412 ins_cost(3*MEMORY_REF_COST); 5413 5414 format %{ "LHZ $dst, $mem \t// short, zero-extend to long, acquire\n\t" 5415 "TWI $dst\n\t" 5416 "ISYNC" %} 5417 size(12); 5418 ins_encode( enc_lhz_ac(dst, mem) ); 5419 ins_pipe(pipe_class_memory); 5420 %} 5421 5422 // Load Integer. 5423 instruct loadI(iRegIdst dst, memory mem) %{ 5424 match(Set dst (LoadI mem)); 5425 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n)); 5426 ins_cost(MEMORY_REF_COST); 5427 5428 format %{ "LWZ $dst, $mem" %} 5429 size(4); 5430 ins_encode( enc_lwz(dst, mem) ); 5431 ins_pipe(pipe_class_memory); 5432 %} 5433 5434 // Load Integer acquire. 5435 instruct loadI_ac(iRegIdst dst, memory mem) %{ 5436 match(Set dst (LoadI mem)); 5437 ins_cost(3*MEMORY_REF_COST); 5438 5439 format %{ "LWZ $dst, $mem \t// load acquire\n\t" 5440 "TWI $dst\n\t" 5441 "ISYNC" %} 5442 size(12); 5443 ins_encode( enc_lwz_ac(dst, mem) ); 5444 ins_pipe(pipe_class_memory); 5445 %} 5446 5447 // Match loading integer and casting it to unsigned int in 5448 // long register. 5449 // LoadI + ConvI2L + AndL 0xffffffff. 5450 instruct loadUI2L(iRegLdst dst, memory mem, immL_32bits mask) %{ 5451 match(Set dst (AndL (ConvI2L (LoadI mem)) mask)); 5452 predicate(_kids[0]->_kids[0]->_leaf->as_Load()->is_unordered()); 5453 ins_cost(MEMORY_REF_COST); 5454 5455 format %{ "LWZ $dst, $mem \t// zero-extend to long" %} 5456 size(4); 5457 ins_encode( enc_lwz(dst, mem) ); 5458 ins_pipe(pipe_class_memory); 5459 %} 5460 5461 // Match loading integer and casting it to long. 5462 instruct loadI2L(iRegLdst dst, memory mem) %{ 5463 match(Set dst (ConvI2L (LoadI mem))); 5464 predicate(_kids[0]->_leaf->as_Load()->is_unordered()); 5465 ins_cost(MEMORY_REF_COST); 5466 5467 format %{ "LWA $dst, $mem \t// loadI2L" %} 5468 size(4); 5469 ins_encode %{ 5470 // TODO: PPC port $archOpcode(ppc64Opcode_lwa); 5471 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); 5472 __ lwa($dst$$Register, Idisp, $mem$$base$$Register); 5473 %} 5474 ins_pipe(pipe_class_memory); 5475 %} 5476 5477 // Match loading integer and casting it to long - acquire. 5478 instruct loadI2L_ac(iRegLdst dst, memory mem) %{ 5479 match(Set dst (ConvI2L (LoadI mem))); 5480 ins_cost(3*MEMORY_REF_COST); 5481 5482 format %{ "LWA $dst, $mem \t// loadI2L acquire" 5483 "TWI $dst\n\t" 5484 "ISYNC" %} 5485 size(12); 5486 ins_encode %{ 5487 // TODO: PPC port $archOpcode(ppc64Opcode_lwa); 5488 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); 5489 __ lwa($dst$$Register, Idisp, $mem$$base$$Register); 5490 __ twi_0($dst$$Register); 5491 __ isync(); 5492 %} 5493 ins_pipe(pipe_class_memory); 5494 %} 5495 5496 // Load Long - aligned 5497 instruct loadL(iRegLdst dst, memoryAlg4 mem) %{ 5498 match(Set dst (LoadL mem)); 5499 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n)); 5500 ins_cost(MEMORY_REF_COST); 5501 5502 format %{ "LD $dst, $mem \t// long" %} 5503 size(4); 5504 ins_encode( enc_ld(dst, mem) ); 5505 ins_pipe(pipe_class_memory); 5506 %} 5507 5508 // Load Long - aligned acquire. 5509 instruct loadL_ac(iRegLdst dst, memoryAlg4 mem) %{ 5510 match(Set dst (LoadL mem)); 5511 ins_cost(3*MEMORY_REF_COST); 5512 5513 format %{ "LD $dst, $mem \t// long acquire\n\t" 5514 "TWI $dst\n\t" 5515 "ISYNC" %} 5516 size(12); 5517 ins_encode( enc_ld_ac(dst, mem) ); 5518 ins_pipe(pipe_class_memory); 5519 %} 5520 5521 // Load Long - UNaligned 5522 instruct loadL_unaligned(iRegLdst dst, memoryAlg4 mem) %{ 5523 match(Set dst (LoadL_unaligned mem)); 5524 // predicate(...) // Unaligned_ac is not needed (and wouldn't make sense). 5525 ins_cost(MEMORY_REF_COST); 5526 5527 format %{ "LD $dst, $mem \t// unaligned long" %} 5528 size(4); 5529 ins_encode( enc_ld(dst, mem) ); 5530 ins_pipe(pipe_class_memory); 5531 %} 5532 5533 // Load nodes for superwords 5534 5535 // Load Aligned Packed Byte 5536 instruct loadV8(iRegLdst dst, memoryAlg4 mem) %{ 5537 predicate(n->as_LoadVector()->memory_size() == 8); 5538 match(Set dst (LoadVector mem)); 5539 ins_cost(MEMORY_REF_COST); 5540 5541 format %{ "LD $dst, $mem \t// load 8-byte Vector" %} 5542 size(4); 5543 ins_encode( enc_ld(dst, mem) ); 5544 ins_pipe(pipe_class_memory); 5545 %} 5546 5547 // Load Range, range = array length (=jint) 5548 instruct loadRange(iRegIdst dst, memory mem) %{ 5549 match(Set dst (LoadRange mem)); 5550 ins_cost(MEMORY_REF_COST); 5551 5552 format %{ "LWZ $dst, $mem \t// range" %} 5553 size(4); 5554 ins_encode( enc_lwz(dst, mem) ); 5555 ins_pipe(pipe_class_memory); 5556 %} 5557 5558 // Load Compressed Pointer 5559 instruct loadN(iRegNdst dst, memory mem) %{ 5560 match(Set dst (LoadN mem)); 5561 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n)); 5562 ins_cost(MEMORY_REF_COST); 5563 5564 format %{ "LWZ $dst, $mem \t// load compressed ptr" %} 5565 size(4); 5566 ins_encode( enc_lwz(dst, mem) ); 5567 ins_pipe(pipe_class_memory); 5568 %} 5569 5570 // Load Compressed Pointer acquire. 5571 instruct loadN_ac(iRegNdst dst, memory mem) %{ 5572 match(Set dst (LoadN mem)); 5573 ins_cost(3*MEMORY_REF_COST); 5574 5575 format %{ "LWZ $dst, $mem \t// load acquire compressed ptr\n\t" 5576 "TWI $dst\n\t" 5577 "ISYNC" %} 5578 size(12); 5579 ins_encode( enc_lwz_ac(dst, mem) ); 5580 ins_pipe(pipe_class_memory); 5581 %} 5582 5583 // Load Compressed Pointer and decode it if narrow_oop_shift == 0. 5584 instruct loadN2P_unscaled(iRegPdst dst, memory mem) %{ 5585 match(Set dst (DecodeN (LoadN mem))); 5586 predicate(_kids[0]->_leaf->as_Load()->is_unordered() && Universe::narrow_oop_shift() == 0); 5587 ins_cost(MEMORY_REF_COST); 5588 5589 format %{ "LWZ $dst, $mem \t// DecodeN (unscaled)" %} 5590 size(4); 5591 ins_encode( enc_lwz(dst, mem) ); 5592 ins_pipe(pipe_class_memory); 5593 %} 5594 5595 // Load Pointer 5596 instruct loadP(iRegPdst dst, memoryAlg4 mem) %{ 5597 match(Set dst (LoadP mem)); 5598 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n)); 5599 ins_cost(MEMORY_REF_COST); 5600 5601 format %{ "LD $dst, $mem \t// ptr" %} 5602 size(4); 5603 ins_encode( enc_ld(dst, mem) ); 5604 ins_pipe(pipe_class_memory); 5605 %} 5606 5607 // Load Pointer acquire. 5608 instruct loadP_ac(iRegPdst dst, memoryAlg4 mem) %{ 5609 match(Set dst (LoadP mem)); 5610 ins_cost(3*MEMORY_REF_COST); 5611 5612 format %{ "LD $dst, $mem \t// ptr acquire\n\t" 5613 "TWI $dst\n\t" 5614 "ISYNC" %} 5615 size(12); 5616 ins_encode( enc_ld_ac(dst, mem) ); 5617 ins_pipe(pipe_class_memory); 5618 %} 5619 5620 // LoadP + CastP2L 5621 instruct loadP2X(iRegLdst dst, memoryAlg4 mem) %{ 5622 match(Set dst (CastP2X (LoadP mem))); 5623 predicate(_kids[0]->_leaf->as_Load()->is_unordered()); 5624 ins_cost(MEMORY_REF_COST); 5625 5626 format %{ "LD $dst, $mem \t// ptr + p2x" %} 5627 size(4); 5628 ins_encode( enc_ld(dst, mem) ); 5629 ins_pipe(pipe_class_memory); 5630 %} 5631 5632 // Load compressed klass pointer. 5633 instruct loadNKlass(iRegNdst dst, memory mem) %{ 5634 match(Set dst (LoadNKlass mem)); 5635 ins_cost(MEMORY_REF_COST); 5636 5637 format %{ "LWZ $dst, $mem \t// compressed klass ptr" %} 5638 size(4); 5639 ins_encode( enc_lwz(dst, mem) ); 5640 ins_pipe(pipe_class_memory); 5641 %} 5642 5643 //// Load compressed klass and decode it if narrow_klass_shift == 0. 5644 //// TODO: will narrow_klass_shift ever be 0? 5645 //instruct decodeNKlass2Klass(iRegPdst dst, memory mem) %{ 5646 // match(Set dst (DecodeNKlass (LoadNKlass mem))); 5647 // predicate(false /* TODO: PPC port Universe::narrow_klass_shift() == 0*); 5648 // ins_cost(MEMORY_REF_COST); 5649 // 5650 // format %{ "LWZ $dst, $mem \t// DecodeNKlass (unscaled)" %} 5651 // size(4); 5652 // ins_encode( enc_lwz(dst, mem) ); 5653 // ins_pipe(pipe_class_memory); 5654 //%} 5655 5656 // Load Klass Pointer 5657 instruct loadKlass(iRegPdst dst, memoryAlg4 mem) %{ 5658 match(Set dst (LoadKlass mem)); 5659 ins_cost(MEMORY_REF_COST); 5660 5661 format %{ "LD $dst, $mem \t// klass ptr" %} 5662 size(4); 5663 ins_encode( enc_ld(dst, mem) ); 5664 ins_pipe(pipe_class_memory); 5665 %} 5666 5667 // Load Float 5668 instruct loadF(regF dst, memory mem) %{ 5669 match(Set dst (LoadF mem)); 5670 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n)); 5671 ins_cost(MEMORY_REF_COST); 5672 5673 format %{ "LFS $dst, $mem" %} 5674 size(4); 5675 ins_encode %{ 5676 // TODO: PPC port $archOpcode(ppc64Opcode_lfs); 5677 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); 5678 __ lfs($dst$$FloatRegister, Idisp, $mem$$base$$Register); 5679 %} 5680 ins_pipe(pipe_class_memory); 5681 %} 5682 5683 // Load Float acquire. 5684 instruct loadF_ac(regF dst, memory mem) %{ 5685 match(Set dst (LoadF mem)); 5686 ins_cost(3*MEMORY_REF_COST); 5687 5688 format %{ "LFS $dst, $mem \t// acquire\n\t" 5689 "FCMPU cr0, $dst, $dst\n\t" 5690 "BNE cr0, next\n" 5691 "next:\n\t" 5692 "ISYNC" %} 5693 size(16); 5694 ins_encode %{ 5695 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 5696 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); 5697 Label next; 5698 __ lfs($dst$$FloatRegister, Idisp, $mem$$base$$Register); 5699 __ fcmpu(CCR0, $dst$$FloatRegister, $dst$$FloatRegister); 5700 __ bne(CCR0, next); 5701 __ bind(next); 5702 __ isync(); 5703 %} 5704 ins_pipe(pipe_class_memory); 5705 %} 5706 5707 // Load Double - aligned 5708 instruct loadD(regD dst, memory mem) %{ 5709 match(Set dst (LoadD mem)); 5710 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n)); 5711 ins_cost(MEMORY_REF_COST); 5712 5713 format %{ "LFD $dst, $mem" %} 5714 size(4); 5715 ins_encode( enc_lfd(dst, mem) ); 5716 ins_pipe(pipe_class_memory); 5717 %} 5718 5719 // Load Double - aligned acquire. 5720 instruct loadD_ac(regD dst, memory mem) %{ 5721 match(Set dst (LoadD mem)); 5722 ins_cost(3*MEMORY_REF_COST); 5723 5724 format %{ "LFD $dst, $mem \t// acquire\n\t" 5725 "FCMPU cr0, $dst, $dst\n\t" 5726 "BNE cr0, next\n" 5727 "next:\n\t" 5728 "ISYNC" %} 5729 size(16); 5730 ins_encode %{ 5731 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 5732 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); 5733 Label next; 5734 __ lfd($dst$$FloatRegister, Idisp, $mem$$base$$Register); 5735 __ fcmpu(CCR0, $dst$$FloatRegister, $dst$$FloatRegister); 5736 __ bne(CCR0, next); 5737 __ bind(next); 5738 __ isync(); 5739 %} 5740 ins_pipe(pipe_class_memory); 5741 %} 5742 5743 // Load Double - UNaligned 5744 instruct loadD_unaligned(regD dst, memory mem) %{ 5745 match(Set dst (LoadD_unaligned mem)); 5746 // predicate(...) // Unaligned_ac is not needed (and wouldn't make sense). 5747 ins_cost(MEMORY_REF_COST); 5748 5749 format %{ "LFD $dst, $mem" %} 5750 size(4); 5751 ins_encode( enc_lfd(dst, mem) ); 5752 ins_pipe(pipe_class_memory); 5753 %} 5754 5755 //----------Constants-------------------------------------------------------- 5756 5757 // Load MachConstantTableBase: add hi offset to global toc. 5758 // TODO: Handle hidden register r29 in bundler! 5759 instruct loadToc_hi(iRegLdst dst) %{ 5760 effect(DEF dst); 5761 ins_cost(DEFAULT_COST); 5762 5763 format %{ "ADDIS $dst, R29, DISP.hi \t// load TOC hi" %} 5764 size(4); 5765 ins_encode %{ 5766 // TODO: PPC port $archOpcode(ppc64Opcode_addis); 5767 __ calculate_address_from_global_toc_hi16only($dst$$Register, __ method_toc()); 5768 %} 5769 ins_pipe(pipe_class_default); 5770 %} 5771 5772 // Load MachConstantTableBase: add lo offset to global toc. 5773 instruct loadToc_lo(iRegLdst dst, iRegLdst src) %{ 5774 effect(DEF dst, USE src); 5775 ins_cost(DEFAULT_COST); 5776 5777 format %{ "ADDI $dst, $src, DISP.lo \t// load TOC lo" %} 5778 size(4); 5779 ins_encode %{ 5780 // TODO: PPC port $archOpcode(ppc64Opcode_ori); 5781 __ calculate_address_from_global_toc_lo16only($dst$$Register, __ method_toc()); 5782 %} 5783 ins_pipe(pipe_class_default); 5784 %} 5785 5786 // Load 16-bit integer constant 0xssss???? 5787 instruct loadConI16(iRegIdst dst, immI16 src) %{ 5788 match(Set dst src); 5789 5790 format %{ "LI $dst, $src" %} 5791 size(4); 5792 ins_encode %{ 5793 // TODO: PPC port $archOpcode(ppc64Opcode_addi); 5794 __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF))); 5795 %} 5796 ins_pipe(pipe_class_default); 5797 %} 5798 5799 // Load integer constant 0x????0000 5800 instruct loadConIhi16(iRegIdst dst, immIhi16 src) %{ 5801 match(Set dst src); 5802 ins_cost(DEFAULT_COST); 5803 5804 format %{ "LIS $dst, $src.hi" %} 5805 size(4); 5806 ins_encode %{ 5807 // TODO: PPC port $archOpcode(ppc64Opcode_addis); 5808 // Lis sign extends 16-bit src then shifts it 16 bit to the left. 5809 __ lis($dst$$Register, (int)((short)(($src$$constant & 0xFFFF0000) >> 16))); 5810 %} 5811 ins_pipe(pipe_class_default); 5812 %} 5813 5814 // Part 2 of loading 32 bit constant: hi16 is is src1 (properly shifted 5815 // and sign extended), this adds the low 16 bits. 5816 instruct loadConI32_lo16(iRegIdst dst, iRegIsrc src1, immI16 src2) %{ 5817 // no match-rule, false predicate 5818 effect(DEF dst, USE src1, USE src2); 5819 predicate(false); 5820 5821 format %{ "ORI $dst, $src1.hi, $src2.lo" %} 5822 size(4); 5823 ins_encode %{ 5824 // TODO: PPC port $archOpcode(ppc64Opcode_ori); 5825 __ ori($dst$$Register, $src1$$Register, ($src2$$constant) & 0xFFFF); 5826 %} 5827 ins_pipe(pipe_class_default); 5828 %} 5829 5830 instruct loadConI_Ex(iRegIdst dst, immI src) %{ 5831 match(Set dst src); 5832 ins_cost(DEFAULT_COST*2); 5833 5834 expand %{ 5835 // Would like to use $src$$constant. 5836 immI16 srcLo %{ _opnds[1]->constant() %} 5837 // srcHi can be 0000 if srcLo sign-extends to a negative number. 5838 immIhi16 srcHi %{ _opnds[1]->constant() %} 5839 iRegIdst tmpI; 5840 loadConIhi16(tmpI, srcHi); 5841 loadConI32_lo16(dst, tmpI, srcLo); 5842 %} 5843 %} 5844 5845 // No constant pool entries required. 5846 instruct loadConL16(iRegLdst dst, immL16 src) %{ 5847 match(Set dst src); 5848 5849 format %{ "LI $dst, $src \t// long" %} 5850 size(4); 5851 ins_encode %{ 5852 // TODO: PPC port $archOpcode(ppc64Opcode_addi); 5853 __ li($dst$$Register, (int)((short) ($src$$constant & 0xFFFF))); 5854 %} 5855 ins_pipe(pipe_class_default); 5856 %} 5857 5858 // Load long constant 0xssssssss????0000 5859 instruct loadConL32hi16(iRegLdst dst, immL32hi16 src) %{ 5860 match(Set dst src); 5861 ins_cost(DEFAULT_COST); 5862 5863 format %{ "LIS $dst, $src.hi \t// long" %} 5864 size(4); 5865 ins_encode %{ 5866 // TODO: PPC port $archOpcode(ppc64Opcode_addis); 5867 __ lis($dst$$Register, (int)((short)(($src$$constant & 0xFFFF0000) >> 16))); 5868 %} 5869 ins_pipe(pipe_class_default); 5870 %} 5871 5872 // To load a 32 bit constant: merge lower 16 bits into already loaded 5873 // high 16 bits. 5874 instruct loadConL32_lo16(iRegLdst dst, iRegLsrc src1, immL16 src2) %{ 5875 // no match-rule, false predicate 5876 effect(DEF dst, USE src1, USE src2); 5877 predicate(false); 5878 5879 format %{ "ORI $dst, $src1, $src2.lo" %} 5880 size(4); 5881 ins_encode %{ 5882 // TODO: PPC port $archOpcode(ppc64Opcode_ori); 5883 __ ori($dst$$Register, $src1$$Register, ($src2$$constant) & 0xFFFF); 5884 %} 5885 ins_pipe(pipe_class_default); 5886 %} 5887 5888 // Load 32-bit long constant 5889 instruct loadConL32_Ex(iRegLdst dst, immL32 src) %{ 5890 match(Set dst src); 5891 ins_cost(DEFAULT_COST*2); 5892 5893 expand %{ 5894 // Would like to use $src$$constant. 5895 immL16 srcLo %{ _opnds[1]->constant() /*& 0x0000FFFFL */%} 5896 // srcHi can be 0000 if srcLo sign-extends to a negative number. 5897 immL32hi16 srcHi %{ _opnds[1]->constant() /*& 0xFFFF0000L */%} 5898 iRegLdst tmpL; 5899 loadConL32hi16(tmpL, srcHi); 5900 loadConL32_lo16(dst, tmpL, srcLo); 5901 %} 5902 %} 5903 5904 // Load long constant 0x????000000000000. 5905 instruct loadConLhighest16_Ex(iRegLdst dst, immLhighest16 src) %{ 5906 match(Set dst src); 5907 ins_cost(DEFAULT_COST); 5908 5909 expand %{ 5910 immL32hi16 srcHi %{ _opnds[1]->constant() >> 32 /*& 0xFFFF0000L */%} 5911 immI shift32 %{ 32 %} 5912 iRegLdst tmpL; 5913 loadConL32hi16(tmpL, srcHi); 5914 lshiftL_regL_immI(dst, tmpL, shift32); 5915 %} 5916 %} 5917 5918 // Expand node for constant pool load: small offset. 5919 instruct loadConL(iRegLdst dst, immL src, iRegLdst toc) %{ 5920 effect(DEF dst, USE src, USE toc); 5921 ins_cost(MEMORY_REF_COST); 5922 5923 ins_num_consts(1); 5924 // Needed so that CallDynamicJavaDirect can compute the address of this 5925 // instruction for relocation. 5926 ins_field_cbuf_insts_offset(int); 5927 5928 format %{ "LD $dst, offset, $toc \t// load long $src from TOC" %} 5929 size(4); 5930 ins_encode( enc_load_long_constL(dst, src, toc) ); 5931 ins_pipe(pipe_class_memory); 5932 %} 5933 5934 // Expand node for constant pool load: large offset. 5935 instruct loadConL_hi(iRegLdst dst, immL src, iRegLdst toc) %{ 5936 effect(DEF dst, USE src, USE toc); 5937 predicate(false); 5938 5939 ins_num_consts(1); 5940 ins_field_const_toc_offset(int); 5941 // Needed so that CallDynamicJavaDirect can compute the address of this 5942 // instruction for relocation. 5943 ins_field_cbuf_insts_offset(int); 5944 5945 format %{ "ADDIS $dst, $toc, offset \t// load long $src from TOC (hi)" %} 5946 size(4); 5947 ins_encode( enc_load_long_constL_hi(dst, toc, src) ); 5948 ins_pipe(pipe_class_default); 5949 %} 5950 5951 // Expand node for constant pool load: large offset. 5952 // No constant pool entries required. 5953 instruct loadConL_lo(iRegLdst dst, immL src, iRegLdst base) %{ 5954 effect(DEF dst, USE src, USE base); 5955 predicate(false); 5956 5957 ins_field_const_toc_offset_hi_node(loadConL_hiNode*); 5958 5959 format %{ "LD $dst, offset, $base \t// load long $src from TOC (lo)" %} 5960 size(4); 5961 ins_encode %{ 5962 // TODO: PPC port $archOpcode(ppc64Opcode_ld); 5963 int offset = ra_->C->in_scratch_emit_size() ? 0 : _const_toc_offset_hi_node->_const_toc_offset; 5964 __ ld($dst$$Register, MacroAssembler::largeoffset_si16_si16_lo(offset), $base$$Register); 5965 %} 5966 ins_pipe(pipe_class_memory); 5967 %} 5968 5969 // Load long constant from constant table. Expand in case of 5970 // offset > 16 bit is needed. 5971 // Adlc adds toc node MachConstantTableBase. 5972 instruct loadConL_Ex(iRegLdst dst, immL src) %{ 5973 match(Set dst src); 5974 ins_cost(MEMORY_REF_COST); 5975 5976 format %{ "LD $dst, offset, $constanttablebase\t// load long $src from table, postalloc expanded" %} 5977 // We can not inline the enc_class for the expand as that does not support constanttablebase. 5978 postalloc_expand( postalloc_expand_load_long_constant(dst, src, constanttablebase) ); 5979 %} 5980 5981 // Load NULL as compressed oop. 5982 instruct loadConN0(iRegNdst dst, immN_0 src) %{ 5983 match(Set dst src); 5984 ins_cost(DEFAULT_COST); 5985 5986 format %{ "LI $dst, $src \t// compressed ptr" %} 5987 size(4); 5988 ins_encode %{ 5989 // TODO: PPC port $archOpcode(ppc64Opcode_addi); 5990 __ li($dst$$Register, 0); 5991 %} 5992 ins_pipe(pipe_class_default); 5993 %} 5994 5995 // Load hi part of compressed oop constant. 5996 instruct loadConN_hi(iRegNdst dst, immN src) %{ 5997 effect(DEF dst, USE src); 5998 ins_cost(DEFAULT_COST); 5999 6000 format %{ "LIS $dst, $src \t// narrow oop hi" %} 6001 size(4); 6002 ins_encode %{ 6003 // TODO: PPC port $archOpcode(ppc64Opcode_addis); 6004 __ lis($dst$$Register, (int)(short)(($src$$constant >> 16) & 0xffff)); 6005 %} 6006 ins_pipe(pipe_class_default); 6007 %} 6008 6009 // Add lo part of compressed oop constant to already loaded hi part. 6010 instruct loadConN_lo(iRegNdst dst, iRegNsrc src1, immN src2) %{ 6011 effect(DEF dst, USE src1, USE src2); 6012 ins_cost(DEFAULT_COST); 6013 6014 format %{ "ORI $dst, $src1, $src2 \t// narrow oop lo" %} 6015 size(4); 6016 ins_encode %{ 6017 // TODO: PPC port $archOpcode(ppc64Opcode_addi); 6018 assert(__ oop_recorder() != NULL, "this assembler needs an OopRecorder"); 6019 int oop_index = __ oop_recorder()->find_index((jobject)$src2$$constant); 6020 RelocationHolder rspec = oop_Relocation::spec(oop_index); 6021 __ relocate(rspec, 1); 6022 __ ori($dst$$Register, $src1$$Register, $src2$$constant & 0xffff); 6023 %} 6024 ins_pipe(pipe_class_default); 6025 %} 6026 6027 // Needed to postalloc expand loadConN: ConN is loaded as ConI 6028 // leaving the upper 32 bits with sign-extension bits. 6029 // This clears these bits: dst = src & 0xFFFFFFFF. 6030 // TODO: Eventually call this maskN_regN_FFFFFFFF. 6031 instruct clearMs32b(iRegNdst dst, iRegNsrc src) %{ 6032 effect(DEF dst, USE src); 6033 predicate(false); 6034 6035 format %{ "MASK $dst, $src, 0xFFFFFFFF" %} // mask 6036 size(4); 6037 ins_encode %{ 6038 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl); 6039 __ clrldi($dst$$Register, $src$$Register, 0x20); 6040 %} 6041 ins_pipe(pipe_class_default); 6042 %} 6043 6044 // Loading ConN must be postalloc expanded so that edges between 6045 // the nodes are safe. They may not interfere with a safepoint. 6046 // GL TODO: This needs three instructions: better put this into the constant pool. 6047 instruct loadConN_Ex(iRegNdst dst, immN src) %{ 6048 match(Set dst src); 6049 ins_cost(DEFAULT_COST*2); 6050 6051 format %{ "LoadN $dst, $src \t// postalloc expanded" %} // mask 6052 postalloc_expand %{ 6053 MachNode *m1 = loadConN_hiNode(); 6054 MachNode *m2 = loadConN_loNode(); 6055 MachNode *m3 = clearMs32bNode(); 6056 m1->add_req(NULL); 6057 m2->add_req(NULL, m1); 6058 m3->add_req(NULL, m2); 6059 m1->_opnds[0] = op_dst; 6060 m1->_opnds[1] = op_src; 6061 m2->_opnds[0] = op_dst; 6062 m2->_opnds[1] = op_dst; 6063 m2->_opnds[2] = op_src; 6064 m3->_opnds[0] = op_dst; 6065 m3->_opnds[1] = op_dst; 6066 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 6067 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 6068 ra_->set_pair(m3->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 6069 nodes->push(m1); 6070 nodes->push(m2); 6071 nodes->push(m3); 6072 %} 6073 %} 6074 6075 instruct loadConNKlass_hi(iRegNdst dst, immNKlass src) %{ 6076 effect(DEF dst, USE src); 6077 ins_cost(DEFAULT_COST); 6078 6079 format %{ "LIS $dst, $src \t// narrow oop hi" %} 6080 size(4); 6081 ins_encode %{ 6082 // TODO: PPC port $archOpcode(ppc64Opcode_addis); 6083 intptr_t Csrc = Klass::encode_klass((Klass *)$src$$constant); 6084 __ lis($dst$$Register, (int)(short)((Csrc >> 16) & 0xffff)); 6085 %} 6086 ins_pipe(pipe_class_default); 6087 %} 6088 6089 // This needs a match rule so that build_oop_map knows this is 6090 // not a narrow oop. 6091 instruct loadConNKlass_lo(iRegNdst dst, immNKlass_NM src1, iRegNsrc src2) %{ 6092 match(Set dst src1); 6093 effect(TEMP src2); 6094 ins_cost(DEFAULT_COST); 6095 6096 format %{ "ADDI $dst, $src1, $src2 \t// narrow oop lo" %} 6097 size(4); 6098 ins_encode %{ 6099 // TODO: PPC port $archOpcode(ppc64Opcode_addi); 6100 intptr_t Csrc = Klass::encode_klass((Klass *)$src1$$constant); 6101 assert(__ oop_recorder() != NULL, "this assembler needs an OopRecorder"); 6102 int klass_index = __ oop_recorder()->find_index((Klass *)$src1$$constant); 6103 RelocationHolder rspec = metadata_Relocation::spec(klass_index); 6104 6105 __ relocate(rspec, 1); 6106 __ ori($dst$$Register, $src2$$Register, Csrc & 0xffff); 6107 %} 6108 ins_pipe(pipe_class_default); 6109 %} 6110 6111 // Loading ConNKlass must be postalloc expanded so that edges between 6112 // the nodes are safe. They may not interfere with a safepoint. 6113 instruct loadConNKlass_Ex(iRegNdst dst, immNKlass src) %{ 6114 match(Set dst src); 6115 ins_cost(DEFAULT_COST*2); 6116 6117 format %{ "LoadN $dst, $src \t// postalloc expanded" %} // mask 6118 postalloc_expand %{ 6119 // Load high bits into register. Sign extended. 6120 MachNode *m1 = loadConNKlass_hiNode(); 6121 m1->add_req(NULL); 6122 m1->_opnds[0] = op_dst; 6123 m1->_opnds[1] = op_src; 6124 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 6125 nodes->push(m1); 6126 6127 MachNode *m2 = m1; 6128 if (!Assembler::is_uimm((jlong)Klass::encode_klass((Klass *)op_src->constant()), 31)) { 6129 // Value might be 1-extended. Mask out these bits. 6130 m2 = clearMs32bNode(); 6131 m2->add_req(NULL, m1); 6132 m2->_opnds[0] = op_dst; 6133 m2->_opnds[1] = op_dst; 6134 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 6135 nodes->push(m2); 6136 } 6137 6138 MachNode *m3 = loadConNKlass_loNode(); 6139 m3->add_req(NULL, m2); 6140 m3->_opnds[0] = op_dst; 6141 m3->_opnds[1] = op_src; 6142 m3->_opnds[2] = op_dst; 6143 ra_->set_pair(m3->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 6144 nodes->push(m3); 6145 %} 6146 %} 6147 6148 // 0x1 is used in object initialization (initial object header). 6149 // No constant pool entries required. 6150 instruct loadConP0or1(iRegPdst dst, immP_0or1 src) %{ 6151 match(Set dst src); 6152 6153 format %{ "LI $dst, $src \t// ptr" %} 6154 size(4); 6155 ins_encode %{ 6156 // TODO: PPC port $archOpcode(ppc64Opcode_addi); 6157 __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF))); 6158 %} 6159 ins_pipe(pipe_class_default); 6160 %} 6161 6162 // Expand node for constant pool load: small offset. 6163 // The match rule is needed to generate the correct bottom_type(), 6164 // however this node should never match. The use of predicate is not 6165 // possible since ADLC forbids predicates for chain rules. The higher 6166 // costs do not prevent matching in this case. For that reason the 6167 // operand immP_NM with predicate(false) is used. 6168 instruct loadConP(iRegPdst dst, immP_NM src, iRegLdst toc) %{ 6169 match(Set dst src); 6170 effect(TEMP toc); 6171 6172 ins_num_consts(1); 6173 6174 format %{ "LD $dst, offset, $toc \t// load ptr $src from TOC" %} 6175 size(4); 6176 ins_encode( enc_load_long_constP(dst, src, toc) ); 6177 ins_pipe(pipe_class_memory); 6178 %} 6179 6180 // Expand node for constant pool load: large offset. 6181 instruct loadConP_hi(iRegPdst dst, immP_NM src, iRegLdst toc) %{ 6182 effect(DEF dst, USE src, USE toc); 6183 predicate(false); 6184 6185 ins_num_consts(1); 6186 ins_field_const_toc_offset(int); 6187 6188 format %{ "ADDIS $dst, $toc, offset \t// load ptr $src from TOC (hi)" %} 6189 size(4); 6190 ins_encode( enc_load_long_constP_hi(dst, src, toc) ); 6191 ins_pipe(pipe_class_default); 6192 %} 6193 6194 // Expand node for constant pool load: large offset. 6195 instruct loadConP_lo(iRegPdst dst, immP_NM src, iRegLdst base) %{ 6196 match(Set dst src); 6197 effect(TEMP base); 6198 6199 ins_field_const_toc_offset_hi_node(loadConP_hiNode*); 6200 6201 format %{ "LD $dst, offset, $base \t// load ptr $src from TOC (lo)" %} 6202 size(4); 6203 ins_encode %{ 6204 // TODO: PPC port $archOpcode(ppc64Opcode_ld); 6205 int offset = ra_->C->in_scratch_emit_size() ? 0 : _const_toc_offset_hi_node->_const_toc_offset; 6206 __ ld($dst$$Register, MacroAssembler::largeoffset_si16_si16_lo(offset), $base$$Register); 6207 %} 6208 ins_pipe(pipe_class_memory); 6209 %} 6210 6211 // Load pointer constant from constant table. Expand in case an 6212 // offset > 16 bit is needed. 6213 // Adlc adds toc node MachConstantTableBase. 6214 instruct loadConP_Ex(iRegPdst dst, immP src) %{ 6215 match(Set dst src); 6216 ins_cost(MEMORY_REF_COST); 6217 6218 // This rule does not use "expand" because then 6219 // the result type is not known to be an Oop. An ADLC 6220 // enhancement will be needed to make that work - not worth it! 6221 6222 // If this instruction rematerializes, it prolongs the live range 6223 // of the toc node, causing illegal graphs. 6224 // assert(edge_from_to(_reg_node[reg_lo],def)) fails in verify_good_schedule(). 6225 ins_cannot_rematerialize(true); 6226 6227 format %{ "LD $dst, offset, $constanttablebase \t// load ptr $src from table, postalloc expanded" %} 6228 postalloc_expand( postalloc_expand_load_ptr_constant(dst, src, constanttablebase) ); 6229 %} 6230 6231 // Expand node for constant pool load: small offset. 6232 instruct loadConF(regF dst, immF src, iRegLdst toc) %{ 6233 effect(DEF dst, USE src, USE toc); 6234 ins_cost(MEMORY_REF_COST); 6235 6236 ins_num_consts(1); 6237 6238 format %{ "LFS $dst, offset, $toc \t// load float $src from TOC" %} 6239 size(4); 6240 ins_encode %{ 6241 // TODO: PPC port $archOpcode(ppc64Opcode_lfs); 6242 address float_address = __ float_constant($src$$constant); 6243 __ lfs($dst$$FloatRegister, __ offset_to_method_toc(float_address), $toc$$Register); 6244 %} 6245 ins_pipe(pipe_class_memory); 6246 %} 6247 6248 // Expand node for constant pool load: large offset. 6249 instruct loadConFComp(regF dst, immF src, iRegLdst toc) %{ 6250 effect(DEF dst, USE src, USE toc); 6251 ins_cost(MEMORY_REF_COST); 6252 6253 ins_num_consts(1); 6254 6255 format %{ "ADDIS $toc, $toc, offset_hi\n\t" 6256 "LFS $dst, offset_lo, $toc \t// load float $src from TOC (hi/lo)\n\t" 6257 "ADDIS $toc, $toc, -offset_hi"%} 6258 size(12); 6259 ins_encode %{ 6260 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 6261 FloatRegister Rdst = $dst$$FloatRegister; 6262 Register Rtoc = $toc$$Register; 6263 address float_address = __ float_constant($src$$constant); 6264 int offset = __ offset_to_method_toc(float_address); 6265 int hi = (offset + (1<<15))>>16; 6266 int lo = offset - hi * (1<<16); 6267 6268 __ addis(Rtoc, Rtoc, hi); 6269 __ lfs(Rdst, lo, Rtoc); 6270 __ addis(Rtoc, Rtoc, -hi); 6271 %} 6272 ins_pipe(pipe_class_memory); 6273 %} 6274 6275 // Adlc adds toc node MachConstantTableBase. 6276 instruct loadConF_Ex(regF dst, immF src) %{ 6277 match(Set dst src); 6278 ins_cost(MEMORY_REF_COST); 6279 6280 // See loadConP. 6281 ins_cannot_rematerialize(true); 6282 6283 format %{ "LFS $dst, offset, $constanttablebase \t// load $src from table, postalloc expanded" %} 6284 postalloc_expand( postalloc_expand_load_float_constant(dst, src, constanttablebase) ); 6285 %} 6286 6287 // Expand node for constant pool load: small offset. 6288 instruct loadConD(regD dst, immD src, iRegLdst toc) %{ 6289 effect(DEF dst, USE src, USE toc); 6290 ins_cost(MEMORY_REF_COST); 6291 6292 ins_num_consts(1); 6293 6294 format %{ "LFD $dst, offset, $toc \t// load double $src from TOC" %} 6295 size(4); 6296 ins_encode %{ 6297 // TODO: PPC port $archOpcode(ppc64Opcode_lfd); 6298 int offset = __ offset_to_method_toc(__ double_constant($src$$constant)); 6299 __ lfd($dst$$FloatRegister, offset, $toc$$Register); 6300 %} 6301 ins_pipe(pipe_class_memory); 6302 %} 6303 6304 // Expand node for constant pool load: large offset. 6305 instruct loadConDComp(regD dst, immD src, iRegLdst toc) %{ 6306 effect(DEF dst, USE src, USE toc); 6307 ins_cost(MEMORY_REF_COST); 6308 6309 ins_num_consts(1); 6310 6311 format %{ "ADDIS $toc, $toc, offset_hi\n\t" 6312 "LFD $dst, offset_lo, $toc \t// load double $src from TOC (hi/lo)\n\t" 6313 "ADDIS $toc, $toc, -offset_hi" %} 6314 size(12); 6315 ins_encode %{ 6316 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 6317 FloatRegister Rdst = $dst$$FloatRegister; 6318 Register Rtoc = $toc$$Register; 6319 address float_address = __ double_constant($src$$constant); 6320 int offset = __ offset_to_method_toc(float_address); 6321 int hi = (offset + (1<<15))>>16; 6322 int lo = offset - hi * (1<<16); 6323 6324 __ addis(Rtoc, Rtoc, hi); 6325 __ lfd(Rdst, lo, Rtoc); 6326 __ addis(Rtoc, Rtoc, -hi); 6327 %} 6328 ins_pipe(pipe_class_memory); 6329 %} 6330 6331 // Adlc adds toc node MachConstantTableBase. 6332 instruct loadConD_Ex(regD dst, immD src) %{ 6333 match(Set dst src); 6334 ins_cost(MEMORY_REF_COST); 6335 6336 // See loadConP. 6337 ins_cannot_rematerialize(true); 6338 6339 format %{ "ConD $dst, offset, $constanttablebase \t// load $src from table, postalloc expanded" %} 6340 postalloc_expand( postalloc_expand_load_double_constant(dst, src, constanttablebase) ); 6341 %} 6342 6343 // Prefetch instructions. 6344 // Must be safe to execute with invalid address (cannot fault). 6345 6346 instruct prefetchr(indirectMemory mem, iRegLsrc src) %{ 6347 match(PrefetchRead (AddP mem src)); 6348 ins_cost(MEMORY_REF_COST); 6349 6350 format %{ "PREFETCH $mem, 0, $src \t// Prefetch read-many" %} 6351 size(4); 6352 ins_encode %{ 6353 // TODO: PPC port $archOpcode(ppc64Opcode_dcbt); 6354 __ dcbt($src$$Register, $mem$$base$$Register); 6355 %} 6356 ins_pipe(pipe_class_memory); 6357 %} 6358 6359 instruct prefetchr_no_offset(indirectMemory mem) %{ 6360 match(PrefetchRead mem); 6361 ins_cost(MEMORY_REF_COST); 6362 6363 format %{ "PREFETCH $mem" %} 6364 size(4); 6365 ins_encode %{ 6366 // TODO: PPC port $archOpcode(ppc64Opcode_dcbt); 6367 __ dcbt($mem$$base$$Register); 6368 %} 6369 ins_pipe(pipe_class_memory); 6370 %} 6371 6372 instruct prefetchw(indirectMemory mem, iRegLsrc src) %{ 6373 match(PrefetchWrite (AddP mem src)); 6374 ins_cost(MEMORY_REF_COST); 6375 6376 format %{ "PREFETCH $mem, 2, $src \t// Prefetch write-many (and read)" %} 6377 size(4); 6378 ins_encode %{ 6379 // TODO: PPC port $archOpcode(ppc64Opcode_dcbtst); 6380 __ dcbtst($src$$Register, $mem$$base$$Register); 6381 %} 6382 ins_pipe(pipe_class_memory); 6383 %} 6384 6385 instruct prefetchw_no_offset(indirectMemory mem) %{ 6386 match(PrefetchWrite mem); 6387 ins_cost(MEMORY_REF_COST); 6388 6389 format %{ "PREFETCH $mem" %} 6390 size(4); 6391 ins_encode %{ 6392 // TODO: PPC port $archOpcode(ppc64Opcode_dcbtst); 6393 __ dcbtst($mem$$base$$Register); 6394 %} 6395 ins_pipe(pipe_class_memory); 6396 %} 6397 6398 // Special prefetch versions which use the dcbz instruction. 6399 instruct prefetch_alloc_zero(indirectMemory mem, iRegLsrc src) %{ 6400 match(PrefetchAllocation (AddP mem src)); 6401 predicate(AllocatePrefetchStyle == 3); 6402 ins_cost(MEMORY_REF_COST); 6403 6404 format %{ "PREFETCH $mem, 2, $src \t// Prefetch write-many with zero" %} 6405 size(4); 6406 ins_encode %{ 6407 // TODO: PPC port $archOpcode(ppc64Opcode_dcbtst); 6408 __ dcbz($src$$Register, $mem$$base$$Register); 6409 %} 6410 ins_pipe(pipe_class_memory); 6411 %} 6412 6413 instruct prefetch_alloc_zero_no_offset(indirectMemory mem) %{ 6414 match(PrefetchAllocation mem); 6415 predicate(AllocatePrefetchStyle == 3); 6416 ins_cost(MEMORY_REF_COST); 6417 6418 format %{ "PREFETCH $mem, 2 \t// Prefetch write-many with zero" %} 6419 size(4); 6420 ins_encode %{ 6421 // TODO: PPC port $archOpcode(ppc64Opcode_dcbtst); 6422 __ dcbz($mem$$base$$Register); 6423 %} 6424 ins_pipe(pipe_class_memory); 6425 %} 6426 6427 instruct prefetch_alloc(indirectMemory mem, iRegLsrc src) %{ 6428 match(PrefetchAllocation (AddP mem src)); 6429 predicate(AllocatePrefetchStyle != 3); 6430 ins_cost(MEMORY_REF_COST); 6431 6432 format %{ "PREFETCH $mem, 2, $src \t// Prefetch write-many" %} 6433 size(4); 6434 ins_encode %{ 6435 // TODO: PPC port $archOpcode(ppc64Opcode_dcbtst); 6436 __ dcbtst($src$$Register, $mem$$base$$Register); 6437 %} 6438 ins_pipe(pipe_class_memory); 6439 %} 6440 6441 instruct prefetch_alloc_no_offset(indirectMemory mem) %{ 6442 match(PrefetchAllocation mem); 6443 predicate(AllocatePrefetchStyle != 3); 6444 ins_cost(MEMORY_REF_COST); 6445 6446 format %{ "PREFETCH $mem, 2 \t// Prefetch write-many" %} 6447 size(4); 6448 ins_encode %{ 6449 // TODO: PPC port $archOpcode(ppc64Opcode_dcbtst); 6450 __ dcbtst($mem$$base$$Register); 6451 %} 6452 ins_pipe(pipe_class_memory); 6453 %} 6454 6455 //----------Store Instructions------------------------------------------------- 6456 6457 // Store Byte 6458 instruct storeB(memory mem, iRegIsrc src) %{ 6459 match(Set mem (StoreB mem src)); 6460 ins_cost(MEMORY_REF_COST); 6461 6462 format %{ "STB $src, $mem \t// byte" %} 6463 size(4); 6464 ins_encode %{ 6465 // TODO: PPC port $archOpcode(ppc64Opcode_stb); 6466 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); 6467 __ stb($src$$Register, Idisp, $mem$$base$$Register); 6468 %} 6469 ins_pipe(pipe_class_memory); 6470 %} 6471 6472 // Store Char/Short 6473 instruct storeC(memory mem, iRegIsrc src) %{ 6474 match(Set mem (StoreC mem src)); 6475 ins_cost(MEMORY_REF_COST); 6476 6477 format %{ "STH $src, $mem \t// short" %} 6478 size(4); 6479 ins_encode %{ 6480 // TODO: PPC port $archOpcode(ppc64Opcode_sth); 6481 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); 6482 __ sth($src$$Register, Idisp, $mem$$base$$Register); 6483 %} 6484 ins_pipe(pipe_class_memory); 6485 %} 6486 6487 // Store Integer 6488 instruct storeI(memory mem, iRegIsrc src) %{ 6489 match(Set mem (StoreI mem src)); 6490 ins_cost(MEMORY_REF_COST); 6491 6492 format %{ "STW $src, $mem" %} 6493 size(4); 6494 ins_encode( enc_stw(src, mem) ); 6495 ins_pipe(pipe_class_memory); 6496 %} 6497 6498 // ConvL2I + StoreI. 6499 instruct storeI_convL2I(memory mem, iRegLsrc src) %{ 6500 match(Set mem (StoreI mem (ConvL2I src))); 6501 ins_cost(MEMORY_REF_COST); 6502 6503 format %{ "STW l2i($src), $mem" %} 6504 size(4); 6505 ins_encode( enc_stw(src, mem) ); 6506 ins_pipe(pipe_class_memory); 6507 %} 6508 6509 // Store Long 6510 instruct storeL(memoryAlg4 mem, iRegLsrc src) %{ 6511 match(Set mem (StoreL mem src)); 6512 ins_cost(MEMORY_REF_COST); 6513 6514 format %{ "STD $src, $mem \t// long" %} 6515 size(4); 6516 ins_encode( enc_std(src, mem) ); 6517 ins_pipe(pipe_class_memory); 6518 %} 6519 6520 // Store super word nodes. 6521 6522 // Store Aligned Packed Byte long register to memory 6523 instruct storeA8B(memoryAlg4 mem, iRegLsrc src) %{ 6524 predicate(n->as_StoreVector()->memory_size() == 8); 6525 match(Set mem (StoreVector mem src)); 6526 ins_cost(MEMORY_REF_COST); 6527 6528 format %{ "STD $mem, $src \t// packed8B" %} 6529 size(4); 6530 ins_encode( enc_std(src, mem) ); 6531 ins_pipe(pipe_class_memory); 6532 %} 6533 6534 // Store Compressed Oop 6535 instruct storeN(memory dst, iRegN_P2N src) %{ 6536 match(Set dst (StoreN dst src)); 6537 ins_cost(MEMORY_REF_COST); 6538 6539 format %{ "STW $src, $dst \t// compressed oop" %} 6540 size(4); 6541 ins_encode( enc_stw(src, dst) ); 6542 ins_pipe(pipe_class_memory); 6543 %} 6544 6545 // Store Compressed KLass 6546 instruct storeNKlass(memory dst, iRegN_P2N src) %{ 6547 match(Set dst (StoreNKlass dst src)); 6548 ins_cost(MEMORY_REF_COST); 6549 6550 format %{ "STW $src, $dst \t// compressed klass" %} 6551 size(4); 6552 ins_encode( enc_stw(src, dst) ); 6553 ins_pipe(pipe_class_memory); 6554 %} 6555 6556 // Store Pointer 6557 instruct storeP(memoryAlg4 dst, iRegPsrc src) %{ 6558 match(Set dst (StoreP dst src)); 6559 ins_cost(MEMORY_REF_COST); 6560 6561 format %{ "STD $src, $dst \t// ptr" %} 6562 size(4); 6563 ins_encode( enc_std(src, dst) ); 6564 ins_pipe(pipe_class_memory); 6565 %} 6566 6567 // Store Float 6568 instruct storeF(memory mem, regF src) %{ 6569 match(Set mem (StoreF mem src)); 6570 ins_cost(MEMORY_REF_COST); 6571 6572 format %{ "STFS $src, $mem" %} 6573 size(4); 6574 ins_encode( enc_stfs(src, mem) ); 6575 ins_pipe(pipe_class_memory); 6576 %} 6577 6578 // Store Double 6579 instruct storeD(memory mem, regD src) %{ 6580 match(Set mem (StoreD mem src)); 6581 ins_cost(MEMORY_REF_COST); 6582 6583 format %{ "STFD $src, $mem" %} 6584 size(4); 6585 ins_encode( enc_stfd(src, mem) ); 6586 ins_pipe(pipe_class_memory); 6587 %} 6588 6589 //----------Store Instructions With Zeros-------------------------------------- 6590 6591 // Card-mark for CMS garbage collection. 6592 // This cardmark does an optimization so that it must not always 6593 // do a releasing store. For this, it gets the address of 6594 // CMSCollectorCardTableModRefBSExt::_requires_release as input. 6595 // (Using releaseFieldAddr in the match rule is a hack.) 6596 instruct storeCM_CMS(memory mem, iRegLdst releaseFieldAddr) %{ 6597 match(Set mem (StoreCM mem releaseFieldAddr)); 6598 predicate(false); 6599 ins_cost(MEMORY_REF_COST); 6600 6601 // See loadConP. 6602 ins_cannot_rematerialize(true); 6603 6604 format %{ "STB #0, $mem \t// CMS card-mark byte (must be 0!), checking requires_release in [$releaseFieldAddr]" %} 6605 ins_encode( enc_cms_card_mark(mem, releaseFieldAddr) ); 6606 ins_pipe(pipe_class_memory); 6607 %} 6608 6609 // Card-mark for CMS garbage collection. 6610 // This cardmark does an optimization so that it must not always 6611 // do a releasing store. For this, it needs the constant address of 6612 // CMSCollectorCardTableModRefBSExt::_requires_release. 6613 // This constant address is split off here by expand so we can use 6614 // adlc / matcher functionality to load it from the constant section. 6615 instruct storeCM_CMS_ExEx(memory mem, immI_0 zero) %{ 6616 match(Set mem (StoreCM mem zero)); 6617 predicate(UseConcMarkSweepGC); 6618 6619 expand %{ 6620 immL baseImm %{ 0 /* TODO: PPC port (jlong)CMSCollectorCardTableModRefBSExt::requires_release_address() */ %} 6621 iRegLdst releaseFieldAddress; 6622 loadConL_Ex(releaseFieldAddress, baseImm); 6623 storeCM_CMS(mem, releaseFieldAddress); 6624 %} 6625 %} 6626 6627 instruct storeCM_G1(memory mem, immI_0 zero) %{ 6628 match(Set mem (StoreCM mem zero)); 6629 predicate(UseG1GC); 6630 ins_cost(MEMORY_REF_COST); 6631 6632 ins_cannot_rematerialize(true); 6633 6634 format %{ "STB #0, $mem \t// CMS card-mark byte store (G1)" %} 6635 size(8); 6636 ins_encode %{ 6637 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 6638 __ li(R0, 0); 6639 //__ release(); // G1: oops are allowed to get visible after dirty marking 6640 guarantee($mem$$base$$Register != R1_SP, "use frame_slots_bias"); 6641 __ stb(R0, $mem$$disp, $mem$$base$$Register); 6642 %} 6643 ins_pipe(pipe_class_memory); 6644 %} 6645 6646 // Convert oop pointer into compressed form. 6647 6648 // Nodes for postalloc expand. 6649 6650 // Shift node for expand. 6651 instruct encodeP_shift(iRegNdst dst, iRegNsrc src) %{ 6652 // The match rule is needed to make it a 'MachTypeNode'! 6653 match(Set dst (EncodeP src)); 6654 predicate(false); 6655 6656 format %{ "SRDI $dst, $src, 3 \t// encode" %} 6657 size(4); 6658 ins_encode %{ 6659 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl); 6660 __ srdi($dst$$Register, $src$$Register, Universe::narrow_oop_shift() & 0x3f); 6661 %} 6662 ins_pipe(pipe_class_default); 6663 %} 6664 6665 // Add node for expand. 6666 instruct encodeP_sub(iRegPdst dst, iRegPdst src) %{ 6667 // The match rule is needed to make it a 'MachTypeNode'! 6668 match(Set dst (EncodeP src)); 6669 predicate(false); 6670 6671 format %{ "SUB $dst, $src, oop_base \t// encode" %} 6672 size(4); 6673 ins_encode %{ 6674 // TODO: PPC port $archOpcode(ppc64Opcode_subf); 6675 __ subf($dst$$Register, R30, $src$$Register); 6676 %} 6677 ins_pipe(pipe_class_default); 6678 %} 6679 6680 // Conditional sub base. 6681 instruct cond_sub_base(iRegNdst dst, flagsReg crx, iRegPsrc src1) %{ 6682 // The match rule is needed to make it a 'MachTypeNode'! 6683 match(Set dst (EncodeP (Binary crx src1))); 6684 predicate(false); 6685 6686 ins_variable_size_depending_on_alignment(true); 6687 6688 format %{ "BEQ $crx, done\n\t" 6689 "SUB $dst, $src1, R30 \t// encode: subtract base if != NULL\n" 6690 "done:" %} 6691 size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8); 6692 ins_encode %{ 6693 // TODO: PPC port $archOpcode(ppc64Opcode_cmove); 6694 Label done; 6695 __ beq($crx$$CondRegister, done); 6696 __ subf($dst$$Register, R30, $src1$$Register); 6697 // TODO PPC port __ endgroup_if_needed(_size == 12); 6698 __ bind(done); 6699 %} 6700 ins_pipe(pipe_class_default); 6701 %} 6702 6703 // Power 7 can use isel instruction 6704 instruct cond_set_0_oop(iRegNdst dst, flagsReg crx, iRegPsrc src1) %{ 6705 // The match rule is needed to make it a 'MachTypeNode'! 6706 match(Set dst (EncodeP (Binary crx src1))); 6707 predicate(false); 6708 6709 format %{ "CMOVE $dst, $crx eq, 0, $src1 \t// encode: preserve 0" %} 6710 size(4); 6711 ins_encode %{ 6712 // This is a Power7 instruction for which no machine description exists. 6713 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 6714 __ isel_0($dst$$Register, $crx$$CondRegister, Assembler::equal, $src1$$Register); 6715 %} 6716 ins_pipe(pipe_class_default); 6717 %} 6718 6719 // base != 0 6720 // 32G aligned narrow oop base. 6721 instruct encodeP_32GAligned(iRegNdst dst, iRegPsrc src) %{ 6722 match(Set dst (EncodeP src)); 6723 predicate(false /* TODO: PPC port Universe::narrow_oop_base_disjoint()*/); 6724 6725 format %{ "EXTRDI $dst, $src, #32, #3 \t// encode with 32G aligned base" %} 6726 size(4); 6727 ins_encode %{ 6728 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl); 6729 __ rldicl($dst$$Register, $src$$Register, 64-Universe::narrow_oop_shift(), 32); 6730 %} 6731 ins_pipe(pipe_class_default); 6732 %} 6733 6734 // shift != 0, base != 0 6735 instruct encodeP_Ex(iRegNdst dst, flagsReg crx, iRegPsrc src) %{ 6736 match(Set dst (EncodeP src)); 6737 effect(TEMP crx); 6738 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull && 6739 Universe::narrow_oop_shift() != 0 && 6740 true /* TODO: PPC port Universe::narrow_oop_base_overlaps()*/); 6741 6742 format %{ "EncodeP $dst, $crx, $src \t// postalloc expanded" %} 6743 postalloc_expand( postalloc_expand_encode_oop(dst, src, crx)); 6744 %} 6745 6746 // shift != 0, base != 0 6747 instruct encodeP_not_null_Ex(iRegNdst dst, iRegPsrc src) %{ 6748 match(Set dst (EncodeP src)); 6749 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull && 6750 Universe::narrow_oop_shift() != 0 && 6751 true /* TODO: PPC port Universe::narrow_oop_base_overlaps()*/); 6752 6753 format %{ "EncodeP $dst, $src\t// $src != Null, postalloc expanded" %} 6754 postalloc_expand( postalloc_expand_encode_oop_not_null(dst, src) ); 6755 %} 6756 6757 // shift != 0, base == 0 6758 // TODO: This is the same as encodeP_shift. Merge! 6759 instruct encodeP_not_null_base_null(iRegNdst dst, iRegPsrc src) %{ 6760 match(Set dst (EncodeP src)); 6761 predicate(Universe::narrow_oop_shift() != 0 && 6762 Universe::narrow_oop_base() ==0); 6763 6764 format %{ "SRDI $dst, $src, #3 \t// encodeP, $src != NULL" %} 6765 size(4); 6766 ins_encode %{ 6767 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl); 6768 __ srdi($dst$$Register, $src$$Register, Universe::narrow_oop_shift() & 0x3f); 6769 %} 6770 ins_pipe(pipe_class_default); 6771 %} 6772 6773 // Compressed OOPs with narrow_oop_shift == 0. 6774 // shift == 0, base == 0 6775 instruct encodeP_narrow_oop_shift_0(iRegNdst dst, iRegPsrc src) %{ 6776 match(Set dst (EncodeP src)); 6777 predicate(Universe::narrow_oop_shift() == 0); 6778 6779 format %{ "MR $dst, $src \t// Ptr->Narrow" %} 6780 // variable size, 0 or 4. 6781 ins_encode %{ 6782 // TODO: PPC port $archOpcode(ppc64Opcode_or); 6783 __ mr_if_needed($dst$$Register, $src$$Register); 6784 %} 6785 ins_pipe(pipe_class_default); 6786 %} 6787 6788 // Decode nodes. 6789 6790 // Shift node for expand. 6791 instruct decodeN_shift(iRegPdst dst, iRegPsrc src) %{ 6792 // The match rule is needed to make it a 'MachTypeNode'! 6793 match(Set dst (DecodeN src)); 6794 predicate(false); 6795 6796 format %{ "SLDI $dst, $src, #3 \t// DecodeN" %} 6797 size(4); 6798 ins_encode %{ 6799 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr); 6800 __ sldi($dst$$Register, $src$$Register, Universe::narrow_oop_shift()); 6801 %} 6802 ins_pipe(pipe_class_default); 6803 %} 6804 6805 // Add node for expand. 6806 instruct decodeN_add(iRegPdst dst, iRegPdst src) %{ 6807 // The match rule is needed to make it a 'MachTypeNode'! 6808 match(Set dst (DecodeN src)); 6809 predicate(false); 6810 6811 format %{ "ADD $dst, $src, R30 \t// DecodeN, add oop base" %} 6812 size(4); 6813 ins_encode %{ 6814 // TODO: PPC port $archOpcode(ppc64Opcode_add); 6815 __ add($dst$$Register, $src$$Register, R30); 6816 %} 6817 ins_pipe(pipe_class_default); 6818 %} 6819 6820 // conditianal add base for expand 6821 instruct cond_add_base(iRegPdst dst, flagsReg crx, iRegPsrc src1) %{ 6822 // The match rule is needed to make it a 'MachTypeNode'! 6823 // NOTICE that the rule is nonsense - we just have to make sure that: 6824 // - _matrule->_rChild->_opType == "DecodeN" (see InstructForm::captures_bottom_type() in formssel.cpp) 6825 // - we have to match 'crx' to avoid an "illegal USE of non-input: flagsReg crx" error in ADLC. 6826 match(Set dst (DecodeN (Binary crx src1))); 6827 predicate(false); 6828 6829 ins_variable_size_depending_on_alignment(true); 6830 6831 format %{ "BEQ $crx, done\n\t" 6832 "ADD $dst, $src1, R30 \t// DecodeN: add oop base if $src1 != NULL\n" 6833 "done:" %} 6834 size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling()) */? 12 : 8); 6835 ins_encode %{ 6836 // TODO: PPC port $archOpcode(ppc64Opcode_cmove); 6837 Label done; 6838 __ beq($crx$$CondRegister, done); 6839 __ add($dst$$Register, $src1$$Register, R30); 6840 // TODO PPC port __ endgroup_if_needed(_size == 12); 6841 __ bind(done); 6842 %} 6843 ins_pipe(pipe_class_default); 6844 %} 6845 6846 instruct cond_set_0_ptr(iRegPdst dst, flagsReg crx, iRegPsrc src1) %{ 6847 // The match rule is needed to make it a 'MachTypeNode'! 6848 // NOTICE that the rule is nonsense - we just have to make sure that: 6849 // - _matrule->_rChild->_opType == "DecodeN" (see InstructForm::captures_bottom_type() in formssel.cpp) 6850 // - we have to match 'crx' to avoid an "illegal USE of non-input: flagsReg crx" error in ADLC. 6851 match(Set dst (DecodeN (Binary crx src1))); 6852 predicate(false); 6853 6854 format %{ "CMOVE $dst, $crx eq, 0, $src1 \t// decode: preserve 0" %} 6855 size(4); 6856 ins_encode %{ 6857 // This is a Power7 instruction for which no machine description exists. 6858 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 6859 __ isel_0($dst$$Register, $crx$$CondRegister, Assembler::equal, $src1$$Register); 6860 %} 6861 ins_pipe(pipe_class_default); 6862 %} 6863 6864 // shift != 0, base != 0 6865 instruct decodeN_Ex(iRegPdst dst, iRegNsrc src, flagsReg crx) %{ 6866 match(Set dst (DecodeN src)); 6867 predicate((n->bottom_type()->is_oopptr()->ptr() != TypePtr::NotNull && 6868 n->bottom_type()->is_oopptr()->ptr() != TypePtr::Constant) && 6869 Universe::narrow_oop_shift() != 0 && 6870 Universe::narrow_oop_base() != 0); 6871 effect(TEMP crx); 6872 6873 format %{ "DecodeN $dst, $src \t// Kills $crx, postalloc expanded" %} 6874 postalloc_expand( postalloc_expand_decode_oop(dst, src, crx) ); 6875 %} 6876 6877 // shift != 0, base == 0 6878 instruct decodeN_nullBase(iRegPdst dst, iRegNsrc src) %{ 6879 match(Set dst (DecodeN src)); 6880 predicate(Universe::narrow_oop_shift() != 0 && 6881 Universe::narrow_oop_base() == 0); 6882 6883 format %{ "SLDI $dst, $src, #3 \t// DecodeN (zerobased)" %} 6884 size(4); 6885 ins_encode %{ 6886 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr); 6887 __ sldi($dst$$Register, $src$$Register, Universe::narrow_oop_shift()); 6888 %} 6889 ins_pipe(pipe_class_default); 6890 %} 6891 6892 // src != 0, shift != 0, base != 0 6893 instruct decodeN_notNull_addBase_Ex(iRegPdst dst, iRegNsrc src) %{ 6894 match(Set dst (DecodeN src)); 6895 predicate((n->bottom_type()->is_oopptr()->ptr() == TypePtr::NotNull || 6896 n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant) && 6897 Universe::narrow_oop_shift() != 0 && 6898 Universe::narrow_oop_base() != 0); 6899 6900 format %{ "DecodeN $dst, $src \t// $src != NULL, postalloc expanded" %} 6901 postalloc_expand( postalloc_expand_decode_oop_not_null(dst, src)); 6902 %} 6903 6904 // Compressed OOPs with narrow_oop_shift == 0. 6905 instruct decodeN_unscaled(iRegPdst dst, iRegNsrc src) %{ 6906 match(Set dst (DecodeN src)); 6907 predicate(Universe::narrow_oop_shift() == 0); 6908 ins_cost(DEFAULT_COST); 6909 6910 format %{ "MR $dst, $src \t// DecodeN (unscaled)" %} 6911 // variable size, 0 or 4. 6912 ins_encode %{ 6913 // TODO: PPC port $archOpcode(ppc64Opcode_or); 6914 __ mr_if_needed($dst$$Register, $src$$Register); 6915 %} 6916 ins_pipe(pipe_class_default); 6917 %} 6918 6919 // Convert compressed oop into int for vectors alignment masking. 6920 instruct decodeN2I_unscaled(iRegIdst dst, iRegNsrc src) %{ 6921 match(Set dst (ConvL2I (CastP2X (DecodeN src)))); 6922 predicate(Universe::narrow_oop_shift() == 0); 6923 ins_cost(DEFAULT_COST); 6924 6925 format %{ "MR $dst, $src \t// (int)DecodeN (unscaled)" %} 6926 // variable size, 0 or 4. 6927 ins_encode %{ 6928 // TODO: PPC port $archOpcode(ppc64Opcode_or); 6929 __ mr_if_needed($dst$$Register, $src$$Register); 6930 %} 6931 ins_pipe(pipe_class_default); 6932 %} 6933 6934 // Convert klass pointer into compressed form. 6935 6936 // Nodes for postalloc expand. 6937 6938 // Shift node for expand. 6939 instruct encodePKlass_shift(iRegNdst dst, iRegNsrc src) %{ 6940 // The match rule is needed to make it a 'MachTypeNode'! 6941 match(Set dst (EncodePKlass src)); 6942 predicate(false); 6943 6944 format %{ "SRDI $dst, $src, 3 \t// encode" %} 6945 size(4); 6946 ins_encode %{ 6947 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl); 6948 __ srdi($dst$$Register, $src$$Register, Universe::narrow_klass_shift()); 6949 %} 6950 ins_pipe(pipe_class_default); 6951 %} 6952 6953 // Add node for expand. 6954 instruct encodePKlass_sub_base(iRegPdst dst, iRegLsrc base, iRegPdst src) %{ 6955 // The match rule is needed to make it a 'MachTypeNode'! 6956 match(Set dst (EncodePKlass (Binary base src))); 6957 predicate(false); 6958 6959 format %{ "SUB $dst, $base, $src \t// encode" %} 6960 size(4); 6961 ins_encode %{ 6962 // TODO: PPC port $archOpcode(ppc64Opcode_subf); 6963 __ subf($dst$$Register, $base$$Register, $src$$Register); 6964 %} 6965 ins_pipe(pipe_class_default); 6966 %} 6967 6968 // base != 0 6969 // 32G aligned narrow oop base. 6970 instruct encodePKlass_32GAligned(iRegNdst dst, iRegPsrc src) %{ 6971 match(Set dst (EncodePKlass src)); 6972 predicate(false /* TODO: PPC port Universe::narrow_klass_base_disjoint()*/); 6973 6974 format %{ "EXTRDI $dst, $src, #32, #3 \t// encode with 32G aligned base" %} 6975 size(4); 6976 ins_encode %{ 6977 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl); 6978 __ rldicl($dst$$Register, $src$$Register, 64-Universe::narrow_oop_shift(), 32); 6979 %} 6980 ins_pipe(pipe_class_default); 6981 %} 6982 6983 // shift != 0, base != 0 6984 instruct encodePKlass_not_null_Ex(iRegNdst dst, iRegLsrc base, iRegPsrc src) %{ 6985 match(Set dst (EncodePKlass (Binary base src))); 6986 predicate(false); 6987 6988 format %{ "EncodePKlass $dst, $src\t// $src != Null, postalloc expanded" %} 6989 postalloc_expand %{ 6990 encodePKlass_sub_baseNode *n1 = encodePKlass_sub_baseNode(); 6991 n1->add_req(n_region, n_base, n_src); 6992 n1->_opnds[0] = op_dst; 6993 n1->_opnds[1] = op_base; 6994 n1->_opnds[2] = op_src; 6995 n1->_bottom_type = _bottom_type; 6996 6997 encodePKlass_shiftNode *n2 = encodePKlass_shiftNode(); 6998 n2->add_req(n_region, n1); 6999 n2->_opnds[0] = op_dst; 7000 n2->_opnds[1] = op_dst; 7001 n2->_bottom_type = _bottom_type; 7002 ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 7003 ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 7004 7005 nodes->push(n1); 7006 nodes->push(n2); 7007 %} 7008 %} 7009 7010 // shift != 0, base != 0 7011 instruct encodePKlass_not_null_ExEx(iRegNdst dst, iRegPsrc src) %{ 7012 match(Set dst (EncodePKlass src)); 7013 //predicate(Universe::narrow_klass_shift() != 0 && 7014 // true /* TODO: PPC port Universe::narrow_klass_base_overlaps()*/); 7015 7016 //format %{ "EncodePKlass $dst, $src\t// $src != Null, postalloc expanded" %} 7017 ins_cost(DEFAULT_COST*2); // Don't count constant. 7018 expand %{ 7019 immL baseImm %{ (jlong)(intptr_t)Universe::narrow_klass_base() %} 7020 iRegLdst base; 7021 loadConL_Ex(base, baseImm); 7022 encodePKlass_not_null_Ex(dst, base, src); 7023 %} 7024 %} 7025 7026 // Decode nodes. 7027 7028 // Shift node for expand. 7029 instruct decodeNKlass_shift(iRegPdst dst, iRegPsrc src) %{ 7030 // The match rule is needed to make it a 'MachTypeNode'! 7031 match(Set dst (DecodeNKlass src)); 7032 predicate(false); 7033 7034 format %{ "SLDI $dst, $src, #3 \t// DecodeNKlass" %} 7035 size(4); 7036 ins_encode %{ 7037 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr); 7038 __ sldi($dst$$Register, $src$$Register, Universe::narrow_klass_shift()); 7039 %} 7040 ins_pipe(pipe_class_default); 7041 %} 7042 7043 // Add node for expand. 7044 7045 instruct decodeNKlass_add_base(iRegPdst dst, iRegLsrc base, iRegPdst src) %{ 7046 // The match rule is needed to make it a 'MachTypeNode'! 7047 match(Set dst (DecodeNKlass (Binary base src))); 7048 predicate(false); 7049 7050 format %{ "ADD $dst, $base, $src \t// DecodeNKlass, add klass base" %} 7051 size(4); 7052 ins_encode %{ 7053 // TODO: PPC port $archOpcode(ppc64Opcode_add); 7054 __ add($dst$$Register, $base$$Register, $src$$Register); 7055 %} 7056 ins_pipe(pipe_class_default); 7057 %} 7058 7059 // src != 0, shift != 0, base != 0 7060 instruct decodeNKlass_notNull_addBase_Ex(iRegPdst dst, iRegLsrc base, iRegNsrc src) %{ 7061 match(Set dst (DecodeNKlass (Binary base src))); 7062 //effect(kill src); // We need a register for the immediate result after shifting. 7063 predicate(false); 7064 7065 format %{ "DecodeNKlass $dst = $base + ($src << 3) \t// $src != NULL, postalloc expanded" %} 7066 postalloc_expand %{ 7067 decodeNKlass_add_baseNode *n1 = decodeNKlass_add_baseNode(); 7068 n1->add_req(n_region, n_base, n_src); 7069 n1->_opnds[0] = op_dst; 7070 n1->_opnds[1] = op_base; 7071 n1->_opnds[2] = op_src; 7072 n1->_bottom_type = _bottom_type; 7073 7074 decodeNKlass_shiftNode *n2 = decodeNKlass_shiftNode(); 7075 n2->add_req(n_region, n1); 7076 n2->_opnds[0] = op_dst; 7077 n2->_opnds[1] = op_dst; 7078 n2->_bottom_type = _bottom_type; 7079 7080 ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 7081 ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 7082 7083 nodes->push(n1); 7084 nodes->push(n2); 7085 %} 7086 %} 7087 7088 // src != 0, shift != 0, base != 0 7089 instruct decodeNKlass_notNull_addBase_ExEx(iRegPdst dst, iRegNsrc src) %{ 7090 match(Set dst (DecodeNKlass src)); 7091 // predicate(Universe::narrow_klass_shift() != 0 && 7092 // Universe::narrow_klass_base() != 0); 7093 7094 //format %{ "DecodeNKlass $dst, $src \t// $src != NULL, expanded" %} 7095 7096 ins_cost(DEFAULT_COST*2); // Don't count constant. 7097 expand %{ 7098 // We add first, then we shift. Like this, we can get along with one register less. 7099 // But we have to load the base pre-shifted. 7100 immL baseImm %{ (jlong)((intptr_t)Universe::narrow_klass_base() >> Universe::narrow_klass_shift()) %} 7101 iRegLdst base; 7102 loadConL_Ex(base, baseImm); 7103 decodeNKlass_notNull_addBase_Ex(dst, base, src); 7104 %} 7105 %} 7106 7107 //----------MemBar Instructions----------------------------------------------- 7108 // Memory barrier flavors 7109 7110 instruct membar_acquire() %{ 7111 match(LoadFence); 7112 ins_cost(4*MEMORY_REF_COST); 7113 7114 format %{ "MEMBAR-acquire" %} 7115 size(4); 7116 ins_encode %{ 7117 // TODO: PPC port $archOpcode(ppc64Opcode_lwsync); 7118 __ acquire(); 7119 %} 7120 ins_pipe(pipe_class_default); 7121 %} 7122 7123 instruct unnecessary_membar_acquire() %{ 7124 match(MemBarAcquire); 7125 ins_cost(0); 7126 7127 format %{ " -- \t// redundant MEMBAR-acquire - empty" %} 7128 size(0); 7129 ins_encode( /*empty*/ ); 7130 ins_pipe(pipe_class_default); 7131 %} 7132 7133 instruct membar_acquire_lock() %{ 7134 match(MemBarAcquireLock); 7135 ins_cost(0); 7136 7137 format %{ " -- \t// redundant MEMBAR-acquire - empty (acquire as part of CAS in prior FastLock)" %} 7138 size(0); 7139 ins_encode( /*empty*/ ); 7140 ins_pipe(pipe_class_default); 7141 %} 7142 7143 instruct membar_release() %{ 7144 match(MemBarRelease); 7145 match(StoreFence); 7146 ins_cost(4*MEMORY_REF_COST); 7147 7148 format %{ "MEMBAR-release" %} 7149 size(4); 7150 ins_encode %{ 7151 // TODO: PPC port $archOpcode(ppc64Opcode_lwsync); 7152 __ release(); 7153 %} 7154 ins_pipe(pipe_class_default); 7155 %} 7156 7157 instruct membar_storestore() %{ 7158 match(MemBarStoreStore); 7159 ins_cost(4*MEMORY_REF_COST); 7160 7161 format %{ "MEMBAR-store-store" %} 7162 size(4); 7163 ins_encode %{ 7164 // TODO: PPC port $archOpcode(ppc64Opcode_lwsync); 7165 __ membar(Assembler::StoreStore); 7166 %} 7167 ins_pipe(pipe_class_default); 7168 %} 7169 7170 instruct membar_release_lock() %{ 7171 match(MemBarReleaseLock); 7172 ins_cost(0); 7173 7174 format %{ " -- \t// redundant MEMBAR-release - empty (release in FastUnlock)" %} 7175 size(0); 7176 ins_encode( /*empty*/ ); 7177 ins_pipe(pipe_class_default); 7178 %} 7179 7180 instruct membar_volatile() %{ 7181 match(MemBarVolatile); 7182 ins_cost(4*MEMORY_REF_COST); 7183 7184 format %{ "MEMBAR-volatile" %} 7185 size(4); 7186 ins_encode %{ 7187 // TODO: PPC port $archOpcode(ppc64Opcode_sync); 7188 __ fence(); 7189 %} 7190 ins_pipe(pipe_class_default); 7191 %} 7192 7193 // This optimization is wrong on PPC. The following pattern is not supported: 7194 // MemBarVolatile 7195 // ^ ^ 7196 // | | 7197 // CtrlProj MemProj 7198 // ^ ^ 7199 // | | 7200 // | Load 7201 // | 7202 // MemBarVolatile 7203 // 7204 // The first MemBarVolatile could get optimized out! According to 7205 // Vladimir, this pattern can not occur on Oracle platforms. 7206 // However, it does occur on PPC64 (because of membars in 7207 // inline_unsafe_load_store). 7208 // 7209 // Add this node again if we found a good solution for inline_unsafe_load_store(). 7210 // Don't forget to look at the implementation of post_store_load_barrier again, 7211 // we did other fixes in that method. 7212 //instruct unnecessary_membar_volatile() %{ 7213 // match(MemBarVolatile); 7214 // predicate(Matcher::post_store_load_barrier(n)); 7215 // ins_cost(0); 7216 // 7217 // format %{ " -- \t// redundant MEMBAR-volatile - empty" %} 7218 // size(0); 7219 // ins_encode( /*empty*/ ); 7220 // ins_pipe(pipe_class_default); 7221 //%} 7222 7223 instruct membar_CPUOrder() %{ 7224 match(MemBarCPUOrder); 7225 ins_cost(0); 7226 7227 format %{ " -- \t// MEMBAR-CPUOrder - empty: PPC64 processors are self-consistent." %} 7228 size(0); 7229 ins_encode( /*empty*/ ); 7230 ins_pipe(pipe_class_default); 7231 %} 7232 7233 //----------Conditional Move--------------------------------------------------- 7234 7235 // Cmove using isel. 7236 instruct cmovI_reg_isel(cmpOp cmp, flagsReg crx, iRegIdst dst, iRegIsrc src) %{ 7237 match(Set dst (CMoveI (Binary cmp crx) (Binary dst src))); 7238 predicate(VM_Version::has_isel()); 7239 ins_cost(DEFAULT_COST); 7240 7241 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %} 7242 size(4); 7243 ins_encode %{ 7244 // This is a Power7 instruction for which no machine description 7245 // exists. Anyways, the scheduler should be off on Power7. 7246 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 7247 int cc = $cmp$$cmpcode; 7248 __ isel($dst$$Register, $crx$$CondRegister, 7249 (Assembler::Condition)(cc & 3), /*invert*/((~cc) & 8), $src$$Register); 7250 %} 7251 ins_pipe(pipe_class_default); 7252 %} 7253 7254 instruct cmovI_reg(cmpOp cmp, flagsReg crx, iRegIdst dst, iRegIsrc src) %{ 7255 match(Set dst (CMoveI (Binary cmp crx) (Binary dst src))); 7256 predicate(!VM_Version::has_isel()); 7257 ins_cost(DEFAULT_COST+BRANCH_COST); 7258 7259 ins_variable_size_depending_on_alignment(true); 7260 7261 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %} 7262 // Worst case is branch + move + stop, no stop without scheduler 7263 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8); 7264 ins_encode( enc_cmove_reg(dst, crx, src, cmp) ); 7265 ins_pipe(pipe_class_default); 7266 %} 7267 7268 instruct cmovI_imm(cmpOp cmp, flagsReg crx, iRegIdst dst, immI16 src) %{ 7269 match(Set dst (CMoveI (Binary cmp crx) (Binary dst src))); 7270 ins_cost(DEFAULT_COST+BRANCH_COST); 7271 7272 ins_variable_size_depending_on_alignment(true); 7273 7274 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %} 7275 // Worst case is branch + move + stop, no stop without scheduler 7276 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8); 7277 ins_encode( enc_cmove_imm(dst, crx, src, cmp) ); 7278 ins_pipe(pipe_class_default); 7279 %} 7280 7281 // Cmove using isel. 7282 instruct cmovL_reg_isel(cmpOp cmp, flagsReg crx, iRegLdst dst, iRegLsrc src) %{ 7283 match(Set dst (CMoveL (Binary cmp crx) (Binary dst src))); 7284 predicate(VM_Version::has_isel()); 7285 ins_cost(DEFAULT_COST); 7286 7287 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %} 7288 size(4); 7289 ins_encode %{ 7290 // This is a Power7 instruction for which no machine description 7291 // exists. Anyways, the scheduler should be off on Power7. 7292 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 7293 int cc = $cmp$$cmpcode; 7294 __ isel($dst$$Register, $crx$$CondRegister, 7295 (Assembler::Condition)(cc & 3), /*invert*/((~cc) & 8), $src$$Register); 7296 %} 7297 ins_pipe(pipe_class_default); 7298 %} 7299 7300 instruct cmovL_reg(cmpOp cmp, flagsReg crx, iRegLdst dst, iRegLsrc src) %{ 7301 match(Set dst (CMoveL (Binary cmp crx) (Binary dst src))); 7302 predicate(!VM_Version::has_isel()); 7303 ins_cost(DEFAULT_COST+BRANCH_COST); 7304 7305 ins_variable_size_depending_on_alignment(true); 7306 7307 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %} 7308 // Worst case is branch + move + stop, no stop without scheduler. 7309 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8); 7310 ins_encode( enc_cmove_reg(dst, crx, src, cmp) ); 7311 ins_pipe(pipe_class_default); 7312 %} 7313 7314 instruct cmovL_imm(cmpOp cmp, flagsReg crx, iRegLdst dst, immL16 src) %{ 7315 match(Set dst (CMoveL (Binary cmp crx) (Binary dst src))); 7316 ins_cost(DEFAULT_COST+BRANCH_COST); 7317 7318 ins_variable_size_depending_on_alignment(true); 7319 7320 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %} 7321 // Worst case is branch + move + stop, no stop without scheduler. 7322 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8); 7323 ins_encode( enc_cmove_imm(dst, crx, src, cmp) ); 7324 ins_pipe(pipe_class_default); 7325 %} 7326 7327 // Cmove using isel. 7328 instruct cmovN_reg_isel(cmpOp cmp, flagsReg crx, iRegNdst dst, iRegNsrc src) %{ 7329 match(Set dst (CMoveN (Binary cmp crx) (Binary dst src))); 7330 predicate(VM_Version::has_isel()); 7331 ins_cost(DEFAULT_COST); 7332 7333 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %} 7334 size(4); 7335 ins_encode %{ 7336 // This is a Power7 instruction for which no machine description 7337 // exists. Anyways, the scheduler should be off on Power7. 7338 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 7339 int cc = $cmp$$cmpcode; 7340 __ isel($dst$$Register, $crx$$CondRegister, 7341 (Assembler::Condition)(cc & 3), /*invert*/((~cc) & 8), $src$$Register); 7342 %} 7343 ins_pipe(pipe_class_default); 7344 %} 7345 7346 // Conditional move for RegN. Only cmov(reg, reg). 7347 instruct cmovN_reg(cmpOp cmp, flagsReg crx, iRegNdst dst, iRegNsrc src) %{ 7348 match(Set dst (CMoveN (Binary cmp crx) (Binary dst src))); 7349 predicate(!VM_Version::has_isel()); 7350 ins_cost(DEFAULT_COST+BRANCH_COST); 7351 7352 ins_variable_size_depending_on_alignment(true); 7353 7354 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %} 7355 // Worst case is branch + move + stop, no stop without scheduler. 7356 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8); 7357 ins_encode( enc_cmove_reg(dst, crx, src, cmp) ); 7358 ins_pipe(pipe_class_default); 7359 %} 7360 7361 instruct cmovN_imm(cmpOp cmp, flagsReg crx, iRegNdst dst, immN_0 src) %{ 7362 match(Set dst (CMoveN (Binary cmp crx) (Binary dst src))); 7363 ins_cost(DEFAULT_COST+BRANCH_COST); 7364 7365 ins_variable_size_depending_on_alignment(true); 7366 7367 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %} 7368 // Worst case is branch + move + stop, no stop without scheduler. 7369 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8); 7370 ins_encode( enc_cmove_imm(dst, crx, src, cmp) ); 7371 ins_pipe(pipe_class_default); 7372 %} 7373 7374 // Cmove using isel. 7375 instruct cmovP_reg_isel(cmpOp cmp, flagsReg crx, iRegPdst dst, iRegPsrc src) %{ 7376 match(Set dst (CMoveP (Binary cmp crx) (Binary dst src))); 7377 predicate(VM_Version::has_isel()); 7378 ins_cost(DEFAULT_COST); 7379 7380 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %} 7381 size(4); 7382 ins_encode %{ 7383 // This is a Power7 instruction for which no machine description 7384 // exists. Anyways, the scheduler should be off on Power7. 7385 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 7386 int cc = $cmp$$cmpcode; 7387 __ isel($dst$$Register, $crx$$CondRegister, 7388 (Assembler::Condition)(cc & 3), /*invert*/((~cc) & 8), $src$$Register); 7389 %} 7390 ins_pipe(pipe_class_default); 7391 %} 7392 7393 instruct cmovP_reg(cmpOp cmp, flagsReg crx, iRegPdst dst, iRegP_N2P src) %{ 7394 match(Set dst (CMoveP (Binary cmp crx) (Binary dst src))); 7395 predicate(!VM_Version::has_isel()); 7396 ins_cost(DEFAULT_COST+BRANCH_COST); 7397 7398 ins_variable_size_depending_on_alignment(true); 7399 7400 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %} 7401 // Worst case is branch + move + stop, no stop without scheduler. 7402 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8); 7403 ins_encode( enc_cmove_reg(dst, crx, src, cmp) ); 7404 ins_pipe(pipe_class_default); 7405 %} 7406 7407 instruct cmovP_imm(cmpOp cmp, flagsReg crx, iRegPdst dst, immP_0 src) %{ 7408 match(Set dst (CMoveP (Binary cmp crx) (Binary dst src))); 7409 ins_cost(DEFAULT_COST+BRANCH_COST); 7410 7411 ins_variable_size_depending_on_alignment(true); 7412 7413 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %} 7414 // Worst case is branch + move + stop, no stop without scheduler. 7415 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8); 7416 ins_encode( enc_cmove_imm(dst, crx, src, cmp) ); 7417 ins_pipe(pipe_class_default); 7418 %} 7419 7420 instruct cmovF_reg(cmpOp cmp, flagsReg crx, regF dst, regF src) %{ 7421 match(Set dst (CMoveF (Binary cmp crx) (Binary dst src))); 7422 ins_cost(DEFAULT_COST+BRANCH_COST); 7423 7424 ins_variable_size_depending_on_alignment(true); 7425 7426 format %{ "CMOVEF $cmp, $crx, $dst, $src\n\t" %} 7427 // Worst case is branch + move + stop, no stop without scheduler. 7428 size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8); 7429 ins_encode %{ 7430 // TODO: PPC port $archOpcode(ppc64Opcode_cmovef); 7431 Label done; 7432 assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding"); 7433 // Branch if not (cmp crx). 7434 __ bc(cc_to_inverse_boint($cmp$$cmpcode), cc_to_biint($cmp$$cmpcode, $crx$$reg), done); 7435 __ fmr($dst$$FloatRegister, $src$$FloatRegister); 7436 // TODO PPC port __ endgroup_if_needed(_size == 12); 7437 __ bind(done); 7438 %} 7439 ins_pipe(pipe_class_default); 7440 %} 7441 7442 instruct cmovD_reg(cmpOp cmp, flagsReg crx, regD dst, regD src) %{ 7443 match(Set dst (CMoveD (Binary cmp crx) (Binary dst src))); 7444 ins_cost(DEFAULT_COST+BRANCH_COST); 7445 7446 ins_variable_size_depending_on_alignment(true); 7447 7448 format %{ "CMOVEF $cmp, $crx, $dst, $src\n\t" %} 7449 // Worst case is branch + move + stop, no stop without scheduler. 7450 size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8); 7451 ins_encode %{ 7452 // TODO: PPC port $archOpcode(ppc64Opcode_cmovef); 7453 Label done; 7454 assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding"); 7455 // Branch if not (cmp crx). 7456 __ bc(cc_to_inverse_boint($cmp$$cmpcode), cc_to_biint($cmp$$cmpcode, $crx$$reg), done); 7457 __ fmr($dst$$FloatRegister, $src$$FloatRegister); 7458 // TODO PPC port __ endgroup_if_needed(_size == 12); 7459 __ bind(done); 7460 %} 7461 ins_pipe(pipe_class_default); 7462 %} 7463 7464 //----------Conditional_store-------------------------------------------------- 7465 // Conditional-store of the updated heap-top. 7466 // Used during allocation of the shared heap. 7467 // Sets flags (EQ) on success. Implemented with a CASA on Sparc. 7468 7469 // As compareAndSwapL, but return flag register instead of boolean value in 7470 // int register. 7471 // Used by sun/misc/AtomicLongCSImpl.java. 7472 // Mem_ptr must be a memory operand, else this node does not get 7473 // Flag_needs_anti_dependence_check set by adlc. If this is not set this node 7474 // can be rematerialized which leads to errors. 7475 instruct storeLConditional_regP_regL_regL(flagsReg crx, indirect mem_ptr, iRegLsrc oldVal, iRegLsrc newVal) %{ 7476 match(Set crx (StoreLConditional mem_ptr (Binary oldVal newVal))); 7477 format %{ "CMPXCHGD if ($crx = ($oldVal == *$mem_ptr)) *mem_ptr = $newVal; as bool" %} 7478 ins_encode %{ 7479 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 7480 __ cmpxchgd($crx$$CondRegister, R0, $oldVal$$Register, $newVal$$Register, $mem_ptr$$Register, 7481 MacroAssembler::MemBarNone, MacroAssembler::cmpxchgx_hint_atomic_update(), 7482 noreg, NULL, true); 7483 %} 7484 ins_pipe(pipe_class_default); 7485 %} 7486 7487 // As compareAndSwapP, but return flag register instead of boolean value in 7488 // int register. 7489 // This instruction is matched if UseTLAB is off. 7490 // Mem_ptr must be a memory operand, else this node does not get 7491 // Flag_needs_anti_dependence_check set by adlc. If this is not set this node 7492 // can be rematerialized which leads to errors. 7493 instruct storePConditional_regP_regP_regP(flagsReg crx, indirect mem_ptr, iRegPsrc oldVal, iRegPsrc newVal) %{ 7494 match(Set crx (StorePConditional mem_ptr (Binary oldVal newVal))); 7495 format %{ "CMPXCHGD if ($crx = ($oldVal == *$mem_ptr)) *mem_ptr = $newVal; as bool" %} 7496 ins_encode %{ 7497 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 7498 __ cmpxchgd($crx$$CondRegister, R0, $oldVal$$Register, $newVal$$Register, $mem_ptr$$Register, 7499 MacroAssembler::MemBarNone, MacroAssembler::cmpxchgx_hint_atomic_update(), 7500 noreg, NULL, true); 7501 %} 7502 ins_pipe(pipe_class_default); 7503 %} 7504 7505 // Implement LoadPLocked. Must be ordered against changes of the memory location 7506 // by storePConditional. 7507 // Don't know whether this is ever used. 7508 instruct loadPLocked(iRegPdst dst, memory mem) %{ 7509 match(Set dst (LoadPLocked mem)); 7510 ins_cost(MEMORY_REF_COST); 7511 7512 format %{ "LD $dst, $mem \t// loadPLocked\n\t" 7513 "TWI $dst\n\t" 7514 "ISYNC" %} 7515 size(12); 7516 ins_encode( enc_ld_ac(dst, mem) ); 7517 ins_pipe(pipe_class_memory); 7518 %} 7519 7520 //----------Compare-And-Swap--------------------------------------------------- 7521 7522 // CompareAndSwap{P,I,L} have more than one output, therefore "CmpI 7523 // (CompareAndSwap ...)" or "If (CmpI (CompareAndSwap ..))" cannot be 7524 // matched. 7525 7526 instruct compareAndSwapI_regP_regI_regI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src1, iRegIsrc src2) %{ 7527 match(Set res (CompareAndSwapI mem_ptr (Binary src1 src2))); 7528 format %{ "CMPXCHGW $res, $mem_ptr, $src1, $src2; as bool" %} 7529 // Variable size: instruction count smaller if regs are disjoint. 7530 ins_encode %{ 7531 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 7532 // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'. 7533 __ cmpxchgw(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register, 7534 MacroAssembler::MemBarFenceAfter, MacroAssembler::cmpxchgx_hint_atomic_update(), 7535 $res$$Register, true); 7536 %} 7537 ins_pipe(pipe_class_default); 7538 %} 7539 7540 instruct compareAndSwapN_regP_regN_regN(iRegIdst res, iRegPdst mem_ptr, iRegNsrc src1, iRegNsrc src2) %{ 7541 match(Set res (CompareAndSwapN mem_ptr (Binary src1 src2))); 7542 format %{ "CMPXCHGW $res, $mem_ptr, $src1, $src2; as bool" %} 7543 // Variable size: instruction count smaller if regs are disjoint. 7544 ins_encode %{ 7545 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 7546 // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'. 7547 __ cmpxchgw(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register, 7548 MacroAssembler::MemBarFenceAfter, MacroAssembler::cmpxchgx_hint_atomic_update(), 7549 $res$$Register, true); 7550 %} 7551 ins_pipe(pipe_class_default); 7552 %} 7553 7554 instruct compareAndSwapL_regP_regL_regL(iRegIdst res, iRegPdst mem_ptr, iRegLsrc src1, iRegLsrc src2) %{ 7555 match(Set res (CompareAndSwapL mem_ptr (Binary src1 src2))); 7556 format %{ "CMPXCHGD $res, $mem_ptr, $src1, $src2; as bool" %} 7557 // Variable size: instruction count smaller if regs are disjoint. 7558 ins_encode %{ 7559 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 7560 // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'. 7561 __ cmpxchgd(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register, 7562 MacroAssembler::MemBarFenceAfter, MacroAssembler::cmpxchgx_hint_atomic_update(), 7563 $res$$Register, NULL, true); 7564 %} 7565 ins_pipe(pipe_class_default); 7566 %} 7567 7568 instruct compareAndSwapP_regP_regP_regP(iRegIdst res, iRegPdst mem_ptr, iRegPsrc src1, iRegPsrc src2) %{ 7569 match(Set res (CompareAndSwapP mem_ptr (Binary src1 src2))); 7570 format %{ "CMPXCHGD $res, $mem_ptr, $src1, $src2; as bool; ptr" %} 7571 // Variable size: instruction count smaller if regs are disjoint. 7572 ins_encode %{ 7573 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 7574 // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'. 7575 __ cmpxchgd(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register, 7576 MacroAssembler::MemBarFenceAfter, MacroAssembler::cmpxchgx_hint_atomic_update(), 7577 $res$$Register, NULL, true); 7578 %} 7579 ins_pipe(pipe_class_default); 7580 %} 7581 7582 instruct getAndAddI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src) %{ 7583 match(Set res (GetAndAddI mem_ptr src)); 7584 format %{ "GetAndAddI $res, $mem_ptr, $src" %} 7585 // Variable size: instruction count smaller if regs are disjoint. 7586 ins_encode( enc_GetAndAddI(res, mem_ptr, src) ); 7587 ins_pipe(pipe_class_default); 7588 %} 7589 7590 instruct getAndAddL(iRegLdst res, iRegPdst mem_ptr, iRegLsrc src) %{ 7591 match(Set res (GetAndAddL mem_ptr src)); 7592 format %{ "GetAndAddL $res, $mem_ptr, $src" %} 7593 // Variable size: instruction count smaller if regs are disjoint. 7594 ins_encode( enc_GetAndAddL(res, mem_ptr, src) ); 7595 ins_pipe(pipe_class_default); 7596 %} 7597 7598 instruct getAndSetI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src) %{ 7599 match(Set res (GetAndSetI mem_ptr src)); 7600 format %{ "GetAndSetI $res, $mem_ptr, $src" %} 7601 // Variable size: instruction count smaller if regs are disjoint. 7602 ins_encode( enc_GetAndSetI(res, mem_ptr, src) ); 7603 ins_pipe(pipe_class_default); 7604 %} 7605 7606 instruct getAndSetL(iRegLdst res, iRegPdst mem_ptr, iRegLsrc src) %{ 7607 match(Set res (GetAndSetL mem_ptr src)); 7608 format %{ "GetAndSetL $res, $mem_ptr, $src" %} 7609 // Variable size: instruction count smaller if regs are disjoint. 7610 ins_encode( enc_GetAndSetL(res, mem_ptr, src) ); 7611 ins_pipe(pipe_class_default); 7612 %} 7613 7614 instruct getAndSetP(iRegPdst res, iRegPdst mem_ptr, iRegPsrc src) %{ 7615 match(Set res (GetAndSetP mem_ptr src)); 7616 format %{ "GetAndSetP $res, $mem_ptr, $src" %} 7617 // Variable size: instruction count smaller if regs are disjoint. 7618 ins_encode( enc_GetAndSetL(res, mem_ptr, src) ); 7619 ins_pipe(pipe_class_default); 7620 %} 7621 7622 instruct getAndSetN(iRegNdst res, iRegPdst mem_ptr, iRegNsrc src) %{ 7623 match(Set res (GetAndSetN mem_ptr src)); 7624 format %{ "GetAndSetN $res, $mem_ptr, $src" %} 7625 // Variable size: instruction count smaller if regs are disjoint. 7626 ins_encode( enc_GetAndSetI(res, mem_ptr, src) ); 7627 ins_pipe(pipe_class_default); 7628 %} 7629 7630 //----------Arithmetic Instructions-------------------------------------------- 7631 // Addition Instructions 7632 7633 // Register Addition 7634 instruct addI_reg_reg(iRegIdst dst, iRegIsrc_iRegL2Isrc src1, iRegIsrc_iRegL2Isrc src2) %{ 7635 match(Set dst (AddI src1 src2)); 7636 format %{ "ADD $dst, $src1, $src2" %} 7637 size(4); 7638 ins_encode %{ 7639 // TODO: PPC port $archOpcode(ppc64Opcode_add); 7640 __ add($dst$$Register, $src1$$Register, $src2$$Register); 7641 %} 7642 ins_pipe(pipe_class_default); 7643 %} 7644 7645 // Expand does not work with above instruct. (??) 7646 instruct addI_reg_reg_2(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ 7647 // no match-rule 7648 effect(DEF dst, USE src1, USE src2); 7649 format %{ "ADD $dst, $src1, $src2" %} 7650 size(4); 7651 ins_encode %{ 7652 // TODO: PPC port $archOpcode(ppc64Opcode_add); 7653 __ add($dst$$Register, $src1$$Register, $src2$$Register); 7654 %} 7655 ins_pipe(pipe_class_default); 7656 %} 7657 7658 instruct tree_addI_addI_addI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2, iRegIsrc src3, iRegIsrc src4) %{ 7659 match(Set dst (AddI (AddI (AddI src1 src2) src3) src4)); 7660 ins_cost(DEFAULT_COST*3); 7661 7662 expand %{ 7663 // FIXME: we should do this in the ideal world. 7664 iRegIdst tmp1; 7665 iRegIdst tmp2; 7666 addI_reg_reg(tmp1, src1, src2); 7667 addI_reg_reg_2(tmp2, src3, src4); // Adlc complains about addI_reg_reg. 7668 addI_reg_reg(dst, tmp1, tmp2); 7669 %} 7670 %} 7671 7672 // Immediate Addition 7673 instruct addI_reg_imm16(iRegIdst dst, iRegIsrc src1, immI16 src2) %{ 7674 match(Set dst (AddI src1 src2)); 7675 format %{ "ADDI $dst, $src1, $src2" %} 7676 size(4); 7677 ins_encode %{ 7678 // TODO: PPC port $archOpcode(ppc64Opcode_addi); 7679 __ addi($dst$$Register, $src1$$Register, $src2$$constant); 7680 %} 7681 ins_pipe(pipe_class_default); 7682 %} 7683 7684 // Immediate Addition with 16-bit shifted operand 7685 instruct addI_reg_immhi16(iRegIdst dst, iRegIsrc src1, immIhi16 src2) %{ 7686 match(Set dst (AddI src1 src2)); 7687 format %{ "ADDIS $dst, $src1, $src2" %} 7688 size(4); 7689 ins_encode %{ 7690 // TODO: PPC port $archOpcode(ppc64Opcode_addis); 7691 __ addis($dst$$Register, $src1$$Register, ($src2$$constant)>>16); 7692 %} 7693 ins_pipe(pipe_class_default); 7694 %} 7695 7696 // Long Addition 7697 instruct addL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{ 7698 match(Set dst (AddL src1 src2)); 7699 format %{ "ADD $dst, $src1, $src2 \t// long" %} 7700 size(4); 7701 ins_encode %{ 7702 // TODO: PPC port $archOpcode(ppc64Opcode_add); 7703 __ add($dst$$Register, $src1$$Register, $src2$$Register); 7704 %} 7705 ins_pipe(pipe_class_default); 7706 %} 7707 7708 // Expand does not work with above instruct. (??) 7709 instruct addL_reg_reg_2(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{ 7710 // no match-rule 7711 effect(DEF dst, USE src1, USE src2); 7712 format %{ "ADD $dst, $src1, $src2 \t// long" %} 7713 size(4); 7714 ins_encode %{ 7715 // TODO: PPC port $archOpcode(ppc64Opcode_add); 7716 __ add($dst$$Register, $src1$$Register, $src2$$Register); 7717 %} 7718 ins_pipe(pipe_class_default); 7719 %} 7720 7721 instruct tree_addL_addL_addL_reg_reg_Ex(iRegLdst dst, iRegLsrc src1, iRegLsrc src2, iRegLsrc src3, iRegLsrc src4) %{ 7722 match(Set dst (AddL (AddL (AddL src1 src2) src3) src4)); 7723 ins_cost(DEFAULT_COST*3); 7724 7725 expand %{ 7726 // FIXME: we should do this in the ideal world. 7727 iRegLdst tmp1; 7728 iRegLdst tmp2; 7729 addL_reg_reg(tmp1, src1, src2); 7730 addL_reg_reg_2(tmp2, src3, src4); // Adlc complains about orI_reg_reg. 7731 addL_reg_reg(dst, tmp1, tmp2); 7732 %} 7733 %} 7734 7735 // AddL + ConvL2I. 7736 instruct addI_regL_regL(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{ 7737 match(Set dst (ConvL2I (AddL src1 src2))); 7738 7739 format %{ "ADD $dst, $src1, $src2 \t// long + l2i" %} 7740 size(4); 7741 ins_encode %{ 7742 // TODO: PPC port $archOpcode(ppc64Opcode_add); 7743 __ add($dst$$Register, $src1$$Register, $src2$$Register); 7744 %} 7745 ins_pipe(pipe_class_default); 7746 %} 7747 7748 // No constant pool entries required. 7749 instruct addL_reg_imm16(iRegLdst dst, iRegLsrc src1, immL16 src2) %{ 7750 match(Set dst (AddL src1 src2)); 7751 7752 format %{ "ADDI $dst, $src1, $src2" %} 7753 size(4); 7754 ins_encode %{ 7755 // TODO: PPC port $archOpcode(ppc64Opcode_addi); 7756 __ addi($dst$$Register, $src1$$Register, $src2$$constant); 7757 %} 7758 ins_pipe(pipe_class_default); 7759 %} 7760 7761 // Long Immediate Addition with 16-bit shifted operand. 7762 // No constant pool entries required. 7763 instruct addL_reg_immhi16(iRegLdst dst, iRegLsrc src1, immL32hi16 src2) %{ 7764 match(Set dst (AddL src1 src2)); 7765 7766 format %{ "ADDIS $dst, $src1, $src2" %} 7767 size(4); 7768 ins_encode %{ 7769 // TODO: PPC port $archOpcode(ppc64Opcode_addis); 7770 __ addis($dst$$Register, $src1$$Register, ($src2$$constant)>>16); 7771 %} 7772 ins_pipe(pipe_class_default); 7773 %} 7774 7775 // Pointer Register Addition 7776 instruct addP_reg_reg(iRegPdst dst, iRegP_N2P src1, iRegLsrc src2) %{ 7777 match(Set dst (AddP src1 src2)); 7778 format %{ "ADD $dst, $src1, $src2" %} 7779 size(4); 7780 ins_encode %{ 7781 // TODO: PPC port $archOpcode(ppc64Opcode_add); 7782 __ add($dst$$Register, $src1$$Register, $src2$$Register); 7783 %} 7784 ins_pipe(pipe_class_default); 7785 %} 7786 7787 // Pointer Immediate Addition 7788 // No constant pool entries required. 7789 instruct addP_reg_imm16(iRegPdst dst, iRegP_N2P src1, immL16 src2) %{ 7790 match(Set dst (AddP src1 src2)); 7791 7792 format %{ "ADDI $dst, $src1, $src2" %} 7793 size(4); 7794 ins_encode %{ 7795 // TODO: PPC port $archOpcode(ppc64Opcode_addi); 7796 __ addi($dst$$Register, $src1$$Register, $src2$$constant); 7797 %} 7798 ins_pipe(pipe_class_default); 7799 %} 7800 7801 // Pointer Immediate Addition with 16-bit shifted operand. 7802 // No constant pool entries required. 7803 instruct addP_reg_immhi16(iRegPdst dst, iRegP_N2P src1, immL32hi16 src2) %{ 7804 match(Set dst (AddP src1 src2)); 7805 7806 format %{ "ADDIS $dst, $src1, $src2" %} 7807 size(4); 7808 ins_encode %{ 7809 // TODO: PPC port $archOpcode(ppc64Opcode_addis); 7810 __ addis($dst$$Register, $src1$$Register, ($src2$$constant)>>16); 7811 %} 7812 ins_pipe(pipe_class_default); 7813 %} 7814 7815 //--------------------- 7816 // Subtraction Instructions 7817 7818 // Register Subtraction 7819 instruct subI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ 7820 match(Set dst (SubI src1 src2)); 7821 format %{ "SUBF $dst, $src2, $src1" %} 7822 size(4); 7823 ins_encode %{ 7824 // TODO: PPC port $archOpcode(ppc64Opcode_subf); 7825 __ subf($dst$$Register, $src2$$Register, $src1$$Register); 7826 %} 7827 ins_pipe(pipe_class_default); 7828 %} 7829 7830 // Immediate Subtraction 7831 // The compiler converts "x-c0" into "x+ -c0" (see SubINode::Ideal), 7832 // so this rule seems to be unused. 7833 instruct subI_reg_imm16(iRegIdst dst, iRegIsrc src1, immI16 src2) %{ 7834 match(Set dst (SubI src1 src2)); 7835 format %{ "SUBI $dst, $src1, $src2" %} 7836 size(4); 7837 ins_encode %{ 7838 // TODO: PPC port $archOpcode(ppc64Opcode_addi); 7839 __ addi($dst$$Register, $src1$$Register, ($src2$$constant) * (-1)); 7840 %} 7841 ins_pipe(pipe_class_default); 7842 %} 7843 7844 // SubI from constant (using subfic). 7845 instruct subI_imm16_reg(iRegIdst dst, immI16 src1, iRegIsrc src2) %{ 7846 match(Set dst (SubI src1 src2)); 7847 format %{ "SUBI $dst, $src1, $src2" %} 7848 7849 size(4); 7850 ins_encode %{ 7851 // TODO: PPC port $archOpcode(ppc64Opcode_subfic); 7852 __ subfic($dst$$Register, $src2$$Register, $src1$$constant); 7853 %} 7854 ins_pipe(pipe_class_default); 7855 %} 7856 7857 // Turn the sign-bit of an integer into a 32-bit mask, 0x0...0 for 7858 // positive integers and 0xF...F for negative ones. 7859 instruct signmask32I_regI(iRegIdst dst, iRegIsrc src) %{ 7860 // no match-rule, false predicate 7861 effect(DEF dst, USE src); 7862 predicate(false); 7863 7864 format %{ "SRAWI $dst, $src, #31" %} 7865 size(4); 7866 ins_encode %{ 7867 // TODO: PPC port $archOpcode(ppc64Opcode_srawi); 7868 __ srawi($dst$$Register, $src$$Register, 0x1f); 7869 %} 7870 ins_pipe(pipe_class_default); 7871 %} 7872 7873 instruct absI_reg_Ex(iRegIdst dst, iRegIsrc src) %{ 7874 match(Set dst (AbsI src)); 7875 ins_cost(DEFAULT_COST*3); 7876 7877 expand %{ 7878 iRegIdst tmp1; 7879 iRegIdst tmp2; 7880 signmask32I_regI(tmp1, src); 7881 xorI_reg_reg(tmp2, tmp1, src); 7882 subI_reg_reg(dst, tmp2, tmp1); 7883 %} 7884 %} 7885 7886 instruct negI_regI(iRegIdst dst, immI_0 zero, iRegIsrc src2) %{ 7887 match(Set dst (SubI zero src2)); 7888 format %{ "NEG $dst, $src2" %} 7889 size(4); 7890 ins_encode %{ 7891 // TODO: PPC port $archOpcode(ppc64Opcode_neg); 7892 __ neg($dst$$Register, $src2$$Register); 7893 %} 7894 ins_pipe(pipe_class_default); 7895 %} 7896 7897 // Long subtraction 7898 instruct subL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{ 7899 match(Set dst (SubL src1 src2)); 7900 format %{ "SUBF $dst, $src2, $src1 \t// long" %} 7901 size(4); 7902 ins_encode %{ 7903 // TODO: PPC port $archOpcode(ppc64Opcode_subf); 7904 __ subf($dst$$Register, $src2$$Register, $src1$$Register); 7905 %} 7906 ins_pipe(pipe_class_default); 7907 %} 7908 7909 // SubL + convL2I. 7910 instruct subI_regL_regL(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{ 7911 match(Set dst (ConvL2I (SubL src1 src2))); 7912 7913 format %{ "SUBF $dst, $src2, $src1 \t// long + l2i" %} 7914 size(4); 7915 ins_encode %{ 7916 // TODO: PPC port $archOpcode(ppc64Opcode_subf); 7917 __ subf($dst$$Register, $src2$$Register, $src1$$Register); 7918 %} 7919 ins_pipe(pipe_class_default); 7920 %} 7921 7922 // Immediate Subtraction 7923 // The compiler converts "x-c0" into "x+ -c0" (see SubLNode::Ideal), 7924 // so this rule seems to be unused. 7925 // No constant pool entries required. 7926 instruct subL_reg_imm16(iRegLdst dst, iRegLsrc src1, immL16 src2) %{ 7927 match(Set dst (SubL src1 src2)); 7928 7929 format %{ "SUBI $dst, $src1, $src2 \t// long" %} 7930 size(4); 7931 ins_encode %{ 7932 // TODO: PPC port $archOpcode(ppc64Opcode_addi); 7933 __ addi($dst$$Register, $src1$$Register, ($src2$$constant) * (-1)); 7934 %} 7935 ins_pipe(pipe_class_default); 7936 %} 7937 7938 // Turn the sign-bit of a long into a 64-bit mask, 0x0...0 for 7939 // positive longs and 0xF...F for negative ones. 7940 instruct signmask64I_regL(iRegIdst dst, iRegLsrc src) %{ 7941 // no match-rule, false predicate 7942 effect(DEF dst, USE src); 7943 predicate(false); 7944 7945 format %{ "SRADI $dst, $src, #63" %} 7946 size(4); 7947 ins_encode %{ 7948 // TODO: PPC port $archOpcode(ppc64Opcode_sradi); 7949 __ sradi($dst$$Register, $src$$Register, 0x3f); 7950 %} 7951 ins_pipe(pipe_class_default); 7952 %} 7953 7954 // Turn the sign-bit of a long into a 64-bit mask, 0x0...0 for 7955 // positive longs and 0xF...F for negative ones. 7956 instruct signmask64L_regL(iRegLdst dst, iRegLsrc src) %{ 7957 // no match-rule, false predicate 7958 effect(DEF dst, USE src); 7959 predicate(false); 7960 7961 format %{ "SRADI $dst, $src, #63" %} 7962 size(4); 7963 ins_encode %{ 7964 // TODO: PPC port $archOpcode(ppc64Opcode_sradi); 7965 __ sradi($dst$$Register, $src$$Register, 0x3f); 7966 %} 7967 ins_pipe(pipe_class_default); 7968 %} 7969 7970 // Long negation 7971 instruct negL_reg_reg(iRegLdst dst, immL_0 zero, iRegLsrc src2) %{ 7972 match(Set dst (SubL zero src2)); 7973 format %{ "NEG $dst, $src2 \t// long" %} 7974 size(4); 7975 ins_encode %{ 7976 // TODO: PPC port $archOpcode(ppc64Opcode_neg); 7977 __ neg($dst$$Register, $src2$$Register); 7978 %} 7979 ins_pipe(pipe_class_default); 7980 %} 7981 7982 // NegL + ConvL2I. 7983 instruct negI_con0_regL(iRegIdst dst, immL_0 zero, iRegLsrc src2) %{ 7984 match(Set dst (ConvL2I (SubL zero src2))); 7985 7986 format %{ "NEG $dst, $src2 \t// long + l2i" %} 7987 size(4); 7988 ins_encode %{ 7989 // TODO: PPC port $archOpcode(ppc64Opcode_neg); 7990 __ neg($dst$$Register, $src2$$Register); 7991 %} 7992 ins_pipe(pipe_class_default); 7993 %} 7994 7995 // Multiplication Instructions 7996 // Integer Multiplication 7997 7998 // Register Multiplication 7999 instruct mulI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ 8000 match(Set dst (MulI src1 src2)); 8001 ins_cost(DEFAULT_COST); 8002 8003 format %{ "MULLW $dst, $src1, $src2" %} 8004 size(4); 8005 ins_encode %{ 8006 // TODO: PPC port $archOpcode(ppc64Opcode_mullw); 8007 __ mullw($dst$$Register, $src1$$Register, $src2$$Register); 8008 %} 8009 ins_pipe(pipe_class_default); 8010 %} 8011 8012 // Immediate Multiplication 8013 instruct mulI_reg_imm16(iRegIdst dst, iRegIsrc src1, immI16 src2) %{ 8014 match(Set dst (MulI src1 src2)); 8015 ins_cost(DEFAULT_COST); 8016 8017 format %{ "MULLI $dst, $src1, $src2" %} 8018 size(4); 8019 ins_encode %{ 8020 // TODO: PPC port $archOpcode(ppc64Opcode_mulli); 8021 __ mulli($dst$$Register, $src1$$Register, $src2$$constant); 8022 %} 8023 ins_pipe(pipe_class_default); 8024 %} 8025 8026 instruct mulL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{ 8027 match(Set dst (MulL src1 src2)); 8028 ins_cost(DEFAULT_COST); 8029 8030 format %{ "MULLD $dst $src1, $src2 \t// long" %} 8031 size(4); 8032 ins_encode %{ 8033 // TODO: PPC port $archOpcode(ppc64Opcode_mulld); 8034 __ mulld($dst$$Register, $src1$$Register, $src2$$Register); 8035 %} 8036 ins_pipe(pipe_class_default); 8037 %} 8038 8039 // Multiply high for optimized long division by constant. 8040 instruct mulHighL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{ 8041 match(Set dst (MulHiL src1 src2)); 8042 ins_cost(DEFAULT_COST); 8043 8044 format %{ "MULHD $dst $src1, $src2 \t// long" %} 8045 size(4); 8046 ins_encode %{ 8047 // TODO: PPC port $archOpcode(ppc64Opcode_mulhd); 8048 __ mulhd($dst$$Register, $src1$$Register, $src2$$Register); 8049 %} 8050 ins_pipe(pipe_class_default); 8051 %} 8052 8053 // Immediate Multiplication 8054 instruct mulL_reg_imm16(iRegLdst dst, iRegLsrc src1, immL16 src2) %{ 8055 match(Set dst (MulL src1 src2)); 8056 ins_cost(DEFAULT_COST); 8057 8058 format %{ "MULLI $dst, $src1, $src2" %} 8059 size(4); 8060 ins_encode %{ 8061 // TODO: PPC port $archOpcode(ppc64Opcode_mulli); 8062 __ mulli($dst$$Register, $src1$$Register, $src2$$constant); 8063 %} 8064 ins_pipe(pipe_class_default); 8065 %} 8066 8067 // Integer Division with Immediate -1: Negate. 8068 instruct divI_reg_immIvalueMinus1(iRegIdst dst, iRegIsrc src1, immI_minus1 src2) %{ 8069 match(Set dst (DivI src1 src2)); 8070 ins_cost(DEFAULT_COST); 8071 8072 format %{ "NEG $dst, $src1 \t// /-1" %} 8073 size(4); 8074 ins_encode %{ 8075 // TODO: PPC port $archOpcode(ppc64Opcode_neg); 8076 __ neg($dst$$Register, $src1$$Register); 8077 %} 8078 ins_pipe(pipe_class_default); 8079 %} 8080 8081 // Integer Division with constant, but not -1. 8082 // We should be able to improve this by checking the type of src2. 8083 // It might well be that src2 is known to be positive. 8084 instruct divI_reg_regnotMinus1(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ 8085 match(Set dst (DivI src1 src2)); 8086 predicate(n->in(2)->find_int_con(-1) != -1); // src2 is a constant, but not -1 8087 ins_cost(2*DEFAULT_COST); 8088 8089 format %{ "DIVW $dst, $src1, $src2 \t// /not-1" %} 8090 size(4); 8091 ins_encode %{ 8092 // TODO: PPC port $archOpcode(ppc64Opcode_divw); 8093 __ divw($dst$$Register, $src1$$Register, $src2$$Register); 8094 %} 8095 ins_pipe(pipe_class_default); 8096 %} 8097 8098 instruct cmovI_bne_negI_reg(iRegIdst dst, flagsReg crx, iRegIsrc src1) %{ 8099 effect(USE_DEF dst, USE src1, USE crx); 8100 predicate(false); 8101 8102 ins_variable_size_depending_on_alignment(true); 8103 8104 format %{ "CMOVE $dst, neg($src1), $crx" %} 8105 // Worst case is branch + move + stop, no stop without scheduler. 8106 size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8); 8107 ins_encode %{ 8108 // TODO: PPC port $archOpcode(ppc64Opcode_cmove); 8109 Label done; 8110 __ bne($crx$$CondRegister, done); 8111 __ neg($dst$$Register, $src1$$Register); 8112 // TODO PPC port __ endgroup_if_needed(_size == 12); 8113 __ bind(done); 8114 %} 8115 ins_pipe(pipe_class_default); 8116 %} 8117 8118 // Integer Division with Registers not containing constants. 8119 instruct divI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ 8120 match(Set dst (DivI src1 src2)); 8121 ins_cost(10*DEFAULT_COST); 8122 8123 expand %{ 8124 immI16 imm %{ (int)-1 %} 8125 flagsReg tmp1; 8126 cmpI_reg_imm16(tmp1, src2, imm); // check src2 == -1 8127 divI_reg_regnotMinus1(dst, src1, src2); // dst = src1 / src2 8128 cmovI_bne_negI_reg(dst, tmp1, src1); // cmove dst = neg(src1) if src2 == -1 8129 %} 8130 %} 8131 8132 // Long Division with Immediate -1: Negate. 8133 instruct divL_reg_immLvalueMinus1(iRegLdst dst, iRegLsrc src1, immL_minus1 src2) %{ 8134 match(Set dst (DivL src1 src2)); 8135 ins_cost(DEFAULT_COST); 8136 8137 format %{ "NEG $dst, $src1 \t// /-1, long" %} 8138 size(4); 8139 ins_encode %{ 8140 // TODO: PPC port $archOpcode(ppc64Opcode_neg); 8141 __ neg($dst$$Register, $src1$$Register); 8142 %} 8143 ins_pipe(pipe_class_default); 8144 %} 8145 8146 // Long Division with constant, but not -1. 8147 instruct divL_reg_regnotMinus1(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{ 8148 match(Set dst (DivL src1 src2)); 8149 predicate(n->in(2)->find_long_con(-1L) != -1L); // Src2 is a constant, but not -1. 8150 ins_cost(2*DEFAULT_COST); 8151 8152 format %{ "DIVD $dst, $src1, $src2 \t// /not-1, long" %} 8153 size(4); 8154 ins_encode %{ 8155 // TODO: PPC port $archOpcode(ppc64Opcode_divd); 8156 __ divd($dst$$Register, $src1$$Register, $src2$$Register); 8157 %} 8158 ins_pipe(pipe_class_default); 8159 %} 8160 8161 instruct cmovL_bne_negL_reg(iRegLdst dst, flagsReg crx, iRegLsrc src1) %{ 8162 effect(USE_DEF dst, USE src1, USE crx); 8163 predicate(false); 8164 8165 ins_variable_size_depending_on_alignment(true); 8166 8167 format %{ "CMOVE $dst, neg($src1), $crx" %} 8168 // Worst case is branch + move + stop, no stop without scheduler. 8169 size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8); 8170 ins_encode %{ 8171 // TODO: PPC port $archOpcode(ppc64Opcode_cmove); 8172 Label done; 8173 __ bne($crx$$CondRegister, done); 8174 __ neg($dst$$Register, $src1$$Register); 8175 // TODO PPC port __ endgroup_if_needed(_size == 12); 8176 __ bind(done); 8177 %} 8178 ins_pipe(pipe_class_default); 8179 %} 8180 8181 // Long Division with Registers not containing constants. 8182 instruct divL_reg_reg_Ex(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{ 8183 match(Set dst (DivL src1 src2)); 8184 ins_cost(10*DEFAULT_COST); 8185 8186 expand %{ 8187 immL16 imm %{ (int)-1 %} 8188 flagsReg tmp1; 8189 cmpL_reg_imm16(tmp1, src2, imm); // check src2 == -1 8190 divL_reg_regnotMinus1(dst, src1, src2); // dst = src1 / src2 8191 cmovL_bne_negL_reg(dst, tmp1, src1); // cmove dst = neg(src1) if src2 == -1 8192 %} 8193 %} 8194 8195 // Integer Remainder with registers. 8196 instruct modI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ 8197 match(Set dst (ModI src1 src2)); 8198 ins_cost(10*DEFAULT_COST); 8199 8200 expand %{ 8201 immI16 imm %{ (int)-1 %} 8202 flagsReg tmp1; 8203 iRegIdst tmp2; 8204 iRegIdst tmp3; 8205 cmpI_reg_imm16(tmp1, src2, imm); // check src2 == -1 8206 divI_reg_regnotMinus1(tmp2, src1, src2); // tmp2 = src1 / src2 8207 cmovI_bne_negI_reg(tmp2, tmp1, src1); // cmove tmp2 = neg(src1) if src2 == -1 8208 mulI_reg_reg(tmp3, src2, tmp2); // tmp3 = src2 * tmp2 8209 subI_reg_reg(dst, src1, tmp3); // dst = src1 - tmp3 8210 %} 8211 %} 8212 8213 // Long Remainder with registers 8214 instruct modL_reg_reg_Ex(iRegLdst dst, iRegLsrc src1, iRegLsrc src2, flagsRegCR0 cr0) %{ 8215 match(Set dst (ModL src1 src2)); 8216 ins_cost(10*DEFAULT_COST); 8217 8218 expand %{ 8219 immL16 imm %{ (int)-1 %} 8220 flagsReg tmp1; 8221 iRegLdst tmp2; 8222 iRegLdst tmp3; 8223 cmpL_reg_imm16(tmp1, src2, imm); // check src2 == -1 8224 divL_reg_regnotMinus1(tmp2, src1, src2); // tmp2 = src1 / src2 8225 cmovL_bne_negL_reg(tmp2, tmp1, src1); // cmove tmp2 = neg(src1) if src2 == -1 8226 mulL_reg_reg(tmp3, src2, tmp2); // tmp3 = src2 * tmp2 8227 subL_reg_reg(dst, src1, tmp3); // dst = src1 - tmp3 8228 %} 8229 %} 8230 8231 // Integer Shift Instructions 8232 8233 // Register Shift Left 8234 8235 // Clear all but the lowest #mask bits. 8236 // Used to normalize shift amounts in registers. 8237 instruct maskI_reg_imm(iRegIdst dst, iRegIsrc src, uimmI6 mask) %{ 8238 // no match-rule, false predicate 8239 effect(DEF dst, USE src, USE mask); 8240 predicate(false); 8241 8242 format %{ "MASK $dst, $src, $mask \t// clear $mask upper bits" %} 8243 size(4); 8244 ins_encode %{ 8245 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl); 8246 __ clrldi($dst$$Register, $src$$Register, $mask$$constant); 8247 %} 8248 ins_pipe(pipe_class_default); 8249 %} 8250 8251 instruct lShiftI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ 8252 // no match-rule, false predicate 8253 effect(DEF dst, USE src1, USE src2); 8254 predicate(false); 8255 8256 format %{ "SLW $dst, $src1, $src2" %} 8257 size(4); 8258 ins_encode %{ 8259 // TODO: PPC port $archOpcode(ppc64Opcode_slw); 8260 __ slw($dst$$Register, $src1$$Register, $src2$$Register); 8261 %} 8262 ins_pipe(pipe_class_default); 8263 %} 8264 8265 instruct lShiftI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ 8266 match(Set dst (LShiftI src1 src2)); 8267 ins_cost(DEFAULT_COST*2); 8268 expand %{ 8269 uimmI6 mask %{ 0x3b /* clear 59 bits, keep 5 */ %} 8270 iRegIdst tmpI; 8271 maskI_reg_imm(tmpI, src2, mask); 8272 lShiftI_reg_reg(dst, src1, tmpI); 8273 %} 8274 %} 8275 8276 // Register Shift Left Immediate 8277 instruct lShiftI_reg_imm(iRegIdst dst, iRegIsrc src1, immI src2) %{ 8278 match(Set dst (LShiftI src1 src2)); 8279 8280 format %{ "SLWI $dst, $src1, ($src2 & 0x1f)" %} 8281 size(4); 8282 ins_encode %{ 8283 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm); 8284 __ slwi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x1f); 8285 %} 8286 ins_pipe(pipe_class_default); 8287 %} 8288 8289 // AndI with negpow2-constant + LShiftI 8290 instruct lShiftI_andI_immInegpow2_imm5(iRegIdst dst, iRegIsrc src1, immInegpow2 src2, uimmI5 src3) %{ 8291 match(Set dst (LShiftI (AndI src1 src2) src3)); 8292 predicate(UseRotateAndMaskInstructionsPPC64); 8293 8294 format %{ "RLWINM $dst, lShiftI(AndI($src1, $src2), $src3)" %} 8295 size(4); 8296 ins_encode %{ 8297 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm); // FIXME: assert that rlwinm is equal to addi 8298 long src2 = $src2$$constant; 8299 long src3 = $src3$$constant; 8300 long maskbits = src3 + log2_long((jlong) (julong) (juint) -src2); 8301 if (maskbits >= 32) { 8302 __ li($dst$$Register, 0); // addi 8303 } else { 8304 __ rlwinm($dst$$Register, $src1$$Register, src3 & 0x1f, 0, (31-maskbits) & 0x1f); 8305 } 8306 %} 8307 ins_pipe(pipe_class_default); 8308 %} 8309 8310 // RShiftI + AndI with negpow2-constant + LShiftI 8311 instruct lShiftI_andI_immInegpow2_rShiftI_imm5(iRegIdst dst, iRegIsrc src1, immInegpow2 src2, uimmI5 src3) %{ 8312 match(Set dst (LShiftI (AndI (RShiftI src1 src3) src2) src3)); 8313 predicate(UseRotateAndMaskInstructionsPPC64); 8314 8315 format %{ "RLWINM $dst, lShiftI(AndI(RShiftI($src1, $src3), $src2), $src3)" %} 8316 size(4); 8317 ins_encode %{ 8318 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm); // FIXME: assert that rlwinm is equal to addi 8319 long src2 = $src2$$constant; 8320 long src3 = $src3$$constant; 8321 long maskbits = src3 + log2_long((jlong) (julong) (juint) -src2); 8322 if (maskbits >= 32) { 8323 __ li($dst$$Register, 0); // addi 8324 } else { 8325 __ rlwinm($dst$$Register, $src1$$Register, 0, 0, (31-maskbits) & 0x1f); 8326 } 8327 %} 8328 ins_pipe(pipe_class_default); 8329 %} 8330 8331 instruct lShiftL_regL_regI(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{ 8332 // no match-rule, false predicate 8333 effect(DEF dst, USE src1, USE src2); 8334 predicate(false); 8335 8336 format %{ "SLD $dst, $src1, $src2" %} 8337 size(4); 8338 ins_encode %{ 8339 // TODO: PPC port $archOpcode(ppc64Opcode_sld); 8340 __ sld($dst$$Register, $src1$$Register, $src2$$Register); 8341 %} 8342 ins_pipe(pipe_class_default); 8343 %} 8344 8345 // Register Shift Left 8346 instruct lShiftL_regL_regI_Ex(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{ 8347 match(Set dst (LShiftL src1 src2)); 8348 ins_cost(DEFAULT_COST*2); 8349 expand %{ 8350 uimmI6 mask %{ 0x3a /* clear 58 bits, keep 6 */ %} 8351 iRegIdst tmpI; 8352 maskI_reg_imm(tmpI, src2, mask); 8353 lShiftL_regL_regI(dst, src1, tmpI); 8354 %} 8355 %} 8356 8357 // Register Shift Left Immediate 8358 instruct lshiftL_regL_immI(iRegLdst dst, iRegLsrc src1, immI src2) %{ 8359 match(Set dst (LShiftL src1 src2)); 8360 format %{ "SLDI $dst, $src1, ($src2 & 0x3f)" %} 8361 size(4); 8362 ins_encode %{ 8363 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr); 8364 __ sldi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f); 8365 %} 8366 ins_pipe(pipe_class_default); 8367 %} 8368 8369 // If we shift more than 32 bits, we need not convert I2L. 8370 instruct lShiftL_regI_immGE32(iRegLdst dst, iRegIsrc src1, uimmI6_ge32 src2) %{ 8371 match(Set dst (LShiftL (ConvI2L src1) src2)); 8372 ins_cost(DEFAULT_COST); 8373 8374 size(4); 8375 format %{ "SLDI $dst, i2l($src1), $src2" %} 8376 ins_encode %{ 8377 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr); 8378 __ sldi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f); 8379 %} 8380 ins_pipe(pipe_class_default); 8381 %} 8382 8383 // Shift a postivie int to the left. 8384 // Clrlsldi clears the upper 32 bits and shifts. 8385 instruct scaledPositiveI2L_lShiftL_convI2L_reg_imm6(iRegLdst dst, iRegIsrc src1, uimmI6 src2) %{ 8386 match(Set dst (LShiftL (ConvI2L src1) src2)); 8387 predicate(((ConvI2LNode*)(_kids[0]->_leaf))->type()->is_long()->is_positive_int()); 8388 8389 format %{ "SLDI $dst, i2l(positive_int($src1)), $src2" %} 8390 size(4); 8391 ins_encode %{ 8392 // TODO: PPC port $archOpcode(ppc64Opcode_rldic); 8393 __ clrlsldi($dst$$Register, $src1$$Register, 0x20, $src2$$constant); 8394 %} 8395 ins_pipe(pipe_class_default); 8396 %} 8397 8398 instruct arShiftI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ 8399 // no match-rule, false predicate 8400 effect(DEF dst, USE src1, USE src2); 8401 predicate(false); 8402 8403 format %{ "SRAW $dst, $src1, $src2" %} 8404 size(4); 8405 ins_encode %{ 8406 // TODO: PPC port $archOpcode(ppc64Opcode_sraw); 8407 __ sraw($dst$$Register, $src1$$Register, $src2$$Register); 8408 %} 8409 ins_pipe(pipe_class_default); 8410 %} 8411 8412 // Register Arithmetic Shift Right 8413 instruct arShiftI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ 8414 match(Set dst (RShiftI src1 src2)); 8415 ins_cost(DEFAULT_COST*2); 8416 expand %{ 8417 uimmI6 mask %{ 0x3b /* clear 59 bits, keep 5 */ %} 8418 iRegIdst tmpI; 8419 maskI_reg_imm(tmpI, src2, mask); 8420 arShiftI_reg_reg(dst, src1, tmpI); 8421 %} 8422 %} 8423 8424 // Register Arithmetic Shift Right Immediate 8425 instruct arShiftI_reg_imm(iRegIdst dst, iRegIsrc src1, immI src2) %{ 8426 match(Set dst (RShiftI src1 src2)); 8427 8428 format %{ "SRAWI $dst, $src1, ($src2 & 0x1f)" %} 8429 size(4); 8430 ins_encode %{ 8431 // TODO: PPC port $archOpcode(ppc64Opcode_srawi); 8432 __ srawi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x1f); 8433 %} 8434 ins_pipe(pipe_class_default); 8435 %} 8436 8437 instruct arShiftL_regL_regI(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{ 8438 // no match-rule, false predicate 8439 effect(DEF dst, USE src1, USE src2); 8440 predicate(false); 8441 8442 format %{ "SRAD $dst, $src1, $src2" %} 8443 size(4); 8444 ins_encode %{ 8445 // TODO: PPC port $archOpcode(ppc64Opcode_srad); 8446 __ srad($dst$$Register, $src1$$Register, $src2$$Register); 8447 %} 8448 ins_pipe(pipe_class_default); 8449 %} 8450 8451 // Register Shift Right Arithmetic Long 8452 instruct arShiftL_regL_regI_Ex(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{ 8453 match(Set dst (RShiftL src1 src2)); 8454 ins_cost(DEFAULT_COST*2); 8455 8456 expand %{ 8457 uimmI6 mask %{ 0x3a /* clear 58 bits, keep 6 */ %} 8458 iRegIdst tmpI; 8459 maskI_reg_imm(tmpI, src2, mask); 8460 arShiftL_regL_regI(dst, src1, tmpI); 8461 %} 8462 %} 8463 8464 // Register Shift Right Immediate 8465 instruct arShiftL_regL_immI(iRegLdst dst, iRegLsrc src1, immI src2) %{ 8466 match(Set dst (RShiftL src1 src2)); 8467 8468 format %{ "SRADI $dst, $src1, ($src2 & 0x3f)" %} 8469 size(4); 8470 ins_encode %{ 8471 // TODO: PPC port $archOpcode(ppc64Opcode_sradi); 8472 __ sradi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f); 8473 %} 8474 ins_pipe(pipe_class_default); 8475 %} 8476 8477 // RShiftL + ConvL2I 8478 instruct convL2I_arShiftL_regL_immI(iRegIdst dst, iRegLsrc src1, immI src2) %{ 8479 match(Set dst (ConvL2I (RShiftL src1 src2))); 8480 8481 format %{ "SRADI $dst, $src1, ($src2 & 0x3f) \t// long + l2i" %} 8482 size(4); 8483 ins_encode %{ 8484 // TODO: PPC port $archOpcode(ppc64Opcode_sradi); 8485 __ sradi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f); 8486 %} 8487 ins_pipe(pipe_class_default); 8488 %} 8489 8490 instruct urShiftI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ 8491 // no match-rule, false predicate 8492 effect(DEF dst, USE src1, USE src2); 8493 predicate(false); 8494 8495 format %{ "SRW $dst, $src1, $src2" %} 8496 size(4); 8497 ins_encode %{ 8498 // TODO: PPC port $archOpcode(ppc64Opcode_srw); 8499 __ srw($dst$$Register, $src1$$Register, $src2$$Register); 8500 %} 8501 ins_pipe(pipe_class_default); 8502 %} 8503 8504 // Register Shift Right 8505 instruct urShiftI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ 8506 match(Set dst (URShiftI src1 src2)); 8507 ins_cost(DEFAULT_COST*2); 8508 8509 expand %{ 8510 uimmI6 mask %{ 0x3b /* clear 59 bits, keep 5 */ %} 8511 iRegIdst tmpI; 8512 maskI_reg_imm(tmpI, src2, mask); 8513 urShiftI_reg_reg(dst, src1, tmpI); 8514 %} 8515 %} 8516 8517 // Register Shift Right Immediate 8518 instruct urShiftI_reg_imm(iRegIdst dst, iRegIsrc src1, immI src2) %{ 8519 match(Set dst (URShiftI src1 src2)); 8520 8521 format %{ "SRWI $dst, $src1, ($src2 & 0x1f)" %} 8522 size(4); 8523 ins_encode %{ 8524 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm); 8525 __ srwi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x1f); 8526 %} 8527 ins_pipe(pipe_class_default); 8528 %} 8529 8530 instruct urShiftL_regL_regI(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{ 8531 // no match-rule, false predicate 8532 effect(DEF dst, USE src1, USE src2); 8533 predicate(false); 8534 8535 format %{ "SRD $dst, $src1, $src2" %} 8536 size(4); 8537 ins_encode %{ 8538 // TODO: PPC port $archOpcode(ppc64Opcode_srd); 8539 __ srd($dst$$Register, $src1$$Register, $src2$$Register); 8540 %} 8541 ins_pipe(pipe_class_default); 8542 %} 8543 8544 // Register Shift Right 8545 instruct urShiftL_regL_regI_Ex(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{ 8546 match(Set dst (URShiftL src1 src2)); 8547 ins_cost(DEFAULT_COST*2); 8548 8549 expand %{ 8550 uimmI6 mask %{ 0x3a /* clear 58 bits, keep 6 */ %} 8551 iRegIdst tmpI; 8552 maskI_reg_imm(tmpI, src2, mask); 8553 urShiftL_regL_regI(dst, src1, tmpI); 8554 %} 8555 %} 8556 8557 // Register Shift Right Immediate 8558 instruct urShiftL_regL_immI(iRegLdst dst, iRegLsrc src1, immI src2) %{ 8559 match(Set dst (URShiftL src1 src2)); 8560 8561 format %{ "SRDI $dst, $src1, ($src2 & 0x3f)" %} 8562 size(4); 8563 ins_encode %{ 8564 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl); 8565 __ srdi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f); 8566 %} 8567 ins_pipe(pipe_class_default); 8568 %} 8569 8570 // URShiftL + ConvL2I. 8571 instruct convL2I_urShiftL_regL_immI(iRegIdst dst, iRegLsrc src1, immI src2) %{ 8572 match(Set dst (ConvL2I (URShiftL src1 src2))); 8573 8574 format %{ "SRDI $dst, $src1, ($src2 & 0x3f) \t// long + l2i" %} 8575 size(4); 8576 ins_encode %{ 8577 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl); 8578 __ srdi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f); 8579 %} 8580 ins_pipe(pipe_class_default); 8581 %} 8582 8583 // Register Shift Right Immediate with a CastP2X 8584 instruct shrP_convP2X_reg_imm6(iRegLdst dst, iRegP_N2P src1, uimmI6 src2) %{ 8585 match(Set dst (URShiftL (CastP2X src1) src2)); 8586 8587 format %{ "SRDI $dst, $src1, $src2 \t// Cast ptr $src1 to long and shift" %} 8588 size(4); 8589 ins_encode %{ 8590 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl); 8591 __ srdi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f); 8592 %} 8593 ins_pipe(pipe_class_default); 8594 %} 8595 8596 instruct sxtI_reg(iRegIdst dst, iRegIsrc src) %{ 8597 match(Set dst (ConvL2I (ConvI2L src))); 8598 8599 format %{ "EXTSW $dst, $src \t// int->int" %} 8600 size(4); 8601 ins_encode %{ 8602 // TODO: PPC port $archOpcode(ppc64Opcode_extsw); 8603 __ extsw($dst$$Register, $src$$Register); 8604 %} 8605 ins_pipe(pipe_class_default); 8606 %} 8607 8608 //----------Rotate Instructions------------------------------------------------ 8609 8610 // Rotate Left by 8-bit immediate 8611 instruct rotlI_reg_immi8(iRegIdst dst, iRegIsrc src, immI8 lshift, immI8 rshift) %{ 8612 match(Set dst (OrI (LShiftI src lshift) (URShiftI src rshift))); 8613 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f)); 8614 8615 format %{ "ROTLWI $dst, $src, $lshift" %} 8616 size(4); 8617 ins_encode %{ 8618 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm); 8619 __ rotlwi($dst$$Register, $src$$Register, $lshift$$constant); 8620 %} 8621 ins_pipe(pipe_class_default); 8622 %} 8623 8624 // Rotate Right by 8-bit immediate 8625 instruct rotrI_reg_immi8(iRegIdst dst, iRegIsrc src, immI8 rshift, immI8 lshift) %{ 8626 match(Set dst (OrI (URShiftI src rshift) (LShiftI src lshift))); 8627 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f)); 8628 8629 format %{ "ROTRWI $dst, $rshift" %} 8630 size(4); 8631 ins_encode %{ 8632 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm); 8633 __ rotrwi($dst$$Register, $src$$Register, $rshift$$constant); 8634 %} 8635 ins_pipe(pipe_class_default); 8636 %} 8637 8638 //----------Floating Point Arithmetic Instructions----------------------------- 8639 8640 // Add float single precision 8641 instruct addF_reg_reg(regF dst, regF src1, regF src2) %{ 8642 match(Set dst (AddF src1 src2)); 8643 8644 format %{ "FADDS $dst, $src1, $src2" %} 8645 size(4); 8646 ins_encode %{ 8647 // TODO: PPC port $archOpcode(ppc64Opcode_fadds); 8648 __ fadds($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister); 8649 %} 8650 ins_pipe(pipe_class_default); 8651 %} 8652 8653 // Add float double precision 8654 instruct addD_reg_reg(regD dst, regD src1, regD src2) %{ 8655 match(Set dst (AddD src1 src2)); 8656 8657 format %{ "FADD $dst, $src1, $src2" %} 8658 size(4); 8659 ins_encode %{ 8660 // TODO: PPC port $archOpcode(ppc64Opcode_fadd); 8661 __ fadd($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister); 8662 %} 8663 ins_pipe(pipe_class_default); 8664 %} 8665 8666 // Sub float single precision 8667 instruct subF_reg_reg(regF dst, regF src1, regF src2) %{ 8668 match(Set dst (SubF src1 src2)); 8669 8670 format %{ "FSUBS $dst, $src1, $src2" %} 8671 size(4); 8672 ins_encode %{ 8673 // TODO: PPC port $archOpcode(ppc64Opcode_fsubs); 8674 __ fsubs($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister); 8675 %} 8676 ins_pipe(pipe_class_default); 8677 %} 8678 8679 // Sub float double precision 8680 instruct subD_reg_reg(regD dst, regD src1, regD src2) %{ 8681 match(Set dst (SubD src1 src2)); 8682 format %{ "FSUB $dst, $src1, $src2" %} 8683 size(4); 8684 ins_encode %{ 8685 // TODO: PPC port $archOpcode(ppc64Opcode_fsub); 8686 __ fsub($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister); 8687 %} 8688 ins_pipe(pipe_class_default); 8689 %} 8690 8691 // Mul float single precision 8692 instruct mulF_reg_reg(regF dst, regF src1, regF src2) %{ 8693 match(Set dst (MulF src1 src2)); 8694 format %{ "FMULS $dst, $src1, $src2" %} 8695 size(4); 8696 ins_encode %{ 8697 // TODO: PPC port $archOpcode(ppc64Opcode_fmuls); 8698 __ fmuls($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister); 8699 %} 8700 ins_pipe(pipe_class_default); 8701 %} 8702 8703 // Mul float double precision 8704 instruct mulD_reg_reg(regD dst, regD src1, regD src2) %{ 8705 match(Set dst (MulD src1 src2)); 8706 format %{ "FMUL $dst, $src1, $src2" %} 8707 size(4); 8708 ins_encode %{ 8709 // TODO: PPC port $archOpcode(ppc64Opcode_fmul); 8710 __ fmul($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister); 8711 %} 8712 ins_pipe(pipe_class_default); 8713 %} 8714 8715 // Div float single precision 8716 instruct divF_reg_reg(regF dst, regF src1, regF src2) %{ 8717 match(Set dst (DivF src1 src2)); 8718 format %{ "FDIVS $dst, $src1, $src2" %} 8719 size(4); 8720 ins_encode %{ 8721 // TODO: PPC port $archOpcode(ppc64Opcode_fdivs); 8722 __ fdivs($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister); 8723 %} 8724 ins_pipe(pipe_class_default); 8725 %} 8726 8727 // Div float double precision 8728 instruct divD_reg_reg(regD dst, regD src1, regD src2) %{ 8729 match(Set dst (DivD src1 src2)); 8730 format %{ "FDIV $dst, $src1, $src2" %} 8731 size(4); 8732 ins_encode %{ 8733 // TODO: PPC port $archOpcode(ppc64Opcode_fdiv); 8734 __ fdiv($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister); 8735 %} 8736 ins_pipe(pipe_class_default); 8737 %} 8738 8739 // Absolute float single precision 8740 instruct absF_reg(regF dst, regF src) %{ 8741 match(Set dst (AbsF src)); 8742 format %{ "FABS $dst, $src \t// float" %} 8743 size(4); 8744 ins_encode %{ 8745 // TODO: PPC port $archOpcode(ppc64Opcode_fabs); 8746 __ fabs($dst$$FloatRegister, $src$$FloatRegister); 8747 %} 8748 ins_pipe(pipe_class_default); 8749 %} 8750 8751 // Absolute float double precision 8752 instruct absD_reg(regD dst, regD src) %{ 8753 match(Set dst (AbsD src)); 8754 format %{ "FABS $dst, $src \t// double" %} 8755 size(4); 8756 ins_encode %{ 8757 // TODO: PPC port $archOpcode(ppc64Opcode_fabs); 8758 __ fabs($dst$$FloatRegister, $src$$FloatRegister); 8759 %} 8760 ins_pipe(pipe_class_default); 8761 %} 8762 8763 instruct negF_reg(regF dst, regF src) %{ 8764 match(Set dst (NegF src)); 8765 format %{ "FNEG $dst, $src \t// float" %} 8766 size(4); 8767 ins_encode %{ 8768 // TODO: PPC port $archOpcode(ppc64Opcode_fneg); 8769 __ fneg($dst$$FloatRegister, $src$$FloatRegister); 8770 %} 8771 ins_pipe(pipe_class_default); 8772 %} 8773 8774 instruct negD_reg(regD dst, regD src) %{ 8775 match(Set dst (NegD src)); 8776 format %{ "FNEG $dst, $src \t// double" %} 8777 size(4); 8778 ins_encode %{ 8779 // TODO: PPC port $archOpcode(ppc64Opcode_fneg); 8780 __ fneg($dst$$FloatRegister, $src$$FloatRegister); 8781 %} 8782 ins_pipe(pipe_class_default); 8783 %} 8784 8785 // AbsF + NegF. 8786 instruct negF_absF_reg(regF dst, regF src) %{ 8787 match(Set dst (NegF (AbsF src))); 8788 format %{ "FNABS $dst, $src \t// float" %} 8789 size(4); 8790 ins_encode %{ 8791 // TODO: PPC port $archOpcode(ppc64Opcode_fnabs); 8792 __ fnabs($dst$$FloatRegister, $src$$FloatRegister); 8793 %} 8794 ins_pipe(pipe_class_default); 8795 %} 8796 8797 // AbsD + NegD. 8798 instruct negD_absD_reg(regD dst, regD src) %{ 8799 match(Set dst (NegD (AbsD src))); 8800 format %{ "FNABS $dst, $src \t// double" %} 8801 size(4); 8802 ins_encode %{ 8803 // TODO: PPC port $archOpcode(ppc64Opcode_fnabs); 8804 __ fnabs($dst$$FloatRegister, $src$$FloatRegister); 8805 %} 8806 ins_pipe(pipe_class_default); 8807 %} 8808 8809 // VM_Version::has_fsqrt() decides if this node will be used. 8810 // Sqrt float double precision 8811 instruct sqrtD_reg(regD dst, regD src) %{ 8812 match(Set dst (SqrtD src)); 8813 format %{ "FSQRT $dst, $src" %} 8814 size(4); 8815 ins_encode %{ 8816 // TODO: PPC port $archOpcode(ppc64Opcode_fsqrt); 8817 __ fsqrt($dst$$FloatRegister, $src$$FloatRegister); 8818 %} 8819 ins_pipe(pipe_class_default); 8820 %} 8821 8822 // Single-precision sqrt. 8823 instruct sqrtF_reg(regF dst, regF src) %{ 8824 match(Set dst (ConvD2F (SqrtD (ConvF2D src)))); 8825 predicate(VM_Version::has_fsqrts()); 8826 ins_cost(DEFAULT_COST); 8827 8828 format %{ "FSQRTS $dst, $src" %} 8829 size(4); 8830 ins_encode %{ 8831 // TODO: PPC port $archOpcode(ppc64Opcode_fsqrts); 8832 __ fsqrts($dst$$FloatRegister, $src$$FloatRegister); 8833 %} 8834 ins_pipe(pipe_class_default); 8835 %} 8836 8837 instruct roundDouble_nop(regD dst) %{ 8838 match(Set dst (RoundDouble dst)); 8839 ins_cost(0); 8840 8841 format %{ " -- \t// RoundDouble not needed - empty" %} 8842 size(0); 8843 // PPC results are already "rounded" (i.e., normal-format IEEE). 8844 ins_encode( /*empty*/ ); 8845 ins_pipe(pipe_class_default); 8846 %} 8847 8848 instruct roundFloat_nop(regF dst) %{ 8849 match(Set dst (RoundFloat dst)); 8850 ins_cost(0); 8851 8852 format %{ " -- \t// RoundFloat not needed - empty" %} 8853 size(0); 8854 // PPC results are already "rounded" (i.e., normal-format IEEE). 8855 ins_encode( /*empty*/ ); 8856 ins_pipe(pipe_class_default); 8857 %} 8858 8859 //----------Logical Instructions----------------------------------------------- 8860 8861 // And Instructions 8862 8863 // Register And 8864 instruct andI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ 8865 match(Set dst (AndI src1 src2)); 8866 format %{ "AND $dst, $src1, $src2" %} 8867 size(4); 8868 ins_encode %{ 8869 // TODO: PPC port $archOpcode(ppc64Opcode_and); 8870 __ andr($dst$$Register, $src1$$Register, $src2$$Register); 8871 %} 8872 ins_pipe(pipe_class_default); 8873 %} 8874 8875 // Immediate And 8876 instruct andI_reg_uimm16(iRegIdst dst, iRegIsrc src1, uimmI16 src2, flagsRegCR0 cr0) %{ 8877 match(Set dst (AndI src1 src2)); 8878 effect(KILL cr0); 8879 8880 format %{ "ANDI $dst, $src1, $src2" %} 8881 size(4); 8882 ins_encode %{ 8883 // TODO: PPC port $archOpcode(ppc64Opcode_andi_); 8884 // FIXME: avoid andi_ ? 8885 __ andi_($dst$$Register, $src1$$Register, $src2$$constant); 8886 %} 8887 ins_pipe(pipe_class_default); 8888 %} 8889 8890 // Immediate And where the immediate is a negative power of 2. 8891 instruct andI_reg_immInegpow2(iRegIdst dst, iRegIsrc src1, immInegpow2 src2) %{ 8892 match(Set dst (AndI src1 src2)); 8893 format %{ "ANDWI $dst, $src1, $src2" %} 8894 size(4); 8895 ins_encode %{ 8896 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr); 8897 __ clrrdi($dst$$Register, $src1$$Register, log2_long((jlong)(julong)(juint)-($src2$$constant))); 8898 %} 8899 ins_pipe(pipe_class_default); 8900 %} 8901 8902 instruct andI_reg_immIpow2minus1(iRegIdst dst, iRegIsrc src1, immIpow2minus1 src2) %{ 8903 match(Set dst (AndI src1 src2)); 8904 format %{ "ANDWI $dst, $src1, $src2" %} 8905 size(4); 8906 ins_encode %{ 8907 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl); 8908 __ clrldi($dst$$Register, $src1$$Register, 64-log2_long((((jlong) $src2$$constant)+1))); 8909 %} 8910 ins_pipe(pipe_class_default); 8911 %} 8912 8913 instruct andI_reg_immIpowerOf2(iRegIdst dst, iRegIsrc src1, immIpowerOf2 src2) %{ 8914 match(Set dst (AndI src1 src2)); 8915 predicate(UseRotateAndMaskInstructionsPPC64); 8916 format %{ "ANDWI $dst, $src1, $src2" %} 8917 size(4); 8918 ins_encode %{ 8919 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm); 8920 __ rlwinm($dst$$Register, $src1$$Register, 0, 8921 (31-log2_long((jlong) $src2$$constant)) & 0x1f, (31-log2_long((jlong) $src2$$constant)) & 0x1f); 8922 %} 8923 ins_pipe(pipe_class_default); 8924 %} 8925 8926 // Register And Long 8927 instruct andL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{ 8928 match(Set dst (AndL src1 src2)); 8929 ins_cost(DEFAULT_COST); 8930 8931 format %{ "AND $dst, $src1, $src2 \t// long" %} 8932 size(4); 8933 ins_encode %{ 8934 // TODO: PPC port $archOpcode(ppc64Opcode_and); 8935 __ andr($dst$$Register, $src1$$Register, $src2$$Register); 8936 %} 8937 ins_pipe(pipe_class_default); 8938 %} 8939 8940 // Immediate And long 8941 instruct andL_reg_uimm16(iRegLdst dst, iRegLsrc src1, uimmL16 src2, flagsRegCR0 cr0) %{ 8942 match(Set dst (AndL src1 src2)); 8943 effect(KILL cr0); 8944 ins_cost(DEFAULT_COST); 8945 8946 format %{ "ANDI $dst, $src1, $src2 \t// long" %} 8947 size(4); 8948 ins_encode %{ 8949 // TODO: PPC port $archOpcode(ppc64Opcode_andi_); 8950 // FIXME: avoid andi_ ? 8951 __ andi_($dst$$Register, $src1$$Register, $src2$$constant); 8952 %} 8953 ins_pipe(pipe_class_default); 8954 %} 8955 8956 // Immediate And Long where the immediate is a negative power of 2. 8957 instruct andL_reg_immLnegpow2(iRegLdst dst, iRegLsrc src1, immLnegpow2 src2) %{ 8958 match(Set dst (AndL src1 src2)); 8959 format %{ "ANDDI $dst, $src1, $src2" %} 8960 size(4); 8961 ins_encode %{ 8962 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr); 8963 __ clrrdi($dst$$Register, $src1$$Register, log2_long((jlong)-$src2$$constant)); 8964 %} 8965 ins_pipe(pipe_class_default); 8966 %} 8967 8968 instruct andL_reg_immLpow2minus1(iRegLdst dst, iRegLsrc src1, immLpow2minus1 src2) %{ 8969 match(Set dst (AndL src1 src2)); 8970 format %{ "ANDDI $dst, $src1, $src2" %} 8971 size(4); 8972 ins_encode %{ 8973 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl); 8974 __ clrldi($dst$$Register, $src1$$Register, 64-log2_long((((jlong) $src2$$constant)+1))); 8975 %} 8976 ins_pipe(pipe_class_default); 8977 %} 8978 8979 // AndL + ConvL2I. 8980 instruct convL2I_andL_reg_immLpow2minus1(iRegIdst dst, iRegLsrc src1, immLpow2minus1 src2) %{ 8981 match(Set dst (ConvL2I (AndL src1 src2))); 8982 ins_cost(DEFAULT_COST); 8983 8984 format %{ "ANDDI $dst, $src1, $src2 \t// long + l2i" %} 8985 size(4); 8986 ins_encode %{ 8987 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl); 8988 __ clrldi($dst$$Register, $src1$$Register, 64-log2_long((((jlong) $src2$$constant)+1))); 8989 %} 8990 ins_pipe(pipe_class_default); 8991 %} 8992 8993 // Or Instructions 8994 8995 // Register Or 8996 instruct orI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ 8997 match(Set dst (OrI src1 src2)); 8998 format %{ "OR $dst, $src1, $src2" %} 8999 size(4); 9000 ins_encode %{ 9001 // TODO: PPC port $archOpcode(ppc64Opcode_or); 9002 __ or_unchecked($dst$$Register, $src1$$Register, $src2$$Register); 9003 %} 9004 ins_pipe(pipe_class_default); 9005 %} 9006 9007 // Expand does not work with above instruct. (??) 9008 instruct orI_reg_reg_2(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ 9009 // no match-rule 9010 effect(DEF dst, USE src1, USE src2); 9011 format %{ "OR $dst, $src1, $src2" %} 9012 size(4); 9013 ins_encode %{ 9014 // TODO: PPC port $archOpcode(ppc64Opcode_or); 9015 __ or_unchecked($dst$$Register, $src1$$Register, $src2$$Register); 9016 %} 9017 ins_pipe(pipe_class_default); 9018 %} 9019 9020 instruct tree_orI_orI_orI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2, iRegIsrc src3, iRegIsrc src4) %{ 9021 match(Set dst (OrI (OrI (OrI src1 src2) src3) src4)); 9022 ins_cost(DEFAULT_COST*3); 9023 9024 expand %{ 9025 // FIXME: we should do this in the ideal world. 9026 iRegIdst tmp1; 9027 iRegIdst tmp2; 9028 orI_reg_reg(tmp1, src1, src2); 9029 orI_reg_reg_2(tmp2, src3, src4); // Adlc complains about orI_reg_reg. 9030 orI_reg_reg(dst, tmp1, tmp2); 9031 %} 9032 %} 9033 9034 // Immediate Or 9035 instruct orI_reg_uimm16(iRegIdst dst, iRegIsrc src1, uimmI16 src2) %{ 9036 match(Set dst (OrI src1 src2)); 9037 format %{ "ORI $dst, $src1, $src2" %} 9038 size(4); 9039 ins_encode %{ 9040 // TODO: PPC port $archOpcode(ppc64Opcode_ori); 9041 __ ori($dst$$Register, $src1$$Register, ($src2$$constant) & 0xFFFF); 9042 %} 9043 ins_pipe(pipe_class_default); 9044 %} 9045 9046 // Register Or Long 9047 instruct orL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{ 9048 match(Set dst (OrL src1 src2)); 9049 ins_cost(DEFAULT_COST); 9050 9051 size(4); 9052 format %{ "OR $dst, $src1, $src2 \t// long" %} 9053 ins_encode %{ 9054 // TODO: PPC port $archOpcode(ppc64Opcode_or); 9055 __ or_unchecked($dst$$Register, $src1$$Register, $src2$$Register); 9056 %} 9057 ins_pipe(pipe_class_default); 9058 %} 9059 9060 // OrL + ConvL2I. 9061 instruct orI_regL_regL(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{ 9062 match(Set dst (ConvL2I (OrL src1 src2))); 9063 ins_cost(DEFAULT_COST); 9064 9065 format %{ "OR $dst, $src1, $src2 \t// long + l2i" %} 9066 size(4); 9067 ins_encode %{ 9068 // TODO: PPC port $archOpcode(ppc64Opcode_or); 9069 __ or_unchecked($dst$$Register, $src1$$Register, $src2$$Register); 9070 %} 9071 ins_pipe(pipe_class_default); 9072 %} 9073 9074 // Immediate Or long 9075 instruct orL_reg_uimm16(iRegLdst dst, iRegLsrc src1, uimmL16 con) %{ 9076 match(Set dst (OrL src1 con)); 9077 ins_cost(DEFAULT_COST); 9078 9079 format %{ "ORI $dst, $src1, $con \t// long" %} 9080 size(4); 9081 ins_encode %{ 9082 // TODO: PPC port $archOpcode(ppc64Opcode_ori); 9083 __ ori($dst$$Register, $src1$$Register, ($con$$constant) & 0xFFFF); 9084 %} 9085 ins_pipe(pipe_class_default); 9086 %} 9087 9088 // Xor Instructions 9089 9090 // Register Xor 9091 instruct xorI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ 9092 match(Set dst (XorI src1 src2)); 9093 format %{ "XOR $dst, $src1, $src2" %} 9094 size(4); 9095 ins_encode %{ 9096 // TODO: PPC port $archOpcode(ppc64Opcode_xor); 9097 __ xorr($dst$$Register, $src1$$Register, $src2$$Register); 9098 %} 9099 ins_pipe(pipe_class_default); 9100 %} 9101 9102 // Expand does not work with above instruct. (??) 9103 instruct xorI_reg_reg_2(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ 9104 // no match-rule 9105 effect(DEF dst, USE src1, USE src2); 9106 format %{ "XOR $dst, $src1, $src2" %} 9107 size(4); 9108 ins_encode %{ 9109 // TODO: PPC port $archOpcode(ppc64Opcode_xor); 9110 __ xorr($dst$$Register, $src1$$Register, $src2$$Register); 9111 %} 9112 ins_pipe(pipe_class_default); 9113 %} 9114 9115 instruct tree_xorI_xorI_xorI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2, iRegIsrc src3, iRegIsrc src4) %{ 9116 match(Set dst (XorI (XorI (XorI src1 src2) src3) src4)); 9117 ins_cost(DEFAULT_COST*3); 9118 9119 expand %{ 9120 // FIXME: we should do this in the ideal world. 9121 iRegIdst tmp1; 9122 iRegIdst tmp2; 9123 xorI_reg_reg(tmp1, src1, src2); 9124 xorI_reg_reg_2(tmp2, src3, src4); // Adlc complains about xorI_reg_reg. 9125 xorI_reg_reg(dst, tmp1, tmp2); 9126 %} 9127 %} 9128 9129 // Immediate Xor 9130 instruct xorI_reg_uimm16(iRegIdst dst, iRegIsrc src1, uimmI16 src2) %{ 9131 match(Set dst (XorI src1 src2)); 9132 format %{ "XORI $dst, $src1, $src2" %} 9133 size(4); 9134 ins_encode %{ 9135 // TODO: PPC port $archOpcode(ppc64Opcode_xori); 9136 __ xori($dst$$Register, $src1$$Register, $src2$$constant); 9137 %} 9138 ins_pipe(pipe_class_default); 9139 %} 9140 9141 // Register Xor Long 9142 instruct xorL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{ 9143 match(Set dst (XorL src1 src2)); 9144 ins_cost(DEFAULT_COST); 9145 9146 format %{ "XOR $dst, $src1, $src2 \t// long" %} 9147 size(4); 9148 ins_encode %{ 9149 // TODO: PPC port $archOpcode(ppc64Opcode_xor); 9150 __ xorr($dst$$Register, $src1$$Register, $src2$$Register); 9151 %} 9152 ins_pipe(pipe_class_default); 9153 %} 9154 9155 // XorL + ConvL2I. 9156 instruct xorI_regL_regL(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{ 9157 match(Set dst (ConvL2I (XorL src1 src2))); 9158 ins_cost(DEFAULT_COST); 9159 9160 format %{ "XOR $dst, $src1, $src2 \t// long + l2i" %} 9161 size(4); 9162 ins_encode %{ 9163 // TODO: PPC port $archOpcode(ppc64Opcode_xor); 9164 __ xorr($dst$$Register, $src1$$Register, $src2$$Register); 9165 %} 9166 ins_pipe(pipe_class_default); 9167 %} 9168 9169 // Immediate Xor Long 9170 instruct xorL_reg_uimm16(iRegLdst dst, iRegLsrc src1, uimmL16 src2) %{ 9171 match(Set dst (XorL src1 src2)); 9172 ins_cost(DEFAULT_COST); 9173 9174 format %{ "XORI $dst, $src1, $src2 \t// long" %} 9175 size(4); 9176 ins_encode %{ 9177 // TODO: PPC port $archOpcode(ppc64Opcode_xori); 9178 __ xori($dst$$Register, $src1$$Register, $src2$$constant); 9179 %} 9180 ins_pipe(pipe_class_default); 9181 %} 9182 9183 instruct notI_reg(iRegIdst dst, iRegIsrc src1, immI_minus1 src2) %{ 9184 match(Set dst (XorI src1 src2)); 9185 ins_cost(DEFAULT_COST); 9186 9187 format %{ "NOT $dst, $src1 ($src2)" %} 9188 size(4); 9189 ins_encode %{ 9190 // TODO: PPC port $archOpcode(ppc64Opcode_nor); 9191 __ nor($dst$$Register, $src1$$Register, $src1$$Register); 9192 %} 9193 ins_pipe(pipe_class_default); 9194 %} 9195 9196 instruct notL_reg(iRegLdst dst, iRegLsrc src1, immL_minus1 src2) %{ 9197 match(Set dst (XorL src1 src2)); 9198 ins_cost(DEFAULT_COST); 9199 9200 format %{ "NOT $dst, $src1 ($src2) \t// long" %} 9201 size(4); 9202 ins_encode %{ 9203 // TODO: PPC port $archOpcode(ppc64Opcode_nor); 9204 __ nor($dst$$Register, $src1$$Register, $src1$$Register); 9205 %} 9206 ins_pipe(pipe_class_default); 9207 %} 9208 9209 // And-complement 9210 instruct andcI_reg_reg(iRegIdst dst, iRegIsrc src1, immI_minus1 src2, iRegIsrc src3) %{ 9211 match(Set dst (AndI (XorI src1 src2) src3)); 9212 ins_cost(DEFAULT_COST); 9213 9214 format %{ "ANDW $dst, xori($src1, $src2), $src3" %} 9215 size(4); 9216 ins_encode( enc_andc(dst, src3, src1) ); 9217 ins_pipe(pipe_class_default); 9218 %} 9219 9220 // And-complement 9221 instruct andcL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{ 9222 // no match-rule, false predicate 9223 effect(DEF dst, USE src1, USE src2); 9224 predicate(false); 9225 9226 format %{ "ANDC $dst, $src1, $src2" %} 9227 size(4); 9228 ins_encode %{ 9229 // TODO: PPC port $archOpcode(ppc64Opcode_andc); 9230 __ andc($dst$$Register, $src1$$Register, $src2$$Register); 9231 %} 9232 ins_pipe(pipe_class_default); 9233 %} 9234 9235 //----------Moves between int/long and float/double---------------------------- 9236 // 9237 // The following rules move values from int/long registers/stack-locations 9238 // to float/double registers/stack-locations and vice versa, without doing any 9239 // conversions. These rules are used to implement the bit-conversion methods 9240 // of java.lang.Float etc., e.g. 9241 // int floatToIntBits(float value) 9242 // float intBitsToFloat(int bits) 9243 // 9244 // Notes on the implementation on ppc64: 9245 // We only provide rules which move between a register and a stack-location, 9246 // because we always have to go through memory when moving between a float 9247 // register and an integer register. 9248 9249 //---------- Chain stack slots between similar types -------- 9250 9251 // These are needed so that the rules below can match. 9252 9253 // Load integer from stack slot 9254 instruct stkI_to_regI(iRegIdst dst, stackSlotI src) %{ 9255 match(Set dst src); 9256 ins_cost(MEMORY_REF_COST); 9257 9258 format %{ "LWZ $dst, $src" %} 9259 size(4); 9260 ins_encode( enc_lwz(dst, src) ); 9261 ins_pipe(pipe_class_memory); 9262 %} 9263 9264 // Store integer to stack slot 9265 instruct regI_to_stkI(stackSlotI dst, iRegIsrc src) %{ 9266 match(Set dst src); 9267 ins_cost(MEMORY_REF_COST); 9268 9269 format %{ "STW $src, $dst \t// stk" %} 9270 size(4); 9271 ins_encode( enc_stw(src, dst) ); // rs=rt 9272 ins_pipe(pipe_class_memory); 9273 %} 9274 9275 // Load long from stack slot 9276 instruct stkL_to_regL(iRegLdst dst, stackSlotL src) %{ 9277 match(Set dst src); 9278 ins_cost(MEMORY_REF_COST); 9279 9280 format %{ "LD $dst, $src \t// long" %} 9281 size(4); 9282 ins_encode( enc_ld(dst, src) ); 9283 ins_pipe(pipe_class_memory); 9284 %} 9285 9286 // Store long to stack slot 9287 instruct regL_to_stkL(stackSlotL dst, iRegLsrc src) %{ 9288 match(Set dst src); 9289 ins_cost(MEMORY_REF_COST); 9290 9291 format %{ "STD $src, $dst \t// long" %} 9292 size(4); 9293 ins_encode( enc_std(src, dst) ); // rs=rt 9294 ins_pipe(pipe_class_memory); 9295 %} 9296 9297 //----------Moves between int and float 9298 9299 // Move float value from float stack-location to integer register. 9300 instruct moveF2I_stack_reg(iRegIdst dst, stackSlotF src) %{ 9301 match(Set dst (MoveF2I src)); 9302 ins_cost(MEMORY_REF_COST); 9303 9304 format %{ "LWZ $dst, $src \t// MoveF2I" %} 9305 size(4); 9306 ins_encode( enc_lwz(dst, src) ); 9307 ins_pipe(pipe_class_memory); 9308 %} 9309 9310 // Move float value from float register to integer stack-location. 9311 instruct moveF2I_reg_stack(stackSlotI dst, regF src) %{ 9312 match(Set dst (MoveF2I src)); 9313 ins_cost(MEMORY_REF_COST); 9314 9315 format %{ "STFS $src, $dst \t// MoveF2I" %} 9316 size(4); 9317 ins_encode( enc_stfs(src, dst) ); 9318 ins_pipe(pipe_class_memory); 9319 %} 9320 9321 // Move integer value from integer stack-location to float register. 9322 instruct moveI2F_stack_reg(regF dst, stackSlotI src) %{ 9323 match(Set dst (MoveI2F src)); 9324 ins_cost(MEMORY_REF_COST); 9325 9326 format %{ "LFS $dst, $src \t// MoveI2F" %} 9327 size(4); 9328 ins_encode %{ 9329 // TODO: PPC port $archOpcode(ppc64Opcode_lfs); 9330 int Idisp = $src$$disp + frame_slots_bias($src$$base, ra_); 9331 __ lfs($dst$$FloatRegister, Idisp, $src$$base$$Register); 9332 %} 9333 ins_pipe(pipe_class_memory); 9334 %} 9335 9336 // Move integer value from integer register to float stack-location. 9337 instruct moveI2F_reg_stack(stackSlotF dst, iRegIsrc src) %{ 9338 match(Set dst (MoveI2F src)); 9339 ins_cost(MEMORY_REF_COST); 9340 9341 format %{ "STW $src, $dst \t// MoveI2F" %} 9342 size(4); 9343 ins_encode( enc_stw(src, dst) ); 9344 ins_pipe(pipe_class_memory); 9345 %} 9346 9347 //----------Moves between long and float 9348 9349 instruct moveF2L_reg_stack(stackSlotL dst, regF src) %{ 9350 // no match-rule, false predicate 9351 effect(DEF dst, USE src); 9352 predicate(false); 9353 9354 format %{ "storeD $src, $dst \t// STACK" %} 9355 size(4); 9356 ins_encode( enc_stfd(src, dst) ); 9357 ins_pipe(pipe_class_default); 9358 %} 9359 9360 //----------Moves between long and double 9361 9362 // Move double value from double stack-location to long register. 9363 instruct moveD2L_stack_reg(iRegLdst dst, stackSlotD src) %{ 9364 match(Set dst (MoveD2L src)); 9365 ins_cost(MEMORY_REF_COST); 9366 size(4); 9367 format %{ "LD $dst, $src \t// MoveD2L" %} 9368 ins_encode( enc_ld(dst, src) ); 9369 ins_pipe(pipe_class_memory); 9370 %} 9371 9372 // Move double value from double register to long stack-location. 9373 instruct moveD2L_reg_stack(stackSlotL dst, regD src) %{ 9374 match(Set dst (MoveD2L src)); 9375 effect(DEF dst, USE src); 9376 ins_cost(MEMORY_REF_COST); 9377 9378 format %{ "STFD $src, $dst \t// MoveD2L" %} 9379 size(4); 9380 ins_encode( enc_stfd(src, dst) ); 9381 ins_pipe(pipe_class_memory); 9382 %} 9383 9384 // Move long value from long stack-location to double register. 9385 instruct moveL2D_stack_reg(regD dst, stackSlotL src) %{ 9386 match(Set dst (MoveL2D src)); 9387 ins_cost(MEMORY_REF_COST); 9388 9389 format %{ "LFD $dst, $src \t// MoveL2D" %} 9390 size(4); 9391 ins_encode( enc_lfd(dst, src) ); 9392 ins_pipe(pipe_class_memory); 9393 %} 9394 9395 // Move long value from long register to double stack-location. 9396 instruct moveL2D_reg_stack(stackSlotD dst, iRegLsrc src) %{ 9397 match(Set dst (MoveL2D src)); 9398 ins_cost(MEMORY_REF_COST); 9399 9400 format %{ "STD $src, $dst \t// MoveL2D" %} 9401 size(4); 9402 ins_encode( enc_std(src, dst) ); 9403 ins_pipe(pipe_class_memory); 9404 %} 9405 9406 //----------Register Move Instructions----------------------------------------- 9407 9408 // Replicate for Superword 9409 9410 instruct moveReg(iRegLdst dst, iRegIsrc src) %{ 9411 predicate(false); 9412 effect(DEF dst, USE src); 9413 9414 format %{ "MR $dst, $src \t// replicate " %} 9415 // variable size, 0 or 4. 9416 ins_encode %{ 9417 // TODO: PPC port $archOpcode(ppc64Opcode_or); 9418 __ mr_if_needed($dst$$Register, $src$$Register); 9419 %} 9420 ins_pipe(pipe_class_default); 9421 %} 9422 9423 //----------Cast instructions (Java-level type cast)--------------------------- 9424 9425 // Cast Long to Pointer for unsafe natives. 9426 instruct castX2P(iRegPdst dst, iRegLsrc src) %{ 9427 match(Set dst (CastX2P src)); 9428 9429 format %{ "MR $dst, $src \t// Long->Ptr" %} 9430 // variable size, 0 or 4. 9431 ins_encode %{ 9432 // TODO: PPC port $archOpcode(ppc64Opcode_or); 9433 __ mr_if_needed($dst$$Register, $src$$Register); 9434 %} 9435 ins_pipe(pipe_class_default); 9436 %} 9437 9438 // Cast Pointer to Long for unsafe natives. 9439 instruct castP2X(iRegLdst dst, iRegP_N2P src) %{ 9440 match(Set dst (CastP2X src)); 9441 9442 format %{ "MR $dst, $src \t// Ptr->Long" %} 9443 // variable size, 0 or 4. 9444 ins_encode %{ 9445 // TODO: PPC port $archOpcode(ppc64Opcode_or); 9446 __ mr_if_needed($dst$$Register, $src$$Register); 9447 %} 9448 ins_pipe(pipe_class_default); 9449 %} 9450 9451 instruct castPP(iRegPdst dst) %{ 9452 match(Set dst (CastPP dst)); 9453 format %{ " -- \t// castPP of $dst" %} 9454 size(0); 9455 ins_encode( /*empty*/ ); 9456 ins_pipe(pipe_class_default); 9457 %} 9458 9459 instruct castII(iRegIdst dst) %{ 9460 match(Set dst (CastII dst)); 9461 format %{ " -- \t// castII of $dst" %} 9462 size(0); 9463 ins_encode( /*empty*/ ); 9464 ins_pipe(pipe_class_default); 9465 %} 9466 9467 instruct checkCastPP(iRegPdst dst) %{ 9468 match(Set dst (CheckCastPP dst)); 9469 format %{ " -- \t// checkcastPP of $dst" %} 9470 size(0); 9471 ins_encode( /*empty*/ ); 9472 ins_pipe(pipe_class_default); 9473 %} 9474 9475 //----------Convert instructions----------------------------------------------- 9476 9477 // Convert to boolean. 9478 9479 // int_to_bool(src) : { 1 if src != 0 9480 // { 0 else 9481 // 9482 // strategy: 9483 // 1) Count leading zeros of 32 bit-value src, 9484 // this returns 32 (0b10.0000) iff src == 0 and <32 otherwise. 9485 // 2) Shift 5 bits to the right, result is 0b1 iff src == 0, 0b0 otherwise. 9486 // 3) Xori the result to get 0b1 if src != 0 and 0b0 if src == 0. 9487 9488 // convI2Bool 9489 instruct convI2Bool_reg__cntlz_Ex(iRegIdst dst, iRegIsrc src) %{ 9490 match(Set dst (Conv2B src)); 9491 predicate(UseCountLeadingZerosInstructionsPPC64); 9492 ins_cost(DEFAULT_COST); 9493 9494 expand %{ 9495 immI shiftAmount %{ 0x5 %} 9496 uimmI16 mask %{ 0x1 %} 9497 iRegIdst tmp1; 9498 iRegIdst tmp2; 9499 countLeadingZerosI(tmp1, src); 9500 urShiftI_reg_imm(tmp2, tmp1, shiftAmount); 9501 xorI_reg_uimm16(dst, tmp2, mask); 9502 %} 9503 %} 9504 9505 instruct convI2Bool_reg__cmove(iRegIdst dst, iRegIsrc src, flagsReg crx) %{ 9506 match(Set dst (Conv2B src)); 9507 effect(TEMP crx); 9508 predicate(!UseCountLeadingZerosInstructionsPPC64); 9509 ins_cost(DEFAULT_COST); 9510 9511 format %{ "CMPWI $crx, $src, #0 \t// convI2B" 9512 "LI $dst, #0\n\t" 9513 "BEQ $crx, done\n\t" 9514 "LI $dst, #1\n" 9515 "done:" %} 9516 size(16); 9517 ins_encode( enc_convI2B_regI__cmove(dst, src, crx, 0x0, 0x1) ); 9518 ins_pipe(pipe_class_compare); 9519 %} 9520 9521 // ConvI2B + XorI 9522 instruct xorI_convI2Bool_reg_immIvalue1__cntlz_Ex(iRegIdst dst, iRegIsrc src, immI_1 mask) %{ 9523 match(Set dst (XorI (Conv2B src) mask)); 9524 predicate(UseCountLeadingZerosInstructionsPPC64); 9525 ins_cost(DEFAULT_COST); 9526 9527 expand %{ 9528 immI shiftAmount %{ 0x5 %} 9529 iRegIdst tmp1; 9530 countLeadingZerosI(tmp1, src); 9531 urShiftI_reg_imm(dst, tmp1, shiftAmount); 9532 %} 9533 %} 9534 9535 instruct xorI_convI2Bool_reg_immIvalue1__cmove(iRegIdst dst, iRegIsrc src, flagsReg crx, immI_1 mask) %{ 9536 match(Set dst (XorI (Conv2B src) mask)); 9537 effect(TEMP crx); 9538 predicate(!UseCountLeadingZerosInstructionsPPC64); 9539 ins_cost(DEFAULT_COST); 9540 9541 format %{ "CMPWI $crx, $src, #0 \t// Xor(convI2B($src), $mask)" 9542 "LI $dst, #1\n\t" 9543 "BEQ $crx, done\n\t" 9544 "LI $dst, #0\n" 9545 "done:" %} 9546 size(16); 9547 ins_encode( enc_convI2B_regI__cmove(dst, src, crx, 0x1, 0x0) ); 9548 ins_pipe(pipe_class_compare); 9549 %} 9550 9551 // AndI 0b0..010..0 + ConvI2B 9552 instruct convI2Bool_andI_reg_immIpowerOf2(iRegIdst dst, iRegIsrc src, immIpowerOf2 mask) %{ 9553 match(Set dst (Conv2B (AndI src mask))); 9554 predicate(UseRotateAndMaskInstructionsPPC64); 9555 ins_cost(DEFAULT_COST); 9556 9557 format %{ "RLWINM $dst, $src, $mask \t// convI2B(AndI($src, $mask))" %} 9558 size(4); 9559 ins_encode %{ 9560 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm); 9561 __ rlwinm($dst$$Register, $src$$Register, (32-log2_long((jlong)$mask$$constant)) & 0x1f, 31, 31); 9562 %} 9563 ins_pipe(pipe_class_default); 9564 %} 9565 9566 // Convert pointer to boolean. 9567 // 9568 // ptr_to_bool(src) : { 1 if src != 0 9569 // { 0 else 9570 // 9571 // strategy: 9572 // 1) Count leading zeros of 64 bit-value src, 9573 // this returns 64 (0b100.0000) iff src == 0 and <64 otherwise. 9574 // 2) Shift 6 bits to the right, result is 0b1 iff src == 0, 0b0 otherwise. 9575 // 3) Xori the result to get 0b1 if src != 0 and 0b0 if src == 0. 9576 9577 // ConvP2B 9578 instruct convP2Bool_reg__cntlz_Ex(iRegIdst dst, iRegP_N2P src) %{ 9579 match(Set dst (Conv2B src)); 9580 predicate(UseCountLeadingZerosInstructionsPPC64); 9581 ins_cost(DEFAULT_COST); 9582 9583 expand %{ 9584 immI shiftAmount %{ 0x6 %} 9585 uimmI16 mask %{ 0x1 %} 9586 iRegIdst tmp1; 9587 iRegIdst tmp2; 9588 countLeadingZerosP(tmp1, src); 9589 urShiftI_reg_imm(tmp2, tmp1, shiftAmount); 9590 xorI_reg_uimm16(dst, tmp2, mask); 9591 %} 9592 %} 9593 9594 instruct convP2Bool_reg__cmove(iRegIdst dst, iRegP_N2P src, flagsReg crx) %{ 9595 match(Set dst (Conv2B src)); 9596 effect(TEMP crx); 9597 predicate(!UseCountLeadingZerosInstructionsPPC64); 9598 ins_cost(DEFAULT_COST); 9599 9600 format %{ "CMPDI $crx, $src, #0 \t// convP2B" 9601 "LI $dst, #0\n\t" 9602 "BEQ $crx, done\n\t" 9603 "LI $dst, #1\n" 9604 "done:" %} 9605 size(16); 9606 ins_encode( enc_convP2B_regP__cmove(dst, src, crx, 0x0, 0x1) ); 9607 ins_pipe(pipe_class_compare); 9608 %} 9609 9610 // ConvP2B + XorI 9611 instruct xorI_convP2Bool_reg__cntlz_Ex(iRegIdst dst, iRegP_N2P src, immI_1 mask) %{ 9612 match(Set dst (XorI (Conv2B src) mask)); 9613 predicate(UseCountLeadingZerosInstructionsPPC64); 9614 ins_cost(DEFAULT_COST); 9615 9616 expand %{ 9617 immI shiftAmount %{ 0x6 %} 9618 iRegIdst tmp1; 9619 countLeadingZerosP(tmp1, src); 9620 urShiftI_reg_imm(dst, tmp1, shiftAmount); 9621 %} 9622 %} 9623 9624 instruct xorI_convP2Bool_reg_immIvalue1__cmove(iRegIdst dst, iRegP_N2P src, flagsReg crx, immI_1 mask) %{ 9625 match(Set dst (XorI (Conv2B src) mask)); 9626 effect(TEMP crx); 9627 predicate(!UseCountLeadingZerosInstructionsPPC64); 9628 ins_cost(DEFAULT_COST); 9629 9630 format %{ "CMPDI $crx, $src, #0 \t// XorI(convP2B($src), $mask)" 9631 "LI $dst, #1\n\t" 9632 "BEQ $crx, done\n\t" 9633 "LI $dst, #0\n" 9634 "done:" %} 9635 size(16); 9636 ins_encode( enc_convP2B_regP__cmove(dst, src, crx, 0x1, 0x0) ); 9637 ins_pipe(pipe_class_compare); 9638 %} 9639 9640 // if src1 < src2, return -1 else return 0 9641 instruct cmpLTMask_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ 9642 match(Set dst (CmpLTMask src1 src2)); 9643 ins_cost(DEFAULT_COST*4); 9644 9645 expand %{ 9646 iRegLdst src1s; 9647 iRegLdst src2s; 9648 iRegLdst diff; 9649 convI2L_reg(src1s, src1); // Ensure proper sign extension. 9650 convI2L_reg(src2s, src2); // Ensure proper sign extension. 9651 subL_reg_reg(diff, src1s, src2s); 9652 // Need to consider >=33 bit result, therefore we need signmaskL. 9653 signmask64I_regL(dst, diff); 9654 %} 9655 %} 9656 9657 instruct cmpLTMask_reg_immI0(iRegIdst dst, iRegIsrc src1, immI_0 src2) %{ 9658 match(Set dst (CmpLTMask src1 src2)); // if src1 < src2, return -1 else return 0 9659 format %{ "SRAWI $dst, $src1, $src2 \t// CmpLTMask" %} 9660 size(4); 9661 ins_encode %{ 9662 // TODO: PPC port $archOpcode(ppc64Opcode_srawi); 9663 __ srawi($dst$$Register, $src1$$Register, 0x1f); 9664 %} 9665 ins_pipe(pipe_class_default); 9666 %} 9667 9668 //----------Arithmetic Conversion Instructions--------------------------------- 9669 9670 // Convert to Byte -- nop 9671 // Convert to Short -- nop 9672 9673 // Convert to Int 9674 9675 instruct convB2I_reg(iRegIdst dst, iRegIsrc src, immI_24 amount) %{ 9676 match(Set dst (RShiftI (LShiftI src amount) amount)); 9677 format %{ "EXTSB $dst, $src \t// byte->int" %} 9678 size(4); 9679 ins_encode %{ 9680 // TODO: PPC port $archOpcode(ppc64Opcode_extsb); 9681 __ extsb($dst$$Register, $src$$Register); 9682 %} 9683 ins_pipe(pipe_class_default); 9684 %} 9685 9686 // LShiftI 16 + RShiftI 16 converts short to int. 9687 instruct convS2I_reg(iRegIdst dst, iRegIsrc src, immI_16 amount) %{ 9688 match(Set dst (RShiftI (LShiftI src amount) amount)); 9689 format %{ "EXTSH $dst, $src \t// short->int" %} 9690 size(4); 9691 ins_encode %{ 9692 // TODO: PPC port $archOpcode(ppc64Opcode_extsh); 9693 __ extsh($dst$$Register, $src$$Register); 9694 %} 9695 ins_pipe(pipe_class_default); 9696 %} 9697 9698 // ConvL2I + ConvI2L: Sign extend int in long register. 9699 instruct sxtI_L2L_reg(iRegLdst dst, iRegLsrc src) %{ 9700 match(Set dst (ConvI2L (ConvL2I src))); 9701 9702 format %{ "EXTSW $dst, $src \t// long->long" %} 9703 size(4); 9704 ins_encode %{ 9705 // TODO: PPC port $archOpcode(ppc64Opcode_extsw); 9706 __ extsw($dst$$Register, $src$$Register); 9707 %} 9708 ins_pipe(pipe_class_default); 9709 %} 9710 9711 instruct convL2I_reg(iRegIdst dst, iRegLsrc src) %{ 9712 match(Set dst (ConvL2I src)); 9713 format %{ "MR $dst, $src \t// long->int" %} 9714 // variable size, 0 or 4 9715 ins_encode %{ 9716 // TODO: PPC port $archOpcode(ppc64Opcode_or); 9717 __ mr_if_needed($dst$$Register, $src$$Register); 9718 %} 9719 ins_pipe(pipe_class_default); 9720 %} 9721 9722 instruct convD2IRaw_regD(regD dst, regD src) %{ 9723 // no match-rule, false predicate 9724 effect(DEF dst, USE src); 9725 predicate(false); 9726 9727 format %{ "FCTIWZ $dst, $src \t// convD2I, $src != NaN" %} 9728 size(4); 9729 ins_encode %{ 9730 // TODO: PPC port $archOpcode(ppc64Opcode_fctiwz);; 9731 __ fctiwz($dst$$FloatRegister, $src$$FloatRegister); 9732 %} 9733 ins_pipe(pipe_class_default); 9734 %} 9735 9736 instruct cmovI_bso_stackSlotL(iRegIdst dst, flagsReg crx, stackSlotL src) %{ 9737 // no match-rule, false predicate 9738 effect(DEF dst, USE crx, USE src); 9739 predicate(false); 9740 9741 ins_variable_size_depending_on_alignment(true); 9742 9743 format %{ "cmovI $crx, $dst, $src" %} 9744 // Worst case is branch + move + stop, no stop without scheduler. 9745 size(false /* TODO: PPC PORT(InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8); 9746 ins_encode( enc_cmove_bso_stackSlotL(dst, crx, src) ); 9747 ins_pipe(pipe_class_default); 9748 %} 9749 9750 instruct cmovI_bso_stackSlotL_conLvalue0_Ex(iRegIdst dst, flagsReg crx, stackSlotL mem) %{ 9751 // no match-rule, false predicate 9752 effect(DEF dst, USE crx, USE mem); 9753 predicate(false); 9754 9755 format %{ "CmovI $dst, $crx, $mem \t// postalloc expanded" %} 9756 postalloc_expand %{ 9757 // 9758 // replaces 9759 // 9760 // region dst crx mem 9761 // \ | | / 9762 // dst=cmovI_bso_stackSlotL_conLvalue0 9763 // 9764 // with 9765 // 9766 // region dst 9767 // \ / 9768 // dst=loadConI16(0) 9769 // | 9770 // ^ region dst crx mem 9771 // | \ | | / 9772 // dst=cmovI_bso_stackSlotL 9773 // 9774 9775 // Create new nodes. 9776 MachNode *m1 = loadConI16Node(); 9777 MachNode *m2 = cmovI_bso_stackSlotLNode(); 9778 9779 // inputs for new nodes 9780 m1->add_req(n_region); 9781 m2->add_req(n_region, n_crx, n_mem); 9782 9783 // precedences for new nodes 9784 m2->add_prec(m1); 9785 9786 // operands for new nodes 9787 m1->_opnds[0] = op_dst; 9788 m1->_opnds[1] = immI16Oper(0); 9789 9790 m2->_opnds[0] = op_dst; 9791 m2->_opnds[1] = op_crx; 9792 m2->_opnds[2] = op_mem; 9793 9794 // registers for new nodes 9795 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst 9796 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst 9797 9798 // Insert new nodes. 9799 nodes->push(m1); 9800 nodes->push(m2); 9801 %} 9802 %} 9803 9804 // Double to Int conversion, NaN is mapped to 0. 9805 instruct convD2I_reg_ExEx(iRegIdst dst, regD src) %{ 9806 match(Set dst (ConvD2I src)); 9807 ins_cost(DEFAULT_COST); 9808 9809 expand %{ 9810 regD tmpD; 9811 stackSlotL tmpS; 9812 flagsReg crx; 9813 cmpDUnordered_reg_reg(crx, src, src); // Check whether src is NaN. 9814 convD2IRaw_regD(tmpD, src); // Convert float to int (speculated). 9815 moveD2L_reg_stack(tmpS, tmpD); // Store float to stack (speculated). 9816 cmovI_bso_stackSlotL_conLvalue0_Ex(dst, crx, tmpS); // Cmove based on NaN check. 9817 %} 9818 %} 9819 9820 instruct convF2IRaw_regF(regF dst, regF src) %{ 9821 // no match-rule, false predicate 9822 effect(DEF dst, USE src); 9823 predicate(false); 9824 9825 format %{ "FCTIWZ $dst, $src \t// convF2I, $src != NaN" %} 9826 size(4); 9827 ins_encode %{ 9828 // TODO: PPC port $archOpcode(ppc64Opcode_fctiwz); 9829 __ fctiwz($dst$$FloatRegister, $src$$FloatRegister); 9830 %} 9831 ins_pipe(pipe_class_default); 9832 %} 9833 9834 // Float to Int conversion, NaN is mapped to 0. 9835 instruct convF2I_regF_ExEx(iRegIdst dst, regF src) %{ 9836 match(Set dst (ConvF2I src)); 9837 ins_cost(DEFAULT_COST); 9838 9839 expand %{ 9840 regF tmpF; 9841 stackSlotL tmpS; 9842 flagsReg crx; 9843 cmpFUnordered_reg_reg(crx, src, src); // Check whether src is NaN. 9844 convF2IRaw_regF(tmpF, src); // Convert float to int (speculated). 9845 moveF2L_reg_stack(tmpS, tmpF); // Store float to stack (speculated). 9846 cmovI_bso_stackSlotL_conLvalue0_Ex(dst, crx, tmpS); // Cmove based on NaN check. 9847 %} 9848 %} 9849 9850 // Convert to Long 9851 9852 instruct convI2L_reg(iRegLdst dst, iRegIsrc src) %{ 9853 match(Set dst (ConvI2L src)); 9854 format %{ "EXTSW $dst, $src \t// int->long" %} 9855 size(4); 9856 ins_encode %{ 9857 // TODO: PPC port $archOpcode(ppc64Opcode_extsw); 9858 __ extsw($dst$$Register, $src$$Register); 9859 %} 9860 ins_pipe(pipe_class_default); 9861 %} 9862 9863 // Zero-extend: convert unsigned int to long (convUI2L). 9864 instruct zeroExtendL_regI(iRegLdst dst, iRegIsrc src, immL_32bits mask) %{ 9865 match(Set dst (AndL (ConvI2L src) mask)); 9866 ins_cost(DEFAULT_COST); 9867 9868 format %{ "CLRLDI $dst, $src, #32 \t// zero-extend int to long" %} 9869 size(4); 9870 ins_encode %{ 9871 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl); 9872 __ clrldi($dst$$Register, $src$$Register, 32); 9873 %} 9874 ins_pipe(pipe_class_default); 9875 %} 9876 9877 // Zero-extend: convert unsigned int to long in long register. 9878 instruct zeroExtendL_regL(iRegLdst dst, iRegLsrc src, immL_32bits mask) %{ 9879 match(Set dst (AndL src mask)); 9880 ins_cost(DEFAULT_COST); 9881 9882 format %{ "CLRLDI $dst, $src, #32 \t// zero-extend int to long" %} 9883 size(4); 9884 ins_encode %{ 9885 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl); 9886 __ clrldi($dst$$Register, $src$$Register, 32); 9887 %} 9888 ins_pipe(pipe_class_default); 9889 %} 9890 9891 instruct convF2LRaw_regF(regF dst, regF src) %{ 9892 // no match-rule, false predicate 9893 effect(DEF dst, USE src); 9894 predicate(false); 9895 9896 format %{ "FCTIDZ $dst, $src \t// convF2L, $src != NaN" %} 9897 size(4); 9898 ins_encode %{ 9899 // TODO: PPC port $archOpcode(ppc64Opcode_fctiwz); 9900 __ fctidz($dst$$FloatRegister, $src$$FloatRegister); 9901 %} 9902 ins_pipe(pipe_class_default); 9903 %} 9904 9905 instruct cmovL_bso_stackSlotL(iRegLdst dst, flagsReg crx, stackSlotL src) %{ 9906 // no match-rule, false predicate 9907 effect(DEF dst, USE crx, USE src); 9908 predicate(false); 9909 9910 ins_variable_size_depending_on_alignment(true); 9911 9912 format %{ "cmovL $crx, $dst, $src" %} 9913 // Worst case is branch + move + stop, no stop without scheduler. 9914 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8); 9915 ins_encode( enc_cmove_bso_stackSlotL(dst, crx, src) ); 9916 ins_pipe(pipe_class_default); 9917 %} 9918 9919 instruct cmovL_bso_stackSlotL_conLvalue0_Ex(iRegLdst dst, flagsReg crx, stackSlotL mem) %{ 9920 // no match-rule, false predicate 9921 effect(DEF dst, USE crx, USE mem); 9922 predicate(false); 9923 9924 format %{ "CmovL $dst, $crx, $mem \t// postalloc expanded" %} 9925 postalloc_expand %{ 9926 // 9927 // replaces 9928 // 9929 // region dst crx mem 9930 // \ | | / 9931 // dst=cmovL_bso_stackSlotL_conLvalue0 9932 // 9933 // with 9934 // 9935 // region dst 9936 // \ / 9937 // dst=loadConL16(0) 9938 // | 9939 // ^ region dst crx mem 9940 // | \ | | / 9941 // dst=cmovL_bso_stackSlotL 9942 // 9943 9944 // Create new nodes. 9945 MachNode *m1 = loadConL16Node(); 9946 MachNode *m2 = cmovL_bso_stackSlotLNode(); 9947 9948 // inputs for new nodes 9949 m1->add_req(n_region); 9950 m2->add_req(n_region, n_crx, n_mem); 9951 m2->add_prec(m1); 9952 9953 // operands for new nodes 9954 m1->_opnds[0] = op_dst; 9955 m1->_opnds[1] = immL16Oper(0); 9956 m2->_opnds[0] = op_dst; 9957 m2->_opnds[1] = op_crx; 9958 m2->_opnds[2] = op_mem; 9959 9960 // registers for new nodes 9961 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst 9962 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst 9963 9964 // Insert new nodes. 9965 nodes->push(m1); 9966 nodes->push(m2); 9967 %} 9968 %} 9969 9970 // Float to Long conversion, NaN is mapped to 0. 9971 instruct convF2L_reg_ExEx(iRegLdst dst, regF src) %{ 9972 match(Set dst (ConvF2L src)); 9973 ins_cost(DEFAULT_COST); 9974 9975 expand %{ 9976 regF tmpF; 9977 stackSlotL tmpS; 9978 flagsReg crx; 9979 cmpFUnordered_reg_reg(crx, src, src); // Check whether src is NaN. 9980 convF2LRaw_regF(tmpF, src); // Convert float to long (speculated). 9981 moveF2L_reg_stack(tmpS, tmpF); // Store float to stack (speculated). 9982 cmovL_bso_stackSlotL_conLvalue0_Ex(dst, crx, tmpS); // Cmove based on NaN check. 9983 %} 9984 %} 9985 9986 instruct convD2LRaw_regD(regD dst, regD src) %{ 9987 // no match-rule, false predicate 9988 effect(DEF dst, USE src); 9989 predicate(false); 9990 9991 format %{ "FCTIDZ $dst, $src \t// convD2L $src != NaN" %} 9992 size(4); 9993 ins_encode %{ 9994 // TODO: PPC port $archOpcode(ppc64Opcode_fctiwz); 9995 __ fctidz($dst$$FloatRegister, $src$$FloatRegister); 9996 %} 9997 ins_pipe(pipe_class_default); 9998 %} 9999 10000 // Double to Long conversion, NaN is mapped to 0. 10001 instruct convD2L_reg_ExEx(iRegLdst dst, regD src) %{ 10002 match(Set dst (ConvD2L src)); 10003 ins_cost(DEFAULT_COST); 10004 10005 expand %{ 10006 regD tmpD; 10007 stackSlotL tmpS; 10008 flagsReg crx; 10009 cmpDUnordered_reg_reg(crx, src, src); // Check whether src is NaN. 10010 convD2LRaw_regD(tmpD, src); // Convert float to long (speculated). 10011 moveD2L_reg_stack(tmpS, tmpD); // Store float to stack (speculated). 10012 cmovL_bso_stackSlotL_conLvalue0_Ex(dst, crx, tmpS); // Cmove based on NaN check. 10013 %} 10014 %} 10015 10016 // Convert to Float 10017 10018 // Placed here as needed in expand. 10019 instruct convL2DRaw_regD(regD dst, regD src) %{ 10020 // no match-rule, false predicate 10021 effect(DEF dst, USE src); 10022 predicate(false); 10023 10024 format %{ "FCFID $dst, $src \t// convL2D" %} 10025 size(4); 10026 ins_encode %{ 10027 // TODO: PPC port $archOpcode(ppc64Opcode_fcfid); 10028 __ fcfid($dst$$FloatRegister, $src$$FloatRegister); 10029 %} 10030 ins_pipe(pipe_class_default); 10031 %} 10032 10033 // Placed here as needed in expand. 10034 instruct convD2F_reg(regF dst, regD src) %{ 10035 match(Set dst (ConvD2F src)); 10036 format %{ "FRSP $dst, $src \t// convD2F" %} 10037 size(4); 10038 ins_encode %{ 10039 // TODO: PPC port $archOpcode(ppc64Opcode_frsp); 10040 __ frsp($dst$$FloatRegister, $src$$FloatRegister); 10041 %} 10042 ins_pipe(pipe_class_default); 10043 %} 10044 10045 // Integer to Float conversion. 10046 instruct convI2F_ireg_Ex(regF dst, iRegIsrc src) %{ 10047 match(Set dst (ConvI2F src)); 10048 predicate(!VM_Version::has_fcfids()); 10049 ins_cost(DEFAULT_COST); 10050 10051 expand %{ 10052 iRegLdst tmpL; 10053 stackSlotL tmpS; 10054 regD tmpD; 10055 regD tmpD2; 10056 convI2L_reg(tmpL, src); // Sign-extension int to long. 10057 regL_to_stkL(tmpS, tmpL); // Store long to stack. 10058 moveL2D_stack_reg(tmpD, tmpS); // Load long into double register. 10059 convL2DRaw_regD(tmpD2, tmpD); // Convert to double. 10060 convD2F_reg(dst, tmpD2); // Convert double to float. 10061 %} 10062 %} 10063 10064 instruct convL2FRaw_regF(regF dst, regD src) %{ 10065 // no match-rule, false predicate 10066 effect(DEF dst, USE src); 10067 predicate(false); 10068 10069 format %{ "FCFIDS $dst, $src \t// convL2F" %} 10070 size(4); 10071 ins_encode %{ 10072 // TODO: PPC port $archOpcode(ppc64Opcode_fcfid); 10073 __ fcfids($dst$$FloatRegister, $src$$FloatRegister); 10074 %} 10075 ins_pipe(pipe_class_default); 10076 %} 10077 10078 // Integer to Float conversion. Special version for Power7. 10079 instruct convI2F_ireg_fcfids_Ex(regF dst, iRegIsrc src) %{ 10080 match(Set dst (ConvI2F src)); 10081 predicate(VM_Version::has_fcfids()); 10082 ins_cost(DEFAULT_COST); 10083 10084 expand %{ 10085 iRegLdst tmpL; 10086 stackSlotL tmpS; 10087 regD tmpD; 10088 convI2L_reg(tmpL, src); // Sign-extension int to long. 10089 regL_to_stkL(tmpS, tmpL); // Store long to stack. 10090 moveL2D_stack_reg(tmpD, tmpS); // Load long into double register. 10091 convL2FRaw_regF(dst, tmpD); // Convert to float. 10092 %} 10093 %} 10094 10095 // L2F to avoid runtime call. 10096 instruct convL2F_ireg_fcfids_Ex(regF dst, iRegLsrc src) %{ 10097 match(Set dst (ConvL2F src)); 10098 predicate(VM_Version::has_fcfids()); 10099 ins_cost(DEFAULT_COST); 10100 10101 expand %{ 10102 stackSlotL tmpS; 10103 regD tmpD; 10104 regL_to_stkL(tmpS, src); // Store long to stack. 10105 moveL2D_stack_reg(tmpD, tmpS); // Load long into double register. 10106 convL2FRaw_regF(dst, tmpD); // Convert to float. 10107 %} 10108 %} 10109 10110 // Moved up as used in expand. 10111 //instruct convD2F_reg(regF dst, regD src) %{%} 10112 10113 // Convert to Double 10114 10115 // Integer to Double conversion. 10116 instruct convI2D_reg_Ex(regD dst, iRegIsrc src) %{ 10117 match(Set dst (ConvI2D src)); 10118 ins_cost(DEFAULT_COST); 10119 10120 expand %{ 10121 iRegLdst tmpL; 10122 stackSlotL tmpS; 10123 regD tmpD; 10124 convI2L_reg(tmpL, src); // Sign-extension int to long. 10125 regL_to_stkL(tmpS, tmpL); // Store long to stack. 10126 moveL2D_stack_reg(tmpD, tmpS); // Load long into double register. 10127 convL2DRaw_regD(dst, tmpD); // Convert to double. 10128 %} 10129 %} 10130 10131 // Long to Double conversion 10132 instruct convL2D_reg_Ex(regD dst, stackSlotL src) %{ 10133 match(Set dst (ConvL2D src)); 10134 ins_cost(DEFAULT_COST + MEMORY_REF_COST); 10135 10136 expand %{ 10137 regD tmpD; 10138 moveL2D_stack_reg(tmpD, src); 10139 convL2DRaw_regD(dst, tmpD); 10140 %} 10141 %} 10142 10143 instruct convF2D_reg(regD dst, regF src) %{ 10144 match(Set dst (ConvF2D src)); 10145 format %{ "FMR $dst, $src \t// float->double" %} 10146 // variable size, 0 or 4 10147 ins_encode %{ 10148 // TODO: PPC port $archOpcode(ppc64Opcode_fmr); 10149 __ fmr_if_needed($dst$$FloatRegister, $src$$FloatRegister); 10150 %} 10151 ins_pipe(pipe_class_default); 10152 %} 10153 10154 //----------Control Flow Instructions------------------------------------------ 10155 // Compare Instructions 10156 10157 // Compare Integers 10158 instruct cmpI_reg_reg(flagsReg crx, iRegIsrc src1, iRegIsrc src2) %{ 10159 match(Set crx (CmpI src1 src2)); 10160 size(4); 10161 format %{ "CMPW $crx, $src1, $src2" %} 10162 ins_encode %{ 10163 // TODO: PPC port $archOpcode(ppc64Opcode_cmp); 10164 __ cmpw($crx$$CondRegister, $src1$$Register, $src2$$Register); 10165 %} 10166 ins_pipe(pipe_class_compare); 10167 %} 10168 10169 instruct cmpI_reg_imm16(flagsReg crx, iRegIsrc src1, immI16 src2) %{ 10170 match(Set crx (CmpI src1 src2)); 10171 format %{ "CMPWI $crx, $src1, $src2" %} 10172 size(4); 10173 ins_encode %{ 10174 // TODO: PPC port $archOpcode(ppc64Opcode_cmpi); 10175 __ cmpwi($crx$$CondRegister, $src1$$Register, $src2$$constant); 10176 %} 10177 ins_pipe(pipe_class_compare); 10178 %} 10179 10180 // (src1 & src2) == 0? 10181 instruct testI_reg_imm(flagsRegCR0 cr0, iRegIsrc src1, uimmI16 src2, immI_0 zero) %{ 10182 match(Set cr0 (CmpI (AndI src1 src2) zero)); 10183 // r0 is killed 10184 format %{ "ANDI R0, $src1, $src2 \t// BTST int" %} 10185 size(4); 10186 ins_encode %{ 10187 // TODO: PPC port $archOpcode(ppc64Opcode_andi_); 10188 // FIXME: avoid andi_ ? 10189 __ andi_(R0, $src1$$Register, $src2$$constant); 10190 %} 10191 ins_pipe(pipe_class_compare); 10192 %} 10193 10194 instruct cmpL_reg_reg(flagsReg crx, iRegLsrc src1, iRegLsrc src2) %{ 10195 match(Set crx (CmpL src1 src2)); 10196 format %{ "CMPD $crx, $src1, $src2" %} 10197 size(4); 10198 ins_encode %{ 10199 // TODO: PPC port $archOpcode(ppc64Opcode_cmp); 10200 __ cmpd($crx$$CondRegister, $src1$$Register, $src2$$Register); 10201 %} 10202 ins_pipe(pipe_class_compare); 10203 %} 10204 10205 instruct cmpL_reg_imm16(flagsReg crx, iRegLsrc src1, immL16 src2) %{ 10206 match(Set crx (CmpL src1 src2)); 10207 format %{ "CMPDI $crx, $src1, $src2" %} 10208 size(4); 10209 ins_encode %{ 10210 // TODO: PPC port $archOpcode(ppc64Opcode_cmpi); 10211 __ cmpdi($crx$$CondRegister, $src1$$Register, $src2$$constant); 10212 %} 10213 ins_pipe(pipe_class_compare); 10214 %} 10215 10216 instruct testL_reg_reg(flagsRegCR0 cr0, iRegLsrc src1, iRegLsrc src2, immL_0 zero) %{ 10217 match(Set cr0 (CmpL (AndL src1 src2) zero)); 10218 // r0 is killed 10219 format %{ "AND R0, $src1, $src2 \t// BTST long" %} 10220 size(4); 10221 ins_encode %{ 10222 // TODO: PPC port $archOpcode(ppc64Opcode_and_); 10223 __ and_(R0, $src1$$Register, $src2$$Register); 10224 %} 10225 ins_pipe(pipe_class_compare); 10226 %} 10227 10228 instruct testL_reg_imm(flagsRegCR0 cr0, iRegLsrc src1, uimmL16 src2, immL_0 zero) %{ 10229 match(Set cr0 (CmpL (AndL src1 src2) zero)); 10230 // r0 is killed 10231 format %{ "ANDI R0, $src1, $src2 \t// BTST long" %} 10232 size(4); 10233 ins_encode %{ 10234 // TODO: PPC port $archOpcode(ppc64Opcode_andi_); 10235 // FIXME: avoid andi_ ? 10236 __ andi_(R0, $src1$$Register, $src2$$constant); 10237 %} 10238 ins_pipe(pipe_class_compare); 10239 %} 10240 10241 instruct cmovI_conIvalueMinus1_conIvalue1(iRegIdst dst, flagsReg crx) %{ 10242 // no match-rule, false predicate 10243 effect(DEF dst, USE crx); 10244 predicate(false); 10245 10246 ins_variable_size_depending_on_alignment(true); 10247 10248 format %{ "cmovI $crx, $dst, -1, 0, +1" %} 10249 // Worst case is branch + move + branch + move + stop, no stop without scheduler. 10250 size(false /* TODO: PPC PORTInsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 20 : 16); 10251 ins_encode %{ 10252 // TODO: PPC port $archOpcode(ppc64Opcode_cmove); 10253 Label done; 10254 // li(Rdst, 0); // equal -> 0 10255 __ beq($crx$$CondRegister, done); 10256 __ li($dst$$Register, 1); // greater -> +1 10257 __ bgt($crx$$CondRegister, done); 10258 __ li($dst$$Register, -1); // unordered or less -> -1 10259 // TODO: PPC port__ endgroup_if_needed(_size == 20); 10260 __ bind(done); 10261 %} 10262 ins_pipe(pipe_class_compare); 10263 %} 10264 10265 instruct cmovI_conIvalueMinus1_conIvalue0_conIvalue1_Ex(iRegIdst dst, flagsReg crx) %{ 10266 // no match-rule, false predicate 10267 effect(DEF dst, USE crx); 10268 predicate(false); 10269 10270 format %{ "CmovI $crx, $dst, -1, 0, +1 \t// postalloc expanded" %} 10271 postalloc_expand %{ 10272 // 10273 // replaces 10274 // 10275 // region crx 10276 // \ | 10277 // dst=cmovI_conIvalueMinus1_conIvalue0_conIvalue1 10278 // 10279 // with 10280 // 10281 // region 10282 // \ 10283 // dst=loadConI16(0) 10284 // | 10285 // ^ region crx 10286 // | \ | 10287 // dst=cmovI_conIvalueMinus1_conIvalue1 10288 // 10289 10290 // Create new nodes. 10291 MachNode *m1 = loadConI16Node(); 10292 MachNode *m2 = cmovI_conIvalueMinus1_conIvalue1Node(); 10293 10294 // inputs for new nodes 10295 m1->add_req(n_region); 10296 m2->add_req(n_region, n_crx); 10297 m2->add_prec(m1); 10298 10299 // operands for new nodes 10300 m1->_opnds[0] = op_dst; 10301 m1->_opnds[1] = immI16Oper(0); 10302 m2->_opnds[0] = op_dst; 10303 m2->_opnds[1] = op_crx; 10304 10305 // registers for new nodes 10306 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst 10307 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst 10308 10309 // Insert new nodes. 10310 nodes->push(m1); 10311 nodes->push(m2); 10312 %} 10313 %} 10314 10315 // Manifest a CmpL3 result in an integer register. Very painful. 10316 // This is the test to avoid. 10317 // (src1 < src2) ? -1 : ((src1 > src2) ? 1 : 0) 10318 instruct cmpL3_reg_reg_ExEx(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{ 10319 match(Set dst (CmpL3 src1 src2)); 10320 ins_cost(DEFAULT_COST*5+BRANCH_COST); 10321 10322 expand %{ 10323 flagsReg tmp1; 10324 cmpL_reg_reg(tmp1, src1, src2); 10325 cmovI_conIvalueMinus1_conIvalue0_conIvalue1_Ex(dst, tmp1); 10326 %} 10327 %} 10328 10329 // Implicit range checks. 10330 // A range check in the ideal world has one of the following shapes: 10331 // - (If le (CmpU length index)), (IfTrue throw exception) 10332 // - (If lt (CmpU index length)), (IfFalse throw exception) 10333 // 10334 // Match range check 'If le (CmpU length index)'. 10335 instruct rangeCheck_iReg_uimm15(cmpOp cmp, iRegIsrc src_length, uimmI15 index, label labl) %{ 10336 match(If cmp (CmpU src_length index)); 10337 effect(USE labl); 10338 predicate(TrapBasedRangeChecks && 10339 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le && 10340 PROB_UNLIKELY(_leaf->as_If()->_prob) >= PROB_ALWAYS && 10341 (Matcher::branches_to_uncommon_trap(_leaf))); 10342 10343 ins_is_TrapBasedCheckNode(true); 10344 10345 format %{ "TWI $index $cmp $src_length \t// RangeCheck => trap $labl" %} 10346 size(4); 10347 ins_encode %{ 10348 // TODO: PPC port $archOpcode(ppc64Opcode_twi); 10349 if ($cmp$$cmpcode == 0x1 /* less_equal */) { 10350 __ trap_range_check_le($src_length$$Register, $index$$constant); 10351 } else { 10352 // Both successors are uncommon traps, probability is 0. 10353 // Node got flipped during fixup flow. 10354 assert($cmp$$cmpcode == 0x9, "must be greater"); 10355 __ trap_range_check_g($src_length$$Register, $index$$constant); 10356 } 10357 %} 10358 ins_pipe(pipe_class_trap); 10359 %} 10360 10361 // Match range check 'If lt (CmpU index length)'. 10362 instruct rangeCheck_iReg_iReg(cmpOp cmp, iRegIsrc src_index, iRegIsrc src_length, label labl) %{ 10363 match(If cmp (CmpU src_index src_length)); 10364 effect(USE labl); 10365 predicate(TrapBasedRangeChecks && 10366 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt && 10367 _leaf->as_If()->_prob >= PROB_ALWAYS && 10368 (Matcher::branches_to_uncommon_trap(_leaf))); 10369 10370 ins_is_TrapBasedCheckNode(true); 10371 10372 format %{ "TW $src_index $cmp $src_length \t// RangeCheck => trap $labl" %} 10373 size(4); 10374 ins_encode %{ 10375 // TODO: PPC port $archOpcode(ppc64Opcode_tw); 10376 if ($cmp$$cmpcode == 0x0 /* greater_equal */) { 10377 __ trap_range_check_ge($src_index$$Register, $src_length$$Register); 10378 } else { 10379 // Both successors are uncommon traps, probability is 0. 10380 // Node got flipped during fixup flow. 10381 assert($cmp$$cmpcode == 0x8, "must be less"); 10382 __ trap_range_check_l($src_index$$Register, $src_length$$Register); 10383 } 10384 %} 10385 ins_pipe(pipe_class_trap); 10386 %} 10387 10388 // Match range check 'If lt (CmpU index length)'. 10389 instruct rangeCheck_uimm15_iReg(cmpOp cmp, iRegIsrc src_index, uimmI15 length, label labl) %{ 10390 match(If cmp (CmpU src_index length)); 10391 effect(USE labl); 10392 predicate(TrapBasedRangeChecks && 10393 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt && 10394 _leaf->as_If()->_prob >= PROB_ALWAYS && 10395 (Matcher::branches_to_uncommon_trap(_leaf))); 10396 10397 ins_is_TrapBasedCheckNode(true); 10398 10399 format %{ "TWI $src_index $cmp $length \t// RangeCheck => trap $labl" %} 10400 size(4); 10401 ins_encode %{ 10402 // TODO: PPC port $archOpcode(ppc64Opcode_twi); 10403 if ($cmp$$cmpcode == 0x0 /* greater_equal */) { 10404 __ trap_range_check_ge($src_index$$Register, $length$$constant); 10405 } else { 10406 // Both successors are uncommon traps, probability is 0. 10407 // Node got flipped during fixup flow. 10408 assert($cmp$$cmpcode == 0x8, "must be less"); 10409 __ trap_range_check_l($src_index$$Register, $length$$constant); 10410 } 10411 %} 10412 ins_pipe(pipe_class_trap); 10413 %} 10414 10415 instruct compU_reg_reg(flagsReg crx, iRegIsrc src1, iRegIsrc src2) %{ 10416 match(Set crx (CmpU src1 src2)); 10417 format %{ "CMPLW $crx, $src1, $src2 \t// unsigned" %} 10418 size(4); 10419 ins_encode %{ 10420 // TODO: PPC port $archOpcode(ppc64Opcode_cmpl); 10421 __ cmplw($crx$$CondRegister, $src1$$Register, $src2$$Register); 10422 %} 10423 ins_pipe(pipe_class_compare); 10424 %} 10425 10426 instruct compU_reg_uimm16(flagsReg crx, iRegIsrc src1, uimmI16 src2) %{ 10427 match(Set crx (CmpU src1 src2)); 10428 size(4); 10429 format %{ "CMPLWI $crx, $src1, $src2" %} 10430 ins_encode %{ 10431 // TODO: PPC port $archOpcode(ppc64Opcode_cmpli); 10432 __ cmplwi($crx$$CondRegister, $src1$$Register, $src2$$constant); 10433 %} 10434 ins_pipe(pipe_class_compare); 10435 %} 10436 10437 // Implicit zero checks (more implicit null checks). 10438 // No constant pool entries required. 10439 instruct zeroCheckN_iReg_imm0(cmpOp cmp, iRegNsrc value, immN_0 zero, label labl) %{ 10440 match(If cmp (CmpN value zero)); 10441 effect(USE labl); 10442 predicate(TrapBasedNullChecks && 10443 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne && 10444 _leaf->as_If()->_prob >= PROB_LIKELY_MAG(4) && 10445 Matcher::branches_to_uncommon_trap(_leaf)); 10446 ins_cost(1); 10447 10448 ins_is_TrapBasedCheckNode(true); 10449 10450 format %{ "TDI $value $cmp $zero \t// ZeroCheckN => trap $labl" %} 10451 size(4); 10452 ins_encode %{ 10453 // TODO: PPC port $archOpcode(ppc64Opcode_tdi); 10454 if ($cmp$$cmpcode == 0xA) { 10455 __ trap_null_check($value$$Register); 10456 } else { 10457 // Both successors are uncommon traps, probability is 0. 10458 // Node got flipped during fixup flow. 10459 assert($cmp$$cmpcode == 0x2 , "must be equal(0xA) or notEqual(0x2)"); 10460 __ trap_null_check($value$$Register, Assembler::traptoGreaterThanUnsigned); 10461 } 10462 %} 10463 ins_pipe(pipe_class_trap); 10464 %} 10465 10466 // Compare narrow oops. 10467 instruct cmpN_reg_reg(flagsReg crx, iRegNsrc src1, iRegNsrc src2) %{ 10468 match(Set crx (CmpN src1 src2)); 10469 10470 size(4); 10471 ins_cost(DEFAULT_COST); 10472 format %{ "CMPLW $crx, $src1, $src2 \t// compressed ptr" %} 10473 ins_encode %{ 10474 // TODO: PPC port $archOpcode(ppc64Opcode_cmpl); 10475 __ cmplw($crx$$CondRegister, $src1$$Register, $src2$$Register); 10476 %} 10477 ins_pipe(pipe_class_compare); 10478 %} 10479 10480 instruct cmpN_reg_imm0(flagsReg crx, iRegNsrc src1, immN_0 src2) %{ 10481 match(Set crx (CmpN src1 src2)); 10482 // Make this more expensive than zeroCheckN_iReg_imm0. 10483 ins_cost(DEFAULT_COST); 10484 10485 format %{ "CMPLWI $crx, $src1, $src2 \t// compressed ptr" %} 10486 size(4); 10487 ins_encode %{ 10488 // TODO: PPC port $archOpcode(ppc64Opcode_cmpli); 10489 __ cmplwi($crx$$CondRegister, $src1$$Register, $src2$$constant); 10490 %} 10491 ins_pipe(pipe_class_compare); 10492 %} 10493 10494 // Implicit zero checks (more implicit null checks). 10495 // No constant pool entries required. 10496 instruct zeroCheckP_reg_imm0(cmpOp cmp, iRegP_N2P value, immP_0 zero, label labl) %{ 10497 match(If cmp (CmpP value zero)); 10498 effect(USE labl); 10499 predicate(TrapBasedNullChecks && 10500 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne && 10501 _leaf->as_If()->_prob >= PROB_LIKELY_MAG(4) && 10502 Matcher::branches_to_uncommon_trap(_leaf)); 10503 10504 ins_is_TrapBasedCheckNode(true); 10505 10506 format %{ "TDI $value $cmp $zero \t// ZeroCheckP => trap $labl" %} 10507 size(4); 10508 ins_encode %{ 10509 // TODO: PPC port $archOpcode(ppc64Opcode_tdi); 10510 if ($cmp$$cmpcode == 0xA) { 10511 __ trap_null_check($value$$Register); 10512 } else { 10513 // Both successors are uncommon traps, probability is 0. 10514 // Node got flipped during fixup flow. 10515 assert($cmp$$cmpcode == 0x2 , "must be equal(0xA) or notEqual(0x2)"); 10516 __ trap_null_check($value$$Register, Assembler::traptoGreaterThanUnsigned); 10517 } 10518 %} 10519 ins_pipe(pipe_class_trap); 10520 %} 10521 10522 // Compare Pointers 10523 instruct cmpP_reg_reg(flagsReg crx, iRegP_N2P src1, iRegP_N2P src2) %{ 10524 match(Set crx (CmpP src1 src2)); 10525 format %{ "CMPLD $crx, $src1, $src2 \t// ptr" %} 10526 size(4); 10527 ins_encode %{ 10528 // TODO: PPC port $archOpcode(ppc64Opcode_cmpl); 10529 __ cmpld($crx$$CondRegister, $src1$$Register, $src2$$Register); 10530 %} 10531 ins_pipe(pipe_class_compare); 10532 %} 10533 10534 // Used in postalloc expand. 10535 instruct cmpP_reg_imm16(flagsReg crx, iRegPsrc src1, immL16 src2) %{ 10536 // This match rule prevents reordering of node before a safepoint. 10537 // This only makes sense if this instructions is used exclusively 10538 // for the expansion of EncodeP! 10539 match(Set crx (CmpP src1 src2)); 10540 predicate(false); 10541 10542 format %{ "CMPDI $crx, $src1, $src2" %} 10543 size(4); 10544 ins_encode %{ 10545 // TODO: PPC port $archOpcode(ppc64Opcode_cmpi); 10546 __ cmpdi($crx$$CondRegister, $src1$$Register, $src2$$constant); 10547 %} 10548 ins_pipe(pipe_class_compare); 10549 %} 10550 10551 //----------Float Compares---------------------------------------------------- 10552 10553 instruct cmpFUnordered_reg_reg(flagsReg crx, regF src1, regF src2) %{ 10554 // no match-rule, false predicate 10555 effect(DEF crx, USE src1, USE src2); 10556 predicate(false); 10557 10558 format %{ "cmpFUrd $crx, $src1, $src2" %} 10559 size(4); 10560 ins_encode %{ 10561 // TODO: PPC port $archOpcode(ppc64Opcode_fcmpu); 10562 __ fcmpu($crx$$CondRegister, $src1$$FloatRegister, $src2$$FloatRegister); 10563 %} 10564 ins_pipe(pipe_class_default); 10565 %} 10566 10567 instruct cmov_bns_less(flagsReg crx) %{ 10568 // no match-rule, false predicate 10569 effect(DEF crx); 10570 predicate(false); 10571 10572 ins_variable_size_depending_on_alignment(true); 10573 10574 format %{ "cmov $crx" %} 10575 // Worst case is branch + move + stop, no stop without scheduler. 10576 size(false /* TODO: PPC PORT(InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 16 : 12); 10577 ins_encode %{ 10578 // TODO: PPC port $archOpcode(ppc64Opcode_cmovecr); 10579 Label done; 10580 __ bns($crx$$CondRegister, done); // not unordered -> keep crx 10581 __ li(R0, 0); 10582 __ cmpwi($crx$$CondRegister, R0, 1); // unordered -> set crx to 'less' 10583 // TODO PPC port __ endgroup_if_needed(_size == 16); 10584 __ bind(done); 10585 %} 10586 ins_pipe(pipe_class_default); 10587 %} 10588 10589 // Compare floating, generate condition code. 10590 instruct cmpF_reg_reg_Ex(flagsReg crx, regF src1, regF src2) %{ 10591 // FIXME: should we match 'If cmp (CmpF src1 src2))' ?? 10592 // 10593 // The following code sequence occurs a lot in mpegaudio: 10594 // 10595 // block BXX: 10596 // 0: instruct cmpFUnordered_reg_reg (cmpF_reg_reg-0): 10597 // cmpFUrd CCR6, F11, F9 10598 // 4: instruct cmov_bns_less (cmpF_reg_reg-1): 10599 // cmov CCR6 10600 // 8: instruct branchConSched: 10601 // B_FARle CCR6, B56 P=0.500000 C=-1.000000 10602 match(Set crx (CmpF src1 src2)); 10603 ins_cost(DEFAULT_COST+BRANCH_COST); 10604 10605 format %{ "CmpF $crx, $src1, $src2 \t// postalloc expanded" %} 10606 postalloc_expand %{ 10607 // 10608 // replaces 10609 // 10610 // region src1 src2 10611 // \ | | 10612 // crx=cmpF_reg_reg 10613 // 10614 // with 10615 // 10616 // region src1 src2 10617 // \ | | 10618 // crx=cmpFUnordered_reg_reg 10619 // | 10620 // ^ region 10621 // | \ 10622 // crx=cmov_bns_less 10623 // 10624 10625 // Create new nodes. 10626 MachNode *m1 = new cmpFUnordered_reg_regNode(); 10627 MachNode *m2 = new cmov_bns_lessNode(); 10628 10629 // inputs for new nodes 10630 m1->add_req(n_region, n_src1, n_src2); 10631 m2->add_req(n_region); 10632 m2->add_prec(m1); 10633 10634 // operands for new nodes 10635 m1->_opnds[0] = op_crx; 10636 m1->_opnds[1] = op_src1; 10637 m1->_opnds[2] = op_src2; 10638 m2->_opnds[0] = op_crx; 10639 10640 // registers for new nodes 10641 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // crx 10642 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // crx 10643 10644 // Insert new nodes. 10645 nodes->push(m1); 10646 nodes->push(m2); 10647 %} 10648 %} 10649 10650 // Compare float, generate -1,0,1 10651 instruct cmpF3_reg_reg_ExEx(iRegIdst dst, regF src1, regF src2) %{ 10652 match(Set dst (CmpF3 src1 src2)); 10653 ins_cost(DEFAULT_COST*5+BRANCH_COST); 10654 10655 expand %{ 10656 flagsReg tmp1; 10657 cmpFUnordered_reg_reg(tmp1, src1, src2); 10658 cmovI_conIvalueMinus1_conIvalue0_conIvalue1_Ex(dst, tmp1); 10659 %} 10660 %} 10661 10662 instruct cmpDUnordered_reg_reg(flagsReg crx, regD src1, regD src2) %{ 10663 // no match-rule, false predicate 10664 effect(DEF crx, USE src1, USE src2); 10665 predicate(false); 10666 10667 format %{ "cmpFUrd $crx, $src1, $src2" %} 10668 size(4); 10669 ins_encode %{ 10670 // TODO: PPC port $archOpcode(ppc64Opcode_fcmpu); 10671 __ fcmpu($crx$$CondRegister, $src1$$FloatRegister, $src2$$FloatRegister); 10672 %} 10673 ins_pipe(pipe_class_default); 10674 %} 10675 10676 instruct cmpD_reg_reg_Ex(flagsReg crx, regD src1, regD src2) %{ 10677 match(Set crx (CmpD src1 src2)); 10678 ins_cost(DEFAULT_COST+BRANCH_COST); 10679 10680 format %{ "CmpD $crx, $src1, $src2 \t// postalloc expanded" %} 10681 postalloc_expand %{ 10682 // 10683 // replaces 10684 // 10685 // region src1 src2 10686 // \ | | 10687 // crx=cmpD_reg_reg 10688 // 10689 // with 10690 // 10691 // region src1 src2 10692 // \ | | 10693 // crx=cmpDUnordered_reg_reg 10694 // | 10695 // ^ region 10696 // | \ 10697 // crx=cmov_bns_less 10698 // 10699 10700 // create new nodes 10701 MachNode *m1 = new cmpDUnordered_reg_regNode(); 10702 MachNode *m2 = new cmov_bns_lessNode(); 10703 10704 // inputs for new nodes 10705 m1->add_req(n_region, n_src1, n_src2); 10706 m2->add_req(n_region); 10707 m2->add_prec(m1); 10708 10709 // operands for new nodes 10710 m1->_opnds[0] = op_crx; 10711 m1->_opnds[1] = op_src1; 10712 m1->_opnds[2] = op_src2; 10713 m2->_opnds[0] = op_crx; 10714 10715 // registers for new nodes 10716 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // crx 10717 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // crx 10718 10719 // Insert new nodes. 10720 nodes->push(m1); 10721 nodes->push(m2); 10722 %} 10723 %} 10724 10725 // Compare double, generate -1,0,1 10726 instruct cmpD3_reg_reg_ExEx(iRegIdst dst, regD src1, regD src2) %{ 10727 match(Set dst (CmpD3 src1 src2)); 10728 ins_cost(DEFAULT_COST*5+BRANCH_COST); 10729 10730 expand %{ 10731 flagsReg tmp1; 10732 cmpDUnordered_reg_reg(tmp1, src1, src2); 10733 cmovI_conIvalueMinus1_conIvalue0_conIvalue1_Ex(dst, tmp1); 10734 %} 10735 %} 10736 10737 //----------Branches--------------------------------------------------------- 10738 // Jump 10739 10740 // Direct Branch. 10741 instruct branch(label labl) %{ 10742 match(Goto); 10743 effect(USE labl); 10744 ins_cost(BRANCH_COST); 10745 10746 format %{ "B $labl" %} 10747 size(4); 10748 ins_encode %{ 10749 // TODO: PPC port $archOpcode(ppc64Opcode_b); 10750 Label d; // dummy 10751 __ bind(d); 10752 Label* p = $labl$$label; 10753 // `p' is `NULL' when this encoding class is used only to 10754 // determine the size of the encoded instruction. 10755 Label& l = (NULL == p)? d : *(p); 10756 __ b(l); 10757 %} 10758 ins_pipe(pipe_class_default); 10759 %} 10760 10761 // Conditional Near Branch 10762 instruct branchCon(cmpOp cmp, flagsReg crx, label lbl) %{ 10763 // Same match rule as `branchConFar'. 10764 match(If cmp crx); 10765 effect(USE lbl); 10766 ins_cost(BRANCH_COST); 10767 10768 // If set to 1 this indicates that the current instruction is a 10769 // short variant of a long branch. This avoids using this 10770 // instruction in first-pass matching. It will then only be used in 10771 // the `Shorten_branches' pass. 10772 ins_short_branch(1); 10773 10774 format %{ "B$cmp $crx, $lbl" %} 10775 size(4); 10776 ins_encode( enc_bc(crx, cmp, lbl) ); 10777 ins_pipe(pipe_class_default); 10778 %} 10779 10780 // This is for cases when the ppc64 `bc' instruction does not 10781 // reach far enough. So we emit a far branch here, which is more 10782 // expensive. 10783 // 10784 // Conditional Far Branch 10785 instruct branchConFar(cmpOp cmp, flagsReg crx, label lbl) %{ 10786 // Same match rule as `branchCon'. 10787 match(If cmp crx); 10788 effect(USE crx, USE lbl); 10789 predicate(!false /* TODO: PPC port HB_Schedule*/); 10790 // Higher cost than `branchCon'. 10791 ins_cost(5*BRANCH_COST); 10792 10793 // This is not a short variant of a branch, but the long variant. 10794 ins_short_branch(0); 10795 10796 format %{ "B_FAR$cmp $crx, $lbl" %} 10797 size(8); 10798 ins_encode( enc_bc_far(crx, cmp, lbl) ); 10799 ins_pipe(pipe_class_default); 10800 %} 10801 10802 // Conditional Branch used with Power6 scheduler (can be far or short). 10803 instruct branchConSched(cmpOp cmp, flagsReg crx, label lbl) %{ 10804 // Same match rule as `branchCon'. 10805 match(If cmp crx); 10806 effect(USE crx, USE lbl); 10807 predicate(false /* TODO: PPC port HB_Schedule*/); 10808 // Higher cost than `branchCon'. 10809 ins_cost(5*BRANCH_COST); 10810 10811 // Actually size doesn't depend on alignment but on shortening. 10812 ins_variable_size_depending_on_alignment(true); 10813 // long variant. 10814 ins_short_branch(0); 10815 10816 format %{ "B_FAR$cmp $crx, $lbl" %} 10817 size(8); // worst case 10818 ins_encode( enc_bc_short_far(crx, cmp, lbl) ); 10819 ins_pipe(pipe_class_default); 10820 %} 10821 10822 instruct branchLoopEnd(cmpOp cmp, flagsReg crx, label labl) %{ 10823 match(CountedLoopEnd cmp crx); 10824 effect(USE labl); 10825 ins_cost(BRANCH_COST); 10826 10827 // short variant. 10828 ins_short_branch(1); 10829 10830 format %{ "B$cmp $crx, $labl \t// counted loop end" %} 10831 size(4); 10832 ins_encode( enc_bc(crx, cmp, labl) ); 10833 ins_pipe(pipe_class_default); 10834 %} 10835 10836 instruct branchLoopEndFar(cmpOp cmp, flagsReg crx, label labl) %{ 10837 match(CountedLoopEnd cmp crx); 10838 effect(USE labl); 10839 predicate(!false /* TODO: PPC port HB_Schedule */); 10840 ins_cost(BRANCH_COST); 10841 10842 // Long variant. 10843 ins_short_branch(0); 10844 10845 format %{ "B_FAR$cmp $crx, $labl \t// counted loop end" %} 10846 size(8); 10847 ins_encode( enc_bc_far(crx, cmp, labl) ); 10848 ins_pipe(pipe_class_default); 10849 %} 10850 10851 // Conditional Branch used with Power6 scheduler (can be far or short). 10852 instruct branchLoopEndSched(cmpOp cmp, flagsReg crx, label labl) %{ 10853 match(CountedLoopEnd cmp crx); 10854 effect(USE labl); 10855 predicate(false /* TODO: PPC port HB_Schedule */); 10856 // Higher cost than `branchCon'. 10857 ins_cost(5*BRANCH_COST); 10858 10859 // Actually size doesn't depend on alignment but on shortening. 10860 ins_variable_size_depending_on_alignment(true); 10861 // Long variant. 10862 ins_short_branch(0); 10863 10864 format %{ "B_FAR$cmp $crx, $labl \t// counted loop end" %} 10865 size(8); // worst case 10866 ins_encode( enc_bc_short_far(crx, cmp, labl) ); 10867 ins_pipe(pipe_class_default); 10868 %} 10869 10870 // ============================================================================ 10871 // Java runtime operations, intrinsics and other complex operations. 10872 10873 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass 10874 // array for an instance of the superklass. Set a hidden internal cache on a 10875 // hit (cache is checked with exposed code in gen_subtype_check()). Return 10876 // not zero for a miss or zero for a hit. The encoding ALSO sets flags. 10877 // 10878 // GL TODO: Improve this. 10879 // - result should not be a TEMP 10880 // - Add match rule as on sparc avoiding additional Cmp. 10881 instruct partialSubtypeCheck(iRegPdst result, iRegP_N2P subklass, iRegP_N2P superklass, 10882 iRegPdst tmp_klass, iRegPdst tmp_arrayptr) %{ 10883 match(Set result (PartialSubtypeCheck subklass superklass)); 10884 effect(TEMP result, TEMP tmp_klass, TEMP tmp_arrayptr); 10885 ins_cost(DEFAULT_COST*10); 10886 10887 format %{ "PartialSubtypeCheck $result = ($subklass instanceOf $superklass) tmp: $tmp_klass, $tmp_arrayptr" %} 10888 ins_encode %{ 10889 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 10890 __ check_klass_subtype_slow_path($subklass$$Register, $superklass$$Register, $tmp_arrayptr$$Register, 10891 $tmp_klass$$Register, NULL, $result$$Register); 10892 %} 10893 ins_pipe(pipe_class_default); 10894 %} 10895 10896 // inlined locking and unlocking 10897 10898 instruct cmpFastLock(flagsReg crx, iRegPdst oop, iRegPdst box, iRegPdst tmp1, iRegPdst tmp2, iRegPdst tmp3) %{ 10899 match(Set crx (FastLock oop box)); 10900 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3); 10901 // TODO PPC port predicate(!UseNewFastLockPPC64 || UseBiasedLocking); 10902 10903 format %{ "FASTLOCK $oop, $box, $tmp1, $tmp2, $tmp3" %} 10904 ins_encode %{ 10905 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 10906 __ compiler_fast_lock_object($crx$$CondRegister, $oop$$Register, $box$$Register, 10907 $tmp3$$Register, $tmp1$$Register, $tmp2$$Register); 10908 // If locking was successfull, crx should indicate 'EQ'. 10909 // The compiler generates a branch to the runtime call to 10910 // _complete_monitor_locking_Java for the case where crx is 'NE'. 10911 %} 10912 ins_pipe(pipe_class_compare); 10913 %} 10914 10915 instruct cmpFastUnlock(flagsReg crx, iRegPdst oop, iRegPdst box, iRegPdst tmp1, iRegPdst tmp2, iRegPdst tmp3) %{ 10916 match(Set crx (FastUnlock oop box)); 10917 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3); 10918 10919 format %{ "FASTUNLOCK $oop, $box, $tmp1, $tmp2" %} 10920 ins_encode %{ 10921 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 10922 __ compiler_fast_unlock_object($crx$$CondRegister, $oop$$Register, $box$$Register, 10923 $tmp3$$Register, $tmp1$$Register, $tmp2$$Register); 10924 // If unlocking was successfull, crx should indicate 'EQ'. 10925 // The compiler generates a branch to the runtime call to 10926 // _complete_monitor_unlocking_Java for the case where crx is 'NE'. 10927 %} 10928 ins_pipe(pipe_class_compare); 10929 %} 10930 10931 // Align address. 10932 instruct align_addr(iRegPdst dst, iRegPsrc src, immLnegpow2 mask) %{ 10933 match(Set dst (CastX2P (AndL (CastP2X src) mask))); 10934 10935 format %{ "ANDDI $dst, $src, $mask \t// next aligned address" %} 10936 size(4); 10937 ins_encode %{ 10938 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr); 10939 __ clrrdi($dst$$Register, $src$$Register, log2_long((jlong)-$mask$$constant)); 10940 %} 10941 ins_pipe(pipe_class_default); 10942 %} 10943 10944 // Array size computation. 10945 instruct array_size(iRegLdst dst, iRegPsrc end, iRegPsrc start) %{ 10946 match(Set dst (SubL (CastP2X end) (CastP2X start))); 10947 10948 format %{ "SUB $dst, $end, $start \t// array size in bytes" %} 10949 size(4); 10950 ins_encode %{ 10951 // TODO: PPC port $archOpcode(ppc64Opcode_subf); 10952 __ subf($dst$$Register, $start$$Register, $end$$Register); 10953 %} 10954 ins_pipe(pipe_class_default); 10955 %} 10956 10957 // Clear-array with dynamic array-size. 10958 instruct inlineCallClearArray(rarg1RegL cnt, rarg2RegP base, Universe dummy, regCTR ctr) %{ 10959 match(Set dummy (ClearArray cnt base)); 10960 effect(USE_KILL cnt, USE_KILL base, KILL ctr); 10961 ins_cost(MEMORY_REF_COST); 10962 10963 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted. 10964 10965 format %{ "ClearArray $cnt, $base" %} 10966 ins_encode %{ 10967 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 10968 __ clear_memory_doubleword($base$$Register, $cnt$$Register); // kills cnt, base, R0 10969 %} 10970 ins_pipe(pipe_class_default); 10971 %} 10972 10973 // String_IndexOf for needle of length 1. 10974 // 10975 // Match needle into immediate operands: no loadConP node needed. Saves one 10976 // register and two instructions over string_indexOf_imm1Node. 10977 // 10978 // Assumes register result differs from all input registers. 10979 // 10980 // Preserves registers haystack, haycnt 10981 // Kills registers tmp1, tmp2 10982 // Defines registers result 10983 // 10984 // Use dst register classes if register gets killed, as it is the case for tmp registers! 10985 // 10986 // Unfortunately this does not match too often. In many situations the AddP is used 10987 // by several nodes, even several StrIndexOf nodes, breaking the match tree. 10988 instruct string_indexOf_imm1_char(iRegIdst result, iRegPsrc haystack, iRegIsrc haycnt, 10989 immP needleImm, immL offsetImm, immI_1 needlecntImm, 10990 iRegIdst tmp1, iRegIdst tmp2, 10991 flagsRegCR0 cr0, flagsRegCR1 cr1) %{ 10992 predicate(SpecialStringIndexOf); // type check implicit by parameter type, See Matcher::match_rule_supported 10993 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary (AddP needleImm offsetImm) needlecntImm))); 10994 10995 effect(TEMP result, TEMP tmp1, TEMP tmp2, KILL cr0, KILL cr1); 10996 10997 ins_cost(150); 10998 format %{ "String IndexOf CSCL1 $haystack[0..$haycnt], $needleImm+$offsetImm[0..$needlecntImm]" 10999 "-> $result \t// KILL $haycnt, $tmp1, $tmp2, $cr0, $cr1" %} 11000 11001 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted 11002 ins_encode %{ 11003 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 11004 immPOper *needleOper = (immPOper *)$needleImm; 11005 const TypeOopPtr *t = needleOper->type()->isa_oopptr(); 11006 ciTypeArray* needle_values = t->const_oop()->as_type_array(); // Pointer to live char * 11007 11008 __ string_indexof_1($result$$Register, 11009 $haystack$$Register, $haycnt$$Register, 11010 R0, needle_values->char_at(0), 11011 $tmp1$$Register, $tmp2$$Register); 11012 %} 11013 ins_pipe(pipe_class_compare); 11014 %} 11015 11016 // String_IndexOf for needle of length 1. 11017 // 11018 // Special case requires less registers and emits less instructions. 11019 // 11020 // Assumes register result differs from all input registers. 11021 // 11022 // Preserves registers haystack, haycnt 11023 // Kills registers tmp1, tmp2, needle 11024 // Defines registers result 11025 // 11026 // Use dst register classes if register gets killed, as it is the case for tmp registers! 11027 instruct string_indexOf_imm1(iRegIdst result, iRegPsrc haystack, iRegIsrc haycnt, 11028 rscratch2RegP needle, immI_1 needlecntImm, 11029 iRegIdst tmp1, iRegIdst tmp2, 11030 flagsRegCR0 cr0, flagsRegCR1 cr1) %{ 11031 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecntImm))); 11032 effect(USE_KILL needle, /* TDEF needle, */ TEMP result, 11033 TEMP tmp1, TEMP tmp2); 11034 // Required for EA: check if it is still a type_array. 11035 predicate(SpecialStringIndexOf && n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop() && 11036 n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop()->is_type_array()); 11037 ins_cost(180); 11038 11039 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted. 11040 11041 format %{ "String IndexOf SCL1 $haystack[0..$haycnt], $needle[0..$needlecntImm]" 11042 " -> $result \t// KILL $haycnt, $needle, $tmp1, $tmp2, $cr0, $cr1" %} 11043 ins_encode %{ 11044 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 11045 Node *ndl = in(operand_index($needle)); // The node that defines needle. 11046 ciTypeArray* needle_values = ndl->bottom_type()->is_aryptr()->const_oop()->as_type_array(); 11047 guarantee(needle_values, "sanity"); 11048 if (needle_values != NULL) { 11049 __ string_indexof_1($result$$Register, 11050 $haystack$$Register, $haycnt$$Register, 11051 R0, needle_values->char_at(0), 11052 $tmp1$$Register, $tmp2$$Register); 11053 } else { 11054 __ string_indexof_1($result$$Register, 11055 $haystack$$Register, $haycnt$$Register, 11056 $needle$$Register, 0, 11057 $tmp1$$Register, $tmp2$$Register); 11058 } 11059 %} 11060 ins_pipe(pipe_class_compare); 11061 %} 11062 11063 // String_IndexOf. 11064 // 11065 // Length of needle as immediate. This saves instruction loading constant needle 11066 // length. 11067 // @@@ TODO Specify rules for length < 8 or so, and roll out comparison of needle 11068 // completely or do it in vector instruction. This should save registers for 11069 // needlecnt and needle. 11070 // 11071 // Assumes register result differs from all input registers. 11072 // Overwrites haycnt, needlecnt. 11073 // Use dst register classes if register gets killed, as it is the case for tmp registers! 11074 instruct string_indexOf_imm(iRegIdst result, iRegPsrc haystack, rscratch1RegI haycnt, 11075 iRegPsrc needle, uimmI15 needlecntImm, 11076 iRegIdst tmp1, iRegIdst tmp2, iRegIdst tmp3, iRegIdst tmp4, iRegIdst tmp5, 11077 flagsRegCR0 cr0, flagsRegCR1 cr1, flagsRegCR6 cr6) %{ 11078 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecntImm))); 11079 effect(USE_KILL haycnt, /* better: TDEF haycnt, */ TEMP result, 11080 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5, KILL cr0, KILL cr1, KILL cr6); 11081 // Required for EA: check if it is still a type_array. 11082 predicate(SpecialStringIndexOf && n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop() && 11083 n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop()->is_type_array()); 11084 ins_cost(250); 11085 11086 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted. 11087 11088 format %{ "String IndexOf SCL $haystack[0..$haycnt], $needle[0..$needlecntImm]" 11089 " -> $result \t// KILL $haycnt, $tmp1, $tmp2, $tmp3, $tmp4, $tmp5, $cr0, $cr1" %} 11090 ins_encode %{ 11091 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 11092 Node *ndl = in(operand_index($needle)); // The node that defines needle. 11093 ciTypeArray* needle_values = ndl->bottom_type()->is_aryptr()->const_oop()->as_type_array(); 11094 11095 __ string_indexof($result$$Register, 11096 $haystack$$Register, $haycnt$$Register, 11097 $needle$$Register, needle_values, $tmp5$$Register, $needlecntImm$$constant, 11098 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register); 11099 %} 11100 ins_pipe(pipe_class_compare); 11101 %} 11102 11103 // StrIndexOf node. 11104 // 11105 // Assumes register result differs from all input registers. 11106 // Overwrites haycnt, needlecnt. 11107 // Use dst register classes if register gets killed, as it is the case for tmp registers! 11108 instruct string_indexOf(iRegIdst result, iRegPsrc haystack, rscratch1RegI haycnt, iRegPsrc needle, rscratch2RegI needlecnt, 11109 iRegLdst tmp1, iRegLdst tmp2, iRegLdst tmp3, iRegLdst tmp4, 11110 flagsRegCR0 cr0, flagsRegCR1 cr1, flagsRegCR6 cr6) %{ 11111 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecnt))); 11112 effect(USE_KILL haycnt, USE_KILL needlecnt, /*better: TDEF haycnt, TDEF needlecnt,*/ 11113 TEMP result, 11114 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL cr0, KILL cr1, KILL cr6); 11115 predicate(SpecialStringIndexOf); // See Matcher::match_rule_supported. 11116 ins_cost(300); 11117 11118 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted. 11119 11120 format %{ "String IndexOf $haystack[0..$haycnt], $needle[0..$needlecnt]" 11121 " -> $result \t// KILL $haycnt, $needlecnt, $tmp1, $tmp2, $tmp3, $tmp4, $cr0, $cr1" %} 11122 ins_encode %{ 11123 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 11124 __ string_indexof($result$$Register, 11125 $haystack$$Register, $haycnt$$Register, 11126 $needle$$Register, NULL, $needlecnt$$Register, 0, // needlecnt not constant. 11127 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register); 11128 %} 11129 ins_pipe(pipe_class_compare); 11130 %} 11131 11132 // String equals with immediate. 11133 instruct string_equals_imm(iRegPsrc str1, iRegPsrc str2, uimmI15 cntImm, iRegIdst result, 11134 iRegPdst tmp1, iRegPdst tmp2, 11135 flagsRegCR0 cr0, flagsRegCR6 cr6, regCTR ctr) %{ 11136 match(Set result (StrEquals (Binary str1 str2) cntImm)); 11137 effect(TEMP result, TEMP tmp1, TEMP tmp2, 11138 KILL cr0, KILL cr6, KILL ctr); 11139 predicate(SpecialStringEquals); // See Matcher::match_rule_supported. 11140 ins_cost(250); 11141 11142 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted. 11143 11144 format %{ "String Equals SCL [0..$cntImm]($str1),[0..$cntImm]($str2)" 11145 " -> $result \t// KILL $cr0, $cr6, $ctr, TEMP $result, $tmp1, $tmp2" %} 11146 ins_encode %{ 11147 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 11148 __ char_arrays_equalsImm($str1$$Register, $str2$$Register, $cntImm$$constant, 11149 $result$$Register, $tmp1$$Register, $tmp2$$Register); 11150 %} 11151 ins_pipe(pipe_class_compare); 11152 %} 11153 11154 // String equals. 11155 // Use dst register classes if register gets killed, as it is the case for TEMP operands! 11156 instruct string_equals(iRegPsrc str1, iRegPsrc str2, iRegIsrc cnt, iRegIdst result, 11157 iRegPdst tmp1, iRegPdst tmp2, iRegPdst tmp3, iRegPdst tmp4, iRegPdst tmp5, 11158 flagsRegCR0 cr0, flagsRegCR1 cr1, flagsRegCR6 cr6, regCTR ctr) %{ 11159 match(Set result (StrEquals (Binary str1 str2) cnt)); 11160 effect(TEMP result, TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5, 11161 KILL cr0, KILL cr1, KILL cr6, KILL ctr); 11162 predicate(SpecialStringEquals); // See Matcher::match_rule_supported. 11163 ins_cost(300); 11164 11165 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted. 11166 11167 format %{ "String Equals [0..$cnt]($str1),[0..$cnt]($str2) -> $result" 11168 " \t// KILL $cr0, $cr1, $cr6, $ctr, TEMP $result, $tmp1, $tmp2, $tmp3, $tmp4, $tmp5" %} 11169 ins_encode %{ 11170 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 11171 __ char_arrays_equals($str1$$Register, $str2$$Register, $cnt$$Register, $result$$Register, 11172 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register, $tmp5$$Register); 11173 %} 11174 ins_pipe(pipe_class_compare); 11175 %} 11176 11177 // String compare. 11178 // Char[] pointers are passed in. 11179 // Use dst register classes if register gets killed, as it is the case for TEMP operands! 11180 instruct string_compare(rarg1RegP str1, rarg2RegP str2, rarg3RegI cnt1, rarg4RegI cnt2, iRegIdst result, 11181 iRegPdst tmp, flagsRegCR0 cr0, regCTR ctr) %{ 11182 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2))); 11183 effect(USE_KILL cnt1, USE_KILL cnt2, USE_KILL str1, USE_KILL str2, TEMP result, TEMP tmp, KILL cr0, KILL ctr); 11184 ins_cost(300); 11185 11186 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted. 11187 11188 format %{ "String Compare $str1[0..$cnt1], $str2[0..$cnt2] -> $result" 11189 " \t// TEMP $tmp, $result KILLs $str1, $cnt1, $str2, $cnt2, $cr0, $ctr" %} 11190 ins_encode %{ 11191 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 11192 __ string_compare($str1$$Register, $str2$$Register, $cnt1$$Register, $cnt2$$Register, 11193 $result$$Register, $tmp$$Register); 11194 %} 11195 ins_pipe(pipe_class_compare); 11196 %} 11197 11198 //---------- Min/Max Instructions --------------------------------------------- 11199 11200 instruct minI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ 11201 match(Set dst (MinI src1 src2)); 11202 ins_cost(DEFAULT_COST*6); 11203 11204 expand %{ 11205 iRegLdst src1s; 11206 iRegLdst src2s; 11207 iRegLdst diff; 11208 iRegLdst sm; 11209 iRegLdst doz; // difference or zero 11210 convI2L_reg(src1s, src1); // Ensure proper sign extension. 11211 convI2L_reg(src2s, src2); // Ensure proper sign extension. 11212 subL_reg_reg(diff, src2s, src1s); 11213 // Need to consider >=33 bit result, therefore we need signmaskL. 11214 signmask64L_regL(sm, diff); 11215 andL_reg_reg(doz, diff, sm); // <=0 11216 addI_regL_regL(dst, doz, src1s); 11217 %} 11218 %} 11219 11220 instruct maxI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ 11221 match(Set dst (MaxI src1 src2)); 11222 ins_cost(DEFAULT_COST*6); 11223 11224 expand %{ 11225 iRegLdst src1s; 11226 iRegLdst src2s; 11227 iRegLdst diff; 11228 iRegLdst sm; 11229 iRegLdst doz; // difference or zero 11230 convI2L_reg(src1s, src1); // Ensure proper sign extension. 11231 convI2L_reg(src2s, src2); // Ensure proper sign extension. 11232 subL_reg_reg(diff, src2s, src1s); 11233 // Need to consider >=33 bit result, therefore we need signmaskL. 11234 signmask64L_regL(sm, diff); 11235 andcL_reg_reg(doz, diff, sm); // >=0 11236 addI_regL_regL(dst, doz, src1s); 11237 %} 11238 %} 11239 11240 //---------- Population Count Instructions ------------------------------------ 11241 11242 // Popcnt for Power7. 11243 instruct popCountI(iRegIdst dst, iRegIsrc src) %{ 11244 match(Set dst (PopCountI src)); 11245 predicate(UsePopCountInstruction && VM_Version::has_popcntw()); 11246 ins_cost(DEFAULT_COST); 11247 11248 format %{ "POPCNTW $dst, $src" %} 11249 size(4); 11250 ins_encode %{ 11251 // TODO: PPC port $archOpcode(ppc64Opcode_popcntb); 11252 __ popcntw($dst$$Register, $src$$Register); 11253 %} 11254 ins_pipe(pipe_class_default); 11255 %} 11256 11257 // Popcnt for Power7. 11258 instruct popCountL(iRegIdst dst, iRegLsrc src) %{ 11259 predicate(UsePopCountInstruction && VM_Version::has_popcntw()); 11260 match(Set dst (PopCountL src)); 11261 ins_cost(DEFAULT_COST); 11262 11263 format %{ "POPCNTD $dst, $src" %} 11264 size(4); 11265 ins_encode %{ 11266 // TODO: PPC port $archOpcode(ppc64Opcode_popcntb); 11267 __ popcntd($dst$$Register, $src$$Register); 11268 %} 11269 ins_pipe(pipe_class_default); 11270 %} 11271 11272 instruct countLeadingZerosI(iRegIdst dst, iRegIsrc src) %{ 11273 match(Set dst (CountLeadingZerosI src)); 11274 predicate(UseCountLeadingZerosInstructionsPPC64); // See Matcher::match_rule_supported. 11275 ins_cost(DEFAULT_COST); 11276 11277 format %{ "CNTLZW $dst, $src" %} 11278 size(4); 11279 ins_encode %{ 11280 // TODO: PPC port $archOpcode(ppc64Opcode_cntlzw); 11281 __ cntlzw($dst$$Register, $src$$Register); 11282 %} 11283 ins_pipe(pipe_class_default); 11284 %} 11285 11286 instruct countLeadingZerosL(iRegIdst dst, iRegLsrc src) %{ 11287 match(Set dst (CountLeadingZerosL src)); 11288 predicate(UseCountLeadingZerosInstructionsPPC64); // See Matcher::match_rule_supported. 11289 ins_cost(DEFAULT_COST); 11290 11291 format %{ "CNTLZD $dst, $src" %} 11292 size(4); 11293 ins_encode %{ 11294 // TODO: PPC port $archOpcode(ppc64Opcode_cntlzd); 11295 __ cntlzd($dst$$Register, $src$$Register); 11296 %} 11297 ins_pipe(pipe_class_default); 11298 %} 11299 11300 instruct countLeadingZerosP(iRegIdst dst, iRegPsrc src) %{ 11301 // no match-rule, false predicate 11302 effect(DEF dst, USE src); 11303 predicate(false); 11304 11305 format %{ "CNTLZD $dst, $src" %} 11306 size(4); 11307 ins_encode %{ 11308 // TODO: PPC port $archOpcode(ppc64Opcode_cntlzd); 11309 __ cntlzd($dst$$Register, $src$$Register); 11310 %} 11311 ins_pipe(pipe_class_default); 11312 %} 11313 11314 instruct countTrailingZerosI_Ex(iRegIdst dst, iRegIsrc src) %{ 11315 match(Set dst (CountTrailingZerosI src)); 11316 predicate(UseCountLeadingZerosInstructionsPPC64); 11317 ins_cost(DEFAULT_COST); 11318 11319 expand %{ 11320 immI16 imm1 %{ (int)-1 %} 11321 immI16 imm2 %{ (int)32 %} 11322 immI_minus1 m1 %{ -1 %} 11323 iRegIdst tmpI1; 11324 iRegIdst tmpI2; 11325 iRegIdst tmpI3; 11326 addI_reg_imm16(tmpI1, src, imm1); 11327 andcI_reg_reg(tmpI2, src, m1, tmpI1); 11328 countLeadingZerosI(tmpI3, tmpI2); 11329 subI_imm16_reg(dst, imm2, tmpI3); 11330 %} 11331 %} 11332 11333 instruct countTrailingZerosL_Ex(iRegIdst dst, iRegLsrc src) %{ 11334 match(Set dst (CountTrailingZerosL src)); 11335 predicate(UseCountLeadingZerosInstructionsPPC64); 11336 ins_cost(DEFAULT_COST); 11337 11338 expand %{ 11339 immL16 imm1 %{ (long)-1 %} 11340 immI16 imm2 %{ (int)64 %} 11341 iRegLdst tmpL1; 11342 iRegLdst tmpL2; 11343 iRegIdst tmpL3; 11344 addL_reg_imm16(tmpL1, src, imm1); 11345 andcL_reg_reg(tmpL2, tmpL1, src); 11346 countLeadingZerosL(tmpL3, tmpL2); 11347 subI_imm16_reg(dst, imm2, tmpL3); 11348 %} 11349 %} 11350 11351 // Expand nodes for byte_reverse_int. 11352 instruct insrwi_a(iRegIdst dst, iRegIsrc src, immI16 pos, immI16 shift) %{ 11353 effect(DEF dst, USE src, USE pos, USE shift); 11354 predicate(false); 11355 11356 format %{ "INSRWI $dst, $src, $pos, $shift" %} 11357 size(4); 11358 ins_encode %{ 11359 // TODO: PPC port $archOpcode(ppc64Opcode_rlwimi); 11360 __ insrwi($dst$$Register, $src$$Register, $shift$$constant, $pos$$constant); 11361 %} 11362 ins_pipe(pipe_class_default); 11363 %} 11364 11365 // As insrwi_a, but with USE_DEF. 11366 instruct insrwi(iRegIdst dst, iRegIsrc src, immI16 pos, immI16 shift) %{ 11367 effect(USE_DEF dst, USE src, USE pos, USE shift); 11368 predicate(false); 11369 11370 format %{ "INSRWI $dst, $src, $pos, $shift" %} 11371 size(4); 11372 ins_encode %{ 11373 // TODO: PPC port $archOpcode(ppc64Opcode_rlwimi); 11374 __ insrwi($dst$$Register, $src$$Register, $shift$$constant, $pos$$constant); 11375 %} 11376 ins_pipe(pipe_class_default); 11377 %} 11378 11379 // Just slightly faster than java implementation. 11380 instruct bytes_reverse_int_Ex(iRegIdst dst, iRegIsrc src) %{ 11381 match(Set dst (ReverseBytesI src)); 11382 predicate(UseCountLeadingZerosInstructionsPPC64); 11383 ins_cost(DEFAULT_COST); 11384 11385 expand %{ 11386 immI16 imm24 %{ (int) 24 %} 11387 immI16 imm16 %{ (int) 16 %} 11388 immI16 imm8 %{ (int) 8 %} 11389 immI16 imm4 %{ (int) 4 %} 11390 immI16 imm0 %{ (int) 0 %} 11391 iRegLdst tmpI1; 11392 iRegLdst tmpI2; 11393 iRegLdst tmpI3; 11394 11395 urShiftI_reg_imm(tmpI1, src, imm24); 11396 insrwi_a(dst, tmpI1, imm24, imm8); 11397 urShiftI_reg_imm(tmpI2, src, imm16); 11398 insrwi(dst, tmpI2, imm8, imm16); 11399 urShiftI_reg_imm(tmpI3, src, imm8); 11400 insrwi(dst, tmpI3, imm8, imm8); 11401 insrwi(dst, src, imm0, imm8); 11402 %} 11403 %} 11404 11405 //---------- Replicate Vector Instructions ------------------------------------ 11406 11407 // Insrdi does replicate if src == dst. 11408 instruct repl32(iRegLdst dst) %{ 11409 predicate(false); 11410 effect(USE_DEF dst); 11411 11412 format %{ "INSRDI $dst, #0, $dst, #32 \t// replicate" %} 11413 size(4); 11414 ins_encode %{ 11415 // TODO: PPC port $archOpcode(ppc64Opcode_rldimi); 11416 __ insrdi($dst$$Register, $dst$$Register, 32, 0); 11417 %} 11418 ins_pipe(pipe_class_default); 11419 %} 11420 11421 // Insrdi does replicate if src == dst. 11422 instruct repl48(iRegLdst dst) %{ 11423 predicate(false); 11424 effect(USE_DEF dst); 11425 11426 format %{ "INSRDI $dst, #0, $dst, #48 \t// replicate" %} 11427 size(4); 11428 ins_encode %{ 11429 // TODO: PPC port $archOpcode(ppc64Opcode_rldimi); 11430 __ insrdi($dst$$Register, $dst$$Register, 48, 0); 11431 %} 11432 ins_pipe(pipe_class_default); 11433 %} 11434 11435 // Insrdi does replicate if src == dst. 11436 instruct repl56(iRegLdst dst) %{ 11437 predicate(false); 11438 effect(USE_DEF dst); 11439 11440 format %{ "INSRDI $dst, #0, $dst, #56 \t// replicate" %} 11441 size(4); 11442 ins_encode %{ 11443 // TODO: PPC port $archOpcode(ppc64Opcode_rldimi); 11444 __ insrdi($dst$$Register, $dst$$Register, 56, 0); 11445 %} 11446 ins_pipe(pipe_class_default); 11447 %} 11448 11449 instruct repl8B_reg_Ex(iRegLdst dst, iRegIsrc src) %{ 11450 match(Set dst (ReplicateB src)); 11451 predicate(n->as_Vector()->length() == 8); 11452 expand %{ 11453 moveReg(dst, src); 11454 repl56(dst); 11455 repl48(dst); 11456 repl32(dst); 11457 %} 11458 %} 11459 11460 instruct repl8B_immI0(iRegLdst dst, immI_0 zero) %{ 11461 match(Set dst (ReplicateB zero)); 11462 predicate(n->as_Vector()->length() == 8); 11463 format %{ "LI $dst, #0 \t// replicate8B" %} 11464 size(4); 11465 ins_encode %{ 11466 // TODO: PPC port $archOpcode(ppc64Opcode_addi); 11467 __ li($dst$$Register, (int)((short)($zero$$constant & 0xFFFF))); 11468 %} 11469 ins_pipe(pipe_class_default); 11470 %} 11471 11472 instruct repl8B_immIminus1(iRegLdst dst, immI_minus1 src) %{ 11473 match(Set dst (ReplicateB src)); 11474 predicate(n->as_Vector()->length() == 8); 11475 format %{ "LI $dst, #-1 \t// replicate8B" %} 11476 size(4); 11477 ins_encode %{ 11478 // TODO: PPC port $archOpcode(ppc64Opcode_addi); 11479 __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF))); 11480 %} 11481 ins_pipe(pipe_class_default); 11482 %} 11483 11484 instruct repl4S_reg_Ex(iRegLdst dst, iRegIsrc src) %{ 11485 match(Set dst (ReplicateS src)); 11486 predicate(n->as_Vector()->length() == 4); 11487 expand %{ 11488 moveReg(dst, src); 11489 repl48(dst); 11490 repl32(dst); 11491 %} 11492 %} 11493 11494 instruct repl4S_immI0(iRegLdst dst, immI_0 zero) %{ 11495 match(Set dst (ReplicateS zero)); 11496 predicate(n->as_Vector()->length() == 4); 11497 format %{ "LI $dst, #0 \t// replicate4C" %} 11498 size(4); 11499 ins_encode %{ 11500 // TODO: PPC port $archOpcode(ppc64Opcode_addi); 11501 __ li($dst$$Register, (int)((short)($zero$$constant & 0xFFFF))); 11502 %} 11503 ins_pipe(pipe_class_default); 11504 %} 11505 11506 instruct repl4S_immIminus1(iRegLdst dst, immI_minus1 src) %{ 11507 match(Set dst (ReplicateS src)); 11508 predicate(n->as_Vector()->length() == 4); 11509 format %{ "LI $dst, -1 \t// replicate4C" %} 11510 size(4); 11511 ins_encode %{ 11512 // TODO: PPC port $archOpcode(ppc64Opcode_addi); 11513 __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF))); 11514 %} 11515 ins_pipe(pipe_class_default); 11516 %} 11517 11518 instruct repl2I_reg_Ex(iRegLdst dst, iRegIsrc src) %{ 11519 match(Set dst (ReplicateI src)); 11520 predicate(n->as_Vector()->length() == 2); 11521 ins_cost(2 * DEFAULT_COST); 11522 expand %{ 11523 moveReg(dst, src); 11524 repl32(dst); 11525 %} 11526 %} 11527 11528 instruct repl2I_immI0(iRegLdst dst, immI_0 zero) %{ 11529 match(Set dst (ReplicateI zero)); 11530 predicate(n->as_Vector()->length() == 2); 11531 format %{ "LI $dst, #0 \t// replicate4C" %} 11532 size(4); 11533 ins_encode %{ 11534 // TODO: PPC port $archOpcode(ppc64Opcode_addi); 11535 __ li($dst$$Register, (int)((short)($zero$$constant & 0xFFFF))); 11536 %} 11537 ins_pipe(pipe_class_default); 11538 %} 11539 11540 instruct repl2I_immIminus1(iRegLdst dst, immI_minus1 src) %{ 11541 match(Set dst (ReplicateI src)); 11542 predicate(n->as_Vector()->length() == 2); 11543 format %{ "LI $dst, -1 \t// replicate4C" %} 11544 size(4); 11545 ins_encode %{ 11546 // TODO: PPC port $archOpcode(ppc64Opcode_addi); 11547 __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF))); 11548 %} 11549 ins_pipe(pipe_class_default); 11550 %} 11551 11552 // Move float to int register via stack, replicate. 11553 instruct repl2F_reg_Ex(iRegLdst dst, regF src) %{ 11554 match(Set dst (ReplicateF src)); 11555 predicate(n->as_Vector()->length() == 2); 11556 ins_cost(2 * MEMORY_REF_COST + DEFAULT_COST); 11557 expand %{ 11558 stackSlotL tmpS; 11559 iRegIdst tmpI; 11560 moveF2I_reg_stack(tmpS, src); // Move float to stack. 11561 moveF2I_stack_reg(tmpI, tmpS); // Move stack to int reg. 11562 moveReg(dst, tmpI); // Move int to long reg. 11563 repl32(dst); // Replicate bitpattern. 11564 %} 11565 %} 11566 11567 // Replicate scalar constant to packed float values in Double register 11568 instruct repl2F_immF_Ex(iRegLdst dst, immF src) %{ 11569 match(Set dst (ReplicateF src)); 11570 predicate(n->as_Vector()->length() == 2); 11571 ins_cost(5 * DEFAULT_COST); 11572 11573 format %{ "LD $dst, offset, $constanttablebase\t// load replicated float $src $src from table, postalloc expanded" %} 11574 postalloc_expand( postalloc_expand_load_replF_constant(dst, src, constanttablebase) ); 11575 %} 11576 11577 // Replicate scalar zero constant to packed float values in Double register 11578 instruct repl2F_immF0(iRegLdst dst, immF_0 zero) %{ 11579 match(Set dst (ReplicateF zero)); 11580 predicate(n->as_Vector()->length() == 2); 11581 11582 format %{ "LI $dst, #0 \t// replicate2F" %} 11583 ins_encode %{ 11584 // TODO: PPC port $archOpcode(ppc64Opcode_addi); 11585 __ li($dst$$Register, 0x0); 11586 %} 11587 ins_pipe(pipe_class_default); 11588 %} 11589 11590 // ============================================================================ 11591 // Safepoint Instruction 11592 11593 instruct safePoint_poll(iRegPdst poll) %{ 11594 match(SafePoint poll); 11595 predicate(LoadPollAddressFromThread); 11596 11597 // It caused problems to add the effect that r0 is killed, but this 11598 // effect no longer needs to be mentioned, since r0 is not contained 11599 // in a reg_class. 11600 11601 format %{ "LD R0, #0, $poll \t// Safepoint poll for GC" %} 11602 size(4); 11603 ins_encode( enc_poll(0x0, poll) ); 11604 ins_pipe(pipe_class_default); 11605 %} 11606 11607 // Safepoint without per-thread support. Load address of page to poll 11608 // as constant. 11609 // Rscratch2RegP is R12. 11610 // LoadConPollAddr node is added in pd_post_matching_hook(). It must be 11611 // a seperate node so that the oop map is at the right location. 11612 instruct safePoint_poll_conPollAddr(rscratch2RegP poll) %{ 11613 match(SafePoint poll); 11614 predicate(!LoadPollAddressFromThread); 11615 11616 // It caused problems to add the effect that r0 is killed, but this 11617 // effect no longer needs to be mentioned, since r0 is not contained 11618 // in a reg_class. 11619 11620 format %{ "LD R0, #0, R12 \t// Safepoint poll for GC" %} 11621 ins_encode( enc_poll(0x0, poll) ); 11622 ins_pipe(pipe_class_default); 11623 %} 11624 11625 // ============================================================================ 11626 // Call Instructions 11627 11628 // Call Java Static Instruction 11629 11630 // Schedulable version of call static node. 11631 instruct CallStaticJavaDirect(method meth) %{ 11632 match(CallStaticJava); 11633 effect(USE meth); 11634 predicate(!((CallStaticJavaNode*)n)->is_method_handle_invoke()); 11635 ins_cost(CALL_COST); 11636 11637 ins_num_consts(3 /* up to 3 patchable constants: inline cache, 2 call targets. */); 11638 11639 format %{ "CALL,static $meth \t// ==> " %} 11640 size(4); 11641 ins_encode( enc_java_static_call(meth) ); 11642 ins_pipe(pipe_class_call); 11643 %} 11644 11645 // Schedulable version of call static node. 11646 instruct CallStaticJavaDirectHandle(method meth) %{ 11647 match(CallStaticJava); 11648 effect(USE meth); 11649 predicate(((CallStaticJavaNode*)n)->is_method_handle_invoke()); 11650 ins_cost(CALL_COST); 11651 11652 ins_num_consts(3 /* up to 3 patchable constants: inline cache, 2 call targets. */); 11653 11654 format %{ "CALL,static $meth \t// ==> " %} 11655 ins_encode( enc_java_handle_call(meth) ); 11656 ins_pipe(pipe_class_call); 11657 %} 11658 11659 // Call Java Dynamic Instruction 11660 11661 // Used by postalloc expand of CallDynamicJavaDirectSchedEx (actual call). 11662 // Loading of IC was postalloc expanded. The nodes loading the IC are reachable 11663 // via fields ins_field_load_ic_hi_node and ins_field_load_ic_node. 11664 // The call destination must still be placed in the constant pool. 11665 instruct CallDynamicJavaDirectSched(method meth) %{ 11666 match(CallDynamicJava); // To get all the data fields we need ... 11667 effect(USE meth); 11668 predicate(false); // ... but never match. 11669 11670 ins_field_load_ic_hi_node(loadConL_hiNode*); 11671 ins_field_load_ic_node(loadConLNode*); 11672 ins_num_consts(1 /* 1 patchable constant: call destination */); 11673 11674 format %{ "BL \t// dynamic $meth ==> " %} 11675 size(4); 11676 ins_encode( enc_java_dynamic_call_sched(meth) ); 11677 ins_pipe(pipe_class_call); 11678 %} 11679 11680 // Schedulable (i.e. postalloc expanded) version of call dynamic java. 11681 // We use postalloc expanded calls if we use inline caches 11682 // and do not update method data. 11683 // 11684 // This instruction has two constants: inline cache (IC) and call destination. 11685 // Loading the inline cache will be postalloc expanded, thus leaving a call with 11686 // one constant. 11687 instruct CallDynamicJavaDirectSched_Ex(method meth) %{ 11688 match(CallDynamicJava); 11689 effect(USE meth); 11690 predicate(UseInlineCaches); 11691 ins_cost(CALL_COST); 11692 11693 ins_num_consts(2 /* 2 patchable constants: inline cache, call destination. */); 11694 11695 format %{ "CALL,dynamic $meth \t// postalloc expanded" %} 11696 postalloc_expand( postalloc_expand_java_dynamic_call_sched(meth, constanttablebase) ); 11697 %} 11698 11699 // Compound version of call dynamic java 11700 // We use postalloc expanded calls if we use inline caches 11701 // and do not update method data. 11702 instruct CallDynamicJavaDirect(method meth) %{ 11703 match(CallDynamicJava); 11704 effect(USE meth); 11705 predicate(!UseInlineCaches); 11706 ins_cost(CALL_COST); 11707 11708 // Enc_java_to_runtime_call needs up to 4 constants (method data oop). 11709 ins_num_consts(4); 11710 11711 format %{ "CALL,dynamic $meth \t// ==> " %} 11712 ins_encode( enc_java_dynamic_call(meth, constanttablebase) ); 11713 ins_pipe(pipe_class_call); 11714 %} 11715 11716 // Call Runtime Instruction 11717 11718 instruct CallRuntimeDirect(method meth) %{ 11719 match(CallRuntime); 11720 effect(USE meth); 11721 ins_cost(CALL_COST); 11722 11723 // Enc_java_to_runtime_call needs up to 3 constants: call target, 11724 // env for callee, C-toc. 11725 ins_num_consts(3); 11726 11727 format %{ "CALL,runtime" %} 11728 ins_encode( enc_java_to_runtime_call(meth) ); 11729 ins_pipe(pipe_class_call); 11730 %} 11731 11732 // Call Leaf 11733 11734 // Used by postalloc expand of CallLeafDirect_Ex (mtctr). 11735 instruct CallLeafDirect_mtctr(iRegLdst dst, iRegLsrc src) %{ 11736 effect(DEF dst, USE src); 11737 11738 ins_num_consts(1); 11739 11740 format %{ "MTCTR $src" %} 11741 size(4); 11742 ins_encode( enc_leaf_call_mtctr(src) ); 11743 ins_pipe(pipe_class_default); 11744 %} 11745 11746 // Used by postalloc expand of CallLeafDirect_Ex (actual call). 11747 instruct CallLeafDirect(method meth) %{ 11748 match(CallLeaf); // To get the data all the data fields we need ... 11749 effect(USE meth); 11750 predicate(false); // but never match. 11751 11752 format %{ "BCTRL \t// leaf call $meth ==> " %} 11753 size(4); 11754 ins_encode %{ 11755 // TODO: PPC port $archOpcode(ppc64Opcode_bctrl); 11756 __ bctrl(); 11757 %} 11758 ins_pipe(pipe_class_call); 11759 %} 11760 11761 // postalloc expand of CallLeafDirect. 11762 // Load adress to call from TOC, then bl to it. 11763 instruct CallLeafDirect_Ex(method meth) %{ 11764 match(CallLeaf); 11765 effect(USE meth); 11766 ins_cost(CALL_COST); 11767 11768 // Postalloc_expand_java_to_runtime_call needs up to 3 constants: call target, 11769 // env for callee, C-toc. 11770 ins_num_consts(3); 11771 11772 format %{ "CALL,runtime leaf $meth \t// postalloc expanded" %} 11773 postalloc_expand( postalloc_expand_java_to_runtime_call(meth, constanttablebase) ); 11774 %} 11775 11776 // Call runtime without safepoint - same as CallLeaf. 11777 // postalloc expand of CallLeafNoFPDirect. 11778 // Load adress to call from TOC, then bl to it. 11779 instruct CallLeafNoFPDirect_Ex(method meth) %{ 11780 match(CallLeafNoFP); 11781 effect(USE meth); 11782 ins_cost(CALL_COST); 11783 11784 // Enc_java_to_runtime_call needs up to 3 constants: call target, 11785 // env for callee, C-toc. 11786 ins_num_consts(3); 11787 11788 format %{ "CALL,runtime leaf nofp $meth \t// postalloc expanded" %} 11789 postalloc_expand( postalloc_expand_java_to_runtime_call(meth, constanttablebase) ); 11790 %} 11791 11792 // Tail Call; Jump from runtime stub to Java code. 11793 // Also known as an 'interprocedural jump'. 11794 // Target of jump will eventually return to caller. 11795 // TailJump below removes the return address. 11796 instruct TailCalljmpInd(iRegPdstNoScratch jump_target, inline_cache_regP method_oop) %{ 11797 match(TailCall jump_target method_oop); 11798 ins_cost(CALL_COST); 11799 11800 format %{ "MTCTR $jump_target \t// $method_oop holds method oop\n\t" 11801 "BCTR \t// tail call" %} 11802 size(8); 11803 ins_encode %{ 11804 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 11805 __ mtctr($jump_target$$Register); 11806 __ bctr(); 11807 %} 11808 ins_pipe(pipe_class_call); 11809 %} 11810 11811 // Return Instruction 11812 instruct Ret() %{ 11813 match(Return); 11814 format %{ "BLR \t// branch to link register" %} 11815 size(4); 11816 ins_encode %{ 11817 // TODO: PPC port $archOpcode(ppc64Opcode_blr); 11818 // LR is restored in MachEpilogNode. Just do the RET here. 11819 __ blr(); 11820 %} 11821 ins_pipe(pipe_class_default); 11822 %} 11823 11824 // Tail Jump; remove the return address; jump to target. 11825 // TailCall above leaves the return address around. 11826 // TailJump is used in only one place, the rethrow_Java stub (fancy_jump=2). 11827 // ex_oop (Exception Oop) is needed in %o0 at the jump. As there would be a 11828 // "restore" before this instruction (in Epilogue), we need to materialize it 11829 // in %i0. 11830 instruct tailjmpInd(iRegPdstNoScratch jump_target, rarg1RegP ex_oop) %{ 11831 match(TailJump jump_target ex_oop); 11832 ins_cost(CALL_COST); 11833 11834 format %{ "LD R4_ARG2 = LR\n\t" 11835 "MTCTR $jump_target\n\t" 11836 "BCTR \t// TailJump, exception oop: $ex_oop" %} 11837 size(12); 11838 ins_encode %{ 11839 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 11840 __ ld(R4_ARG2/* issuing pc */, _abi(lr), R1_SP); 11841 __ mtctr($jump_target$$Register); 11842 __ bctr(); 11843 %} 11844 ins_pipe(pipe_class_call); 11845 %} 11846 11847 // Create exception oop: created by stack-crawling runtime code. 11848 // Created exception is now available to this handler, and is setup 11849 // just prior to jumping to this handler. No code emitted. 11850 instruct CreateException(rarg1RegP ex_oop) %{ 11851 match(Set ex_oop (CreateEx)); 11852 ins_cost(0); 11853 11854 format %{ " -- \t// exception oop; no code emitted" %} 11855 size(0); 11856 ins_encode( /*empty*/ ); 11857 ins_pipe(pipe_class_default); 11858 %} 11859 11860 // Rethrow exception: The exception oop will come in the first 11861 // argument position. Then JUMP (not call) to the rethrow stub code. 11862 instruct RethrowException() %{ 11863 match(Rethrow); 11864 ins_cost(CALL_COST); 11865 11866 format %{ "Jmp rethrow_stub" %} 11867 ins_encode %{ 11868 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 11869 cbuf.set_insts_mark(); 11870 __ b64_patchable((address)OptoRuntime::rethrow_stub(), relocInfo::runtime_call_type); 11871 %} 11872 ins_pipe(pipe_class_call); 11873 %} 11874 11875 // Die now. 11876 instruct ShouldNotReachHere() %{ 11877 match(Halt); 11878 ins_cost(CALL_COST); 11879 11880 format %{ "ShouldNotReachHere" %} 11881 size(4); 11882 ins_encode %{ 11883 // TODO: PPC port $archOpcode(ppc64Opcode_tdi); 11884 __ trap_should_not_reach_here(); 11885 %} 11886 ins_pipe(pipe_class_default); 11887 %} 11888 11889 // This name is KNOWN by the ADLC and cannot be changed. The ADLC 11890 // forces a 'TypeRawPtr::BOTTOM' output type for this guy. 11891 // Get a DEF on threadRegP, no costs, no encoding, use 11892 // 'ins_should_rematerialize(true)' to avoid spilling. 11893 instruct tlsLoadP(threadRegP dst) %{ 11894 match(Set dst (ThreadLocal)); 11895 ins_cost(0); 11896 11897 ins_should_rematerialize(true); 11898 11899 format %{ " -- \t// $dst=Thread::current(), empty" %} 11900 size(0); 11901 ins_encode( /*empty*/ ); 11902 ins_pipe(pipe_class_empty); 11903 %} 11904 11905 //---Some PPC specific nodes--------------------------------------------------- 11906 11907 // Stop a group. 11908 instruct endGroup() %{ 11909 ins_cost(0); 11910 11911 ins_is_nop(true); 11912 11913 format %{ "End Bundle (ori r1, r1, 0)" %} 11914 size(4); 11915 ins_encode %{ 11916 // TODO: PPC port $archOpcode(ppc64Opcode_endgroup); 11917 __ endgroup(); 11918 %} 11919 ins_pipe(pipe_class_default); 11920 %} 11921 11922 // Nop instructions 11923 11924 instruct fxNop() %{ 11925 ins_cost(0); 11926 11927 ins_is_nop(true); 11928 11929 format %{ "fxNop" %} 11930 size(4); 11931 ins_encode %{ 11932 // TODO: PPC port $archOpcode(ppc64Opcode_fmr); 11933 __ nop(); 11934 %} 11935 ins_pipe(pipe_class_default); 11936 %} 11937 11938 instruct fpNop0() %{ 11939 ins_cost(0); 11940 11941 ins_is_nop(true); 11942 11943 format %{ "fpNop0" %} 11944 size(4); 11945 ins_encode %{ 11946 // TODO: PPC port $archOpcode(ppc64Opcode_fmr); 11947 __ fpnop0(); 11948 %} 11949 ins_pipe(pipe_class_default); 11950 %} 11951 11952 instruct fpNop1() %{ 11953 ins_cost(0); 11954 11955 ins_is_nop(true); 11956 11957 format %{ "fpNop1" %} 11958 size(4); 11959 ins_encode %{ 11960 // TODO: PPC port $archOpcode(ppc64Opcode_fmr); 11961 __ fpnop1(); 11962 %} 11963 ins_pipe(pipe_class_default); 11964 %} 11965 11966 instruct brNop0() %{ 11967 ins_cost(0); 11968 size(4); 11969 format %{ "brNop0" %} 11970 ins_encode %{ 11971 // TODO: PPC port $archOpcode(ppc64Opcode_mcrf); 11972 __ brnop0(); 11973 %} 11974 ins_is_nop(true); 11975 ins_pipe(pipe_class_default); 11976 %} 11977 11978 instruct brNop1() %{ 11979 ins_cost(0); 11980 11981 ins_is_nop(true); 11982 11983 format %{ "brNop1" %} 11984 size(4); 11985 ins_encode %{ 11986 // TODO: PPC port $archOpcode(ppc64Opcode_mcrf); 11987 __ brnop1(); 11988 %} 11989 ins_pipe(pipe_class_default); 11990 %} 11991 11992 instruct brNop2() %{ 11993 ins_cost(0); 11994 11995 ins_is_nop(true); 11996 11997 format %{ "brNop2" %} 11998 size(4); 11999 ins_encode %{ 12000 // TODO: PPC port $archOpcode(ppc64Opcode_mcrf); 12001 __ brnop2(); 12002 %} 12003 ins_pipe(pipe_class_default); 12004 %} 12005 12006 //----------PEEPHOLE RULES----------------------------------------------------- 12007 // These must follow all instruction definitions as they use the names 12008 // defined in the instructions definitions. 12009 // 12010 // peepmatch ( root_instr_name [preceeding_instruction]* ); 12011 // 12012 // peepconstraint %{ 12013 // (instruction_number.operand_name relational_op instruction_number.operand_name 12014 // [, ...] ); 12015 // // instruction numbers are zero-based using left to right order in peepmatch 12016 // 12017 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) ); 12018 // // provide an instruction_number.operand_name for each operand that appears 12019 // // in the replacement instruction's match rule 12020 // 12021 // ---------VM FLAGS--------------------------------------------------------- 12022 // 12023 // All peephole optimizations can be turned off using -XX:-OptoPeephole 12024 // 12025 // Each peephole rule is given an identifying number starting with zero and 12026 // increasing by one in the order seen by the parser. An individual peephole 12027 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=# 12028 // on the command-line. 12029 // 12030 // ---------CURRENT LIMITATIONS---------------------------------------------- 12031 // 12032 // Only match adjacent instructions in same basic block 12033 // Only equality constraints 12034 // Only constraints between operands, not (0.dest_reg == EAX_enc) 12035 // Only one replacement instruction 12036 // 12037 // ---------EXAMPLE---------------------------------------------------------- 12038 // 12039 // // pertinent parts of existing instructions in architecture description 12040 // instruct movI(eRegI dst, eRegI src) %{ 12041 // match(Set dst (CopyI src)); 12042 // %} 12043 // 12044 // instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{ 12045 // match(Set dst (AddI dst src)); 12046 // effect(KILL cr); 12047 // %} 12048 // 12049 // // Change (inc mov) to lea 12050 // peephole %{ 12051 // // increment preceeded by register-register move 12052 // peepmatch ( incI_eReg movI ); 12053 // // require that the destination register of the increment 12054 // // match the destination register of the move 12055 // peepconstraint ( 0.dst == 1.dst ); 12056 // // construct a replacement instruction that sets 12057 // // the destination to ( move's source register + one ) 12058 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) ); 12059 // %} 12060 // 12061 // Implementation no longer uses movX instructions since 12062 // machine-independent system no longer uses CopyX nodes. 12063 // 12064 // peephole %{ 12065 // peepmatch ( incI_eReg movI ); 12066 // peepconstraint ( 0.dst == 1.dst ); 12067 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) ); 12068 // %} 12069 // 12070 // peephole %{ 12071 // peepmatch ( decI_eReg movI ); 12072 // peepconstraint ( 0.dst == 1.dst ); 12073 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) ); 12074 // %} 12075 // 12076 // peephole %{ 12077 // peepmatch ( addI_eReg_imm movI ); 12078 // peepconstraint ( 0.dst == 1.dst ); 12079 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) ); 12080 // %} 12081 // 12082 // peephole %{ 12083 // peepmatch ( addP_eReg_imm movP ); 12084 // peepconstraint ( 0.dst == 1.dst ); 12085 // peepreplace ( leaP_eReg_immI( 0.dst 1.src 0.src ) ); 12086 // %} 12087 12088 // // Change load of spilled value to only a spill 12089 // instruct storeI(memory mem, eRegI src) %{ 12090 // match(Set mem (StoreI mem src)); 12091 // %} 12092 // 12093 // instruct loadI(eRegI dst, memory mem) %{ 12094 // match(Set dst (LoadI mem)); 12095 // %} 12096 // 12097 peephole %{ 12098 peepmatch ( loadI storeI ); 12099 peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem ); 12100 peepreplace ( storeI( 1.mem 1.mem 1.src ) ); 12101 %} 12102 12103 peephole %{ 12104 peepmatch ( loadL storeL ); 12105 peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem ); 12106 peepreplace ( storeL( 1.mem 1.mem 1.src ) ); 12107 %} 12108 12109 peephole %{ 12110 peepmatch ( loadP storeP ); 12111 peepconstraint ( 1.src == 0.dst, 1.dst == 0.mem ); 12112 peepreplace ( storeP( 1.dst 1.dst 1.src ) ); 12113 %} 12114 12115 //----------SMARTSPILL RULES--------------------------------------------------- 12116 // These must follow all instruction definitions as they use the names 12117 // defined in the instructions definitions.