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src/cpu/aarch32/vm/assembler_aarch32.hpp
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rev 8069 : 8164652: aarch32: C1 port
@@ -872,14 +872,14 @@
//NOTE: arithmetic immediate instructions are defined below to allow dispatch.
#undef INSN
protected:
// Mov data to destination register in the shortest number of instructions
// possible.
- void mov_immediate(Register dst, u_int32_t imm32, Condition cond, bool s);
+ void mov_immediate(Register dst, uint32_t imm32, Condition cond, bool s);
// Mov data to destination register but always emit enough instructions that would
// permit any 32-bit constant to be loaded. (Allow for rewriting later).
- void mov_immediate32(Register dst, u_int32_t imm32, Condition cond, bool s);
+ void mov_immediate32(Register dst, uint32_t imm32, Condition cond, bool s);
void add_sub_imm(int decode, Register Rd, Register Rn, int imm,
Condition cond, bool s);
public:
@@ -1208,11 +1208,11 @@
if(encodeable(op, dest)) { /* Plan A */ \
long offset = dest - pc(); \
NAME(Rt, Address(r15_pc, offset), cond); \
} else if(isload){ /* Plan B */ \
/* TODO check we don't have to relocate this*/ \
- mov_immediate(Rt, (u_int32_t)dest, cond, false); \
+ mov_immediate(Rt, (uint32_t)dest, cond, false); \
NAME(Rt, Address(Rt, 0), cond); \
} else { /* There is no plan C */ \
ShouldNotReachHere(); \
} \
} \
@@ -1594,11 +1594,11 @@
}
void dsb(enum barrier option) {
sync_instr(0b0100, option);
}
void dmb(enum barrier option) {
- sync_instr(0b0100, option);
+ sync_instr(0b0101, option);
}
void bkpt();
void isb() {
sync_instr(0b0110, SY);
}
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