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25 // This file is a derivative work resulting from (and including) modifications
26 // made by Azul Systems, Inc. The dates of such changes are 2013-2016.
27 // Copyright 2013-2016 Azul Systems, Inc. All Rights Reserved.
28 //
29 // Please contact Azul Systems, 385 Moffett Park Drive, Suite 115, Sunnyvale,
30 // CA 94089 USA or visit www.azul.com if you need additional information or
31 // have any questions.
32
33 #ifndef CPU_AARCH32_VM_C1_DEFS_AARCH32_HPP
34 #define CPU_AARCH32_VM_C1_DEFS_AARCH32_HPP
35
36 // Native word offsets from memory address (little endian format)
37 enum {
38 pd_lo_word_offset_in_bytes = 0,
39 pd_hi_word_offset_in_bytes = BytesPerWord
40 };
41
42 // TODO: We should understand what values are correct for the following 3 flags
43 // relevant to floating point operations:
44 // - UseSSE
45 // Highest supported SSE instruction set on x86/x64. I believe we should
46 // set it to 0 in VM_Version::initialize(), like other non-x86 ports do.
47 // - RoundFPResults
48 // Indicates whether rounding is needed for floating point results
49 // - pd_strict_fp_requires_explicit_rounding
50 // The same as above but for the strictfp mode
51
52 // Explicit rounding operations are not required to implement the strictfp mode
53 enum {
54 pd_strict_fp_requires_explicit_rounding = false
55 };
56
57 // Registers
58 enum {
59 // Number of registers used during code emission
60 pd_nof_cpu_regs_frame_map = RegisterImpl::number_of_registers,
61 pd_nof_fpu_regs_frame_map = FloatRegisterImpl::number_of_registers,
62
63 // Number of registers killed by calls
64 pd_nof_caller_save_cpu_regs_frame_map = 8,
65 pd_nof_caller_save_fpu_regs_frame_map = 32,
66
67 // The following two constants need to be defined since they are referenced
68 // from c1_FrameMap.hpp, but actually they are never used, so can be set to
69 // arbitrary values.
70 pd_nof_cpu_regs_reg_alloc = -1,
71 pd_nof_fpu_regs_reg_alloc = -1,
72
73 // All the constants below are used by linear scan register allocator only.
74 // Number of registers visible to register allocator
75 pd_nof_cpu_regs_linearscan = pd_nof_cpu_regs_frame_map,
76 pd_nof_fpu_regs_linearscan = pd_nof_fpu_regs_frame_map,
77 pd_nof_xmm_regs_linearscan = 0,
78
79 // Register allocator specific register numbers corresponding to first/last
80 // CPU/FPU registers available for allocation
81 pd_first_cpu_reg = 0,
82 pd_last_cpu_reg = 7,
83 pd_first_fpu_reg = pd_nof_cpu_regs_frame_map,
84 pd_last_fpu_reg = pd_first_fpu_reg + 31,
85
86 // Register allocator specific register numbers corresponding to first/last
87 // CPU/FPU callee-saved registers. These constants are used in
88 // LinearScan::is_caller_save() only.
89 pd_first_callee_saved_cpu_reg = 4,
90 pd_last_callee_saved_cpu_reg = 11,
91 pd_first_callee_saved_fpu_reg = pd_first_fpu_reg + 16,
92 pd_last_callee_saved_fpu_reg = pd_first_fpu_reg + 31
93 };
94
95 // This flag must be in sync with how the floating point registers are stored
96 // on the stack by RegisterSaver::save_live_registers() method
97 // (sharedRuntime_aarch32.cpp) and save_live_registers() function
98 // (c1_Runtime1_aarch32.cpp). On AArch32 the floating point registers keep
99 // floats and doubles in their native form. No float to double conversion
100 // happens when the registers are stored on the stack. This is opposite to
101 // what happens on x86, where the FPU stack registers are 80 bits wide,
102 // and storing them in either 4 byte or 8 byte stack slot is a conversion
103 // operation.
104 enum {
105 pd_float_saved_as_double = false
106 };
107
108 #endif // CPU_AARCH32_VM_C1_DEFS_AARCH32_HPP