1 /* 2 * Copyright (c) 2003, 2012, Oracle and/or its affiliates. All rights reserved. 3 * Copyright (c) 2014, Red Hat Inc. All rights reserved. 4 * Copyright (c) 2015, Linaro Ltd. All rights reserved. 5 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 6 * 7 * This code is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License version 2 only, as 9 * published by the Free Software Foundation. 10 * 11 * This code is distributed in the hope that it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 14 * version 2 for more details (a copy is included in the LICENSE file that 15 * accompanied this code). 16 * 17 * You should have received a copy of the GNU General Public License version 18 * 2 along with this work; if not, write to the Free Software Foundation, 19 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 20 * 21 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 22 * or visit www.oracle.com if you need additional information or have any 23 * questions. 24 * 25 */ 26 27 #include "precompiled.hpp" 28 #include "asm/macroAssembler.hpp" 29 #include "asm/macroAssembler.inline.hpp" 30 #include "code/debugInfoRec.hpp" 31 #include "code/icBuffer.hpp" 32 #include "code/vtableStubs.hpp" 33 #include "interp_masm_aarch32.hpp" 34 #include "interpreter/interpreter.hpp" 35 #include "oops/compiledICHolder.hpp" 36 #include "prims/jvmtiRedefineClassesTrace.hpp" 37 #include "runtime/sharedRuntime.hpp" 38 #include "runtime/vframeArray.hpp" 39 #include "vmreg_aarch32.inline.hpp" 40 #ifdef COMPILER1 41 #include "c1/c1_Runtime1.hpp" 42 #endif 43 #ifdef COMPILER2 44 #include "adfiles/ad_aarch32.hpp" 45 #include "opto/runtime.hpp" 46 #endif 47 48 49 #define __ masm-> 50 51 const int StackAlignmentInSlots = StackAlignmentInBytes / VMRegImpl::stack_slot_size; 52 53 class SimpleRuntimeFrame { 54 55 public: 56 57 // Most of the runtime stubs have this simple frame layout. 58 // This class exists to make the layout shared in one place. 59 // Offsets are for compiler stack slots, which are jints. 60 enum layout { 61 // The frame sender code expects that rbp will be in the "natural" place and 62 // will override any oopMap setting for it. We must therefore force the layout 63 // so that it agrees with the frame sender code. 64 // we don't expect any arg reg save area so aarch32 asserts that 65 // frame::arg_reg_save_area_bytes == 0 66 rbp_off = 0, 67 rbp_off2, 68 return_off, return_off2, 69 framesize 70 }; 71 }; 72 73 // FIXME -- this is used by C1 74 class RegisterSaver { 75 public: 76 static OopMap* save_live_registers(MacroAssembler* masm, int additional_frame_words, int* total_frame_words); 77 static void restore_live_registers(MacroAssembler* masm); 78 79 // Capture info about frame layout 80 enum layout { 81 fpu_state_off = 0, 82 fpu_state_end = fpu_state_off+FPUStateSizeInWords-1, 83 // The frame sender code expects that rfp will be in 84 // the "natural" place and will override any oopMap 85 // setting for it. We must therefore force the layout 86 // so that it agrees with the frame sender code. 87 // 88 // FIXME there are extra saved register (from `push_CPU_state`) note that r11 == rfp 89 r0_off, 90 r1_off, 91 r2_off, 92 r3_off, 93 r4_off, 94 r5_off, 95 r6_off, 96 r7_off, 97 r8_off, 98 r9_off, rscratch1_off = r9_off, 99 r10_off, rmethod_off = r10_off, 100 r11_off, 101 r12_off, 102 reg_save_pad, // align area to 8-bytes to simplify stack alignment to 8 103 rfp_off, 104 return_off, 105 reg_save_size, 106 }; 107 108 109 // Offsets into the register save area 110 // Used by deoptimization when it is managing result register 111 // values on its own 112 113 static int offset_in_bytes(int offset) { return offset * wordSize; } 114 115 // During deoptimization only the result registers need to be restored, 116 // all the other values have already been extracted. 117 static void restore_result_registers(MacroAssembler* masm); 118 119 }; 120 121 OopMap* RegisterSaver::save_live_registers(MacroAssembler* masm, int additional_frame_words, int* total_frame_words) { 122 int frame_size_in_bytes = additional_frame_words*wordSize + reg_save_size*BytesPerInt; 123 int frame_size_in_slots = frame_size_in_bytes / BytesPerInt; 124 int additional_frame_slots = additional_frame_words*wordSize / BytesPerInt; 125 *total_frame_words = frame_size_in_bytes / wordSize;; 126 127 __ enter(); 128 __ push_CPU_state(); 129 130 // Set an oopmap for the call site. This oopmap will map all 131 // oop-registers and debug-info registers as callee-saved. This 132 // will allow deoptimization at this safepoint to find all possible 133 // debug-info recordings, as well as let GC find all oops. 134 135 OopMapSet *oop_maps = new OopMapSet(); 136 OopMap* oop_map = new OopMap(frame_size_in_slots, 0); 137 138 oop_map->set_callee_saved(VMRegImpl::stack2reg(r0_off + additional_frame_slots), r0->as_VMReg()); 139 oop_map->set_callee_saved(VMRegImpl::stack2reg(r1_off + additional_frame_slots), r1->as_VMReg()); 140 oop_map->set_callee_saved(VMRegImpl::stack2reg(r2_off + additional_frame_slots), r2->as_VMReg()); 141 oop_map->set_callee_saved(VMRegImpl::stack2reg(r3_off + additional_frame_slots), r3->as_VMReg()); 142 oop_map->set_callee_saved(VMRegImpl::stack2reg(r4_off + additional_frame_slots), r4->as_VMReg()); 143 oop_map->set_callee_saved(VMRegImpl::stack2reg(r5_off + additional_frame_slots), r5->as_VMReg()); 144 oop_map->set_callee_saved(VMRegImpl::stack2reg(r6_off + additional_frame_slots), r6->as_VMReg()); 145 oop_map->set_callee_saved(VMRegImpl::stack2reg(r7_off + additional_frame_slots), r7->as_VMReg()); 146 oop_map->set_callee_saved(VMRegImpl::stack2reg(r8_off + additional_frame_slots), r8->as_VMReg()); 147 oop_map->set_callee_saved(VMRegImpl::stack2reg(r10_off + additional_frame_slots), r10->as_VMReg()); 148 // r11 saved in frame header as rfp, not map it here 149 // r11 & r14 have special meaning (can't hold oop), so not map them 150 151 for (int i = 0; i < 31; ++i) { 152 oop_map->set_callee_saved(VMRegImpl::stack2reg(fpu_state_off + i + additional_frame_slots), 153 as_FloatRegister(i)->as_VMReg()); 154 } 155 156 return oop_map; 157 } 158 159 void RegisterSaver::restore_live_registers(MacroAssembler* masm) { 160 __ pop_CPU_state(); 161 __ leave(); 162 } 163 164 void RegisterSaver::restore_result_registers(MacroAssembler* masm) { 165 166 // Just restore result register. Only used by deoptimization. By 167 // now any callee save register that needs to be restored to a c2 168 // caller of the deoptee has been extracted into the vframeArray 169 // and will be stuffed into the c2i adapter we create for later 170 // restoration so only result registers need to be restored here. 171 172 173 174 // Restore fp result register 175 __ vldr_f64(d0, Address(sp, offset_in_bytes(fpu_state_off))); 176 // Restore integer result register 177 __ ldr(r0, Address(sp, offset_in_bytes(r0_off))); 178 __ ldr(r1, Address(sp, offset_in_bytes(r1_off))); 179 180 // Pop all of the register save are off the stack 181 __ add(sp, sp, reg_save_size * wordSize); 182 } 183 184 // Is vector's size (in bytes) bigger than a size saved by default? 185 // 16 bytes XMM registers are saved by default using fxsave/fxrstor instructions. 186 bool SharedRuntime::is_wide_vector(int size) { 187 return size > 16; 188 } 189 190 // This functions returns offset from fp to java arguments on stack. 191 // 192 // The java_calling_convention describes stack locations as ideal slots on 193 // a frame with no abi restrictions. Since we must observe abi restrictions 194 // (like the placement of the register window) the slots must be biased by 195 // the following value. 196 static int reg2offset_in(VMReg r) { 197 // After stack frame created, fp points to 1 slot after previous sp value. 198 return (r->reg2stack() + 1) * VMRegImpl::stack_slot_size; 199 } 200 201 static int reg2offset_out(VMReg r) { 202 return (r->reg2stack() + SharedRuntime::out_preserve_stack_slots()) * VMRegImpl::stack_slot_size; 203 } 204 205 // --------------------------------------------------------------------------- 206 // Read the array of BasicTypes from a signature, and compute where the 207 // arguments should go. Values in the VMRegPair regs array refer to 4-byte 208 // quantities. Values less than VMRegImpl::stack0 are registers, those above 209 // refer to 4-byte stack slots. All stack slots are based off of the stack pointer 210 // as framesizes are fixed. 211 // VMRegImpl::stack0 refers to the first slot 0(sp). 212 // and VMRegImpl::stack0+1 refers to the memory word 4-byes higher. Register 213 // up to RegisterImpl::number_of_registers) are the 64-bit 214 // integer registers. 215 216 // Note: the INPUTS in sig_bt are in units of Java argument words, 217 // which are 64-bit. The OUTPUTS are in 32-bit units. 218 219 // The Java calling convention is a "shifted" version of the C ABI. 220 // By skipping the first C ABI register we can call non-static jni 221 // methods with small numbers of arguments without having to shuffle 222 // the arguments at all. Since we control the java ABI we ought to at 223 // least get some advantage out of it. 224 225 int SharedRuntime::java_calling_convention(const BasicType *sig_bt, 226 VMRegPair *regs, 227 int total_args_passed, 228 int is_outgoing) { 229 230 // Create the mapping between argument positions and 231 // registers. 232 static const Register INT_ArgReg[Argument::n_int_register_parameters_j] = { 233 j_rarg0, j_rarg1, j_rarg2, j_rarg3 234 }; 235 const int FP_ArgReg_N = 16; 236 static const FloatRegister FP_ArgReg[] = { 237 f0, f1, f2, f3, 238 f4, f5, f6, f7, 239 f8, f9, f10, f11, 240 f12, f13, f14, f15, 241 }; 242 243 uint int_args = 0; 244 uint fp_args = 0; 245 uint stk_args = 0; 246 247 for (int i = 0; i < total_args_passed; i++) { 248 switch (sig_bt[i]) { 249 case T_BOOLEAN: 250 case T_CHAR: 251 case T_BYTE: 252 case T_SHORT: 253 case T_INT: 254 case T_OBJECT: 255 case T_ARRAY: 256 case T_ADDRESS: 257 if (int_args < Argument::n_int_register_parameters_j) { 258 regs[i].set1(INT_ArgReg[int_args++]->as_VMReg()); 259 } else { 260 regs[i].set1(VMRegImpl::stack2reg(stk_args)); 261 stk_args += 1; 262 } 263 break; 264 case T_VOID: 265 // halves of T_LONG or T_DOUBLE 266 assert(i != 0 && (sig_bt[i - 1] == T_LONG || sig_bt[i - 1] == T_DOUBLE), "expecting half"); 267 regs[i].set_bad(); 268 break; 269 case T_LONG: 270 assert(sig_bt[i + 1] == T_VOID, "expecting half"); 271 if (int_args + 1 < Argument::n_int_register_parameters_j) { 272 regs[i].set_pair(INT_ArgReg[int_args + 1]->as_VMReg(), INT_ArgReg[int_args]->as_VMReg()); 273 int_args += 2; 274 } else { 275 regs[i].set2(VMRegImpl::stack2reg(stk_args)); 276 stk_args += 2; 277 } 278 break; 279 case T_FLOAT: 280 if (fp_args < FP_ArgReg_N) { 281 regs[i].set1(FP_ArgReg[fp_args++]->as_VMReg()); 282 } else { 283 regs[i].set1(VMRegImpl::stack2reg(stk_args)); 284 stk_args += 1; 285 } 286 break; 287 case T_DOUBLE: 288 assert(sig_bt[i + 1] == T_VOID, "expecting half"); 289 fp_args = round_to(fp_args, 2); 290 if (fp_args < FP_ArgReg_N) { 291 regs[i].set2(FP_ArgReg[fp_args]->as_VMReg()); 292 fp_args += 2; 293 } else { 294 regs[i].set2(VMRegImpl::stack2reg(stk_args)); 295 stk_args += 2; 296 } 297 break; 298 default: 299 ShouldNotReachHere(); 300 break; 301 } 302 } 303 304 return round_to(stk_args, StackAlignmentInBytes/wordSize); 305 } 306 307 // Patch the callers callsite with entry to compiled code if it exists. 308 static void patch_callers_callsite(MacroAssembler *masm) { 309 Label L; 310 __ ldr(rscratch1, Address(rmethod, in_bytes(Method::code_offset()))); 311 __ cbz(rscratch1, L); 312 313 __ enter(); 314 __ push_CPU_state(); 315 316 // VM needs caller's callsite 317 // VM needs target method 318 // This needs to be a long call since we will relocate this adapter to 319 // the codeBuffer and it may not reach 320 321 #ifndef PRODUCT 322 assert(frame::arg_reg_save_area_bytes == 0, "not expecting frame reg save area"); 323 #endif 324 325 __ mov(c_rarg0, rmethod); 326 __ mov(c_rarg1, lr); 327 __ lea(rscratch1, RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::fixup_callers_callsite))); 328 __ bl(rscratch1); 329 __ maybe_isb(); 330 331 __ pop_CPU_state(); 332 // restore sp 333 __ leave(); 334 __ bind(L); 335 } 336 337 static void gen_c2i_adapter(MacroAssembler *masm, 338 int total_args_passed, 339 int comp_args_on_stack, 340 const BasicType *sig_bt, 341 const VMRegPair *regs, 342 Label& skip_fixup) { 343 // Before we get into the guts of the C2I adapter, see if we should be here 344 // at all. We've come from compiled code and are attempting to jump to the 345 // interpreter, which means the caller made a static call to get here 346 // (vcalls always get a compiled target if there is one). Check for a 347 // compiled target. If there is one, we need to patch the caller's call. 348 patch_callers_callsite(masm); 349 350 __ bind(skip_fixup); 351 352 // Since all args are passed on the stack, total_args_passed * 353 // Interpreter::stackElementSize is the space we need. 354 355 const int extraspace = total_args_passed * Interpreter::stackElementSize; 356 const Register compArgPos = lr; 357 int ld_shift = 0; 358 359 __ str(compArgPos, Address(sp, -(extraspace + wordSize))); 360 __ mov(compArgPos, sp); 361 362 // Now write the args into the outgoing interpreter space 363 for (int i = 0; i < total_args_passed; i++) { 364 365 if (sig_bt[i] == T_VOID) { 366 assert(i > 0 && (sig_bt[i-1] == T_LONG || sig_bt[i-1] == T_DOUBLE), "missing half"); 367 continue; 368 } 369 370 // next stack slot offset 371 const int next_off = -Interpreter::stackElementSize; 372 373 VMReg r_1 = regs[i].first(); 374 VMReg r_2 = regs[i].second(); 375 if (!r_1->is_valid()) { 376 assert(!r_2->is_valid(), ""); 377 continue; 378 } 379 380 if (r_2->is_valid()) { 381 assert(i + 1 < total_args_passed && sig_bt[i + 1] == T_VOID, "going to overrwrite reg_2 value"); 382 } 383 384 if (r_1->is_stack()) { 385 // memory to memory use rscratch1 386 int ld_off = r_1->reg2stack() * VMRegImpl::stack_slot_size - ld_shift; 387 if (!r_2->is_valid()) { 388 __ ldr(rscratch1, Address(compArgPos, ld_off)); 389 __ str(rscratch1, Address(sp, next_off, Address::pre)); 390 } else { 391 int tmp_off = ld_off; 392 // ldrd accepts only imm8 393 if(abs(ld_off) > (255 << 2)) { 394 if(__ is_valid_for_imm12(ld_off)) { 395 __ add(compArgPos, compArgPos, ld_off); 396 } else { 397 // add operates encoded imm12, NOT plain 398 __ mov(rscratch1, ld_off); 399 __ add(compArgPos, compArgPos, rscratch1); 400 } 401 tmp_off = 0; 402 ld_shift += ld_off; 403 } 404 __ ldrd(rscratch1, rscratch2, Address(compArgPos, tmp_off)); 405 __ strd(rscratch1, rscratch2, Address(sp, 2* next_off, Address::pre)); 406 } 407 } else if (r_1->is_Register()) { 408 Register r = r_1->as_Register(); 409 assert(r != compArgPos, "compArgPos was modified"); 410 if (!r_2->is_valid()) { 411 __ str(r, Address(sp, next_off, Address::pre)); 412 } else { 413 assert(r_2->as_Register() != compArgPos, "compArgPos was modified"); 414 __ strd(r, r_2->as_Register(), Address(sp, 2 * next_off, Address::pre)); 415 } 416 } else { 417 assert(r_1->is_FloatRegister(), ""); 418 if (!r_2->is_valid()) { 419 // Can't do pre or post addressing for vldr, vstr 420 __ add(sp, sp, next_off); 421 __ vstr_f32(r_1->as_FloatRegister(), Address(sp)); 422 } else { 423 // TODO assert(r_2->is_FloatRegister() && r_2->as_FloatRegister() == r_1->as_FloatRegister() + 1, ""); 424 // Can't do pre or post addressing for vldr, vstr 425 __ add(sp, sp, 2 * next_off); 426 __ vstr_f64(r_1->as_FloatRegister(), Address(sp)); 427 } 428 } 429 } 430 431 // hope, sp is returned to desired value 432 __ ldr(compArgPos, Address(sp, -wordSize)); 433 434 // set sender sp 435 if(__ is_valid_for_imm12(extraspace)) { 436 __ add(r4, sp, extraspace); 437 } else { 438 __ mov(rscratch1, extraspace); 439 __ add(r4, sp, rscratch1); 440 } 441 442 __ ldr(rscratch1, Address(rmethod, in_bytes(Method::interpreter_entry_offset()))); 443 __ b(rscratch1); 444 } 445 446 static void range_check(MacroAssembler* masm, Register pc_reg, Register temp_reg, 447 address code_start, address code_end, 448 Label& L_ok) { 449 Label L_fail; 450 __ lea(temp_reg, ExternalAddress(code_start)); 451 __ cmp(pc_reg, temp_reg); 452 __ b(L_fail, Assembler::LO); 453 __ lea(temp_reg, ExternalAddress(code_end)); 454 __ cmp(pc_reg, temp_reg); 455 __ b(L_ok, Assembler::LO); 456 __ bind(L_fail); 457 } 458 459 static void gen_i2c_adapter(MacroAssembler *masm, 460 int total_args_passed, 461 int comp_args_on_stack, 462 const BasicType *sig_bt, 463 const VMRegPair *regs) { 464 465 // Note: r13 contains the senderSP on entry. We must preserve it since 466 // we may do a i2c -> c2i transition if we lose a race where compiled 467 // code goes non-entrant while we get args ready. 468 469 // In addition we use r13 to locate all the interpreter args because 470 // we must align the stack to 16 bytes. 471 472 // Adapters are frameless. 473 474 // An i2c adapter is frameless because the *caller* frame, which is 475 // interpreted, routinely repairs its own sp (from 476 // interpreter_frame_last_sp), even if a callee has modified the 477 // stack pointer. It also recalculates and aligns sp. 478 479 // A c2i adapter is frameless because the *callee* frame, which is 480 // interpreted, routinely repairs its caller's sp (from sender_sp, 481 // which is set up via the senderSP register). 482 483 // In other words, if *either* the caller or callee is interpreted, we can 484 // get the stack pointer repaired after a call. 485 486 // This is why c2i and i2c adapters cannot be indefinitely composed. 487 // In particular, if a c2i adapter were to somehow call an i2c adapter, 488 // both caller and callee would be compiled methods, and neither would 489 // clean up the stack pointer changes performed by the two adapters. 490 // If this happens, control eventually transfers back to the compiled 491 // caller, but with an uncorrected stack, causing delayed havoc. 492 493 if (VerifyAdapterCalls && 494 (Interpreter::code() != NULL || StubRoutines::code1() != NULL)) { 495 // So, let's test for cascading c2i/i2c adapters right now. 496 // assert(Interpreter::contains($return_addr) || 497 // StubRoutines::contains($return_addr), 498 // "i2c adapter must return to an interpreter frame"); 499 __ block_comment("verify_i2c { "); 500 Label L_ok; 501 if (Interpreter::code() != NULL) 502 range_check(masm, lr, rscratch1, 503 Interpreter::code()->code_start(), Interpreter::code()->code_end(), 504 L_ok); 505 if (StubRoutines::code1() != NULL) 506 range_check(masm, lr, rscratch1, 507 StubRoutines::code1()->code_begin(), StubRoutines::code1()->code_end(), 508 L_ok); 509 if (StubRoutines::code2() != NULL) 510 range_check(masm, lr, rscratch1, 511 StubRoutines::code2()->code_begin(), StubRoutines::code2()->code_end(), 512 L_ok); 513 const char* msg = "i2c adapter must return to an interpreter frame"; 514 __ block_comment(msg); 515 __ stop(msg); 516 __ bind(L_ok); 517 __ block_comment("} verify_i2ce "); 518 } 519 520 const int stack_space = round_to(comp_args_on_stack * VMRegImpl::stack_slot_size, StackAlignmentInBytes); 521 const int ld_high = total_args_passed *Interpreter::stackElementSize; 522 // Point to interpreter value (vs. tag) 523 const int next_off = -Interpreter::stackElementSize; // offset from ld ptr 524 const Register loadCounter = lr; 525 526 // Align sp to StackAlignmentInBytes so compiled frame starts always aligned 527 // This is required by APCS, so all native code depends on it. The compiled 528 // Java code is not required to follow this standard however doing so 529 // simplifies the code because allows to have fixed size for compiled frames 530 __ mov(rscratch2, sp); 531 __ align_stack(); 532 if(total_args_passed) { 533 // put below reserved stack space, imm12 should be enough 534 __ str(loadCounter, Address(sp, -(stack_space + wordSize))); 535 536 if(__ is_valid_for_imm12(ld_high)) { 537 __ add(loadCounter, rscratch2, ld_high); 538 } else { 539 // add operates encoded imm12, we need plain 540 __ mov(rscratch1, ld_high); 541 __ add(loadCounter, rscratch2, rscratch1); 542 } 543 } 544 545 if(comp_args_on_stack) { 546 if(__ is_valid_for_imm12(stack_space)) { 547 __ sub(sp, sp, stack_space); 548 } else { 549 // add operates encoded imm12, we need plain 550 __ mov(rscratch1, stack_space); 551 __ sub(sp, sp, rscratch1); 552 } 553 } 554 555 // +------+ -> r4 556 // | 0 | \ 557 // | 1 | \ 558 // | 2 | - > Load in argument order going down. 559 // | x | / 560 // | N | / 561 // +------+ -> inital sp 562 // | pad | maybe 1 word to align the stack to 8 bytes 563 // | M | \ 564 // | x | \ 565 // | 2 | -> Load in argument order going up. 566 // | 1 | / 567 // | 0 | / 568 // +------+ -> 569 570 571 int sp_offset = 0; 572 573 // Now generate the shuffle code. 574 for (int i = 0; i < total_args_passed; i++) { 575 576 if (sig_bt[i] == T_VOID) { 577 assert(i > 0 && (sig_bt[i-1] == T_LONG || sig_bt[i-1] == T_DOUBLE), "missing half"); 578 continue; 579 } 580 581 // Pick up 0, 1 or 2 words from SP+offset. 582 583 // 584 // 585 // 586 VMReg r_1 = regs[i].first(); 587 VMReg r_2 = regs[i].second(); 588 if (!r_1->is_valid()) { 589 assert(!r_2->is_valid(), ""); 590 continue; 591 } 592 593 if (r_2->is_valid()) { 594 assert(i + 1 < total_args_passed && sig_bt[i + 1] == T_VOID, "going to overrwrite reg_2 value"); 595 } 596 597 if (r_1->is_stack()) { 598 // Convert stack slot to an SP offset 599 int st_off = regs[i].first()->reg2stack()*VMRegImpl::stack_slot_size - sp_offset; 600 601 if (!r_2->is_valid()) { 602 __ ldr(rscratch2, Address(loadCounter, next_off, Address::pre)); 603 __ str(rscratch2, Address(sp, st_off)); 604 } else { 605 int tmp_off = st_off; 606 if(abs(st_off) > (255 << 2)) { 607 //st_off doesn't fit imm8 required by strd 608 609 if(__ is_valid_for_imm12(st_off)) { 610 __ add(sp, sp, st_off); 611 } else { 612 // add operates encoded imm12, NOT plain 613 __ mov(rscratch1, st_off); 614 __ add(sp, sp, rscratch1); 615 } 616 tmp_off = 0; 617 sp_offset += st_off; 618 } 619 620 621 // Interpreter local[n] == MSW, local[n+1] == LSW however locals 622 // are accessed as negative so LSW is at LOW address 623 624 // this can be a misaligned move 625 __ ldrd(rscratch1, rscratch2, Address(loadCounter, 2 * next_off, Address::pre)); 626 __ strd(rscratch1, rscratch2, Address(sp, tmp_off)); 627 } 628 } else if (r_1->is_Register()) { // Register argument 629 Register r = r_1->as_Register(); 630 assert(r != loadCounter, "loadCounter is reloaded"); 631 if (r_2->is_valid()) { 632 assert(r_2->as_Register() != loadCounter, "loadCounter is reloaded"); 633 // this can be a misaligned move 634 // ldrd can handle inconsecutive registers 635 __ ldrd(r, r_2->as_Register(), Address(loadCounter, 2 * next_off, Address::pre)); 636 } else { 637 __ ldr(r, Address(loadCounter, next_off, Address::pre)); 638 } 639 } else { 640 assert(r_1->is_FloatRegister(), ""); 641 if (!r_2->is_valid()) { 642 // Can't do pre or post addressing for vldr, vstr 643 __ add(loadCounter, loadCounter, next_off); 644 __ vldr_f32(r_1->as_FloatRegister(), Address(loadCounter)); 645 } else { 646 // TODO assert(r_2->is_FloatRegister() && r_2->as_FloatRegister() == r_1->as_FloatRegister() + 1, ""); 647 // Can't do pre or post addressing for vldr, vstr 648 __ add(loadCounter, loadCounter, 2 * next_off); 649 __ vldr_f64(r_1->as_FloatRegister(), Address(loadCounter)); 650 } 651 } 652 } 653 654 // restore sp 655 if(sp_offset) { 656 if(__ is_valid_for_imm12(sp_offset)) { 657 __ sub(sp, sp, sp_offset); 658 } else { 659 // add operates encoded imm12, we need plain 660 __ mov(rscratch1, sp_offset); 661 __ sub(sp, sp, rscratch1); 662 } 663 } 664 665 if(total_args_passed) { 666 // restore loadCounter 667 __ ldr(loadCounter, Address(sp, -wordSize)); 668 } 669 670 // 6243940 We might end up in handle_wrong_method if 671 // the callee is deoptimized as we race thru here. If that 672 // happens we don't want to take a safepoint because the 673 // caller frame will look interpreted and arguments are now 674 // "compiled" so it is much better to make this transition 675 // invisible to the stack walking code. Unfortunately if 676 // we try and find the callee by normal means a safepoint 677 // is possible. So we stash the desired callee in the thread 678 // and the vm will find there should this case occur. 679 680 __ str(rmethod, Address(rthread, JavaThread::callee_target_offset())); 681 682 // Will jump to the compiled code just as if compiled code was doing it. 683 __ ldr(rscratch1, Address(rmethod, in_bytes(Method::from_compiled_offset()))); 684 __ b(rscratch1); 685 } 686 687 // --------------------------------------------------------------- 688 AdapterHandlerEntry* SharedRuntime::generate_i2c2i_adapters(MacroAssembler *masm, 689 int total_args_passed, 690 int comp_args_on_stack, 691 const BasicType *sig_bt, 692 const VMRegPair *regs, 693 AdapterFingerPrint* fingerprint) { 694 address i2c_entry = __ pc(); 695 gen_i2c_adapter(masm, total_args_passed, comp_args_on_stack, sig_bt, regs); 696 697 address c2i_unverified_entry = __ pc(); 698 Label skip_fixup; 699 700 Label ok; 701 702 Register holder = rscratch2; 703 Register receiver = j_rarg0; 704 Register tmp = r10; // A call-clobbered register not used for arg passing 705 706 // ------------------------------------------------------------------------- 707 // Generate a C2I adapter. On entry we know rmethod holds the Method* during calls 708 // to the interpreter. The args start out packed in the compiled layout. They 709 // need to be unpacked into the interpreter layout. This will almost always 710 // require some stack space. We grow the current (compiled) stack, then repack 711 // the args. We finally end in a jump to the generic interpreter entry point. 712 // On exit from the interpreter, the interpreter will restore our SP (lest the 713 // compiled code, which relys solely on SP and not FP, get sick). 714 715 { 716 __ block_comment("c2i_unverified_entry {"); 717 __ load_klass(rscratch1, receiver); 718 __ ldr(tmp, Address(holder, CompiledICHolder::holder_klass_offset())); 719 __ cmp(rscratch1, tmp); 720 __ ldr(rmethod, Address(holder, CompiledICHolder::holder_method_offset())); 721 __ b(ok, Assembler::EQ); 722 __ far_jump(RuntimeAddress(SharedRuntime::get_ic_miss_stub())); 723 724 __ bind(ok); 725 // Method might have been compiled since the call site was patched to 726 // interpreted; if that is the case treat it as a miss so we can get 727 // the call site corrected. 728 __ ldr(rscratch1, Address(rmethod, in_bytes(Method::code_offset()))); 729 __ cbz(rscratch1, skip_fixup); 730 __ far_jump(RuntimeAddress(SharedRuntime::get_ic_miss_stub())); 731 __ block_comment("} c2i_unverified_entry"); 732 } 733 734 address c2i_entry = __ pc(); 735 736 gen_c2i_adapter(masm, total_args_passed, comp_args_on_stack, sig_bt, regs, skip_fixup); 737 738 __ flush(); 739 return AdapterHandlerLibrary::new_entry(fingerprint, i2c_entry, c2i_entry, c2i_unverified_entry); 740 } 741 742 int SharedRuntime::c_calling_convention(const BasicType *sig_bt, 743 VMRegPair *regs, 744 VMRegPair *regs2, 745 int total_args_passed) { 746 assert(regs2 == NULL, "not needed on AArch32"); 747 748 // We return the amount of VMRegImpl stack slots we need to reserve for all 749 // the arguments NOT counting out_preserve_stack_slots. 750 751 static const Register INT_ArgReg[Argument::n_int_register_parameters_c] = { 752 c_rarg0, c_rarg1, c_rarg2, c_rarg3 753 }; 754 const int FP_ArgReg_N = 16; 755 static const FloatRegister FP_ArgReg[] = { 756 f0, f1, f2, f3, 757 f4, f5, f6, f7, 758 f8, f9, f10, f11, 759 f12, f13, f14, f15, 760 }; 761 unsigned long fp_free_mask = (1 << FP_ArgReg_N) - 1; 762 763 uint int_args = 0; 764 uint fp_args = 0; 765 uint stk_args = 0; 766 767 for (int i = 0; i < total_args_passed; i++) { 768 switch (sig_bt[i]) { 769 case T_BOOLEAN: 770 case T_CHAR: 771 case T_BYTE: 772 case T_SHORT: 773 case T_INT: 774 case T_OBJECT: 775 case T_ARRAY: 776 case T_ADDRESS: 777 case T_METADATA: 778 if (int_args < Argument::n_int_register_parameters_c) { 779 regs[i].set1(INT_ArgReg[int_args++]->as_VMReg()); 780 } else { 781 regs[i].set1(VMRegImpl::stack2reg(stk_args)); 782 stk_args += 1; 783 } 784 break; 785 case T_LONG: 786 assert(sig_bt[i + 1] == T_VOID, "expecting half"); 787 if (int_args + 1 < Argument::n_int_register_parameters_c) { 788 if ((int_args % 2) != 0) { 789 ++int_args; 790 } 791 regs[i].set2(INT_ArgReg[int_args]->as_VMReg()); 792 int_args += 2; 793 } else { 794 if (stk_args % 2 != 0) { 795 ++stk_args; 796 } 797 regs[i].set2(VMRegImpl::stack2reg(stk_args)); 798 stk_args += 2; 799 int_args = Argument::n_int_register_parameters_c; 800 } 801 break; 802 case T_FLOAT: 803 if (fp_free_mask & ((1 << FP_ArgReg_N)-1)) { 804 unsigned index = __builtin_ctz(fp_free_mask); 805 regs[i].set1(FP_ArgReg[index]->as_VMReg()); 806 fp_free_mask &= ~(1 << index); 807 fp_args += 2 * ((~index) & 1); 808 } else { 809 regs[i].set1(VMRegImpl::stack2reg(stk_args)); 810 stk_args += 1; 811 } 812 break; 813 case T_DOUBLE: 814 assert(sig_bt[i + 1] == T_VOID, "expecting half"); 815 if (fp_args + 1 < FP_ArgReg_N) { 816 fp_free_mask &= ~(3 << fp_args); 817 regs[i].set2(FP_ArgReg[fp_args]->as_VMReg()); 818 fp_args += 2; 819 } else { 820 regs[i].set2(VMRegImpl::stack2reg(stk_args)); 821 stk_args += 2; 822 } 823 break; 824 case T_VOID: // Halves of longs and doubles 825 assert(i != 0 && (sig_bt[i - 1] == T_LONG || sig_bt[i - 1] == T_DOUBLE), "expecting half"); 826 regs[i].set_bad(); 827 break; 828 default: 829 ShouldNotReachHere(); 830 break; 831 } 832 } 833 834 return round_to(stk_args, StackAlignmentInBytes/wordSize); 835 } 836 837 // On 64 bit we will store integer like items to the stack as 838 // 64 bits items (sparc abi) even though java would only store 839 // 32bits for a parameter. On 32bit it will simply be 32 bits 840 // So this routine will do 32->32 on 32bit and 32->64 on 64bit 841 842 static void move_int(MacroAssembler* masm, VMRegPair src, VMRegPair dst) { 843 if (src.first()->is_stack()) { 844 if (dst.first()->is_stack()) { 845 // stack to stack 846 __ ldr(rscratch1, Address(rfp, reg2offset_in(src.first()))); 847 __ str(rscratch1, Address(sp, reg2offset_out(dst.first()))); 848 } else { 849 // stack to reg 850 __ ldr(dst.first()->as_Register(), Address(rfp, reg2offset_in(src.first()))); 851 } 852 } else if (dst.first()->is_stack()) { 853 // reg to stack 854 __ str(src.first()->as_Register(), Address(sp, reg2offset_out(dst.first()))); 855 } else { 856 if (dst.first() != src.first()) { 857 __ mov(dst.first()->as_Register(), src.first()->as_Register()); 858 } 859 } 860 } 861 862 // An oop arg. Must pass a handle not the oop itself 863 static void object_move(MacroAssembler* masm, 864 OopMap* map, 865 int oop_handle_offset, 866 int framesize_in_slots, 867 VMRegPair src, 868 VMRegPair dst, 869 bool is_receiver, 870 int* receiver_offset) { 871 872 // must pass a handle. First figure out the location we use as a handle 873 874 Register rHandle = dst.first()->is_stack() ? rscratch2 : dst.first()->as_Register(); 875 876 // See if oop is NULL if it is we need no handle 877 878 if (src.first()->is_stack()) { 879 880 // Oop is already on the stack as an argument 881 int offset_in_older_frame = src.first()->reg2stack() + SharedRuntime::out_preserve_stack_slots(); 882 map->set_oop(VMRegImpl::stack2reg(offset_in_older_frame + framesize_in_slots)); 883 if (is_receiver) { 884 *receiver_offset = (offset_in_older_frame + framesize_in_slots) * VMRegImpl::stack_slot_size; 885 } 886 887 __ ldr(rscratch1, Address(rfp, reg2offset_in(src.first()))); 888 __ lea(rHandle, Address(rfp, reg2offset_in(src.first()))); 889 // conditionally move a NULL 890 __ cmp(rscratch1, 0); 891 __ mov(rHandle, 0, Assembler::EQ); 892 } else { 893 894 // Oop is in an a register we must store it to the space we reserve 895 // on the stack for oop_handles and pass a handle if oop is non-NULL 896 897 const Register rOop = src.first()->as_Register(); 898 int oop_slot; 899 if (rOop == j_rarg0) 900 oop_slot = 0; 901 else if (rOop == j_rarg1) 902 oop_slot = 1; 903 else if (rOop == j_rarg2) 904 oop_slot = 2; 905 else { 906 assert(rOop == j_rarg3, "wrong register"); 907 oop_slot = 3; 908 } 909 910 oop_slot = oop_slot * VMRegImpl::slots_per_word + oop_handle_offset; 911 int offset = oop_slot*VMRegImpl::stack_slot_size; 912 913 map->set_oop(VMRegImpl::stack2reg(oop_slot)); 914 // Store oop in handle area, may be NULL 915 __ str(rOop, Address(sp, offset)); 916 if (is_receiver) { 917 *receiver_offset = offset; 918 } 919 920 __ cmp(rOop, 0); 921 __ lea(rHandle, Address(sp, offset)); 922 // conditionally move a NULL 923 __ mov(rHandle, 0, Assembler::EQ); 924 } 925 926 // If arg is on the stack then place it otherwise it is already in correct reg. 927 if (dst.first()->is_stack()) { 928 __ str(rHandle, Address(sp, reg2offset_out(dst.first()))); 929 } 930 } 931 932 // A float arg may have to do float reg int reg conversion 933 static void float_move(MacroAssembler* masm, VMRegPair src, VMRegPair dst) { 934 if (src.first()->is_stack()) { 935 if (dst.first()->is_stack()) { 936 // stack to stack 937 // Have no vfp scratch registers, so copy via gpr 938 __ ldr(rscratch1, Address(rfp, reg2offset_in(src.first()))); 939 __ str(rscratch1, Address(sp, reg2offset_out(dst.first()))); 940 } else { 941 // stack to reg 942 __ vldr_f32(dst.first()->as_FloatRegister(), Address(rfp, reg2offset_in(src.first()))); 943 } 944 } else if (dst.first()->is_stack()) { 945 // reg to stack 946 __ vstr_f32(src.first()->as_FloatRegister(), Address(sp, reg2offset_out(dst.first()))); 947 } else { 948 if (dst.first() != src.first()) { 949 __ vmov_f32(dst.first()->as_FloatRegister(), src.first()->as_FloatRegister()); 950 } 951 } 952 } 953 954 // A long move 955 static void long_move(MacroAssembler* masm, VMRegPair src, VMRegPair dst) { 956 if (src.first()->is_stack()) { 957 if (dst.first()->is_stack()) { 958 // stack to stack 959 __ ldrd(rscratch1, rscratch2, Address(rfp, reg2offset_in(src.first()))); 960 __ strd(rscratch1, rscratch2, Address(sp, reg2offset_out(dst.first()))); 961 } else { 962 // stack to reg 963 __ ldrd(dst.first()->as_Register(), dst.second()->as_Register(), 964 Address(rfp, reg2offset_in(src.first()))); 965 } 966 } else if (dst.first()->is_stack()) { 967 // reg to stack 968 __ strd(src.first()->as_Register(), src.second()->as_Register(), 969 Address(sp, reg2offset_out(dst.first()))); 970 } else { 971 // reg to reg 972 if (dst.first() != src.first()) { 973 if (dst.first() != src.second()) { 974 __ mov(dst.first()->as_Register(), src.first()->as_Register()); 975 __ mov(dst.second()->as_Register(), src.second()->as_Register()); 976 } else { 977 __ mov(dst.second()->as_Register(), src.second()->as_Register()); 978 __ mov(dst.first()->as_Register(), src.first()->as_Register()); 979 } 980 } 981 } 982 } 983 984 // A double move 985 static void double_move(MacroAssembler* masm, VMRegPair src, VMRegPair dst) { 986 if (src.first()->is_stack()) { 987 if (dst.first()->is_stack()) { 988 // stack to stack 989 // Have no vfp scratch registers, so copy via gpr 990 __ ldrd(rscratch1, rscratch2, Address(rfp, reg2offset_in(src.first()))); 991 __ strd(rscratch1, rscratch2, Address(sp, reg2offset_out(dst.first()))); 992 } else { 993 // stack to reg 994 __ vldr_f64(dst.first()->as_FloatRegister(), Address(rfp, reg2offset_in(src.first()))); 995 } 996 } else if (dst.first()->is_stack()) { 997 // reg to stack 998 __ vstr_f64(src.first()->as_FloatRegister(), Address(sp, reg2offset_out(dst.first()))); 999 } else { 1000 if (dst.first() != src.first()) { 1001 __ vmov_f64(dst.first()->as_FloatRegister(), src.first()->as_FloatRegister()); 1002 } 1003 } 1004 } 1005 1006 1007 void SharedRuntime::save_native_result(MacroAssembler *masm, BasicType ret_type, int frame_slots) { 1008 // We always ignore the frame_slots arg and just use the space just below frame pointer 1009 // which by this time is free to use 1010 switch (ret_type) { 1011 case T_FLOAT: 1012 __ vstr_f32(f0, Address(rfp, -2 * wordSize)); 1013 break; 1014 case T_DOUBLE: 1015 __ vstr_f64(d0, Address(rfp, -3 * wordSize)); 1016 break; 1017 case T_LONG: 1018 __ strd(r0, r1, Address(rfp, -3 * wordSize)); 1019 break; 1020 case T_VOID: 1021 break; 1022 default: 1023 __ str(r0, Address(rfp, -2 * wordSize)); 1024 break; 1025 } 1026 } 1027 1028 void SharedRuntime::restore_native_result(MacroAssembler *masm, BasicType ret_type, int frame_slots) { 1029 // We always ignore the frame_slots arg and just use the space just below frame pointer 1030 // which by this time is free to use 1031 switch (ret_type) { 1032 case T_FLOAT: 1033 __ vldr_f32(d0, Address(rfp, -2 * wordSize)); 1034 break; 1035 case T_DOUBLE: 1036 __ vldr_f64(d0, Address(rfp, -3 * wordSize)); 1037 break; 1038 case T_LONG: 1039 __ ldrd(r0, r1, Address(rfp, -3 * wordSize)); 1040 break; 1041 case T_VOID: 1042 break; 1043 default: 1044 __ ldr(r0, Address(rfp, -2 * wordSize)); 1045 break; 1046 } 1047 } 1048 1049 static void save_args(MacroAssembler *masm, int arg_count, int first_arg, VMRegPair *args) { 1050 RegSet x; 1051 for ( int i = first_arg ; i < arg_count ; i++ ) { 1052 if (args[i].first()->is_Register()) { 1053 x = x + args[i].first()->as_Register(); 1054 } else if (args[i].first()->is_FloatRegister()) { 1055 FloatRegister fr = args[i].first()->as_FloatRegister(); 1056 1057 if (args[i].second()->is_FloatRegister()) { 1058 assert(args[i].is_single_phys_reg(), "doubles should be 2 consequents float regs"); 1059 __ decrement(sp, 2 * wordSize); 1060 __ vstr_f64(fr, Address(sp)); 1061 } else { 1062 __ decrement(sp, wordSize); 1063 __ vstr_f32(fr, Address(sp)); 1064 } 1065 } 1066 } 1067 __ push(x, sp); 1068 } 1069 1070 static void restore_args(MacroAssembler *masm, int arg_count, int first_arg, VMRegPair *args) { 1071 RegSet x; 1072 for ( int i = first_arg ; i < arg_count ; i++ ) { 1073 if (args[i].first()->is_Register()) { 1074 x = x + args[i].first()->as_Register(); 1075 } else { 1076 ; 1077 } 1078 } 1079 __ pop(x, sp); 1080 for ( int i = first_arg ; i < arg_count ; i++ ) { 1081 if (args[i].first()->is_Register()) { 1082 ; 1083 } else if (args[i].first()->is_FloatRegister()) { 1084 FloatRegister fr = args[i].first()->as_FloatRegister(); 1085 1086 if (args[i].second()->is_FloatRegister()) { 1087 assert(args[i].is_single_phys_reg(), "doubles should be 2 consequents float regs"); 1088 __ vstr_f64(fr, Address(sp)); 1089 __ increment(sp, 2 * wordSize); 1090 } else { 1091 __ vstr_f32(fr, Address(sp)); 1092 __ increment(sp, wordSize); 1093 } 1094 } 1095 } 1096 } 1097 1098 1099 // Check GC_locker::needs_gc and enter the runtime if it's true. This 1100 // keeps a new JNI critical region from starting until a GC has been 1101 // forced. Save down any oops in registers and describe them in an 1102 // OopMap. 1103 static void check_needs_gc_for_critical_native(MacroAssembler* masm, 1104 int stack_slots, 1105 int total_c_args, 1106 int total_in_args, 1107 int arg_save_area, 1108 OopMapSet* oop_maps, 1109 VMRegPair* in_regs, 1110 BasicType* in_sig_bt) { Unimplemented(); } 1111 1112 // Unpack an array argument into a pointer to the body and the length 1113 // if the array is non-null, otherwise pass 0 for both. 1114 static void unpack_array_argument(MacroAssembler* masm, VMRegPair reg, BasicType in_elem_type, VMRegPair body_arg, VMRegPair length_arg) { Unimplemented(); } 1115 1116 1117 class ComputeMoveOrder: public StackObj { 1118 class MoveOperation: public ResourceObj { 1119 friend class ComputeMoveOrder; 1120 private: 1121 VMRegPair _src; 1122 VMRegPair _dst; 1123 int _src_index; 1124 int _dst_index; 1125 bool _processed; 1126 MoveOperation* _next; 1127 MoveOperation* _prev; 1128 1129 static int get_id(VMRegPair r) { Unimplemented(); return 0; } 1130 1131 public: 1132 MoveOperation(int src_index, VMRegPair src, int dst_index, VMRegPair dst): 1133 _src(src) 1134 , _src_index(src_index) 1135 , _dst(dst) 1136 , _dst_index(dst_index) 1137 , _next(NULL) 1138 , _prev(NULL) 1139 , _processed(false) { Unimplemented(); } 1140 1141 VMRegPair src() const { Unimplemented(); return _src; } 1142 int src_id() const { Unimplemented(); return 0; } 1143 int src_index() const { Unimplemented(); return 0; } 1144 VMRegPair dst() const { Unimplemented(); return _src; } 1145 void set_dst(int i, VMRegPair dst) { Unimplemented(); } 1146 int dst_index() const { Unimplemented(); return 0; } 1147 int dst_id() const { Unimplemented(); return 0; } 1148 MoveOperation* next() const { Unimplemented(); return 0; } 1149 MoveOperation* prev() const { Unimplemented(); return 0; } 1150 void set_processed() { Unimplemented(); } 1151 bool is_processed() const { Unimplemented(); return 0; } 1152 1153 // insert 1154 void break_cycle(VMRegPair temp_register) { Unimplemented(); } 1155 1156 void link(GrowableArray<MoveOperation*>& killer) { Unimplemented(); } 1157 }; 1158 1159 private: 1160 GrowableArray<MoveOperation*> edges; 1161 1162 public: 1163 ComputeMoveOrder(int total_in_args, VMRegPair* in_regs, int total_c_args, VMRegPair* out_regs, 1164 BasicType* in_sig_bt, GrowableArray<int>& arg_order, VMRegPair tmp_vmreg) { Unimplemented(); } 1165 1166 // Collected all the move operations 1167 void add_edge(int src_index, VMRegPair src, int dst_index, VMRegPair dst) { Unimplemented(); } 1168 1169 // Walk the edges breaking cycles between moves. The result list 1170 // can be walked in order to produce the proper set of loads 1171 GrowableArray<MoveOperation*>* get_store_order(VMRegPair temp_register) { Unimplemented(); return 0; } 1172 }; 1173 1174 1175 static void rt_call(MacroAssembler* masm, address dest) { 1176 CodeBlob *cb = CodeCache::find_blob(dest); 1177 if (cb) { 1178 __ far_call(RuntimeAddress(dest), NULL, rscratch2); 1179 } else { 1180 __ lea(rscratch2, RuntimeAddress(dest)); 1181 __ bl(rscratch2); 1182 __ maybe_isb(); 1183 } 1184 } 1185 1186 static void verify_oop_args(MacroAssembler* masm, 1187 methodHandle method, 1188 const BasicType* sig_bt, 1189 const VMRegPair* regs) { 1190 Register temp_reg = rscratch2; // not part of any compiled calling seq 1191 if (VerifyOops) { 1192 for (int i = 0; i < method->size_of_parameters(); i++) { 1193 if (sig_bt[i] == T_OBJECT || 1194 sig_bt[i] == T_ARRAY) { 1195 VMReg r = regs[i].first(); 1196 assert(r->is_valid(), "bad oop arg"); 1197 if (r->is_stack()) { 1198 __ ldr(temp_reg, Address(sp, r->reg2stack() * VMRegImpl::stack_slot_size)); 1199 __ verify_oop(temp_reg); 1200 } else { 1201 __ verify_oop(r->as_Register()); 1202 } 1203 } 1204 } 1205 } 1206 } 1207 1208 static void gen_special_dispatch(MacroAssembler* masm, 1209 methodHandle method, 1210 const BasicType* sig_bt, 1211 const VMRegPair* regs) { 1212 verify_oop_args(masm, method, sig_bt, regs); 1213 vmIntrinsics::ID iid = method->intrinsic_id(); 1214 1215 // Now write the args into the outgoing interpreter space 1216 bool has_receiver = false; 1217 Register receiver_reg = noreg; 1218 int member_arg_pos = -1; 1219 Register member_reg = noreg; 1220 int ref_kind = MethodHandles::signature_polymorphic_intrinsic_ref_kind(iid); 1221 if (ref_kind != 0) { 1222 member_arg_pos = method->size_of_parameters() - 1; // trailing MemberName argument 1223 member_reg = r4; 1224 has_receiver = MethodHandles::ref_kind_has_receiver(ref_kind); 1225 } else if (iid == vmIntrinsics::_invokeBasic) { 1226 has_receiver = true; 1227 } else { 1228 fatal(err_msg_res("unexpected intrinsic id %d", iid)); 1229 } 1230 1231 if (member_reg != noreg) { 1232 // Load the member_arg into register, if necessary. 1233 SharedRuntime::check_member_name_argument_is_last_argument(method, sig_bt, regs); 1234 VMReg r = regs[member_arg_pos].first(); 1235 if (r->is_stack()) { 1236 __ ldr(member_reg, Address(sp, r->reg2stack() * VMRegImpl::stack_slot_size)); 1237 } else { 1238 // no data motion is needed 1239 member_reg = r->as_Register(); 1240 } 1241 } 1242 1243 if (has_receiver) { 1244 // Make sure the receiver is loaded into a register. 1245 assert(method->size_of_parameters() > 0, "oob"); 1246 assert(sig_bt[0] == T_OBJECT, "receiver argument must be an object"); 1247 VMReg r = regs[0].first(); 1248 assert(r->is_valid(), "bad receiver arg"); 1249 if (r->is_stack()) { 1250 // Porting note: This assumes that compiled calling conventions always 1251 // pass the receiver oop in a register. If this is not true on some 1252 // platform, pick a temp and load the receiver from stack. 1253 fatal("receiver always in a register"); 1254 } else { 1255 // no data motion is needed 1256 receiver_reg = r->as_Register(); 1257 } 1258 } 1259 1260 // Figure out which address we are really jumping to: 1261 MethodHandles::generate_method_handle_dispatch(masm, iid, 1262 receiver_reg, member_reg, /*for_compiler_entry:*/ true); 1263 } 1264 1265 // --------------------------------------------------------------------------- 1266 // Generate a native wrapper for a given method. The method takes arguments 1267 // in the Java compiled code convention, marshals them to the native 1268 // convention (handlizes oops, etc), transitions to native, makes the call, 1269 // returns to java state (possibly blocking), unhandlizes any result and 1270 // returns. 1271 // 1272 // Critical native functions are a shorthand for the use of 1273 // GetPrimtiveArrayCritical and disallow the use of any other JNI 1274 // functions. The wrapper is expected to unpack the arguments before 1275 // passing them to the callee and perform checks before and after the 1276 // native call to ensure that they GC_locker 1277 // lock_critical/unlock_critical semantics are followed. Some other 1278 // parts of JNI setup are skipped like the tear down of the JNI handle 1279 // block and the check for pending exceptions it's impossible for them 1280 // to be thrown. 1281 // 1282 // They are roughly structured like this: 1283 // if (GC_locker::needs_gc()) 1284 // SharedRuntime::block_for_jni_critical(); 1285 // tranistion to thread_in_native 1286 // unpack arrray arguments and call native entry point 1287 // check for safepoint in progress 1288 // check if any thread suspend flags are set 1289 // call into JVM and possible unlock the JNI critical 1290 // if a GC was suppressed while in the critical native. 1291 // transition back to thread_in_Java 1292 // return to caller 1293 // 1294 nmethod* SharedRuntime::generate_native_wrapper(MacroAssembler* masm, 1295 methodHandle method, 1296 int compile_id, 1297 BasicType* in_sig_bt, 1298 VMRegPair* in_regs, 1299 BasicType ret_type) { 1300 if (method->is_method_handle_intrinsic()) { 1301 vmIntrinsics::ID iid = method->intrinsic_id(); 1302 intptr_t start = (intptr_t)__ pc(); 1303 int vep_offset = ((intptr_t)__ pc()) - start; 1304 1305 // First instruction must be a nop as it may need to be patched on deoptimisation 1306 __ nop(); 1307 gen_special_dispatch(masm, 1308 method, 1309 in_sig_bt, 1310 in_regs); 1311 int frame_complete = ((intptr_t)__ pc()) - start; // not complete, period 1312 __ flush(); 1313 int stack_slots = SharedRuntime::out_preserve_stack_slots(); // no out slots at all, actually 1314 return nmethod::new_native_nmethod(method, 1315 compile_id, 1316 masm->code(), 1317 vep_offset, 1318 frame_complete, 1319 stack_slots / VMRegImpl::slots_per_word, 1320 in_ByteSize(-1), 1321 in_ByteSize(-1), 1322 (OopMapSet*)NULL); 1323 } 1324 1325 bool is_critical_native = true; 1326 address native_func = method->critical_native_function(); 1327 if (native_func == NULL) { 1328 native_func = method->native_function(); 1329 is_critical_native = false; 1330 } 1331 assert(native_func != NULL, "must have function"); 1332 1333 // An OopMap for lock (and class if static) 1334 OopMapSet *oop_maps = new OopMapSet(); 1335 intptr_t start = (intptr_t)__ pc(); 1336 1337 // We have received a description of where all the java arg are located 1338 // on entry to the wrapper. We need to convert these args to where 1339 // the jni function will expect them. To figure out where they go 1340 // we convert the java signature to a C signature by inserting 1341 // the hidden arguments as arg[0] and possibly arg[1] (static method) 1342 1343 const int total_in_args = method->size_of_parameters(); 1344 int total_c_args = total_in_args; 1345 if (!is_critical_native) { 1346 total_c_args += 1; 1347 if (method->is_static()) { 1348 total_c_args++; 1349 } 1350 } else { 1351 for (int i = 0; i < total_in_args; i++) { 1352 if (in_sig_bt[i] == T_ARRAY) { 1353 total_c_args++; 1354 } 1355 } 1356 } 1357 1358 BasicType* out_sig_bt = NEW_RESOURCE_ARRAY(BasicType, total_c_args); 1359 VMRegPair* out_regs = NEW_RESOURCE_ARRAY(VMRegPair, total_c_args); 1360 BasicType* in_elem_bt = NULL; 1361 1362 int argc = 0; 1363 if (!is_critical_native) { 1364 out_sig_bt[argc++] = T_ADDRESS; 1365 if (method->is_static()) { 1366 out_sig_bt[argc++] = T_OBJECT; 1367 } 1368 1369 for (int i = 0; i < total_in_args ; i++ ) { 1370 out_sig_bt[argc++] = in_sig_bt[i]; 1371 } 1372 } else { 1373 Thread* THREAD = Thread::current(); 1374 in_elem_bt = NEW_RESOURCE_ARRAY(BasicType, total_in_args); 1375 SignatureStream ss(method->signature()); 1376 for (int i = 0; i < total_in_args ; i++ ) { 1377 if (in_sig_bt[i] == T_ARRAY) { 1378 // Arrays are passed as int, elem* pair 1379 out_sig_bt[argc++] = T_INT; 1380 out_sig_bt[argc++] = T_ADDRESS; 1381 Symbol* atype = ss.as_symbol(CHECK_NULL); 1382 const char* at = atype->as_C_string(); 1383 if (strlen(at) == 2) { 1384 assert(at[0] == '[', "must be"); 1385 switch (at[1]) { 1386 case 'B': in_elem_bt[i] = T_BYTE; break; 1387 case 'C': in_elem_bt[i] = T_CHAR; break; 1388 case 'D': in_elem_bt[i] = T_DOUBLE; break; 1389 case 'F': in_elem_bt[i] = T_FLOAT; break; 1390 case 'I': in_elem_bt[i] = T_INT; break; 1391 case 'J': in_elem_bt[i] = T_LONG; break; 1392 case 'S': in_elem_bt[i] = T_SHORT; break; 1393 case 'Z': in_elem_bt[i] = T_BOOLEAN; break; 1394 default: ShouldNotReachHere(); 1395 } 1396 } 1397 } else { 1398 out_sig_bt[argc++] = in_sig_bt[i]; 1399 in_elem_bt[i] = T_VOID; 1400 } 1401 if (in_sig_bt[i] != T_VOID) { 1402 assert(in_sig_bt[i] == ss.type(), "must match"); 1403 ss.next(); 1404 } 1405 } 1406 } 1407 1408 // Now figure out where the args must be stored and how much stack space 1409 // they require. 1410 int out_arg_slots; 1411 out_arg_slots = c_calling_convention(out_sig_bt, out_regs, NULL, total_c_args); 1412 1413 // Compute framesize for the wrapper. We need to handlize all oops in 1414 // incoming registers 1415 1416 // Calculate the total number of stack slots we will need. 1417 1418 // First count the abi requirement plus all of the outgoing args 1419 int stack_slots = SharedRuntime::out_preserve_stack_slots() + out_arg_slots; 1420 1421 // Now the space for the inbound oop handle area 1422 int total_save_slots = -1; 1423 if (is_critical_native) { 1424 // Critical natives may have to call out so they need a save area 1425 // for register arguments. 1426 int double_slots = 0; 1427 int single_slots = 0; 1428 for ( int i = 0; i < total_in_args; i++) { 1429 if (in_regs[i].first()->is_Register()) { 1430 const Register reg = in_regs[i].first()->as_Register(); 1431 switch (in_sig_bt[i]) { 1432 case T_ARRAY: // critical array (uses 2 slots on LP64) 1433 case T_BOOLEAN: 1434 case T_BYTE: 1435 case T_SHORT: 1436 case T_CHAR: 1437 case T_INT: single_slots++; break; 1438 case T_LONG: double_slots++; break; 1439 default: ShouldNotReachHere(); 1440 } 1441 } else if (in_regs[i].first()->is_FloatRegister()) { 1442 ShouldNotReachHere(); 1443 } 1444 } 1445 total_save_slots = double_slots * 2 + single_slots; 1446 // align the save area 1447 if (double_slots != 0) { 1448 stack_slots = round_to(stack_slots, 2); 1449 } 1450 } else { 1451 total_save_slots = 4 * VMRegImpl::slots_per_word; // 4 arguments passed in registers 1452 } 1453 assert(total_save_slots != -1, "initialize total_save_slots!"); 1454 1455 int oop_handle_offset = stack_slots; 1456 stack_slots += total_save_slots; 1457 1458 // Now any space we need for handlizing a klass if static method 1459 1460 int klass_slot_offset = 0; 1461 int klass_offset = -1; 1462 int lock_slot_offset = 0; 1463 bool is_static = false; 1464 1465 if (method->is_static()) { 1466 klass_slot_offset = stack_slots; 1467 stack_slots += VMRegImpl::slots_per_word; 1468 klass_offset = klass_slot_offset * VMRegImpl::stack_slot_size; 1469 is_static = true; 1470 } 1471 1472 // Plus a lock if needed 1473 1474 if (method->is_synchronized()) { 1475 lock_slot_offset = stack_slots; 1476 stack_slots += VMRegImpl::slots_per_word; 1477 } 1478 1479 // Now a place (+2) to save return values or temp during shuffling 1480 // + 2 for return address (which we own) and saved rfp 1481 stack_slots += 4; 1482 1483 // Ok The space we have allocated will look like: 1484 // 1485 // 1486 // FP-> | saved lr | 1487 // |---------------------| 1488 // | saved fp | 1489 // |---------------------| 1490 // | 2 slots for moves | 1491 // |---------------------| 1492 // | lock box (if sync) | 1493 // |---------------------| <- lock_slot_offset 1494 // | klass (if static) | 1495 // |---------------------| <- klass_slot_offset 1496 // | oopHandle area | 1497 // |---------------------| <- oop_handle_offset (8 java arg registers) 1498 // | outbound memory | 1499 // | based arguments | 1500 // | | 1501 // |---------------------| 1502 // | | 1503 // SP-> | out_preserved_slots | 1504 // 1505 // 1506 1507 1508 // Now compute actual number of stack words we need rounding to make 1509 // stack properly aligned. 1510 stack_slots = round_to(stack_slots, StackAlignmentInSlots); 1511 1512 int stack_size = stack_slots * VMRegImpl::stack_slot_size; 1513 1514 // First thing make an ic check to see if we should even be here 1515 1516 // We are free to use all registers as temps without saving them and 1517 // restoring them except rfp. rfp is the only callee save register 1518 // as far as the interpreter and the compiler(s) are concerned. 1519 1520 1521 const Register ic_reg = rscratch2; 1522 const Register receiver = j_rarg0; 1523 1524 Label hit; 1525 Label exception_pending; 1526 1527 assert_different_registers(ic_reg, receiver, rscratch1); 1528 __ verify_oop(receiver); 1529 __ cmp_klass(receiver, ic_reg, rscratch1); 1530 __ b(hit, Assembler::EQ); 1531 1532 __ far_jump(RuntimeAddress(SharedRuntime::get_ic_miss_stub())); 1533 1534 // Verified entry point must be aligned 1535 __ align(8); 1536 1537 __ bind(hit); 1538 1539 #ifdef ASSERT 1540 __ mov(ic_reg, 0xdead); // trash ic_reg(rscratch2), as used as real scratch further 1541 #endif 1542 1543 int vep_offset = ((intptr_t)__ pc()) - start; 1544 1545 // Generate stack overflow check 1546 1547 // If we have to make this method not-entrant we'll overwrite its 1548 // first instruction with a jump. For this action to be legal we 1549 // must ensure that this first instruction is a B, BL, NOP, BKPT, 1550 // SVC, HVC, or SMC. Make it a NOP. 1551 __ nop(); 1552 1553 if (UseStackBanging) { 1554 __ bang_stack_with_offset(StackShadowPages*os::vm_page_size()); 1555 } else { 1556 Unimplemented(); 1557 } 1558 1559 // Generate a new frame for the wrapper. 1560 __ enter(); 1561 // -2 because return address is already present and so is saved rfp 1562 __ sub(sp, sp, stack_size - 2*wordSize); 1563 1564 // Frame is now completed as far as size and linkage. 1565 int frame_complete = ((intptr_t)__ pc()) - start; 1566 1567 if (is_critical_native) { 1568 check_needs_gc_for_critical_native(masm, stack_slots, total_c_args, total_in_args, 1569 oop_handle_offset, oop_maps, in_regs, in_sig_bt); 1570 } 1571 1572 // 1573 // We immediately shuffle the arguments so that any vm call we have to 1574 // make from here on out (sync slow path, jvmti, etc.) we will have 1575 // captured the oops from our caller and have a valid oopMap for 1576 // them. 1577 1578 // ----------------- 1579 // The Grand Shuffle 1580 1581 // The Java calling convention is either equal (linux) or denser (win64) than the 1582 // c calling convention. However the because of the jni_env argument the c calling 1583 // convention always has at least one more (and two for static) arguments than Java. 1584 // Therefore if we move the args from java -> c backwards then we will never have 1585 // a register->register conflict and we don't have to build a dependency graph 1586 // and figure out how to break any cycles. 1587 // 1588 1589 // Record sp-based slot for receiver on stack for non-static methods 1590 int receiver_offset = -1; 1591 1592 // This is a trick. We double the stack slots so we can claim 1593 // the oops in the caller's frame. Since we are sure to have 1594 // more args than the caller doubling is enough to make 1595 // sure we can capture all the incoming oop args from the 1596 // caller. 1597 // 1598 OopMap* map = new OopMap(stack_slots * 2, 0 /* arg_slots*/); 1599 1600 // Mark location of rfp (someday) 1601 // map->set_callee_saved(VMRegImpl::stack2reg( stack_slots - 2), stack_slots * 2, 0, vmreg(rfp)); 1602 1603 1604 #ifdef ASSERT 1605 bool reg_destroyed[RegisterImpl::number_of_registers]; 1606 bool freg_destroyed[FloatRegisterImpl::number_of_registers]; 1607 for ( int r = 0 ; r < RegisterImpl::number_of_registers ; r++ ) { 1608 reg_destroyed[r] = false; 1609 } 1610 for ( int f = 0 ; f < FloatRegisterImpl::number_of_registers ; f++ ) { 1611 freg_destroyed[f] = false; 1612 } 1613 1614 #endif // ASSERT 1615 1616 // This may iterate in two different directions depending on the 1617 // kind of native it is. The reason is that for regular JNI natives 1618 // the incoming and outgoing registers are offset upwards and for 1619 // critical natives they are offset down. 1620 GrowableArray<int> arg_order(2 * total_in_args); 1621 VMRegPair tmp_vmreg; 1622 tmp_vmreg.set1(rscratch2->as_VMReg()); 1623 1624 if (!is_critical_native) { 1625 for (int i = total_in_args - 1, c_arg = total_c_args - 1; i >= 0; i--, c_arg--) { 1626 arg_order.push(i); 1627 arg_order.push(c_arg); 1628 } 1629 } else { 1630 // Compute a valid move order, using tmp_vmreg to break any cycles 1631 ComputeMoveOrder cmo(total_in_args, in_regs, total_c_args, out_regs, in_sig_bt, arg_order, tmp_vmreg); 1632 } 1633 1634 int temploc = -1; 1635 for (int ai = 0; ai < arg_order.length(); ai += 2) { 1636 int i = arg_order.at(ai); 1637 int c_arg = arg_order.at(ai + 1); 1638 __ block_comment(err_msg("move %d -> %d", i, c_arg)); 1639 if (c_arg == -1) { 1640 assert(is_critical_native, "should only be required for critical natives"); 1641 // This arg needs to be moved to a temporary 1642 __ mov(tmp_vmreg.first()->as_Register(), in_regs[i].first()->as_Register()); 1643 in_regs[i] = tmp_vmreg; 1644 temploc = i; 1645 continue; 1646 } else if (i == -1) { 1647 assert(is_critical_native, "should only be required for critical natives"); 1648 // Read from the temporary location 1649 assert(temploc != -1, "must be valid"); 1650 i = temploc; 1651 temploc = -1; 1652 } 1653 #ifdef ASSERT 1654 if (in_regs[i].first()->is_Register()) { 1655 assert(!reg_destroyed[in_regs[i].first()->as_Register()->encoding()], "destroyed reg!"); 1656 } else if (in_regs[i].first()->is_FloatRegister()) { 1657 assert(!freg_destroyed[in_regs[i].first()->as_FloatRegister()->encoding()], "destroyed reg!"); 1658 } 1659 if (out_regs[c_arg].first()->is_Register()) { 1660 reg_destroyed[out_regs[c_arg].first()->as_Register()->encoding()] = true; 1661 } else if (out_regs[c_arg].first()->is_FloatRegister()) { 1662 freg_destroyed[out_regs[c_arg].first()->as_FloatRegister()->encoding()] = true; 1663 } 1664 #endif // ASSERT 1665 switch (in_sig_bt[i]) { 1666 case T_ARRAY: 1667 if (is_critical_native) { 1668 unpack_array_argument(masm, in_regs[i], in_elem_bt[i], out_regs[c_arg + 1], out_regs[c_arg]); 1669 c_arg++; 1670 #ifdef ASSERT 1671 if (out_regs[c_arg].first()->is_Register()) { 1672 reg_destroyed[out_regs[c_arg].first()->as_Register()->encoding()] = true; 1673 } else if (out_regs[c_arg].first()->is_FloatRegister()) { 1674 freg_destroyed[out_regs[c_arg].first()->as_FloatRegister()->encoding()] = true; 1675 } 1676 #endif 1677 break; 1678 } 1679 case T_OBJECT: 1680 assert(!is_critical_native, "no oop arguments"); 1681 object_move(masm, map, oop_handle_offset, stack_slots, in_regs[i], out_regs[c_arg], 1682 ((i == 0) && (!is_static)), 1683 &receiver_offset); 1684 break; 1685 case T_VOID: 1686 break; 1687 1688 case T_FLOAT: 1689 float_move(masm, in_regs[i], out_regs[c_arg]); 1690 break; 1691 1692 case T_DOUBLE: 1693 assert( i + 1 < total_in_args && 1694 in_sig_bt[i + 1] == T_VOID && 1695 out_sig_bt[c_arg+1] == T_VOID, "bad arg list"); 1696 double_move(masm, in_regs[i], out_regs[c_arg]); 1697 break; 1698 1699 case T_LONG : 1700 long_move(masm, in_regs[i], out_regs[c_arg]); 1701 break; 1702 1703 case T_BOOLEAN : 1704 case T_BYTE : 1705 case T_CHAR : 1706 case T_SHORT : 1707 case T_INT : 1708 move_int(masm, in_regs[i], out_regs[c_arg]); 1709 break; 1710 1711 case T_ADDRESS: assert(false, "found T_ADDRESS in java args"); 1712 case T_NARROWOOP : 1713 case T_METADATA : 1714 case T_NARROWKLASS : 1715 default: 1716 ShouldNotReachHere(); 1717 } 1718 } 1719 1720 // point c_arg at the first arg that is already loaded in case we 1721 // need to spill before we call out 1722 int c_arg = total_c_args - total_in_args; 1723 1724 // We use r4 as the oop handle for the receiver/klass 1725 // It is callee save so it survives the call to native 1726 1727 const Register oop_handle_reg = r4; 1728 1729 // Pre-load a static method's oop. Used both by locking code and 1730 // the normal JNI call code. 1731 if (method->is_static() && !is_critical_native) { 1732 1733 // load oop into a register 1734 __ movoop(oop_handle_reg, 1735 JNIHandles::make_local(method->method_holder()->java_mirror()), 1736 /*immediate*/true); 1737 1738 // Now handlize the static class mirror it's known not-null. 1739 __ str(oop_handle_reg, Address(sp, klass_offset)); 1740 map->set_oop(VMRegImpl::stack2reg(klass_slot_offset)); 1741 1742 // Now get the handle 1743 __ lea(oop_handle_reg, Address(sp, klass_offset)); 1744 // store the klass handle as second argument 1745 __ mov(c_rarg1, oop_handle_reg); 1746 // and protect the arg if we must spill 1747 c_arg--; 1748 } 1749 1750 // Change state to native (we save the return address in the thread, since it might not 1751 // be pushed on the stack when we do a a stack traversal). It is enough that the pc() 1752 // points into the right code segment. It does not have to be the correct return pc. 1753 // We use the same pc/oopMap repeatedly when we call out 1754 1755 intptr_t the_pc = (intptr_t) __ pc(); 1756 oop_maps->add_gc_map(the_pc - start, map); 1757 1758 __ set_last_Java_frame(sp, noreg, (address)the_pc, rscratch1); 1759 1760 1761 // We have all of the arguments setup at this point. We must not touch any register 1762 // argument registers at this point (what if we save/restore them there are no oop? 1763 1764 #ifdef DTRACE_ENABLED 1765 { 1766 SkipIfEqual skip(masm, &DTraceMethodProbes, false); 1767 // protect the args we've loaded 1768 save_args(masm, total_c_args, c_arg, out_regs); 1769 __ mov_metadata(c_rarg1, method()); 1770 __ call_VM_leaf( 1771 CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_entry), 1772 rthread, c_rarg1); 1773 restore_args(masm, total_c_args, c_arg, out_regs); 1774 } 1775 #endif 1776 1777 // RedefineClasses() tracing support for obsolete method entry 1778 if (RC_TRACE_IN_RANGE(0x00001000, 0x00002000)) { 1779 // protect the args we've loaded 1780 save_args(masm, total_c_args, c_arg, out_regs); 1781 __ mov_metadata(c_rarg1, method()); 1782 __ call_VM_leaf( 1783 CAST_FROM_FN_PTR(address, SharedRuntime::rc_trace_method_entry), 1784 rthread, c_rarg1); 1785 restore_args(masm, total_c_args, c_arg, out_regs); 1786 } 1787 1788 // Lock a synchronized method 1789 1790 // Register definitions used by locking and unlocking 1791 1792 Label slow_path_lock; 1793 Label lock_done; 1794 1795 if (method->is_synchronized()) { 1796 assert(!is_critical_native, "unhandled"); 1797 // TODO Fast path disabled as requires at least 4 registers, which already contain arguments prepared for call 1798 1799 // Get the handle (the 2nd argument) 1800 __ mov(oop_handle_reg, c_rarg1); 1801 __ b(slow_path_lock); 1802 1803 // Slow path will re-enter here 1804 __ bind(lock_done); 1805 } 1806 1807 1808 // Finally just about ready to make the JNI call 1809 1810 1811 // get JNIEnv* which is first argument to native 1812 if (!is_critical_native) { 1813 __ lea(c_rarg0, Address(rthread, in_bytes(JavaThread::jni_environment_offset()))); 1814 } 1815 1816 // Now set thread in native 1817 __ mov(rscratch1, _thread_in_native); 1818 __ lea(rscratch2, Address(rthread, JavaThread::thread_state_offset())); 1819 __ dmb(Assembler::ISH); 1820 __ str(rscratch1, rscratch2); 1821 1822 // Do the call 1823 rt_call(masm, native_func); 1824 1825 // Unpack native results. 1826 switch (ret_type) { 1827 case T_BOOLEAN: __ uxtb(r0, r0); break; 1828 case T_CHAR : __ uxth(r0, r0); break; 1829 case T_BYTE : __ sxtb(r0, r0); break; 1830 case T_SHORT : __ sxth(r0, r0); break; 1831 case T_INT : break; 1832 case T_DOUBLE : 1833 case T_FLOAT : 1834 // Result is in d0 we'll save as needed 1835 break; 1836 case T_ARRAY: // Really a handle 1837 case T_OBJECT: // Really a handle 1838 break; // can't de-handlize until after safepoint check 1839 case T_VOID: break; 1840 case T_LONG: break; 1841 default : ShouldNotReachHere(); 1842 } 1843 1844 // Switch thread to "native transition" state before reading the synchronization state. 1845 // This additional state is necessary because reading and testing the synchronization 1846 // state is not atomic w.r.t. GC, as this scenario demonstrates: 1847 // Java thread A, in _thread_in_native state, loads _not_synchronized and is preempted. 1848 // VM thread changes sync state to synchronizing and suspends threads for GC. 1849 // Thread A is resumed to finish this native method, but doesn't block here since it 1850 // didn't see any synchronization is progress, and escapes. 1851 __ mov(rscratch1, _thread_in_native_trans); 1852 __ lea(rscratch2, Address(rthread, JavaThread::thread_state_offset())); 1853 __ dmb(Assembler::ISH); 1854 __ str(rscratch1, rscratch2); 1855 1856 if(os::is_MP()) { 1857 if (UseMembar) { 1858 // Force this write out before the read below 1859 __ dmb(Assembler::SY); 1860 } else { 1861 // Write serialization page so VM thread can do a pseudo remote membar. 1862 // We use the current thread pointer to calculate a thread specific 1863 // offset to write to within the page. This minimizes bus traffic 1864 // due to cache line collision. 1865 __ serialize_memory(rthread, rscratch1); 1866 } 1867 } 1868 1869 Label after_transition; 1870 1871 // check for safepoint operation in progress and/or pending suspend requests 1872 { 1873 Label Continue; 1874 1875 __ mov(rscratch1, ExternalAddress((address)SafepointSynchronize::address_of_state())); 1876 __ ldr(rscratch1, Address(rscratch1)); 1877 __ cmp(rscratch1, SafepointSynchronize::_not_synchronized); 1878 1879 Label L; 1880 __ b(L, Assembler::NE); 1881 __ ldr(rscratch1, Address(rthread, JavaThread::suspend_flags_offset())); 1882 __ cbz(rscratch1, Continue); 1883 __ bind(L); 1884 1885 // Don't use call_VM as it will see a possible pending exception and forward it 1886 // and never return here preventing us from clearing _last_native_pc down below. 1887 // 1888 save_native_result(masm, ret_type, stack_slots); 1889 __ mov(c_rarg0, rthread); 1890 #ifndef PRODUCT 1891 assert(frame::arg_reg_save_area_bytes == 0, "not expecting frame reg save area"); 1892 #endif 1893 if (!is_critical_native) { 1894 __ lea(rscratch1, RuntimeAddress(CAST_FROM_FN_PTR(address, JavaThread::check_special_condition_for_native_trans))); 1895 } else { 1896 __ lea(rscratch1, RuntimeAddress(CAST_FROM_FN_PTR(address, JavaThread::check_special_condition_for_native_trans_and_transition))); 1897 } 1898 __ bl(rscratch1); 1899 __ maybe_isb(); 1900 // Restore any method result value 1901 restore_native_result(masm, ret_type, stack_slots); 1902 1903 if (is_critical_native) { 1904 // The call above performed the transition to thread_in_Java so 1905 // skip the transition logic below. 1906 __ b(after_transition); 1907 } 1908 1909 __ bind(Continue); 1910 } 1911 1912 // change thread state 1913 __ mov(rscratch1, _thread_in_Java); 1914 __ lea(rscratch2, Address(rthread, JavaThread::thread_state_offset())); 1915 __ dmb(Assembler::ISH); 1916 __ str(rscratch1, rscratch2); 1917 __ bind(after_transition); 1918 1919 Label reguard; 1920 Label reguard_done; 1921 __ ldrb(rscratch1, Address(rthread, JavaThread::stack_guard_state_offset())); 1922 __ cmp(rscratch1, JavaThread::stack_guard_yellow_disabled); 1923 __ b(reguard, Assembler::EQ); 1924 __ bind(reguard_done); 1925 1926 // native result if any is live 1927 1928 // Unlock 1929 Label unlock_done; 1930 Label slow_path_unlock; 1931 if (method->is_synchronized()) { 1932 // TODO fast path disabled as requires at least 4 registers, but r0,r1 contains result 1933 __ b(slow_path_unlock); 1934 1935 // slow path re-enters here 1936 __ bind(unlock_done); 1937 } 1938 1939 #ifdef DTRACE_ENABLED 1940 { 1941 SkipIfEqual skip(masm, &DTraceMethodProbes, false); 1942 save_native_result(masm, ret_type, stack_slots); 1943 __ mov_metadata(c_rarg1, method()); 1944 __ call_VM_leaf( 1945 CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit), 1946 rthread, c_rarg1); 1947 restore_native_result(masm, ret_type, stack_slots); 1948 } 1949 #endif 1950 1951 __ reset_last_Java_frame(false, true); 1952 1953 // Unpack oop result 1954 if (ret_type == T_OBJECT || ret_type == T_ARRAY) { 1955 Label L; 1956 __ cbz(r0, L); 1957 __ ldr(r0, Address(r0, 0)); 1958 __ bind(L); 1959 __ verify_oop(r0); 1960 } 1961 1962 if (!is_critical_native) { 1963 // reset handle block 1964 __ mov(rscratch1, 0); 1965 __ ldr(r2, Address(rthread, JavaThread::active_handles_offset())); 1966 __ str(rscratch1, Address(r2, JNIHandleBlock::top_offset_in_bytes())); 1967 } 1968 1969 __ leave(); 1970 1971 if (!is_critical_native) { 1972 // Any exception pending? 1973 __ ldr(rscratch1, Address(rthread, in_bytes(Thread::pending_exception_offset()))); 1974 __ cbnz(rscratch1, exception_pending); 1975 } 1976 1977 // We're done 1978 __ b(lr); 1979 1980 // Unexpected paths are out of line and go here 1981 1982 if (!is_critical_native) { 1983 // forward the exception 1984 __ bind(exception_pending); 1985 1986 // and forward the exception 1987 __ far_jump(RuntimeAddress(StubRoutines::forward_exception_entry())); 1988 } 1989 1990 // Slow path locking & unlocking 1991 if (method->is_synchronized()) { 1992 1993 // BEGIN Slow path lock 1994 __ bind(slow_path_lock); 1995 1996 // has last_Java_frame setup. No exceptions so do vanilla call not call_VM 1997 // args are (oop obj, BasicLock* lock, JavaThread* thread) 1998 1999 // protect the args we've loaded 2000 save_args(masm, total_c_args, c_arg, out_regs); 2001 2002 __ ldr(c_rarg0, Address(oop_handle_reg)); 2003 __ lea(c_rarg1, Address(sp, lock_slot_offset * VMRegImpl::stack_slot_size)); 2004 __ mov(c_rarg2, rthread); 2005 2006 // Not a leaf but we have last_Java_frame setup as we want 2007 __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::complete_monitor_locking_C), 3); 2008 restore_args(masm, total_c_args, c_arg, out_regs); 2009 2010 #ifdef ASSERT 2011 { Label L; 2012 __ ldr(rscratch1, Address(rthread, in_bytes(Thread::pending_exception_offset()))); 2013 __ cbz(rscratch1, L); 2014 __ stop("no pending exception allowed on exit from monitorenter"); 2015 __ bind(L); 2016 } 2017 #endif 2018 __ b(lock_done); 2019 2020 // END Slow path lock 2021 2022 // BEGIN Slow path unlock 2023 __ bind(slow_path_unlock); 2024 2025 // If we haven't already saved the native result we must save it now as xmm registers 2026 // are still exposed. 2027 2028 save_native_result(masm, ret_type, stack_slots); 2029 2030 __ ldr(c_rarg0, Address(oop_handle_reg)); 2031 __ lea(c_rarg1, Address(sp, lock_slot_offset * VMRegImpl::stack_slot_size)); 2032 2033 // Save pending exception around call to VM (which contains an EXCEPTION_MARK) 2034 __ ldr(rscratch1, Address(rthread, in_bytes(Thread::pending_exception_offset()))); 2035 __ mov(rscratch2, 0); 2036 __ str(rscratch2, Address(rthread, in_bytes(Thread::pending_exception_offset()))); 2037 2038 rt_call(masm, CAST_FROM_FN_PTR(address, SharedRuntime::complete_monitor_unlocking_C)); 2039 2040 #ifdef ASSERT 2041 { 2042 Label L; 2043 __ ldr(rscratch2, Address(rthread, in_bytes(Thread::pending_exception_offset()))); 2044 __ cbz(rscratch2, L); 2045 __ stop("no pending exception allowed on exit complete_monitor_unlocking_C"); 2046 __ bind(L); 2047 } 2048 #endif // ASSERT 2049 2050 __ str(rscratch1, Address(rthread, in_bytes(Thread::pending_exception_offset()))); 2051 2052 restore_native_result(masm, ret_type, stack_slots); 2053 2054 __ b(unlock_done); 2055 2056 // END Slow path unlock 2057 2058 } // synchronized 2059 2060 // SLOW PATH Reguard the stack if needed 2061 2062 __ bind(reguard); 2063 save_native_result(masm, ret_type, stack_slots); 2064 rt_call(masm, CAST_FROM_FN_PTR(address, SharedRuntime::reguard_yellow_pages)); 2065 restore_native_result(masm, ret_type, stack_slots); 2066 // and continue 2067 __ b(reguard_done); 2068 2069 2070 2071 __ flush(); 2072 2073 nmethod *nm = nmethod::new_native_nmethod(method, 2074 compile_id, 2075 masm->code(), 2076 vep_offset, 2077 frame_complete, 2078 stack_slots / VMRegImpl::slots_per_word, 2079 (is_static ? in_ByteSize(klass_offset) : in_ByteSize(receiver_offset)), 2080 in_ByteSize(lock_slot_offset*VMRegImpl::stack_slot_size), 2081 oop_maps); 2082 2083 if (is_critical_native) { 2084 nm->set_lazy_critical_native(true); 2085 } 2086 2087 return nm; 2088 } 2089 2090 // this function returns the adjust size (in number of words) to a c2i adapter 2091 // activation for use during deoptimization 2092 int Deoptimization::last_frame_adjust(int callee_parameters, int callee_locals) { 2093 assert(callee_locals >= callee_parameters, 2094 "test and remove; got more parms than locals"); 2095 if (callee_locals < callee_parameters) 2096 return 0; // No adjustment for negative locals 2097 int diff = (callee_locals - callee_parameters) * Interpreter::stackElementWords; 2098 // diff is counted in stack words 2099 return round_to(diff, 2); 2100 } 2101 2102 2103 //------------------------------generate_deopt_blob---------------------------- 2104 void SharedRuntime::generate_deopt_blob() { 2105 2106 // Allocate space for the code 2107 ResourceMark rm; 2108 // Setup code generation tools 2109 CodeBuffer buffer("deopt_blob", 2048, 1024); 2110 MacroAssembler* masm = new MacroAssembler(&buffer); 2111 int frame_size_in_words; 2112 OopMap* map = NULL; 2113 OopMapSet *oop_maps = new OopMapSet(); 2114 2115 // ------------- 2116 // This code enters when returning to a de-optimized nmethod. A return 2117 // address has been pushed on the the stack, and return values are in 2118 // registers. 2119 // If we are doing a normal deopt then we were called from the patched 2120 // nmethod from the point we returned to the nmethod. So the return 2121 // address on the stack is wrong by NativeCall::instruction_size 2122 // We will adjust the value so it looks like we have the original return 2123 // address on the stack (like when we eagerly deoptimized). 2124 // In the case of an exception pending when deoptimizing, we enter 2125 // with a return address on the stack that points after the call we patched 2126 // into the exception handler. We have the following register state from, 2127 // e.g., the forward exception stub (see stubGenerator_x86_64.cpp). 2128 // r0: exception oop 2129 // r7: exception handler 2130 // r3: throwing pc 2131 // So in this case we simply jam r3 into the useless return address and 2132 // the stack looks just like we want. 2133 // 2134 // At this point we need to de-opt. We save the argument return 2135 // registers. We call the first C routine, fetch_unroll_info(). This 2136 // routine captures the return values and returns a structure which 2137 // describes the current frame size and the sizes of all replacement frames. 2138 // The current frame is compiled code and may contain many inlined 2139 // functions, each with their own JVM state. We pop the current frame, then 2140 // push all the new frames. Then we call the C routine unpack_frames() to 2141 // populate these frames. Finally unpack_frames() returns us the new target 2142 // address. Notice that callee-save registers are BLOWN here; they have 2143 // already been captured in the vframeArray at the time the return PC was 2144 // patched. 2145 address start = __ pc(); 2146 Label cont; 2147 2148 // Prolog for non exception case! 2149 2150 // Save everything in sight. 2151 map = RegisterSaver::save_live_registers(masm, 0, &frame_size_in_words); 2152 2153 // Normal deoptimization. Save exec mode for unpack_frames. 2154 __ mov(r7, Deoptimization::Unpack_deopt); // callee-saved 2155 __ b(cont); 2156 2157 int reexecute_offset = __ pc() - start; 2158 2159 // Reexecute case 2160 // return address is the pc describes what bci to do re-execute at 2161 2162 // No need to update map as each call to save_live_registers will produce identical oopmap 2163 (void) RegisterSaver::save_live_registers(masm, 0, &frame_size_in_words); 2164 2165 __ mov(r7, Deoptimization::Unpack_reexecute); // callee-saved 2166 __ b(cont); 2167 2168 int exception_offset = __ pc() - start; 2169 2170 // Prolog for exception case 2171 2172 // all registers are dead at this entry point, except for r0, and 2173 // r3 which contain the exception oop and exception pc 2174 // respectively. Set them in TLS and fall thru to the 2175 // unpack_with_exception_in_tls entry point. 2176 2177 __ str(r3, Address(rthread, JavaThread::exception_pc_offset())); 2178 __ str(r0, Address(rthread, JavaThread::exception_oop_offset())); 2179 2180 int exception_in_tls_offset = __ pc() - start; 2181 2182 // new implementation because exception oop is now passed in JavaThread 2183 2184 // Prolog for exception case 2185 // All registers must be preserved because they might be used by LinearScan 2186 // Exceptiop oop and throwing PC are passed in JavaThread 2187 // tos: stack at point of call to method that threw the exception (i.e. only 2188 // args are on the stack, no return address) 2189 2190 // The return address pushed by save_live_registers will be patched 2191 // later with the throwing pc. The correct value is not available 2192 // now because loading it from memory would destroy registers. 2193 2194 // NB: The SP at this point must be the SP of the method that is 2195 // being deoptimized. Deoptimization assumes that the frame created 2196 // here by save_live_registers is immediately below the method's SP. 2197 // This is a somewhat fragile mechanism. 2198 2199 // Save everything in sight. 2200 map = RegisterSaver::save_live_registers(masm, 0, &frame_size_in_words); 2201 2202 // Now it is safe to overwrite any register 2203 2204 // Deopt during an exception. Save exec mode for unpack_frames. 2205 __ mov(r7, Deoptimization::Unpack_exception); // callee-saved 2206 2207 // load throwing pc from JavaThread and patch it as the return address 2208 // of the current frame. Then clear the field in JavaThread 2209 2210 __ ldr(r3, Address(rthread, JavaThread::exception_pc_offset())); 2211 __ str(r3, Address(rfp)); 2212 __ mov(rscratch1, 0); 2213 __ str(rscratch1, Address(rthread, JavaThread::exception_pc_offset())); 2214 2215 #ifdef ASSERT 2216 // verify that there is really an exception oop in JavaThread 2217 __ ldr(r0, Address(rthread, JavaThread::exception_oop_offset())); 2218 __ verify_oop(r0); 2219 2220 // verify that there is no pending exception 2221 Label no_pending_exception; 2222 __ ldr(rscratch1, Address(rthread, Thread::pending_exception_offset())); 2223 __ cbz(rscratch1, no_pending_exception); 2224 __ stop("must not have pending exception here"); 2225 __ bind(no_pending_exception); 2226 #endif 2227 2228 __ bind(cont); 2229 2230 // Call C code. Need thread and this frame, but NOT official VM entry 2231 // crud. We cannot block on this call, no GC can happen. 2232 // 2233 // UnrollBlock* fetch_unroll_info(JavaThread* thread) 2234 2235 // fetch_unroll_info needs to call last_java_frame(). 2236 2237 Label retaddr; 2238 __ set_last_Java_frame(sp, noreg, retaddr, rscratch1); 2239 #ifdef ASSERT0 2240 { Label L; 2241 __ ldr(rscratch1, Address(rthread, 2242 JavaThread::last_Java_fp_offset())); 2243 __ cbz(rscratch1, L); 2244 __ stop("SharedRuntime::generate_deopt_blob: last_Java_fp not cleared"); 2245 __ bind(L); 2246 } 2247 #endif // ASSERT 2248 __ mov(c_rarg0, rthread); 2249 __ lea(rscratch1, RuntimeAddress(CAST_FROM_FN_PTR(address, Deoptimization::fetch_unroll_info))); 2250 __ bl(rscratch1); 2251 __ bind(retaddr); 2252 2253 // Need to have an oopmap that tells fetch_unroll_info where to 2254 // find any register it might need. 2255 oop_maps->add_gc_map(__ pc() - start, map); 2256 2257 __ reset_last_Java_frame(false, true); 2258 2259 // Load UnrollBlock* into rdi 2260 __ mov(r5, r0); 2261 2262 Label noException; 2263 __ cmp(r7, Deoptimization::Unpack_exception); // Was exception pending? 2264 __ b(noException, Assembler::NE); 2265 __ ldr(r0, Address(rthread, JavaThread::exception_oop_offset())); 2266 // QQQ this is useless it was NULL above 2267 __ ldr(r3, Address(rthread, JavaThread::exception_pc_offset())); 2268 __ mov(rscratch1, 0); 2269 __ str(rscratch1, Address(rthread, JavaThread::exception_oop_offset())); 2270 __ str(rscratch1, Address(rthread, JavaThread::exception_pc_offset())); 2271 2272 __ verify_oop(r0); 2273 2274 // Overwrite the result registers with the exception results. 2275 __ str(r0, Address(sp, RegisterSaver::offset_in_bytes(RegisterSaver::r0_off))); 2276 // I think this is useless 2277 // __ str(r3, Address(sp, RegisterSaver::r3_offset_in_bytes())); 2278 2279 __ bind(noException); 2280 2281 // Only register save data is on the stack. 2282 // Now restore the result registers. Everything else is either dead 2283 // or captured in the vframeArray. 2284 RegisterSaver::restore_result_registers(masm); 2285 2286 // All of the register save area has been popped of the stack. Only the 2287 // return address remains. 2288 2289 // Pop all the frames we must move/replace. 2290 // 2291 // Frame picture (youngest to oldest) 2292 // 1: self-frame (no frame link) 2293 // 2: deopting frame (no frame link) 2294 // 3: caller of deopting frame (could be compiled/interpreted). 2295 // 2296 // Note: by leaving the return address of self-frame on the stack 2297 // and using the size of frame 2 to adjust the stack 2298 // when we are done the return to frame 3 will still be on the stack. 2299 2300 // Pop deoptimized frame 2301 __ ldr(r2, Address(r5, Deoptimization::UnrollBlock::size_of_deoptimized_frame_offset_in_bytes())); 2302 __ sub(r2, r2, 2 * wordSize); 2303 __ add(sp, sp, r2); 2304 __ ldrd(rfp, lr, __ post(sp, 2 * wordSize)); 2305 // LR should now be the return address to the caller (3) 2306 2307 #ifdef ASSERT 2308 // Compilers generate code that bang the stack by as much as the 2309 // interpreter would need. So this stack banging should never 2310 // trigger a fault. Verify that it does not on non product builds. 2311 if (UseStackBanging) { 2312 __ ldr(rscratch2, Address(r5, Deoptimization::UnrollBlock::total_frame_sizes_offset_in_bytes())); 2313 __ bang_stack_size(rscratch2, r2); 2314 } 2315 #endif 2316 // Load address of array of frame pcs into r2 2317 __ ldr(r2, Address(r5, Deoptimization::UnrollBlock::frame_pcs_offset_in_bytes())); 2318 2319 // Trash the old pc 2320 // __ addptr(sp, wordSize); FIXME ???? 2321 2322 // Load address of array of frame sizes into r4 2323 __ ldr(r4, Address(r5, Deoptimization::UnrollBlock::frame_sizes_offset_in_bytes())); 2324 2325 // Load counter into r3 2326 __ ldr(r3, Address(r5, Deoptimization::UnrollBlock::number_of_frames_offset_in_bytes())); 2327 2328 // Now adjust the caller's stack to make up for the extra locals 2329 // but record the original sp so that we can save it in the skeletal interpreter 2330 // frame and the stack walking of interpreter_sender will get the unextended sp 2331 // value and not the "real" sp value. 2332 2333 const Register sender_sp = r6; 2334 2335 __ mov(sender_sp, sp); 2336 __ ldr(rscratch1, Address(r5, 2337 Deoptimization::UnrollBlock:: 2338 caller_adjustment_offset_in_bytes())); 2339 __ sub(sp, sp, rscratch1); 2340 2341 // Push interpreter frames in a loop 2342 __ mov(rscratch1, (address)0xDEADDEAD); // Make a recognizable pattern 2343 // Initially used to place 0xDEADDEAD in rscratch2 as well - why? 2344 __ mov(rscratch2, 0); 2345 Label loop; 2346 __ bind(loop); 2347 __ ldr(rscratch1, Address(__ post(r4, wordSize))); // Load frame size 2348 __ sub(rscratch1, rscratch1, 2*wordSize); // We'll push pc and fp by hand 2349 __ ldr(lr, Address(__ post(r2, wordSize))); // Load pc 2350 __ enter(); // Save old & set new fp 2351 __ sub(sp, sp, rscratch1); // Prolog 2352 // This value is corrected by layout_activation_impl 2353 __ str(rscratch2, Address(rfp, frame::interpreter_frame_last_sp_offset * wordSize)); 2354 __ str(sender_sp, Address(rfp, frame::interpreter_frame_sender_sp_offset * wordSize)); // Make it walkable 2355 __ mov(sender_sp, sp); // Pass sender_sp to next frame 2356 __ sub(r3, r3, 1); // Decrement counter 2357 __ cbnz(r3, loop); 2358 2359 // Re-push self-frame 2360 __ ldr(lr, Address(r2)); 2361 __ enter(); 2362 2363 // Allocate a full sized register save area. We subtract 2 because 2364 // enter() just pushed 2 words 2365 __ sub(sp, sp, (frame_size_in_words - 2) * wordSize); 2366 2367 // Restore frame locals after moving the frame 2368 __ vstr_f64(d0, Address(sp, RegisterSaver::offset_in_bytes(RegisterSaver::fpu_state_off))); 2369 __ strd(r0, Address(sp, RegisterSaver::offset_in_bytes(RegisterSaver::r0_off))); 2370 2371 // Call C code. Need thread but NOT official VM entry 2372 // crud. We cannot block on this call, no GC can happen. Call should 2373 // restore return values to their stack-slots with the new SP. 2374 // 2375 // void Deoptimization::unpack_frames(JavaThread* thread, int exec_mode) 2376 2377 // Use rfp because the frames look interpreted now 2378 // Don't need the precise return PC here, just precise enough to point into this code blob. 2379 address the_pc = __ pc(); 2380 __ set_last_Java_frame(sp, rfp, the_pc, rscratch1); 2381 2382 __ mov(c_rarg0, rthread); 2383 __ mov(c_rarg1, r7); // second arg: exec_mode 2384 __ lea(rscratch1, RuntimeAddress(CAST_FROM_FN_PTR(address, Deoptimization::unpack_frames))); 2385 __ bl(rscratch1); 2386 2387 // Set an oopmap for the call site 2388 // Use the same PC we used for the last java frame 2389 oop_maps->add_gc_map(the_pc - start, 2390 new OopMap( frame_size_in_words, 0 )); 2391 2392 // Clear fp AND pc 2393 __ reset_last_Java_frame(true, true); 2394 2395 // Collect return values 2396 __ vldr_f64(d0, Address(sp, RegisterSaver::offset_in_bytes(RegisterSaver::fpu_state_off))); 2397 __ ldrd(r0, Address(sp, RegisterSaver::offset_in_bytes(RegisterSaver::r0_off))); 2398 // I think this is useless (throwing pc?) 2399 // __ ldr(r3, Address(sp, RegisterSaver::r3_offset_in_bytes())); 2400 2401 // Pop self-frame. 2402 __ leave(); // Epilog 2403 2404 // Jump to interpreter 2405 __ b(lr); 2406 2407 // Make sure all code is generated 2408 masm->flush(); 2409 2410 _deopt_blob = DeoptimizationBlob::create(&buffer, oop_maps, 0, exception_offset, reexecute_offset, frame_size_in_words); 2411 _deopt_blob->set_unpack_with_exception_in_tls_offset(exception_in_tls_offset); 2412 2413 } 2414 2415 uint SharedRuntime::out_preserve_stack_slots() { 2416 return 0; 2417 } 2418 2419 #ifdef COMPILER2 2420 //------------------------------generate_uncommon_trap_blob-------------------- 2421 /*void SharedRuntime::generate_uncommon_trap_blob() { 2422 // Allocate space for the code 2423 ResourceMark rm; 2424 // Setup code generation tools 2425 CodeBuffer buffer("uncommon_trap_blob", 2048, 1024); 2426 MacroAssembler* masm = new MacroAssembler(&buffer); 2427 2428 assert(SimpleRuntimeFrame::framesize % 4 == 0, "sp not 16-byte aligned"); 2429 2430 address start = __ pc(); 2431 2432 // Push self-frame. We get here with a return address in LR 2433 // and sp should be 16 byte aligned 2434 // push rfp and retaddr by hand 2435 __ strd(rfp, lr, Address(__ pre(sp, -2 * wordSize))); 2436 // we don't expect an arg reg save area 2437 #ifndef PRODUCT 2438 assert(frame::arg_reg_save_area_bytes == 0, "not expecting frame reg save area"); 2439 #endif 2440 // compiler left unloaded_class_index in j_rarg0 move to where the 2441 // runtime expects it. 2442 if (c_rarg1 != j_rarg0) { 2443 __ mov(c_rarg1, j_rarg0); 2444 } 2445 2446 // we need to set the past SP to the stack pointer of the stub frame 2447 // and the pc to the address where this runtime call will return 2448 // although actually any pc in this code blob will do). 2449 Label retaddr; 2450 __ set_last_Java_frame(sp, noreg, retaddr, rscratch1); 2451 2452 // Call C code. Need thread but NOT official VM entry 2453 // crud. We cannot block on this call, no GC can happen. Call should 2454 // capture callee-saved registers as well as return values. 2455 // Thread is in rdi already. 2456 // 2457 // UnrollBlock* uncommon_trap(JavaThread* thread, jint unloaded_class_index); 2458 // 2459 // n.b. 2 gp args, 0 fp args, integral return type 2460 2461 __ mov(c_rarg0, rthread); 2462 __ lea(rscratch1, 2463 RuntimeAddress(CAST_FROM_FN_PTR(address, 2464 Deoptimization::uncommon_trap))); 2465 __ bl(rscratch1); 2466 __ bind(retaddr); 2467 2468 // Set an oopmap for the call site 2469 OopMapSet* oop_maps = new OopMapSet(); 2470 OopMap* map = new OopMap(SimpleRuntimeFrame::framesize, 0); 2471 2472 // location of rfp is known implicitly by the frame sender code 2473 2474 oop_maps->add_gc_map(__ pc() - start, map); 2475 2476 __ reset_last_Java_frame(false, true); 2477 2478 // move UnrollBlock* into r4 2479 __ mov(r4, r0); 2480 2481 // Pop all the frames we must move/replace. 2482 // 2483 // Frame picture (youngest to oldest) 2484 // 1: self-frame (no frame link) 2485 // 2: deopting frame (no frame link) 2486 // 3: caller of deopting frame (could be compiled/interpreted). 2487 2488 // Pop self-frame. We have no frame, and must rely only on r0 and sp. 2489 __ add(sp, sp, (SimpleRuntimeFrame::framesize) << LogBytesPerInt); // Epilog! 2490 2491 // Pop deoptimized frame (int) 2492 __ ldr(r2, Address(r4, 2493 Deoptimization::UnrollBlock:: 2494 size_of_deoptimized_frame_offset_in_bytes())); 2495 __ sub(r2, r2, 2 * wordSize); 2496 __ add(sp, sp, r2); 2497 __ ldrd(rfp, lr, __ post(sp, 2 * wordSize)); 2498 // LR should now be the return address to the caller (3) frame 2499 2500 #ifdef ASSERT 2501 // Compilers generate code that bang the stack by as much as the 2502 // interpreter would need. So this stack banging should never 2503 // trigger a fault. Verify that it does not on non product builds. 2504 if (UseStackBanging) { 2505 __ ldr(r1, Address(r4, 2506 Deoptimization::UnrollBlock:: 2507 total_frame_sizes_offset_in_bytes())); 2508 __ bang_stack_size(r1, r2); 2509 } 2510 #endif 2511 2512 // Load address of array of frame pcs into r2 (address*) 2513 __ ldr(r2, Address(r4, 2514 Deoptimization::UnrollBlock::frame_pcs_offset_in_bytes())); 2515 2516 // Load address of array of frame sizes into r5 (intptr_t*) 2517 __ ldr(r5, Address(r4, 2518 Deoptimization::UnrollBlock:: 2519 frame_sizes_offset_in_bytes())); 2520 2521 // Counter 2522 __ ldr(r3, Address(r4, 2523 Deoptimization::UnrollBlock:: 2524 number_of_frames_offset_in_bytes())); // (int) 2525 2526 // Now adjust the caller's stack to make up for the extra locals but 2527 // record the original sp so that we can save it in the skeletal 2528 // interpreter frame and the stack walking of interpreter_sender 2529 // will get the unextended sp value and not the "real" sp value. 2530 2531 const Register sender_sp = r8; 2532 2533 __ mov(sender_sp, sp); 2534 __ ldr(r1, Address(r4, 2535 Deoptimization::UnrollBlock:: 2536 caller_adjustment_offset_in_bytes())); // (int) 2537 __ sub(sp, sp, r1); 2538 2539 __ mov(rscratch1, 0); 2540 // Push interpreter frames in a loop 2541 Label loop; 2542 __ bind(loop); 2543 __ ldr(r1, Address(r5, 0)); // Load frame size 2544 __ sub(r1, r1, 2 * wordSize); // We'll push pc and rfp by hand 2545 __ ldr(lr, Address(r2, 0)); // Save return address 2546 __ enter(); // and old rfp & set new rfp 2547 __ sub(sp, sp, r1); // Prolog 2548 __ str(sender_sp, Address(rfp, frame::interpreter_frame_sender_sp_offset * wordSize)); // Make it walkable 2549 // This value is corrected by layout_activation_impl 2550 __ str(rscratch1, Address(rfp, frame::interpreter_frame_last_sp_offset * wordSize)); //zero it 2551 __ mov(sender_sp, sp); // Pass sender_sp to next frame 2552 __ add(r5, r5, wordSize); // Bump array pointer (sizes) 2553 __ add(r2, r2, wordSize); // Bump array pointer (pcs) 2554 __ subs(r3, r3, 1); // Decrement counter 2555 __ b(loop, Assembler::GT); 2556 __ ldr(lr, Address(r2, 0)); // save final return address 2557 // Re-push self-frame 2558 __ enter(); // & old rfp & set new rfp 2559 2560 // Use rfp because the frames look interpreted now 2561 // Save "the_pc" since it cannot easily be retrieved using the last_java_SP after we aligned SP. 2562 // Don't need the precise return PC here, just precise enough to point into this code blob. 2563 address the_pc = __ pc(); 2564 __ set_last_Java_frame(sp, rfp, the_pc, rscratch1); 2565 2566 // Call C code. Need thread but NOT official VM entry 2567 // crud. We cannot block on this call, no GC can happen. Call should 2568 // restore return values to their stack-slots with the new SP. 2569 // Thread is in rdi already. 2570 // 2571 // BasicType unpack_frames(JavaThread* thread, int exec_mode); 2572 // 2573 // n.b. 2 gp args, 0 fp args, integral return type 2574 2575 // sp should already be aligned 2576 __ mov(c_rarg0, rthread); 2577 __ mov(c_rarg1, (unsigned)Deoptimization::Unpack_uncommon_trap); 2578 __ lea(rscratch1, RuntimeAddress(CAST_FROM_FN_PTR(address, Deoptimization::unpack_frames))); 2579 __ bl(rscratch1); 2580 2581 // Set an oopmap for the call site 2582 // Use the same PC we used for the last java frame 2583 oop_maps->add_gc_map(the_pc - start, new OopMap(SimpleRuntimeFrame::framesize, 0)); 2584 2585 // Clear fp AND pc 2586 __ reset_last_Java_frame(true, true); 2587 2588 // Pop self-frame. 2589 __ leave(); // Epilog 2590 2591 // Jump to interpreter 2592 __ b(lr); 2593 2594 // Make sure all code is generated 2595 masm->flush(); 2596 2597 _uncommon_trap_blob = UncommonTrapBlob::create(&buffer, oop_maps, 2598 SimpleRuntimeFrame::framesize >> 1); 2599 2600 } */ 2601 #endif // COMPILER2 2602 2603 2604 //------------------------------generate_handler_blob------ 2605 // 2606 // Generate a special Compile2Runtime blob that saves all registers, 2607 // and setup oopmap. 2608 // 2609 SafepointBlob* SharedRuntime::generate_handler_blob(address call_ptr, int poll_type) { 2610 ResourceMark rm; 2611 OopMapSet *oop_maps = new OopMapSet(); 2612 OopMap* map; 2613 2614 // Allocate space for the code. Setup code generation tools. 2615 CodeBuffer buffer("handler_blob", 2048, 1024); 2616 MacroAssembler* masm = new MacroAssembler(&buffer); 2617 2618 address start = __ pc(); 2619 address call_pc = NULL; 2620 int frame_size_in_words; 2621 bool cause_return = (poll_type == POLL_AT_RETURN); 2622 bool save_vectors = (poll_type == POLL_AT_VECTOR_LOOP); 2623 2624 // Save registers, fpu state, and flags 2625 map = RegisterSaver::save_live_registers(masm, 0, &frame_size_in_words); 2626 2627 // The following is basically a call_VM. However, we need the precise 2628 // address of the call in order to generate an oopmap. Hence, we do all the 2629 // work outselves. 2630 2631 Label retaddr; 2632 __ set_last_Java_frame(sp, noreg, retaddr, rscratch1); 2633 2634 // The return address must always be correct so that frame constructor never 2635 // sees an invalid pc. 2636 2637 if (!cause_return) { 2638 // overwrite the return address pushed by save_live_registers 2639 __ ldr(lr, Address(rthread, JavaThread::saved_exception_pc_offset())); 2640 __ str(lr, Address(rfp)); 2641 } 2642 2643 // Do the call 2644 __ mov(c_rarg0, rthread); 2645 __ lea(rscratch1, RuntimeAddress(call_ptr)); 2646 __ bl(rscratch1); 2647 __ bind(retaddr); 2648 2649 // Set an oopmap for the call site. This oopmap will map all 2650 // oop-registers and debug-info registers as callee-saved. This 2651 // will allow deoptimization at this safepoint to find all possible 2652 // debug-info recordings, as well as let GC find all oops. 2653 2654 oop_maps->add_gc_map( __ pc() - start, map); 2655 2656 Label noException; 2657 2658 __ reset_last_Java_frame(false, true); 2659 2660 __ maybe_isb(); 2661 __ membar(Assembler::LoadLoad | Assembler::LoadStore); 2662 2663 __ ldr(rscratch1, Address(rthread, Thread::pending_exception_offset())); 2664 __ cbz(rscratch1, noException); 2665 2666 // Exception pending 2667 2668 RegisterSaver::restore_live_registers(masm); 2669 2670 __ far_jump(RuntimeAddress(StubRoutines::forward_exception_entry())); 2671 2672 // No exception case 2673 __ bind(noException); 2674 2675 // Normal exit, restore registers and exit. 2676 RegisterSaver::restore_live_registers(masm); 2677 2678 __ b(lr); 2679 2680 // Make sure all code is generated 2681 masm->flush(); 2682 2683 // Fill-out other meta info 2684 return SafepointBlob::create(&buffer, oop_maps, frame_size_in_words); 2685 } 2686 2687 // 2688 // generate_resolve_blob - call resolution (static/virtual/opt-virtual/ic-miss 2689 // 2690 // Generate a stub that calls into vm to find out the proper destination 2691 // of a java call. All the argument registers are live at this point 2692 // but since this is generic code we don't know what they are and the caller 2693 // must do any gc of the args. 2694 // 2695 RuntimeStub* SharedRuntime::generate_resolve_blob(address destination, const char* name) { 2696 assert (StubRoutines::forward_exception_entry() != NULL, "must be generated before"); 2697 2698 // allocate space for the code 2699 ResourceMark rm; 2700 2701 //CodeBuffer buffer(name, 1000, 512); 2702 CodeBuffer buffer(name, 2048, 512 ); // changed as error later 2703 MacroAssembler* masm = new MacroAssembler(&buffer); 2704 2705 int frame_size_in_words; 2706 2707 OopMapSet *oop_maps = new OopMapSet(); 2708 OopMap* map = NULL; 2709 2710 int start = __ offset(); 2711 2712 map = RegisterSaver::save_live_registers(masm, 0, &frame_size_in_words); 2713 2714 int frame_complete = __ offset(); 2715 2716 { 2717 Label retaddr; 2718 __ set_last_Java_frame(sp, noreg, retaddr, rscratch1); 2719 2720 __ mov(c_rarg0, rthread); 2721 __ lea(rscratch1, RuntimeAddress(destination)); 2722 2723 __ bl(rscratch1); 2724 __ bind(retaddr); 2725 } 2726 2727 // Set an oopmap for the call site. 2728 // We need this not only for callee-saved registers, but also for volatile 2729 // registers that the compiler might be keeping live across a safepoint. 2730 2731 oop_maps->add_gc_map( __ offset() - start, map); 2732 2733 __ maybe_isb(); 2734 2735 // r0 contains the address we are going to jump to assuming no exception got installed 2736 2737 // clear last_Java_sp 2738 // TODO x86 have different action: reset_last_Java_frame(thread, true(fp), false(pc)); 2739 // TODO below is false(fp), true(pc) 2740 __ reset_last_Java_frame(false, true); 2741 // check for pending exceptions 2742 Label pending; 2743 __ ldr(rscratch1, Address(rthread, Thread::pending_exception_offset())); 2744 __ cbnz(rscratch1, pending); 2745 2746 // get the returned Method* 2747 __ get_vm_result_2(rmethod, rthread); 2748 __ str(rmethod, Address(sp, RegisterSaver::offset_in_bytes(RegisterSaver::rmethod_off))); 2749 2750 // r0 is where we want to jump, overwrite rscratch1 which is saved and scratch 2751 __ str(r0, Address(sp, RegisterSaver::offset_in_bytes(RegisterSaver::rscratch1_off))); 2752 RegisterSaver::restore_live_registers(masm); 2753 2754 // We are back the the original state on entry and ready to go. 2755 2756 __ b(rscratch1); 2757 2758 // Pending exception after the safepoint 2759 2760 __ bind(pending); 2761 2762 RegisterSaver::restore_live_registers(masm); 2763 2764 // exception pending => remove activation and forward to exception handler 2765 __ mov(rscratch1, 0); 2766 __ str(rscratch1, Address(rthread, JavaThread::vm_result_offset())); 2767 2768 __ ldr(r0, Address(rthread, Thread::pending_exception_offset())); 2769 __ far_jump(RuntimeAddress(StubRoutines::forward_exception_entry())); 2770 2771 // ------------- 2772 // make sure all code is generated 2773 masm->flush(); 2774 2775 // return the blob 2776 // frame_size_words or bytes?? 2777 return RuntimeStub::new_runtime_stub(name, &buffer, frame_complete, frame_size_in_words, oop_maps, true); 2778 } 2779 2780 2781 #ifdef COMPILER2 2782 // This is here instead of runtime_x86_64.cpp because it uses SimpleRuntimeFrame 2783 // 2784 //------------------------------generate_exception_blob--------------------------- 2785 // creates exception blob at the end 2786 // Using exception blob, this code is jumped from a compiled method. 2787 // (see emit_exception_handler in x86_64.ad file) 2788 // 2789 // Given an exception pc at a call we call into the runtime for the 2790 // handler in this method. This handler might merely restore state 2791 // (i.e. callee save registers) unwind the frame and jump to the 2792 // exception handler for the nmethod if there is no Java level handler 2793 // for the nmethod. 2794 // 2795 // This code is entered with a jmp. 2796 // 2797 // Arguments: 2798 // r0: exception oop 2799 // r3: exception pc 2800 // 2801 // Results: 2802 // r0: exception oop 2803 // r3: exception pc in caller or ??? 2804 // destination: exception handler of caller 2805 // 2806 // Note: the exception pc MUST be at a call (precise debug information) 2807 // Registers r0, r3, r2, r4, r5, r8-r11 are not callee saved. 2808 // 2809 2810 void OptoRuntime::generate_exception_blob() { 2811 assert(!OptoRuntime::is_callee_saved_register(R3_num), ""); 2812 assert(!OptoRuntime::is_callee_saved_register(R0_num), ""); 2813 assert(!OptoRuntime::is_callee_saved_register(R2_num), ""); 2814 2815 assert(SimpleRuntimeFrame::framesize % 4 == 0, "sp not 16-byte aligned"); 2816 2817 // Allocate space for the code 2818 ResourceMark rm; 2819 // Setup code generation tools 2820 CodeBuffer buffer("exception_blob", 2048, 1024); 2821 MacroAssembler* masm = new MacroAssembler(&buffer); 2822 2823 __ stop("FIXME generate_exception_blob"); 2824 // TODO check various assumptions made here 2825 // 2826 // make sure we do so before running this 2827 2828 address start = __ pc(); 2829 2830 // push rfp and retaddr by hand 2831 // Exception pc is 'return address' for stack walker 2832 __ strd(rfp, lr, Address(__ pre(sp, -2 * wordSize))); 2833 // there are no callee save registers and we don't expect an 2834 // arg reg save area 2835 #ifndef PRODUCT 2836 assert(frame::arg_reg_save_area_bytes == 0, "not expecting frame reg save area"); 2837 #endif 2838 // Store exception in Thread object. We cannot pass any arguments to the 2839 // handle_exception call, since we do not want to make any assumption 2840 // about the size of the frame where the exception happened in. 2841 __ str(r0, Address(rthread, JavaThread::exception_oop_offset())); 2842 __ str(r3, Address(rthread, JavaThread::exception_pc_offset())); 2843 2844 // This call does all the hard work. It checks if an exception handler 2845 // exists in the method. 2846 // If so, it returns the handler address. 2847 // If not, it prepares for stack-unwinding, restoring the callee-save 2848 // registers of the frame being removed. 2849 // 2850 // address OptoRuntime::handle_exception_C(JavaThread* thread) 2851 // 2852 // n.b. 1 gp arg, 0 fp args, integral return type 2853 2854 // the stack should always be aligned 2855 address the_pc = __ pc(); 2856 __ set_last_Java_frame(sp, noreg, the_pc, rscratch1); 2857 __ mov(c_rarg0, rthread); 2858 __ lea(rscratch1, RuntimeAddress(CAST_FROM_FN_PTR(address, OptoRuntime::handle_exception_C))); 2859 __ bl(rscratch1); 2860 __ maybe_isb(); 2861 2862 // Set an oopmap for the call site. This oopmap will only be used if we 2863 // are unwinding the stack. Hence, all locations will be dead. 2864 // Callee-saved registers will be the same as the frame above (i.e., 2865 // handle_exception_stub), since they were restored when we got the 2866 // exception. 2867 2868 OopMapSet* oop_maps = new OopMapSet(); 2869 2870 oop_maps->add_gc_map(the_pc - start, new OopMap(SimpleRuntimeFrame::framesize, 0)); 2871 2872 __ reset_last_Java_frame(false, true); 2873 2874 // Restore callee-saved registers 2875 2876 // rfp is an implicitly saved callee saved register (i.e. the calling 2877 // convention will save restore it in prolog/epilog) Other than that 2878 // there are no callee save registers now that adapter frames are gone. 2879 // and we dont' expect an arg reg save area 2880 __ ldrd(rfp, r3, Address(__ post(sp, 2 * wordSize))); 2881 2882 // r0: exception handler 2883 2884 // We have a handler in r0 (could be deopt blob). 2885 __ mov(r8, r0); 2886 2887 // Get the exception oop 2888 __ ldr(r0, Address(rthread, JavaThread::exception_oop_offset())); 2889 // Get the exception pc in case we are deoptimized 2890 __ ldr(r4, Address(rthread, JavaThread::exception_pc_offset())); 2891 __ mov(rscratch1, 0); 2892 #ifdef ASSERT 2893 __ str(rscratch1, Address(rthread, JavaThread::exception_handler_pc_offset())); 2894 __ str(rscratch1, Address(rthread, JavaThread::exception_pc_offset())); 2895 #endif 2896 // Clear the exception oop so GC no longer processes it as a root. 2897 __ str(rscratch1, Address(rthread, JavaThread::exception_oop_offset())); 2898 2899 // r0: exception oop 2900 // r8: exception handler 2901 // r4: exception pc 2902 // Jump to handler 2903 2904 __ b(r8); 2905 2906 // Make sure all code is generated 2907 masm->flush(); 2908 2909 // Set exception blob 2910 _exception_blob = ExceptionBlob::create(&buffer, oop_maps, SimpleRuntimeFrame::framesize >> 1); 2911 } 2912 #endif // COMPILER2