rev 8069 : 8164652: aarch32: C1 port
602 return (LIR_Opr)(intptr_t)((reg << LIR_OprDesc::reg1_shift) |
603 LIR_OprDesc::metadata_type |
604 LIR_OprDesc::cpu_register |
605 LIR_OprDesc::single_size);
606 }
607 static LIR_Opr double_cpu(int reg1, int reg2) {
608 LP64_ONLY(assert(reg1 == reg2, "must be identical"));
609 return (LIR_Opr)(intptr_t)((reg1 << LIR_OprDesc::reg1_shift) |
610 (reg2 << LIR_OprDesc::reg2_shift) |
611 LIR_OprDesc::long_type |
612 LIR_OprDesc::cpu_register |
613 LIR_OprDesc::double_size);
614 }
615
616 static LIR_Opr single_fpu(int reg) { return (LIR_Opr)(intptr_t)((reg << LIR_OprDesc::reg1_shift) |
617 LIR_OprDesc::float_type |
618 LIR_OprDesc::fpu_register |
619 LIR_OprDesc::single_size); }
620 #if defined(C1_LIR_MD_HPP)
621 # include C1_LIR_MD_HPP
622 #elif defined(SPARC)
623 static LIR_Opr double_fpu(int reg1, int reg2) { return (LIR_Opr)(intptr_t)((reg1 << LIR_OprDesc::reg1_shift) |
624 (reg2 << LIR_OprDesc::reg2_shift) |
625 LIR_OprDesc::double_type |
626 LIR_OprDesc::fpu_register |
627 LIR_OprDesc::double_size); }
628 #elif defined(X86)
629 static LIR_Opr double_fpu(int reg) { return (LIR_Opr)(intptr_t)((reg << LIR_OprDesc::reg1_shift) |
630 (reg << LIR_OprDesc::reg2_shift) |
631 LIR_OprDesc::double_type |
632 LIR_OprDesc::fpu_register |
633 LIR_OprDesc::double_size); }
634
635 static LIR_Opr single_xmm(int reg) { return (LIR_Opr)(intptr_t)((reg << LIR_OprDesc::reg1_shift) |
636 LIR_OprDesc::float_type |
637 LIR_OprDesc::fpu_register |
638 LIR_OprDesc::single_size |
639 LIR_OprDesc::is_xmm_mask); }
640 static LIR_Opr double_xmm(int reg) { return (LIR_Opr)(intptr_t)((reg << LIR_OprDesc::reg1_shift) |
641 (reg << LIR_OprDesc::reg2_shift) |
642 LIR_OprDesc::double_type |
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602 return (LIR_Opr)(intptr_t)((reg << LIR_OprDesc::reg1_shift) |
603 LIR_OprDesc::metadata_type |
604 LIR_OprDesc::cpu_register |
605 LIR_OprDesc::single_size);
606 }
607 static LIR_Opr double_cpu(int reg1, int reg2) {
608 LP64_ONLY(assert(reg1 == reg2, "must be identical"));
609 return (LIR_Opr)(intptr_t)((reg1 << LIR_OprDesc::reg1_shift) |
610 (reg2 << LIR_OprDesc::reg2_shift) |
611 LIR_OprDesc::long_type |
612 LIR_OprDesc::cpu_register |
613 LIR_OprDesc::double_size);
614 }
615
616 static LIR_Opr single_fpu(int reg) { return (LIR_Opr)(intptr_t)((reg << LIR_OprDesc::reg1_shift) |
617 LIR_OprDesc::float_type |
618 LIR_OprDesc::fpu_register |
619 LIR_OprDesc::single_size); }
620 #if defined(C1_LIR_MD_HPP)
621 # include C1_LIR_MD_HPP
622 #elif defined(SPARC) || defined(AARCH32)
623 static LIR_Opr double_fpu(int reg1, int reg2) { return (LIR_Opr)(intptr_t)((reg1 << LIR_OprDesc::reg1_shift) |
624 (reg2 << LIR_OprDesc::reg2_shift) |
625 LIR_OprDesc::double_type |
626 LIR_OprDesc::fpu_register |
627 LIR_OprDesc::double_size); }
628 #elif defined(X86)
629 static LIR_Opr double_fpu(int reg) { return (LIR_Opr)(intptr_t)((reg << LIR_OprDesc::reg1_shift) |
630 (reg << LIR_OprDesc::reg2_shift) |
631 LIR_OprDesc::double_type |
632 LIR_OprDesc::fpu_register |
633 LIR_OprDesc::double_size); }
634
635 static LIR_Opr single_xmm(int reg) { return (LIR_Opr)(intptr_t)((reg << LIR_OprDesc::reg1_shift) |
636 LIR_OprDesc::float_type |
637 LIR_OprDesc::fpu_register |
638 LIR_OprDesc::single_size |
639 LIR_OprDesc::is_xmm_mask); }
640 static LIR_Opr double_xmm(int reg) { return (LIR_Opr)(intptr_t)((reg << LIR_OprDesc::reg1_shift) |
641 (reg << LIR_OprDesc::reg2_shift) |
642 LIR_OprDesc::double_type |
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