1 /* 2 * Copyright (c) 2005, 2015, Oracle and/or its affiliates. All rights reserved. 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 4 * 5 * This code is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 only, as 7 * published by the Free Software Foundation. 8 * 9 * This code is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * version 2 for more details (a copy is included in the LICENSE file that 13 * accompanied this code). 14 * 15 * You should have received a copy of the GNU General Public License version 16 * 2 along with this work; if not, write to the Free Software Foundation, 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 18 * 19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 20 * or visit www.oracle.com if you need additional information or have any 21 * questions. 22 * 23 */ 24 25 #include "precompiled.hpp" 26 #include "c1/c1_CFGPrinter.hpp" 27 #include "c1/c1_CodeStubs.hpp" 28 #include "c1/c1_Compilation.hpp" 29 #include "c1/c1_FrameMap.hpp" 30 #include "c1/c1_IR.hpp" 31 #include "c1/c1_LIRGenerator.hpp" 32 #include "c1/c1_LinearScan.hpp" 33 #include "c1/c1_ValueStack.hpp" 34 #include "utilities/bitMap.inline.hpp" 35 #ifdef TARGET_ARCH_x86 36 # include "vmreg_x86.inline.hpp" 37 #endif 38 #ifdef TARGET_ARCH_sparc 39 # include "vmreg_sparc.inline.hpp" 40 #endif 41 #ifdef TARGET_ARCH_zero 42 # include "vmreg_zero.inline.hpp" 43 #endif 44 #ifdef TARGET_ARCH_arm 45 # include "vmreg_arm.inline.hpp" 46 #endif 47 #ifdef TARGET_ARCH_ppc 48 # include "vmreg_ppc.inline.hpp" 49 #endif 50 #ifdef TARGET_ARCH_aarch32 51 # include "vmreg_aarch32.inline.hpp" 52 #endif 53 54 55 #ifndef PRODUCT 56 57 static LinearScanStatistic _stat_before_alloc; 58 static LinearScanStatistic _stat_after_asign; 59 static LinearScanStatistic _stat_final; 60 61 static LinearScanTimers _total_timer; 62 63 // helper macro for short definition of timer 64 #define TIME_LINEAR_SCAN(timer_name) TraceTime _block_timer("", _total_timer.timer(LinearScanTimers::timer_name), TimeLinearScan || TimeEachLinearScan, Verbose); 65 66 // helper macro for short definition of trace-output inside code 67 #define TRACE_LINEAR_SCAN(level, code) \ 68 if (TraceLinearScanLevel >= level) { \ 69 code; \ 70 } 71 72 #else 73 74 #define TIME_LINEAR_SCAN(timer_name) 75 #define TRACE_LINEAR_SCAN(level, code) 76 77 #endif 78 79 // Map BasicType to spill size in 32-bit words, matching VMReg's notion of words 80 #ifdef _LP64 81 static int type2spill_size[T_CONFLICT+1]={ -1, 0, 0, 0, 1, 1, 1, 2, 1, 1, 1, 2, 2, 2, 0, 2, 1, 2, 1, -1}; 82 #else 83 static int type2spill_size[T_CONFLICT+1]={ -1, 0, 0, 0, 1, 1, 1, 2, 1, 1, 1, 2, 1, 1, 0, 1, -1, 1, 1, -1}; 84 #endif 85 86 87 // Implementation of LinearScan 88 89 LinearScan::LinearScan(IR* ir, LIRGenerator* gen, FrameMap* frame_map) 90 : _compilation(ir->compilation()) 91 , _ir(ir) 92 , _gen(gen) 93 , _frame_map(frame_map) 94 , _num_virtual_regs(gen->max_virtual_register_number()) 95 , _has_fpu_registers(false) 96 , _num_calls(-1) 97 , _max_spills(0) 98 , _unused_spill_slot(-1) 99 , _intervals(0) // initialized later with correct length 100 , _new_intervals_from_allocation(new IntervalList()) 101 , _sorted_intervals(NULL) 102 , _needs_full_resort(false) 103 , _lir_ops(0) // initialized later with correct length 104 , _block_of_op(0) // initialized later with correct length 105 , _has_info(0) 106 , _has_call(0) 107 , _scope_value_cache(0) // initialized later with correct length 108 , _interval_in_loop(0, 0) // initialized later with correct length 109 , _cached_blocks(*ir->linear_scan_order()) 110 #ifdef X86 111 , _fpu_stack_allocator(NULL) 112 #endif 113 { 114 assert(this->ir() != NULL, "check if valid"); 115 assert(this->compilation() != NULL, "check if valid"); 116 assert(this->gen() != NULL, "check if valid"); 117 assert(this->frame_map() != NULL, "check if valid"); 118 } 119 120 121 // ********** functions for converting LIR-Operands to register numbers 122 // 123 // Emulate a flat register file comprising physical integer registers, 124 // physical floating-point registers and virtual registers, in that order. 125 // Virtual registers already have appropriate numbers, since V0 is 126 // the number of physical registers. 127 // Returns -1 for hi word if opr is a single word operand. 128 // 129 // Note: the inverse operation (calculating an operand for register numbers) 130 // is done in calc_operand_for_interval() 131 132 int LinearScan::reg_num(LIR_Opr opr) { 133 assert(opr->is_register(), "should not call this otherwise"); 134 135 if (opr->is_virtual_register()) { 136 assert(opr->vreg_number() >= nof_regs, "found a virtual register with a fixed-register number"); 137 return opr->vreg_number(); 138 } else if (opr->is_single_cpu()) { 139 return opr->cpu_regnr(); 140 } else if (opr->is_double_cpu()) { 141 return opr->cpu_regnrLo(); 142 #ifdef X86 143 } else if (opr->is_single_xmm()) { 144 return opr->fpu_regnr() + pd_first_xmm_reg; 145 } else if (opr->is_double_xmm()) { 146 return opr->fpu_regnrLo() + pd_first_xmm_reg; 147 #endif 148 } else if (opr->is_single_fpu()) { 149 return opr->fpu_regnr() + pd_first_fpu_reg; 150 } else if (opr->is_double_fpu()) { 151 return opr->fpu_regnrLo() + pd_first_fpu_reg; 152 } else { 153 ShouldNotReachHere(); 154 return -1; 155 } 156 } 157 158 int LinearScan::reg_numHi(LIR_Opr opr) { 159 assert(opr->is_register(), "should not call this otherwise"); 160 161 if (opr->is_virtual_register()) { 162 return -1; 163 } else if (opr->is_single_cpu()) { 164 return -1; 165 } else if (opr->is_double_cpu()) { 166 return opr->cpu_regnrHi(); 167 #ifdef X86 168 } else if (opr->is_single_xmm()) { 169 return -1; 170 } else if (opr->is_double_xmm()) { 171 return -1; 172 #endif 173 } else if (opr->is_single_fpu()) { 174 return -1; 175 } else if (opr->is_double_fpu()) { 176 return opr->fpu_regnrHi() + pd_first_fpu_reg; 177 } else { 178 ShouldNotReachHere(); 179 return -1; 180 } 181 } 182 183 184 // ********** functions for classification of intervals 185 186 bool LinearScan::is_precolored_interval(const Interval* i) { 187 return i->reg_num() < LinearScan::nof_regs; 188 } 189 190 bool LinearScan::is_virtual_interval(const Interval* i) { 191 return i->reg_num() >= LIR_OprDesc::vreg_base; 192 } 193 194 bool LinearScan::is_precolored_cpu_interval(const Interval* i) { 195 return i->reg_num() < LinearScan::nof_cpu_regs; 196 } 197 198 bool LinearScan::is_virtual_cpu_interval(const Interval* i) { 199 #if defined(__SOFTFP__) || defined(E500V2) 200 return i->reg_num() >= LIR_OprDesc::vreg_base; 201 #else 202 return i->reg_num() >= LIR_OprDesc::vreg_base && (i->type() != T_FLOAT && i->type() != T_DOUBLE); 203 #endif // __SOFTFP__ or E500V2 204 } 205 206 bool LinearScan::is_precolored_fpu_interval(const Interval* i) { 207 return i->reg_num() >= LinearScan::nof_cpu_regs && i->reg_num() < LinearScan::nof_regs; 208 } 209 210 bool LinearScan::is_virtual_fpu_interval(const Interval* i) { 211 #if defined(__SOFTFP__) || defined(E500V2) 212 return false; 213 #else 214 return i->reg_num() >= LIR_OprDesc::vreg_base && (i->type() == T_FLOAT || i->type() == T_DOUBLE); 215 #endif // __SOFTFP__ or E500V2 216 } 217 218 bool LinearScan::is_in_fpu_register(const Interval* i) { 219 // fixed intervals not needed for FPU stack allocation 220 return i->reg_num() >= nof_regs && pd_first_fpu_reg <= i->assigned_reg() && i->assigned_reg() <= pd_last_fpu_reg; 221 } 222 223 bool LinearScan::is_oop_interval(const Interval* i) { 224 // fixed intervals never contain oops 225 return i->reg_num() >= nof_regs && i->type() == T_OBJECT; 226 } 227 228 229 // ********** General helper functions 230 231 // compute next unused stack index that can be used for spilling 232 int LinearScan::allocate_spill_slot(bool double_word) { 233 int spill_slot; 234 if (double_word) { 235 if ((_max_spills & 1) == 1) { 236 // alignment of double-word values 237 // the hole because of the alignment is filled with the next single-word value 238 assert(_unused_spill_slot == -1, "wasting a spill slot"); 239 _unused_spill_slot = _max_spills; 240 _max_spills++; 241 } 242 spill_slot = _max_spills; 243 _max_spills += 2; 244 245 } else if (_unused_spill_slot != -1) { 246 // re-use hole that was the result of a previous double-word alignment 247 spill_slot = _unused_spill_slot; 248 _unused_spill_slot = -1; 249 250 } else { 251 spill_slot = _max_spills; 252 _max_spills++; 253 } 254 255 int result = spill_slot + LinearScan::nof_regs + frame_map()->argcount(); 256 257 // the class OopMapValue uses only 11 bits for storing the name of the 258 // oop location. So a stack slot bigger than 2^11 leads to an overflow 259 // that is not reported in product builds. Prevent this by checking the 260 // spill slot here (altough this value and the later used location name 261 // are slightly different) 262 if (result > 2000) { 263 bailout("too many stack slots used"); 264 } 265 266 return result; 267 } 268 269 void LinearScan::assign_spill_slot(Interval* it) { 270 // assign the canonical spill slot of the parent (if a part of the interval 271 // is already spilled) or allocate a new spill slot 272 if (it->canonical_spill_slot() >= 0) { 273 it->assign_reg(it->canonical_spill_slot()); 274 } else { 275 int spill = allocate_spill_slot(type2spill_size[it->type()] == 2); 276 it->set_canonical_spill_slot(spill); 277 it->assign_reg(spill); 278 } 279 } 280 281 void LinearScan::propagate_spill_slots() { 282 if (!frame_map()->finalize_frame(max_spills())) { 283 bailout("frame too large"); 284 } 285 } 286 287 // create a new interval with a predefined reg_num 288 // (only used for parent intervals that are created during the building phase) 289 Interval* LinearScan::create_interval(int reg_num) { 290 assert(_intervals.at(reg_num) == NULL, "overwriting exisiting interval"); 291 292 Interval* interval = new Interval(reg_num); 293 _intervals.at_put(reg_num, interval); 294 295 // assign register number for precolored intervals 296 if (reg_num < LIR_OprDesc::vreg_base) { 297 interval->assign_reg(reg_num); 298 } 299 return interval; 300 } 301 302 // assign a new reg_num to the interval and append it to the list of intervals 303 // (only used for child intervals that are created during register allocation) 304 void LinearScan::append_interval(Interval* it) { 305 it->set_reg_num(_intervals.length()); 306 _intervals.append(it); 307 _new_intervals_from_allocation->append(it); 308 } 309 310 // copy the vreg-flags if an interval is split 311 void LinearScan::copy_register_flags(Interval* from, Interval* to) { 312 if (gen()->is_vreg_flag_set(from->reg_num(), LIRGenerator::byte_reg)) { 313 gen()->set_vreg_flag(to->reg_num(), LIRGenerator::byte_reg); 314 } 315 if (gen()->is_vreg_flag_set(from->reg_num(), LIRGenerator::callee_saved)) { 316 gen()->set_vreg_flag(to->reg_num(), LIRGenerator::callee_saved); 317 } 318 319 // Note: do not copy the must_start_in_memory flag because it is not necessary for child 320 // intervals (only the very beginning of the interval must be in memory) 321 } 322 323 324 // ********** spill move optimization 325 // eliminate moves from register to stack if stack slot is known to be correct 326 327 // called during building of intervals 328 void LinearScan::change_spill_definition_pos(Interval* interval, int def_pos) { 329 assert(interval->is_split_parent(), "can only be called for split parents"); 330 331 switch (interval->spill_state()) { 332 case noDefinitionFound: 333 assert(interval->spill_definition_pos() == -1, "must no be set before"); 334 interval->set_spill_definition_pos(def_pos); 335 interval->set_spill_state(oneDefinitionFound); 336 break; 337 338 case oneDefinitionFound: 339 assert(def_pos <= interval->spill_definition_pos(), "positions are processed in reverse order when intervals are created"); 340 if (def_pos < interval->spill_definition_pos() - 2) { 341 // second definition found, so no spill optimization possible for this interval 342 interval->set_spill_state(noOptimization); 343 } else { 344 // two consecutive definitions (because of two-operand LIR form) 345 assert(block_of_op_with_id(def_pos) == block_of_op_with_id(interval->spill_definition_pos()), "block must be equal"); 346 } 347 break; 348 349 case noOptimization: 350 // nothing to do 351 break; 352 353 default: 354 assert(false, "other states not allowed at this time"); 355 } 356 } 357 358 // called during register allocation 359 void LinearScan::change_spill_state(Interval* interval, int spill_pos) { 360 switch (interval->spill_state()) { 361 case oneDefinitionFound: { 362 int def_loop_depth = block_of_op_with_id(interval->spill_definition_pos())->loop_depth(); 363 int spill_loop_depth = block_of_op_with_id(spill_pos)->loop_depth(); 364 365 if (def_loop_depth < spill_loop_depth) { 366 // the loop depth of the spilling position is higher then the loop depth 367 // at the definition of the interval -> move write to memory out of loop 368 // by storing at definitin of the interval 369 interval->set_spill_state(storeAtDefinition); 370 } else { 371 // the interval is currently spilled only once, so for now there is no 372 // reason to store the interval at the definition 373 interval->set_spill_state(oneMoveInserted); 374 } 375 break; 376 } 377 378 case oneMoveInserted: { 379 // the interval is spilled more then once, so it is better to store it to 380 // memory at the definition 381 interval->set_spill_state(storeAtDefinition); 382 break; 383 } 384 385 case storeAtDefinition: 386 case startInMemory: 387 case noOptimization: 388 case noDefinitionFound: 389 // nothing to do 390 break; 391 392 default: 393 assert(false, "other states not allowed at this time"); 394 } 395 } 396 397 398 bool LinearScan::must_store_at_definition(const Interval* i) { 399 return i->is_split_parent() && i->spill_state() == storeAtDefinition; 400 } 401 402 // called once before asignment of register numbers 403 void LinearScan::eliminate_spill_moves() { 404 TIME_LINEAR_SCAN(timer_eliminate_spill_moves); 405 TRACE_LINEAR_SCAN(3, tty->print_cr("***** Eliminating unnecessary spill moves")); 406 407 // collect all intervals that must be stored after their definion. 408 // the list is sorted by Interval::spill_definition_pos 409 Interval* interval; 410 Interval* temp_list; 411 create_unhandled_lists(&interval, &temp_list, must_store_at_definition, NULL); 412 413 #ifdef ASSERT 414 Interval* prev = NULL; 415 Interval* temp = interval; 416 while (temp != Interval::end()) { 417 assert(temp->spill_definition_pos() > 0, "invalid spill definition pos"); 418 if (prev != NULL) { 419 assert(temp->from() >= prev->from(), "intervals not sorted"); 420 assert(temp->spill_definition_pos() >= prev->spill_definition_pos(), "when intervals are sorted by from, then they must also be sorted by spill_definition_pos"); 421 } 422 423 assert(temp->canonical_spill_slot() >= LinearScan::nof_regs, "interval has no spill slot assigned"); 424 assert(temp->spill_definition_pos() >= temp->from(), "invalid order"); 425 assert(temp->spill_definition_pos() <= temp->from() + 2, "only intervals defined once at their start-pos can be optimized"); 426 427 TRACE_LINEAR_SCAN(4, tty->print_cr("interval %d (from %d to %d) must be stored at %d", temp->reg_num(), temp->from(), temp->to(), temp->spill_definition_pos())); 428 429 temp = temp->next(); 430 } 431 #endif 432 433 LIR_InsertionBuffer insertion_buffer; 434 int num_blocks = block_count(); 435 for (int i = 0; i < num_blocks; i++) { 436 BlockBegin* block = block_at(i); 437 LIR_OpList* instructions = block->lir()->instructions_list(); 438 int num_inst = instructions->length(); 439 bool has_new = false; 440 441 // iterate all instructions of the block. skip the first because it is always a label 442 for (int j = 1; j < num_inst; j++) { 443 LIR_Op* op = instructions->at(j); 444 int op_id = op->id(); 445 446 if (op_id == -1) { 447 // remove move from register to stack if the stack slot is guaranteed to be correct. 448 // only moves that have been inserted by LinearScan can be removed. 449 assert(op->code() == lir_move, "only moves can have a op_id of -1"); 450 assert(op->as_Op1() != NULL, "move must be LIR_Op1"); 451 assert(op->as_Op1()->result_opr()->is_virtual(), "LinearScan inserts only moves to virtual registers"); 452 453 LIR_Op1* op1 = (LIR_Op1*)op; 454 Interval* interval = interval_at(op1->result_opr()->vreg_number()); 455 456 if (interval->assigned_reg() >= LinearScan::nof_regs && interval->always_in_memory()) { 457 // move target is a stack slot that is always correct, so eliminate instruction 458 TRACE_LINEAR_SCAN(4, tty->print_cr("eliminating move from interval %d to %d", op1->in_opr()->vreg_number(), op1->result_opr()->vreg_number())); 459 instructions->at_put(j, NULL); // NULL-instructions are deleted by assign_reg_num 460 } 461 462 } else { 463 // insert move from register to stack just after the beginning of the interval 464 assert(interval == Interval::end() || interval->spill_definition_pos() >= op_id, "invalid order"); 465 assert(interval == Interval::end() || (interval->is_split_parent() && interval->spill_state() == storeAtDefinition), "invalid interval"); 466 467 while (interval != Interval::end() && interval->spill_definition_pos() == op_id) { 468 if (!has_new) { 469 // prepare insertion buffer (appended when all instructions of the block are processed) 470 insertion_buffer.init(block->lir()); 471 has_new = true; 472 } 473 474 LIR_Opr from_opr = operand_for_interval(interval); 475 LIR_Opr to_opr = canonical_spill_opr(interval); 476 assert(from_opr->is_fixed_cpu() || from_opr->is_fixed_fpu(), "from operand must be a register"); 477 assert(to_opr->is_stack(), "to operand must be a stack slot"); 478 479 insertion_buffer.move(j, from_opr, to_opr); 480 TRACE_LINEAR_SCAN(4, tty->print_cr("inserting move after definition of interval %d to stack slot %d at op_id %d", interval->reg_num(), interval->canonical_spill_slot() - LinearScan::nof_regs, op_id)); 481 482 interval = interval->next(); 483 } 484 } 485 } // end of instruction iteration 486 487 if (has_new) { 488 block->lir()->append(&insertion_buffer); 489 } 490 } // end of block iteration 491 492 assert(interval == Interval::end(), "missed an interval"); 493 } 494 495 496 // ********** Phase 1: number all instructions in all blocks 497 // Compute depth-first and linear scan block orders, and number LIR_Op nodes for linear scan. 498 499 void LinearScan::number_instructions() { 500 { 501 // dummy-timer to measure the cost of the timer itself 502 // (this time is then subtracted from all other timers to get the real value) 503 TIME_LINEAR_SCAN(timer_do_nothing); 504 } 505 TIME_LINEAR_SCAN(timer_number_instructions); 506 507 // Assign IDs to LIR nodes and build a mapping, lir_ops, from ID to LIR_Op node. 508 int num_blocks = block_count(); 509 int num_instructions = 0; 510 int i; 511 for (i = 0; i < num_blocks; i++) { 512 num_instructions += block_at(i)->lir()->instructions_list()->length(); 513 } 514 515 // initialize with correct length 516 _lir_ops = LIR_OpArray(num_instructions); 517 _block_of_op = BlockBeginArray(num_instructions); 518 519 int op_id = 0; 520 int idx = 0; 521 522 for (i = 0; i < num_blocks; i++) { 523 BlockBegin* block = block_at(i); 524 block->set_first_lir_instruction_id(op_id); 525 LIR_OpList* instructions = block->lir()->instructions_list(); 526 527 int num_inst = instructions->length(); 528 for (int j = 0; j < num_inst; j++) { 529 LIR_Op* op = instructions->at(j); 530 op->set_id(op_id); 531 532 _lir_ops.at_put(idx, op); 533 _block_of_op.at_put(idx, block); 534 assert(lir_op_with_id(op_id) == op, "must match"); 535 536 idx++; 537 op_id += 2; // numbering of lir_ops by two 538 } 539 block->set_last_lir_instruction_id(op_id - 2); 540 } 541 assert(idx == num_instructions, "must match"); 542 assert(idx * 2 == op_id, "must match"); 543 544 _has_call = BitMap(num_instructions); _has_call.clear(); 545 _has_info = BitMap(num_instructions); _has_info.clear(); 546 } 547 548 549 // ********** Phase 2: compute local live sets separately for each block 550 // (sets live_gen and live_kill for each block) 551 552 void LinearScan::set_live_gen_kill(Value value, LIR_Op* op, BitMap& live_gen, BitMap& live_kill) { 553 LIR_Opr opr = value->operand(); 554 Constant* con = value->as_Constant(); 555 556 // check some asumptions about debug information 557 assert(!value->type()->is_illegal(), "if this local is used by the interpreter it shouldn't be of indeterminate type"); 558 assert(con == NULL || opr->is_virtual() || opr->is_constant() || opr->is_illegal(), "asumption: Constant instructions have only constant operands"); 559 assert(con != NULL || opr->is_virtual(), "asumption: non-Constant instructions have only virtual operands"); 560 561 if ((con == NULL || con->is_pinned()) && opr->is_register()) { 562 assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below"); 563 int reg = opr->vreg_number(); 564 if (!live_kill.at(reg)) { 565 live_gen.set_bit(reg); 566 TRACE_LINEAR_SCAN(4, tty->print_cr(" Setting live_gen for value %c%d, LIR op_id %d, register number %d", value->type()->tchar(), value->id(), op->id(), reg)); 567 } 568 } 569 } 570 571 572 void LinearScan::compute_local_live_sets() { 573 TIME_LINEAR_SCAN(timer_compute_local_live_sets); 574 575 int num_blocks = block_count(); 576 int live_size = live_set_size(); 577 bool local_has_fpu_registers = false; 578 int local_num_calls = 0; 579 LIR_OpVisitState visitor; 580 581 BitMap2D local_interval_in_loop = BitMap2D(_num_virtual_regs, num_loops()); 582 local_interval_in_loop.clear(); 583 584 // iterate all blocks 585 for (int i = 0; i < num_blocks; i++) { 586 BlockBegin* block = block_at(i); 587 588 BitMap live_gen(live_size); live_gen.clear(); 589 BitMap live_kill(live_size); live_kill.clear(); 590 591 if (block->is_set(BlockBegin::exception_entry_flag)) { 592 // Phi functions at the begin of an exception handler are 593 // implicitly defined (= killed) at the beginning of the block. 594 for_each_phi_fun(block, phi, 595 live_kill.set_bit(phi->operand()->vreg_number()) 596 ); 597 } 598 599 LIR_OpList* instructions = block->lir()->instructions_list(); 600 int num_inst = instructions->length(); 601 602 // iterate all instructions of the block. skip the first because it is always a label 603 assert(visitor.no_operands(instructions->at(0)), "first operation must always be a label"); 604 for (int j = 1; j < num_inst; j++) { 605 LIR_Op* op = instructions->at(j); 606 607 // visit operation to collect all operands 608 visitor.visit(op); 609 610 if (visitor.has_call()) { 611 _has_call.set_bit(op->id() >> 1); 612 local_num_calls++; 613 } 614 if (visitor.info_count() > 0) { 615 _has_info.set_bit(op->id() >> 1); 616 } 617 618 // iterate input operands of instruction 619 int k, n, reg; 620 n = visitor.opr_count(LIR_OpVisitState::inputMode); 621 for (k = 0; k < n; k++) { 622 LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::inputMode, k); 623 assert(opr->is_register(), "visitor should only return register operands"); 624 625 if (opr->is_virtual_register()) { 626 assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below"); 627 reg = opr->vreg_number(); 628 if (!live_kill.at(reg)) { 629 live_gen.set_bit(reg); 630 TRACE_LINEAR_SCAN(4, tty->print_cr(" Setting live_gen for register %d at instruction %d", reg, op->id())); 631 } 632 if (block->loop_index() >= 0) { 633 local_interval_in_loop.set_bit(reg, block->loop_index()); 634 } 635 local_has_fpu_registers = local_has_fpu_registers || opr->is_virtual_fpu(); 636 } 637 638 #ifdef ASSERT 639 // fixed intervals are never live at block boundaries, so 640 // they need not be processed in live sets. 641 // this is checked by these assertions to be sure about it. 642 // the entry block may have incoming values in registers, which is ok. 643 if (!opr->is_virtual_register() && block != ir()->start()) { 644 reg = reg_num(opr); 645 if (is_processed_reg_num(reg)) { 646 assert(live_kill.at(reg), "using fixed register that is not defined in this block"); 647 } 648 reg = reg_numHi(opr); 649 if (is_valid_reg_num(reg) && is_processed_reg_num(reg)) { 650 assert(live_kill.at(reg), "using fixed register that is not defined in this block"); 651 } 652 } 653 #endif 654 } 655 656 // Add uses of live locals from interpreter's point of view for proper debug information generation 657 n = visitor.info_count(); 658 for (k = 0; k < n; k++) { 659 CodeEmitInfo* info = visitor.info_at(k); 660 ValueStack* stack = info->stack(); 661 for_each_state_value(stack, value, 662 set_live_gen_kill(value, op, live_gen, live_kill) 663 ); 664 } 665 666 // iterate temp operands of instruction 667 n = visitor.opr_count(LIR_OpVisitState::tempMode); 668 for (k = 0; k < n; k++) { 669 LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::tempMode, k); 670 assert(opr->is_register(), "visitor should only return register operands"); 671 672 if (opr->is_virtual_register()) { 673 assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below"); 674 reg = opr->vreg_number(); 675 live_kill.set_bit(reg); 676 if (block->loop_index() >= 0) { 677 local_interval_in_loop.set_bit(reg, block->loop_index()); 678 } 679 local_has_fpu_registers = local_has_fpu_registers || opr->is_virtual_fpu(); 680 } 681 682 #ifdef ASSERT 683 // fixed intervals are never live at block boundaries, so 684 // they need not be processed in live sets 685 // process them only in debug mode so that this can be checked 686 if (!opr->is_virtual_register()) { 687 reg = reg_num(opr); 688 if (is_processed_reg_num(reg)) { 689 live_kill.set_bit(reg_num(opr)); 690 } 691 reg = reg_numHi(opr); 692 if (is_valid_reg_num(reg) && is_processed_reg_num(reg)) { 693 live_kill.set_bit(reg); 694 } 695 } 696 #endif 697 } 698 699 // iterate output operands of instruction 700 n = visitor.opr_count(LIR_OpVisitState::outputMode); 701 for (k = 0; k < n; k++) { 702 LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::outputMode, k); 703 assert(opr->is_register(), "visitor should only return register operands"); 704 705 if (opr->is_virtual_register()) { 706 assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below"); 707 reg = opr->vreg_number(); 708 live_kill.set_bit(reg); 709 if (block->loop_index() >= 0) { 710 local_interval_in_loop.set_bit(reg, block->loop_index()); 711 } 712 local_has_fpu_registers = local_has_fpu_registers || opr->is_virtual_fpu(); 713 } 714 715 #ifdef ASSERT 716 // fixed intervals are never live at block boundaries, so 717 // they need not be processed in live sets 718 // process them only in debug mode so that this can be checked 719 if (!opr->is_virtual_register()) { 720 reg = reg_num(opr); 721 if (is_processed_reg_num(reg)) { 722 live_kill.set_bit(reg_num(opr)); 723 } 724 reg = reg_numHi(opr); 725 if (is_valid_reg_num(reg) && is_processed_reg_num(reg)) { 726 live_kill.set_bit(reg); 727 } 728 } 729 #endif 730 } 731 } // end of instruction iteration 732 733 block->set_live_gen (live_gen); 734 block->set_live_kill(live_kill); 735 block->set_live_in (BitMap(live_size)); block->live_in().clear(); 736 block->set_live_out (BitMap(live_size)); block->live_out().clear(); 737 738 TRACE_LINEAR_SCAN(4, tty->print("live_gen B%d ", block->block_id()); print_bitmap(block->live_gen())); 739 TRACE_LINEAR_SCAN(4, tty->print("live_kill B%d ", block->block_id()); print_bitmap(block->live_kill())); 740 } // end of block iteration 741 742 // propagate local calculated information into LinearScan object 743 _has_fpu_registers = local_has_fpu_registers; 744 compilation()->set_has_fpu_code(local_has_fpu_registers); 745 746 _num_calls = local_num_calls; 747 _interval_in_loop = local_interval_in_loop; 748 } 749 750 751 // ********** Phase 3: perform a backward dataflow analysis to compute global live sets 752 // (sets live_in and live_out for each block) 753 754 void LinearScan::compute_global_live_sets() { 755 TIME_LINEAR_SCAN(timer_compute_global_live_sets); 756 757 int num_blocks = block_count(); 758 bool change_occurred; 759 bool change_occurred_in_block; 760 int iteration_count = 0; 761 BitMap live_out(live_set_size()); live_out.clear(); // scratch set for calculations 762 763 // Perform a backward dataflow analysis to compute live_out and live_in for each block. 764 // The loop is executed until a fixpoint is reached (no changes in an iteration) 765 // Exception handlers must be processed because not all live values are 766 // present in the state array, e.g. because of global value numbering 767 do { 768 change_occurred = false; 769 770 // iterate all blocks in reverse order 771 for (int i = num_blocks - 1; i >= 0; i--) { 772 BlockBegin* block = block_at(i); 773 774 change_occurred_in_block = false; 775 776 // live_out(block) is the union of live_in(sux), for successors sux of block 777 int n = block->number_of_sux(); 778 int e = block->number_of_exception_handlers(); 779 if (n + e > 0) { 780 // block has successors 781 if (n > 0) { 782 live_out.set_from(block->sux_at(0)->live_in()); 783 for (int j = 1; j < n; j++) { 784 live_out.set_union(block->sux_at(j)->live_in()); 785 } 786 } else { 787 live_out.clear(); 788 } 789 for (int j = 0; j < e; j++) { 790 live_out.set_union(block->exception_handler_at(j)->live_in()); 791 } 792 793 if (!block->live_out().is_same(live_out)) { 794 // A change occurred. Swap the old and new live out sets to avoid copying. 795 BitMap temp = block->live_out(); 796 block->set_live_out(live_out); 797 live_out = temp; 798 799 change_occurred = true; 800 change_occurred_in_block = true; 801 } 802 } 803 804 if (iteration_count == 0 || change_occurred_in_block) { 805 // live_in(block) is the union of live_gen(block) with (live_out(block) & !live_kill(block)) 806 // note: live_in has to be computed only in first iteration or if live_out has changed! 807 BitMap live_in = block->live_in(); 808 live_in.set_from(block->live_out()); 809 live_in.set_difference(block->live_kill()); 810 live_in.set_union(block->live_gen()); 811 } 812 813 #ifndef PRODUCT 814 if (TraceLinearScanLevel >= 4) { 815 char c = ' '; 816 if (iteration_count == 0 || change_occurred_in_block) { 817 c = '*'; 818 } 819 tty->print("(%d) live_in%c B%d ", iteration_count, c, block->block_id()); print_bitmap(block->live_in()); 820 tty->print("(%d) live_out%c B%d ", iteration_count, c, block->block_id()); print_bitmap(block->live_out()); 821 } 822 #endif 823 } 824 iteration_count++; 825 826 if (change_occurred && iteration_count > 50) { 827 BAILOUT("too many iterations in compute_global_live_sets"); 828 } 829 } while (change_occurred); 830 831 832 #ifdef ASSERT 833 // check that fixed intervals are not live at block boundaries 834 // (live set must be empty at fixed intervals) 835 for (int i = 0; i < num_blocks; i++) { 836 BlockBegin* block = block_at(i); 837 for (int j = 0; j < LIR_OprDesc::vreg_base; j++) { 838 assert(block->live_in().at(j) == false, "live_in set of fixed register must be empty"); 839 assert(block->live_out().at(j) == false, "live_out set of fixed register must be empty"); 840 assert(block->live_gen().at(j) == false, "live_gen set of fixed register must be empty"); 841 } 842 } 843 #endif 844 845 // check that the live_in set of the first block is empty 846 BitMap live_in_args(ir()->start()->live_in().size()); 847 live_in_args.clear(); 848 if (!ir()->start()->live_in().is_same(live_in_args)) { 849 #ifdef ASSERT 850 tty->print_cr("Error: live_in set of first block must be empty (when this fails, virtual registers are used before they are defined)"); 851 tty->print_cr("affected registers:"); 852 print_bitmap(ir()->start()->live_in()); 853 854 // print some additional information to simplify debugging 855 for (unsigned int i = 0; i < ir()->start()->live_in().size(); i++) { 856 if (ir()->start()->live_in().at(i)) { 857 Instruction* instr = gen()->instruction_for_vreg(i); 858 tty->print_cr("* vreg %d (HIR instruction %c%d)", i, instr == NULL ? ' ' : instr->type()->tchar(), instr == NULL ? 0 : instr->id()); 859 860 for (int j = 0; j < num_blocks; j++) { 861 BlockBegin* block = block_at(j); 862 if (block->live_gen().at(i)) { 863 tty->print_cr(" used in block B%d", block->block_id()); 864 } 865 if (block->live_kill().at(i)) { 866 tty->print_cr(" defined in block B%d", block->block_id()); 867 } 868 } 869 } 870 } 871 872 #endif 873 // when this fails, virtual registers are used before they are defined. 874 assert(false, "live_in set of first block must be empty"); 875 // bailout of if this occurs in product mode. 876 bailout("live_in set of first block not empty"); 877 } 878 } 879 880 881 // ********** Phase 4: build intervals 882 // (fills the list _intervals) 883 884 void LinearScan::add_use(Value value, int from, int to, IntervalUseKind use_kind) { 885 assert(!value->type()->is_illegal(), "if this value is used by the interpreter it shouldn't be of indeterminate type"); 886 LIR_Opr opr = value->operand(); 887 Constant* con = value->as_Constant(); 888 889 if ((con == NULL || con->is_pinned()) && opr->is_register()) { 890 assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below"); 891 add_use(opr, from, to, use_kind); 892 } 893 } 894 895 896 void LinearScan::add_def(LIR_Opr opr, int def_pos, IntervalUseKind use_kind) { 897 TRACE_LINEAR_SCAN(2, tty->print(" def "); opr->print(tty); tty->print_cr(" def_pos %d (%d)", def_pos, use_kind)); 898 assert(opr->is_register(), "should not be called otherwise"); 899 900 if (opr->is_virtual_register()) { 901 assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below"); 902 add_def(opr->vreg_number(), def_pos, use_kind, opr->type_register()); 903 904 } else { 905 int reg = reg_num(opr); 906 if (is_processed_reg_num(reg)) { 907 add_def(reg, def_pos, use_kind, opr->type_register()); 908 } 909 reg = reg_numHi(opr); 910 if (is_valid_reg_num(reg) && is_processed_reg_num(reg)) { 911 add_def(reg, def_pos, use_kind, opr->type_register()); 912 } 913 } 914 } 915 916 void LinearScan::add_use(LIR_Opr opr, int from, int to, IntervalUseKind use_kind) { 917 TRACE_LINEAR_SCAN(2, tty->print(" use "); opr->print(tty); tty->print_cr(" from %d to %d (%d)", from, to, use_kind)); 918 assert(opr->is_register(), "should not be called otherwise"); 919 920 if (opr->is_virtual_register()) { 921 assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below"); 922 add_use(opr->vreg_number(), from, to, use_kind, opr->type_register()); 923 924 } else { 925 int reg = reg_num(opr); 926 if (is_processed_reg_num(reg)) { 927 add_use(reg, from, to, use_kind, opr->type_register()); 928 } 929 reg = reg_numHi(opr); 930 if (is_valid_reg_num(reg) && is_processed_reg_num(reg)) { 931 add_use(reg, from, to, use_kind, opr->type_register()); 932 } 933 } 934 } 935 936 void LinearScan::add_temp(LIR_Opr opr, int temp_pos, IntervalUseKind use_kind) { 937 TRACE_LINEAR_SCAN(2, tty->print(" temp "); opr->print(tty); tty->print_cr(" temp_pos %d (%d)", temp_pos, use_kind)); 938 assert(opr->is_register(), "should not be called otherwise"); 939 940 if (opr->is_virtual_register()) { 941 assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below"); 942 add_temp(opr->vreg_number(), temp_pos, use_kind, opr->type_register()); 943 944 } else { 945 int reg = reg_num(opr); 946 if (is_processed_reg_num(reg)) { 947 add_temp(reg, temp_pos, use_kind, opr->type_register()); 948 } 949 reg = reg_numHi(opr); 950 if (is_valid_reg_num(reg) && is_processed_reg_num(reg)) { 951 add_temp(reg, temp_pos, use_kind, opr->type_register()); 952 } 953 } 954 } 955 956 957 void LinearScan::add_def(int reg_num, int def_pos, IntervalUseKind use_kind, BasicType type) { 958 Interval* interval = interval_at(reg_num); 959 if (interval != NULL) { 960 assert(interval->reg_num() == reg_num, "wrong interval"); 961 962 if (type != T_ILLEGAL) { 963 interval->set_type(type); 964 } 965 966 Range* r = interval->first(); 967 if (r->from() <= def_pos) { 968 // Update the starting point (when a range is first created for a use, its 969 // start is the beginning of the current block until a def is encountered.) 970 r->set_from(def_pos); 971 interval->add_use_pos(def_pos, use_kind); 972 973 } else { 974 // Dead value - make vacuous interval 975 // also add use_kind for dead intervals 976 interval->add_range(def_pos, def_pos + 1); 977 interval->add_use_pos(def_pos, use_kind); 978 TRACE_LINEAR_SCAN(2, tty->print_cr("Warning: def of reg %d at %d occurs without use", reg_num, def_pos)); 979 } 980 981 } else { 982 // Dead value - make vacuous interval 983 // also add use_kind for dead intervals 984 interval = create_interval(reg_num); 985 if (type != T_ILLEGAL) { 986 interval->set_type(type); 987 } 988 989 interval->add_range(def_pos, def_pos + 1); 990 interval->add_use_pos(def_pos, use_kind); 991 TRACE_LINEAR_SCAN(2, tty->print_cr("Warning: dead value %d at %d in live intervals", reg_num, def_pos)); 992 } 993 994 change_spill_definition_pos(interval, def_pos); 995 if (use_kind == noUse && interval->spill_state() <= startInMemory) { 996 // detection of method-parameters and roundfp-results 997 // TODO: move this directly to position where use-kind is computed 998 interval->set_spill_state(startInMemory); 999 } 1000 } 1001 1002 void LinearScan::add_use(int reg_num, int from, int to, IntervalUseKind use_kind, BasicType type) { 1003 Interval* interval = interval_at(reg_num); 1004 if (interval == NULL) { 1005 interval = create_interval(reg_num); 1006 } 1007 assert(interval->reg_num() == reg_num, "wrong interval"); 1008 1009 if (type != T_ILLEGAL) { 1010 interval->set_type(type); 1011 } 1012 1013 interval->add_range(from, to); 1014 interval->add_use_pos(to, use_kind); 1015 } 1016 1017 void LinearScan::add_temp(int reg_num, int temp_pos, IntervalUseKind use_kind, BasicType type) { 1018 Interval* interval = interval_at(reg_num); 1019 if (interval == NULL) { 1020 interval = create_interval(reg_num); 1021 } 1022 assert(interval->reg_num() == reg_num, "wrong interval"); 1023 1024 if (type != T_ILLEGAL) { 1025 interval->set_type(type); 1026 } 1027 1028 interval->add_range(temp_pos, temp_pos + 1); 1029 interval->add_use_pos(temp_pos, use_kind); 1030 } 1031 1032 1033 // the results of this functions are used for optimizing spilling and reloading 1034 // if the functions return shouldHaveRegister and the interval is spilled, 1035 // it is not reloaded to a register. 1036 IntervalUseKind LinearScan::use_kind_of_output_operand(LIR_Op* op, LIR_Opr opr) { 1037 if (op->code() == lir_move) { 1038 assert(op->as_Op1() != NULL, "lir_move must be LIR_Op1"); 1039 LIR_Op1* move = (LIR_Op1*)op; 1040 LIR_Opr res = move->result_opr(); 1041 bool result_in_memory = res->is_virtual() && gen()->is_vreg_flag_set(res->vreg_number(), LIRGenerator::must_start_in_memory); 1042 1043 if (result_in_memory) { 1044 // Begin of an interval with must_start_in_memory set. 1045 // This interval will always get a stack slot first, so return noUse. 1046 return noUse; 1047 1048 } else if (move->in_opr()->is_stack()) { 1049 // method argument (condition must be equal to handle_method_arguments) 1050 return noUse; 1051 1052 } else if (move->in_opr()->is_register() && move->result_opr()->is_register()) { 1053 // Move from register to register 1054 if (block_of_op_with_id(op->id())->is_set(BlockBegin::osr_entry_flag)) { 1055 // special handling of phi-function moves inside osr-entry blocks 1056 // input operand must have a register instead of output operand (leads to better register allocation) 1057 return shouldHaveRegister; 1058 } 1059 } 1060 } 1061 1062 if (opr->is_virtual() && 1063 gen()->is_vreg_flag_set(opr->vreg_number(), LIRGenerator::must_start_in_memory)) { 1064 // result is a stack-slot, so prevent immediate reloading 1065 return noUse; 1066 } 1067 1068 // all other operands require a register 1069 return mustHaveRegister; 1070 } 1071 1072 IntervalUseKind LinearScan::use_kind_of_input_operand(LIR_Op* op, LIR_Opr opr) { 1073 if (op->code() == lir_move) { 1074 assert(op->as_Op1() != NULL, "lir_move must be LIR_Op1"); 1075 LIR_Op1* move = (LIR_Op1*)op; 1076 LIR_Opr res = move->result_opr(); 1077 bool result_in_memory = res->is_virtual() && gen()->is_vreg_flag_set(res->vreg_number(), LIRGenerator::must_start_in_memory); 1078 1079 if (result_in_memory) { 1080 // Move to an interval with must_start_in_memory set. 1081 // To avoid moves from stack to stack (not allowed) force the input operand to a register 1082 return mustHaveRegister; 1083 1084 } else if (move->in_opr()->is_register() && move->result_opr()->is_register()) { 1085 // Move from register to register 1086 if (block_of_op_with_id(op->id())->is_set(BlockBegin::osr_entry_flag)) { 1087 // special handling of phi-function moves inside osr-entry blocks 1088 // input operand must have a register instead of output operand (leads to better register allocation) 1089 return mustHaveRegister; 1090 } 1091 1092 // The input operand is not forced to a register (moves from stack to register are allowed), 1093 // but it is faster if the input operand is in a register 1094 return shouldHaveRegister; 1095 } 1096 } 1097 1098 1099 #ifdef X86 1100 if (op->code() == lir_cmove) { 1101 // conditional moves can handle stack operands 1102 assert(op->result_opr()->is_register(), "result must always be in a register"); 1103 return shouldHaveRegister; 1104 } 1105 1106 // optimizations for second input operand of arithmehtic operations on Intel 1107 // this operand is allowed to be on the stack in some cases 1108 BasicType opr_type = opr->type_register(); 1109 if (opr_type == T_FLOAT || opr_type == T_DOUBLE) { 1110 if ((UseSSE == 1 && opr_type == T_FLOAT) || UseSSE >= 2) { 1111 // SSE float instruction (T_DOUBLE only supported with SSE2) 1112 switch (op->code()) { 1113 case lir_cmp: 1114 case lir_add: 1115 case lir_sub: 1116 case lir_mul: 1117 case lir_div: 1118 { 1119 assert(op->as_Op2() != NULL, "must be LIR_Op2"); 1120 LIR_Op2* op2 = (LIR_Op2*)op; 1121 if (op2->in_opr1() != op2->in_opr2() && op2->in_opr2() == opr) { 1122 assert((op2->result_opr()->is_register() || op->code() == lir_cmp) && op2->in_opr1()->is_register(), "cannot mark second operand as stack if others are not in register"); 1123 return shouldHaveRegister; 1124 } 1125 } 1126 } 1127 } else { 1128 // FPU stack float instruction 1129 switch (op->code()) { 1130 case lir_add: 1131 case lir_sub: 1132 case lir_mul: 1133 case lir_div: 1134 { 1135 assert(op->as_Op2() != NULL, "must be LIR_Op2"); 1136 LIR_Op2* op2 = (LIR_Op2*)op; 1137 if (op2->in_opr1() != op2->in_opr2() && op2->in_opr2() == opr) { 1138 assert((op2->result_opr()->is_register() || op->code() == lir_cmp) && op2->in_opr1()->is_register(), "cannot mark second operand as stack if others are not in register"); 1139 return shouldHaveRegister; 1140 } 1141 } 1142 } 1143 } 1144 // We want to sometimes use logical operations on pointers, in particular in GC barriers. 1145 // Since 64bit logical operations do not current support operands on stack, we have to make sure 1146 // T_OBJECT doesn't get spilled along with T_LONG. 1147 } else if (opr_type != T_LONG LP64_ONLY(&& opr_type != T_OBJECT)) { 1148 // integer instruction (note: long operands must always be in register) 1149 switch (op->code()) { 1150 case lir_cmp: 1151 case lir_add: 1152 case lir_sub: 1153 case lir_logic_and: 1154 case lir_logic_or: 1155 case lir_logic_xor: 1156 { 1157 assert(op->as_Op2() != NULL, "must be LIR_Op2"); 1158 LIR_Op2* op2 = (LIR_Op2*)op; 1159 if (op2->in_opr1() != op2->in_opr2() && op2->in_opr2() == opr) { 1160 assert((op2->result_opr()->is_register() || op->code() == lir_cmp) && op2->in_opr1()->is_register(), "cannot mark second operand as stack if others are not in register"); 1161 return shouldHaveRegister; 1162 } 1163 } 1164 } 1165 } 1166 #endif // X86 1167 1168 // all other operands require a register 1169 return mustHaveRegister; 1170 } 1171 1172 1173 void LinearScan::handle_method_arguments(LIR_Op* op) { 1174 // special handling for method arguments (moves from stack to virtual register): 1175 // the interval gets no register assigned, but the stack slot. 1176 // it is split before the first use by the register allocator. 1177 1178 if (op->code() == lir_move) { 1179 assert(op->as_Op1() != NULL, "must be LIR_Op1"); 1180 LIR_Op1* move = (LIR_Op1*)op; 1181 1182 if (move->in_opr()->is_stack()) { 1183 #ifdef ASSERT 1184 int arg_size = compilation()->method()->arg_size(); 1185 LIR_Opr o = move->in_opr(); 1186 if (o->is_single_stack()) { 1187 assert(o->single_stack_ix() >= 0 && o->single_stack_ix() < arg_size, "out of range"); 1188 } else if (o->is_double_stack()) { 1189 assert(o->double_stack_ix() >= 0 && o->double_stack_ix() < arg_size, "out of range"); 1190 } else { 1191 ShouldNotReachHere(); 1192 } 1193 1194 assert(move->id() > 0, "invalid id"); 1195 assert(block_of_op_with_id(move->id())->number_of_preds() == 0, "move from stack must be in first block"); 1196 assert(move->result_opr()->is_virtual(), "result of move must be a virtual register"); 1197 1198 TRACE_LINEAR_SCAN(4, tty->print_cr("found move from stack slot %d to vreg %d", o->is_single_stack() ? o->single_stack_ix() : o->double_stack_ix(), reg_num(move->result_opr()))); 1199 #endif 1200 1201 Interval* interval = interval_at(reg_num(move->result_opr())); 1202 1203 int stack_slot = LinearScan::nof_regs + (move->in_opr()->is_single_stack() ? move->in_opr()->single_stack_ix() : move->in_opr()->double_stack_ix()); 1204 interval->set_canonical_spill_slot(stack_slot); 1205 interval->assign_reg(stack_slot); 1206 } 1207 } 1208 } 1209 1210 void LinearScan::handle_doubleword_moves(LIR_Op* op) { 1211 // special handling for doubleword move from memory to register: 1212 // in this case the registers of the input address and the result 1213 // registers must not overlap -> add a temp range for the input registers 1214 if (op->code() == lir_move) { 1215 assert(op->as_Op1() != NULL, "must be LIR_Op1"); 1216 LIR_Op1* move = (LIR_Op1*)op; 1217 1218 if (move->result_opr()->is_double_cpu() && move->in_opr()->is_pointer()) { 1219 LIR_Address* address = move->in_opr()->as_address_ptr(); 1220 if (address != NULL) { 1221 if (address->base()->is_valid()) { 1222 add_temp(address->base(), op->id(), noUse); 1223 } 1224 if (address->index()->is_valid()) { 1225 add_temp(address->index(), op->id(), noUse); 1226 } 1227 } 1228 } 1229 } 1230 } 1231 1232 void LinearScan::add_register_hints(LIR_Op* op) { 1233 switch (op->code()) { 1234 case lir_move: // fall through 1235 case lir_convert: { 1236 assert(op->as_Op1() != NULL, "lir_move, lir_convert must be LIR_Op1"); 1237 LIR_Op1* move = (LIR_Op1*)op; 1238 1239 LIR_Opr move_from = move->in_opr(); 1240 LIR_Opr move_to = move->result_opr(); 1241 1242 if (move_to->is_register() && move_from->is_register()) { 1243 Interval* from = interval_at(reg_num(move_from)); 1244 Interval* to = interval_at(reg_num(move_to)); 1245 if (from != NULL && to != NULL) { 1246 to->set_register_hint(from); 1247 TRACE_LINEAR_SCAN(4, tty->print_cr("operation at op_id %d: added hint from interval %d to %d", move->id(), from->reg_num(), to->reg_num())); 1248 } 1249 } 1250 break; 1251 } 1252 case lir_cmove: { 1253 assert(op->as_Op2() != NULL, "lir_cmove must be LIR_Op2"); 1254 LIR_Op2* cmove = (LIR_Op2*)op; 1255 1256 LIR_Opr move_from = cmove->in_opr1(); 1257 LIR_Opr move_to = cmove->result_opr(); 1258 1259 if (move_to->is_register() && move_from->is_register()) { 1260 Interval* from = interval_at(reg_num(move_from)); 1261 Interval* to = interval_at(reg_num(move_to)); 1262 if (from != NULL && to != NULL) { 1263 to->set_register_hint(from); 1264 TRACE_LINEAR_SCAN(4, tty->print_cr("operation at op_id %d: added hint from interval %d to %d", cmove->id(), from->reg_num(), to->reg_num())); 1265 } 1266 } 1267 break; 1268 } 1269 } 1270 } 1271 1272 1273 void LinearScan::build_intervals() { 1274 TIME_LINEAR_SCAN(timer_build_intervals); 1275 1276 // initialize interval list with expected number of intervals 1277 // (32 is added to have some space for split children without having to resize the list) 1278 _intervals = IntervalList(num_virtual_regs() + 32); 1279 // initialize all slots that are used by build_intervals 1280 _intervals.at_put_grow(num_virtual_regs() - 1, NULL, NULL); 1281 1282 // create a list with all caller-save registers (cpu, fpu, xmm) 1283 // when an instruction is a call, a temp range is created for all these registers 1284 int num_caller_save_registers = 0; 1285 int caller_save_registers[LinearScan::nof_regs]; 1286 1287 int i; 1288 for (i = 0; i < FrameMap::nof_caller_save_cpu_regs(); i++) { 1289 LIR_Opr opr = FrameMap::caller_save_cpu_reg_at(i); 1290 assert(opr->is_valid() && opr->is_register(), "FrameMap should not return invalid operands"); 1291 assert(reg_numHi(opr) == -1, "missing addition of range for hi-register"); 1292 caller_save_registers[num_caller_save_registers++] = reg_num(opr); 1293 } 1294 1295 // temp ranges for fpu registers are only created when the method has 1296 // virtual fpu operands. Otherwise no allocation for fpu registers is 1297 // perfomed and so the temp ranges would be useless 1298 if (has_fpu_registers()) { 1299 #ifdef X86 1300 if (UseSSE < 2) { 1301 #endif 1302 for (i = 0; i < FrameMap::nof_caller_save_fpu_regs; i++) { 1303 LIR_Opr opr = FrameMap::caller_save_fpu_reg_at(i); 1304 assert(opr->is_valid() && opr->is_register(), "FrameMap should not return invalid operands"); 1305 assert(reg_numHi(opr) == -1, "missing addition of range for hi-register"); 1306 caller_save_registers[num_caller_save_registers++] = reg_num(opr); 1307 } 1308 #ifdef X86 1309 } 1310 if (UseSSE > 0) { 1311 for (i = 0; i < FrameMap::nof_caller_save_xmm_regs; i++) { 1312 LIR_Opr opr = FrameMap::caller_save_xmm_reg_at(i); 1313 assert(opr->is_valid() && opr->is_register(), "FrameMap should not return invalid operands"); 1314 assert(reg_numHi(opr) == -1, "missing addition of range for hi-register"); 1315 caller_save_registers[num_caller_save_registers++] = reg_num(opr); 1316 } 1317 } 1318 #endif 1319 } 1320 assert(num_caller_save_registers <= LinearScan::nof_regs, "out of bounds"); 1321 1322 1323 LIR_OpVisitState visitor; 1324 1325 // iterate all blocks in reverse order 1326 for (i = block_count() - 1; i >= 0; i--) { 1327 BlockBegin* block = block_at(i); 1328 LIR_OpList* instructions = block->lir()->instructions_list(); 1329 int block_from = block->first_lir_instruction_id(); 1330 int block_to = block->last_lir_instruction_id(); 1331 1332 assert(block_from == instructions->at(0)->id(), "must be"); 1333 assert(block_to == instructions->at(instructions->length() - 1)->id(), "must be"); 1334 1335 // Update intervals for registers live at the end of this block; 1336 BitMap live = block->live_out(); 1337 int size = (int)live.size(); 1338 for (int number = (int)live.get_next_one_offset(0, size); number < size; number = (int)live.get_next_one_offset(number + 1, size)) { 1339 assert(live.at(number), "should not stop here otherwise"); 1340 assert(number >= LIR_OprDesc::vreg_base, "fixed intervals must not be live on block bounds"); 1341 TRACE_LINEAR_SCAN(2, tty->print_cr("live in %d to %d", number, block_to + 2)); 1342 1343 add_use(number, block_from, block_to + 2, noUse, T_ILLEGAL); 1344 1345 // add special use positions for loop-end blocks when the 1346 // interval is used anywhere inside this loop. It's possible 1347 // that the block was part of a non-natural loop, so it might 1348 // have an invalid loop index. 1349 if (block->is_set(BlockBegin::linear_scan_loop_end_flag) && 1350 block->loop_index() != -1 && 1351 is_interval_in_loop(number, block->loop_index())) { 1352 interval_at(number)->add_use_pos(block_to + 1, loopEndMarker); 1353 } 1354 } 1355 1356 // iterate all instructions of the block in reverse order. 1357 // skip the first instruction because it is always a label 1358 // definitions of intervals are processed before uses 1359 assert(visitor.no_operands(instructions->at(0)), "first operation must always be a label"); 1360 for (int j = instructions->length() - 1; j >= 1; j--) { 1361 LIR_Op* op = instructions->at(j); 1362 int op_id = op->id(); 1363 1364 // visit operation to collect all operands 1365 visitor.visit(op); 1366 1367 // add a temp range for each register if operation destroys caller-save registers 1368 if (visitor.has_call()) { 1369 for (int k = 0; k < num_caller_save_registers; k++) { 1370 add_temp(caller_save_registers[k], op_id, noUse, T_ILLEGAL); 1371 } 1372 TRACE_LINEAR_SCAN(4, tty->print_cr("operation destroys all caller-save registers")); 1373 } 1374 1375 // Add any platform dependent temps 1376 pd_add_temps(op); 1377 1378 // visit definitions (output and temp operands) 1379 int k, n; 1380 n = visitor.opr_count(LIR_OpVisitState::outputMode); 1381 for (k = 0; k < n; k++) { 1382 LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::outputMode, k); 1383 assert(opr->is_register(), "visitor should only return register operands"); 1384 add_def(opr, op_id, use_kind_of_output_operand(op, opr)); 1385 } 1386 1387 n = visitor.opr_count(LIR_OpVisitState::tempMode); 1388 for (k = 0; k < n; k++) { 1389 LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::tempMode, k); 1390 assert(opr->is_register(), "visitor should only return register operands"); 1391 add_temp(opr, op_id, mustHaveRegister); 1392 } 1393 1394 // visit uses (input operands) 1395 n = visitor.opr_count(LIR_OpVisitState::inputMode); 1396 for (k = 0; k < n; k++) { 1397 LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::inputMode, k); 1398 assert(opr->is_register(), "visitor should only return register operands"); 1399 add_use(opr, block_from, op_id, use_kind_of_input_operand(op, opr)); 1400 } 1401 1402 // Add uses of live locals from interpreter's point of view for proper 1403 // debug information generation 1404 // Treat these operands as temp values (if the life range is extended 1405 // to a call site, the value would be in a register at the call otherwise) 1406 n = visitor.info_count(); 1407 for (k = 0; k < n; k++) { 1408 CodeEmitInfo* info = visitor.info_at(k); 1409 ValueStack* stack = info->stack(); 1410 for_each_state_value(stack, value, 1411 add_use(value, block_from, op_id + 1, noUse); 1412 ); 1413 } 1414 1415 // special steps for some instructions (especially moves) 1416 handle_method_arguments(op); 1417 handle_doubleword_moves(op); 1418 add_register_hints(op); 1419 1420 } // end of instruction iteration 1421 } // end of block iteration 1422 1423 1424 // add the range [0, 1[ to all fixed intervals 1425 // -> the register allocator need not handle unhandled fixed intervals 1426 for (int n = 0; n < LinearScan::nof_regs; n++) { 1427 Interval* interval = interval_at(n); 1428 if (interval != NULL) { 1429 interval->add_range(0, 1); 1430 } 1431 } 1432 } 1433 1434 1435 // ********** Phase 5: actual register allocation 1436 1437 int LinearScan::interval_cmp(Interval** a, Interval** b) { 1438 if (*a != NULL) { 1439 if (*b != NULL) { 1440 return (*a)->from() - (*b)->from(); 1441 } else { 1442 return -1; 1443 } 1444 } else { 1445 if (*b != NULL) { 1446 return 1; 1447 } else { 1448 return 0; 1449 } 1450 } 1451 } 1452 1453 #ifndef PRODUCT 1454 bool LinearScan::is_sorted(IntervalArray* intervals) { 1455 int from = -1; 1456 int i, j; 1457 for (i = 0; i < intervals->length(); i ++) { 1458 Interval* it = intervals->at(i); 1459 if (it != NULL) { 1460 if (from > it->from()) { 1461 assert(false, ""); 1462 return false; 1463 } 1464 from = it->from(); 1465 } 1466 } 1467 1468 // check in both directions if sorted list and unsorted list contain same intervals 1469 for (i = 0; i < interval_count(); i++) { 1470 if (interval_at(i) != NULL) { 1471 int num_found = 0; 1472 for (j = 0; j < intervals->length(); j++) { 1473 if (interval_at(i) == intervals->at(j)) { 1474 num_found++; 1475 } 1476 } 1477 assert(num_found == 1, "lists do not contain same intervals"); 1478 } 1479 } 1480 for (j = 0; j < intervals->length(); j++) { 1481 int num_found = 0; 1482 for (i = 0; i < interval_count(); i++) { 1483 if (interval_at(i) == intervals->at(j)) { 1484 num_found++; 1485 } 1486 } 1487 assert(num_found == 1, "lists do not contain same intervals"); 1488 } 1489 1490 return true; 1491 } 1492 #endif 1493 1494 void LinearScan::add_to_list(Interval** first, Interval** prev, Interval* interval) { 1495 if (*prev != NULL) { 1496 (*prev)->set_next(interval); 1497 } else { 1498 *first = interval; 1499 } 1500 *prev = interval; 1501 } 1502 1503 void LinearScan::create_unhandled_lists(Interval** list1, Interval** list2, bool (is_list1)(const Interval* i), bool (is_list2)(const Interval* i)) { 1504 assert(is_sorted(_sorted_intervals), "interval list is not sorted"); 1505 1506 *list1 = *list2 = Interval::end(); 1507 1508 Interval* list1_prev = NULL; 1509 Interval* list2_prev = NULL; 1510 Interval* v; 1511 1512 const int n = _sorted_intervals->length(); 1513 for (int i = 0; i < n; i++) { 1514 v = _sorted_intervals->at(i); 1515 if (v == NULL) continue; 1516 1517 if (is_list1(v)) { 1518 add_to_list(list1, &list1_prev, v); 1519 } else if (is_list2 == NULL || is_list2(v)) { 1520 add_to_list(list2, &list2_prev, v); 1521 } 1522 } 1523 1524 if (list1_prev != NULL) list1_prev->set_next(Interval::end()); 1525 if (list2_prev != NULL) list2_prev->set_next(Interval::end()); 1526 1527 assert(list1_prev == NULL || list1_prev->next() == Interval::end(), "linear list ends not with sentinel"); 1528 assert(list2_prev == NULL || list2_prev->next() == Interval::end(), "linear list ends not with sentinel"); 1529 } 1530 1531 1532 void LinearScan::sort_intervals_before_allocation() { 1533 TIME_LINEAR_SCAN(timer_sort_intervals_before); 1534 1535 if (_needs_full_resort) { 1536 // There is no known reason why this should occur but just in case... 1537 assert(false, "should never occur"); 1538 // Re-sort existing interval list because an Interval::from() has changed 1539 _sorted_intervals->sort(interval_cmp); 1540 _needs_full_resort = false; 1541 } 1542 1543 IntervalList* unsorted_list = &_intervals; 1544 int unsorted_len = unsorted_list->length(); 1545 int sorted_len = 0; 1546 int unsorted_idx; 1547 int sorted_idx = 0; 1548 int sorted_from_max = -1; 1549 1550 // calc number of items for sorted list (sorted list must not contain NULL values) 1551 for (unsorted_idx = 0; unsorted_idx < unsorted_len; unsorted_idx++) { 1552 if (unsorted_list->at(unsorted_idx) != NULL) { 1553 sorted_len++; 1554 } 1555 } 1556 IntervalArray* sorted_list = new IntervalArray(sorted_len); 1557 1558 // special sorting algorithm: the original interval-list is almost sorted, 1559 // only some intervals are swapped. So this is much faster than a complete QuickSort 1560 for (unsorted_idx = 0; unsorted_idx < unsorted_len; unsorted_idx++) { 1561 Interval* cur_interval = unsorted_list->at(unsorted_idx); 1562 1563 if (cur_interval != NULL) { 1564 int cur_from = cur_interval->from(); 1565 1566 if (sorted_from_max <= cur_from) { 1567 sorted_list->at_put(sorted_idx++, cur_interval); 1568 sorted_from_max = cur_interval->from(); 1569 } else { 1570 // the asumption that the intervals are already sorted failed, 1571 // so this interval must be sorted in manually 1572 int j; 1573 for (j = sorted_idx - 1; j >= 0 && cur_from < sorted_list->at(j)->from(); j--) { 1574 sorted_list->at_put(j + 1, sorted_list->at(j)); 1575 } 1576 sorted_list->at_put(j + 1, cur_interval); 1577 sorted_idx++; 1578 } 1579 } 1580 } 1581 _sorted_intervals = sorted_list; 1582 assert(is_sorted(_sorted_intervals), "intervals unsorted"); 1583 } 1584 1585 void LinearScan::sort_intervals_after_allocation() { 1586 TIME_LINEAR_SCAN(timer_sort_intervals_after); 1587 1588 if (_needs_full_resort) { 1589 // Re-sort existing interval list because an Interval::from() has changed 1590 _sorted_intervals->sort(interval_cmp); 1591 _needs_full_resort = false; 1592 } 1593 1594 IntervalArray* old_list = _sorted_intervals; 1595 IntervalList* new_list = _new_intervals_from_allocation; 1596 int old_len = old_list->length(); 1597 int new_len = new_list->length(); 1598 1599 if (new_len == 0) { 1600 // no intervals have been added during allocation, so sorted list is already up to date 1601 assert(is_sorted(_sorted_intervals), "intervals unsorted"); 1602 return; 1603 } 1604 1605 // conventional sort-algorithm for new intervals 1606 new_list->sort(interval_cmp); 1607 1608 // merge old and new list (both already sorted) into one combined list 1609 IntervalArray* combined_list = new IntervalArray(old_len + new_len); 1610 int old_idx = 0; 1611 int new_idx = 0; 1612 1613 while (old_idx + new_idx < old_len + new_len) { 1614 if (new_idx >= new_len || (old_idx < old_len && old_list->at(old_idx)->from() <= new_list->at(new_idx)->from())) { 1615 combined_list->at_put(old_idx + new_idx, old_list->at(old_idx)); 1616 old_idx++; 1617 } else { 1618 combined_list->at_put(old_idx + new_idx, new_list->at(new_idx)); 1619 new_idx++; 1620 } 1621 } 1622 1623 _sorted_intervals = combined_list; 1624 assert(is_sorted(_sorted_intervals), "intervals unsorted"); 1625 } 1626 1627 1628 void LinearScan::allocate_registers() { 1629 TIME_LINEAR_SCAN(timer_allocate_registers); 1630 1631 Interval* precolored_cpu_intervals, *not_precolored_cpu_intervals; 1632 Interval* precolored_fpu_intervals, *not_precolored_fpu_intervals; 1633 1634 // allocate cpu registers 1635 create_unhandled_lists(&precolored_cpu_intervals, ¬_precolored_cpu_intervals, 1636 is_precolored_cpu_interval, is_virtual_cpu_interval); 1637 1638 // allocate fpu registers 1639 create_unhandled_lists(&precolored_fpu_intervals, ¬_precolored_fpu_intervals, 1640 is_precolored_fpu_interval, is_virtual_fpu_interval); 1641 1642 // the fpu interval allocation cannot be moved down below with the fpu section as 1643 // the cpu_lsw.walk() changes interval positions. 1644 1645 LinearScanWalker cpu_lsw(this, precolored_cpu_intervals, not_precolored_cpu_intervals); 1646 cpu_lsw.walk(); 1647 cpu_lsw.finish_allocation(); 1648 1649 if (has_fpu_registers()) { 1650 LinearScanWalker fpu_lsw(this, precolored_fpu_intervals, not_precolored_fpu_intervals); 1651 fpu_lsw.walk(); 1652 fpu_lsw.finish_allocation(); 1653 } 1654 } 1655 1656 1657 // ********** Phase 6: resolve data flow 1658 // (insert moves at edges between blocks if intervals have been split) 1659 1660 // wrapper for Interval::split_child_at_op_id that performs a bailout in product mode 1661 // instead of returning NULL 1662 Interval* LinearScan::split_child_at_op_id(Interval* interval, int op_id, LIR_OpVisitState::OprMode mode) { 1663 Interval* result = interval->split_child_at_op_id(op_id, mode); 1664 if (result != NULL) { 1665 return result; 1666 } 1667 1668 assert(false, "must find an interval, but do a clean bailout in product mode"); 1669 result = new Interval(LIR_OprDesc::vreg_base); 1670 result->assign_reg(0); 1671 result->set_type(T_INT); 1672 BAILOUT_("LinearScan: interval is NULL", result); 1673 } 1674 1675 1676 Interval* LinearScan::interval_at_block_begin(BlockBegin* block, int reg_num) { 1677 assert(LinearScan::nof_regs <= reg_num && reg_num < num_virtual_regs(), "register number out of bounds"); 1678 assert(interval_at(reg_num) != NULL, "no interval found"); 1679 1680 return split_child_at_op_id(interval_at(reg_num), block->first_lir_instruction_id(), LIR_OpVisitState::outputMode); 1681 } 1682 1683 Interval* LinearScan::interval_at_block_end(BlockBegin* block, int reg_num) { 1684 assert(LinearScan::nof_regs <= reg_num && reg_num < num_virtual_regs(), "register number out of bounds"); 1685 assert(interval_at(reg_num) != NULL, "no interval found"); 1686 1687 return split_child_at_op_id(interval_at(reg_num), block->last_lir_instruction_id() + 1, LIR_OpVisitState::outputMode); 1688 } 1689 1690 Interval* LinearScan::interval_at_op_id(int reg_num, int op_id) { 1691 assert(LinearScan::nof_regs <= reg_num && reg_num < num_virtual_regs(), "register number out of bounds"); 1692 assert(interval_at(reg_num) != NULL, "no interval found"); 1693 1694 return split_child_at_op_id(interval_at(reg_num), op_id, LIR_OpVisitState::inputMode); 1695 } 1696 1697 1698 void LinearScan::resolve_collect_mappings(BlockBegin* from_block, BlockBegin* to_block, MoveResolver &move_resolver) { 1699 DEBUG_ONLY(move_resolver.check_empty()); 1700 1701 const int num_regs = num_virtual_regs(); 1702 const int size = live_set_size(); 1703 const BitMap live_at_edge = to_block->live_in(); 1704 1705 // visit all registers where the live_at_edge bit is set 1706 for (int r = (int)live_at_edge.get_next_one_offset(0, size); r < size; r = (int)live_at_edge.get_next_one_offset(r + 1, size)) { 1707 assert(r < num_regs, "live information set for not exisiting interval"); 1708 assert(from_block->live_out().at(r) && to_block->live_in().at(r), "interval not live at this edge"); 1709 1710 Interval* from_interval = interval_at_block_end(from_block, r); 1711 Interval* to_interval = interval_at_block_begin(to_block, r); 1712 1713 if (from_interval != to_interval && (from_interval->assigned_reg() != to_interval->assigned_reg() || from_interval->assigned_regHi() != to_interval->assigned_regHi())) { 1714 // need to insert move instruction 1715 move_resolver.add_mapping(from_interval, to_interval); 1716 } 1717 } 1718 } 1719 1720 1721 void LinearScan::resolve_find_insert_pos(BlockBegin* from_block, BlockBegin* to_block, MoveResolver &move_resolver) { 1722 if (from_block->number_of_sux() <= 1) { 1723 TRACE_LINEAR_SCAN(4, tty->print_cr("inserting moves at end of from_block B%d", from_block->block_id())); 1724 1725 LIR_OpList* instructions = from_block->lir()->instructions_list(); 1726 LIR_OpBranch* branch = instructions->last()->as_OpBranch(); 1727 if (branch != NULL) { 1728 // insert moves before branch 1729 assert(branch->cond() == lir_cond_always, "block does not end with an unconditional jump"); 1730 move_resolver.set_insert_position(from_block->lir(), instructions->length() - 2); 1731 } else { 1732 move_resolver.set_insert_position(from_block->lir(), instructions->length() - 1); 1733 } 1734 1735 } else { 1736 TRACE_LINEAR_SCAN(4, tty->print_cr("inserting moves at beginning of to_block B%d", to_block->block_id())); 1737 #ifdef ASSERT 1738 assert(from_block->lir()->instructions_list()->at(0)->as_OpLabel() != NULL, "block does not start with a label"); 1739 1740 // because the number of predecessor edges matches the number of 1741 // successor edges, blocks which are reached by switch statements 1742 // may have be more than one predecessor but it will be guaranteed 1743 // that all predecessors will be the same. 1744 for (int i = 0; i < to_block->number_of_preds(); i++) { 1745 assert(from_block == to_block->pred_at(i), "all critical edges must be broken"); 1746 } 1747 #endif 1748 1749 move_resolver.set_insert_position(to_block->lir(), 0); 1750 } 1751 } 1752 1753 1754 // insert necessary moves (spilling or reloading) at edges between blocks if interval has been split 1755 void LinearScan::resolve_data_flow() { 1756 TIME_LINEAR_SCAN(timer_resolve_data_flow); 1757 1758 int num_blocks = block_count(); 1759 MoveResolver move_resolver(this); 1760 BitMap block_completed(num_blocks); block_completed.clear(); 1761 BitMap already_resolved(num_blocks); already_resolved.clear(); 1762 1763 int i; 1764 for (i = 0; i < num_blocks; i++) { 1765 BlockBegin* block = block_at(i); 1766 1767 // check if block has only one predecessor and only one successor 1768 if (block->number_of_preds() == 1 && block->number_of_sux() == 1 && block->number_of_exception_handlers() == 0) { 1769 LIR_OpList* instructions = block->lir()->instructions_list(); 1770 assert(instructions->at(0)->code() == lir_label, "block must start with label"); 1771 assert(instructions->last()->code() == lir_branch, "block with successors must end with branch"); 1772 assert(instructions->last()->as_OpBranch()->cond() == lir_cond_always, "block with successor must end with unconditional branch"); 1773 1774 // check if block is empty (only label and branch) 1775 if (instructions->length() == 2) { 1776 BlockBegin* pred = block->pred_at(0); 1777 BlockBegin* sux = block->sux_at(0); 1778 1779 // prevent optimization of two consecutive blocks 1780 if (!block_completed.at(pred->linear_scan_number()) && !block_completed.at(sux->linear_scan_number())) { 1781 TRACE_LINEAR_SCAN(3, tty->print_cr("**** optimizing empty block B%d (pred: B%d, sux: B%d)", block->block_id(), pred->block_id(), sux->block_id())); 1782 block_completed.set_bit(block->linear_scan_number()); 1783 1784 // directly resolve between pred and sux (without looking at the empty block between) 1785 resolve_collect_mappings(pred, sux, move_resolver); 1786 if (move_resolver.has_mappings()) { 1787 move_resolver.set_insert_position(block->lir(), 0); 1788 move_resolver.resolve_and_append_moves(); 1789 } 1790 } 1791 } 1792 } 1793 } 1794 1795 1796 for (i = 0; i < num_blocks; i++) { 1797 if (!block_completed.at(i)) { 1798 BlockBegin* from_block = block_at(i); 1799 already_resolved.set_from(block_completed); 1800 1801 int num_sux = from_block->number_of_sux(); 1802 for (int s = 0; s < num_sux; s++) { 1803 BlockBegin* to_block = from_block->sux_at(s); 1804 1805 // check for duplicate edges between the same blocks (can happen with switch blocks) 1806 if (!already_resolved.at(to_block->linear_scan_number())) { 1807 TRACE_LINEAR_SCAN(3, tty->print_cr("**** processing edge between B%d and B%d", from_block->block_id(), to_block->block_id())); 1808 already_resolved.set_bit(to_block->linear_scan_number()); 1809 1810 // collect all intervals that have been split between from_block and to_block 1811 resolve_collect_mappings(from_block, to_block, move_resolver); 1812 if (move_resolver.has_mappings()) { 1813 resolve_find_insert_pos(from_block, to_block, move_resolver); 1814 move_resolver.resolve_and_append_moves(); 1815 } 1816 } 1817 } 1818 } 1819 } 1820 } 1821 1822 1823 void LinearScan::resolve_exception_entry(BlockBegin* block, int reg_num, MoveResolver &move_resolver) { 1824 if (interval_at(reg_num) == NULL) { 1825 // if a phi function is never used, no interval is created -> ignore this 1826 return; 1827 } 1828 1829 Interval* interval = interval_at_block_begin(block, reg_num); 1830 int reg = interval->assigned_reg(); 1831 int regHi = interval->assigned_regHi(); 1832 1833 if ((reg < nof_regs && interval->always_in_memory()) || 1834 (use_fpu_stack_allocation() && reg >= pd_first_fpu_reg && reg <= pd_last_fpu_reg)) { 1835 // the interval is split to get a short range that is located on the stack 1836 // in the following two cases: 1837 // * the interval started in memory (e.g. method parameter), but is currently in a register 1838 // this is an optimization for exception handling that reduces the number of moves that 1839 // are necessary for resolving the states when an exception uses this exception handler 1840 // * the interval would be on the fpu stack at the begin of the exception handler 1841 // this is not allowed because of the complicated fpu stack handling on Intel 1842 1843 // range that will be spilled to memory 1844 int from_op_id = block->first_lir_instruction_id(); 1845 int to_op_id = from_op_id + 1; // short live range of length 1 1846 assert(interval->from() <= from_op_id && interval->to() >= to_op_id, 1847 "no split allowed between exception entry and first instruction"); 1848 1849 if (interval->from() != from_op_id) { 1850 // the part before from_op_id is unchanged 1851 interval = interval->split(from_op_id); 1852 interval->assign_reg(reg, regHi); 1853 append_interval(interval); 1854 } else { 1855 _needs_full_resort = true; 1856 } 1857 assert(interval->from() == from_op_id, "must be true now"); 1858 1859 Interval* spilled_part = interval; 1860 if (interval->to() != to_op_id) { 1861 // the part after to_op_id is unchanged 1862 spilled_part = interval->split_from_start(to_op_id); 1863 append_interval(spilled_part); 1864 move_resolver.add_mapping(spilled_part, interval); 1865 } 1866 assign_spill_slot(spilled_part); 1867 1868 assert(spilled_part->from() == from_op_id && spilled_part->to() == to_op_id, "just checking"); 1869 } 1870 } 1871 1872 void LinearScan::resolve_exception_entry(BlockBegin* block, MoveResolver &move_resolver) { 1873 assert(block->is_set(BlockBegin::exception_entry_flag), "should not call otherwise"); 1874 DEBUG_ONLY(move_resolver.check_empty()); 1875 1876 // visit all registers where the live_in bit is set 1877 int size = live_set_size(); 1878 for (int r = (int)block->live_in().get_next_one_offset(0, size); r < size; r = (int)block->live_in().get_next_one_offset(r + 1, size)) { 1879 resolve_exception_entry(block, r, move_resolver); 1880 } 1881 1882 // the live_in bits are not set for phi functions of the xhandler entry, so iterate them separately 1883 for_each_phi_fun(block, phi, 1884 resolve_exception_entry(block, phi->operand()->vreg_number(), move_resolver) 1885 ); 1886 1887 if (move_resolver.has_mappings()) { 1888 // insert moves after first instruction 1889 move_resolver.set_insert_position(block->lir(), 0); 1890 move_resolver.resolve_and_append_moves(); 1891 } 1892 } 1893 1894 1895 void LinearScan::resolve_exception_edge(XHandler* handler, int throwing_op_id, int reg_num, Phi* phi, MoveResolver &move_resolver) { 1896 if (interval_at(reg_num) == NULL) { 1897 // if a phi function is never used, no interval is created -> ignore this 1898 return; 1899 } 1900 1901 // the computation of to_interval is equal to resolve_collect_mappings, 1902 // but from_interval is more complicated because of phi functions 1903 BlockBegin* to_block = handler->entry_block(); 1904 Interval* to_interval = interval_at_block_begin(to_block, reg_num); 1905 1906 if (phi != NULL) { 1907 // phi function of the exception entry block 1908 // no moves are created for this phi function in the LIR_Generator, so the 1909 // interval at the throwing instruction must be searched using the operands 1910 // of the phi function 1911 Value from_value = phi->operand_at(handler->phi_operand()); 1912 1913 // with phi functions it can happen that the same from_value is used in 1914 // multiple mappings, so notify move-resolver that this is allowed 1915 move_resolver.set_multiple_reads_allowed(); 1916 1917 Constant* con = from_value->as_Constant(); 1918 if (con != NULL && !con->is_pinned()) { 1919 // unpinned constants may have no register, so add mapping from constant to interval 1920 move_resolver.add_mapping(LIR_OprFact::value_type(con->type()), to_interval); 1921 } else { 1922 // search split child at the throwing op_id 1923 Interval* from_interval = interval_at_op_id(from_value->operand()->vreg_number(), throwing_op_id); 1924 move_resolver.add_mapping(from_interval, to_interval); 1925 } 1926 1927 } else { 1928 // no phi function, so use reg_num also for from_interval 1929 // search split child at the throwing op_id 1930 Interval* from_interval = interval_at_op_id(reg_num, throwing_op_id); 1931 if (from_interval != to_interval) { 1932 // optimization to reduce number of moves: when to_interval is on stack and 1933 // the stack slot is known to be always correct, then no move is necessary 1934 if (!from_interval->always_in_memory() || from_interval->canonical_spill_slot() != to_interval->assigned_reg()) { 1935 move_resolver.add_mapping(from_interval, to_interval); 1936 } 1937 } 1938 } 1939 } 1940 1941 void LinearScan::resolve_exception_edge(XHandler* handler, int throwing_op_id, MoveResolver &move_resolver) { 1942 TRACE_LINEAR_SCAN(4, tty->print_cr("resolving exception handler B%d: throwing_op_id=%d", handler->entry_block()->block_id(), throwing_op_id)); 1943 1944 DEBUG_ONLY(move_resolver.check_empty()); 1945 assert(handler->lir_op_id() == -1, "already processed this xhandler"); 1946 DEBUG_ONLY(handler->set_lir_op_id(throwing_op_id)); 1947 assert(handler->entry_code() == NULL, "code already present"); 1948 1949 // visit all registers where the live_in bit is set 1950 BlockBegin* block = handler->entry_block(); 1951 int size = live_set_size(); 1952 for (int r = (int)block->live_in().get_next_one_offset(0, size); r < size; r = (int)block->live_in().get_next_one_offset(r + 1, size)) { 1953 resolve_exception_edge(handler, throwing_op_id, r, NULL, move_resolver); 1954 } 1955 1956 // the live_in bits are not set for phi functions of the xhandler entry, so iterate them separately 1957 for_each_phi_fun(block, phi, 1958 resolve_exception_edge(handler, throwing_op_id, phi->operand()->vreg_number(), phi, move_resolver) 1959 ); 1960 1961 if (move_resolver.has_mappings()) { 1962 LIR_List* entry_code = new LIR_List(compilation()); 1963 move_resolver.set_insert_position(entry_code, 0); 1964 move_resolver.resolve_and_append_moves(); 1965 1966 entry_code->jump(handler->entry_block()); 1967 handler->set_entry_code(entry_code); 1968 } 1969 } 1970 1971 1972 void LinearScan::resolve_exception_handlers() { 1973 MoveResolver move_resolver(this); 1974 LIR_OpVisitState visitor; 1975 int num_blocks = block_count(); 1976 1977 int i; 1978 for (i = 0; i < num_blocks; i++) { 1979 BlockBegin* block = block_at(i); 1980 if (block->is_set(BlockBegin::exception_entry_flag)) { 1981 resolve_exception_entry(block, move_resolver); 1982 } 1983 } 1984 1985 for (i = 0; i < num_blocks; i++) { 1986 BlockBegin* block = block_at(i); 1987 LIR_List* ops = block->lir(); 1988 int num_ops = ops->length(); 1989 1990 // iterate all instructions of the block. skip the first because it is always a label 1991 assert(visitor.no_operands(ops->at(0)), "first operation must always be a label"); 1992 for (int j = 1; j < num_ops; j++) { 1993 LIR_Op* op = ops->at(j); 1994 int op_id = op->id(); 1995 1996 if (op_id != -1 && has_info(op_id)) { 1997 // visit operation to collect all operands 1998 visitor.visit(op); 1999 assert(visitor.info_count() > 0, "should not visit otherwise"); 2000 2001 XHandlers* xhandlers = visitor.all_xhandler(); 2002 int n = xhandlers->length(); 2003 for (int k = 0; k < n; k++) { 2004 resolve_exception_edge(xhandlers->handler_at(k), op_id, move_resolver); 2005 } 2006 2007 #ifdef ASSERT 2008 } else { 2009 visitor.visit(op); 2010 assert(visitor.all_xhandler()->length() == 0, "missed exception handler"); 2011 #endif 2012 } 2013 } 2014 } 2015 } 2016 2017 2018 // ********** Phase 7: assign register numbers back to LIR 2019 // (includes computation of debug information and oop maps) 2020 2021 VMReg LinearScan::vm_reg_for_interval(Interval* interval) { 2022 VMReg reg = interval->cached_vm_reg(); 2023 if (!reg->is_valid() ) { 2024 reg = vm_reg_for_operand(operand_for_interval(interval)); 2025 interval->set_cached_vm_reg(reg); 2026 } 2027 assert(reg == vm_reg_for_operand(operand_for_interval(interval)), "wrong cached value"); 2028 return reg; 2029 } 2030 2031 VMReg LinearScan::vm_reg_for_operand(LIR_Opr opr) { 2032 assert(opr->is_oop(), "currently only implemented for oop operands"); 2033 return frame_map()->regname(opr); 2034 } 2035 2036 2037 LIR_Opr LinearScan::operand_for_interval(Interval* interval) { 2038 LIR_Opr opr = interval->cached_opr(); 2039 if (opr->is_illegal()) { 2040 opr = calc_operand_for_interval(interval); 2041 interval->set_cached_opr(opr); 2042 } 2043 2044 assert(opr == calc_operand_for_interval(interval), "wrong cached value"); 2045 return opr; 2046 } 2047 2048 LIR_Opr LinearScan::calc_operand_for_interval(const Interval* interval) { 2049 int assigned_reg = interval->assigned_reg(); 2050 BasicType type = interval->type(); 2051 2052 if (assigned_reg >= nof_regs) { 2053 // stack slot 2054 assert(interval->assigned_regHi() == any_reg, "must not have hi register"); 2055 return LIR_OprFact::stack(assigned_reg - nof_regs, type); 2056 2057 } else { 2058 // register 2059 switch (type) { 2060 case T_OBJECT: { 2061 assert(assigned_reg >= pd_first_cpu_reg && assigned_reg <= pd_last_cpu_reg, "no cpu register"); 2062 assert(interval->assigned_regHi() == any_reg, "must not have hi register"); 2063 return LIR_OprFact::single_cpu_oop(assigned_reg); 2064 } 2065 2066 case T_ADDRESS: { 2067 assert(assigned_reg >= pd_first_cpu_reg && assigned_reg <= pd_last_cpu_reg, "no cpu register"); 2068 assert(interval->assigned_regHi() == any_reg, "must not have hi register"); 2069 return LIR_OprFact::single_cpu_address(assigned_reg); 2070 } 2071 2072 case T_METADATA: { 2073 assert(assigned_reg >= pd_first_cpu_reg && assigned_reg <= pd_last_cpu_reg, "no cpu register"); 2074 assert(interval->assigned_regHi() == any_reg, "must not have hi register"); 2075 return LIR_OprFact::single_cpu_metadata(assigned_reg); 2076 } 2077 2078 #ifdef __SOFTFP__ 2079 case T_FLOAT: // fall through 2080 #endif // __SOFTFP__ 2081 case T_INT: { 2082 assert(assigned_reg >= pd_first_cpu_reg && assigned_reg <= pd_last_cpu_reg, "no cpu register"); 2083 assert(interval->assigned_regHi() == any_reg, "must not have hi register"); 2084 return LIR_OprFact::single_cpu(assigned_reg); 2085 } 2086 2087 #ifdef __SOFTFP__ 2088 case T_DOUBLE: // fall through 2089 #endif // __SOFTFP__ 2090 case T_LONG: { 2091 int assigned_regHi = interval->assigned_regHi(); 2092 assert(assigned_reg >= pd_first_cpu_reg && assigned_reg <= pd_last_cpu_reg, "no cpu register"); 2093 assert(num_physical_regs(T_LONG) == 1 || 2094 (assigned_regHi >= pd_first_cpu_reg && assigned_regHi <= pd_last_cpu_reg), "no cpu register"); 2095 2096 assert(assigned_reg != assigned_regHi, "invalid allocation"); 2097 assert(num_physical_regs(T_LONG) == 1 || assigned_reg < assigned_regHi, 2098 "register numbers must be sorted (ensure that e.g. a move from eax,ebx to ebx,eax can not occur)"); 2099 assert((assigned_regHi != any_reg) ^ (num_physical_regs(T_LONG) == 1), "must be match"); 2100 if (requires_adjacent_regs(T_LONG)) { 2101 assert(assigned_reg % 2 == 0 && assigned_reg + 1 == assigned_regHi, "must be sequential and even"); 2102 } 2103 2104 #ifdef _LP64 2105 return LIR_OprFact::double_cpu(assigned_reg, assigned_reg); 2106 #else 2107 #if defined(SPARC) || defined(PPC) 2108 return LIR_OprFact::double_cpu(assigned_regHi, assigned_reg); 2109 #else 2110 return LIR_OprFact::double_cpu(assigned_reg, assigned_regHi); 2111 #endif // SPARC 2112 #endif // LP64 2113 } 2114 2115 #ifndef __SOFTFP__ 2116 case T_FLOAT: { 2117 #ifdef X86 2118 if (UseSSE >= 1) { 2119 assert(assigned_reg >= pd_first_xmm_reg && assigned_reg <= pd_last_xmm_reg, "no xmm register"); 2120 assert(interval->assigned_regHi() == any_reg, "must not have hi register"); 2121 return LIR_OprFact::single_xmm(assigned_reg - pd_first_xmm_reg); 2122 } 2123 #endif 2124 2125 assert(assigned_reg >= pd_first_fpu_reg && assigned_reg <= pd_last_fpu_reg, "no fpu register"); 2126 assert(interval->assigned_regHi() == any_reg, "must not have hi register"); 2127 return LIR_OprFact::single_fpu(assigned_reg - pd_first_fpu_reg); 2128 } 2129 2130 case T_DOUBLE: { 2131 #ifdef X86 2132 if (UseSSE >= 2) { 2133 assert(assigned_reg >= pd_first_xmm_reg && assigned_reg <= pd_last_xmm_reg, "no xmm register"); 2134 assert(interval->assigned_regHi() == any_reg, "must not have hi register (double xmm values are stored in one register)"); 2135 return LIR_OprFact::double_xmm(assigned_reg - pd_first_xmm_reg); 2136 } 2137 #endif 2138 2139 #ifdef SPARC 2140 assert(assigned_reg >= pd_first_fpu_reg && assigned_reg <= pd_last_fpu_reg, "no fpu register"); 2141 assert(interval->assigned_regHi() >= pd_first_fpu_reg && interval->assigned_regHi() <= pd_last_fpu_reg, "no fpu register"); 2142 assert(assigned_reg % 2 == 0 && assigned_reg + 1 == interval->assigned_regHi(), "must be sequential and even"); 2143 LIR_Opr result = LIR_OprFact::double_fpu(interval->assigned_regHi() - pd_first_fpu_reg, assigned_reg - pd_first_fpu_reg); 2144 #elif defined(ARM32) || defined(AARCH32) 2145 assert(assigned_reg >= pd_first_fpu_reg && assigned_reg <= pd_last_fpu_reg, "no fpu register"); 2146 assert(interval->assigned_regHi() >= pd_first_fpu_reg && interval->assigned_regHi() <= pd_last_fpu_reg, "no fpu register"); 2147 assert(assigned_reg % 2 == 0 && assigned_reg + 1 == interval->assigned_regHi(), "must be sequential and even"); 2148 LIR_Opr result = LIR_OprFact::double_fpu(assigned_reg - pd_first_fpu_reg, interval->assigned_regHi() - pd_first_fpu_reg); 2149 #else 2150 assert(assigned_reg >= pd_first_fpu_reg && assigned_reg <= pd_last_fpu_reg, "no fpu register"); 2151 assert(interval->assigned_regHi() == any_reg, "must not have hi register (double fpu values are stored in one register on Intel)"); 2152 LIR_Opr result = LIR_OprFact::double_fpu(assigned_reg - pd_first_fpu_reg); 2153 #endif 2154 return result; 2155 } 2156 #endif // __SOFTFP__ 2157 2158 default: { 2159 ShouldNotReachHere(); 2160 return LIR_OprFact::illegalOpr; 2161 } 2162 } 2163 } 2164 } 2165 2166 LIR_Opr LinearScan::canonical_spill_opr(Interval* interval) { 2167 assert(interval->canonical_spill_slot() >= nof_regs, "canonical spill slot not set"); 2168 return LIR_OprFact::stack(interval->canonical_spill_slot() - nof_regs, interval->type()); 2169 } 2170 2171 LIR_Opr LinearScan::color_lir_opr(LIR_Opr opr, int op_id, LIR_OpVisitState::OprMode mode) { 2172 assert(opr->is_virtual(), "should not call this otherwise"); 2173 2174 Interval* interval = interval_at(opr->vreg_number()); 2175 assert(interval != NULL, "interval must exist"); 2176 2177 if (op_id != -1) { 2178 #ifdef ASSERT 2179 BlockBegin* block = block_of_op_with_id(op_id); 2180 if (block->number_of_sux() <= 1 && op_id == block->last_lir_instruction_id()) { 2181 // check if spill moves could have been appended at the end of this block, but 2182 // before the branch instruction. So the split child information for this branch would 2183 // be incorrect. 2184 LIR_OpBranch* branch = block->lir()->instructions_list()->last()->as_OpBranch(); 2185 if (branch != NULL) { 2186 if (block->live_out().at(opr->vreg_number())) { 2187 assert(branch->cond() == lir_cond_always, "block does not end with an unconditional jump"); 2188 assert(false, "can't get split child for the last branch of a block because the information would be incorrect (moves are inserted before the branch in resolve_data_flow)"); 2189 } 2190 } 2191 } 2192 #endif 2193 2194 // operands are not changed when an interval is split during allocation, 2195 // so search the right interval here 2196 interval = split_child_at_op_id(interval, op_id, mode); 2197 } 2198 2199 LIR_Opr res = operand_for_interval(interval); 2200 2201 #ifdef X86 2202 // new semantic for is_last_use: not only set on definite end of interval, 2203 // but also before hole 2204 // This may still miss some cases (e.g. for dead values), but it is not necessary that the 2205 // last use information is completely correct 2206 // information is only needed for fpu stack allocation 2207 if (res->is_fpu_register()) { 2208 if (opr->is_last_use() || op_id == interval->to() || (op_id != -1 && interval->has_hole_between(op_id, op_id + 1))) { 2209 assert(op_id == -1 || !is_block_begin(op_id), "holes at begin of block may also result from control flow"); 2210 res = res->make_last_use(); 2211 } 2212 } 2213 #endif 2214 2215 assert(!gen()->is_vreg_flag_set(opr->vreg_number(), LIRGenerator::callee_saved) || !FrameMap::is_caller_save_register(res), "bad allocation"); 2216 2217 return res; 2218 } 2219 2220 2221 #ifdef ASSERT 2222 // some methods used to check correctness of debug information 2223 2224 void assert_no_register_values(GrowableArray<ScopeValue*>* values) { 2225 if (values == NULL) { 2226 return; 2227 } 2228 2229 for (int i = 0; i < values->length(); i++) { 2230 ScopeValue* value = values->at(i); 2231 2232 if (value->is_location()) { 2233 Location location = ((LocationValue*)value)->location(); 2234 assert(location.where() == Location::on_stack, "value is in register"); 2235 } 2236 } 2237 } 2238 2239 void assert_no_register_values(GrowableArray<MonitorValue*>* values) { 2240 if (values == NULL) { 2241 return; 2242 } 2243 2244 for (int i = 0; i < values->length(); i++) { 2245 MonitorValue* value = values->at(i); 2246 2247 if (value->owner()->is_location()) { 2248 Location location = ((LocationValue*)value->owner())->location(); 2249 assert(location.where() == Location::on_stack, "owner is in register"); 2250 } 2251 assert(value->basic_lock().where() == Location::on_stack, "basic_lock is in register"); 2252 } 2253 } 2254 2255 void assert_equal(Location l1, Location l2) { 2256 assert(l1.where() == l2.where() && l1.type() == l2.type() && l1.offset() == l2.offset(), ""); 2257 } 2258 2259 void assert_equal(ScopeValue* v1, ScopeValue* v2) { 2260 if (v1->is_location()) { 2261 assert(v2->is_location(), ""); 2262 assert_equal(((LocationValue*)v1)->location(), ((LocationValue*)v2)->location()); 2263 } else if (v1->is_constant_int()) { 2264 assert(v2->is_constant_int(), ""); 2265 assert(((ConstantIntValue*)v1)->value() == ((ConstantIntValue*)v2)->value(), ""); 2266 } else if (v1->is_constant_double()) { 2267 assert(v2->is_constant_double(), ""); 2268 assert(((ConstantDoubleValue*)v1)->value() == ((ConstantDoubleValue*)v2)->value(), ""); 2269 } else if (v1->is_constant_long()) { 2270 assert(v2->is_constant_long(), ""); 2271 assert(((ConstantLongValue*)v1)->value() == ((ConstantLongValue*)v2)->value(), ""); 2272 } else if (v1->is_constant_oop()) { 2273 assert(v2->is_constant_oop(), ""); 2274 assert(((ConstantOopWriteValue*)v1)->value() == ((ConstantOopWriteValue*)v2)->value(), ""); 2275 } else { 2276 ShouldNotReachHere(); 2277 } 2278 } 2279 2280 void assert_equal(MonitorValue* m1, MonitorValue* m2) { 2281 assert_equal(m1->owner(), m2->owner()); 2282 assert_equal(m1->basic_lock(), m2->basic_lock()); 2283 } 2284 2285 void assert_equal(IRScopeDebugInfo* d1, IRScopeDebugInfo* d2) { 2286 assert(d1->scope() == d2->scope(), "not equal"); 2287 assert(d1->bci() == d2->bci(), "not equal"); 2288 2289 if (d1->locals() != NULL) { 2290 assert(d1->locals() != NULL && d2->locals() != NULL, "not equal"); 2291 assert(d1->locals()->length() == d2->locals()->length(), "not equal"); 2292 for (int i = 0; i < d1->locals()->length(); i++) { 2293 assert_equal(d1->locals()->at(i), d2->locals()->at(i)); 2294 } 2295 } else { 2296 assert(d1->locals() == NULL && d2->locals() == NULL, "not equal"); 2297 } 2298 2299 if (d1->expressions() != NULL) { 2300 assert(d1->expressions() != NULL && d2->expressions() != NULL, "not equal"); 2301 assert(d1->expressions()->length() == d2->expressions()->length(), "not equal"); 2302 for (int i = 0; i < d1->expressions()->length(); i++) { 2303 assert_equal(d1->expressions()->at(i), d2->expressions()->at(i)); 2304 } 2305 } else { 2306 assert(d1->expressions() == NULL && d2->expressions() == NULL, "not equal"); 2307 } 2308 2309 if (d1->monitors() != NULL) { 2310 assert(d1->monitors() != NULL && d2->monitors() != NULL, "not equal"); 2311 assert(d1->monitors()->length() == d2->monitors()->length(), "not equal"); 2312 for (int i = 0; i < d1->monitors()->length(); i++) { 2313 assert_equal(d1->monitors()->at(i), d2->monitors()->at(i)); 2314 } 2315 } else { 2316 assert(d1->monitors() == NULL && d2->monitors() == NULL, "not equal"); 2317 } 2318 2319 if (d1->caller() != NULL) { 2320 assert(d1->caller() != NULL && d2->caller() != NULL, "not equal"); 2321 assert_equal(d1->caller(), d2->caller()); 2322 } else { 2323 assert(d1->caller() == NULL && d2->caller() == NULL, "not equal"); 2324 } 2325 } 2326 2327 void check_stack_depth(CodeEmitInfo* info, int stack_end) { 2328 if (info->stack()->bci() != SynchronizationEntryBCI && !info->scope()->method()->is_native()) { 2329 Bytecodes::Code code = info->scope()->method()->java_code_at_bci(info->stack()->bci()); 2330 switch (code) { 2331 case Bytecodes::_ifnull : // fall through 2332 case Bytecodes::_ifnonnull : // fall through 2333 case Bytecodes::_ifeq : // fall through 2334 case Bytecodes::_ifne : // fall through 2335 case Bytecodes::_iflt : // fall through 2336 case Bytecodes::_ifge : // fall through 2337 case Bytecodes::_ifgt : // fall through 2338 case Bytecodes::_ifle : // fall through 2339 case Bytecodes::_if_icmpeq : // fall through 2340 case Bytecodes::_if_icmpne : // fall through 2341 case Bytecodes::_if_icmplt : // fall through 2342 case Bytecodes::_if_icmpge : // fall through 2343 case Bytecodes::_if_icmpgt : // fall through 2344 case Bytecodes::_if_icmple : // fall through 2345 case Bytecodes::_if_acmpeq : // fall through 2346 case Bytecodes::_if_acmpne : 2347 assert(stack_end >= -Bytecodes::depth(code), "must have non-empty expression stack at if bytecode"); 2348 break; 2349 } 2350 } 2351 } 2352 2353 #endif // ASSERT 2354 2355 2356 IntervalWalker* LinearScan::init_compute_oop_maps() { 2357 // setup lists of potential oops for walking 2358 Interval* oop_intervals; 2359 Interval* non_oop_intervals; 2360 2361 create_unhandled_lists(&oop_intervals, &non_oop_intervals, is_oop_interval, NULL); 2362 2363 // intervals that have no oops inside need not to be processed 2364 // to ensure a walking until the last instruction id, add a dummy interval 2365 // with a high operation id 2366 non_oop_intervals = new Interval(any_reg); 2367 non_oop_intervals->add_range(max_jint - 2, max_jint - 1); 2368 2369 return new IntervalWalker(this, oop_intervals, non_oop_intervals); 2370 } 2371 2372 2373 OopMap* LinearScan::compute_oop_map(IntervalWalker* iw, LIR_Op* op, CodeEmitInfo* info, bool is_call_site) { 2374 TRACE_LINEAR_SCAN(3, tty->print_cr("creating oop map at op_id %d", op->id())); 2375 2376 // walk before the current operation -> intervals that start at 2377 // the operation (= output operands of the operation) are not 2378 // included in the oop map 2379 iw->walk_before(op->id()); 2380 2381 int frame_size = frame_map()->framesize(); 2382 int arg_count = frame_map()->oop_map_arg_count(); 2383 OopMap* map = new OopMap(frame_size, arg_count); 2384 2385 // Iterate through active intervals 2386 for (Interval* interval = iw->active_first(fixedKind); interval != Interval::end(); interval = interval->next()) { 2387 int assigned_reg = interval->assigned_reg(); 2388 2389 assert(interval->current_from() <= op->id() && op->id() <= interval->current_to(), "interval should not be active otherwise"); 2390 assert(interval->assigned_regHi() == any_reg, "oop must be single word"); 2391 assert(interval->reg_num() >= LIR_OprDesc::vreg_base, "fixed interval found"); 2392 2393 // Check if this range covers the instruction. Intervals that 2394 // start or end at the current operation are not included in the 2395 // oop map, except in the case of patching moves. For patching 2396 // moves, any intervals which end at this instruction are included 2397 // in the oop map since we may safepoint while doing the patch 2398 // before we've consumed the inputs. 2399 if (op->is_patching() || op->id() < interval->current_to()) { 2400 2401 // caller-save registers must not be included into oop-maps at calls 2402 assert(!is_call_site || assigned_reg >= nof_regs || !is_caller_save(assigned_reg), "interval is in a caller-save register at a call -> register will be overwritten"); 2403 2404 VMReg name = vm_reg_for_interval(interval); 2405 set_oop(map, name); 2406 2407 // Spill optimization: when the stack value is guaranteed to be always correct, 2408 // then it must be added to the oop map even if the interval is currently in a register 2409 if (interval->always_in_memory() && 2410 op->id() > interval->spill_definition_pos() && 2411 interval->assigned_reg() != interval->canonical_spill_slot()) { 2412 assert(interval->spill_definition_pos() > 0, "position not set correctly"); 2413 assert(interval->canonical_spill_slot() >= LinearScan::nof_regs, "no spill slot assigned"); 2414 assert(interval->assigned_reg() < LinearScan::nof_regs, "interval is on stack, so stack slot is registered twice"); 2415 2416 set_oop(map, frame_map()->slot_regname(interval->canonical_spill_slot() - LinearScan::nof_regs)); 2417 } 2418 } 2419 } 2420 2421 // add oops from lock stack 2422 assert(info->stack() != NULL, "CodeEmitInfo must always have a stack"); 2423 int locks_count = info->stack()->total_locks_size(); 2424 for (int i = 0; i < locks_count; i++) { 2425 set_oop(map, frame_map()->monitor_object_regname(i)); 2426 } 2427 2428 return map; 2429 } 2430 2431 2432 void LinearScan::compute_oop_map(IntervalWalker* iw, const LIR_OpVisitState &visitor, LIR_Op* op) { 2433 assert(visitor.info_count() > 0, "no oop map needed"); 2434 2435 // compute oop_map only for first CodeEmitInfo 2436 // because it is (in most cases) equal for all other infos of the same operation 2437 CodeEmitInfo* first_info = visitor.info_at(0); 2438 OopMap* first_oop_map = compute_oop_map(iw, op, first_info, visitor.has_call()); 2439 2440 for (int i = 0; i < visitor.info_count(); i++) { 2441 CodeEmitInfo* info = visitor.info_at(i); 2442 OopMap* oop_map = first_oop_map; 2443 2444 // compute worst case interpreter size in case of a deoptimization 2445 _compilation->update_interpreter_frame_size(info->interpreter_frame_size()); 2446 2447 if (info->stack()->locks_size() != first_info->stack()->locks_size()) { 2448 // this info has a different number of locks then the precomputed oop map 2449 // (possible for lock and unlock instructions) -> compute oop map with 2450 // correct lock information 2451 oop_map = compute_oop_map(iw, op, info, visitor.has_call()); 2452 } 2453 2454 if (info->_oop_map == NULL) { 2455 info->_oop_map = oop_map; 2456 } else { 2457 // a CodeEmitInfo can not be shared between different LIR-instructions 2458 // because interval splitting can occur anywhere between two instructions 2459 // and so the oop maps must be different 2460 // -> check if the already set oop_map is exactly the one calculated for this operation 2461 assert(info->_oop_map == oop_map, "same CodeEmitInfo used for multiple LIR instructions"); 2462 } 2463 } 2464 } 2465 2466 2467 // frequently used constants 2468 // Allocate them with new so they are never destroyed (otherwise, a 2469 // forced exit could destroy these objects while they are still in 2470 // use). 2471 ConstantOopWriteValue* LinearScan::_oop_null_scope_value = new (ResourceObj::C_HEAP, mtCompiler) ConstantOopWriteValue(NULL); 2472 ConstantIntValue* LinearScan::_int_m1_scope_value = new (ResourceObj::C_HEAP, mtCompiler) ConstantIntValue(-1); 2473 ConstantIntValue* LinearScan::_int_0_scope_value = new (ResourceObj::C_HEAP, mtCompiler) ConstantIntValue(0); 2474 ConstantIntValue* LinearScan::_int_1_scope_value = new (ResourceObj::C_HEAP, mtCompiler) ConstantIntValue(1); 2475 ConstantIntValue* LinearScan::_int_2_scope_value = new (ResourceObj::C_HEAP, mtCompiler) ConstantIntValue(2); 2476 LocationValue* _illegal_value = new (ResourceObj::C_HEAP, mtCompiler) LocationValue(Location()); 2477 2478 void LinearScan::init_compute_debug_info() { 2479 // cache for frequently used scope values 2480 // (cpu registers and stack slots) 2481 _scope_value_cache = ScopeValueArray((LinearScan::nof_cpu_regs + frame_map()->argcount() + max_spills()) * 2, NULL); 2482 } 2483 2484 MonitorValue* LinearScan::location_for_monitor_index(int monitor_index) { 2485 Location loc; 2486 if (!frame_map()->location_for_monitor_object(monitor_index, &loc)) { 2487 bailout("too large frame"); 2488 } 2489 ScopeValue* object_scope_value = new LocationValue(loc); 2490 2491 if (!frame_map()->location_for_monitor_lock(monitor_index, &loc)) { 2492 bailout("too large frame"); 2493 } 2494 return new MonitorValue(object_scope_value, loc); 2495 } 2496 2497 LocationValue* LinearScan::location_for_name(int name, Location::Type loc_type) { 2498 Location loc; 2499 if (!frame_map()->locations_for_slot(name, loc_type, &loc)) { 2500 bailout("too large frame"); 2501 } 2502 return new LocationValue(loc); 2503 } 2504 2505 2506 int LinearScan::append_scope_value_for_constant(LIR_Opr opr, GrowableArray<ScopeValue*>* scope_values) { 2507 assert(opr->is_constant(), "should not be called otherwise"); 2508 2509 LIR_Const* c = opr->as_constant_ptr(); 2510 BasicType t = c->type(); 2511 switch (t) { 2512 case T_OBJECT: { 2513 jobject value = c->as_jobject(); 2514 if (value == NULL) { 2515 scope_values->append(_oop_null_scope_value); 2516 } else { 2517 scope_values->append(new ConstantOopWriteValue(c->as_jobject())); 2518 } 2519 return 1; 2520 } 2521 2522 case T_INT: // fall through 2523 case T_FLOAT: { 2524 int value = c->as_jint_bits(); 2525 switch (value) { 2526 case -1: scope_values->append(_int_m1_scope_value); break; 2527 case 0: scope_values->append(_int_0_scope_value); break; 2528 case 1: scope_values->append(_int_1_scope_value); break; 2529 case 2: scope_values->append(_int_2_scope_value); break; 2530 default: scope_values->append(new ConstantIntValue(c->as_jint_bits())); break; 2531 } 2532 return 1; 2533 } 2534 2535 case T_LONG: // fall through 2536 case T_DOUBLE: { 2537 #ifdef _LP64 2538 scope_values->append(_int_0_scope_value); 2539 scope_values->append(new ConstantLongValue(c->as_jlong_bits())); 2540 #else 2541 if (hi_word_offset_in_bytes > lo_word_offset_in_bytes) { 2542 scope_values->append(new ConstantIntValue(c->as_jint_hi_bits())); 2543 scope_values->append(new ConstantIntValue(c->as_jint_lo_bits())); 2544 } else { 2545 scope_values->append(new ConstantIntValue(c->as_jint_lo_bits())); 2546 scope_values->append(new ConstantIntValue(c->as_jint_hi_bits())); 2547 } 2548 #endif 2549 return 2; 2550 } 2551 2552 case T_ADDRESS: { 2553 #ifdef _LP64 2554 scope_values->append(new ConstantLongValue(c->as_jint())); 2555 #else 2556 scope_values->append(new ConstantIntValue(c->as_jint())); 2557 #endif 2558 return 1; 2559 } 2560 2561 default: 2562 ShouldNotReachHere(); 2563 return -1; 2564 } 2565 } 2566 2567 int LinearScan::append_scope_value_for_operand(LIR_Opr opr, GrowableArray<ScopeValue*>* scope_values) { 2568 if (opr->is_single_stack()) { 2569 int stack_idx = opr->single_stack_ix(); 2570 bool is_oop = opr->is_oop_register(); 2571 int cache_idx = (stack_idx + LinearScan::nof_cpu_regs) * 2 + (is_oop ? 1 : 0); 2572 2573 ScopeValue* sv = _scope_value_cache.at(cache_idx); 2574 if (sv == NULL) { 2575 Location::Type loc_type = is_oop ? Location::oop : Location::normal; 2576 sv = location_for_name(stack_idx, loc_type); 2577 _scope_value_cache.at_put(cache_idx, sv); 2578 } 2579 2580 // check if cached value is correct 2581 DEBUG_ONLY(assert_equal(sv, location_for_name(stack_idx, is_oop ? Location::oop : Location::normal))); 2582 2583 scope_values->append(sv); 2584 return 1; 2585 2586 } else if (opr->is_single_cpu()) { 2587 bool is_oop = opr->is_oop_register(); 2588 int cache_idx = opr->cpu_regnr() * 2 + (is_oop ? 1 : 0); 2589 Location::Type int_loc_type = NOT_LP64(Location::normal) LP64_ONLY(Location::int_in_long); 2590 2591 ScopeValue* sv = _scope_value_cache.at(cache_idx); 2592 if (sv == NULL) { 2593 Location::Type loc_type = is_oop ? Location::oop : int_loc_type; 2594 VMReg rname = frame_map()->regname(opr); 2595 sv = new LocationValue(Location::new_reg_loc(loc_type, rname)); 2596 _scope_value_cache.at_put(cache_idx, sv); 2597 } 2598 2599 // check if cached value is correct 2600 DEBUG_ONLY(assert_equal(sv, new LocationValue(Location::new_reg_loc(is_oop ? Location::oop : int_loc_type, frame_map()->regname(opr))))); 2601 2602 scope_values->append(sv); 2603 return 1; 2604 2605 #ifdef X86 2606 } else if (opr->is_single_xmm()) { 2607 VMReg rname = opr->as_xmm_float_reg()->as_VMReg(); 2608 LocationValue* sv = new LocationValue(Location::new_reg_loc(Location::normal, rname)); 2609 2610 scope_values->append(sv); 2611 return 1; 2612 #endif 2613 2614 } else if (opr->is_single_fpu()) { 2615 #ifdef X86 2616 // the exact location of fpu stack values is only known 2617 // during fpu stack allocation, so the stack allocator object 2618 // must be present 2619 assert(use_fpu_stack_allocation(), "should not have float stack values without fpu stack allocation (all floats must be SSE2)"); 2620 assert(_fpu_stack_allocator != NULL, "must be present"); 2621 opr = _fpu_stack_allocator->to_fpu_stack(opr); 2622 #endif 2623 2624 Location::Type loc_type = float_saved_as_double ? Location::float_in_dbl : Location::normal; 2625 VMReg rname = frame_map()->fpu_regname(opr->fpu_regnr()); 2626 #ifndef __SOFTFP__ 2627 #ifndef VM_LITTLE_ENDIAN 2628 if (! float_saved_as_double) { 2629 // On big endian system, we may have an issue if float registers use only 2630 // the low half of the (same) double registers. 2631 // Both the float and the double could have the same regnr but would correspond 2632 // to two different addresses once saved. 2633 2634 // get next safely (no assertion checks) 2635 VMReg next = VMRegImpl::as_VMReg(1+rname->value()); 2636 if (next->is_reg() && 2637 (next->as_FloatRegister() == rname->as_FloatRegister())) { 2638 // the back-end does use the same numbering for the double and the float 2639 rname = next; // VMReg for the low bits, e.g. the real VMReg for the float 2640 } 2641 } 2642 #endif 2643 #endif 2644 LocationValue* sv = new LocationValue(Location::new_reg_loc(loc_type, rname)); 2645 2646 scope_values->append(sv); 2647 return 1; 2648 2649 } else { 2650 // double-size operands 2651 2652 ScopeValue* first; 2653 ScopeValue* second; 2654 2655 if (opr->is_double_stack()) { 2656 #ifdef _LP64 2657 Location loc1; 2658 Location::Type loc_type = opr->type() == T_LONG ? Location::lng : Location::dbl; 2659 if (!frame_map()->locations_for_slot(opr->double_stack_ix(), loc_type, &loc1, NULL)) { 2660 bailout("too large frame"); 2661 } 2662 // Does this reverse on x86 vs. sparc? 2663 first = new LocationValue(loc1); 2664 second = _int_0_scope_value; 2665 #else 2666 Location loc1, loc2; 2667 if (!frame_map()->locations_for_slot(opr->double_stack_ix(), Location::normal, &loc1, &loc2)) { 2668 bailout("too large frame"); 2669 } 2670 first = new LocationValue(loc1); 2671 second = new LocationValue(loc2); 2672 #endif // _LP64 2673 2674 } else if (opr->is_double_cpu()) { 2675 #ifdef _LP64 2676 VMReg rname_first = opr->as_register_lo()->as_VMReg(); 2677 first = new LocationValue(Location::new_reg_loc(Location::lng, rname_first)); 2678 second = _int_0_scope_value; 2679 #else 2680 VMReg rname_first = opr->as_register_lo()->as_VMReg(); 2681 VMReg rname_second = opr->as_register_hi()->as_VMReg(); 2682 2683 if (hi_word_offset_in_bytes < lo_word_offset_in_bytes) { 2684 // lo/hi and swapped relative to first and second, so swap them 2685 VMReg tmp = rname_first; 2686 rname_first = rname_second; 2687 rname_second = tmp; 2688 } 2689 2690 first = new LocationValue(Location::new_reg_loc(Location::normal, rname_first)); 2691 second = new LocationValue(Location::new_reg_loc(Location::normal, rname_second)); 2692 #endif //_LP64 2693 2694 2695 #ifdef X86 2696 } else if (opr->is_double_xmm()) { 2697 assert(opr->fpu_regnrLo() == opr->fpu_regnrHi(), "assumed in calculation"); 2698 VMReg rname_first = opr->as_xmm_double_reg()->as_VMReg(); 2699 # ifdef _LP64 2700 first = new LocationValue(Location::new_reg_loc(Location::dbl, rname_first)); 2701 second = _int_0_scope_value; 2702 # else 2703 first = new LocationValue(Location::new_reg_loc(Location::normal, rname_first)); 2704 // %%% This is probably a waste but we'll keep things as they were for now 2705 if (true) { 2706 VMReg rname_second = rname_first->next(); 2707 second = new LocationValue(Location::new_reg_loc(Location::normal, rname_second)); 2708 } 2709 # endif 2710 #endif 2711 2712 } else if (opr->is_double_fpu()) { 2713 // On SPARC, fpu_regnrLo/fpu_regnrHi represents the two halves of 2714 // the double as float registers in the native ordering. On X86, 2715 // fpu_regnrLo is a FPU stack slot whose VMReg represents 2716 // the low-order word of the double and fpu_regnrLo + 1 is the 2717 // name for the other half. *first and *second must represent the 2718 // least and most significant words, respectively. 2719 2720 #ifdef X86 2721 // the exact location of fpu stack values is only known 2722 // during fpu stack allocation, so the stack allocator object 2723 // must be present 2724 assert(use_fpu_stack_allocation(), "should not have float stack values without fpu stack allocation (all floats must be SSE2)"); 2725 assert(_fpu_stack_allocator != NULL, "must be present"); 2726 opr = _fpu_stack_allocator->to_fpu_stack(opr); 2727 2728 assert(opr->fpu_regnrLo() == opr->fpu_regnrHi(), "assumed in calculation (only fpu_regnrLo is used)"); 2729 #endif 2730 #ifdef SPARC 2731 assert(opr->fpu_regnrLo() == opr->fpu_regnrHi() + 1, "assumed in calculation (only fpu_regnrHi is used)"); 2732 #endif 2733 #if defined(ARM32) || defined(AARCH32) 2734 assert(opr->fpu_regnrHi() == opr->fpu_regnrLo() + 1, "assumed in calculation (only fpu_regnrLo is used)"); 2735 #endif // ARM32 || AARCH32 2736 #ifdef PPC 2737 assert(opr->fpu_regnrLo() == opr->fpu_regnrHi(), "assumed in calculation (only fpu_regnrHi is used)"); 2738 #endif 2739 2740 #ifdef VM_LITTLE_ENDIAN 2741 VMReg rname_first = frame_map()->fpu_regname(opr->fpu_regnrLo()); 2742 #else 2743 VMReg rname_first = frame_map()->fpu_regname(opr->fpu_regnrHi()); 2744 #endif 2745 2746 #ifdef _LP64 2747 first = new LocationValue(Location::new_reg_loc(Location::dbl, rname_first)); 2748 second = _int_0_scope_value; 2749 #else 2750 first = new LocationValue(Location::new_reg_loc(Location::normal, rname_first)); 2751 // %%% This is probably a waste but we'll keep things as they were for now 2752 if (true) { 2753 VMReg rname_second = rname_first->next(); 2754 second = new LocationValue(Location::new_reg_loc(Location::normal, rname_second)); 2755 } 2756 #endif 2757 2758 } else { 2759 ShouldNotReachHere(); 2760 first = NULL; 2761 second = NULL; 2762 } 2763 2764 assert(first != NULL && second != NULL, "must be set"); 2765 // The convention the interpreter uses is that the second local 2766 // holds the first raw word of the native double representation. 2767 // This is actually reasonable, since locals and stack arrays 2768 // grow downwards in all implementations. 2769 // (If, on some machine, the interpreter's Java locals or stack 2770 // were to grow upwards, the embedded doubles would be word-swapped.) 2771 scope_values->append(second); 2772 scope_values->append(first); 2773 return 2; 2774 } 2775 } 2776 2777 2778 int LinearScan::append_scope_value(int op_id, Value value, GrowableArray<ScopeValue*>* scope_values) { 2779 if (value != NULL) { 2780 LIR_Opr opr = value->operand(); 2781 Constant* con = value->as_Constant(); 2782 2783 assert(con == NULL || opr->is_virtual() || opr->is_constant() || opr->is_illegal(), "asumption: Constant instructions have only constant operands (or illegal if constant is optimized away)"); 2784 assert(con != NULL || opr->is_virtual(), "asumption: non-Constant instructions have only virtual operands"); 2785 2786 if (con != NULL && !con->is_pinned() && !opr->is_constant()) { 2787 // Unpinned constants may have a virtual operand for a part of the lifetime 2788 // or may be illegal when it was optimized away, 2789 // so always use a constant operand 2790 opr = LIR_OprFact::value_type(con->type()); 2791 } 2792 assert(opr->is_virtual() || opr->is_constant(), "other cases not allowed here"); 2793 2794 if (opr->is_virtual()) { 2795 LIR_OpVisitState::OprMode mode = LIR_OpVisitState::inputMode; 2796 2797 BlockBegin* block = block_of_op_with_id(op_id); 2798 if (block->number_of_sux() == 1 && op_id == block->last_lir_instruction_id()) { 2799 // generating debug information for the last instruction of a block. 2800 // if this instruction is a branch, spill moves are inserted before this branch 2801 // and so the wrong operand would be returned (spill moves at block boundaries are not 2802 // considered in the live ranges of intervals) 2803 // Solution: use the first op_id of the branch target block instead. 2804 if (block->lir()->instructions_list()->last()->as_OpBranch() != NULL) { 2805 if (block->live_out().at(opr->vreg_number())) { 2806 op_id = block->sux_at(0)->first_lir_instruction_id(); 2807 mode = LIR_OpVisitState::outputMode; 2808 } 2809 } 2810 } 2811 2812 // Get current location of operand 2813 // The operand must be live because debug information is considered when building the intervals 2814 // if the interval is not live, color_lir_opr will cause an assertion failure 2815 opr = color_lir_opr(opr, op_id, mode); 2816 assert(!has_call(op_id) || opr->is_stack() || !is_caller_save(reg_num(opr)), "can not have caller-save register operands at calls"); 2817 2818 // Append to ScopeValue array 2819 return append_scope_value_for_operand(opr, scope_values); 2820 2821 } else { 2822 assert(value->as_Constant() != NULL, "all other instructions have only virtual operands"); 2823 assert(opr->is_constant(), "operand must be constant"); 2824 2825 return append_scope_value_for_constant(opr, scope_values); 2826 } 2827 } else { 2828 // append a dummy value because real value not needed 2829 scope_values->append(_illegal_value); 2830 return 1; 2831 } 2832 } 2833 2834 2835 IRScopeDebugInfo* LinearScan::compute_debug_info_for_scope(int op_id, IRScope* cur_scope, ValueStack* cur_state, ValueStack* innermost_state) { 2836 IRScopeDebugInfo* caller_debug_info = NULL; 2837 2838 ValueStack* caller_state = cur_state->caller_state(); 2839 if (caller_state != NULL) { 2840 // process recursively to compute outermost scope first 2841 caller_debug_info = compute_debug_info_for_scope(op_id, cur_scope->caller(), caller_state, innermost_state); 2842 } 2843 2844 // initialize these to null. 2845 // If we don't need deopt info or there are no locals, expressions or monitors, 2846 // then these get recorded as no information and avoids the allocation of 0 length arrays. 2847 GrowableArray<ScopeValue*>* locals = NULL; 2848 GrowableArray<ScopeValue*>* expressions = NULL; 2849 GrowableArray<MonitorValue*>* monitors = NULL; 2850 2851 // describe local variable values 2852 int nof_locals = cur_state->locals_size(); 2853 if (nof_locals > 0) { 2854 locals = new GrowableArray<ScopeValue*>(nof_locals); 2855 2856 int pos = 0; 2857 while (pos < nof_locals) { 2858 assert(pos < cur_state->locals_size(), "why not?"); 2859 2860 Value local = cur_state->local_at(pos); 2861 pos += append_scope_value(op_id, local, locals); 2862 2863 assert(locals->length() == pos, "must match"); 2864 } 2865 assert(locals->length() == cur_scope->method()->max_locals(), "wrong number of locals"); 2866 assert(locals->length() == cur_state->locals_size(), "wrong number of locals"); 2867 } else if (cur_scope->method()->max_locals() > 0) { 2868 assert(cur_state->kind() == ValueStack::EmptyExceptionState, "should be"); 2869 nof_locals = cur_scope->method()->max_locals(); 2870 locals = new GrowableArray<ScopeValue*>(nof_locals); 2871 for(int i = 0; i < nof_locals; i++) { 2872 locals->append(_illegal_value); 2873 } 2874 } 2875 2876 // describe expression stack 2877 int nof_stack = cur_state->stack_size(); 2878 if (nof_stack > 0) { 2879 expressions = new GrowableArray<ScopeValue*>(nof_stack); 2880 2881 int pos = 0; 2882 while (pos < nof_stack) { 2883 Value expression = cur_state->stack_at_inc(pos); 2884 append_scope_value(op_id, expression, expressions); 2885 2886 assert(expressions->length() == pos, "must match"); 2887 } 2888 assert(expressions->length() == cur_state->stack_size(), "wrong number of stack entries"); 2889 } 2890 2891 // describe monitors 2892 int nof_locks = cur_state->locks_size(); 2893 if (nof_locks > 0) { 2894 int lock_offset = cur_state->caller_state() != NULL ? cur_state->caller_state()->total_locks_size() : 0; 2895 monitors = new GrowableArray<MonitorValue*>(nof_locks); 2896 for (int i = 0; i < nof_locks; i++) { 2897 monitors->append(location_for_monitor_index(lock_offset + i)); 2898 } 2899 } 2900 2901 return new IRScopeDebugInfo(cur_scope, cur_state->bci(), locals, expressions, monitors, caller_debug_info); 2902 } 2903 2904 2905 void LinearScan::compute_debug_info(CodeEmitInfo* info, int op_id) { 2906 TRACE_LINEAR_SCAN(3, tty->print_cr("creating debug information at op_id %d", op_id)); 2907 2908 IRScope* innermost_scope = info->scope(); 2909 ValueStack* innermost_state = info->stack(); 2910 2911 assert(innermost_scope != NULL && innermost_state != NULL, "why is it missing?"); 2912 2913 DEBUG_ONLY(check_stack_depth(info, innermost_state->stack_size())); 2914 2915 if (info->_scope_debug_info == NULL) { 2916 // compute debug information 2917 info->_scope_debug_info = compute_debug_info_for_scope(op_id, innermost_scope, innermost_state, innermost_state); 2918 } else { 2919 // debug information already set. Check that it is correct from the current point of view 2920 DEBUG_ONLY(assert_equal(info->_scope_debug_info, compute_debug_info_for_scope(op_id, innermost_scope, innermost_state, innermost_state))); 2921 } 2922 } 2923 2924 2925 void LinearScan::assign_reg_num(LIR_OpList* instructions, IntervalWalker* iw) { 2926 LIR_OpVisitState visitor; 2927 int num_inst = instructions->length(); 2928 bool has_dead = false; 2929 2930 for (int j = 0; j < num_inst; j++) { 2931 LIR_Op* op = instructions->at(j); 2932 if (op == NULL) { // this can happen when spill-moves are removed in eliminate_spill_moves 2933 has_dead = true; 2934 continue; 2935 } 2936 int op_id = op->id(); 2937 2938 // visit instruction to get list of operands 2939 visitor.visit(op); 2940 2941 // iterate all modes of the visitor and process all virtual operands 2942 for_each_visitor_mode(mode) { 2943 int n = visitor.opr_count(mode); 2944 for (int k = 0; k < n; k++) { 2945 LIR_Opr opr = visitor.opr_at(mode, k); 2946 if (opr->is_virtual_register()) { 2947 visitor.set_opr_at(mode, k, color_lir_opr(opr, op_id, mode)); 2948 } 2949 } 2950 } 2951 2952 if (visitor.info_count() > 0) { 2953 // exception handling 2954 if (compilation()->has_exception_handlers()) { 2955 XHandlers* xhandlers = visitor.all_xhandler(); 2956 int n = xhandlers->length(); 2957 for (int k = 0; k < n; k++) { 2958 XHandler* handler = xhandlers->handler_at(k); 2959 if (handler->entry_code() != NULL) { 2960 assign_reg_num(handler->entry_code()->instructions_list(), NULL); 2961 } 2962 } 2963 } else { 2964 assert(visitor.all_xhandler()->length() == 0, "missed exception handler"); 2965 } 2966 2967 // compute oop map 2968 assert(iw != NULL, "needed for compute_oop_map"); 2969 compute_oop_map(iw, visitor, op); 2970 2971 // compute debug information 2972 if (!use_fpu_stack_allocation()) { 2973 // compute debug information if fpu stack allocation is not needed. 2974 // when fpu stack allocation is needed, the debug information can not 2975 // be computed here because the exact location of fpu operands is not known 2976 // -> debug information is created inside the fpu stack allocator 2977 int n = visitor.info_count(); 2978 for (int k = 0; k < n; k++) { 2979 compute_debug_info(visitor.info_at(k), op_id); 2980 } 2981 } 2982 } 2983 2984 #ifdef ASSERT 2985 // make sure we haven't made the op invalid. 2986 op->verify(); 2987 #endif 2988 2989 // remove useless moves 2990 if (op->code() == lir_move) { 2991 assert(op->as_Op1() != NULL, "move must be LIR_Op1"); 2992 LIR_Op1* move = (LIR_Op1*)op; 2993 LIR_Opr src = move->in_opr(); 2994 LIR_Opr dst = move->result_opr(); 2995 if (dst == src || 2996 !dst->is_pointer() && !src->is_pointer() && 2997 src->is_same_register(dst)) { 2998 instructions->at_put(j, NULL); 2999 has_dead = true; 3000 } 3001 } 3002 } 3003 3004 if (has_dead) { 3005 // iterate all instructions of the block and remove all null-values. 3006 int insert_point = 0; 3007 for (int j = 0; j < num_inst; j++) { 3008 LIR_Op* op = instructions->at(j); 3009 if (op != NULL) { 3010 if (insert_point != j) { 3011 instructions->at_put(insert_point, op); 3012 } 3013 insert_point++; 3014 } 3015 } 3016 instructions->truncate(insert_point); 3017 } 3018 } 3019 3020 void LinearScan::assign_reg_num() { 3021 TIME_LINEAR_SCAN(timer_assign_reg_num); 3022 3023 init_compute_debug_info(); 3024 IntervalWalker* iw = init_compute_oop_maps(); 3025 3026 int num_blocks = block_count(); 3027 for (int i = 0; i < num_blocks; i++) { 3028 BlockBegin* block = block_at(i); 3029 assign_reg_num(block->lir()->instructions_list(), iw); 3030 } 3031 } 3032 3033 3034 void LinearScan::do_linear_scan() { 3035 NOT_PRODUCT(_total_timer.begin_method()); 3036 3037 number_instructions(); 3038 3039 NOT_PRODUCT(print_lir(1, "Before Register Allocation")); 3040 3041 compute_local_live_sets(); 3042 compute_global_live_sets(); 3043 CHECK_BAILOUT(); 3044 3045 build_intervals(); 3046 CHECK_BAILOUT(); 3047 sort_intervals_before_allocation(); 3048 3049 NOT_PRODUCT(print_intervals("Before Register Allocation")); 3050 NOT_PRODUCT(LinearScanStatistic::compute(this, _stat_before_alloc)); 3051 3052 allocate_registers(); 3053 CHECK_BAILOUT(); 3054 3055 resolve_data_flow(); 3056 if (compilation()->has_exception_handlers()) { 3057 resolve_exception_handlers(); 3058 } 3059 // fill in number of spill slots into frame_map 3060 propagate_spill_slots(); 3061 CHECK_BAILOUT(); 3062 3063 NOT_PRODUCT(print_intervals("After Register Allocation")); 3064 NOT_PRODUCT(print_lir(2, "LIR after register allocation:")); 3065 3066 sort_intervals_after_allocation(); 3067 3068 DEBUG_ONLY(verify()); 3069 3070 eliminate_spill_moves(); 3071 assign_reg_num(); 3072 CHECK_BAILOUT(); 3073 3074 NOT_PRODUCT(print_lir(2, "LIR after assignment of register numbers:")); 3075 NOT_PRODUCT(LinearScanStatistic::compute(this, _stat_after_asign)); 3076 3077 { TIME_LINEAR_SCAN(timer_allocate_fpu_stack); 3078 3079 if (use_fpu_stack_allocation()) { 3080 allocate_fpu_stack(); // Only has effect on Intel 3081 NOT_PRODUCT(print_lir(2, "LIR after FPU stack allocation:")); 3082 } 3083 } 3084 3085 { TIME_LINEAR_SCAN(timer_optimize_lir); 3086 3087 EdgeMoveOptimizer::optimize(ir()->code()); 3088 ControlFlowOptimizer::optimize(ir()->code()); 3089 // check that cfg is still correct after optimizations 3090 ir()->verify(); 3091 } 3092 3093 NOT_PRODUCT(print_lir(1, "Before Code Generation", false)); 3094 NOT_PRODUCT(LinearScanStatistic::compute(this, _stat_final)); 3095 NOT_PRODUCT(_total_timer.end_method(this)); 3096 } 3097 3098 3099 // ********** Printing functions 3100 3101 #ifndef PRODUCT 3102 3103 void LinearScan::print_timers(double total) { 3104 _total_timer.print(total); 3105 } 3106 3107 void LinearScan::print_statistics() { 3108 _stat_before_alloc.print("before allocation"); 3109 _stat_after_asign.print("after assignment of register"); 3110 _stat_final.print("after optimization"); 3111 } 3112 3113 void LinearScan::print_bitmap(BitMap& b) { 3114 for (unsigned int i = 0; i < b.size(); i++) { 3115 if (b.at(i)) tty->print("%d ", i); 3116 } 3117 tty->cr(); 3118 } 3119 3120 void LinearScan::print_intervals(const char* label) { 3121 if (TraceLinearScanLevel >= 1) { 3122 int i; 3123 tty->cr(); 3124 tty->print_cr("%s", label); 3125 3126 for (i = 0; i < interval_count(); i++) { 3127 Interval* interval = interval_at(i); 3128 if (interval != NULL) { 3129 interval->print(); 3130 } 3131 } 3132 3133 tty->cr(); 3134 tty->print_cr("--- Basic Blocks ---"); 3135 for (i = 0; i < block_count(); i++) { 3136 BlockBegin* block = block_at(i); 3137 tty->print("B%d [%d, %d, %d, %d] ", block->block_id(), block->first_lir_instruction_id(), block->last_lir_instruction_id(), block->loop_index(), block->loop_depth()); 3138 } 3139 tty->cr(); 3140 tty->cr(); 3141 } 3142 3143 if (PrintCFGToFile) { 3144 CFGPrinter::print_intervals(&_intervals, label); 3145 } 3146 } 3147 3148 void LinearScan::print_lir(int level, const char* label, bool hir_valid) { 3149 if (TraceLinearScanLevel >= level) { 3150 tty->cr(); 3151 tty->print_cr("%s", label); 3152 print_LIR(ir()->linear_scan_order()); 3153 tty->cr(); 3154 } 3155 3156 if (level == 1 && PrintCFGToFile) { 3157 CFGPrinter::print_cfg(ir()->linear_scan_order(), label, hir_valid, true); 3158 } 3159 } 3160 3161 #endif //PRODUCT 3162 3163 3164 // ********** verification functions for allocation 3165 // (check that all intervals have a correct register and that no registers are overwritten) 3166 #ifdef ASSERT 3167 3168 void LinearScan::verify() { 3169 TRACE_LINEAR_SCAN(2, tty->print_cr("********* verifying intervals ******************************************")); 3170 verify_intervals(); 3171 3172 TRACE_LINEAR_SCAN(2, tty->print_cr("********* verifying that no oops are in fixed intervals ****************")); 3173 verify_no_oops_in_fixed_intervals(); 3174 3175 TRACE_LINEAR_SCAN(2, tty->print_cr("********* verifying that unpinned constants are not alive across block boundaries")); 3176 verify_constants(); 3177 3178 TRACE_LINEAR_SCAN(2, tty->print_cr("********* verifying register allocation ********************************")); 3179 verify_registers(); 3180 3181 TRACE_LINEAR_SCAN(2, tty->print_cr("********* no errors found **********************************************")); 3182 } 3183 3184 void LinearScan::verify_intervals() { 3185 int len = interval_count(); 3186 bool has_error = false; 3187 3188 for (int i = 0; i < len; i++) { 3189 Interval* i1 = interval_at(i); 3190 if (i1 == NULL) continue; 3191 3192 i1->check_split_children(); 3193 3194 if (i1->reg_num() != i) { 3195 tty->print_cr("Interval %d is on position %d in list", i1->reg_num(), i); i1->print(); tty->cr(); 3196 has_error = true; 3197 } 3198 3199 if (i1->reg_num() >= LIR_OprDesc::vreg_base && i1->type() == T_ILLEGAL) { 3200 tty->print_cr("Interval %d has no type assigned", i1->reg_num()); i1->print(); tty->cr(); 3201 has_error = true; 3202 } 3203 3204 if (i1->assigned_reg() == any_reg) { 3205 tty->print_cr("Interval %d has no register assigned", i1->reg_num()); i1->print(); tty->cr(); 3206 has_error = true; 3207 } 3208 3209 if (i1->assigned_reg() == i1->assigned_regHi()) { 3210 tty->print_cr("Interval %d: low and high register equal", i1->reg_num()); i1->print(); tty->cr(); 3211 has_error = true; 3212 } 3213 3214 if (!is_processed_reg_num(i1->assigned_reg())) { 3215 tty->print_cr("Can not have an Interval for an ignored register"); i1->print(); tty->cr(); 3216 has_error = true; 3217 } 3218 3219 if (i1->first() == Range::end()) { 3220 tty->print_cr("Interval %d has no Range", i1->reg_num()); i1->print(); tty->cr(); 3221 has_error = true; 3222 } 3223 3224 for (Range* r = i1->first(); r != Range::end(); r = r->next()) { 3225 if (r->from() >= r->to()) { 3226 tty->print_cr("Interval %d has zero length range", i1->reg_num()); i1->print(); tty->cr(); 3227 has_error = true; 3228 } 3229 } 3230 3231 for (int j = i + 1; j < len; j++) { 3232 Interval* i2 = interval_at(j); 3233 if (i2 == NULL) continue; 3234 3235 // special intervals that are created in MoveResolver 3236 // -> ignore them because the range information has no meaning there 3237 if (i1->from() == 1 && i1->to() == 2) continue; 3238 if (i2->from() == 1 && i2->to() == 2) continue; 3239 3240 int r1 = i1->assigned_reg(); 3241 int r1Hi = i1->assigned_regHi(); 3242 int r2 = i2->assigned_reg(); 3243 int r2Hi = i2->assigned_regHi(); 3244 if (i1->intersects(i2) && (r1 == r2 || r1 == r2Hi || (r1Hi != any_reg && (r1Hi == r2 || r1Hi == r2Hi)))) { 3245 tty->print_cr("Intervals %d and %d overlap and have the same register assigned", i1->reg_num(), i2->reg_num()); 3246 i1->print(); tty->cr(); 3247 i2->print(); tty->cr(); 3248 has_error = true; 3249 } 3250 } 3251 } 3252 3253 assert(has_error == false, "register allocation invalid"); 3254 } 3255 3256 3257 void LinearScan::verify_no_oops_in_fixed_intervals() { 3258 Interval* fixed_intervals; 3259 Interval* other_intervals; 3260 create_unhandled_lists(&fixed_intervals, &other_intervals, is_precolored_cpu_interval, NULL); 3261 3262 // to ensure a walking until the last instruction id, add a dummy interval 3263 // with a high operation id 3264 other_intervals = new Interval(any_reg); 3265 other_intervals->add_range(max_jint - 2, max_jint - 1); 3266 IntervalWalker* iw = new IntervalWalker(this, fixed_intervals, other_intervals); 3267 3268 LIR_OpVisitState visitor; 3269 for (int i = 0; i < block_count(); i++) { 3270 BlockBegin* block = block_at(i); 3271 3272 LIR_OpList* instructions = block->lir()->instructions_list(); 3273 3274 for (int j = 0; j < instructions->length(); j++) { 3275 LIR_Op* op = instructions->at(j); 3276 int op_id = op->id(); 3277 3278 visitor.visit(op); 3279 3280 if (visitor.info_count() > 0) { 3281 iw->walk_before(op->id()); 3282 bool check_live = true; 3283 if (op->code() == lir_move) { 3284 LIR_Op1* move = (LIR_Op1*)op; 3285 check_live = (move->patch_code() == lir_patch_none); 3286 } 3287 LIR_OpBranch* branch = op->as_OpBranch(); 3288 if (branch != NULL && branch->stub() != NULL && branch->stub()->is_exception_throw_stub()) { 3289 // Don't bother checking the stub in this case since the 3290 // exception stub will never return to normal control flow. 3291 check_live = false; 3292 } 3293 3294 // Make sure none of the fixed registers is live across an 3295 // oopmap since we can't handle that correctly. 3296 if (check_live) { 3297 for (Interval* interval = iw->active_first(fixedKind); 3298 interval != Interval::end(); 3299 interval = interval->next()) { 3300 if (interval->current_to() > op->id() + 1) { 3301 // This interval is live out of this op so make sure 3302 // that this interval represents some value that's 3303 // referenced by this op either as an input or output. 3304 bool ok = false; 3305 for_each_visitor_mode(mode) { 3306 int n = visitor.opr_count(mode); 3307 for (int k = 0; k < n; k++) { 3308 LIR_Opr opr = visitor.opr_at(mode, k); 3309 if (opr->is_fixed_cpu()) { 3310 if (interval_at(reg_num(opr)) == interval) { 3311 ok = true; 3312 break; 3313 } 3314 int hi = reg_numHi(opr); 3315 if (hi != -1 && interval_at(hi) == interval) { 3316 ok = true; 3317 break; 3318 } 3319 } 3320 } 3321 } 3322 assert(ok, "fixed intervals should never be live across an oopmap point"); 3323 } 3324 } 3325 } 3326 } 3327 3328 // oop-maps at calls do not contain registers, so check is not needed 3329 if (!visitor.has_call()) { 3330 3331 for_each_visitor_mode(mode) { 3332 int n = visitor.opr_count(mode); 3333 for (int k = 0; k < n; k++) { 3334 LIR_Opr opr = visitor.opr_at(mode, k); 3335 3336 if (opr->is_fixed_cpu() && opr->is_oop()) { 3337 // operand is a non-virtual cpu register and contains an oop 3338 TRACE_LINEAR_SCAN(4, op->print_on(tty); tty->print("checking operand "); opr->print(); tty->cr()); 3339 3340 Interval* interval = interval_at(reg_num(opr)); 3341 assert(interval != NULL, "no interval"); 3342 3343 if (mode == LIR_OpVisitState::inputMode) { 3344 if (interval->to() >= op_id + 1) { 3345 assert(interval->to() < op_id + 2 || 3346 interval->has_hole_between(op_id, op_id + 2), 3347 "oop input operand live after instruction"); 3348 } 3349 } else if (mode == LIR_OpVisitState::outputMode) { 3350 if (interval->from() <= op_id - 1) { 3351 assert(interval->has_hole_between(op_id - 1, op_id), 3352 "oop input operand live after instruction"); 3353 } 3354 } 3355 } 3356 } 3357 } 3358 } 3359 } 3360 } 3361 } 3362 3363 3364 void LinearScan::verify_constants() { 3365 int num_regs = num_virtual_regs(); 3366 int size = live_set_size(); 3367 int num_blocks = block_count(); 3368 3369 for (int i = 0; i < num_blocks; i++) { 3370 BlockBegin* block = block_at(i); 3371 BitMap live_at_edge = block->live_in(); 3372 3373 // visit all registers where the live_at_edge bit is set 3374 for (int r = (int)live_at_edge.get_next_one_offset(0, size); r < size; r = (int)live_at_edge.get_next_one_offset(r + 1, size)) { 3375 TRACE_LINEAR_SCAN(4, tty->print("checking interval %d of block B%d", r, block->block_id())); 3376 3377 Value value = gen()->instruction_for_vreg(r); 3378 3379 assert(value != NULL, "all intervals live across block boundaries must have Value"); 3380 assert(value->operand()->is_register() && value->operand()->is_virtual(), "value must have virtual operand"); 3381 assert(value->operand()->vreg_number() == r, "register number must match"); 3382 // TKR assert(value->as_Constant() == NULL || value->is_pinned(), "only pinned constants can be alive accross block boundaries"); 3383 } 3384 } 3385 } 3386 3387 3388 class RegisterVerifier: public StackObj { 3389 private: 3390 LinearScan* _allocator; 3391 BlockList _work_list; // all blocks that must be processed 3392 IntervalsList _saved_states; // saved information of previous check 3393 3394 // simplified access to methods of LinearScan 3395 Compilation* compilation() const { return _allocator->compilation(); } 3396 Interval* interval_at(int reg_num) const { return _allocator->interval_at(reg_num); } 3397 int reg_num(LIR_Opr opr) const { return _allocator->reg_num(opr); } 3398 3399 // currently, only registers are processed 3400 int state_size() { return LinearScan::nof_regs; } 3401 3402 // accessors 3403 IntervalList* state_for_block(BlockBegin* block) { return _saved_states.at(block->block_id()); } 3404 void set_state_for_block(BlockBegin* block, IntervalList* saved_state) { _saved_states.at_put(block->block_id(), saved_state); } 3405 void add_to_work_list(BlockBegin* block) { if (!_work_list.contains(block)) _work_list.append(block); } 3406 3407 // helper functions 3408 IntervalList* copy(IntervalList* input_state); 3409 void state_put(IntervalList* input_state, int reg, Interval* interval); 3410 bool check_state(IntervalList* input_state, int reg, Interval* interval); 3411 3412 void process_block(BlockBegin* block); 3413 void process_xhandler(XHandler* xhandler, IntervalList* input_state); 3414 void process_successor(BlockBegin* block, IntervalList* input_state); 3415 void process_operations(LIR_List* ops, IntervalList* input_state); 3416 3417 public: 3418 RegisterVerifier(LinearScan* allocator) 3419 : _allocator(allocator) 3420 , _work_list(16) 3421 , _saved_states(BlockBegin::number_of_blocks(), NULL) 3422 { } 3423 3424 void verify(BlockBegin* start); 3425 }; 3426 3427 3428 // entry function from LinearScan that starts the verification 3429 void LinearScan::verify_registers() { 3430 RegisterVerifier verifier(this); 3431 verifier.verify(block_at(0)); 3432 } 3433 3434 3435 void RegisterVerifier::verify(BlockBegin* start) { 3436 // setup input registers (method arguments) for first block 3437 IntervalList* input_state = new IntervalList(state_size(), NULL); 3438 CallingConvention* args = compilation()->frame_map()->incoming_arguments(); 3439 for (int n = 0; n < args->length(); n++) { 3440 LIR_Opr opr = args->at(n); 3441 if (opr->is_register()) { 3442 Interval* interval = interval_at(reg_num(opr)); 3443 3444 if (interval->assigned_reg() < state_size()) { 3445 input_state->at_put(interval->assigned_reg(), interval); 3446 } 3447 if (interval->assigned_regHi() != LinearScan::any_reg && interval->assigned_regHi() < state_size()) { 3448 input_state->at_put(interval->assigned_regHi(), interval); 3449 } 3450 } 3451 } 3452 3453 set_state_for_block(start, input_state); 3454 add_to_work_list(start); 3455 3456 // main loop for verification 3457 do { 3458 BlockBegin* block = _work_list.at(0); 3459 _work_list.remove_at(0); 3460 3461 process_block(block); 3462 } while (!_work_list.is_empty()); 3463 } 3464 3465 void RegisterVerifier::process_block(BlockBegin* block) { 3466 TRACE_LINEAR_SCAN(2, tty->cr(); tty->print_cr("process_block B%d", block->block_id())); 3467 3468 // must copy state because it is modified 3469 IntervalList* input_state = copy(state_for_block(block)); 3470 3471 if (TraceLinearScanLevel >= 4) { 3472 tty->print_cr("Input-State of intervals:"); 3473 tty->print(" "); 3474 for (int i = 0; i < state_size(); i++) { 3475 if (input_state->at(i) != NULL) { 3476 tty->print(" %4d", input_state->at(i)->reg_num()); 3477 } else { 3478 tty->print(" __"); 3479 } 3480 } 3481 tty->cr(); 3482 tty->cr(); 3483 } 3484 3485 // process all operations of the block 3486 process_operations(block->lir(), input_state); 3487 3488 // iterate all successors 3489 for (int i = 0; i < block->number_of_sux(); i++) { 3490 process_successor(block->sux_at(i), input_state); 3491 } 3492 } 3493 3494 void RegisterVerifier::process_xhandler(XHandler* xhandler, IntervalList* input_state) { 3495 TRACE_LINEAR_SCAN(2, tty->print_cr("process_xhandler B%d", xhandler->entry_block()->block_id())); 3496 3497 // must copy state because it is modified 3498 input_state = copy(input_state); 3499 3500 if (xhandler->entry_code() != NULL) { 3501 process_operations(xhandler->entry_code(), input_state); 3502 } 3503 process_successor(xhandler->entry_block(), input_state); 3504 } 3505 3506 void RegisterVerifier::process_successor(BlockBegin* block, IntervalList* input_state) { 3507 IntervalList* saved_state = state_for_block(block); 3508 3509 if (saved_state != NULL) { 3510 // this block was already processed before. 3511 // check if new input_state is consistent with saved_state 3512 3513 bool saved_state_correct = true; 3514 for (int i = 0; i < state_size(); i++) { 3515 if (input_state->at(i) != saved_state->at(i)) { 3516 // current input_state and previous saved_state assume a different 3517 // interval in this register -> assume that this register is invalid 3518 if (saved_state->at(i) != NULL) { 3519 // invalidate old calculation only if it assumed that 3520 // register was valid. when the register was already invalid, 3521 // then the old calculation was correct. 3522 saved_state_correct = false; 3523 saved_state->at_put(i, NULL); 3524 3525 TRACE_LINEAR_SCAN(4, tty->print_cr("process_successor B%d: invalidating slot %d", block->block_id(), i)); 3526 } 3527 } 3528 } 3529 3530 if (saved_state_correct) { 3531 // already processed block with correct input_state 3532 TRACE_LINEAR_SCAN(2, tty->print_cr("process_successor B%d: previous visit already correct", block->block_id())); 3533 } else { 3534 // must re-visit this block 3535 TRACE_LINEAR_SCAN(2, tty->print_cr("process_successor B%d: must re-visit because input state changed", block->block_id())); 3536 add_to_work_list(block); 3537 } 3538 3539 } else { 3540 // block was not processed before, so set initial input_state 3541 TRACE_LINEAR_SCAN(2, tty->print_cr("process_successor B%d: initial visit", block->block_id())); 3542 3543 set_state_for_block(block, copy(input_state)); 3544 add_to_work_list(block); 3545 } 3546 } 3547 3548 3549 IntervalList* RegisterVerifier::copy(IntervalList* input_state) { 3550 IntervalList* copy_state = new IntervalList(input_state->length()); 3551 copy_state->push_all(input_state); 3552 return copy_state; 3553 } 3554 3555 void RegisterVerifier::state_put(IntervalList* input_state, int reg, Interval* interval) { 3556 if (reg != LinearScan::any_reg && reg < state_size()) { 3557 if (interval != NULL) { 3558 TRACE_LINEAR_SCAN(4, tty->print_cr(" reg[%d] = %d", reg, interval->reg_num())); 3559 } else if (input_state->at(reg) != NULL) { 3560 TRACE_LINEAR_SCAN(4, tty->print_cr(" reg[%d] = NULL", reg)); 3561 } 3562 3563 input_state->at_put(reg, interval); 3564 } 3565 } 3566 3567 bool RegisterVerifier::check_state(IntervalList* input_state, int reg, Interval* interval) { 3568 if (reg != LinearScan::any_reg && reg < state_size()) { 3569 if (input_state->at(reg) != interval) { 3570 tty->print_cr("!! Error in register allocation: register %d does not contain interval %d", reg, interval->reg_num()); 3571 return true; 3572 } 3573 } 3574 return false; 3575 } 3576 3577 void RegisterVerifier::process_operations(LIR_List* ops, IntervalList* input_state) { 3578 // visit all instructions of the block 3579 LIR_OpVisitState visitor; 3580 bool has_error = false; 3581 3582 for (int i = 0; i < ops->length(); i++) { 3583 LIR_Op* op = ops->at(i); 3584 visitor.visit(op); 3585 3586 TRACE_LINEAR_SCAN(4, op->print_on(tty)); 3587 3588 // check if input operands are correct 3589 int j; 3590 int n = visitor.opr_count(LIR_OpVisitState::inputMode); 3591 for (j = 0; j < n; j++) { 3592 LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::inputMode, j); 3593 if (opr->is_register() && LinearScan::is_processed_reg_num(reg_num(opr))) { 3594 Interval* interval = interval_at(reg_num(opr)); 3595 if (op->id() != -1) { 3596 interval = interval->split_child_at_op_id(op->id(), LIR_OpVisitState::inputMode); 3597 } 3598 3599 has_error |= check_state(input_state, interval->assigned_reg(), interval->split_parent()); 3600 has_error |= check_state(input_state, interval->assigned_regHi(), interval->split_parent()); 3601 3602 // When an operand is marked with is_last_use, then the fpu stack allocator 3603 // removes the register from the fpu stack -> the register contains no value 3604 if (opr->is_last_use()) { 3605 state_put(input_state, interval->assigned_reg(), NULL); 3606 state_put(input_state, interval->assigned_regHi(), NULL); 3607 } 3608 } 3609 } 3610 3611 // invalidate all caller save registers at calls 3612 if (visitor.has_call()) { 3613 for (j = 0; j < FrameMap::nof_caller_save_cpu_regs(); j++) { 3614 state_put(input_state, reg_num(FrameMap::caller_save_cpu_reg_at(j)), NULL); 3615 } 3616 for (j = 0; j < FrameMap::nof_caller_save_fpu_regs; j++) { 3617 state_put(input_state, reg_num(FrameMap::caller_save_fpu_reg_at(j)), NULL); 3618 } 3619 3620 #ifdef X86 3621 for (j = 0; j < FrameMap::nof_caller_save_xmm_regs; j++) { 3622 state_put(input_state, reg_num(FrameMap::caller_save_xmm_reg_at(j)), NULL); 3623 } 3624 #endif 3625 } 3626 3627 // process xhandler before output and temp operands 3628 XHandlers* xhandlers = visitor.all_xhandler(); 3629 n = xhandlers->length(); 3630 for (int k = 0; k < n; k++) { 3631 process_xhandler(xhandlers->handler_at(k), input_state); 3632 } 3633 3634 // set temp operands (some operations use temp operands also as output operands, so can't set them NULL) 3635 n = visitor.opr_count(LIR_OpVisitState::tempMode); 3636 for (j = 0; j < n; j++) { 3637 LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::tempMode, j); 3638 if (opr->is_register() && LinearScan::is_processed_reg_num(reg_num(opr))) { 3639 Interval* interval = interval_at(reg_num(opr)); 3640 if (op->id() != -1) { 3641 interval = interval->split_child_at_op_id(op->id(), LIR_OpVisitState::tempMode); 3642 } 3643 3644 state_put(input_state, interval->assigned_reg(), interval->split_parent()); 3645 state_put(input_state, interval->assigned_regHi(), interval->split_parent()); 3646 } 3647 } 3648 3649 // set output operands 3650 n = visitor.opr_count(LIR_OpVisitState::outputMode); 3651 for (j = 0; j < n; j++) { 3652 LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::outputMode, j); 3653 if (opr->is_register() && LinearScan::is_processed_reg_num(reg_num(opr))) { 3654 Interval* interval = interval_at(reg_num(opr)); 3655 if (op->id() != -1) { 3656 interval = interval->split_child_at_op_id(op->id(), LIR_OpVisitState::outputMode); 3657 } 3658 3659 state_put(input_state, interval->assigned_reg(), interval->split_parent()); 3660 state_put(input_state, interval->assigned_regHi(), interval->split_parent()); 3661 } 3662 } 3663 } 3664 assert(has_error == false, "Error in register allocation"); 3665 } 3666 3667 #endif // ASSERT 3668 3669 3670 3671 // **** Implementation of MoveResolver ****************************** 3672 3673 MoveResolver::MoveResolver(LinearScan* allocator) : 3674 _allocator(allocator), 3675 _multiple_reads_allowed(false), 3676 _mapping_from(8), 3677 _mapping_from_opr(8), 3678 _mapping_to(8), 3679 _insert_list(NULL), 3680 _insert_idx(-1), 3681 _insertion_buffer() 3682 { 3683 for (int i = 0; i < LinearScan::nof_regs; i++) { 3684 _register_blocked[i] = 0; 3685 } 3686 DEBUG_ONLY(check_empty()); 3687 } 3688 3689 3690 #ifdef ASSERT 3691 3692 void MoveResolver::check_empty() { 3693 assert(_mapping_from.length() == 0 && _mapping_from_opr.length() == 0 && _mapping_to.length() == 0, "list must be empty before and after processing"); 3694 for (int i = 0; i < LinearScan::nof_regs; i++) { 3695 assert(register_blocked(i) == 0, "register map must be empty before and after processing"); 3696 } 3697 assert(_multiple_reads_allowed == false, "must have default value"); 3698 } 3699 3700 void MoveResolver::verify_before_resolve() { 3701 assert(_mapping_from.length() == _mapping_from_opr.length(), "length must be equal"); 3702 assert(_mapping_from.length() == _mapping_to.length(), "length must be equal"); 3703 assert(_insert_list != NULL && _insert_idx != -1, "insert position not set"); 3704 3705 int i, j; 3706 if (!_multiple_reads_allowed) { 3707 for (i = 0; i < _mapping_from.length(); i++) { 3708 for (j = i + 1; j < _mapping_from.length(); j++) { 3709 assert(_mapping_from.at(i) == NULL || _mapping_from.at(i) != _mapping_from.at(j), "cannot read from same interval twice"); 3710 } 3711 } 3712 } 3713 3714 for (i = 0; i < _mapping_to.length(); i++) { 3715 for (j = i + 1; j < _mapping_to.length(); j++) { 3716 assert(_mapping_to.at(i) != _mapping_to.at(j), "cannot write to same interval twice"); 3717 } 3718 } 3719 3720 3721 BitMap used_regs(LinearScan::nof_regs + allocator()->frame_map()->argcount() + allocator()->max_spills()); 3722 used_regs.clear(); 3723 if (!_multiple_reads_allowed) { 3724 for (i = 0; i < _mapping_from.length(); i++) { 3725 Interval* it = _mapping_from.at(i); 3726 if (it != NULL) { 3727 assert(!used_regs.at(it->assigned_reg()), "cannot read from same register twice"); 3728 used_regs.set_bit(it->assigned_reg()); 3729 3730 if (it->assigned_regHi() != LinearScan::any_reg) { 3731 assert(!used_regs.at(it->assigned_regHi()), "cannot read from same register twice"); 3732 used_regs.set_bit(it->assigned_regHi()); 3733 } 3734 } 3735 } 3736 } 3737 3738 used_regs.clear(); 3739 for (i = 0; i < _mapping_to.length(); i++) { 3740 Interval* it = _mapping_to.at(i); 3741 assert(!used_regs.at(it->assigned_reg()), "cannot write to same register twice"); 3742 used_regs.set_bit(it->assigned_reg()); 3743 3744 if (it->assigned_regHi() != LinearScan::any_reg) { 3745 assert(!used_regs.at(it->assigned_regHi()), "cannot write to same register twice"); 3746 used_regs.set_bit(it->assigned_regHi()); 3747 } 3748 } 3749 3750 used_regs.clear(); 3751 for (i = 0; i < _mapping_from.length(); i++) { 3752 Interval* it = _mapping_from.at(i); 3753 if (it != NULL && it->assigned_reg() >= LinearScan::nof_regs) { 3754 used_regs.set_bit(it->assigned_reg()); 3755 } 3756 } 3757 for (i = 0; i < _mapping_to.length(); i++) { 3758 Interval* it = _mapping_to.at(i); 3759 assert(!used_regs.at(it->assigned_reg()) || it->assigned_reg() == _mapping_from.at(i)->assigned_reg(), "stack slots used in _mapping_from must be disjoint to _mapping_to"); 3760 } 3761 } 3762 3763 #endif // ASSERT 3764 3765 3766 // mark assigned_reg and assigned_regHi of the interval as blocked 3767 void MoveResolver::block_registers(Interval* it) { 3768 int reg = it->assigned_reg(); 3769 if (reg < LinearScan::nof_regs) { 3770 assert(_multiple_reads_allowed || register_blocked(reg) == 0, "register already marked as used"); 3771 set_register_blocked(reg, 1); 3772 } 3773 reg = it->assigned_regHi(); 3774 if (reg != LinearScan::any_reg && reg < LinearScan::nof_regs) { 3775 assert(_multiple_reads_allowed || register_blocked(reg) == 0, "register already marked as used"); 3776 set_register_blocked(reg, 1); 3777 } 3778 } 3779 3780 // mark assigned_reg and assigned_regHi of the interval as unblocked 3781 void MoveResolver::unblock_registers(Interval* it) { 3782 int reg = it->assigned_reg(); 3783 if (reg < LinearScan::nof_regs) { 3784 assert(register_blocked(reg) > 0, "register already marked as unused"); 3785 set_register_blocked(reg, -1); 3786 } 3787 reg = it->assigned_regHi(); 3788 if (reg != LinearScan::any_reg && reg < LinearScan::nof_regs) { 3789 assert(register_blocked(reg) > 0, "register already marked as unused"); 3790 set_register_blocked(reg, -1); 3791 } 3792 } 3793 3794 // check if assigned_reg and assigned_regHi of the to-interval are not blocked (or only blocked by from) 3795 bool MoveResolver::save_to_process_move(Interval* from, Interval* to) { 3796 int from_reg = -1; 3797 int from_regHi = -1; 3798 if (from != NULL) { 3799 from_reg = from->assigned_reg(); 3800 from_regHi = from->assigned_regHi(); 3801 } 3802 3803 int reg = to->assigned_reg(); 3804 if (reg < LinearScan::nof_regs) { 3805 if (register_blocked(reg) > 1 || (register_blocked(reg) == 1 && reg != from_reg && reg != from_regHi)) { 3806 return false; 3807 } 3808 } 3809 reg = to->assigned_regHi(); 3810 if (reg != LinearScan::any_reg && reg < LinearScan::nof_regs) { 3811 if (register_blocked(reg) > 1 || (register_blocked(reg) == 1 && reg != from_reg && reg != from_regHi)) { 3812 return false; 3813 } 3814 } 3815 3816 return true; 3817 } 3818 3819 3820 void MoveResolver::create_insertion_buffer(LIR_List* list) { 3821 assert(!_insertion_buffer.initialized(), "overwriting existing buffer"); 3822 _insertion_buffer.init(list); 3823 } 3824 3825 void MoveResolver::append_insertion_buffer() { 3826 if (_insertion_buffer.initialized()) { 3827 _insertion_buffer.lir_list()->append(&_insertion_buffer); 3828 } 3829 assert(!_insertion_buffer.initialized(), "must be uninitialized now"); 3830 3831 _insert_list = NULL; 3832 _insert_idx = -1; 3833 } 3834 3835 void MoveResolver::insert_move(Interval* from_interval, Interval* to_interval) { 3836 assert(from_interval->reg_num() != to_interval->reg_num(), "from and to interval equal"); 3837 assert(from_interval->type() == to_interval->type(), "move between different types"); 3838 assert(_insert_list != NULL && _insert_idx != -1, "must setup insert position first"); 3839 assert(_insertion_buffer.lir_list() == _insert_list, "wrong insertion buffer"); 3840 3841 LIR_Opr from_opr = LIR_OprFact::virtual_register(from_interval->reg_num(), from_interval->type()); 3842 LIR_Opr to_opr = LIR_OprFact::virtual_register(to_interval->reg_num(), to_interval->type()); 3843 3844 if (!_multiple_reads_allowed) { 3845 // the last_use flag is an optimization for FPU stack allocation. When the same 3846 // input interval is used in more than one move, then it is too difficult to determine 3847 // if this move is really the last use. 3848 from_opr = from_opr->make_last_use(); 3849 } 3850 _insertion_buffer.move(_insert_idx, from_opr, to_opr); 3851 3852 TRACE_LINEAR_SCAN(4, tty->print_cr("MoveResolver: inserted move from register %d (%d, %d) to %d (%d, %d)", from_interval->reg_num(), from_interval->assigned_reg(), from_interval->assigned_regHi(), to_interval->reg_num(), to_interval->assigned_reg(), to_interval->assigned_regHi())); 3853 } 3854 3855 void MoveResolver::insert_move(LIR_Opr from_opr, Interval* to_interval) { 3856 assert(from_opr->type() == to_interval->type(), "move between different types"); 3857 assert(_insert_list != NULL && _insert_idx != -1, "must setup insert position first"); 3858 assert(_insertion_buffer.lir_list() == _insert_list, "wrong insertion buffer"); 3859 3860 LIR_Opr to_opr = LIR_OprFact::virtual_register(to_interval->reg_num(), to_interval->type()); 3861 _insertion_buffer.move(_insert_idx, from_opr, to_opr); 3862 3863 TRACE_LINEAR_SCAN(4, tty->print("MoveResolver: inserted move from constant "); from_opr->print(); tty->print_cr(" to %d (%d, %d)", to_interval->reg_num(), to_interval->assigned_reg(), to_interval->assigned_regHi())); 3864 } 3865 3866 3867 void MoveResolver::resolve_mappings() { 3868 TRACE_LINEAR_SCAN(4, tty->print_cr("MoveResolver: resolving mappings for Block B%d, index %d", _insert_list->block() != NULL ? _insert_list->block()->block_id() : -1, _insert_idx)); 3869 DEBUG_ONLY(verify_before_resolve()); 3870 3871 // Block all registers that are used as input operands of a move. 3872 // When a register is blocked, no move to this register is emitted. 3873 // This is necessary for detecting cycles in moves. 3874 int i; 3875 for (i = _mapping_from.length() - 1; i >= 0; i--) { 3876 Interval* from_interval = _mapping_from.at(i); 3877 if (from_interval != NULL) { 3878 block_registers(from_interval); 3879 } 3880 } 3881 3882 int spill_candidate = -1; 3883 while (_mapping_from.length() > 0) { 3884 bool processed_interval = false; 3885 3886 for (i = _mapping_from.length() - 1; i >= 0; i--) { 3887 Interval* from_interval = _mapping_from.at(i); 3888 Interval* to_interval = _mapping_to.at(i); 3889 3890 if (save_to_process_move(from_interval, to_interval)) { 3891 // this inverval can be processed because target is free 3892 if (from_interval != NULL) { 3893 insert_move(from_interval, to_interval); 3894 unblock_registers(from_interval); 3895 } else { 3896 insert_move(_mapping_from_opr.at(i), to_interval); 3897 } 3898 _mapping_from.remove_at(i); 3899 _mapping_from_opr.remove_at(i); 3900 _mapping_to.remove_at(i); 3901 3902 processed_interval = true; 3903 } else if (from_interval != NULL && from_interval->assigned_reg() < LinearScan::nof_regs) { 3904 // this interval cannot be processed now because target is not free 3905 // it starts in a register, so it is a possible candidate for spilling 3906 spill_candidate = i; 3907 } 3908 } 3909 3910 if (!processed_interval) { 3911 // no move could be processed because there is a cycle in the move list 3912 // (e.g. r1 -> r2, r2 -> r1), so one interval must be spilled to memory 3913 assert(spill_candidate != -1, "no interval in register for spilling found"); 3914 3915 // create a new spill interval and assign a stack slot to it 3916 Interval* from_interval = _mapping_from.at(spill_candidate); 3917 Interval* spill_interval = new Interval(-1); 3918 spill_interval->set_type(from_interval->type()); 3919 3920 // add a dummy range because real position is difficult to calculate 3921 // Note: this range is a special case when the integrity of the allocation is checked 3922 spill_interval->add_range(1, 2); 3923 3924 // do not allocate a new spill slot for temporary interval, but 3925 // use spill slot assigned to from_interval. Otherwise moves from 3926 // one stack slot to another can happen (not allowed by LIR_Assembler 3927 int spill_slot = from_interval->canonical_spill_slot(); 3928 if (spill_slot < 0) { 3929 spill_slot = allocator()->allocate_spill_slot(type2spill_size[spill_interval->type()] == 2); 3930 from_interval->set_canonical_spill_slot(spill_slot); 3931 } 3932 spill_interval->assign_reg(spill_slot); 3933 allocator()->append_interval(spill_interval); 3934 3935 TRACE_LINEAR_SCAN(4, tty->print_cr("created new Interval %d for spilling", spill_interval->reg_num())); 3936 3937 // insert a move from register to stack and update the mapping 3938 insert_move(from_interval, spill_interval); 3939 _mapping_from.at_put(spill_candidate, spill_interval); 3940 unblock_registers(from_interval); 3941 } 3942 } 3943 3944 // reset to default value 3945 _multiple_reads_allowed = false; 3946 3947 // check that all intervals have been processed 3948 DEBUG_ONLY(check_empty()); 3949 } 3950 3951 3952 void MoveResolver::set_insert_position(LIR_List* insert_list, int insert_idx) { 3953 TRACE_LINEAR_SCAN(4, tty->print_cr("MoveResolver: setting insert position to Block B%d, index %d", insert_list->block() != NULL ? insert_list->block()->block_id() : -1, insert_idx)); 3954 assert(_insert_list == NULL && _insert_idx == -1, "use move_insert_position instead of set_insert_position when data already set"); 3955 3956 create_insertion_buffer(insert_list); 3957 _insert_list = insert_list; 3958 _insert_idx = insert_idx; 3959 } 3960 3961 void MoveResolver::move_insert_position(LIR_List* insert_list, int insert_idx) { 3962 TRACE_LINEAR_SCAN(4, tty->print_cr("MoveResolver: moving insert position to Block B%d, index %d", insert_list->block() != NULL ? insert_list->block()->block_id() : -1, insert_idx)); 3963 3964 if (_insert_list != NULL && (insert_list != _insert_list || insert_idx != _insert_idx)) { 3965 // insert position changed -> resolve current mappings 3966 resolve_mappings(); 3967 } 3968 3969 if (insert_list != _insert_list) { 3970 // block changed -> append insertion_buffer because it is 3971 // bound to a specific block and create a new insertion_buffer 3972 append_insertion_buffer(); 3973 create_insertion_buffer(insert_list); 3974 } 3975 3976 _insert_list = insert_list; 3977 _insert_idx = insert_idx; 3978 } 3979 3980 void MoveResolver::add_mapping(Interval* from_interval, Interval* to_interval) { 3981 TRACE_LINEAR_SCAN(4, tty->print_cr("MoveResolver: adding mapping from %d (%d, %d) to %d (%d, %d)", from_interval->reg_num(), from_interval->assigned_reg(), from_interval->assigned_regHi(), to_interval->reg_num(), to_interval->assigned_reg(), to_interval->assigned_regHi())); 3982 3983 _mapping_from.append(from_interval); 3984 _mapping_from_opr.append(LIR_OprFact::illegalOpr); 3985 _mapping_to.append(to_interval); 3986 } 3987 3988 3989 void MoveResolver::add_mapping(LIR_Opr from_opr, Interval* to_interval) { 3990 TRACE_LINEAR_SCAN(4, tty->print("MoveResolver: adding mapping from "); from_opr->print(); tty->print_cr(" to %d (%d, %d)", to_interval->reg_num(), to_interval->assigned_reg(), to_interval->assigned_regHi())); 3991 assert(from_opr->is_constant(), "only for constants"); 3992 3993 _mapping_from.append(NULL); 3994 _mapping_from_opr.append(from_opr); 3995 _mapping_to.append(to_interval); 3996 } 3997 3998 void MoveResolver::resolve_and_append_moves() { 3999 if (has_mappings()) { 4000 resolve_mappings(); 4001 } 4002 append_insertion_buffer(); 4003 } 4004 4005 4006 4007 // **** Implementation of Range ************************************* 4008 4009 Range::Range(int from, int to, Range* next) : 4010 _from(from), 4011 _to(to), 4012 _next(next) 4013 { 4014 } 4015 4016 // initialize sentinel 4017 Range* Range::_end = NULL; 4018 void Range::initialize(Arena* arena) { 4019 _end = new (arena) Range(max_jint, max_jint, NULL); 4020 } 4021 4022 int Range::intersects_at(Range* r2) const { 4023 const Range* r1 = this; 4024 4025 assert(r1 != NULL && r2 != NULL, "null ranges not allowed"); 4026 assert(r1 != _end && r2 != _end, "empty ranges not allowed"); 4027 4028 do { 4029 if (r1->from() < r2->from()) { 4030 if (r1->to() <= r2->from()) { 4031 r1 = r1->next(); if (r1 == _end) return -1; 4032 } else { 4033 return r2->from(); 4034 } 4035 } else if (r2->from() < r1->from()) { 4036 if (r2->to() <= r1->from()) { 4037 r2 = r2->next(); if (r2 == _end) return -1; 4038 } else { 4039 return r1->from(); 4040 } 4041 } else { // r1->from() == r2->from() 4042 if (r1->from() == r1->to()) { 4043 r1 = r1->next(); if (r1 == _end) return -1; 4044 } else if (r2->from() == r2->to()) { 4045 r2 = r2->next(); if (r2 == _end) return -1; 4046 } else { 4047 return r1->from(); 4048 } 4049 } 4050 } while (true); 4051 } 4052 4053 #ifndef PRODUCT 4054 void Range::print(outputStream* out) const { 4055 out->print("[%d, %d[ ", _from, _to); 4056 } 4057 #endif 4058 4059 4060 4061 // **** Implementation of Interval ********************************** 4062 4063 // initialize sentinel 4064 Interval* Interval::_end = NULL; 4065 void Interval::initialize(Arena* arena) { 4066 Range::initialize(arena); 4067 _end = new (arena) Interval(-1); 4068 } 4069 4070 Interval::Interval(int reg_num) : 4071 _reg_num(reg_num), 4072 _type(T_ILLEGAL), 4073 _first(Range::end()), 4074 _use_pos_and_kinds(12), 4075 _current(Range::end()), 4076 _next(_end), 4077 _state(invalidState), 4078 _assigned_reg(LinearScan::any_reg), 4079 _assigned_regHi(LinearScan::any_reg), 4080 _cached_to(-1), 4081 _cached_opr(LIR_OprFact::illegalOpr), 4082 _cached_vm_reg(VMRegImpl::Bad()), 4083 _split_children(0), 4084 _canonical_spill_slot(-1), 4085 _insert_move_when_activated(false), 4086 _register_hint(NULL), 4087 _spill_state(noDefinitionFound), 4088 _spill_definition_pos(-1) 4089 { 4090 _split_parent = this; 4091 _current_split_child = this; 4092 } 4093 4094 int Interval::calc_to() { 4095 assert(_first != Range::end(), "interval has no range"); 4096 4097 Range* r = _first; 4098 while (r->next() != Range::end()) { 4099 r = r->next(); 4100 } 4101 return r->to(); 4102 } 4103 4104 4105 #ifdef ASSERT 4106 // consistency check of split-children 4107 void Interval::check_split_children() { 4108 if (_split_children.length() > 0) { 4109 assert(is_split_parent(), "only split parents can have children"); 4110 4111 for (int i = 0; i < _split_children.length(); i++) { 4112 Interval* i1 = _split_children.at(i); 4113 4114 assert(i1->split_parent() == this, "not a split child of this interval"); 4115 assert(i1->type() == type(), "must be equal for all split children"); 4116 assert(i1->canonical_spill_slot() == canonical_spill_slot(), "must be equal for all split children"); 4117 4118 for (int j = i + 1; j < _split_children.length(); j++) { 4119 Interval* i2 = _split_children.at(j); 4120 4121 assert(i1->reg_num() != i2->reg_num(), "same register number"); 4122 4123 if (i1->from() < i2->from()) { 4124 assert(i1->to() <= i2->from() && i1->to() < i2->to(), "intervals overlapping"); 4125 } else { 4126 assert(i2->from() < i1->from(), "intervals start at same op_id"); 4127 assert(i2->to() <= i1->from() && i2->to() < i1->to(), "intervals overlapping"); 4128 } 4129 } 4130 } 4131 } 4132 } 4133 #endif // ASSERT 4134 4135 Interval* Interval::register_hint(bool search_split_child) const { 4136 if (!search_split_child) { 4137 return _register_hint; 4138 } 4139 4140 if (_register_hint != NULL) { 4141 assert(_register_hint->is_split_parent(), "ony split parents are valid hint registers"); 4142 4143 if (_register_hint->assigned_reg() >= 0 && _register_hint->assigned_reg() < LinearScan::nof_regs) { 4144 return _register_hint; 4145 4146 } else if (_register_hint->_split_children.length() > 0) { 4147 // search the first split child that has a register assigned 4148 int len = _register_hint->_split_children.length(); 4149 for (int i = 0; i < len; i++) { 4150 Interval* cur = _register_hint->_split_children.at(i); 4151 4152 if (cur->assigned_reg() >= 0 && cur->assigned_reg() < LinearScan::nof_regs) { 4153 return cur; 4154 } 4155 } 4156 } 4157 } 4158 4159 // no hint interval found that has a register assigned 4160 return NULL; 4161 } 4162 4163 4164 Interval* Interval::split_child_at_op_id(int op_id, LIR_OpVisitState::OprMode mode) { 4165 assert(is_split_parent(), "can only be called for split parents"); 4166 assert(op_id >= 0, "invalid op_id (method can not be called for spill moves)"); 4167 4168 Interval* result; 4169 if (_split_children.length() == 0) { 4170 result = this; 4171 } else { 4172 result = NULL; 4173 int len = _split_children.length(); 4174 4175 // in outputMode, the end of the interval (op_id == cur->to()) is not valid 4176 int to_offset = (mode == LIR_OpVisitState::outputMode ? 0 : 1); 4177 4178 int i; 4179 for (i = 0; i < len; i++) { 4180 Interval* cur = _split_children.at(i); 4181 if (cur->from() <= op_id && op_id < cur->to() + to_offset) { 4182 if (i > 0) { 4183 // exchange current split child to start of list (faster access for next call) 4184 _split_children.at_put(i, _split_children.at(0)); 4185 _split_children.at_put(0, cur); 4186 } 4187 4188 // interval found 4189 result = cur; 4190 break; 4191 } 4192 } 4193 4194 #ifdef ASSERT 4195 for (i = 0; i < len; i++) { 4196 Interval* tmp = _split_children.at(i); 4197 if (tmp != result && tmp->from() <= op_id && op_id < tmp->to() + to_offset) { 4198 tty->print_cr("two valid result intervals found for op_id %d: %d and %d", op_id, result->reg_num(), tmp->reg_num()); 4199 result->print(); 4200 tmp->print(); 4201 assert(false, "two valid result intervals found"); 4202 } 4203 } 4204 #endif 4205 } 4206 4207 assert(result != NULL, "no matching interval found"); 4208 assert(result->covers(op_id, mode), "op_id not covered by interval"); 4209 4210 return result; 4211 } 4212 4213 4214 // returns the last split child that ends before the given op_id 4215 Interval* Interval::split_child_before_op_id(int op_id) { 4216 assert(op_id >= 0, "invalid op_id"); 4217 4218 Interval* parent = split_parent(); 4219 Interval* result = NULL; 4220 4221 int len = parent->_split_children.length(); 4222 assert(len > 0, "no split children available"); 4223 4224 for (int i = len - 1; i >= 0; i--) { 4225 Interval* cur = parent->_split_children.at(i); 4226 if (cur->to() <= op_id && (result == NULL || result->to() < cur->to())) { 4227 result = cur; 4228 } 4229 } 4230 4231 assert(result != NULL, "no split child found"); 4232 return result; 4233 } 4234 4235 4236 // checks if op_id is covered by any split child 4237 bool Interval::split_child_covers(int op_id, LIR_OpVisitState::OprMode mode) { 4238 assert(is_split_parent(), "can only be called for split parents"); 4239 assert(op_id >= 0, "invalid op_id (method can not be called for spill moves)"); 4240 4241 if (_split_children.length() == 0) { 4242 // simple case if interval was not split 4243 return covers(op_id, mode); 4244 4245 } else { 4246 // extended case: check all split children 4247 int len = _split_children.length(); 4248 for (int i = 0; i < len; i++) { 4249 Interval* cur = _split_children.at(i); 4250 if (cur->covers(op_id, mode)) { 4251 return true; 4252 } 4253 } 4254 return false; 4255 } 4256 } 4257 4258 4259 // Note: use positions are sorted descending -> first use has highest index 4260 int Interval::first_usage(IntervalUseKind min_use_kind) const { 4261 assert(LinearScan::is_virtual_interval(this), "cannot access use positions for fixed intervals"); 4262 4263 for (int i = _use_pos_and_kinds.length() - 2; i >= 0; i -= 2) { 4264 if (_use_pos_and_kinds.at(i + 1) >= min_use_kind) { 4265 return _use_pos_and_kinds.at(i); 4266 } 4267 } 4268 return max_jint; 4269 } 4270 4271 int Interval::next_usage(IntervalUseKind min_use_kind, int from) const { 4272 assert(LinearScan::is_virtual_interval(this), "cannot access use positions for fixed intervals"); 4273 4274 for (int i = _use_pos_and_kinds.length() - 2; i >= 0; i -= 2) { 4275 if (_use_pos_and_kinds.at(i) >= from && _use_pos_and_kinds.at(i + 1) >= min_use_kind) { 4276 return _use_pos_and_kinds.at(i); 4277 } 4278 } 4279 return max_jint; 4280 } 4281 4282 int Interval::next_usage_exact(IntervalUseKind exact_use_kind, int from) const { 4283 assert(LinearScan::is_virtual_interval(this), "cannot access use positions for fixed intervals"); 4284 4285 for (int i = _use_pos_and_kinds.length() - 2; i >= 0; i -= 2) { 4286 if (_use_pos_and_kinds.at(i) >= from && _use_pos_and_kinds.at(i + 1) == exact_use_kind) { 4287 return _use_pos_and_kinds.at(i); 4288 } 4289 } 4290 return max_jint; 4291 } 4292 4293 int Interval::previous_usage(IntervalUseKind min_use_kind, int from) const { 4294 assert(LinearScan::is_virtual_interval(this), "cannot access use positions for fixed intervals"); 4295 4296 int prev = 0; 4297 for (int i = _use_pos_and_kinds.length() - 2; i >= 0; i -= 2) { 4298 if (_use_pos_and_kinds.at(i) > from) { 4299 return prev; 4300 } 4301 if (_use_pos_and_kinds.at(i + 1) >= min_use_kind) { 4302 prev = _use_pos_and_kinds.at(i); 4303 } 4304 } 4305 return prev; 4306 } 4307 4308 void Interval::add_use_pos(int pos, IntervalUseKind use_kind) { 4309 assert(covers(pos, LIR_OpVisitState::inputMode), "use position not covered by live range"); 4310 4311 // do not add use positions for precolored intervals because 4312 // they are never used 4313 if (use_kind != noUse && reg_num() >= LIR_OprDesc::vreg_base) { 4314 #ifdef ASSERT 4315 assert(_use_pos_and_kinds.length() % 2 == 0, "must be"); 4316 for (int i = 0; i < _use_pos_and_kinds.length(); i += 2) { 4317 assert(pos <= _use_pos_and_kinds.at(i), "already added a use-position with lower position"); 4318 assert(_use_pos_and_kinds.at(i + 1) >= firstValidKind && _use_pos_and_kinds.at(i + 1) <= lastValidKind, "invalid use kind"); 4319 if (i > 0) { 4320 assert(_use_pos_and_kinds.at(i) < _use_pos_and_kinds.at(i - 2), "not sorted descending"); 4321 } 4322 } 4323 #endif 4324 4325 // Note: add_use is called in descending order, so list gets sorted 4326 // automatically by just appending new use positions 4327 int len = _use_pos_and_kinds.length(); 4328 if (len == 0 || _use_pos_and_kinds.at(len - 2) > pos) { 4329 _use_pos_and_kinds.append(pos); 4330 _use_pos_and_kinds.append(use_kind); 4331 } else if (_use_pos_and_kinds.at(len - 1) < use_kind) { 4332 assert(_use_pos_and_kinds.at(len - 2) == pos, "list not sorted correctly"); 4333 _use_pos_and_kinds.at_put(len - 1, use_kind); 4334 } 4335 } 4336 } 4337 4338 void Interval::add_range(int from, int to) { 4339 assert(from < to, "invalid range"); 4340 assert(first() == Range::end() || to < first()->next()->from(), "not inserting at begin of interval"); 4341 assert(from <= first()->to(), "not inserting at begin of interval"); 4342 4343 if (first()->from() <= to) { 4344 // join intersecting ranges 4345 first()->set_from(MIN2(from, first()->from())); 4346 first()->set_to (MAX2(to, first()->to())); 4347 } else { 4348 // insert new range 4349 _first = new Range(from, to, first()); 4350 } 4351 } 4352 4353 Interval* Interval::new_split_child() { 4354 // allocate new interval 4355 Interval* result = new Interval(-1); 4356 result->set_type(type()); 4357 4358 Interval* parent = split_parent(); 4359 result->_split_parent = parent; 4360 result->set_register_hint(parent); 4361 4362 // insert new interval in children-list of parent 4363 if (parent->_split_children.length() == 0) { 4364 assert(is_split_parent(), "list must be initialized at first split"); 4365 4366 parent->_split_children = IntervalList(4); 4367 parent->_split_children.append(this); 4368 } 4369 parent->_split_children.append(result); 4370 4371 return result; 4372 } 4373 4374 // split this interval at the specified position and return 4375 // the remainder as a new interval. 4376 // 4377 // when an interval is split, a bi-directional link is established between the original interval 4378 // (the split parent) and the intervals that are split off this interval (the split children) 4379 // When a split child is split again, the new created interval is also a direct child 4380 // of the original parent (there is no tree of split children stored, but a flat list) 4381 // All split children are spilled to the same stack slot (stored in _canonical_spill_slot) 4382 // 4383 // Note: The new interval has no valid reg_num 4384 Interval* Interval::split(int split_pos) { 4385 assert(LinearScan::is_virtual_interval(this), "cannot split fixed intervals"); 4386 4387 // allocate new interval 4388 Interval* result = new_split_child(); 4389 4390 // split the ranges 4391 Range* prev = NULL; 4392 Range* cur = _first; 4393 while (cur != Range::end() && cur->to() <= split_pos) { 4394 prev = cur; 4395 cur = cur->next(); 4396 } 4397 assert(cur != Range::end(), "split interval after end of last range"); 4398 4399 if (cur->from() < split_pos) { 4400 result->_first = new Range(split_pos, cur->to(), cur->next()); 4401 cur->set_to(split_pos); 4402 cur->set_next(Range::end()); 4403 4404 } else { 4405 assert(prev != NULL, "split before start of first range"); 4406 result->_first = cur; 4407 prev->set_next(Range::end()); 4408 } 4409 result->_current = result->_first; 4410 _cached_to = -1; // clear cached value 4411 4412 // split list of use positions 4413 int total_len = _use_pos_and_kinds.length(); 4414 int start_idx = total_len - 2; 4415 while (start_idx >= 0 && _use_pos_and_kinds.at(start_idx) < split_pos) { 4416 start_idx -= 2; 4417 } 4418 4419 intStack new_use_pos_and_kinds(total_len - start_idx); 4420 int i; 4421 for (i = start_idx + 2; i < total_len; i++) { 4422 new_use_pos_and_kinds.append(_use_pos_and_kinds.at(i)); 4423 } 4424 4425 _use_pos_and_kinds.truncate(start_idx + 2); 4426 result->_use_pos_and_kinds = _use_pos_and_kinds; 4427 _use_pos_and_kinds = new_use_pos_and_kinds; 4428 4429 #ifdef ASSERT 4430 assert(_use_pos_and_kinds.length() % 2 == 0, "must have use kind for each use pos"); 4431 assert(result->_use_pos_and_kinds.length() % 2 == 0, "must have use kind for each use pos"); 4432 assert(_use_pos_and_kinds.length() + result->_use_pos_and_kinds.length() == total_len, "missed some entries"); 4433 4434 for (i = 0; i < _use_pos_and_kinds.length(); i += 2) { 4435 assert(_use_pos_and_kinds.at(i) < split_pos, "must be"); 4436 assert(_use_pos_and_kinds.at(i + 1) >= firstValidKind && _use_pos_and_kinds.at(i + 1) <= lastValidKind, "invalid use kind"); 4437 } 4438 for (i = 0; i < result->_use_pos_and_kinds.length(); i += 2) { 4439 assert(result->_use_pos_and_kinds.at(i) >= split_pos, "must be"); 4440 assert(result->_use_pos_and_kinds.at(i + 1) >= firstValidKind && result->_use_pos_and_kinds.at(i + 1) <= lastValidKind, "invalid use kind"); 4441 } 4442 #endif 4443 4444 return result; 4445 } 4446 4447 // split this interval at the specified position and return 4448 // the head as a new interval (the original interval is the tail) 4449 // 4450 // Currently, only the first range can be split, and the new interval 4451 // must not have split positions 4452 Interval* Interval::split_from_start(int split_pos) { 4453 assert(LinearScan::is_virtual_interval(this), "cannot split fixed intervals"); 4454 assert(split_pos > from() && split_pos < to(), "can only split inside interval"); 4455 assert(split_pos > _first->from() && split_pos <= _first->to(), "can only split inside first range"); 4456 assert(first_usage(noUse) > split_pos, "can not split when use positions are present"); 4457 4458 // allocate new interval 4459 Interval* result = new_split_child(); 4460 4461 // the new created interval has only one range (checked by assertion above), 4462 // so the splitting of the ranges is very simple 4463 result->add_range(_first->from(), split_pos); 4464 4465 if (split_pos == _first->to()) { 4466 assert(_first->next() != Range::end(), "must not be at end"); 4467 _first = _first->next(); 4468 } else { 4469 _first->set_from(split_pos); 4470 } 4471 4472 return result; 4473 } 4474 4475 4476 // returns true if the op_id is inside the interval 4477 bool Interval::covers(int op_id, LIR_OpVisitState::OprMode mode) const { 4478 Range* cur = _first; 4479 4480 while (cur != Range::end() && cur->to() < op_id) { 4481 cur = cur->next(); 4482 } 4483 if (cur != Range::end()) { 4484 assert(cur->to() != cur->next()->from(), "ranges not separated"); 4485 4486 if (mode == LIR_OpVisitState::outputMode) { 4487 return cur->from() <= op_id && op_id < cur->to(); 4488 } else { 4489 return cur->from() <= op_id && op_id <= cur->to(); 4490 } 4491 } 4492 return false; 4493 } 4494 4495 // returns true if the interval has any hole between hole_from and hole_to 4496 // (even if the hole has only the length 1) 4497 bool Interval::has_hole_between(int hole_from, int hole_to) { 4498 assert(hole_from < hole_to, "check"); 4499 assert(from() <= hole_from && hole_to <= to(), "index out of interval"); 4500 4501 Range* cur = _first; 4502 while (cur != Range::end()) { 4503 assert(cur->to() < cur->next()->from(), "no space between ranges"); 4504 4505 // hole-range starts before this range -> hole 4506 if (hole_from < cur->from()) { 4507 return true; 4508 4509 // hole-range completely inside this range -> no hole 4510 } else if (hole_to <= cur->to()) { 4511 return false; 4512 4513 // overlapping of hole-range with this range -> hole 4514 } else if (hole_from <= cur->to()) { 4515 return true; 4516 } 4517 4518 cur = cur->next(); 4519 } 4520 4521 return false; 4522 } 4523 4524 4525 #ifndef PRODUCT 4526 void Interval::print(outputStream* out) const { 4527 const char* SpillState2Name[] = { "no definition", "no spill store", "one spill store", "store at definition", "start in memory", "no optimization" }; 4528 const char* UseKind2Name[] = { "N", "L", "S", "M" }; 4529 4530 const char* type_name; 4531 LIR_Opr opr = LIR_OprFact::illegal(); 4532 if (reg_num() < LIR_OprDesc::vreg_base) { 4533 type_name = "fixed"; 4534 // need a temporary operand for fixed intervals because type() cannot be called 4535 if (assigned_reg() >= pd_first_cpu_reg && assigned_reg() <= pd_last_cpu_reg) { 4536 opr = LIR_OprFact::single_cpu(assigned_reg()); 4537 } else if (assigned_reg() >= pd_first_fpu_reg && assigned_reg() <= pd_last_fpu_reg) { 4538 opr = LIR_OprFact::single_fpu(assigned_reg() - pd_first_fpu_reg); 4539 #ifdef X86 4540 } else if (assigned_reg() >= pd_first_xmm_reg && assigned_reg() <= pd_last_xmm_reg) { 4541 opr = LIR_OprFact::single_xmm(assigned_reg() - pd_first_xmm_reg); 4542 #endif 4543 } else { 4544 ShouldNotReachHere(); 4545 } 4546 } else { 4547 type_name = type2name(type()); 4548 if (assigned_reg() != -1 && 4549 (LinearScan::num_physical_regs(type()) == 1 || assigned_regHi() != -1)) { 4550 opr = LinearScan::calc_operand_for_interval(this); 4551 } 4552 } 4553 4554 out->print("%d %s ", reg_num(), type_name); 4555 if (opr->is_valid()) { 4556 out->print("\""); 4557 opr->print(out); 4558 out->print("\" "); 4559 } 4560 out->print("%d %d ", split_parent()->reg_num(), (register_hint(false) != NULL ? register_hint(false)->reg_num() : -1)); 4561 4562 // print ranges 4563 Range* cur = _first; 4564 while (cur != Range::end()) { 4565 cur->print(out); 4566 cur = cur->next(); 4567 assert(cur != NULL, "range list not closed with range sentinel"); 4568 } 4569 4570 // print use positions 4571 int prev = 0; 4572 assert(_use_pos_and_kinds.length() % 2 == 0, "must be"); 4573 for (int i =_use_pos_and_kinds.length() - 2; i >= 0; i -= 2) { 4574 assert(_use_pos_and_kinds.at(i + 1) >= firstValidKind && _use_pos_and_kinds.at(i + 1) <= lastValidKind, "invalid use kind"); 4575 assert(prev < _use_pos_and_kinds.at(i), "use positions not sorted"); 4576 4577 out->print("%d %s ", _use_pos_and_kinds.at(i), UseKind2Name[_use_pos_and_kinds.at(i + 1)]); 4578 prev = _use_pos_and_kinds.at(i); 4579 } 4580 4581 out->print(" \"%s\"", SpillState2Name[spill_state()]); 4582 out->cr(); 4583 } 4584 #endif 4585 4586 4587 4588 // **** Implementation of IntervalWalker **************************** 4589 4590 IntervalWalker::IntervalWalker(LinearScan* allocator, Interval* unhandled_fixed_first, Interval* unhandled_any_first) 4591 : _compilation(allocator->compilation()) 4592 , _allocator(allocator) 4593 { 4594 _unhandled_first[fixedKind] = unhandled_fixed_first; 4595 _unhandled_first[anyKind] = unhandled_any_first; 4596 _active_first[fixedKind] = Interval::end(); 4597 _inactive_first[fixedKind] = Interval::end(); 4598 _active_first[anyKind] = Interval::end(); 4599 _inactive_first[anyKind] = Interval::end(); 4600 _current_position = -1; 4601 _current = NULL; 4602 next_interval(); 4603 } 4604 4605 4606 // append interval at top of list 4607 void IntervalWalker::append_unsorted(Interval** list, Interval* interval) { 4608 interval->set_next(*list); *list = interval; 4609 } 4610 4611 4612 // append interval in order of current range from() 4613 void IntervalWalker::append_sorted(Interval** list, Interval* interval) { 4614 Interval* prev = NULL; 4615 Interval* cur = *list; 4616 while (cur->current_from() < interval->current_from()) { 4617 prev = cur; cur = cur->next(); 4618 } 4619 if (prev == NULL) { 4620 *list = interval; 4621 } else { 4622 prev->set_next(interval); 4623 } 4624 interval->set_next(cur); 4625 } 4626 4627 void IntervalWalker::append_to_unhandled(Interval** list, Interval* interval) { 4628 assert(interval->from() >= current()->current_from(), "cannot append new interval before current walk position"); 4629 4630 Interval* prev = NULL; 4631 Interval* cur = *list; 4632 while (cur->from() < interval->from() || (cur->from() == interval->from() && cur->first_usage(noUse) < interval->first_usage(noUse))) { 4633 prev = cur; cur = cur->next(); 4634 } 4635 if (prev == NULL) { 4636 *list = interval; 4637 } else { 4638 prev->set_next(interval); 4639 } 4640 interval->set_next(cur); 4641 } 4642 4643 4644 inline bool IntervalWalker::remove_from_list(Interval** list, Interval* i) { 4645 while (*list != Interval::end() && *list != i) { 4646 list = (*list)->next_addr(); 4647 } 4648 if (*list != Interval::end()) { 4649 assert(*list == i, "check"); 4650 *list = (*list)->next(); 4651 return true; 4652 } else { 4653 return false; 4654 } 4655 } 4656 4657 void IntervalWalker::remove_from_list(Interval* i) { 4658 bool deleted; 4659 4660 if (i->state() == activeState) { 4661 deleted = remove_from_list(active_first_addr(anyKind), i); 4662 } else { 4663 assert(i->state() == inactiveState, "invalid state"); 4664 deleted = remove_from_list(inactive_first_addr(anyKind), i); 4665 } 4666 4667 assert(deleted, "interval has not been found in list"); 4668 } 4669 4670 4671 void IntervalWalker::walk_to(IntervalState state, int from) { 4672 assert (state == activeState || state == inactiveState, "wrong state"); 4673 for_each_interval_kind(kind) { 4674 Interval** prev = state == activeState ? active_first_addr(kind) : inactive_first_addr(kind); 4675 Interval* next = *prev; 4676 while (next->current_from() <= from) { 4677 Interval* cur = next; 4678 next = cur->next(); 4679 4680 bool range_has_changed = false; 4681 while (cur->current_to() <= from) { 4682 cur->next_range(); 4683 range_has_changed = true; 4684 } 4685 4686 // also handle move from inactive list to active list 4687 range_has_changed = range_has_changed || (state == inactiveState && cur->current_from() <= from); 4688 4689 if (range_has_changed) { 4690 // remove cur from list 4691 *prev = next; 4692 if (cur->current_at_end()) { 4693 // move to handled state (not maintained as a list) 4694 cur->set_state(handledState); 4695 interval_moved(cur, kind, state, handledState); 4696 } else if (cur->current_from() <= from){ 4697 // sort into active list 4698 append_sorted(active_first_addr(kind), cur); 4699 cur->set_state(activeState); 4700 if (*prev == cur) { 4701 assert(state == activeState, "check"); 4702 prev = cur->next_addr(); 4703 } 4704 interval_moved(cur, kind, state, activeState); 4705 } else { 4706 // sort into inactive list 4707 append_sorted(inactive_first_addr(kind), cur); 4708 cur->set_state(inactiveState); 4709 if (*prev == cur) { 4710 assert(state == inactiveState, "check"); 4711 prev = cur->next_addr(); 4712 } 4713 interval_moved(cur, kind, state, inactiveState); 4714 } 4715 } else { 4716 prev = cur->next_addr(); 4717 continue; 4718 } 4719 } 4720 } 4721 } 4722 4723 4724 void IntervalWalker::next_interval() { 4725 IntervalKind kind; 4726 Interval* any = _unhandled_first[anyKind]; 4727 Interval* fixed = _unhandled_first[fixedKind]; 4728 4729 if (any != Interval::end()) { 4730 // intervals may start at same position -> prefer fixed interval 4731 kind = fixed != Interval::end() && fixed->from() <= any->from() ? fixedKind : anyKind; 4732 4733 assert (kind == fixedKind && fixed->from() <= any->from() || 4734 kind == anyKind && any->from() <= fixed->from(), "wrong interval!!!"); 4735 assert(any == Interval::end() || fixed == Interval::end() || any->from() != fixed->from() || kind == fixedKind, "if fixed and any-Interval start at same position, fixed must be processed first"); 4736 4737 } else if (fixed != Interval::end()) { 4738 kind = fixedKind; 4739 } else { 4740 _current = NULL; return; 4741 } 4742 _current_kind = kind; 4743 _current = _unhandled_first[kind]; 4744 _unhandled_first[kind] = _current->next(); 4745 _current->set_next(Interval::end()); 4746 _current->rewind_range(); 4747 } 4748 4749 4750 void IntervalWalker::walk_to(int lir_op_id) { 4751 assert(_current_position <= lir_op_id, "can not walk backwards"); 4752 while (current() != NULL) { 4753 bool is_active = current()->from() <= lir_op_id; 4754 int id = is_active ? current()->from() : lir_op_id; 4755 4756 TRACE_LINEAR_SCAN(2, if (_current_position < id) { tty->cr(); tty->print_cr("walk_to(%d) **************************************************************", id); }) 4757 4758 // set _current_position prior to call of walk_to 4759 _current_position = id; 4760 4761 // call walk_to even if _current_position == id 4762 walk_to(activeState, id); 4763 walk_to(inactiveState, id); 4764 4765 if (is_active) { 4766 current()->set_state(activeState); 4767 if (activate_current()) { 4768 append_sorted(active_first_addr(current_kind()), current()); 4769 interval_moved(current(), current_kind(), unhandledState, activeState); 4770 } 4771 4772 next_interval(); 4773 } else { 4774 return; 4775 } 4776 } 4777 } 4778 4779 void IntervalWalker::interval_moved(Interval* interval, IntervalKind kind, IntervalState from, IntervalState to) { 4780 #ifndef PRODUCT 4781 if (TraceLinearScanLevel >= 4) { 4782 #define print_state(state) \ 4783 switch(state) {\ 4784 case unhandledState: tty->print("unhandled"); break;\ 4785 case activeState: tty->print("active"); break;\ 4786 case inactiveState: tty->print("inactive"); break;\ 4787 case handledState: tty->print("handled"); break;\ 4788 default: ShouldNotReachHere(); \ 4789 } 4790 4791 print_state(from); tty->print(" to "); print_state(to); 4792 tty->fill_to(23); 4793 interval->print(); 4794 4795 #undef print_state 4796 } 4797 #endif 4798 } 4799 4800 4801 4802 // **** Implementation of LinearScanWalker ************************** 4803 4804 LinearScanWalker::LinearScanWalker(LinearScan* allocator, Interval* unhandled_fixed_first, Interval* unhandled_any_first) 4805 : IntervalWalker(allocator, unhandled_fixed_first, unhandled_any_first) 4806 , _move_resolver(allocator) 4807 { 4808 for (int i = 0; i < LinearScan::nof_regs; i++) { 4809 _spill_intervals[i] = new IntervalList(2); 4810 } 4811 } 4812 4813 4814 inline void LinearScanWalker::init_use_lists(bool only_process_use_pos) { 4815 for (int i = _first_reg; i <= _last_reg; i++) { 4816 _use_pos[i] = max_jint; 4817 4818 if (!only_process_use_pos) { 4819 _block_pos[i] = max_jint; 4820 _spill_intervals[i]->clear(); 4821 } 4822 } 4823 } 4824 4825 inline void LinearScanWalker::exclude_from_use(int reg) { 4826 assert(reg < LinearScan::nof_regs, "interval must have a register assigned (stack slots not allowed)"); 4827 if (reg >= _first_reg && reg <= _last_reg) { 4828 _use_pos[reg] = 0; 4829 } 4830 } 4831 inline void LinearScanWalker::exclude_from_use(Interval* i) { 4832 assert(i->assigned_reg() != any_reg, "interval has no register assigned"); 4833 4834 exclude_from_use(i->assigned_reg()); 4835 exclude_from_use(i->assigned_regHi()); 4836 } 4837 4838 inline void LinearScanWalker::set_use_pos(int reg, Interval* i, int use_pos, bool only_process_use_pos) { 4839 assert(use_pos != 0, "must use exclude_from_use to set use_pos to 0"); 4840 4841 if (reg >= _first_reg && reg <= _last_reg) { 4842 if (_use_pos[reg] > use_pos) { 4843 _use_pos[reg] = use_pos; 4844 } 4845 if (!only_process_use_pos) { 4846 _spill_intervals[reg]->append(i); 4847 } 4848 } 4849 } 4850 inline void LinearScanWalker::set_use_pos(Interval* i, int use_pos, bool only_process_use_pos) { 4851 assert(i->assigned_reg() != any_reg, "interval has no register assigned"); 4852 if (use_pos != -1) { 4853 set_use_pos(i->assigned_reg(), i, use_pos, only_process_use_pos); 4854 set_use_pos(i->assigned_regHi(), i, use_pos, only_process_use_pos); 4855 } 4856 } 4857 4858 inline void LinearScanWalker::set_block_pos(int reg, Interval* i, int block_pos) { 4859 if (reg >= _first_reg && reg <= _last_reg) { 4860 if (_block_pos[reg] > block_pos) { 4861 _block_pos[reg] = block_pos; 4862 } 4863 if (_use_pos[reg] > block_pos) { 4864 _use_pos[reg] = block_pos; 4865 } 4866 } 4867 } 4868 inline void LinearScanWalker::set_block_pos(Interval* i, int block_pos) { 4869 assert(i->assigned_reg() != any_reg, "interval has no register assigned"); 4870 if (block_pos != -1) { 4871 set_block_pos(i->assigned_reg(), i, block_pos); 4872 set_block_pos(i->assigned_regHi(), i, block_pos); 4873 } 4874 } 4875 4876 4877 void LinearScanWalker::free_exclude_active_fixed() { 4878 Interval* list = active_first(fixedKind); 4879 while (list != Interval::end()) { 4880 assert(list->assigned_reg() < LinearScan::nof_regs, "active interval must have a register assigned"); 4881 exclude_from_use(list); 4882 list = list->next(); 4883 } 4884 } 4885 4886 void LinearScanWalker::free_exclude_active_any() { 4887 Interval* list = active_first(anyKind); 4888 while (list != Interval::end()) { 4889 exclude_from_use(list); 4890 list = list->next(); 4891 } 4892 } 4893 4894 void LinearScanWalker::free_collect_inactive_fixed(Interval* cur) { 4895 Interval* list = inactive_first(fixedKind); 4896 while (list != Interval::end()) { 4897 if (cur->to() <= list->current_from()) { 4898 assert(list->current_intersects_at(cur) == -1, "must not intersect"); 4899 set_use_pos(list, list->current_from(), true); 4900 } else { 4901 set_use_pos(list, list->current_intersects_at(cur), true); 4902 } 4903 list = list->next(); 4904 } 4905 } 4906 4907 void LinearScanWalker::free_collect_inactive_any(Interval* cur) { 4908 Interval* list = inactive_first(anyKind); 4909 while (list != Interval::end()) { 4910 set_use_pos(list, list->current_intersects_at(cur), true); 4911 list = list->next(); 4912 } 4913 } 4914 4915 void LinearScanWalker::free_collect_unhandled(IntervalKind kind, Interval* cur) { 4916 Interval* list = unhandled_first(kind); 4917 while (list != Interval::end()) { 4918 set_use_pos(list, list->intersects_at(cur), true); 4919 if (kind == fixedKind && cur->to() <= list->from()) { 4920 set_use_pos(list, list->from(), true); 4921 } 4922 list = list->next(); 4923 } 4924 } 4925 4926 void LinearScanWalker::spill_exclude_active_fixed() { 4927 Interval* list = active_first(fixedKind); 4928 while (list != Interval::end()) { 4929 exclude_from_use(list); 4930 list = list->next(); 4931 } 4932 } 4933 4934 void LinearScanWalker::spill_block_unhandled_fixed(Interval* cur) { 4935 Interval* list = unhandled_first(fixedKind); 4936 while (list != Interval::end()) { 4937 set_block_pos(list, list->intersects_at(cur)); 4938 list = list->next(); 4939 } 4940 } 4941 4942 void LinearScanWalker::spill_block_inactive_fixed(Interval* cur) { 4943 Interval* list = inactive_first(fixedKind); 4944 while (list != Interval::end()) { 4945 if (cur->to() > list->current_from()) { 4946 set_block_pos(list, list->current_intersects_at(cur)); 4947 } else { 4948 assert(list->current_intersects_at(cur) == -1, "invalid optimization: intervals intersect"); 4949 } 4950 4951 list = list->next(); 4952 } 4953 } 4954 4955 void LinearScanWalker::spill_collect_active_any() { 4956 Interval* list = active_first(anyKind); 4957 while (list != Interval::end()) { 4958 set_use_pos(list, MIN2(list->next_usage(loopEndMarker, _current_position), list->to()), false); 4959 list = list->next(); 4960 } 4961 } 4962 4963 void LinearScanWalker::spill_collect_inactive_any(Interval* cur) { 4964 Interval* list = inactive_first(anyKind); 4965 while (list != Interval::end()) { 4966 if (list->current_intersects(cur)) { 4967 set_use_pos(list, MIN2(list->next_usage(loopEndMarker, _current_position), list->to()), false); 4968 } 4969 list = list->next(); 4970 } 4971 } 4972 4973 4974 void LinearScanWalker::insert_move(int op_id, Interval* src_it, Interval* dst_it) { 4975 // output all moves here. When source and target are equal, the move is 4976 // optimized away later in assign_reg_nums 4977 4978 op_id = (op_id + 1) & ~1; 4979 BlockBegin* op_block = allocator()->block_of_op_with_id(op_id); 4980 assert(op_id > 0 && allocator()->block_of_op_with_id(op_id - 2) == op_block, "cannot insert move at block boundary"); 4981 4982 // calculate index of instruction inside instruction list of current block 4983 // the minimal index (for a block with no spill moves) can be calculated because the 4984 // numbering of instructions is known. 4985 // When the block already contains spill moves, the index must be increased until the 4986 // correct index is reached. 4987 LIR_OpList* list = op_block->lir()->instructions_list(); 4988 int index = (op_id - list->at(0)->id()) / 2; 4989 assert(list->at(index)->id() <= op_id, "error in calculation"); 4990 4991 while (list->at(index)->id() != op_id) { 4992 index++; 4993 assert(0 <= index && index < list->length(), "index out of bounds"); 4994 } 4995 assert(1 <= index && index < list->length(), "index out of bounds"); 4996 assert(list->at(index)->id() == op_id, "error in calculation"); 4997 4998 // insert new instruction before instruction at position index 4999 _move_resolver.move_insert_position(op_block->lir(), index - 1); 5000 _move_resolver.add_mapping(src_it, dst_it); 5001 } 5002 5003 5004 int LinearScanWalker::find_optimal_split_pos(BlockBegin* min_block, BlockBegin* max_block, int max_split_pos) { 5005 int from_block_nr = min_block->linear_scan_number(); 5006 int to_block_nr = max_block->linear_scan_number(); 5007 5008 assert(0 <= from_block_nr && from_block_nr < block_count(), "out of range"); 5009 assert(0 <= to_block_nr && to_block_nr < block_count(), "out of range"); 5010 assert(from_block_nr < to_block_nr, "must cross block boundary"); 5011 5012 // Try to split at end of max_block. If this would be after 5013 // max_split_pos, then use the begin of max_block 5014 int optimal_split_pos = max_block->last_lir_instruction_id() + 2; 5015 if (optimal_split_pos > max_split_pos) { 5016 optimal_split_pos = max_block->first_lir_instruction_id(); 5017 } 5018 5019 int min_loop_depth = max_block->loop_depth(); 5020 for (int i = to_block_nr - 1; i >= from_block_nr; i--) { 5021 BlockBegin* cur = block_at(i); 5022 5023 if (cur->loop_depth() < min_loop_depth) { 5024 // block with lower loop-depth found -> split at the end of this block 5025 min_loop_depth = cur->loop_depth(); 5026 optimal_split_pos = cur->last_lir_instruction_id() + 2; 5027 } 5028 } 5029 assert(optimal_split_pos > allocator()->max_lir_op_id() || allocator()->is_block_begin(optimal_split_pos), "algorithm must move split pos to block boundary"); 5030 5031 return optimal_split_pos; 5032 } 5033 5034 5035 int LinearScanWalker::find_optimal_split_pos(Interval* it, int min_split_pos, int max_split_pos, bool do_loop_optimization) { 5036 int optimal_split_pos = -1; 5037 if (min_split_pos == max_split_pos) { 5038 // trivial case, no optimization of split position possible 5039 TRACE_LINEAR_SCAN(4, tty->print_cr(" min-pos and max-pos are equal, no optimization possible")); 5040 optimal_split_pos = min_split_pos; 5041 5042 } else { 5043 assert(min_split_pos < max_split_pos, "must be true then"); 5044 assert(min_split_pos > 0, "cannot access min_split_pos - 1 otherwise"); 5045 5046 // reason for using min_split_pos - 1: when the minimal split pos is exactly at the 5047 // beginning of a block, then min_split_pos is also a possible split position. 5048 // Use the block before as min_block, because then min_block->last_lir_instruction_id() + 2 == min_split_pos 5049 BlockBegin* min_block = allocator()->block_of_op_with_id(min_split_pos - 1); 5050 5051 // reason for using max_split_pos - 1: otherwise there would be an assertion failure 5052 // when an interval ends at the end of the last block of the method 5053 // (in this case, max_split_pos == allocator()->max_lir_op_id() + 2, and there is no 5054 // block at this op_id) 5055 BlockBegin* max_block = allocator()->block_of_op_with_id(max_split_pos - 1); 5056 5057 assert(min_block->linear_scan_number() <= max_block->linear_scan_number(), "invalid order"); 5058 if (min_block == max_block) { 5059 // split position cannot be moved to block boundary, so split as late as possible 5060 TRACE_LINEAR_SCAN(4, tty->print_cr(" cannot move split pos to block boundary because min_pos and max_pos are in same block")); 5061 optimal_split_pos = max_split_pos; 5062 5063 } else if (it->has_hole_between(max_split_pos - 1, max_split_pos) && !allocator()->is_block_begin(max_split_pos)) { 5064 // Do not move split position if the interval has a hole before max_split_pos. 5065 // Intervals resulting from Phi-Functions have more than one definition (marked 5066 // as mustHaveRegister) with a hole before each definition. When the register is needed 5067 // for the second definition, an earlier reloading is unnecessary. 5068 TRACE_LINEAR_SCAN(4, tty->print_cr(" interval has hole just before max_split_pos, so splitting at max_split_pos")); 5069 optimal_split_pos = max_split_pos; 5070 5071 } else { 5072 // seach optimal block boundary between min_split_pos and max_split_pos 5073 TRACE_LINEAR_SCAN(4, tty->print_cr(" moving split pos to optimal block boundary between block B%d and B%d", min_block->block_id(), max_block->block_id())); 5074 5075 if (do_loop_optimization) { 5076 // Loop optimization: if a loop-end marker is found between min- and max-position, 5077 // then split before this loop 5078 int loop_end_pos = it->next_usage_exact(loopEndMarker, min_block->last_lir_instruction_id() + 2); 5079 TRACE_LINEAR_SCAN(4, tty->print_cr(" loop optimization: loop end found at pos %d", loop_end_pos)); 5080 5081 assert(loop_end_pos > min_split_pos, "invalid order"); 5082 if (loop_end_pos < max_split_pos) { 5083 // loop-end marker found between min- and max-position 5084 // if it is not the end marker for the same loop as the min-position, then move 5085 // the max-position to this loop block. 5086 // Desired result: uses tagged as shouldHaveRegister inside a loop cause a reloading 5087 // of the interval (normally, only mustHaveRegister causes a reloading) 5088 BlockBegin* loop_block = allocator()->block_of_op_with_id(loop_end_pos); 5089 5090 TRACE_LINEAR_SCAN(4, tty->print_cr(" interval is used in loop that ends in block B%d, so trying to move max_block back from B%d to B%d", loop_block->block_id(), max_block->block_id(), loop_block->block_id())); 5091 assert(loop_block != min_block, "loop_block and min_block must be different because block boundary is needed between"); 5092 5093 optimal_split_pos = find_optimal_split_pos(min_block, loop_block, loop_block->last_lir_instruction_id() + 2); 5094 if (optimal_split_pos == loop_block->last_lir_instruction_id() + 2) { 5095 optimal_split_pos = -1; 5096 TRACE_LINEAR_SCAN(4, tty->print_cr(" loop optimization not necessary")); 5097 } else { 5098 TRACE_LINEAR_SCAN(4, tty->print_cr(" loop optimization successful")); 5099 } 5100 } 5101 } 5102 5103 if (optimal_split_pos == -1) { 5104 // not calculated by loop optimization 5105 optimal_split_pos = find_optimal_split_pos(min_block, max_block, max_split_pos); 5106 } 5107 } 5108 } 5109 TRACE_LINEAR_SCAN(4, tty->print_cr(" optimal split position: %d", optimal_split_pos)); 5110 5111 return optimal_split_pos; 5112 } 5113 5114 5115 /* 5116 split an interval at the optimal position between min_split_pos and 5117 max_split_pos in two parts: 5118 1) the left part has already a location assigned 5119 2) the right part is sorted into to the unhandled-list 5120 */ 5121 void LinearScanWalker::split_before_usage(Interval* it, int min_split_pos, int max_split_pos) { 5122 TRACE_LINEAR_SCAN(2, tty->print ("----- splitting interval: "); it->print()); 5123 TRACE_LINEAR_SCAN(2, tty->print_cr(" between %d and %d", min_split_pos, max_split_pos)); 5124 5125 assert(it->from() < min_split_pos, "cannot split at start of interval"); 5126 assert(current_position() < min_split_pos, "cannot split before current position"); 5127 assert(min_split_pos <= max_split_pos, "invalid order"); 5128 assert(max_split_pos <= it->to(), "cannot split after end of interval"); 5129 5130 int optimal_split_pos = find_optimal_split_pos(it, min_split_pos, max_split_pos, true); 5131 5132 assert(min_split_pos <= optimal_split_pos && optimal_split_pos <= max_split_pos, "out of range"); 5133 assert(optimal_split_pos <= it->to(), "cannot split after end of interval"); 5134 assert(optimal_split_pos > it->from(), "cannot split at start of interval"); 5135 5136 if (optimal_split_pos == it->to() && it->next_usage(mustHaveRegister, min_split_pos) == max_jint) { 5137 // the split position would be just before the end of the interval 5138 // -> no split at all necessary 5139 TRACE_LINEAR_SCAN(4, tty->print_cr(" no split necessary because optimal split position is at end of interval")); 5140 return; 5141 } 5142 5143 // must calculate this before the actual split is performed and before split position is moved to odd op_id 5144 bool move_necessary = !allocator()->is_block_begin(optimal_split_pos) && !it->has_hole_between(optimal_split_pos - 1, optimal_split_pos); 5145 5146 if (!allocator()->is_block_begin(optimal_split_pos)) { 5147 // move position before actual instruction (odd op_id) 5148 optimal_split_pos = (optimal_split_pos - 1) | 1; 5149 } 5150 5151 TRACE_LINEAR_SCAN(4, tty->print_cr(" splitting at position %d", optimal_split_pos)); 5152 assert(allocator()->is_block_begin(optimal_split_pos) || (optimal_split_pos % 2 == 1), "split pos must be odd when not on block boundary"); 5153 assert(!allocator()->is_block_begin(optimal_split_pos) || (optimal_split_pos % 2 == 0), "split pos must be even on block boundary"); 5154 5155 Interval* split_part = it->split(optimal_split_pos); 5156 5157 allocator()->append_interval(split_part); 5158 allocator()->copy_register_flags(it, split_part); 5159 split_part->set_insert_move_when_activated(move_necessary); 5160 append_to_unhandled(unhandled_first_addr(anyKind), split_part); 5161 5162 TRACE_LINEAR_SCAN(2, tty->print_cr(" split interval in two parts (insert_move_when_activated: %d)", move_necessary)); 5163 TRACE_LINEAR_SCAN(2, tty->print (" "); it->print()); 5164 TRACE_LINEAR_SCAN(2, tty->print (" "); split_part->print()); 5165 } 5166 5167 /* 5168 split an interval at the optimal position between min_split_pos and 5169 max_split_pos in two parts: 5170 1) the left part has already a location assigned 5171 2) the right part is always on the stack and therefore ignored in further processing 5172 */ 5173 void LinearScanWalker::split_for_spilling(Interval* it) { 5174 // calculate allowed range of splitting position 5175 int max_split_pos = current_position(); 5176 int min_split_pos = MAX2(it->previous_usage(shouldHaveRegister, max_split_pos) + 1, it->from()); 5177 5178 TRACE_LINEAR_SCAN(2, tty->print ("----- splitting and spilling interval: "); it->print()); 5179 TRACE_LINEAR_SCAN(2, tty->print_cr(" between %d and %d", min_split_pos, max_split_pos)); 5180 5181 assert(it->state() == activeState, "why spill interval that is not active?"); 5182 assert(it->from() <= min_split_pos, "cannot split before start of interval"); 5183 assert(min_split_pos <= max_split_pos, "invalid order"); 5184 assert(max_split_pos < it->to(), "cannot split at end end of interval"); 5185 assert(current_position() < it->to(), "interval must not end before current position"); 5186 5187 if (min_split_pos == it->from()) { 5188 // the whole interval is never used, so spill it entirely to memory 5189 TRACE_LINEAR_SCAN(2, tty->print_cr(" spilling entire interval because split pos is at beginning of interval")); 5190 assert(it->first_usage(shouldHaveRegister) > current_position(), "interval must not have use position before current_position"); 5191 5192 allocator()->assign_spill_slot(it); 5193 allocator()->change_spill_state(it, min_split_pos); 5194 5195 // Also kick parent intervals out of register to memory when they have no use 5196 // position. This avoids short interval in register surrounded by intervals in 5197 // memory -> avoid useless moves from memory to register and back 5198 Interval* parent = it; 5199 while (parent != NULL && parent->is_split_child()) { 5200 parent = parent->split_child_before_op_id(parent->from()); 5201 5202 if (parent->assigned_reg() < LinearScan::nof_regs) { 5203 if (parent->first_usage(shouldHaveRegister) == max_jint) { 5204 // parent is never used, so kick it out of its assigned register 5205 TRACE_LINEAR_SCAN(4, tty->print_cr(" kicking out interval %d out of its register because it is never used", parent->reg_num())); 5206 allocator()->assign_spill_slot(parent); 5207 } else { 5208 // do not go further back because the register is actually used by the interval 5209 parent = NULL; 5210 } 5211 } 5212 } 5213 5214 } else { 5215 // search optimal split pos, split interval and spill only the right hand part 5216 int optimal_split_pos = find_optimal_split_pos(it, min_split_pos, max_split_pos, false); 5217 5218 assert(min_split_pos <= optimal_split_pos && optimal_split_pos <= max_split_pos, "out of range"); 5219 assert(optimal_split_pos < it->to(), "cannot split at end of interval"); 5220 assert(optimal_split_pos >= it->from(), "cannot split before start of interval"); 5221 5222 if (!allocator()->is_block_begin(optimal_split_pos)) { 5223 // move position before actual instruction (odd op_id) 5224 optimal_split_pos = (optimal_split_pos - 1) | 1; 5225 } 5226 5227 TRACE_LINEAR_SCAN(4, tty->print_cr(" splitting at position %d", optimal_split_pos)); 5228 assert(allocator()->is_block_begin(optimal_split_pos) || (optimal_split_pos % 2 == 1), "split pos must be odd when not on block boundary"); 5229 assert(!allocator()->is_block_begin(optimal_split_pos) || (optimal_split_pos % 2 == 0), "split pos must be even on block boundary"); 5230 5231 Interval* spilled_part = it->split(optimal_split_pos); 5232 allocator()->append_interval(spilled_part); 5233 allocator()->assign_spill_slot(spilled_part); 5234 allocator()->change_spill_state(spilled_part, optimal_split_pos); 5235 5236 if (!allocator()->is_block_begin(optimal_split_pos)) { 5237 TRACE_LINEAR_SCAN(4, tty->print_cr(" inserting move from interval %d to %d", it->reg_num(), spilled_part->reg_num())); 5238 insert_move(optimal_split_pos, it, spilled_part); 5239 } 5240 5241 // the current_split_child is needed later when moves are inserted for reloading 5242 assert(spilled_part->current_split_child() == it, "overwriting wrong current_split_child"); 5243 spilled_part->make_current_split_child(); 5244 5245 TRACE_LINEAR_SCAN(2, tty->print_cr(" split interval in two parts")); 5246 TRACE_LINEAR_SCAN(2, tty->print (" "); it->print()); 5247 TRACE_LINEAR_SCAN(2, tty->print (" "); spilled_part->print()); 5248 } 5249 } 5250 5251 5252 void LinearScanWalker::split_stack_interval(Interval* it) { 5253 int min_split_pos = current_position() + 1; 5254 int max_split_pos = MIN2(it->first_usage(shouldHaveRegister), it->to()); 5255 5256 split_before_usage(it, min_split_pos, max_split_pos); 5257 } 5258 5259 void LinearScanWalker::split_when_partial_register_available(Interval* it, int register_available_until) { 5260 int min_split_pos = MAX2(it->previous_usage(shouldHaveRegister, register_available_until), it->from() + 1); 5261 int max_split_pos = register_available_until; 5262 5263 split_before_usage(it, min_split_pos, max_split_pos); 5264 } 5265 5266 void LinearScanWalker::split_and_spill_interval(Interval* it) { 5267 assert(it->state() == activeState || it->state() == inactiveState, "other states not allowed"); 5268 5269 int current_pos = current_position(); 5270 if (it->state() == inactiveState) { 5271 // the interval is currently inactive, so no spill slot is needed for now. 5272 // when the split part is activated, the interval has a new chance to get a register, 5273 // so in the best case no stack slot is necessary 5274 assert(it->has_hole_between(current_pos - 1, current_pos + 1), "interval can not be inactive otherwise"); 5275 split_before_usage(it, current_pos + 1, current_pos + 1); 5276 5277 } else { 5278 // search the position where the interval must have a register and split 5279 // at the optimal position before. 5280 // The new created part is added to the unhandled list and will get a register 5281 // when it is activated 5282 int min_split_pos = current_pos + 1; 5283 int max_split_pos = MIN2(it->next_usage(mustHaveRegister, min_split_pos), it->to()); 5284 5285 split_before_usage(it, min_split_pos, max_split_pos); 5286 5287 assert(it->next_usage(mustHaveRegister, current_pos) == max_jint, "the remaining part is spilled to stack and therefore has no register"); 5288 split_for_spilling(it); 5289 } 5290 } 5291 5292 5293 int LinearScanWalker::find_free_reg(int reg_needed_until, int interval_to, int hint_reg, int ignore_reg, bool* need_split) { 5294 int min_full_reg = any_reg; 5295 int max_partial_reg = any_reg; 5296 5297 for (int i = _first_reg; i <= _last_reg; i++) { 5298 if (i == ignore_reg) { 5299 // this register must be ignored 5300 5301 } else if (_use_pos[i] >= interval_to) { 5302 // this register is free for the full interval 5303 if (min_full_reg == any_reg || i == hint_reg || (_use_pos[i] < _use_pos[min_full_reg] && min_full_reg != hint_reg)) { 5304 min_full_reg = i; 5305 } 5306 } else if (_use_pos[i] > reg_needed_until) { 5307 // this register is at least free until reg_needed_until 5308 if (max_partial_reg == any_reg || i == hint_reg || (_use_pos[i] > _use_pos[max_partial_reg] && max_partial_reg != hint_reg)) { 5309 max_partial_reg = i; 5310 } 5311 } 5312 } 5313 5314 if (min_full_reg != any_reg) { 5315 return min_full_reg; 5316 } else if (max_partial_reg != any_reg) { 5317 *need_split = true; 5318 return max_partial_reg; 5319 } else { 5320 return any_reg; 5321 } 5322 } 5323 5324 int LinearScanWalker::find_free_double_reg(int reg_needed_until, int interval_to, int hint_reg, bool* need_split) { 5325 assert((_last_reg - _first_reg + 1) % 2 == 0, "adjust algorithm"); 5326 5327 int min_full_reg = any_reg; 5328 int max_partial_reg = any_reg; 5329 5330 for (int i = _first_reg; i < _last_reg; i+=2) { 5331 if (_use_pos[i] >= interval_to && _use_pos[i + 1] >= interval_to) { 5332 // this register is free for the full interval 5333 if (min_full_reg == any_reg || i == hint_reg || (_use_pos[i] < _use_pos[min_full_reg] && min_full_reg != hint_reg)) { 5334 min_full_reg = i; 5335 } 5336 } else if (_use_pos[i] > reg_needed_until && _use_pos[i + 1] > reg_needed_until) { 5337 // this register is at least free until reg_needed_until 5338 if (max_partial_reg == any_reg || i == hint_reg || (_use_pos[i] > _use_pos[max_partial_reg] && max_partial_reg != hint_reg)) { 5339 max_partial_reg = i; 5340 } 5341 } 5342 } 5343 5344 if (min_full_reg != any_reg) { 5345 return min_full_reg; 5346 } else if (max_partial_reg != any_reg) { 5347 *need_split = true; 5348 return max_partial_reg; 5349 } else { 5350 return any_reg; 5351 } 5352 } 5353 5354 5355 bool LinearScanWalker::alloc_free_reg(Interval* cur) { 5356 TRACE_LINEAR_SCAN(2, tty->print("trying to find free register for "); cur->print()); 5357 5358 init_use_lists(true); 5359 free_exclude_active_fixed(); 5360 free_exclude_active_any(); 5361 free_collect_inactive_fixed(cur); 5362 free_collect_inactive_any(cur); 5363 // free_collect_unhandled(fixedKind, cur); 5364 assert(unhandled_first(fixedKind) == Interval::end(), "must not have unhandled fixed intervals because all fixed intervals have a use at position 0"); 5365 5366 // _use_pos contains the start of the next interval that has this register assigned 5367 // (either as a fixed register or a normal allocated register in the past) 5368 // only intervals overlapping with cur are processed, non-overlapping invervals can be ignored safely 5369 TRACE_LINEAR_SCAN(4, tty->print_cr(" state of registers:")); 5370 TRACE_LINEAR_SCAN(4, for (int i = _first_reg; i <= _last_reg; i++) tty->print_cr(" reg %d: use_pos: %d", i, _use_pos[i])); 5371 5372 int hint_reg, hint_regHi; 5373 Interval* register_hint = cur->register_hint(); 5374 if (register_hint != NULL) { 5375 hint_reg = register_hint->assigned_reg(); 5376 hint_regHi = register_hint->assigned_regHi(); 5377 5378 if (allocator()->is_precolored_cpu_interval(register_hint)) { 5379 assert(hint_reg != any_reg && hint_regHi == any_reg, "must be for fixed intervals"); 5380 hint_regHi = hint_reg + 1; // connect e.g. eax-edx 5381 } 5382 TRACE_LINEAR_SCAN(4, tty->print(" hint registers %d, %d from interval ", hint_reg, hint_regHi); register_hint->print()); 5383 5384 } else { 5385 hint_reg = any_reg; 5386 hint_regHi = any_reg; 5387 } 5388 assert(hint_reg == any_reg || hint_reg != hint_regHi, "hint reg and regHi equal"); 5389 assert(cur->assigned_reg() == any_reg && cur->assigned_regHi() == any_reg, "register already assigned to interval"); 5390 5391 // the register must be free at least until this position 5392 int reg_needed_until = cur->from() + 1; 5393 int interval_to = cur->to(); 5394 5395 bool need_split = false; 5396 int split_pos = -1; 5397 int reg = any_reg; 5398 int regHi = any_reg; 5399 5400 if (_adjacent_regs) { 5401 reg = find_free_double_reg(reg_needed_until, interval_to, hint_reg, &need_split); 5402 regHi = reg + 1; 5403 if (reg == any_reg) { 5404 return false; 5405 } 5406 split_pos = MIN2(_use_pos[reg], _use_pos[regHi]); 5407 5408 } else { 5409 reg = find_free_reg(reg_needed_until, interval_to, hint_reg, any_reg, &need_split); 5410 if (reg == any_reg) { 5411 return false; 5412 } 5413 split_pos = _use_pos[reg]; 5414 5415 if (_num_phys_regs == 2) { 5416 regHi = find_free_reg(reg_needed_until, interval_to, hint_regHi, reg, &need_split); 5417 5418 if (_use_pos[reg] < interval_to && regHi == any_reg) { 5419 // do not split interval if only one register can be assigned until the split pos 5420 // (when one register is found for the whole interval, split&spill is only 5421 // performed for the hi register) 5422 return false; 5423 5424 } else if (regHi != any_reg) { 5425 split_pos = MIN2(split_pos, _use_pos[regHi]); 5426 5427 // sort register numbers to prevent e.g. a move from eax,ebx to ebx,eax 5428 if (reg > regHi) { 5429 int temp = reg; 5430 reg = regHi; 5431 regHi = temp; 5432 } 5433 } 5434 } 5435 } 5436 5437 cur->assign_reg(reg, regHi); 5438 TRACE_LINEAR_SCAN(2, tty->print_cr("selected register %d, %d", reg, regHi)); 5439 5440 assert(split_pos > 0, "invalid split_pos"); 5441 if (need_split) { 5442 // register not available for full interval, so split it 5443 split_when_partial_register_available(cur, split_pos); 5444 } 5445 5446 // only return true if interval is completely assigned 5447 return _num_phys_regs == 1 || regHi != any_reg; 5448 } 5449 5450 5451 int LinearScanWalker::find_locked_reg(int reg_needed_until, int interval_to, int hint_reg, int ignore_reg, bool* need_split) { 5452 int max_reg = any_reg; 5453 5454 for (int i = _first_reg; i <= _last_reg; i++) { 5455 if (i == ignore_reg) { 5456 // this register must be ignored 5457 5458 } else if (_use_pos[i] > reg_needed_until) { 5459 if (max_reg == any_reg || i == hint_reg || (_use_pos[i] > _use_pos[max_reg] && max_reg != hint_reg)) { 5460 max_reg = i; 5461 } 5462 } 5463 } 5464 5465 if (max_reg != any_reg && _block_pos[max_reg] <= interval_to) { 5466 *need_split = true; 5467 } 5468 5469 return max_reg; 5470 } 5471 5472 int LinearScanWalker::find_locked_double_reg(int reg_needed_until, int interval_to, int hint_reg, bool* need_split) { 5473 assert((_last_reg - _first_reg + 1) % 2 == 0, "adjust algorithm"); 5474 5475 int max_reg = any_reg; 5476 5477 for (int i = _first_reg; i < _last_reg; i+=2) { 5478 if (_use_pos[i] > reg_needed_until && _use_pos[i + 1] > reg_needed_until) { 5479 if (max_reg == any_reg || _use_pos[i] > _use_pos[max_reg]) { 5480 max_reg = i; 5481 } 5482 } 5483 } 5484 5485 if (_block_pos[max_reg] <= interval_to || _block_pos[max_reg + 1] <= interval_to) { 5486 *need_split = true; 5487 } 5488 5489 return max_reg; 5490 } 5491 5492 void LinearScanWalker::split_and_spill_intersecting_intervals(int reg, int regHi) { 5493 assert(reg != any_reg, "no register assigned"); 5494 5495 for (int i = 0; i < _spill_intervals[reg]->length(); i++) { 5496 Interval* it = _spill_intervals[reg]->at(i); 5497 remove_from_list(it); 5498 split_and_spill_interval(it); 5499 } 5500 5501 if (regHi != any_reg) { 5502 IntervalList* processed = _spill_intervals[reg]; 5503 for (int i = 0; i < _spill_intervals[regHi]->length(); i++) { 5504 Interval* it = _spill_intervals[regHi]->at(i); 5505 if (processed->index_of(it) == -1) { 5506 remove_from_list(it); 5507 split_and_spill_interval(it); 5508 } 5509 } 5510 } 5511 } 5512 5513 5514 // Split an Interval and spill it to memory so that cur can be placed in a register 5515 void LinearScanWalker::alloc_locked_reg(Interval* cur) { 5516 TRACE_LINEAR_SCAN(2, tty->print("need to split and spill to get register for "); cur->print()); 5517 5518 // collect current usage of registers 5519 init_use_lists(false); 5520 spill_exclude_active_fixed(); 5521 // spill_block_unhandled_fixed(cur); 5522 assert(unhandled_first(fixedKind) == Interval::end(), "must not have unhandled fixed intervals because all fixed intervals have a use at position 0"); 5523 spill_block_inactive_fixed(cur); 5524 spill_collect_active_any(); 5525 spill_collect_inactive_any(cur); 5526 5527 #ifndef PRODUCT 5528 if (TraceLinearScanLevel >= 4) { 5529 tty->print_cr(" state of registers:"); 5530 for (int i = _first_reg; i <= _last_reg; i++) { 5531 tty->print(" reg %d: use_pos: %d, block_pos: %d, intervals: ", i, _use_pos[i], _block_pos[i]); 5532 for (int j = 0; j < _spill_intervals[i]->length(); j++) { 5533 tty->print("%d ", _spill_intervals[i]->at(j)->reg_num()); 5534 } 5535 tty->cr(); 5536 } 5537 } 5538 #endif 5539 5540 // the register must be free at least until this position 5541 int reg_needed_until = MIN2(cur->first_usage(mustHaveRegister), cur->from() + 1); 5542 int interval_to = cur->to(); 5543 assert (reg_needed_until > 0 && reg_needed_until < max_jint, "interval has no use"); 5544 5545 int split_pos = 0; 5546 int use_pos = 0; 5547 bool need_split = false; 5548 int reg, regHi; 5549 5550 if (_adjacent_regs) { 5551 reg = find_locked_double_reg(reg_needed_until, interval_to, any_reg, &need_split); 5552 regHi = reg + 1; 5553 5554 if (reg != any_reg) { 5555 use_pos = MIN2(_use_pos[reg], _use_pos[regHi]); 5556 split_pos = MIN2(_block_pos[reg], _block_pos[regHi]); 5557 } 5558 } else { 5559 reg = find_locked_reg(reg_needed_until, interval_to, any_reg, cur->assigned_reg(), &need_split); 5560 regHi = any_reg; 5561 5562 if (reg != any_reg) { 5563 use_pos = _use_pos[reg]; 5564 split_pos = _block_pos[reg]; 5565 5566 if (_num_phys_regs == 2) { 5567 if (cur->assigned_reg() != any_reg) { 5568 regHi = reg; 5569 reg = cur->assigned_reg(); 5570 } else { 5571 regHi = find_locked_reg(reg_needed_until, interval_to, any_reg, reg, &need_split); 5572 if (regHi != any_reg) { 5573 use_pos = MIN2(use_pos, _use_pos[regHi]); 5574 split_pos = MIN2(split_pos, _block_pos[regHi]); 5575 } 5576 } 5577 5578 if (regHi != any_reg && reg > regHi) { 5579 // sort register numbers to prevent e.g. a move from eax,ebx to ebx,eax 5580 int temp = reg; 5581 reg = regHi; 5582 regHi = temp; 5583 } 5584 } 5585 } 5586 } 5587 5588 if (reg == any_reg || (_num_phys_regs == 2 && regHi == any_reg) || use_pos <= cur->first_usage(mustHaveRegister)) { 5589 // the first use of cur is later than the spilling position -> spill cur 5590 TRACE_LINEAR_SCAN(4, tty->print_cr("able to spill current interval. first_usage(register): %d, use_pos: %d", cur->first_usage(mustHaveRegister), use_pos)); 5591 5592 if (cur->first_usage(mustHaveRegister) <= cur->from() + 1) { 5593 assert(false, "cannot spill interval that is used in first instruction (possible reason: no register found)"); 5594 // assign a reasonable register and do a bailout in product mode to avoid errors 5595 allocator()->assign_spill_slot(cur); 5596 BAILOUT("LinearScan: no register found"); 5597 } 5598 5599 split_and_spill_interval(cur); 5600 } else { 5601 TRACE_LINEAR_SCAN(4, tty->print_cr("decided to use register %d, %d", reg, regHi)); 5602 assert(reg != any_reg && (_num_phys_regs == 1 || regHi != any_reg), "no register found"); 5603 assert(split_pos > 0, "invalid split_pos"); 5604 assert(need_split == false || split_pos > cur->from(), "splitting interval at from"); 5605 5606 cur->assign_reg(reg, regHi); 5607 if (need_split) { 5608 // register not available for full interval, so split it 5609 split_when_partial_register_available(cur, split_pos); 5610 } 5611 5612 // perform splitting and spilling for all affected intervalls 5613 split_and_spill_intersecting_intervals(reg, regHi); 5614 } 5615 } 5616 5617 bool LinearScanWalker::no_allocation_possible(Interval* cur) { 5618 #ifdef X86 5619 // fast calculation of intervals that can never get a register because the 5620 // the next instruction is a call that blocks all registers 5621 // Note: this does not work if callee-saved registers are available (e.g. on Sparc) 5622 5623 // check if this interval is the result of a split operation 5624 // (an interval got a register until this position) 5625 int pos = cur->from(); 5626 if ((pos & 1) == 1) { 5627 // the current instruction is a call that blocks all registers 5628 if (pos < allocator()->max_lir_op_id() && allocator()->has_call(pos + 1)) { 5629 TRACE_LINEAR_SCAN(4, tty->print_cr(" free register cannot be available because all registers blocked by following call")); 5630 5631 // safety check that there is really no register available 5632 assert(alloc_free_reg(cur) == false, "found a register for this interval"); 5633 return true; 5634 } 5635 5636 } 5637 #endif 5638 return false; 5639 } 5640 5641 void LinearScanWalker::init_vars_for_alloc(Interval* cur) { 5642 BasicType type = cur->type(); 5643 _num_phys_regs = LinearScan::num_physical_regs(type); 5644 _adjacent_regs = LinearScan::requires_adjacent_regs(type); 5645 5646 if (pd_init_regs_for_alloc(cur)) { 5647 // the appropriate register range was selected. 5648 } else if (type == T_FLOAT || type == T_DOUBLE) { 5649 _first_reg = pd_first_fpu_reg; 5650 _last_reg = pd_last_fpu_reg; 5651 } else { 5652 _first_reg = pd_first_cpu_reg; 5653 _last_reg = FrameMap::last_cpu_reg(); 5654 } 5655 5656 assert(0 <= _first_reg && _first_reg < LinearScan::nof_regs, "out of range"); 5657 assert(0 <= _last_reg && _last_reg < LinearScan::nof_regs, "out of range"); 5658 } 5659 5660 5661 bool LinearScanWalker::is_move(LIR_Op* op, Interval* from, Interval* to) { 5662 if (op->code() != lir_move) { 5663 return false; 5664 } 5665 assert(op->as_Op1() != NULL, "move must be LIR_Op1"); 5666 5667 LIR_Opr in = ((LIR_Op1*)op)->in_opr(); 5668 LIR_Opr res = ((LIR_Op1*)op)->result_opr(); 5669 return in->is_virtual() && res->is_virtual() && in->vreg_number() == from->reg_num() && res->vreg_number() == to->reg_num(); 5670 } 5671 5672 // optimization (especially for phi functions of nested loops): 5673 // assign same spill slot to non-intersecting intervals 5674 void LinearScanWalker::combine_spilled_intervals(Interval* cur) { 5675 if (cur->is_split_child()) { 5676 // optimization is only suitable for split parents 5677 return; 5678 } 5679 5680 Interval* register_hint = cur->register_hint(false); 5681 if (register_hint == NULL) { 5682 // cur is not the target of a move, otherwise register_hint would be set 5683 return; 5684 } 5685 assert(register_hint->is_split_parent(), "register hint must be split parent"); 5686 5687 if (cur->spill_state() != noOptimization || register_hint->spill_state() != noOptimization) { 5688 // combining the stack slots for intervals where spill move optimization is applied 5689 // is not benefitial and would cause problems 5690 return; 5691 } 5692 5693 int begin_pos = cur->from(); 5694 int end_pos = cur->to(); 5695 if (end_pos > allocator()->max_lir_op_id() || (begin_pos & 1) != 0 || (end_pos & 1) != 0) { 5696 // safety check that lir_op_with_id is allowed 5697 return; 5698 } 5699 5700 if (!is_move(allocator()->lir_op_with_id(begin_pos), register_hint, cur) || !is_move(allocator()->lir_op_with_id(end_pos), cur, register_hint)) { 5701 // cur and register_hint are not connected with two moves 5702 return; 5703 } 5704 5705 Interval* begin_hint = register_hint->split_child_at_op_id(begin_pos, LIR_OpVisitState::inputMode); 5706 Interval* end_hint = register_hint->split_child_at_op_id(end_pos, LIR_OpVisitState::outputMode); 5707 if (begin_hint == end_hint || begin_hint->to() != begin_pos || end_hint->from() != end_pos) { 5708 // register_hint must be split, otherwise the re-writing of use positions does not work 5709 return; 5710 } 5711 5712 assert(begin_hint->assigned_reg() != any_reg, "must have register assigned"); 5713 assert(end_hint->assigned_reg() == any_reg, "must not have register assigned"); 5714 assert(cur->first_usage(mustHaveRegister) == begin_pos, "must have use position at begin of interval because of move"); 5715 assert(end_hint->first_usage(mustHaveRegister) == end_pos, "must have use position at begin of interval because of move"); 5716 5717 if (begin_hint->assigned_reg() < LinearScan::nof_regs) { 5718 // register_hint is not spilled at begin_pos, so it would not be benefitial to immediately spill cur 5719 return; 5720 } 5721 assert(register_hint->canonical_spill_slot() != -1, "must be set when part of interval was spilled"); 5722 5723 // modify intervals such that cur gets the same stack slot as register_hint 5724 // delete use positions to prevent the intervals to get a register at beginning 5725 cur->set_canonical_spill_slot(register_hint->canonical_spill_slot()); 5726 cur->remove_first_use_pos(); 5727 end_hint->remove_first_use_pos(); 5728 } 5729 5730 5731 // allocate a physical register or memory location to an interval 5732 bool LinearScanWalker::activate_current() { 5733 Interval* cur = current(); 5734 bool result = true; 5735 5736 TRACE_LINEAR_SCAN(2, tty->print ("+++++ activating interval "); cur->print()); 5737 TRACE_LINEAR_SCAN(4, tty->print_cr(" split_parent: %d, insert_move_when_activated: %d", cur->split_parent()->reg_num(), cur->insert_move_when_activated())); 5738 5739 if (cur->assigned_reg() >= LinearScan::nof_regs) { 5740 // activating an interval that has a stack slot assigned -> split it at first use position 5741 // used for method parameters 5742 TRACE_LINEAR_SCAN(4, tty->print_cr(" interval has spill slot assigned (method parameter) -> split it before first use")); 5743 5744 split_stack_interval(cur); 5745 result = false; 5746 5747 } else if (allocator()->gen()->is_vreg_flag_set(cur->reg_num(), LIRGenerator::must_start_in_memory)) { 5748 // activating an interval that must start in a stack slot, but may get a register later 5749 // used for lir_roundfp: rounding is done by store to stack and reload later 5750 TRACE_LINEAR_SCAN(4, tty->print_cr(" interval must start in stack slot -> split it before first use")); 5751 assert(cur->assigned_reg() == any_reg && cur->assigned_regHi() == any_reg, "register already assigned"); 5752 5753 allocator()->assign_spill_slot(cur); 5754 split_stack_interval(cur); 5755 result = false; 5756 5757 } else if (cur->assigned_reg() == any_reg) { 5758 // interval has not assigned register -> normal allocation 5759 // (this is the normal case for most intervals) 5760 TRACE_LINEAR_SCAN(4, tty->print_cr(" normal allocation of register")); 5761 5762 // assign same spill slot to non-intersecting intervals 5763 combine_spilled_intervals(cur); 5764 5765 init_vars_for_alloc(cur); 5766 if (no_allocation_possible(cur) || !alloc_free_reg(cur)) { 5767 // no empty register available. 5768 // split and spill another interval so that this interval gets a register 5769 alloc_locked_reg(cur); 5770 } 5771 5772 // spilled intervals need not be move to active-list 5773 if (cur->assigned_reg() >= LinearScan::nof_regs) { 5774 result = false; 5775 } 5776 } 5777 5778 // load spilled values that become active from stack slot to register 5779 if (cur->insert_move_when_activated()) { 5780 assert(cur->is_split_child(), "must be"); 5781 assert(cur->current_split_child() != NULL, "must be"); 5782 assert(cur->current_split_child()->reg_num() != cur->reg_num(), "cannot insert move between same interval"); 5783 TRACE_LINEAR_SCAN(4, tty->print_cr("Inserting move from interval %d to %d because insert_move_when_activated is set", cur->current_split_child()->reg_num(), cur->reg_num())); 5784 5785 insert_move(cur->from(), cur->current_split_child(), cur); 5786 } 5787 cur->make_current_split_child(); 5788 5789 return result; // true = interval is moved to active list 5790 } 5791 5792 5793 // Implementation of EdgeMoveOptimizer 5794 5795 EdgeMoveOptimizer::EdgeMoveOptimizer() : 5796 _edge_instructions(4), 5797 _edge_instructions_idx(4) 5798 { 5799 } 5800 5801 void EdgeMoveOptimizer::optimize(BlockList* code) { 5802 EdgeMoveOptimizer optimizer = EdgeMoveOptimizer(); 5803 5804 // ignore the first block in the list (index 0 is not processed) 5805 for (int i = code->length() - 1; i >= 1; i--) { 5806 BlockBegin* block = code->at(i); 5807 5808 if (block->number_of_preds() > 1 && !block->is_set(BlockBegin::exception_entry_flag)) { 5809 optimizer.optimize_moves_at_block_end(block); 5810 } 5811 if (block->number_of_sux() == 2) { 5812 optimizer.optimize_moves_at_block_begin(block); 5813 } 5814 } 5815 } 5816 5817 5818 // clear all internal data structures 5819 void EdgeMoveOptimizer::init_instructions() { 5820 _edge_instructions.clear(); 5821 _edge_instructions_idx.clear(); 5822 } 5823 5824 // append a lir-instruction-list and the index of the current operation in to the list 5825 void EdgeMoveOptimizer::append_instructions(LIR_OpList* instructions, int instructions_idx) { 5826 _edge_instructions.append(instructions); 5827 _edge_instructions_idx.append(instructions_idx); 5828 } 5829 5830 // return the current operation of the given edge (predecessor or successor) 5831 LIR_Op* EdgeMoveOptimizer::instruction_at(int edge) { 5832 LIR_OpList* instructions = _edge_instructions.at(edge); 5833 int idx = _edge_instructions_idx.at(edge); 5834 5835 if (idx < instructions->length()) { 5836 return instructions->at(idx); 5837 } else { 5838 return NULL; 5839 } 5840 } 5841 5842 // removes the current operation of the given edge (predecessor or successor) 5843 void EdgeMoveOptimizer::remove_cur_instruction(int edge, bool decrement_index) { 5844 LIR_OpList* instructions = _edge_instructions.at(edge); 5845 int idx = _edge_instructions_idx.at(edge); 5846 instructions->remove_at(idx); 5847 5848 if (decrement_index) { 5849 _edge_instructions_idx.at_put(edge, idx - 1); 5850 } 5851 } 5852 5853 5854 bool EdgeMoveOptimizer::operations_different(LIR_Op* op1, LIR_Op* op2) { 5855 if (op1 == NULL || op2 == NULL) { 5856 // at least one block is already empty -> no optimization possible 5857 return true; 5858 } 5859 5860 if (op1->code() == lir_move && op2->code() == lir_move) { 5861 assert(op1->as_Op1() != NULL, "move must be LIR_Op1"); 5862 assert(op2->as_Op1() != NULL, "move must be LIR_Op1"); 5863 LIR_Op1* move1 = (LIR_Op1*)op1; 5864 LIR_Op1* move2 = (LIR_Op1*)op2; 5865 if (move1->info() == move2->info() && move1->in_opr() == move2->in_opr() && move1->result_opr() == move2->result_opr()) { 5866 // these moves are exactly equal and can be optimized 5867 return false; 5868 } 5869 5870 } else if (op1->code() == lir_fxch && op2->code() == lir_fxch) { 5871 assert(op1->as_Op1() != NULL, "fxch must be LIR_Op1"); 5872 assert(op2->as_Op1() != NULL, "fxch must be LIR_Op1"); 5873 LIR_Op1* fxch1 = (LIR_Op1*)op1; 5874 LIR_Op1* fxch2 = (LIR_Op1*)op2; 5875 if (fxch1->in_opr()->as_jint() == fxch2->in_opr()->as_jint()) { 5876 // equal FPU stack operations can be optimized 5877 return false; 5878 } 5879 5880 } else if (op1->code() == lir_fpop_raw && op2->code() == lir_fpop_raw) { 5881 // equal FPU stack operations can be optimized 5882 return false; 5883 } 5884 5885 // no optimization possible 5886 return true; 5887 } 5888 5889 void EdgeMoveOptimizer::optimize_moves_at_block_end(BlockBegin* block) { 5890 TRACE_LINEAR_SCAN(4, tty->print_cr("optimizing moves at end of block B%d", block->block_id())); 5891 5892 if (block->is_predecessor(block)) { 5893 // currently we can't handle this correctly. 5894 return; 5895 } 5896 5897 init_instructions(); 5898 int num_preds = block->number_of_preds(); 5899 assert(num_preds > 1, "do not call otherwise"); 5900 assert(!block->is_set(BlockBegin::exception_entry_flag), "exception handlers not allowed"); 5901 5902 // setup a list with the lir-instructions of all predecessors 5903 int i; 5904 for (i = 0; i < num_preds; i++) { 5905 BlockBegin* pred = block->pred_at(i); 5906 LIR_OpList* pred_instructions = pred->lir()->instructions_list(); 5907 5908 if (pred->number_of_sux() != 1) { 5909 // this can happen with switch-statements where multiple edges are between 5910 // the same blocks. 5911 return; 5912 } 5913 5914 assert(pred->number_of_sux() == 1, "can handle only one successor"); 5915 assert(pred->sux_at(0) == block, "invalid control flow"); 5916 assert(pred_instructions->last()->code() == lir_branch, "block with successor must end with branch"); 5917 assert(pred_instructions->last()->as_OpBranch() != NULL, "branch must be LIR_OpBranch"); 5918 assert(pred_instructions->last()->as_OpBranch()->cond() == lir_cond_always, "block must end with unconditional branch"); 5919 5920 if (pred_instructions->last()->info() != NULL) { 5921 // can not optimize instructions when debug info is needed 5922 return; 5923 } 5924 5925 // ignore the unconditional branch at the end of the block 5926 append_instructions(pred_instructions, pred_instructions->length() - 2); 5927 } 5928 5929 5930 // process lir-instructions while all predecessors end with the same instruction 5931 while (true) { 5932 LIR_Op* op = instruction_at(0); 5933 for (i = 1; i < num_preds; i++) { 5934 if (operations_different(op, instruction_at(i))) { 5935 // these instructions are different and cannot be optimized -> 5936 // no further optimization possible 5937 return; 5938 } 5939 } 5940 5941 TRACE_LINEAR_SCAN(4, tty->print("found instruction that is equal in all %d predecessors: ", num_preds); op->print()); 5942 5943 // insert the instruction at the beginning of the current block 5944 block->lir()->insert_before(1, op); 5945 5946 // delete the instruction at the end of all predecessors 5947 for (i = 0; i < num_preds; i++) { 5948 remove_cur_instruction(i, true); 5949 } 5950 } 5951 } 5952 5953 5954 void EdgeMoveOptimizer::optimize_moves_at_block_begin(BlockBegin* block) { 5955 TRACE_LINEAR_SCAN(4, tty->print_cr("optimization moves at begin of block B%d", block->block_id())); 5956 5957 init_instructions(); 5958 int num_sux = block->number_of_sux(); 5959 5960 LIR_OpList* cur_instructions = block->lir()->instructions_list(); 5961 5962 assert(num_sux == 2, "method should not be called otherwise"); 5963 assert(cur_instructions->last()->code() == lir_branch, "block with successor must end with branch"); 5964 assert(cur_instructions->last()->as_OpBranch() != NULL, "branch must be LIR_OpBranch"); 5965 assert(cur_instructions->last()->as_OpBranch()->cond() == lir_cond_always, "block must end with unconditional branch"); 5966 5967 if (cur_instructions->last()->info() != NULL) { 5968 // can no optimize instructions when debug info is needed 5969 return; 5970 } 5971 5972 LIR_Op* branch = cur_instructions->at(cur_instructions->length() - 2); 5973 if (branch->info() != NULL || (branch->code() != lir_branch && branch->code() != lir_cond_float_branch)) { 5974 // not a valid case for optimization 5975 // currently, only blocks that end with two branches (conditional branch followed 5976 // by unconditional branch) are optimized 5977 return; 5978 } 5979 5980 // now it is guaranteed that the block ends with two branch instructions. 5981 // the instructions are inserted at the end of the block before these two branches 5982 int insert_idx = cur_instructions->length() - 2; 5983 5984 int i; 5985 #ifdef ASSERT 5986 for (i = insert_idx - 1; i >= 0; i--) { 5987 LIR_Op* op = cur_instructions->at(i); 5988 if ((op->code() == lir_branch || op->code() == lir_cond_float_branch) && ((LIR_OpBranch*)op)->block() != NULL) { 5989 assert(false, "block with two successors can have only two branch instructions"); 5990 } 5991 } 5992 #endif 5993 5994 // setup a list with the lir-instructions of all successors 5995 for (i = 0; i < num_sux; i++) { 5996 BlockBegin* sux = block->sux_at(i); 5997 LIR_OpList* sux_instructions = sux->lir()->instructions_list(); 5998 5999 assert(sux_instructions->at(0)->code() == lir_label, "block must start with label"); 6000 6001 if (sux->number_of_preds() != 1) { 6002 // this can happen with switch-statements where multiple edges are between 6003 // the same blocks. 6004 return; 6005 } 6006 assert(sux->pred_at(0) == block, "invalid control flow"); 6007 assert(!sux->is_set(BlockBegin::exception_entry_flag), "exception handlers not allowed"); 6008 6009 // ignore the label at the beginning of the block 6010 append_instructions(sux_instructions, 1); 6011 } 6012 6013 // process lir-instructions while all successors begin with the same instruction 6014 while (true) { 6015 LIR_Op* op = instruction_at(0); 6016 for (i = 1; i < num_sux; i++) { 6017 if (operations_different(op, instruction_at(i))) { 6018 // these instructions are different and cannot be optimized -> 6019 // no further optimization possible 6020 return; 6021 } 6022 } 6023 6024 TRACE_LINEAR_SCAN(4, tty->print("----- found instruction that is equal in all %d successors: ", num_sux); op->print()); 6025 6026 // insert instruction at end of current block 6027 block->lir()->insert_before(insert_idx, op); 6028 insert_idx++; 6029 6030 // delete the instructions at the beginning of all successors 6031 for (i = 0; i < num_sux; i++) { 6032 remove_cur_instruction(i, false); 6033 } 6034 } 6035 } 6036 6037 6038 // Implementation of ControlFlowOptimizer 6039 6040 ControlFlowOptimizer::ControlFlowOptimizer() : 6041 _original_preds(4) 6042 { 6043 } 6044 6045 void ControlFlowOptimizer::optimize(BlockList* code) { 6046 ControlFlowOptimizer optimizer = ControlFlowOptimizer(); 6047 6048 // push the OSR entry block to the end so that we're not jumping over it. 6049 BlockBegin* osr_entry = code->at(0)->end()->as_Base()->osr_entry(); 6050 if (osr_entry) { 6051 int index = osr_entry->linear_scan_number(); 6052 assert(code->at(index) == osr_entry, "wrong index"); 6053 code->remove_at(index); 6054 code->append(osr_entry); 6055 } 6056 6057 optimizer.reorder_short_loops(code); 6058 optimizer.delete_empty_blocks(code); 6059 optimizer.delete_unnecessary_jumps(code); 6060 optimizer.delete_jumps_to_return(code); 6061 } 6062 6063 void ControlFlowOptimizer::reorder_short_loop(BlockList* code, BlockBegin* header_block, int header_idx) { 6064 int i = header_idx + 1; 6065 int max_end = MIN2(header_idx + ShortLoopSize, code->length()); 6066 while (i < max_end && code->at(i)->loop_depth() >= header_block->loop_depth()) { 6067 i++; 6068 } 6069 6070 if (i == code->length() || code->at(i)->loop_depth() < header_block->loop_depth()) { 6071 int end_idx = i - 1; 6072 BlockBegin* end_block = code->at(end_idx); 6073 6074 if (end_block->number_of_sux() == 1 && end_block->sux_at(0) == header_block) { 6075 // short loop from header_idx to end_idx found -> reorder blocks such that 6076 // the header_block is the last block instead of the first block of the loop 6077 TRACE_LINEAR_SCAN(1, tty->print_cr("Reordering short loop: length %d, header B%d, end B%d", 6078 end_idx - header_idx + 1, 6079 header_block->block_id(), end_block->block_id())); 6080 6081 for (int j = header_idx; j < end_idx; j++) { 6082 code->at_put(j, code->at(j + 1)); 6083 } 6084 code->at_put(end_idx, header_block); 6085 6086 // correct the flags so that any loop alignment occurs in the right place. 6087 assert(code->at(end_idx)->is_set(BlockBegin::backward_branch_target_flag), "must be backward branch target"); 6088 code->at(end_idx)->clear(BlockBegin::backward_branch_target_flag); 6089 code->at(header_idx)->set(BlockBegin::backward_branch_target_flag); 6090 } 6091 } 6092 } 6093 6094 void ControlFlowOptimizer::reorder_short_loops(BlockList* code) { 6095 for (int i = code->length() - 1; i >= 0; i--) { 6096 BlockBegin* block = code->at(i); 6097 6098 if (block->is_set(BlockBegin::linear_scan_loop_header_flag)) { 6099 reorder_short_loop(code, block, i); 6100 } 6101 } 6102 6103 DEBUG_ONLY(verify(code)); 6104 } 6105 6106 // only blocks with exactly one successor can be deleted. Such blocks 6107 // must always end with an unconditional branch to this successor 6108 bool ControlFlowOptimizer::can_delete_block(BlockBegin* block) { 6109 if (block->number_of_sux() != 1 || block->number_of_exception_handlers() != 0 || block->is_entry_block()) { 6110 return false; 6111 } 6112 6113 LIR_OpList* instructions = block->lir()->instructions_list(); 6114 6115 assert(instructions->length() >= 2, "block must have label and branch"); 6116 assert(instructions->at(0)->code() == lir_label, "first instruction must always be a label"); 6117 assert(instructions->last()->as_OpBranch() != NULL, "last instrcution must always be a branch"); 6118 assert(instructions->last()->as_OpBranch()->cond() == lir_cond_always, "branch must be unconditional"); 6119 assert(instructions->last()->as_OpBranch()->block() == block->sux_at(0), "branch target must be the successor"); 6120 6121 // block must have exactly one successor 6122 6123 if (instructions->length() == 2 && instructions->last()->info() == NULL) { 6124 return true; 6125 } 6126 return false; 6127 } 6128 6129 // substitute branch targets in all branch-instructions of this blocks 6130 void ControlFlowOptimizer::substitute_branch_target(BlockBegin* block, BlockBegin* target_from, BlockBegin* target_to) { 6131 TRACE_LINEAR_SCAN(3, tty->print_cr("Deleting empty block: substituting from B%d to B%d inside B%d", target_from->block_id(), target_to->block_id(), block->block_id())); 6132 6133 LIR_OpList* instructions = block->lir()->instructions_list(); 6134 6135 assert(instructions->at(0)->code() == lir_label, "first instruction must always be a label"); 6136 for (int i = instructions->length() - 1; i >= 1; i--) { 6137 LIR_Op* op = instructions->at(i); 6138 6139 if (op->code() == lir_branch || op->code() == lir_cond_float_branch) { 6140 assert(op->as_OpBranch() != NULL, "branch must be of type LIR_OpBranch"); 6141 LIR_OpBranch* branch = (LIR_OpBranch*)op; 6142 6143 if (branch->block() == target_from) { 6144 branch->change_block(target_to); 6145 } 6146 if (branch->ublock() == target_from) { 6147 branch->change_ublock(target_to); 6148 } 6149 } 6150 } 6151 } 6152 6153 void ControlFlowOptimizer::delete_empty_blocks(BlockList* code) { 6154 int old_pos = 0; 6155 int new_pos = 0; 6156 int num_blocks = code->length(); 6157 6158 while (old_pos < num_blocks) { 6159 BlockBegin* block = code->at(old_pos); 6160 6161 if (can_delete_block(block)) { 6162 BlockBegin* new_target = block->sux_at(0); 6163 6164 // propagate backward branch target flag for correct code alignment 6165 if (block->is_set(BlockBegin::backward_branch_target_flag)) { 6166 new_target->set(BlockBegin::backward_branch_target_flag); 6167 } 6168 6169 // collect a list with all predecessors that contains each predecessor only once 6170 // the predecessors of cur are changed during the substitution, so a copy of the 6171 // predecessor list is necessary 6172 int j; 6173 _original_preds.clear(); 6174 for (j = block->number_of_preds() - 1; j >= 0; j--) { 6175 BlockBegin* pred = block->pred_at(j); 6176 if (_original_preds.index_of(pred) == -1) { 6177 _original_preds.append(pred); 6178 } 6179 } 6180 6181 for (j = _original_preds.length() - 1; j >= 0; j--) { 6182 BlockBegin* pred = _original_preds.at(j); 6183 substitute_branch_target(pred, block, new_target); 6184 pred->substitute_sux(block, new_target); 6185 } 6186 } else { 6187 // adjust position of this block in the block list if blocks before 6188 // have been deleted 6189 if (new_pos != old_pos) { 6190 code->at_put(new_pos, code->at(old_pos)); 6191 } 6192 new_pos++; 6193 } 6194 old_pos++; 6195 } 6196 code->truncate(new_pos); 6197 6198 DEBUG_ONLY(verify(code)); 6199 } 6200 6201 void ControlFlowOptimizer::delete_unnecessary_jumps(BlockList* code) { 6202 // skip the last block because there a branch is always necessary 6203 for (int i = code->length() - 2; i >= 0; i--) { 6204 BlockBegin* block = code->at(i); 6205 LIR_OpList* instructions = block->lir()->instructions_list(); 6206 6207 LIR_Op* last_op = instructions->last(); 6208 if (last_op->code() == lir_branch) { 6209 assert(last_op->as_OpBranch() != NULL, "branch must be of type LIR_OpBranch"); 6210 LIR_OpBranch* last_branch = (LIR_OpBranch*)last_op; 6211 6212 assert(last_branch->block() != NULL, "last branch must always have a block as target"); 6213 assert(last_branch->label() == last_branch->block()->label(), "must be equal"); 6214 6215 if (last_branch->info() == NULL) { 6216 if (last_branch->block() == code->at(i + 1)) { 6217 6218 TRACE_LINEAR_SCAN(3, tty->print_cr("Deleting unconditional branch at end of block B%d", block->block_id())); 6219 6220 // delete last branch instruction 6221 instructions->truncate(instructions->length() - 1); 6222 6223 } else { 6224 LIR_Op* prev_op = instructions->at(instructions->length() - 2); 6225 if (prev_op->code() == lir_branch || prev_op->code() == lir_cond_float_branch) { 6226 assert(prev_op->as_OpBranch() != NULL, "branch must be of type LIR_OpBranch"); 6227 LIR_OpBranch* prev_branch = (LIR_OpBranch*)prev_op; 6228 6229 if (prev_branch->stub() == NULL) { 6230 6231 LIR_Op2* prev_cmp = NULL; 6232 6233 for(int j = instructions->length() - 3; j >= 0 && prev_cmp == NULL; j--) { 6234 prev_op = instructions->at(j); 6235 if (prev_op->code() == lir_cmp) { 6236 assert(prev_op->as_Op2() != NULL, "branch must be of type LIR_Op2"); 6237 prev_cmp = (LIR_Op2*)prev_op; 6238 assert(prev_branch->cond() == prev_cmp->condition(), "should be the same"); 6239 } 6240 } 6241 assert(prev_cmp != NULL, "should have found comp instruction for branch"); 6242 if (prev_branch->block() == code->at(i + 1) && prev_branch->info() == NULL) { 6243 6244 TRACE_LINEAR_SCAN(3, tty->print_cr("Negating conditional branch and deleting unconditional branch at end of block B%d", block->block_id())); 6245 6246 // eliminate a conditional branch to the immediate successor 6247 prev_branch->change_block(last_branch->block()); 6248 prev_branch->negate_cond(); 6249 prev_cmp->set_condition(prev_branch->cond()); 6250 instructions->truncate(instructions->length() - 1); 6251 } 6252 } 6253 } 6254 } 6255 } 6256 } 6257 } 6258 6259 DEBUG_ONLY(verify(code)); 6260 } 6261 6262 void ControlFlowOptimizer::delete_jumps_to_return(BlockList* code) { 6263 #ifdef ASSERT 6264 BitMap return_converted(BlockBegin::number_of_blocks()); 6265 return_converted.clear(); 6266 #endif 6267 6268 for (int i = code->length() - 1; i >= 0; i--) { 6269 BlockBegin* block = code->at(i); 6270 LIR_OpList* cur_instructions = block->lir()->instructions_list(); 6271 LIR_Op* cur_last_op = cur_instructions->last(); 6272 6273 assert(cur_instructions->at(0)->code() == lir_label, "first instruction must always be a label"); 6274 if (cur_instructions->length() == 2 && cur_last_op->code() == lir_return) { 6275 // the block contains only a label and a return 6276 // if a predecessor ends with an unconditional jump to this block, then the jump 6277 // can be replaced with a return instruction 6278 // 6279 // Note: the original block with only a return statement cannot be deleted completely 6280 // because the predecessors might have other (conditional) jumps to this block 6281 // -> this may lead to unnecesary return instructions in the final code 6282 6283 assert(cur_last_op->info() == NULL, "return instructions do not have debug information"); 6284 assert(block->number_of_sux() == 0 || 6285 (return_converted.at(block->block_id()) && block->number_of_sux() == 1), 6286 "blocks that end with return must not have successors"); 6287 6288 assert(cur_last_op->as_Op1() != NULL, "return must be LIR_Op1"); 6289 LIR_Opr return_opr = ((LIR_Op1*)cur_last_op)->in_opr(); 6290 6291 for (int j = block->number_of_preds() - 1; j >= 0; j--) { 6292 BlockBegin* pred = block->pred_at(j); 6293 LIR_OpList* pred_instructions = pred->lir()->instructions_list(); 6294 LIR_Op* pred_last_op = pred_instructions->last(); 6295 6296 if (pred_last_op->code() == lir_branch) { 6297 assert(pred_last_op->as_OpBranch() != NULL, "branch must be LIR_OpBranch"); 6298 LIR_OpBranch* pred_last_branch = (LIR_OpBranch*)pred_last_op; 6299 6300 if (pred_last_branch->block() == block && pred_last_branch->cond() == lir_cond_always && pred_last_branch->info() == NULL) { 6301 // replace the jump to a return with a direct return 6302 // Note: currently the edge between the blocks is not deleted 6303 pred_instructions->at_put(pred_instructions->length() - 1, new LIR_Op1(lir_return, return_opr)); 6304 #ifdef ASSERT 6305 return_converted.set_bit(pred->block_id()); 6306 #endif 6307 } 6308 } 6309 } 6310 } 6311 } 6312 } 6313 6314 6315 #ifdef ASSERT 6316 void ControlFlowOptimizer::verify(BlockList* code) { 6317 for (int i = 0; i < code->length(); i++) { 6318 BlockBegin* block = code->at(i); 6319 LIR_OpList* instructions = block->lir()->instructions_list(); 6320 6321 int j; 6322 for (j = 0; j < instructions->length(); j++) { 6323 LIR_OpBranch* op_branch = instructions->at(j)->as_OpBranch(); 6324 6325 if (op_branch != NULL) { 6326 assert(op_branch->block() == NULL || code->index_of(op_branch->block()) != -1, "branch target not valid"); 6327 assert(op_branch->ublock() == NULL || code->index_of(op_branch->ublock()) != -1, "branch target not valid"); 6328 } 6329 } 6330 6331 for (j = 0; j < block->number_of_sux() - 1; j++) { 6332 BlockBegin* sux = block->sux_at(j); 6333 assert(code->index_of(sux) != -1, "successor not valid"); 6334 } 6335 6336 for (j = 0; j < block->number_of_preds() - 1; j++) { 6337 BlockBegin* pred = block->pred_at(j); 6338 assert(code->index_of(pred) != -1, "successor not valid"); 6339 } 6340 } 6341 } 6342 #endif 6343 6344 6345 #ifndef PRODUCT 6346 6347 // Implementation of LinearStatistic 6348 6349 const char* LinearScanStatistic::counter_name(int counter_idx) { 6350 switch (counter_idx) { 6351 case counter_method: return "compiled methods"; 6352 case counter_fpu_method: return "methods using fpu"; 6353 case counter_loop_method: return "methods with loops"; 6354 case counter_exception_method:return "methods with xhandler"; 6355 6356 case counter_loop: return "loops"; 6357 case counter_block: return "blocks"; 6358 case counter_loop_block: return "blocks inside loop"; 6359 case counter_exception_block: return "exception handler entries"; 6360 case counter_interval: return "intervals"; 6361 case counter_fixed_interval: return "fixed intervals"; 6362 case counter_range: return "ranges"; 6363 case counter_fixed_range: return "fixed ranges"; 6364 case counter_use_pos: return "use positions"; 6365 case counter_fixed_use_pos: return "fixed use positions"; 6366 case counter_spill_slots: return "spill slots"; 6367 6368 // counter for classes of lir instructions 6369 case counter_instruction: return "total instructions"; 6370 case counter_label: return "labels"; 6371 case counter_entry: return "method entries"; 6372 case counter_return: return "method returns"; 6373 case counter_call: return "method calls"; 6374 case counter_move: return "moves"; 6375 case counter_cmp: return "compare"; 6376 case counter_cond_branch: return "conditional branches"; 6377 case counter_uncond_branch: return "unconditional branches"; 6378 case counter_stub_branch: return "branches to stub"; 6379 case counter_alu: return "artithmetic + logic"; 6380 case counter_alloc: return "allocations"; 6381 case counter_sync: return "synchronisation"; 6382 case counter_throw: return "throw"; 6383 case counter_unwind: return "unwind"; 6384 case counter_typecheck: return "type+null-checks"; 6385 case counter_fpu_stack: return "fpu-stack"; 6386 case counter_misc_inst: return "other instructions"; 6387 case counter_other_inst: return "misc. instructions"; 6388 6389 // counter for different types of moves 6390 case counter_move_total: return "total moves"; 6391 case counter_move_reg_reg: return "register->register"; 6392 case counter_move_reg_stack: return "register->stack"; 6393 case counter_move_stack_reg: return "stack->register"; 6394 case counter_move_stack_stack:return "stack->stack"; 6395 case counter_move_reg_mem: return "register->memory"; 6396 case counter_move_mem_reg: return "memory->register"; 6397 case counter_move_const_any: return "constant->any"; 6398 6399 case blank_line_1: return ""; 6400 case blank_line_2: return ""; 6401 6402 default: ShouldNotReachHere(); return ""; 6403 } 6404 } 6405 6406 LinearScanStatistic::Counter LinearScanStatistic::base_counter(int counter_idx) { 6407 if (counter_idx == counter_fpu_method || counter_idx == counter_loop_method || counter_idx == counter_exception_method) { 6408 return counter_method; 6409 } else if (counter_idx == counter_loop_block || counter_idx == counter_exception_block) { 6410 return counter_block; 6411 } else if (counter_idx >= counter_instruction && counter_idx <= counter_other_inst) { 6412 return counter_instruction; 6413 } else if (counter_idx >= counter_move_total && counter_idx <= counter_move_const_any) { 6414 return counter_move_total; 6415 } 6416 return invalid_counter; 6417 } 6418 6419 LinearScanStatistic::LinearScanStatistic() { 6420 for (int i = 0; i < number_of_counters; i++) { 6421 _counters_sum[i] = 0; 6422 _counters_max[i] = -1; 6423 } 6424 6425 } 6426 6427 // add the method-local numbers to the total sum 6428 void LinearScanStatistic::sum_up(LinearScanStatistic &method_statistic) { 6429 for (int i = 0; i < number_of_counters; i++) { 6430 _counters_sum[i] += method_statistic._counters_sum[i]; 6431 _counters_max[i] = MAX2(_counters_max[i], method_statistic._counters_sum[i]); 6432 } 6433 } 6434 6435 void LinearScanStatistic::print(const char* title) { 6436 if (CountLinearScan || TraceLinearScanLevel > 0) { 6437 tty->cr(); 6438 tty->print_cr("***** LinearScan statistic - %s *****", title); 6439 6440 for (int i = 0; i < number_of_counters; i++) { 6441 if (_counters_sum[i] > 0 || _counters_max[i] >= 0) { 6442 tty->print("%25s: %8d", counter_name(i), _counters_sum[i]); 6443 6444 if (base_counter(i) != invalid_counter) { 6445 tty->print(" (%5.1f%%) ", _counters_sum[i] * 100.0 / _counters_sum[base_counter(i)]); 6446 } else { 6447 tty->print(" "); 6448 } 6449 6450 if (_counters_max[i] >= 0) { 6451 tty->print("%8d", _counters_max[i]); 6452 } 6453 } 6454 tty->cr(); 6455 } 6456 } 6457 } 6458 6459 void LinearScanStatistic::collect(LinearScan* allocator) { 6460 inc_counter(counter_method); 6461 if (allocator->has_fpu_registers()) { 6462 inc_counter(counter_fpu_method); 6463 } 6464 if (allocator->num_loops() > 0) { 6465 inc_counter(counter_loop_method); 6466 } 6467 inc_counter(counter_loop, allocator->num_loops()); 6468 inc_counter(counter_spill_slots, allocator->max_spills()); 6469 6470 int i; 6471 for (i = 0; i < allocator->interval_count(); i++) { 6472 Interval* cur = allocator->interval_at(i); 6473 6474 if (cur != NULL) { 6475 inc_counter(counter_interval); 6476 inc_counter(counter_use_pos, cur->num_use_positions()); 6477 if (LinearScan::is_precolored_interval(cur)) { 6478 inc_counter(counter_fixed_interval); 6479 inc_counter(counter_fixed_use_pos, cur->num_use_positions()); 6480 } 6481 6482 Range* range = cur->first(); 6483 while (range != Range::end()) { 6484 inc_counter(counter_range); 6485 if (LinearScan::is_precolored_interval(cur)) { 6486 inc_counter(counter_fixed_range); 6487 } 6488 range = range->next(); 6489 } 6490 } 6491 } 6492 6493 bool has_xhandlers = false; 6494 // Note: only count blocks that are in code-emit order 6495 for (i = 0; i < allocator->ir()->code()->length(); i++) { 6496 BlockBegin* cur = allocator->ir()->code()->at(i); 6497 6498 inc_counter(counter_block); 6499 if (cur->loop_depth() > 0) { 6500 inc_counter(counter_loop_block); 6501 } 6502 if (cur->is_set(BlockBegin::exception_entry_flag)) { 6503 inc_counter(counter_exception_block); 6504 has_xhandlers = true; 6505 } 6506 6507 LIR_OpList* instructions = cur->lir()->instructions_list(); 6508 for (int j = 0; j < instructions->length(); j++) { 6509 LIR_Op* op = instructions->at(j); 6510 6511 inc_counter(counter_instruction); 6512 6513 switch (op->code()) { 6514 case lir_label: inc_counter(counter_label); break; 6515 case lir_std_entry: 6516 case lir_osr_entry: inc_counter(counter_entry); break; 6517 case lir_return: inc_counter(counter_return); break; 6518 6519 case lir_rtcall: 6520 case lir_static_call: 6521 case lir_optvirtual_call: 6522 case lir_virtual_call: inc_counter(counter_call); break; 6523 6524 case lir_move: { 6525 inc_counter(counter_move); 6526 inc_counter(counter_move_total); 6527 6528 LIR_Opr in = op->as_Op1()->in_opr(); 6529 LIR_Opr res = op->as_Op1()->result_opr(); 6530 if (in->is_register()) { 6531 if (res->is_register()) { 6532 inc_counter(counter_move_reg_reg); 6533 } else if (res->is_stack()) { 6534 inc_counter(counter_move_reg_stack); 6535 } else if (res->is_address()) { 6536 inc_counter(counter_move_reg_mem); 6537 } else { 6538 ShouldNotReachHere(); 6539 } 6540 } else if (in->is_stack()) { 6541 if (res->is_register()) { 6542 inc_counter(counter_move_stack_reg); 6543 } else { 6544 inc_counter(counter_move_stack_stack); 6545 } 6546 } else if (in->is_address()) { 6547 assert(res->is_register(), "must be"); 6548 inc_counter(counter_move_mem_reg); 6549 } else if (in->is_constant()) { 6550 inc_counter(counter_move_const_any); 6551 } else { 6552 ShouldNotReachHere(); 6553 } 6554 break; 6555 } 6556 6557 case lir_cmp: inc_counter(counter_cmp); break; 6558 6559 case lir_branch: 6560 case lir_cond_float_branch: { 6561 LIR_OpBranch* branch = op->as_OpBranch(); 6562 if (branch->block() == NULL) { 6563 inc_counter(counter_stub_branch); 6564 } else if (branch->cond() == lir_cond_always) { 6565 inc_counter(counter_uncond_branch); 6566 } else { 6567 inc_counter(counter_cond_branch); 6568 } 6569 break; 6570 } 6571 6572 case lir_neg: 6573 case lir_add: 6574 case lir_sub: 6575 case lir_mul: 6576 case lir_mul_strictfp: 6577 case lir_div: 6578 case lir_div_strictfp: 6579 case lir_rem: 6580 case lir_sqrt: 6581 case lir_sin: 6582 case lir_cos: 6583 case lir_abs: 6584 case lir_log10: 6585 case lir_log: 6586 case lir_pow: 6587 case lir_exp: 6588 case lir_logic_and: 6589 case lir_logic_or: 6590 case lir_logic_xor: 6591 case lir_shl: 6592 case lir_shr: 6593 case lir_ushr: inc_counter(counter_alu); break; 6594 6595 case lir_alloc_object: 6596 case lir_alloc_array: inc_counter(counter_alloc); break; 6597 6598 case lir_monaddr: 6599 case lir_lock: 6600 case lir_unlock: inc_counter(counter_sync); break; 6601 6602 case lir_throw: inc_counter(counter_throw); break; 6603 6604 case lir_unwind: inc_counter(counter_unwind); break; 6605 6606 case lir_null_check: 6607 case lir_leal: 6608 case lir_instanceof: 6609 case lir_checkcast: 6610 case lir_store_check: inc_counter(counter_typecheck); break; 6611 6612 case lir_fpop_raw: 6613 case lir_fxch: 6614 case lir_fld: inc_counter(counter_fpu_stack); break; 6615 6616 case lir_nop: 6617 case lir_push: 6618 case lir_pop: 6619 case lir_convert: 6620 case lir_roundfp: 6621 case lir_cmove: inc_counter(counter_misc_inst); break; 6622 6623 default: inc_counter(counter_other_inst); break; 6624 } 6625 } 6626 } 6627 6628 if (has_xhandlers) { 6629 inc_counter(counter_exception_method); 6630 } 6631 } 6632 6633 void LinearScanStatistic::compute(LinearScan* allocator, LinearScanStatistic &global_statistic) { 6634 if (CountLinearScan || TraceLinearScanLevel > 0) { 6635 6636 LinearScanStatistic local_statistic = LinearScanStatistic(); 6637 6638 local_statistic.collect(allocator); 6639 global_statistic.sum_up(local_statistic); 6640 6641 if (TraceLinearScanLevel > 2) { 6642 local_statistic.print("current local statistic"); 6643 } 6644 } 6645 } 6646 6647 6648 // Implementation of LinearTimers 6649 6650 LinearScanTimers::LinearScanTimers() { 6651 for (int i = 0; i < number_of_timers; i++) { 6652 timer(i)->reset(); 6653 } 6654 } 6655 6656 const char* LinearScanTimers::timer_name(int idx) { 6657 switch (idx) { 6658 case timer_do_nothing: return "Nothing (Time Check)"; 6659 case timer_number_instructions: return "Number Instructions"; 6660 case timer_compute_local_live_sets: return "Local Live Sets"; 6661 case timer_compute_global_live_sets: return "Global Live Sets"; 6662 case timer_build_intervals: return "Build Intervals"; 6663 case timer_sort_intervals_before: return "Sort Intervals Before"; 6664 case timer_allocate_registers: return "Allocate Registers"; 6665 case timer_resolve_data_flow: return "Resolve Data Flow"; 6666 case timer_sort_intervals_after: return "Sort Intervals After"; 6667 case timer_eliminate_spill_moves: return "Spill optimization"; 6668 case timer_assign_reg_num: return "Assign Reg Num"; 6669 case timer_allocate_fpu_stack: return "Allocate FPU Stack"; 6670 case timer_optimize_lir: return "Optimize LIR"; 6671 default: ShouldNotReachHere(); return ""; 6672 } 6673 } 6674 6675 void LinearScanTimers::begin_method() { 6676 if (TimeEachLinearScan) { 6677 // reset all timers to measure only current method 6678 for (int i = 0; i < number_of_timers; i++) { 6679 timer(i)->reset(); 6680 } 6681 } 6682 } 6683 6684 void LinearScanTimers::end_method(LinearScan* allocator) { 6685 if (TimeEachLinearScan) { 6686 6687 double c = timer(timer_do_nothing)->seconds(); 6688 double total = 0; 6689 for (int i = 1; i < number_of_timers; i++) { 6690 total += timer(i)->seconds() - c; 6691 } 6692 6693 if (total >= 0.0005) { 6694 // print all information in one line for automatic processing 6695 tty->print("@"); allocator->compilation()->method()->print_name(); 6696 6697 tty->print("@ %d ", allocator->compilation()->method()->code_size()); 6698 tty->print("@ %d ", allocator->block_at(allocator->block_count() - 1)->last_lir_instruction_id() / 2); 6699 tty->print("@ %d ", allocator->block_count()); 6700 tty->print("@ %d ", allocator->num_virtual_regs()); 6701 tty->print("@ %d ", allocator->interval_count()); 6702 tty->print("@ %d ", allocator->_num_calls); 6703 tty->print("@ %d ", allocator->num_loops()); 6704 6705 tty->print("@ %6.6f ", total); 6706 for (int i = 1; i < number_of_timers; i++) { 6707 tty->print("@ %4.1f ", ((timer(i)->seconds() - c) / total) * 100); 6708 } 6709 tty->cr(); 6710 } 6711 } 6712 } 6713 6714 void LinearScanTimers::print(double total_time) { 6715 if (TimeLinearScan) { 6716 // correction value: sum of dummy-timer that only measures the time that 6717 // is necesary to start and stop itself 6718 double c = timer(timer_do_nothing)->seconds(); 6719 6720 for (int i = 0; i < number_of_timers; i++) { 6721 double t = timer(i)->seconds(); 6722 tty->print_cr(" %25s: %6.3f s (%4.1f%%) corrected: %6.3f s (%4.1f%%)", timer_name(i), t, (t / total_time) * 100.0, t - c, (t - c) / (total_time - 2 * number_of_timers * c) * 100); 6723 } 6724 } 6725 } 6726 6727 #endif // #ifndef PRODUCT