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src/share/vm/c1/c1_LinearScan.cpp

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rev 8069 : 8164652: aarch32: C1 port


2124 
2125         assert(assigned_reg >= pd_first_fpu_reg && assigned_reg <= pd_last_fpu_reg, "no fpu register");
2126         assert(interval->assigned_regHi() == any_reg, "must not have hi register");
2127         return LIR_OprFact::single_fpu(assigned_reg - pd_first_fpu_reg);
2128       }
2129 
2130       case T_DOUBLE: {
2131 #ifdef X86
2132         if (UseSSE >= 2) {
2133           assert(assigned_reg >= pd_first_xmm_reg && assigned_reg <= pd_last_xmm_reg, "no xmm register");
2134           assert(interval->assigned_regHi() == any_reg, "must not have hi register (double xmm values are stored in one register)");
2135           return LIR_OprFact::double_xmm(assigned_reg - pd_first_xmm_reg);
2136         }
2137 #endif
2138 
2139 #ifdef SPARC
2140         assert(assigned_reg >= pd_first_fpu_reg && assigned_reg <= pd_last_fpu_reg, "no fpu register");
2141         assert(interval->assigned_regHi() >= pd_first_fpu_reg && interval->assigned_regHi() <= pd_last_fpu_reg, "no fpu register");
2142         assert(assigned_reg % 2 == 0 && assigned_reg + 1 == interval->assigned_regHi(), "must be sequential and even");
2143         LIR_Opr result = LIR_OprFact::double_fpu(interval->assigned_regHi() - pd_first_fpu_reg, assigned_reg - pd_first_fpu_reg);
2144 #elif defined(ARM32)
2145         assert(assigned_reg >= pd_first_fpu_reg && assigned_reg <= pd_last_fpu_reg, "no fpu register");
2146         assert(interval->assigned_regHi() >= pd_first_fpu_reg && interval->assigned_regHi() <= pd_last_fpu_reg, "no fpu register");
2147         assert(assigned_reg % 2 == 0 && assigned_reg + 1 == interval->assigned_regHi(), "must be sequential and even");
2148         LIR_Opr result = LIR_OprFact::double_fpu(assigned_reg - pd_first_fpu_reg, interval->assigned_regHi() - pd_first_fpu_reg);
2149 #else
2150         assert(assigned_reg >= pd_first_fpu_reg && assigned_reg <= pd_last_fpu_reg, "no fpu register");
2151         assert(interval->assigned_regHi() == any_reg, "must not have hi register (double fpu values are stored in one register on Intel)");
2152         LIR_Opr result = LIR_OprFact::double_fpu(assigned_reg - pd_first_fpu_reg);
2153 #endif
2154         return result;
2155       }
2156 #endif // __SOFTFP__
2157 
2158       default: {
2159         ShouldNotReachHere();
2160         return LIR_OprFact::illegalOpr;
2161       }
2162     }
2163   }
2164 }


2713       // On SPARC, fpu_regnrLo/fpu_regnrHi represents the two halves of
2714       // the double as float registers in the native ordering. On X86,
2715       // fpu_regnrLo is a FPU stack slot whose VMReg represents
2716       // the low-order word of the double and fpu_regnrLo + 1 is the
2717       // name for the other half.  *first and *second must represent the
2718       // least and most significant words, respectively.
2719 
2720 #ifdef X86
2721       // the exact location of fpu stack values is only known
2722       // during fpu stack allocation, so the stack allocator object
2723       // must be present
2724       assert(use_fpu_stack_allocation(), "should not have float stack values without fpu stack allocation (all floats must be SSE2)");
2725       assert(_fpu_stack_allocator != NULL, "must be present");
2726       opr = _fpu_stack_allocator->to_fpu_stack(opr);
2727 
2728       assert(opr->fpu_regnrLo() == opr->fpu_regnrHi(), "assumed in calculation (only fpu_regnrLo is used)");
2729 #endif
2730 #ifdef SPARC
2731       assert(opr->fpu_regnrLo() == opr->fpu_regnrHi() + 1, "assumed in calculation (only fpu_regnrHi is used)");
2732 #endif
2733 #ifdef ARM32
2734       assert(opr->fpu_regnrHi() == opr->fpu_regnrLo() + 1, "assumed in calculation (only fpu_regnrLo is used)");
2735 #endif
2736 #ifdef PPC
2737       assert(opr->fpu_regnrLo() == opr->fpu_regnrHi(), "assumed in calculation (only fpu_regnrHi is used)");
2738 #endif
2739 
2740 #ifdef VM_LITTLE_ENDIAN
2741       VMReg rname_first = frame_map()->fpu_regname(opr->fpu_regnrLo());
2742 #else
2743       VMReg rname_first = frame_map()->fpu_regname(opr->fpu_regnrHi());
2744 #endif
2745 
2746 #ifdef _LP64
2747       first = new LocationValue(Location::new_reg_loc(Location::dbl, rname_first));
2748       second = _int_0_scope_value;
2749 #else
2750       first = new LocationValue(Location::new_reg_loc(Location::normal, rname_first));
2751       // %%% This is probably a waste but we'll keep things as they were for now
2752       if (true) {
2753         VMReg rname_second = rname_first->next();
2754         second = new LocationValue(Location::new_reg_loc(Location::normal, rname_second));
2755       }




2124 
2125         assert(assigned_reg >= pd_first_fpu_reg && assigned_reg <= pd_last_fpu_reg, "no fpu register");
2126         assert(interval->assigned_regHi() == any_reg, "must not have hi register");
2127         return LIR_OprFact::single_fpu(assigned_reg - pd_first_fpu_reg);
2128       }
2129 
2130       case T_DOUBLE: {
2131 #ifdef X86
2132         if (UseSSE >= 2) {
2133           assert(assigned_reg >= pd_first_xmm_reg && assigned_reg <= pd_last_xmm_reg, "no xmm register");
2134           assert(interval->assigned_regHi() == any_reg, "must not have hi register (double xmm values are stored in one register)");
2135           return LIR_OprFact::double_xmm(assigned_reg - pd_first_xmm_reg);
2136         }
2137 #endif
2138 
2139 #ifdef SPARC
2140         assert(assigned_reg >= pd_first_fpu_reg && assigned_reg <= pd_last_fpu_reg, "no fpu register");
2141         assert(interval->assigned_regHi() >= pd_first_fpu_reg && interval->assigned_regHi() <= pd_last_fpu_reg, "no fpu register");
2142         assert(assigned_reg % 2 == 0 && assigned_reg + 1 == interval->assigned_regHi(), "must be sequential and even");
2143         LIR_Opr result = LIR_OprFact::double_fpu(interval->assigned_regHi() - pd_first_fpu_reg, assigned_reg - pd_first_fpu_reg);
2144 #elif defined(ARM32) || defined(AARCH32)
2145         assert(assigned_reg >= pd_first_fpu_reg && assigned_reg <= pd_last_fpu_reg, "no fpu register");
2146         assert(interval->assigned_regHi() >= pd_first_fpu_reg && interval->assigned_regHi() <= pd_last_fpu_reg, "no fpu register");
2147         assert(assigned_reg % 2 == 0 && assigned_reg + 1 == interval->assigned_regHi(), "must be sequential and even");
2148         LIR_Opr result = LIR_OprFact::double_fpu(assigned_reg - pd_first_fpu_reg, interval->assigned_regHi() - pd_first_fpu_reg);
2149 #else
2150         assert(assigned_reg >= pd_first_fpu_reg && assigned_reg <= pd_last_fpu_reg, "no fpu register");
2151         assert(interval->assigned_regHi() == any_reg, "must not have hi register (double fpu values are stored in one register on Intel)");
2152         LIR_Opr result = LIR_OprFact::double_fpu(assigned_reg - pd_first_fpu_reg);
2153 #endif
2154         return result;
2155       }
2156 #endif // __SOFTFP__
2157 
2158       default: {
2159         ShouldNotReachHere();
2160         return LIR_OprFact::illegalOpr;
2161       }
2162     }
2163   }
2164 }


2713       // On SPARC, fpu_regnrLo/fpu_regnrHi represents the two halves of
2714       // the double as float registers in the native ordering. On X86,
2715       // fpu_regnrLo is a FPU stack slot whose VMReg represents
2716       // the low-order word of the double and fpu_regnrLo + 1 is the
2717       // name for the other half.  *first and *second must represent the
2718       // least and most significant words, respectively.
2719 
2720 #ifdef X86
2721       // the exact location of fpu stack values is only known
2722       // during fpu stack allocation, so the stack allocator object
2723       // must be present
2724       assert(use_fpu_stack_allocation(), "should not have float stack values without fpu stack allocation (all floats must be SSE2)");
2725       assert(_fpu_stack_allocator != NULL, "must be present");
2726       opr = _fpu_stack_allocator->to_fpu_stack(opr);
2727 
2728       assert(opr->fpu_regnrLo() == opr->fpu_regnrHi(), "assumed in calculation (only fpu_regnrLo is used)");
2729 #endif
2730 #ifdef SPARC
2731       assert(opr->fpu_regnrLo() == opr->fpu_regnrHi() + 1, "assumed in calculation (only fpu_regnrHi is used)");
2732 #endif
2733 #if defined(ARM32) || defined(AARCH32)
2734       assert(opr->fpu_regnrHi() == opr->fpu_regnrLo() + 1, "assumed in calculation (only fpu_regnrLo is used)");
2735 #endif // ARM32 || AARCH32
2736 #ifdef PPC
2737       assert(opr->fpu_regnrLo() == opr->fpu_regnrHi(), "assumed in calculation (only fpu_regnrHi is used)");
2738 #endif
2739 
2740 #ifdef VM_LITTLE_ENDIAN
2741       VMReg rname_first = frame_map()->fpu_regname(opr->fpu_regnrLo());
2742 #else
2743       VMReg rname_first = frame_map()->fpu_regname(opr->fpu_regnrHi());
2744 #endif
2745 
2746 #ifdef _LP64
2747       first = new LocationValue(Location::new_reg_loc(Location::dbl, rname_first));
2748       second = _int_0_scope_value;
2749 #else
2750       first = new LocationValue(Location::new_reg_loc(Location::normal, rname_first));
2751       // %%% This is probably a waste but we'll keep things as they were for now
2752       if (true) {
2753         VMReg rname_second = rname_first->next();
2754         second = new LocationValue(Location::new_reg_loc(Location::normal, rname_second));
2755       }


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