1 /*
2 * Copyright (c) 2014, Red Hat Inc. All rights reserved.
3 * Copyright (c) 2015, Linaro Ltd. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #ifndef _CPU_STATE_H
27 #define _CPU_STATE_H
28
29 #include <sys/types.h>
30
31 /*
32 * symbolic names used to identify general registers which also match
33 * the registers indices in machine code
34 *
35 * We have 32 general registers which can be read/written as 32 bit or
36 * 64 bit sources/sinks and are appropriately referred to as Wn or Xn
37 * in the assembly code. Some instructions mix these access modes
38 * (e.g. ADD X0, X1, W2) so the implementation of the instruction
39 * needs to *know* which type of read or write access is required.
40 */
41 enum GReg {
42 R0,
43 R1,
44 R2,
45 R3,
46 R4,
47 R5,
48 R6,
49 R7,
50 R8,
51 R9,
52 R10,
53 R11,
54 R12,
55 R13,
56 R14,
57 R15,
58 R16,
59 R17,
60 R18,
61 R19,
62 R20,
63 R21,
64 R22,
65 R23,
66 R24,
67 R25,
68 R26,
69 R27,
70 R28,
71 R29,
72 R30,
73 R31,
74 // and now the aliases
75 RSCRATCH1=R8,
76 RSCRATCH2=R9,
77 RMETHOD=R12,
78 RESP=R20,
79 RDISPATCH=R21,
80 RBCP=R22,
81 RLOCALS=R24,
82 RMONITORS=R25,
83 RCPOOL=R26,
84 RHEAPBASE=R27,
85 RTHREAD=R28,
86 FP = R29,
87 LR = R30,
88 SP = R31,
89 ZR = R31
90 };
91
92 /*
93 * symbolic names used to refer to floating point registers which also
94 * match the registers indices in machine code
95 *
96 * We have 32 FP registers which can be read/written as 8, 16, 32, 64
97 * and 128 bit sources/sinks and are appropriately referred to as Bn,
98 * Hn, Sn, Dn and Qn in the assembly code. Some instructions mix these
99 * access modes (e.g. FCVT S0, D0) so the implementation of the
100 * instruction needs to *know* which type of read or write access is
101 * required.
102 */
103
104 enum VReg {
105 V0,
106 V1,
107 V2,
108 V3,
109 V4,
110 V5,
111 V6,
112 V7,
113 V8,
114 V9,
115 V10,
116 V11,
117 V12,
118 V13,
119 V14,
120 V15,
121 V16,
122 V17,
123 V18,
124 V19,
125 V20,
126 V21,
127 V22,
128 V23,
129 V24,
130 V25,
131 V26,
132 V27,
133 V28,
134 V29,
135 V30,
136 V31,
137 };
138
139 /**
140 * all the different integer bit patterns for the components of a
141 * general register are overlaid here using a union so as to allow all
142 * reading and writing of the desired bits.
143 *
144 * n.b. the ARM spec says that when you write a 32 bit register you
145 * are supposed to write the low 32 bits and zero the high 32
146 * bits. But we don't actually have to care about this because Java
147 * will only ever consume the 32 bits value as a 64 bit quantity after
148 * an explicit extend.
149 */
150 union GRegisterValue
151 {
152 int8_t s8;
153 int16_t s16;
154 int32_t s32;
155 int64_t s64;
156 u_int8_t u8;
157 u_int16_t u16;
158 u_int32_t u32;
159 u_int64_t u64;
160 };
161
162 class GRegister
163 {
164 public:
165 GRegisterValue value;
166 };
167
168 /*
169 * float registers provide for storage of a single, double or quad
170 * word format float in the same register. single floats are not
171 * paired within each double register as per 32 bit arm. instead each
172 * 128 bit register Vn embeds the bits for Sn, and Dn in the lower
173 * quarter and half, respectively, of the bits for Qn.
174 *
175 * The upper bits can also be accessed as single or double floats by
176 * the float vector operations using indexing e.g. V1.D[1], V1.S[3]
177 * etc and, for SIMD operations using a horrible index range notation.
178 *
179 * The spec also talks about accessing float registers as half words
180 * and bytes with Hn and Bn providing access to the low 16 and 8 bits
181 * of Vn but it is not really clear what these bits represent. We can
182 * probably ignore this for Java anyway. However, we do need to access
183 * the raw bits at 32 and 64 bit resolution to load to/from integer
184 * registers.
185 */
186
187 union FRegisterValue
188 {
189 float s;
190 double d;
191 long double q;
192 // eventually we will need to be able to access the data as a vector
193 // the integral array elements allow us to access the bits in s, d,
194 // q, vs and vd at an appropriate level of granularity
195 u_int8_t vb[16];
196 u_int16_t vh[8];
197 u_int32_t vw[4];
198 u_int64_t vx[2];
199 float vs[4];
200 double vd[2];
201 };
202
203 class FRegister
204 {
205 public:
206 FRegisterValue value;
207 };
208
209 /*
210 * CPSR register -- this does not exist as a directly accessible
211 * register but we need to store the flags so we can implement
212 * flag-seting and flag testing operations
213 *
214 * we can possibly use injected x86 asm to report the outcome of flag
215 * setting operations. if so we will need to grab the flags
216 * immediately after the operation in order to ensure we don't lose
217 * them because of the actions of the simulator. so we still need
218 * somewhere to store the condition codes.
219 */
220
221 class CPSRRegister
222 {
223 public:
224 u_int32_t value;
225
226 /*
227 * condition register bit select values
228 *
229 * the order of bits here is important because some of
230 * the flag setting conditional instructions employ a
231 * bit field to populate the flags when a false condition
232 * bypasses execution of the operation and we want to
233 * be able to assign the flags register using the
234 * supplied value.
235 */
236
237 enum CPSRIdx {
238 V_IDX,
239 C_IDX,
240 Z_IDX,
241 N_IDX
242 };
243
244 enum CPSRMask {
245 V = 1 << V_IDX,
246 C = 1 << C_IDX,
247 Z = 1 << Z_IDX,
248 N = 1 << N_IDX
249 };
250
251 static const int CPSR_ALL_FLAGS = (V | C | Z | N);
252 };
253
254 // auxiliary function to assemble the relevant bits from
255 // the x86 EFLAGS register into an ARM CPSR value
256
257 #define X86_V_IDX 11
258 #define X86_C_IDX 0
259 #define X86_Z_IDX 6
260 #define X86_N_IDX 7
261
262 #define X86_V (1 << X86_V_IDX)
263 #define X86_C (1 << X86_C_IDX)
264 #define X86_Z (1 << X86_Z_IDX)
265 #define X86_N (1 << X86_N_IDX)
266
267 inline u_int32_t convertX86Flags(u_int32_t x86flags)
268 {
269 u_int32_t flags;
270 // set N flag
271 flags = ((x86flags & X86_N) >> X86_N_IDX);
272 // shift then or in Z flag
273 flags <<= 1;
274 flags |= ((x86flags & X86_Z) >> X86_Z_IDX);
275 // shift then or in C flag
276 flags <<= 1;
277 flags |= ((x86flags & X86_C) >> X86_C_IDX);
278 // shift then or in V flag
279 flags <<= 1;
280 flags |= ((x86flags & X86_V) >> X86_V_IDX);
281
282 return flags;
283 }
284
285 inline u_int32_t convertX86FlagsFP(u_int32_t x86flags)
286 {
287 // x86 flags set by fcomi(x,y) are ZF:PF:CF
288 // (yes, that's PF for parity, WTF?)
289 // where
290 // 0) 0:0:0 means x > y
291 // 1) 0:0:1 means x < y
292 // 2) 1:0:0 means x = y
293 // 3) 1:1:1 means x and y are unordered
294 // note that we don't have to check PF so
295 // we really have a simple 2-bit case switch
296 // the corresponding ARM64 flags settings
297 // in hi->lo bit order are
298 // 0) --C-
299 // 1) N---
300 // 2) -ZC-
301 // 3) --CV
302
303 static u_int32_t armFlags[] = {
304 0b0010,
305 0b1000,
306 0b0110,
307 0b0011
308 };
309 // pick out the ZF and CF bits
310 u_int32_t zc = ((x86flags & X86_Z) >> X86_Z_IDX);
311 zc <<= 1;
312 zc |= ((x86flags & X86_C) >> X86_C_IDX);
313
314 return armFlags[zc];
315 }
316
317 /*
318 * FPSR register -- floating point status register
319
320 * this register includes IDC, IXC, UFC, OFC, DZC, IOC and QC bits,
321 * and the floating point N, Z, C, V bits but the latter are unused in
322 * aarch32 mode. the sim ignores QC for now.
323 *
324 * bit positions are as per the ARMv7 FPSCR register
325 *
326 * IDC : 7 ==> Input Denormal (cumulative exception bit)
327 * IXC : 4 ==> Inexact
328 * UFC : 3 ==> Underflow
329 * OFC : 2 ==> Overflow
330 * DZC : 1 ==> Division by Zero
331 * IOC : 0 ==> Invalid Operation
332 */
333
334 class FPSRRegister
335 {
336 public:
337 u_int32_t value;
338 // indices for bits in the FPSR register value
339 enum FPSRIdx {
340 IO_IDX = 0,
341 DZ_IDX = 1,
342 OF_IDX = 2,
343 UF_IDX = 3,
344 IX_IDX = 4,
345 ID_IDX = 7
346 };
347 // corresponding bits as numeric values
348 enum FPSRMask {
349 IO = (1 << IO_IDX),
350 DZ = (1 << DZ_IDX),
351 OF = (1 << OF_IDX),
352 UF = (1 << UF_IDX),
353 IX = (1 << IX_IDX),
354 ID = (1 << ID_IDX)
355 };
356 static const int FPSR_ALL_FPSRS = (IO | DZ | OF | UF | IX | ID);
357 };
358
359 // debugger support
360
361 enum PrintFormat
362 {
363 FMT_DECIMAL,
364 FMT_HEX,
365 FMT_SINGLE,
366 FMT_DOUBLE,
367 FMT_QUAD,
368 FMT_MULTI
369 };
370
371 /*
372 * model of the registers and other state associated with the cpu
373 */
374 class CPUState
375 {
376 friend class AArch64Simulator;
377 private:
378 // this is the PC of the instruction being executed
379 u_int64_t pc;
380 // this is the PC of the instruction to be executed next
381 // it is defaulted to pc + 4 at instruction decode but
382 // execute may reset it
383
384 u_int64_t nextpc;
385 GRegister gr[33]; // extra register at index 32 is used
386 // to hold zero value
387 FRegister fr[32];
388 CPSRRegister cpsr;
389 FPSRRegister fpsr;
390
391 public:
392
393 CPUState() {
394 gr[20].value.u64 = 0; // establish initial condition for
395 // checkAssertions()
396 trace_counter = 0;
397 }
398
399 // General Register access macros
400
401 // only xreg or xregs can be used as an lvalue in order to update a
402 // register. this ensures that the top part of a register is always
403 // assigned when it is written by the sim.
404
405 inline u_int64_t &xreg(GReg reg, int r31_is_sp) {
406 if (reg == R31 && !r31_is_sp) {
407 return gr[32].value.u64;
408 } else {
409 return gr[reg].value.u64;
410 }
411 }
412
413 inline int64_t &xregs(GReg reg, int r31_is_sp) {
414 if (reg == R31 && !r31_is_sp) {
415 return gr[32].value.s64;
416 } else {
417 return gr[reg].value.s64;
418 }
419 }
420
421 inline u_int32_t wreg(GReg reg, int r31_is_sp) {
422 if (reg == R31 && !r31_is_sp) {
423 return gr[32].value.u32;
424 } else {
425 return gr[reg].value.u32;
426 }
427 }
428
429 inline int32_t wregs(GReg reg, int r31_is_sp) {
430 if (reg == R31 && !r31_is_sp) {
431 return gr[32].value.s32;
432 } else {
433 return gr[reg].value.s32;
434 }
435 }
436
437 inline u_int32_t hreg(GReg reg, int r31_is_sp) {
438 if (reg == R31 && !r31_is_sp) {
439 return gr[32].value.u16;
440 } else {
441 return gr[reg].value.u16;
442 }
443 }
444
445 inline int32_t hregs(GReg reg, int r31_is_sp) {
446 if (reg == R31 && !r31_is_sp) {
447 return gr[32].value.s16;
448 } else {
449 return gr[reg].value.s16;
450 }
451 }
452
453 inline u_int32_t breg(GReg reg, int r31_is_sp) {
454 if (reg == R31 && !r31_is_sp) {
455 return gr[32].value.u8;
456 } else {
457 return gr[reg].value.u8;
458 }
459 }
460
461 inline int32_t bregs(GReg reg, int r31_is_sp) {
462 if (reg == R31 && !r31_is_sp) {
463 return gr[32].value.s8;
464 } else {
465 return gr[reg].value.s8;
466 }
467 }
468
469 // FP Register access macros
470
471 // all non-vector accessors return a reference so we can both read
472 // and assign
473
474 inline float &sreg(VReg reg) {
475 return fr[reg].value.s;
476 }
477
478 inline double &dreg(VReg reg) {
479 return fr[reg].value.d;
480 }
481
482 inline long double &qreg(VReg reg) {
483 return fr[reg].value.q;
484 }
485
486 // all vector register accessors return a pointer
487
488 inline float *vsreg(VReg reg) {
489 return &fr[reg].value.vs[0];
490 }
491
492 inline double *vdreg(VReg reg) {
493 return &fr[reg].value.vd[0];
494 }
495
496 inline u_int8_t *vbreg(VReg reg) {
497 return &fr[reg].value.vb[0];
498 }
499
500 inline u_int16_t *vhreg(VReg reg) {
501 return &fr[reg].value.vh[0];
502 }
503
504 inline u_int32_t *vwreg(VReg reg) {
505 return &fr[reg].value.vw[0];
506 }
507
508 inline u_int64_t *vxreg(VReg reg) {
509 return &fr[reg].value.vx[0];
510 }
511
512 union GRegisterValue prev_sp, prev_fp;
513
514 static const int trace_size = 256;
515 u_int64_t trace_buffer[trace_size];
516 int trace_counter;
517
518 bool checkAssertions()
519 {
520 // Make sure that SP is 16-aligned
521 // Also make sure that ESP is above SP.
522 // We don't care about checking ESP if it is null, i.e. it hasn't
523 // been used yet.
524 if (gr[31].value.u64 & 0x0f) {
525 asm volatile("nop");
526 return false;
527 }
528 return true;
529 }
530
531 // pc register accessors
532
533 // this instruction can be used to fetch the current PC
534 u_int64_t getPC();
535 // instead of setting the current PC directly you can
536 // first set the next PC (either absolute or PC-relative)
537 // and later copy the next PC into the current PC
538 // this supports a default increment by 4 at instruction
539 // fetch with an optional reset by control instructions
540 u_int64_t getNextPC();
541 void setNextPC(u_int64_t next);
542 void offsetNextPC(int64_t offset);
543 // install nextpc as current pc
544 void updatePC();
545
546 // this instruction can be used to save the next PC to LR
547 // just before installing a branch PC
548 inline void saveLR() { gr[LR].value.u64 = nextpc; }
549
550 // cpsr register accessors
551 u_int32_t getCPSRRegister();
552 void setCPSRRegister(u_int32_t flags);
553 // read a specific subset of the flags as a bit pattern
554 // mask should be composed using elements of enum FlagMask
555 u_int32_t getCPSRBits(u_int32_t mask);
556 // assign a specific subset of the flags as a bit pattern
557 // mask and value should be composed using elements of enum FlagMask
558 void setCPSRBits(u_int32_t mask, u_int32_t value);
559 // test the value of a single flag returned as 1 or 0
560 u_int32_t testCPSR(CPSRRegister::CPSRIdx idx);
561 // set a single flag
562 void setCPSR(CPSRRegister::CPSRIdx idx);
563 // clear a single flag
564 void clearCPSR(CPSRRegister::CPSRIdx idx);
565 // utility method to set ARM CSPR flags from an x86 bit mask generated by integer arithmetic
566 void setCPSRRegisterFromX86(u_int64_t x86Flags);
567 // utility method to set ARM CSPR flags from an x86 bit mask generated by floating compare
568 void setCPSRRegisterFromX86FP(u_int64_t x86Flags);
569
570 // fpsr register accessors
571 u_int32_t getFPSRRegister();
572 void setFPSRRegister(u_int32_t flags);
573 // read a specific subset of the fprs bits as a bit pattern
574 // mask should be composed using elements of enum FPSRRegister::FlagMask
575 u_int32_t getFPSRBits(u_int32_t mask);
576 // assign a specific subset of the flags as a bit pattern
577 // mask and value should be composed using elements of enum FPSRRegister::FlagMask
578 void setFPSRBits(u_int32_t mask, u_int32_t value);
579 // test the value of a single flag returned as 1 or 0
580 u_int32_t testFPSR(FPSRRegister::FPSRIdx idx);
581 // set a single flag
582 void setFPSR(FPSRRegister::FPSRIdx idx);
583 // clear a single flag
584 void clearFPSR(FPSRRegister::FPSRIdx idx);
585
586 // debugger support
587 void printPC(int pending, const char *trailing = "\n");
588 void printInstr(u_int32_t instr, void (*dasm)(u_int64_t), const char *trailing = "\n");
589 void printGReg(GReg reg, PrintFormat format = FMT_HEX, const char *trailing = "\n");
590 void printVReg(VReg reg, PrintFormat format = FMT_HEX, const char *trailing = "\n");
591 void printCPSR(const char *trailing = "\n");
592 void printFPSR(const char *trailing = "\n");
593 void dumpState();
594 };
595
596 #endif // ifndef _CPU_STATE_H