1 /* 2 * Copyright (c) 1999, 2015, Oracle and/or its affiliates. All rights reserved. 3 * Copyright (c) 2014, Red Hat Inc. All rights reserved. 4 * Copyright (c) 2015, Linaro Ltd. All rights reserved. 5 * Copyright (c) 2015-2018, Azul Systems, Inc. All rights reserved. 6 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 7 * 8 * This code is free software; you can redistribute it and/or modify it 9 * under the terms of the GNU General Public License version 2 only, as 10 * published by the Free Software Foundation. 11 * 12 * This code is distributed in the hope that it will be useful, but WITHOUT 13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 15 * version 2 for more details (a copy is included in the LICENSE file that 16 * accompanied this code). 17 * 18 * You should have received a copy of the GNU General Public License version 19 * 2 along with this work; if not, write to the Free Software Foundation, 20 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 21 * 22 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 23 * or visit www.oracle.com if you need additional information or have any 24 * questions. 25 * 26 */ 27 28 #ifndef CPU_AARCH32_VM_GLOBALDEFINITIONS_AARCH32_HPP 29 #define CPU_AARCH32_VM_GLOBALDEFINITIONS_AARCH32_HPP 30 31 // __ARM_PCS_VFP indicates that gcc runs with "-mfloat-abi=hard" option. 32 // This option allows generation of floating point instructions and enforces 33 // usage of FPU-specific calling conventions. 34 #ifdef __ARM_PCS_VFP 35 #define HARD_FLOAT_CC 36 #endif // __ARM_PCS_VFP 37 38 // If changing this please be sure to review all code which saves the registers 39 // and the corresponding register maps to ensure that the respective frame 40 // sizes are multiple of this new value 41 const int StackAlignmentInBytes = 8; 42 43 // Indicates whether the C calling conventions require that 44 // 32-bit integer argument values are properly extended to 64 bits. 45 const bool CCallingConventionRequiresIntsAsLongs = false; 46 47 #define SUPPORTS_NATIVE_CX8 48 49 // The maximum B/BL offset range on AArch32 is 32MB. 50 #undef CODE_CACHE_DEFAULT_LIMIT 51 #define CODE_CACHE_DEFAULT_LIMIT (32*M) 52 53 // According to the ARMv8 ARM, "Concurrent modification and execution 54 // of instructions can lead to the resulting instruction performing 55 // any behavior that can be achieved by executing any sequence of 56 // instructions that can be executed from the same Exception level, 57 // except where the instruction before modification and the 58 // instruction after modification is a B, BL, NOP, BKPT, SVC, HVC, or 59 // SMC instruction." 60 // 61 // This makes the games we play when patching difficult, so when we 62 // come across an access that needs patching we deoptimize. There are 63 // ways we can avoid this, but these would slow down C1-compiled code 64 // in the default case. We could revisit this decision if we get any 65 // evidence that it's worth doing. 66 #define DEOPTIMIZE_WHEN_PATCHING 67 68 #define SUPPORT_RESERVED_STACK_AREA 69 70 #define THREAD_LOCAL_POLL 71 72 #endif // CPU_AARCH32_VM_GLOBALDEFINITIONS_AARCH32_HPP