1 /*
2 * Copyright (c) 2000, 2010, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2014, Red Hat Inc. All rights reserved.
4 * Copyright (c) 2015, Linaro Ltd. All rights reserved.
5 * Copyright (c) 2015-2018, Azul Systems, Inc. All rights reserved.
6 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
7 *
8 * This code is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License version 2 only, as
10 * published by the Free Software Foundation.
11 *
12 * This code is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15 * version 2 for more details (a copy is included in the LICENSE file that
16 * accompanied this code).
17 *
18 * You should have received a copy of the GNU General Public License version
19 * 2 along with this work; if not, write to the Free Software Foundation,
20 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
21 *
22 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
23 * or visit www.oracle.com if you need additional information or have any
24 * questions.
25 *
26 */
27
28 #ifndef CPU_AARCH32_VM_REGISTER_AARCH32_HPP
29 #define CPU_AARCH32_VM_REGISTER_AARCH32_HPP
30
31 #include "asm/register.hpp"
32
33 class VMRegImpl;
34 typedef VMRegImpl* VMReg;
35
36 // Implementation of integer registers for AArch32 architecture
37
38 class RegisterImpl;
39 typedef RegisterImpl* Register;
40
41 inline Register as_Register(int encoding) {
42 return (Register)(intptr_t) encoding;
43 }
44
45 class RegisterImpl : public AbstractRegisterImpl {
46 public:
47 enum {
48 number_of_registers = 16
49 };
50
51 // Construction
52 inline friend Register as_Register(int encoding);
53
54 // Accessors
55 int encoding() const {
56 assert(is_valid(), "invalid register");
57 return (intptr_t) this;
58 }
59 int encoding_nocheck() const {
60 return (intptr_t) this;
61 }
62 VMReg as_VMReg();
63 Register successor() const {
64 return as_Register(encoding() + 1);
65 }
66
67 // Testers
68 bool is_valid() const {
69 return 0 <= (intptr_t) this && (intptr_t) this < number_of_registers;
70 }
71
72 // Return the bit which represents this register. This is intended to be
73 // used in bitmasks. See RegSet class below.
74 unsigned long bit(bool should_set = true) const {
75 return should_set ? 1 << encoding() : 0;
76 }
77
78 // Return the name of this register
79 const char* name() const;
80 };
81
82 // Integer registers of AArch32 architecture
83 #define R(r) ((Register)(r))
84
85 #define Rmh_SP_save r11 // for C2
86
87 CONSTANT_REGISTER_DECLARATION(Register, noreg, -1);
88
89 CONSTANT_REGISTER_DECLARATION(Register, r0, 0);
90 CONSTANT_REGISTER_DECLARATION(Register, r1, 1);
91 CONSTANT_REGISTER_DECLARATION(Register, r2, 2);
92 CONSTANT_REGISTER_DECLARATION(Register, r3, 3);
93 CONSTANT_REGISTER_DECLARATION(Register, r4, 4);
94 CONSTANT_REGISTER_DECLARATION(Register, r5, 5);
95 CONSTANT_REGISTER_DECLARATION(Register, r6, 6);
96 CONSTANT_REGISTER_DECLARATION(Register, r7, 7);
97 CONSTANT_REGISTER_DECLARATION(Register, r8, 8);
98 CONSTANT_REGISTER_DECLARATION(Register, r9, 9);
99 CONSTANT_REGISTER_DECLARATION(Register, r10, 10);
100 CONSTANT_REGISTER_DECLARATION(Register, r11, 11);
101 CONSTANT_REGISTER_DECLARATION(Register, r12, 12);
102 CONSTANT_REGISTER_DECLARATION(Register, r13, 13);
103 CONSTANT_REGISTER_DECLARATION(Register, r14, 14);
104 CONSTANT_REGISTER_DECLARATION(Register, r15, 15);
105
106 // Implementation of floating point registers for AArch32 (VFPv3-D16)
107 // architecture
108
109 class FloatRegisterImpl;
110 typedef FloatRegisterImpl* FloatRegister;
111
112 // Return FloatRegister corresponding to the given s-type (aka f-type in this
113 // port) register number
114 inline FloatRegister as_FloatRegister(int encoding) {
115 return (FloatRegister)(intptr_t) encoding;
116 }
117
118 // Return FloatRegister corresponding to the given d-type register number
119 inline FloatRegister as_DoubleFloatRegister(int encoding) {
120 return as_FloatRegister(2 * encoding);
121 }
122
123 class FloatRegisterImpl : public AbstractRegisterImpl {
124 public:
125 enum {
126 // VFPv3-D16 architecture includes 16 doubleword registers, which can be
127 // also observed as 32 singleword registers. We count the singleword
128 // registers here.
129 number_of_registers = 32
130 };
131
132 enum FloatRegisterSize {
133 SINGLE = 1,
134 DOUBLE = 2,
135 QUAD = 4
136 };
137
138 // Construction
139 inline friend FloatRegister as_FloatRegister(int encoding);
140 inline friend FloatRegister as_DoubleFloatRegister(int encoding);
141
142 // Accessors
143 int encoding() const {
144 assert(is_valid(), "invalid register");
145 return (intptr_t) this;
146 }
147 int encoding_nocheck() const {
148 return (intptr_t) this;
149 }
150 VMReg as_VMReg();
151 FloatRegister successor(enum FloatRegisterSize size) const {
152 return (as_FloatRegister((encoding() + (int)size) % number_of_registers |
153 (encoding() + (int)size) / number_of_registers));
154 }
155
156 // Testers
157 bool is_valid() const {
158 return 0 <= (intptr_t) this && (intptr_t) this < number_of_registers;
159 }
160
161 // Return the bit which represents this register. This is intended to be
162 // used in bitmasks. See FloatRegSet class below.
163 unsigned long bit(bool should_set = true) const {
164 return should_set ? 1 << encoding() : 0;
165 }
166
167 // Return the name of this register
168 const char* name() const;
169 };
170
171 // Floating point registers of AArch32 (VFPv3-D16, D32 and SIMD) architecture
172
173 // Only the first 8 doubleword registers can be used for parameter passing
174 // and thus are caller-saved. The rest 8 registers are callee-saved.
175 // In VFPv3-D32 there are additional 16 doubleword registers that are
176 // caller-saved again.
177
178 // Here we introduce the symbolic names for doubleword registers and the
179 // corresponding singleword views for the first 16 of them. The instruction
180 // set allows us to encode the doubleword register numbers directly using
181 // the constants below.
182
183 // The respective names are as well defined for quad-word registers with
184 // encoding set by the same principles.
185
186 CONSTANT_REGISTER_DECLARATION(FloatRegister, fnoreg, -1);
187
188 CONSTANT_REGISTER_DECLARATION(FloatRegister, d0, 0);
189 CONSTANT_REGISTER_DECLARATION(FloatRegister, d1, 2);
190 CONSTANT_REGISTER_DECLARATION(FloatRegister, d2, 4);
191 CONSTANT_REGISTER_DECLARATION(FloatRegister, d3, 6);
192 CONSTANT_REGISTER_DECLARATION(FloatRegister, d4, 8);
193 CONSTANT_REGISTER_DECLARATION(FloatRegister, d5, 10);
194 CONSTANT_REGISTER_DECLARATION(FloatRegister, d6, 12);
195 CONSTANT_REGISTER_DECLARATION(FloatRegister, d7, 14);
196 CONSTANT_REGISTER_DECLARATION(FloatRegister, d8, 16);
197 CONSTANT_REGISTER_DECLARATION(FloatRegister, d9, 18);
198 CONSTANT_REGISTER_DECLARATION(FloatRegister, d10, 20);
199 CONSTANT_REGISTER_DECLARATION(FloatRegister, d11, 22);
200 CONSTANT_REGISTER_DECLARATION(FloatRegister, d12, 24);
201 CONSTANT_REGISTER_DECLARATION(FloatRegister, d13, 26);
202 CONSTANT_REGISTER_DECLARATION(FloatRegister, d14, 28);
203 CONSTANT_REGISTER_DECLARATION(FloatRegister, d15, 30);
204 CONSTANT_REGISTER_DECLARATION(FloatRegister, d16, 1);
205 CONSTANT_REGISTER_DECLARATION(FloatRegister, d17, 3);
206 CONSTANT_REGISTER_DECLARATION(FloatRegister, d18, 5);
207 CONSTANT_REGISTER_DECLARATION(FloatRegister, d19, 7);
208 CONSTANT_REGISTER_DECLARATION(FloatRegister, d20, 9);
209 CONSTANT_REGISTER_DECLARATION(FloatRegister, d21, 11);
210 CONSTANT_REGISTER_DECLARATION(FloatRegister, d22, 13);
211 CONSTANT_REGISTER_DECLARATION(FloatRegister, d23, 15);
212 CONSTANT_REGISTER_DECLARATION(FloatRegister, d24, 17);
213 CONSTANT_REGISTER_DECLARATION(FloatRegister, d25, 19);
214 CONSTANT_REGISTER_DECLARATION(FloatRegister, d26, 21);
215 CONSTANT_REGISTER_DECLARATION(FloatRegister, d27, 23);
216 CONSTANT_REGISTER_DECLARATION(FloatRegister, d28, 25);
217 CONSTANT_REGISTER_DECLARATION(FloatRegister, d29, 27);
218 CONSTANT_REGISTER_DECLARATION(FloatRegister, d30, 29);
219 CONSTANT_REGISTER_DECLARATION(FloatRegister, d31, 31);
220
221 CONSTANT_REGISTER_DECLARATION(FloatRegister, q0, 0);
222 CONSTANT_REGISTER_DECLARATION(FloatRegister, q1, 4);
223 CONSTANT_REGISTER_DECLARATION(FloatRegister, q2, 8);
224 CONSTANT_REGISTER_DECLARATION(FloatRegister, q3, 12);
225 CONSTANT_REGISTER_DECLARATION(FloatRegister, q4, 16);
226 CONSTANT_REGISTER_DECLARATION(FloatRegister, q5, 20);
227 CONSTANT_REGISTER_DECLARATION(FloatRegister, q6, 24);
228 CONSTANT_REGISTER_DECLARATION(FloatRegister, q7, 28);
229 CONSTANT_REGISTER_DECLARATION(FloatRegister, q8, 1);
230 CONSTANT_REGISTER_DECLARATION(FloatRegister, q9, 5);
231 CONSTANT_REGISTER_DECLARATION(FloatRegister, q10, 9);
232 CONSTANT_REGISTER_DECLARATION(FloatRegister, q11, 13);
233 CONSTANT_REGISTER_DECLARATION(FloatRegister, q12, 17);
234 CONSTANT_REGISTER_DECLARATION(FloatRegister, q13, 21);
235 CONSTANT_REGISTER_DECLARATION(FloatRegister, q14, 25);
236 CONSTANT_REGISTER_DECLARATION(FloatRegister, q15, 29);
237
238 CONSTANT_REGISTER_DECLARATION(FloatRegister, f0, 0);
239 CONSTANT_REGISTER_DECLARATION(FloatRegister, f1, 1);
240 CONSTANT_REGISTER_DECLARATION(FloatRegister, f2, 2);
241 CONSTANT_REGISTER_DECLARATION(FloatRegister, f3, 3);
242 CONSTANT_REGISTER_DECLARATION(FloatRegister, f4, 4);
243 CONSTANT_REGISTER_DECLARATION(FloatRegister, f5, 5);
244 CONSTANT_REGISTER_DECLARATION(FloatRegister, f6, 6);
245 CONSTANT_REGISTER_DECLARATION(FloatRegister, f7, 7);
246 CONSTANT_REGISTER_DECLARATION(FloatRegister, f8, 8);
247 CONSTANT_REGISTER_DECLARATION(FloatRegister, f9, 9);
248 CONSTANT_REGISTER_DECLARATION(FloatRegister, f10, 10);
249 CONSTANT_REGISTER_DECLARATION(FloatRegister, f11, 11);
250 CONSTANT_REGISTER_DECLARATION(FloatRegister, f12, 12);
251 CONSTANT_REGISTER_DECLARATION(FloatRegister, f13, 13);
252 CONSTANT_REGISTER_DECLARATION(FloatRegister, f14, 14);
253 CONSTANT_REGISTER_DECLARATION(FloatRegister, f15, 15);
254 CONSTANT_REGISTER_DECLARATION(FloatRegister, f16, 16);
255 CONSTANT_REGISTER_DECLARATION(FloatRegister, f17, 17);
256 CONSTANT_REGISTER_DECLARATION(FloatRegister, f18, 18);
257 CONSTANT_REGISTER_DECLARATION(FloatRegister, f19, 19);
258 CONSTANT_REGISTER_DECLARATION(FloatRegister, f20, 20);
259 CONSTANT_REGISTER_DECLARATION(FloatRegister, f21, 21);
260 CONSTANT_REGISTER_DECLARATION(FloatRegister, f22, 22);
261 CONSTANT_REGISTER_DECLARATION(FloatRegister, f23, 23);
262 CONSTANT_REGISTER_DECLARATION(FloatRegister, f24, 24);
263 CONSTANT_REGISTER_DECLARATION(FloatRegister, f25, 25);
264 CONSTANT_REGISTER_DECLARATION(FloatRegister, f26, 26);
265 CONSTANT_REGISTER_DECLARATION(FloatRegister, f27, 27);
266 CONSTANT_REGISTER_DECLARATION(FloatRegister, f28, 28);
267 CONSTANT_REGISTER_DECLARATION(FloatRegister, f29, 29);
268 CONSTANT_REGISTER_DECLARATION(FloatRegister, f30, 30);
269 CONSTANT_REGISTER_DECLARATION(FloatRegister, f31, 31);
270
271 // Set of singleword floating point registers
272
273 class FloatRegSet {
274 private:
275 uint32_t _bitset;
276
277 FloatRegSet(uint32_t bitset) : _bitset(bitset) { }
278
279 public:
280 FloatRegSet() : _bitset(0) { }
281
282 FloatRegSet(FloatRegister r1) : _bitset(r1->bit()) { }
283
284 FloatRegSet operator+(const FloatRegSet aSet) const {
285 FloatRegSet result(_bitset | aSet._bitset);
286 return result;
287 }
288
289 FloatRegSet operator-(const FloatRegSet aSet) const {
290 FloatRegSet result(_bitset & ~aSet._bitset);
291 return result;
292 }
293
294 FloatRegSet& operator+=(const FloatRegSet aSet) {
295 *this = *this + aSet;
296 return *this;
297 }
298
299 static FloatRegSet of(FloatRegister r1) {
300 return FloatRegSet(r1);
301 }
302
303 static FloatRegSet of(FloatRegister r1, FloatRegister r2) {
304 return of(r1) + r2;
305 }
306
307 static FloatRegSet of(FloatRegister r1, FloatRegister r2, FloatRegister r3) {
308 return of(r1, r2) + r3;
309 }
310
311 static FloatRegSet of(FloatRegister r1, FloatRegister r2, FloatRegister r3,
312 FloatRegister r4) {
313 return of(r1, r2, r3) + r4;
314 }
315
316 static FloatRegSet range(FloatRegister start, FloatRegister end) {
317 uint32_t bits = ~0;
318 bits <<= start->encoding();
319 bits <<= 31 - end->encoding();
320 bits >>= 31 - end->encoding();
321 return FloatRegSet(bits);
322 }
323
324 uint32_t bits() const {
325 return _bitset;
326 }
327 };
328
329 // Set of doubleword floating point registers
330
331 class DoubleFloatRegSet {
332 private:
333 uint32_t _bitset;
334
335 DoubleFloatRegSet(uint32_t bitset) : _bitset(bitset) { }
336
337 public:
338 DoubleFloatRegSet() : _bitset(0) { }
339
340 DoubleFloatRegSet(FloatRegister r1) : _bitset(1 << (r1->encoding()>>1)+((r1->encoding()%2)?16:0)) { }
341
342 DoubleFloatRegSet operator+(const DoubleFloatRegSet aSet) const {
343 DoubleFloatRegSet result(_bitset | aSet._bitset);
344 return result;
345 }
346
347 DoubleFloatRegSet operator-(const DoubleFloatRegSet aSet) const {
348 DoubleFloatRegSet result(_bitset & ~aSet._bitset);
349 return result;
350 }
351
352 DoubleFloatRegSet& operator+=(const DoubleFloatRegSet aSet) {
353 *this = *this + aSet;
354 return *this;
355 }
356
357 static DoubleFloatRegSet of(FloatRegister r1) {
358 return DoubleFloatRegSet(r1);
359 }
360
361 static DoubleFloatRegSet of(FloatRegister r1, FloatRegister r2) {
362 return of(r1) + r2;
363 }
364
365 static DoubleFloatRegSet of(FloatRegister r1, FloatRegister r2,
366 FloatRegister r3) {
367 return of(r1, r2) + r3;
368 }
369
370 static DoubleFloatRegSet of(FloatRegister r1, FloatRegister r2,
371 FloatRegister r3, FloatRegister r4) {
372 return of(r1, r2, r3) + r4;
373 }
374
375 static DoubleFloatRegSet range(FloatRegister start, FloatRegister end) {
376 int start_reg = (start->encoding() >> 1)+((start->encoding()%2)?16:0);
377 int end_reg = (end->encoding() >> 1)+((end->encoding()%2)?16:0);
378 uint32_t bits = ~0;
379 bits <<= start_reg;
380 bits <<= 31 - end_reg;
381 bits >>= 31 - end_reg;
382 return DoubleFloatRegSet(bits);
383 }
384
385 uint32_t bits() const {
386 return _bitset;
387 }
388 };
389
390 // Total number of registers of all sorts
391
392 class ConcreteRegisterImpl : public AbstractRegisterImpl {
393 public:
394 enum {
395 // Here we count the total number of 32-bit slots available in registers.
396 // This number must be large enough to cover REG_COUNT (defined by C2)
397 // registers. There is no requirement that any ordering here matches
398 // any ordering C2 gives its OptoReg's.
399 // C2 port is made to be able to operate on all 32 double registers of VFPD32
400 // but the register count is 32 since high half of 32-bit regs are not addressable
401 // so need to double the amount of known registers to get expected 64
402 #ifndef COMPILER2
403 number_of_registers = RegisterImpl::number_of_registers +
404 FloatRegisterImpl::number_of_registers
405 #else
406 number_of_registers = RegisterImpl::number_of_registers +
407 (FloatRegisterImpl::number_of_registers*2) +
408 2
409 #endif
410 };
411
412 static const int max_gpr;
413 static const int max_fpr;
414 };
415
416
417 // Set of integer registers
418
419 class RegSet {
420 private:
421 uint32_t _bitset;
422
423 RegSet(uint32_t bitset) : _bitset(bitset) { }
424
425 public:
426 RegSet() : _bitset(0) { }
427
428 RegSet(Register r1) : _bitset(r1->bit()) { }
429
430 RegSet operator+(const RegSet aSet) const {
431 RegSet result(_bitset | aSet._bitset);
432 return result;
433 }
434
435 RegSet operator-(const RegSet aSet) const {
436 RegSet result(_bitset & ~aSet._bitset);
437 return result;
438 }
439
440 RegSet& operator+=(const RegSet aSet) {
441 *this = *this + aSet;
442 return *this;
443 }
444
445 static RegSet of(Register r1) {
446 return RegSet(r1);
447 }
448
449 static RegSet of(Register r1, Register r2) {
450 return of(r1) + r2;
451 }
452
453 static RegSet of(Register r1, Register r2, Register r3) {
454 return of(r1, r2) + r3;
455 }
456
457 static RegSet of(Register r1, Register r2, Register r3, Register r4) {
458 return of(r1, r2, r3) + r4;
459 }
460
461 static RegSet of(Register r1, Register r2, Register r3, Register r4, Register r5) {
462 return of(r1, r2, r3, r4) + r5;
463 }
464
465 static RegSet of(Register r1, Register r2, Register r3, Register r4, Register r5, Register r6) {
466 return of(r1, r2, r3, r4, r5) + r6;
467 }
468
469 static RegSet range(Register start, Register end) {
470 uint32_t bits = ~0;
471 bits <<= start->encoding();
472 bits <<= 31 - end->encoding();
473 bits >>= 31 - end->encoding();
474 return RegSet(bits);
475 }
476
477 uint32_t bits() const {
478 return _bitset;
479 }
480 };
481
482
483 #endif // CPU_AARCH32_VM_REGISTER_AARCH32_HPP